1 /* Copyright 2013-2015 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17
18
19 #include <skiboot.h>
20 #include <xscom.h>
21 #include <io.h>
22 #include <cpu.h>
23 #include <nx.h>
24 #include <chip.h>
25 #include <phys-map.h>
26 #include <xscom-p9-regs.h>
27
28 /*
29 * On P9 the DARN instruction is used to access the HW RNG. There is still
30 * an NX RNG BAR, but it is used to configure which NX a core will source
31 * random numbers from rather than being a MMIO window.
32 */
nx_init_p9_rng(uint32_t chip_id)33 static void nx_init_p9_rng(uint32_t chip_id)
34 {
35 uint64_t bar, tmp;
36
37 if (chip_quirk(QUIRK_NO_RNG))
38 return;
39
40 phys_map_get(chip_id, NX_RNG, 0, &bar, NULL);
41 xscom_write(chip_id, P9X_NX_MMIO_BAR, bar | P9X_NX_MMIO_BAR_EN);
42
43 /* Read config register for pace info */
44 xscom_read(chip_id, P9X_NX_RNG_CFG, &tmp);
45 prlog(PR_INFO, "NX RNG[%x] pace:%lli\n", chip_id, 0xffff & (tmp >> 2));
46 }
47
nx_create_rng_node(struct dt_node * node)48 void nx_create_rng_node(struct dt_node *node)
49 {
50 u64 bar, cfg;
51 u64 xbar, xcfg;
52 u32 pb_base;
53 u32 gcid;
54 u64 rng_addr, rng_len, len, addr_mask;
55 struct dt_node *rng;
56 int rc;
57
58 gcid = dt_get_chip_id(node);
59 pb_base = dt_get_address(node, 0, NULL);
60
61 if (dt_node_is_compatible(node, "ibm,power8-nx")) {
62 xbar = pb_base + NX_P8_RNG_BAR;
63 xcfg = pb_base + NX_P8_RNG_CFG;
64 addr_mask = NX_P8_RNG_BAR_ADDR;
65 } else if (dt_node_is_compatible(node, "ibm,power9-nx")) {
66 nx_init_p9_rng(gcid);
67 return;
68 } else {
69 prerror("NX%d: Unknown NX type!\n", gcid);
70 return;
71 }
72
73 rc = xscom_read(gcid, xbar, &bar); /* Get RNG BAR */
74 if (rc) {
75 prerror("NX%d: ERROR: XSCOM RNG BAR read failure %d\n",
76 gcid, rc);
77 return;
78 }
79
80 rc = xscom_read(gcid, xcfg, &cfg); /* Get RNG CFG */
81 if (rc) {
82 prerror("NX%d: ERROR: XSCOM RNG config read failure %d\n",
83 gcid, rc);
84 return;
85 }
86
87 /*
88 * We mask in-place rather than using GETFIELD for the base address
89 * as we happen to *know* that it's properly aligned in the register.
90 *
91 * FIXME? Always assusme BAR gets a valid address from FSP
92 */
93 rng_addr = bar & addr_mask;
94 len = GETFIELD(NX_RNG_BAR_SIZE, bar);
95 if (len > 4) {
96 prerror("NX%d: Corrupted bar size %lld\n", gcid, len);
97 return;
98 }
99 rng_len = (u64[]){ 0x1000, /* 4K */
100 0x10000, /* 64K */
101 0x400000000UL, /* 16G*/
102 0x100000, /* 1M */
103 0x1000000 /* 16M */} [len];
104
105
106 prlog(PR_INFO, "NX%d: RNG BAR set to 0x%016llx..0x%016llx\n",
107 gcid, rng_addr, rng_addr + rng_len - 1);
108
109 /* RNG must be enabled before MMIO is enabled */
110 rc = xscom_write(gcid, xcfg, cfg | NX_RNG_CFG_ENABLE);
111 if (rc) {
112 prerror("NX%d: ERROR: XSCOM RNG config enable failure %d\n",
113 gcid, rc);
114 return;
115 }
116
117 /* The BAR needs to be enabled too */
118 rc = xscom_write(gcid, xbar, bar | NX_RNG_BAR_ENABLE);
119 if (rc) {
120 prerror("NX%d: ERROR: XSCOM RNG config enable failure %d\n",
121 gcid, rc);
122 return;
123 }
124
125 rng = dt_new_addr(dt_root, "hwrng", rng_addr);
126 if (!rng)
127 return;
128
129 dt_add_property_strings(rng, "compatible", "ibm,power-rng");
130 dt_add_property_u64s(rng, "reg", rng_addr, rng_len);
131 dt_add_property_cells(rng, "ibm,chip-id", gcid);
132 }
133