1 /* Copyright 2017-2019 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 /*
18 * P9 OPAL - SBE communication driver
19 *
20 * P9 chip has Self Boot Engine (SBE). OPAL uses SBE for various purpose like
21 * timer, scom, MPIPL, etc,. Every chip has SBE. OPAL can communicate to SBE
22 * on all chips. Based on message type it selects appropriate SBE (ex: schedule
23 * timer on any chip).
24 *
25 * OPAL communicates to SBE via a set of data and control registers provided by
26 * the PSU block in P9 chip.
27 * - Four 8 byte registers for Host to send command packets to SBE.
28 * - Four 8 byte registers for SBE to send response packets to Host.
29 * - Two doorbell registers (1 on each side) to alert either party
30 * when data is placed in above mentioned data registers. Once Host/SBE reads
31 * incoming data, it should clear doorbell register. Interrupt is disabled
32 * as soon as doorbell register is cleared.
33 *
34 * OPAL - SBE message format:
35 * - OPAL communicates to SBE via set of well defined commands.
36 * - Reg0 contains message header (command class, subclass, flags etc).
37 * - Reg1-3 contains actual data. If data is big then it uses indirect method
38 * (data is passed via memory and memory address/size is passed in Reg1-3).
39 * - Every message has defined timeout. SBE must respond within specified
40 * time. Otherwise OPAL discards message and sends error message to caller.
41 *
42 * Constraints:
43 * - Only one command is accepted in the command buffer until the response for
44 * the command is enqueued in the response buffer by SBE.
45 */
46
47 #define pr_fmt(fmt) "SBE: " fmt
48
49 #include <chip.h>
50 #include <errorlog.h>
51 #include <lock.h>
52 #include <opal.h>
53 #include <sbe-p9.h>
54 #include <skiboot.h>
55 #include <timebase.h>
56 #include <timer.h>
57 #include <trace.h>
58 #include <xscom.h>
59
60 enum p9_sbe_mbox_state {
61 sbe_mbox_idle = 0, /* Ready to send message */
62 sbe_mbox_send, /* Message sent, waiting for ack/response */
63 sbe_mbox_rr, /* SBE in R/R */
64 };
65
66 struct p9_sbe {
67 /* Chip ID to send message */
68 u32 chip_id;
69
70 /* List to hold SBE queue messages */
71 struct list_head msg_list;
72
73 struct lock lock;
74
75 enum p9_sbe_mbox_state state;
76
77 /* SBE MBOX message sequence number */
78 u16 cur_seq;
79 };
80
81 /* Default SBE chip ID */
82 static int sbe_default_chip_id = -1;
83
84 /* Is SBE timer running? */
85 static bool sbe_has_timer = false;
86 static bool sbe_timer_in_progress = false;
87 static bool has_new_target = false;
88
89 /* Inflight and next timer in TB */
90 static uint64_t sbe_last_gen_stamp;
91 static uint64_t sbe_timer_target;
92
93 /* Timer lock */
94 static struct lock sbe_timer_lock;
95
96 /*
97 * Minimum timeout value for P9 is 500 microseconds. After that
98 * SBE timer can handle granularity of 1 microsecond.
99 */
100 #define SBE_TIMER_DEFAULT_US 500
101 static uint64_t sbe_timer_def_tb;
102
103 /* Timer control message */
104 static struct p9_sbe_msg *timer_ctrl_msg;
105
106 #define SBE_STATUS_PRI_SHIFT 0x30
107 #define SBE_STATUS_SEC_SHIFT 0x20
108
109 /* Forward declaration */
110 static void p9_sbe_timeout_poll_one(struct p9_sbe *sbe);
111 static void p9_sbe_timer_schedule(void);
112
113 /* bit 0-15 : Primary status code */
p9_sbe_get_primary_rc(struct p9_sbe_msg * resp)114 static inline u16 p9_sbe_get_primary_rc(struct p9_sbe_msg *resp)
115 {
116 return (resp->reg[0] >> SBE_STATUS_PRI_SHIFT);
117 }
118
p9_sbe_set_primary_rc(struct p9_sbe_msg * resp,u64 rc)119 static inline void p9_sbe_set_primary_rc(struct p9_sbe_msg *resp, u64 rc)
120 {
121 resp->reg[0] |= (rc << SBE_STATUS_PRI_SHIFT);
122 }
123
p9_sbe_rreg(u32 chip_id,u64 reg)124 static u64 p9_sbe_rreg(u32 chip_id, u64 reg)
125 {
126 u64 data = 0;
127 int rc;
128
129 rc = xscom_read(chip_id, reg, &data);
130 if (rc != OPAL_SUCCESS) {
131 prlog(PR_DEBUG, "XSCOM error %d reading reg 0x%llx\n", rc, reg);
132 return 0xffffffff;
133 }
134
135 return be64_to_cpu(data);
136 }
137
p9_sbe_reg_dump(u32 chip_id)138 static void p9_sbe_reg_dump(u32 chip_id)
139 {
140 #define SBE_DUMP_REG_ONE(chip_id, x) \
141 prlog(PR_DEBUG, " %20s: %016llx\n", #x, p9_sbe_rreg(chip_id, x))
142
143 prlog(PR_DEBUG, "MBOX register dump for chip : %x\n", chip_id);
144 SBE_DUMP_REG_ONE(chip_id, PSU_SBE_DOORBELL_REG_RW);
145 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_SBE_MBOX_REG0);
146 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_SBE_MBOX_REG1);
147 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_SBE_MBOX_REG2);
148 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_SBE_MBOX_REG3);
149 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_DOORBELL_REG_RW);
150 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_SBE_MBOX_REG4);
151 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_SBE_MBOX_REG5);
152 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_SBE_MBOX_REG6);
153 SBE_DUMP_REG_ONE(chip_id, PSU_HOST_SBE_MBOX_REG7);
154 }
155
p9_sbe_freemsg(struct p9_sbe_msg * msg)156 void p9_sbe_freemsg(struct p9_sbe_msg *msg)
157 {
158 if (msg && msg->resp)
159 free(msg->resp);
160 free(msg);
161 }
162
p9_sbe_fillmsg(struct p9_sbe_msg * msg,u16 cmd,u16 ctrl_flag,u64 reg1,u64 reg2,u64 reg3)163 static void p9_sbe_fillmsg(struct p9_sbe_msg *msg, u16 cmd,
164 u16 ctrl_flag, u64 reg1, u64 reg2, u64 reg3)
165 {
166 bool response = !!(ctrl_flag & SBE_CMD_CTRL_RESP_REQ);
167 u16 flag;
168
169 /*
170 * Always set ack required flag. SBE will interrupt OPAL once it read
171 * message from mailbox register. If OPAL is expecting response, then
172 * it will update message timeout, otherwise it will send next message.
173 */
174 flag = ctrl_flag | SBE_CMD_CTRL_ACK_REQ;
175
176 /* Seqence ID is filled by p9_sbe_queue_msg() */
177 msg->reg[0] = ((u64)flag << 32) | cmd;
178 msg->reg[1] = reg1;
179 msg->reg[2] = reg2;
180 msg->reg[3] = reg3;
181 msg->state = sbe_msg_unused;
182 msg->response = response;
183 }
184
p9_sbe_allocmsg(bool alloc_resp)185 static struct p9_sbe_msg *p9_sbe_allocmsg(bool alloc_resp)
186 {
187 struct p9_sbe_msg *msg;
188
189 msg = zalloc(sizeof(struct p9_sbe_msg));
190 if (!msg) {
191 prlog(PR_ERR, "Failed to allocate SBE message\n");
192 return NULL;
193 }
194 if (alloc_resp) {
195 msg->resp = zalloc(sizeof(struct p9_sbe_msg));
196 if (!msg->resp) {
197 prlog(PR_ERR, "Failed to allocate SBE resp message\n");
198 free(msg);
199 return NULL;
200 }
201 }
202
203 return msg;
204 }
205
206 /*
207 * Handles "command with direct data" format only.
208 *
209 * Note: All mbox messages of our interest uses direct data format. If we need
210 * indirect data format then we may have to enhance this function.
211 */
p9_sbe_mkmsg(u16 cmd,u16 ctrl_flag,u64 reg1,u64 reg2,u64 reg3)212 struct p9_sbe_msg *p9_sbe_mkmsg(u16 cmd, u16 ctrl_flag,
213 u64 reg1, u64 reg2, u64 reg3)
214 {
215 struct p9_sbe_msg *msg;
216
217 msg = p9_sbe_allocmsg(!!(ctrl_flag & SBE_CMD_CTRL_RESP_REQ));
218 if (!msg)
219 return NULL;
220
221 p9_sbe_fillmsg(msg, cmd, ctrl_flag, reg1, reg2, reg3);
222 return msg;
223 }
224
p9_sbe_mbox_busy(struct p9_sbe * sbe)225 static inline bool p9_sbe_mbox_busy(struct p9_sbe *sbe)
226 {
227 return (sbe->state != sbe_mbox_idle);
228 }
229
p9_sbe_msg_busy(struct p9_sbe_msg * msg)230 static inline bool p9_sbe_msg_busy(struct p9_sbe_msg *msg)
231 {
232 switch (msg->state) {
233 case sbe_msg_queued:
234 /* fall through */
235 case sbe_msg_sent:
236 case sbe_msg_wresp:
237 return true;
238 default: /* + sbe_msg_unused, sbe_msg_done,
239 sbe_msg_timeout, sbe_msg_error */
240 break;
241 }
242 return false;
243 }
244
p9_sbe_get_sbe(u32 chip_id)245 static inline struct p9_sbe *p9_sbe_get_sbe(u32 chip_id)
246 {
247 struct proc_chip *chip;
248
249 /* Default to SBE on master chip */
250 if (chip_id == -1) {
251 if (sbe_default_chip_id == -1)
252 return NULL;
253
254 chip = get_chip(sbe_default_chip_id);
255 } else {
256 chip = get_chip(chip_id);
257 }
258 if (chip == NULL || chip->sbe == NULL)
259 return NULL;
260
261 return chip->sbe;
262 }
263
p9_sbe_msg_send(struct p9_sbe * sbe,struct p9_sbe_msg * msg)264 static int p9_sbe_msg_send(struct p9_sbe *sbe, struct p9_sbe_msg *msg)
265 {
266 int rc, i;
267 u64 addr, *data;
268
269 addr = PSU_HOST_SBE_MBOX_REG0;
270 data = &msg->reg[0];
271
272 for (i = 0; i < NR_HOST_SBE_MBOX_REG; i++) {
273 rc = xscom_write(sbe->chip_id, addr, *data);
274 if (rc)
275 return rc;
276
277 addr++;
278 data++;
279 }
280
281 rc = xscom_write(sbe->chip_id, PSU_SBE_DOORBELL_REG_OR,
282 HOST_SBE_MSG_WAITING);
283 if (rc != OPAL_SUCCESS)
284 return rc;
285
286 prlog(PR_TRACE, "Message queued [chip id = 0x%x]:\n\t Reg0 : %016llx"
287 "\n\t Reg1 : %016llx\n\t Reg2 : %016llx\n\t Reg3 : %016llx\n",
288 sbe->chip_id, msg->reg[0], msg->reg[1], msg->reg[2], msg->reg[3]);
289
290 msg->timeout = mftb() + msecs_to_tb(SBE_CMD_TIMEOUT_MAX);
291 sbe->state = sbe_mbox_send;
292 msg->state = sbe_msg_sent;
293 return rc;
294 }
295
p9_sbe_msg_receive(u32 chip_id,struct p9_sbe_msg * resp)296 static int p9_sbe_msg_receive(u32 chip_id, struct p9_sbe_msg *resp)
297 {
298 int i;
299 int rc = OPAL_SUCCESS;
300 u64 addr, *data;
301
302 addr = PSU_HOST_SBE_MBOX_REG4;
303 data = &resp->reg[0];
304
305 for (i = 0; i < NR_HOST_SBE_MBOX_REG; i++) {
306 rc = xscom_read(chip_id, addr, data);
307 if (rc)
308 return rc;
309
310 addr++;
311 data++;
312 }
313 return rc;
314 }
315
316 /* WARNING: This will drop sbe->lock */
p9_sbe_msg_complete(struct p9_sbe * sbe,struct p9_sbe_msg * msg,enum p9_sbe_msg_state msg_state)317 static void p9_sbe_msg_complete(struct p9_sbe *sbe, struct p9_sbe_msg *msg,
318 enum p9_sbe_msg_state msg_state)
319 {
320 void (*comp)(struct p9_sbe_msg *msg);
321
322 prlog(PR_TRACE, "Completing msg [chip id = %x], reg0 : 0x%llx\n",
323 sbe->chip_id, msg->reg[0]);
324
325 comp = msg->complete;
326 list_del(&msg->link);
327 sync();
328 msg->state = msg_state;
329
330 if (comp) {
331 unlock(&sbe->lock);
332 comp(msg);
333 lock(&sbe->lock);
334 }
335 }
336
337 /* WARNING: This will drop sbe->lock */
p9_sbe_send_complete(struct p9_sbe * sbe)338 static void p9_sbe_send_complete(struct p9_sbe *sbe)
339 {
340 struct p9_sbe_msg *msg;
341
342 if (list_empty(&sbe->msg_list))
343 return;
344
345 msg = list_top(&sbe->msg_list, struct p9_sbe_msg, link);
346 /* Need response */
347 if (msg->response) {
348 msg->state = sbe_msg_wresp;
349 } else {
350 sbe->state = sbe_mbox_idle;
351 p9_sbe_msg_complete(sbe, msg, sbe_msg_done);
352 }
353 }
354
355 /* WARNING: This will drop sbe->lock */
p9_sbe_process_queue(struct p9_sbe * sbe)356 static void p9_sbe_process_queue(struct p9_sbe *sbe)
357 {
358 int rc, retry_cnt = 0;
359 struct p9_sbe_msg *msg = NULL;
360
361 if (p9_sbe_mbox_busy(sbe))
362 return;
363
364 while (!list_empty(&sbe->msg_list)) {
365 msg = list_top(&sbe->msg_list, struct p9_sbe_msg, link);
366 /* Send message */
367 rc = p9_sbe_msg_send(sbe, msg);
368 if (rc == OPAL_SUCCESS)
369 return;
370
371 prlog(PR_ERR, "Failed to send message to SBE [chip id = %x]\n",
372 sbe->chip_id);
373 if (msg->resp) {
374 p9_sbe_set_primary_rc(msg->resp,
375 SBE_STATUS_PRI_GENERIC_ERR);
376 }
377 p9_sbe_msg_complete(sbe, msg, sbe_msg_error);
378
379 /*
380 * Repeatedly failed to send message to SBE. Lets stop
381 * sending message.
382 */
383 if (retry_cnt++ >= 3) {
384 prlog(PR_ERR, "Temporarily stopped sending "
385 "message to SBE\n");
386 return;
387 }
388 }
389 }
390
391 /*
392 * WARNING:
393 * Only one command is accepted in the command buffer until response
394 * to the command is enqueued in the response buffer by SBE.
395 *
396 * Head of msg_list contains in-flight message. Hence we should always
397 * add new message to tail of the list.
398 */
p9_sbe_queue_msg(u32 chip_id,struct p9_sbe_msg * msg,void (* comp)(struct p9_sbe_msg * msg))399 int p9_sbe_queue_msg(u32 chip_id, struct p9_sbe_msg *msg,
400 void (*comp)(struct p9_sbe_msg *msg))
401 {
402 struct p9_sbe *sbe;
403
404 if (!msg)
405 return OPAL_PARAMETER;
406
407 sbe = p9_sbe_get_sbe(chip_id);
408 if (!sbe)
409 return OPAL_HARDWARE;
410
411 lock(&sbe->lock);
412 /* Set completion and update sequence number */
413 msg->complete = comp;
414 msg->state = sbe_msg_queued;
415 msg->reg[0] = msg->reg[0] | ((u64)sbe->cur_seq << 16);
416 sbe->cur_seq++;
417
418 /* Reset sequence number */
419 if (sbe->cur_seq == 0xffff)
420 sbe->cur_seq = 1;
421
422 /* Add message to queue */
423 list_add_tail(&sbe->msg_list, &msg->link);
424 p9_sbe_process_queue(sbe);
425 unlock(&sbe->lock);
426
427 return OPAL_SUCCESS;
428 }
429
p9_sbe_sync_msg(u32 chip_id,struct p9_sbe_msg * msg,bool autofree)430 int p9_sbe_sync_msg(u32 chip_id, struct p9_sbe_msg *msg, bool autofree)
431 {
432 int rc;
433 struct p9_sbe *sbe;
434
435 rc = p9_sbe_queue_msg(chip_id, msg, NULL);
436 if (rc)
437 goto free_msg;
438
439 sbe = p9_sbe_get_sbe(chip_id);
440 if (!sbe) {
441 rc = OPAL_HARDWARE;
442 goto free_msg;
443 }
444
445 while (p9_sbe_msg_busy(msg)) {
446 cpu_relax();
447 p9_sbe_timeout_poll_one(sbe);
448 }
449
450 if (msg->state == sbe_msg_done)
451 rc = SBE_STATUS_PRI_SUCCESS;
452 else
453 rc = SBE_STATUS_PRI_GENERIC_ERR;
454
455 if (msg->response && msg->resp)
456 rc = p9_sbe_get_primary_rc(msg->resp);
457
458 free_msg:
459 if (autofree)
460 p9_sbe_freemsg(msg);
461
462 return rc;
463 }
464
465 /* Remove SBE message from queue. It will not remove inflight message */
p9_sbe_cancelmsg(u32 chip_id,struct p9_sbe_msg * msg)466 int p9_sbe_cancelmsg(u32 chip_id, struct p9_sbe_msg *msg)
467 {
468 struct p9_sbe *sbe;
469
470 sbe = p9_sbe_get_sbe(chip_id);
471 if (!sbe)
472 return OPAL_PARAMETER;
473
474 lock(&sbe->lock);
475 if (msg->state != sbe_msg_queued) {
476 unlock(&sbe->lock);
477 return OPAL_BUSY;
478 }
479
480 list_del(&msg->link);
481 msg->state = sbe_msg_done;
482 unlock(&sbe->lock);
483 return OPAL_SUCCESS;
484 }
485
p9_sbe_handle_response(u32 chip_id,struct p9_sbe_msg * msg)486 static void p9_sbe_handle_response(u32 chip_id, struct p9_sbe_msg *msg)
487 {
488 u16 send_seq, resp_seq;
489 int rc;
490
491 if (msg == NULL || msg->resp == NULL)
492 return;
493
494 memset(msg->resp, 0, sizeof(struct p9_sbe_msg));
495
496 rc = p9_sbe_msg_receive(chip_id, msg->resp);
497 if (rc != OPAL_SUCCESS) {
498 prlog(PR_ERR, "Failed to read response message "
499 "[chip id = %x]\n", chip_id);
500 p9_sbe_set_primary_rc(msg->resp, SBE_STATUS_PRI_GENERIC_ERR);
501 return;
502 }
503
504 /* Validate sequence number */
505 send_seq = (msg->reg[0] >> 16) & 0xffff;
506 resp_seq = (msg->resp->reg[0] >> 16) & 0xffff;
507 if (send_seq != resp_seq) {
508 /*
509 * XXX Handle SBE R/R.
510 * Lets send sequence error to caller until SBE reset works.
511 */
512 prlog(PR_ERR, "Invalid sequence id [chip id = %x]\n", chip_id);
513 p9_sbe_set_primary_rc(msg->resp, SBE_STATUS_PRI_SEQ_ERR);
514 return;
515 }
516 }
517
p9_sbe_clear_interrupt(struct p9_sbe * sbe,u64 bits)518 static int p9_sbe_clear_interrupt(struct p9_sbe *sbe, u64 bits)
519 {
520 int rc;
521 u64 val;
522
523 /* Clear doorbell register */
524 val = SBE_HOST_RESPONSE_MASK & ~bits;
525 rc = xscom_write(sbe->chip_id, PSU_HOST_DOORBELL_REG_AND, val);
526 if (rc) {
527 prlog(PR_ERR, "Failed to clear SBE to Host doorbell "
528 "interrupt [chip id = %x]\n", sbe->chip_id);
529 }
530 return rc;
531 }
532
533 /* WARNING: This will drop sbe->lock */
p9_sbe_timer_response(struct p9_sbe * sbe)534 static void p9_sbe_timer_response(struct p9_sbe *sbe)
535 {
536 if (sbe->chip_id != sbe_default_chip_id)
537 return;
538
539 sbe_timer_in_progress = false;
540 /* Drop lock and call timers */
541 unlock(&sbe->lock);
542 check_timers(true);
543 lock(&sbe->lock);
544 }
545
546 /* WARNING: This will drop sbe->lock */
__p9_sbe_interrupt(struct p9_sbe * sbe)547 static void __p9_sbe_interrupt(struct p9_sbe *sbe)
548 {
549 bool has_response;
550 int rc;
551 u64 data = 0, val;
552 struct p9_sbe_msg *msg = NULL;
553
554 again:
555 /* Read doorbell register */
556 rc = xscom_read(sbe->chip_id, PSU_HOST_DOORBELL_REG_RW, &data);
557 if (rc) {
558 prlog(PR_ERR, "Failed to read SBE to Host doorbell register "
559 "[chip id = %x]\n", sbe->chip_id);
560 p9_sbe_reg_dump(sbe->chip_id);
561 return;
562 }
563
564 /* Completed processing all the bits */
565 if (!data)
566 return;
567
568 /* SBE came back from reset */
569 if (data & SBE_HOST_RESET) {
570 /* Clear all bits and restart sending message */
571 rc = p9_sbe_clear_interrupt(sbe, data);
572 if (rc)
573 return;
574
575 prlog(PR_NOTICE,
576 "Back from reset [chip id = %x]\n", sbe->chip_id);
577 /* Reset SBE MBOX state */
578 sbe->state = sbe_mbox_idle;
579
580 /* Reset message state */
581 if (!list_empty(&sbe->msg_list)) {
582 msg = list_top(&sbe->msg_list, struct p9_sbe_msg, link);
583 msg->state = sbe_msg_queued;
584 }
585 return;
586 }
587
588 /* Process ACK message before response */
589 if (data & SBE_HOST_MSG_READ) {
590 rc = p9_sbe_clear_interrupt(sbe, SBE_HOST_MSG_READ);
591 if (rc)
592 return;
593 p9_sbe_send_complete(sbe);
594 goto again;
595 }
596
597 /* Read SBE response before clearing doorbell register */
598 if (data & SBE_HOST_RESPONSE_WAITING) {
599 if (!list_empty(&sbe->msg_list)) {
600 msg = list_top(&sbe->msg_list, struct p9_sbe_msg, link);
601 p9_sbe_handle_response(sbe->chip_id, msg);
602 has_response = true;
603 } else {
604 has_response = false;
605 prlog(PR_DEBUG,
606 "Got response with no pending message\n");
607 }
608
609 rc = p9_sbe_clear_interrupt(sbe, SBE_HOST_RESPONSE_WAITING);
610 if (rc)
611 return;
612
613 /* Reset SBE MBOX state */
614 sbe->state = sbe_mbox_idle;
615 if (has_response)
616 p9_sbe_msg_complete(sbe, msg, sbe_msg_done);
617
618 goto again;
619 }
620
621 /* SBE passthrough command, call prd handler */
622 if (data & SBE_HOST_PASSTHROUGH) {
623 rc = p9_sbe_clear_interrupt(sbe, SBE_HOST_PASSTHROUGH);
624 if (rc)
625 return;
626 prd_sbe_passthrough(sbe->chip_id);
627 goto again;
628 }
629
630 /* Timer expired */
631 if (data & SBE_HOST_TIMER_EXPIRY) {
632 rc = p9_sbe_clear_interrupt(sbe, SBE_HOST_TIMER_EXPIRY);
633 if (rc)
634 return;
635 p9_sbe_timer_response(sbe);
636 goto again;
637 }
638
639 /* Unhandled bits */
640 val = data & ~(SBE_HOST_RESPONSE_MASK);
641 if (val) {
642 prlog(PR_ERR, "Unhandled interrupt bit [chip id = %x] : "
643 " %016llx\n", sbe->chip_id, val);
644 rc = p9_sbe_clear_interrupt(sbe, data);
645 if (rc)
646 return;
647 goto again;
648 }
649 }
650
p9_sbe_interrupt(uint32_t chip_id)651 void p9_sbe_interrupt(uint32_t chip_id)
652 {
653 struct proc_chip *chip;
654 struct p9_sbe *sbe;
655
656 chip = get_chip(chip_id);
657 if (chip == NULL || chip->sbe == NULL)
658 return;
659
660 sbe = chip->sbe;
661 lock(&sbe->lock);
662 __p9_sbe_interrupt(sbe);
663 p9_sbe_process_queue(sbe);
664 unlock(&sbe->lock);
665 }
666
667 /*
668 * Check if the timer is working. If at least 10ms elapsed since
669 * last scheduled timer expiry.
670 */
p9_sbe_timer_poll(struct p9_sbe * sbe)671 static void p9_sbe_timer_poll(struct p9_sbe *sbe)
672 {
673 if (sbe->chip_id != sbe_default_chip_id)
674 return;
675
676 if (!sbe_has_timer || !sbe_timer_in_progress)
677 return;
678
679 if (tb_compare(mftb(), sbe_last_gen_stamp + msecs_to_tb(10))
680 != TB_AAFTERB)
681 return;
682
683 prlog(PR_ERR, "Timer stuck, falling back to OPAL pollers.\n");
684 prlog(PR_ERR, "You will likely have slower I2C and may have "
685 "experienced increased jitter.\n");
686 p9_sbe_reg_dump(sbe->chip_id);
687 sbe_has_timer = false;
688 sbe_timer_in_progress = false;
689 }
690
p9_sbe_timeout_poll_one(struct p9_sbe * sbe)691 static void p9_sbe_timeout_poll_one(struct p9_sbe *sbe)
692 {
693 struct p9_sbe_msg *msg;
694
695 if (sbe->chip_id == sbe_default_chip_id) {
696 if (list_empty_nocheck(&sbe->msg_list) &&
697 !sbe_timer_in_progress)
698 return;
699 } else {
700 if (list_empty_nocheck(&sbe->msg_list))
701 return;
702 }
703
704 lock(&sbe->lock);
705
706 /*
707 * In some cases there will be a delay in calling OPAL interrupt
708 * handler routine (opal_handle_interrupt). In such cases its
709 * possible that SBE has responded, but OPAL didn't act on that.
710 * Hence check for SBE response.
711 */
712 __p9_sbe_interrupt(sbe);
713 p9_sbe_timer_poll(sbe);
714
715 if (list_empty(&sbe->msg_list))
716 goto out;
717
718 /*
719 * For some reason OPAL didn't sent message to SBE.
720 * Lets try to send message again.
721 */
722 if (!p9_sbe_mbox_busy(sbe)) {
723 p9_sbe_process_queue(sbe);
724 goto out;
725 }
726
727 msg = list_top(&sbe->msg_list, struct p9_sbe_msg, link);
728 if (tb_compare(mftb(), msg->timeout) != TB_AAFTERB)
729 goto out;
730
731 /* Message timeout */
732 prlog(PR_ERR, "Message timeout [chip id = %x], cmd = %llx, "
733 "subcmd = %llx\n", sbe->chip_id,
734 (msg->reg[0] >> 8) & 0xff, msg->reg[0] & 0xff);
735 p9_sbe_reg_dump(sbe->chip_id);
736 if (msg->resp) {
737 p9_sbe_set_primary_rc(msg->resp,
738 SBE_STATUS_PRI_GENERIC_ERR);
739 }
740
741 /* XXX Handle SBE R/R. Reset SBE state until SBE R/R works. */
742 sbe->state = sbe_mbox_idle;
743 p9_sbe_msg_complete(sbe, msg, sbe_msg_timeout);
744 p9_sbe_process_queue(sbe);
745
746 out:
747 unlock(&sbe->lock);
748 }
749
p9_sbe_timeout_poll(void * user_data __unused)750 static void p9_sbe_timeout_poll(void *user_data __unused)
751 {
752 struct p9_sbe *sbe;
753 struct proc_chip *chip;
754
755 for_each_chip(chip) {
756 if (chip->sbe == NULL)
757 continue;
758 sbe = chip->sbe;
759 p9_sbe_timeout_poll_one(sbe);
760 }
761 }
762
p9_sbe_timer_resp(struct p9_sbe_msg * msg)763 static void p9_sbe_timer_resp(struct p9_sbe_msg *msg)
764 {
765 if (msg->state != sbe_msg_done) {
766 prlog(PR_DEBUG, "Failed to schedule timer [chip id %x]\n",
767 sbe_default_chip_id);
768 } else {
769 /* Update last scheduled timer value */
770 sbe_last_gen_stamp = mftb() +
771 usecs_to_tb(timer_ctrl_msg->reg[1]);
772 sbe_timer_in_progress = true;
773 }
774
775 if (!has_new_target)
776 return;
777
778 lock(&sbe_timer_lock);
779 if (has_new_target) {
780 has_new_target = false;
781 p9_sbe_timer_schedule();
782 }
783 unlock(&sbe_timer_lock);
784 }
785
p9_sbe_timer_schedule(void)786 static void p9_sbe_timer_schedule(void)
787 {
788 int rc;
789 u32 tick_us = SBE_TIMER_DEFAULT_US;
790 u64 tb_cnt, now = mftb();
791
792 if (sbe_timer_in_progress) {
793 if (now >= sbe_last_gen_stamp)
794 return;
795
796 /* Remaining time of inflight timer <= sbe_timer_def_tb */
797 if ((sbe_last_gen_stamp - now) <= sbe_timer_def_tb)
798 return;
799 }
800
801 if (now < sbe_timer_target) {
802 /* Calculate how many microseconds from now, rounded up */
803 if ((sbe_timer_target - now) > sbe_timer_def_tb) {
804 tb_cnt = sbe_timer_target - now + usecs_to_tb(1) - 1;
805 tick_us = tb_to_usecs(tb_cnt);
806 }
807 }
808
809 /* Clear sequence number. p9_sbe_queue_msg will add new sequene ID */
810 timer_ctrl_msg->reg[0] &= ~(PPC_BITMASK(32, 47));
811 /* Update timeout value */
812 timer_ctrl_msg->reg[1] = tick_us;
813 rc = p9_sbe_queue_msg(sbe_default_chip_id, timer_ctrl_msg,
814 p9_sbe_timer_resp);
815 if (rc != OPAL_SUCCESS) {
816 prlog(PR_ERR, "Failed to start timer [chip id = %x]\n",
817 sbe_default_chip_id);
818 return;
819 }
820 }
821
822 /*
823 * This is called with the timer lock held, so there is no
824 * issue with re-entrancy or concurrence
825 */
p9_sbe_update_timer_expiry(uint64_t new_target)826 void p9_sbe_update_timer_expiry(uint64_t new_target)
827 {
828 if (!sbe_has_timer || new_target == sbe_timer_target)
829 return;
830
831 lock(&sbe_timer_lock);
832 /* Timer message is in flight. Record new timer and schedule later */
833 if (p9_sbe_msg_busy(timer_ctrl_msg) || has_new_target) {
834 if (new_target < sbe_timer_target) {
835 sbe_timer_target = new_target;
836 has_new_target = true;
837 }
838 } else {
839 sbe_timer_target = new_target;
840 p9_sbe_timer_schedule();
841 }
842 unlock(&sbe_timer_lock);
843 }
844
845 /* Initialize SBE timer */
p9_sbe_timer_init(void)846 static void p9_sbe_timer_init(void)
847 {
848 timer_ctrl_msg = p9_sbe_mkmsg(SBE_CMD_CONTROL_TIMER,
849 CONTROL_TIMER_START, 0, 0, 0);
850 assert(timer_ctrl_msg);
851 init_lock(&sbe_timer_lock);
852 sbe_has_timer = true;
853 sbe_timer_target = mftb();
854 sbe_last_gen_stamp = ~0ull;
855 sbe_timer_def_tb = usecs_to_tb(SBE_TIMER_DEFAULT_US);
856 prlog(PR_INFO, "Timer facility on chip %x\n", sbe_default_chip_id);
857 }
858
p9_sbe_timer_ok(void)859 bool p9_sbe_timer_ok(void)
860 {
861 return sbe_has_timer;
862 }
863
p9_sbe_init(void)864 void p9_sbe_init(void)
865 {
866 struct dt_node *xn;
867 struct proc_chip *chip;
868 struct p9_sbe *sbe;
869
870 if (proc_gen < proc_gen_p9)
871 return;
872
873 dt_for_each_compatible(dt_root, xn, "ibm,xscom") {
874 sbe = zalloc(sizeof(struct p9_sbe));
875 assert(sbe);
876 sbe->chip_id = dt_get_chip_id(xn);
877 sbe->cur_seq = 1;
878 sbe->state = sbe_mbox_idle;
879 list_head_init(&sbe->msg_list);
880 init_lock(&sbe->lock);
881
882 chip = get_chip(sbe->chip_id);
883 assert(chip);
884 chip->sbe = sbe;
885
886 if (dt_has_node_property(xn, "primary", NULL)) {
887 sbe_default_chip_id = sbe->chip_id;
888 prlog(PR_DEBUG, "Master chip id : %x\n", sbe->chip_id);
889 }
890 }
891
892 if (sbe_default_chip_id == -1) {
893 prlog(PR_ERR, "Master chip ID not found.\n");
894 return;
895 }
896
897 /* Initiate SBE timer */
898 p9_sbe_timer_init();
899
900 /* Initiate SBE timeout poller */
901 opal_add_poller(p9_sbe_timeout_poll, NULL);
902 }
903