1 /* 2 * (C) Copyright 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 37 #define CONFIG_IVML24 1 /* ...on a IVML24 board */ 38 39 #if defined (CONFIG_IVML24_16M) 40 # define CONFIG_IDENT_STRING " IVML24" 41 #elif defined (CONFIG_IVML24_32M) 42 # define CONFIG_IDENT_STRING " IVML24_128" 43 #elif defined (CONFIG_IVML24_64M) 44 # define CONFIG_IDENT_STRING " IVML24_256" 45 #endif 46 47 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 48 #undef CONFIG_8xx_CONS_SMC2 49 #undef CONFIG_8xx_CONS_NONE 50 #define CONFIG_BAUDRATE 115200 51 52 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 53 #define CONFIG_8xx_GCLK_FREQ 50331648 54 55 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 56 57 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ 58 59 #if 0 60 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 61 #else 62 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 63 #endif 64 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ 65 66 #define CONFIG_BOOTARGS "root=/dev/nfs rw " \ 67 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ 68 "nfsaddrs=10.0.0.99:10.0.0.2" 69 70 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 71 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 72 73 #undef CONFIG_WATCHDOG /* watchdog disabled */ 74 75 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 76 77 78 /* 79 * Command line configuration. 80 */ 81 #include <config_cmd_default.h> 82 83 #define CONFIG_CMD_IDE 84 85 86 #define CONFIG_MAC_PARTITION 87 #define CONFIG_DOS_PARTITION 88 89 /* 90 * BOOTP options 91 */ 92 #define CONFIG_BOOTP_SUBNETMASK 93 #define CONFIG_BOOTP_HOSTNAME 94 #define CONFIG_BOOTP_BOOTPATH 95 #define CONFIG_BOOTP_BOOTFILESIZE 96 97 98 /* 99 * Miscellaneous configurable options 100 */ 101 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 102 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 103 #if defined(CONFIG_CMD_KGDB) 104 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 105 #else 106 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 107 #endif 108 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 109 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 110 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 111 112 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 113 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ 114 115 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 116 117 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ 118 119 #define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */ 120 #define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */ 121 #define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ 122 #define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ 123 #define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */ 124 125 #define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ 126 #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ 127 128 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 129 130 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 131 132 /* 133 * Low Level Configuration Settings 134 * (address mappings, register initial values, etc.) 135 * You should know what you are doing if you make changes here. 136 */ 137 /*----------------------------------------------------------------------- 138 * Internal Memory Mapped Register 139 */ 140 #define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ 141 142 /*----------------------------------------------------------------------- 143 * Definitions for initial stack pointer and data area (in DPRAM) 144 */ 145 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 146 147 #if defined (CONFIG_IVML24_16M) 148 # define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 149 #elif defined (CONFIG_IVML24_32M) 150 # define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ 151 #elif defined (CONFIG_IVML24_64M) 152 # define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ 153 #endif 154 155 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 156 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 158 159 /*----------------------------------------------------------------------- 160 * Start addresses for the final memory configuration 161 * (Set up by the startup code) 162 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 163 */ 164 #define CONFIG_SYS_SDRAM_BASE 0x00000000 165 #define CONFIG_SYS_FLASH_BASE 0xFF000000 166 #ifdef DEBUG 167 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 168 #else 169 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 170 #endif 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 172 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 173 174 /* 175 * For booting Linux, the board info and command line data 176 * have to be in the first 8 MB of memory, since this is 177 * the maximum mapped by the Linux kernel during initialization. 178 */ 179 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 180 /*----------------------------------------------------------------------- 181 * FLASH organization 182 */ 183 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 184 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 185 186 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 187 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 188 189 #define CONFIG_ENV_IS_IN_FLASH 1 190 #define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ 191 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 192 /*----------------------------------------------------------------------- 193 * Cache Configuration 194 */ 195 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 196 #if defined(CONFIG_CMD_KGDB) 197 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 198 #endif 199 200 /*----------------------------------------------------------------------- 201 * SYPCR - System Protection Control 11-9 202 * SYPCR can only be written once after reset! 203 *----------------------------------------------------------------------- 204 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 205 */ 206 #if defined(CONFIG_WATCHDOG) 207 208 # if defined (CONFIG_IVML24_16M) 209 # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 210 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 211 # elif defined (CONFIG_IVML24_32M) 212 # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 213 SYPCR_SWE | SYPCR_SWP) 214 # elif defined (CONFIG_IVML24_64M) 215 # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 216 SYPCR_SWE | SYPCR_SWP) 217 # endif 218 219 #else 220 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 221 #endif 222 223 /*----------------------------------------------------------------------- 224 * SIUMCR - SIU Module Configuration 11-6 225 *----------------------------------------------------------------------- 226 * PCMCIA config., multi-function pin tri-state 227 */ 228 /* EARB, DBGC and DBPC are initialised by the HCW */ 229 /* => 0x000000C0 */ 230 #define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) 231 232 /*----------------------------------------------------------------------- 233 * TBSCR - Time Base Status and Control 11-26 234 *----------------------------------------------------------------------- 235 * Clear Reference Interrupt Status, Timebase freezing enabled 236 */ 237 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 238 239 /*----------------------------------------------------------------------- 240 * PISCR - Periodic Interrupt Status and Control 11-31 241 *----------------------------------------------------------------------- 242 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 243 */ 244 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 245 246 /*----------------------------------------------------------------------- 247 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 248 *----------------------------------------------------------------------- 249 * Reset PLL lock status sticky bit, timer expired status bit and timer 250 * interrupt status bit, set PLL multiplication factor ! 251 */ 252 /* 0x00B0C0C0 */ 253 #define CONFIG_SYS_PLPRCR \ 254 ( (11 << PLPRCR_MF_SHIFT) | \ 255 PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ 256 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ 257 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ 258 ) 259 260 /*----------------------------------------------------------------------- 261 * SCCR - System Clock and reset Control Register 15-27 262 *----------------------------------------------------------------------- 263 * Set clock output, timebase and RTC source and divider, 264 * power management and some other internal clocks 265 */ 266 #define SCCR_MASK SCCR_EBDF11 267 /* 0x01800014 */ 268 #define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ 269 SCCR_RTDIV | SCCR_RTSEL | \ 270 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ 271 SCCR_EBDF00 | SCCR_DFSYNC00 | \ 272 SCCR_DFBRG00 | SCCR_DFNL000 | \ 273 SCCR_DFNH000 | SCCR_DFLCD101 | \ 274 SCCR_DFALCD00) 275 276 /*----------------------------------------------------------------------- 277 * RTCSC - Real-Time Clock Status and Control Register 11-27 278 *----------------------------------------------------------------------- 279 */ 280 /* 0x00C3 */ 281 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 282 283 284 /*----------------------------------------------------------------------- 285 * RCCR - RISC Controller Configuration Register 19-4 286 *----------------------------------------------------------------------- 287 */ 288 /* TIMEP=2 */ 289 #define CONFIG_SYS_RCCR 0x0200 290 291 /*----------------------------------------------------------------------- 292 * RMDS - RISC Microcode Development Support Control Register 293 *----------------------------------------------------------------------- 294 */ 295 #define CONFIG_SYS_RMDS 0 296 297 /*----------------------------------------------------------------------- 298 * 299 * Interrupt Levels 300 *----------------------------------------------------------------------- 301 */ 302 #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ 303 304 /*----------------------------------------------------------------------- 305 * PCMCIA stuff 306 *----------------------------------------------------------------------- 307 * 308 */ 309 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 310 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 311 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 312 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 313 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 314 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 315 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 316 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 317 318 /*----------------------------------------------------------------------- 319 * IDE/ATA stuff 320 *----------------------------------------------------------------------- 321 */ 322 #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ 323 #define CONFIG_IDE_RESET 1 /* reset for ide supported */ 324 325 #define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/ 326 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ 327 328 #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 329 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 330 #undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */ 331 332 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ 333 #define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ 334 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ 335 336 /*----------------------------------------------------------------------- 337 * 338 *----------------------------------------------------------------------- 339 * 340 */ 341 #define CONFIG_SYS_DER 0 342 343 /* 344 * Init Memory Controller: 345 * 346 * BR0 and OR0 (FLASH) 347 */ 348 349 #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ 350 351 /* used to re-map FLASH both when starting from SRAM or FLASH: 352 * restrict access enough to keep SRAM working (if any) 353 * but not too much to meddle with FLASH accesses 354 */ 355 /* EPROMs are 512kb */ 356 #define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ 357 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ 358 359 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 360 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR) 361 362 #define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \ 363 CONFIG_SYS_OR_TIMING_FLASH) 364 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \ 365 CONFIG_SYS_OR_TIMING_FLASH) 366 /* 16 bit, bank valid */ 367 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 368 369 /* 370 * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 371 * 372 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 373 */ 374 #define ELIC_SACCO_BASE 0xFE000000 375 #define ELIC_SACCO_OR_AM 0xFFFF8000 376 #define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) 377 378 #define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ 379 ELIC_SACCO_TIMING) 380 #define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) 381 382 /* 383 * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 384 * 385 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 386 */ 387 #define ELIC_EPIC_BASE 0xFE008000 388 #define ELIC_EPIC_OR_AM 0xFFFF8000 389 #define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) 390 391 #define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ 392 ELIC_EPIC_TIMING) 393 #define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) 394 395 /* 396 * BR3/OR3: SDRAM 397 * 398 * Multiplexed addresses, GPL5 output to GPL5_A (don't care) 399 */ 400 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ 401 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ 402 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ 403 404 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ 405 406 #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) 407 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) 408 409 /* 410 * BR4/OR4 - HDLC Address 411 * 412 * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0 413 */ 414 #define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */ 415 #define HDLC_ADDR_OR_AM 0xFFFF8000 416 #define HDLC_ADDR_TIMING OR_SCY_1_CLK 417 418 #define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING) 419 #define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V ) 420 421 /* 422 * BR5/OR5: SHARC ADSP-2165L 423 * 424 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 425 */ 426 #define SHARC_BASE 0xFE400000 427 #define SHARC_OR_AM 0xFFC00000 428 #define SHARC_TIMING OR_SCY_0_CLK 429 430 #define CONFIG_SYS_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING ) 431 #define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) 432 433 /* 434 * Memory Periodic Timer Prescaler 435 */ 436 437 /* periodic timer for refresh */ 438 #define CONFIG_SYS_MBMR_PTB 204 439 440 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 441 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 442 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 443 444 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 445 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 446 447 #if defined (CONFIG_IVML24_16M) 448 # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 449 #elif defined (CONFIG_IVML24_32M) 450 # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 451 #elif defined (CONFIG_IVML24_64M) 452 # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ 453 #endif 454 455 456 /* 457 * MBMR settings for SDRAM 458 */ 459 460 #if defined (CONFIG_IVML24_16M) 461 /* 8 column SDRAM */ 462 # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ 463 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ 464 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) 465 #elif defined (CONFIG_IVML24_32M) 466 /* 128 MBit SDRAM */ 467 # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ 468 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ 469 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) 470 #elif defined (CONFIG_IVML24_64M) 471 /* 128 MBit SDRAM */ 472 # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ 473 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ 474 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) 475 #endif 476 477 /* 478 * Internal Definitions 479 * 480 * Boot Flags 481 */ 482 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 483 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 484 485 #endif /* __CONFIG_H */ 486