1 /* 2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> 3 * (C) Copyright 2009, DAVE Srl <www.dave.eu> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * Aria board configuration file 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #define CONFIG_ARIA 1 32 /* 33 * Memory map for the ARIA board: 34 * 35 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) 36 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) 37 * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6 38 * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2 39 * 0x8000_0000-0x803F_FFFF IMMR (4 MB) 40 * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB) 41 * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB) 42 * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB) 43 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) 44 */ 45 46 /* 47 * High Level Configuration Options 48 */ 49 #define CONFIG_E300 1 /* E300 Family */ 50 #define CONFIG_MPC512X 1 /* MPC512X family */ 51 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 52 #define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */ 53 54 /* video */ 55 #undef CONFIG_VIDEO 56 57 #if defined(CONFIG_VIDEO) 58 #define CONFIG_CFB_CONSOLE 59 #define CONFIG_VGA_AS_SINGLE_DEVICE 60 #endif 61 62 /* CONFIG_PCI is defined at config time */ 63 64 #define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ 65 66 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ 67 #define CONFIG_MISC_INIT_R 68 69 #define CONFIG_SYS_IMMR 0x80000000 70 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) 71 72 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 73 #define CONFIG_SYS_MEMTEST_END 0x00400000 74 75 /* 76 * DDR Setup - manually set all parameters as there's no SPD etc. 77 */ 78 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 79 #define CONFIG_SYS_DDR_BASE 0x00000000 80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 81 #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 82 83 #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 84 85 /* DDR Controller Configuration 86 * 87 * SYS_CFG: 88 * [31:31] MDDRC Soft Reset: Diabled 89 * [30:30] DRAM CKE pin: Enabled 90 * [29:29] DRAM CLK: Enabled 91 * [28:28] Command Mode: Enabled (For initialization only) 92 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] 93 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] 94 * [20:19] Read Test: DON'T USE 95 * [18:18] Self Refresh: Enabled 96 * [17:17] 16bit Mode: Disabled 97 * [16:13] Ready Delay: 2 98 * [12:12] Half DQS Delay: Disabled 99 * [11:11] Quarter DQS Delay: Disabled 100 * [10:08] Write Delay: 2 101 * [07:07] Early ODT: Disabled 102 * [06:06] On DIE Termination: Disabled 103 * [05:05] FIFO Overflow Clear: DON'T USE here 104 * [04:04] FIFO Underflow Clear: DON'T USE here 105 * [03:03] FIFO Overflow Pending: DON'T USE here 106 * [02:02] FIFO Underlfow Pending: DON'T USE here 107 * [01:01] FIFO Overlfow Enabled: Enabled 108 * [00:00] FIFO Underflow Enabled: Enabled 109 * TIME_CFG0 110 * [31:16] DRAM Refresh Time: 0 CSB clocks 111 * [15:8] DRAM Command Time: 0 CSB clocks 112 * [07:00] DRAM Precharge Time: 0 CSB clocks 113 * TIME_CFG1 114 * [31:26] DRAM tRFC: 115 * [25:21] DRAM tWR1: 116 * [20:17] DRAM tWRT1: 117 * [16:11] DRAM tDRR: 118 * [10:05] DRAM tRC: 119 * [04:00] DRAM tRAS: 120 * TIME_CFG2 121 * [31:28] DRAM tRCD: 122 * [27:23] DRAM tFAW: 123 * [22:19] DRAM tRTW1: 124 * [18:15] DRAM tCCD: 125 * [14:10] DRAM tRTP: 126 * [09:05] DRAM tRP: 127 * [04:00] DRAM tRPA 128 */ 129 #define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ 130 (1 << 30) | /* CKE */ \ 131 (1 << 29) | /* CLK_ON */ \ 132 (0 << 28) | /* CMD_MODE */ \ 133 (4 << 25) | /* DRAM_ROW_SELECT */ \ 134 (3 << 21) | /* DRAM_BANK_SELECT */ \ 135 (0 << 18) | /* SELF_REF_EN */ \ 136 (0 << 17) | /* 16BIT_MODE */ \ 137 (2 << 13) | /* RDLY */ \ 138 (0 << 12) | /* HALF_DQS_DLY */ \ 139 (1 << 11) | /* QUART_DQS_DLY */ \ 140 (2 << 8) | /* WDLY */ \ 141 (0 << 7) | /* EARLY_ODT */ \ 142 (1 << 6) | /* ON_DIE_TERMINATE */ \ 143 (0 << 5) | /* FIFO_OV_CLEAR */ \ 144 (0 << 4) | /* FIFO_UV_CLEAR */ \ 145 (0 << 1) | /* FIFO_OV_EN */ \ 146 (0 << 0) /* FIFO_UV_EN */ \ 147 ) 148 149 #define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E 150 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 151 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 152 153 #define CONFIG_SYS_DDRCMD_NOP 0x01380000 154 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 155 #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ 156 (0 << 22) | /* DRAM_CS */ \ 157 (0 << 21) | /* DRAM_RAS */ \ 158 (0 << 20) | /* DRAM_CAS */ \ 159 (0 << 19) | /* DRAM_WEB */ \ 160 (1 << 16) | /* DRAM_BS[2:0] */ \ 161 (0 << 15) | /* */ \ 162 (0 << 12) | /* A12->out */ \ 163 (0 << 11) | /* A11->RDQS */ \ 164 (0 << 10) | /* A10->DQS# */ \ 165 (0 << 7) | /* OCD program */ \ 166 (0 << 6) | /* Rtt1 */ \ 167 (0 << 3) | /* posted CAS# */ \ 168 (0 << 2) | /* Rtt0 */ \ 169 (1 << 1) | /* ODS */ \ 170 (0 << 0) /* DLL */ \ 171 ) 172 #define CONFIG_SYS_MICRON_EMR2 0x01020000 173 #define CONFIG_SYS_MICRON_EMR3 0x01030000 174 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 175 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 176 #define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ 177 (0 << 22) | /* DRAM_CS */ \ 178 (0 << 21) | /* DRAM_RAS */ \ 179 (0 << 20) | /* DRAM_CAS */ \ 180 (0 << 19) | /* DRAM_WEB */ \ 181 (1 << 16) | /* DRAM_BS[2:0] */ \ 182 (0 << 15) | /* */ \ 183 (0 << 12) | /* A12->out */ \ 184 (0 << 11) | /* A11->RDQS */ \ 185 (1 << 10) | /* A10->DQS# */ \ 186 (7 << 7) | /* OCD program */ \ 187 (0 << 6) | /* Rtt1 */ \ 188 (0 << 3) | /* posted CAS# */ \ 189 (1 << 2) | /* Rtt0 */ \ 190 (0 << 1) | /* ODS (Output Drive Strength) */ \ 191 (0 << 0) /* DLL */ \ 192 ) 193 194 /* 195 * Backward compatible definitions, 196 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c 197 */ 198 #define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) 199 #define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) 200 #define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) 201 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) 202 203 /* DDR Priority Manager Configuration */ 204 #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 205 #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 206 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 207 #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC 208 #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA 209 #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 210 #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 211 #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 212 #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 213 #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 214 #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 215 #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 216 #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 217 #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa 218 #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa 219 #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 220 #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 221 #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 222 #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 223 #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 224 #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 225 #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 226 #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 227 228 /* 229 * NOR FLASH on the Local Bus 230 */ 231 #define CONFIG_SYS_FLASH_CFI /* use the CFI code */ 232 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 233 #define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */ 234 #define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */ 235 236 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 238 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 239 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */ 240 241 #undef CONFIG_SYS_FLASH_CHECKSUM 242 243 /* 244 * NAND FLASH support 245 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) 246 */ 247 #define CONFIG_CMD_NAND /* enable NAND support */ 248 #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ 249 250 251 #define CONFIG_NAND_MPC5121_NFC 252 #define CONFIG_SYS_NAND_BASE 0x40000000 253 254 #define CONFIG_SYS_MAX_NAND_DEVICE 1 255 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 256 257 /* 258 * Configuration parameters for MPC5121 NAND driver 259 */ 260 #define CONFIG_FSL_NFC_WIDTH 1 261 #define CONFIG_FSL_NFC_WRITE_SIZE 2048 262 #define CONFIG_FSL_NFC_SPARE_SIZE 64 263 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 264 265 #define CONFIG_SYS_SRAM_BASE 0x30000000 266 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ 267 268 /* Make two SRAM regions contiguous */ 269 #define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ 270 CONFIG_SYS_SRAM_SIZE) 271 #define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ 272 273 #define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ 274 CONFIG_SYS_ARIA_SRAM_SIZE) 275 #define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ 276 277 #define CONFIG_SYS_CS0_CFG 0x05059150 278 #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ 279 (5 << 16) | \ 280 (1 << 15) | \ 281 (0 << 14) | \ 282 (0 << 13) | \ 283 (1 << 12) | \ 284 (0 << 10) | \ 285 (3 << 8) | /* 32 bit */ \ 286 (0 << 7) | \ 287 (1 << 6) | \ 288 (1 << 4) | \ 289 (0 << 3) | \ 290 (0 << 2) | \ 291 (0 << 1) | \ 292 (0 << 0) \ 293 ) 294 #define CONFIG_SYS_CS6_CFG 0x05059150 295 296 /* Use alternative CS timing for CS0 and CS2 */ 297 #define CONFIG_SYS_CS_ALETIMING 0x00000005 298 299 /* Use SRAM for initial stack */ 300 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE 301 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE 302 303 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 304 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ 305 CONFIG_SYS_GBL_DATA_SIZE) 306 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 307 308 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 309 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 310 311 #ifdef CONFIG_FSL_DIU_FB 312 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) 313 #else 314 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 315 #endif 316 317 /* FPGA */ 318 #define CONFIG_ARIA_FPGA 1 319 320 /* 321 * Serial Port 322 */ 323 #define CONFIG_CONS_INDEX 1 324 #undef CONFIG_SERIAL_SOFTWARE_FIFO 325 326 /* 327 * Serial console configuration 328 */ 329 #define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ 330 #if CONFIG_PSC_CONSOLE != 3 331 #error CONFIG_PSC_CONSOLE must be 3 332 #endif 333 334 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 335 #define CONFIG_SYS_BAUDRATE_TABLE \ 336 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 337 338 #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE 339 #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR 340 #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE 341 #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR 342 343 #define CONFIG_CMDLINE_EDITING 1 /* command line history */ 344 /* Use the HUSH parser */ 345 #define CONFIG_SYS_HUSH_PARSER 346 #ifdef CONFIG_SYS_HUSH_PARSER 347 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 348 #endif 349 350 /* 351 * PCI 352 */ 353 #ifdef CONFIG_PCI 354 355 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 356 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 357 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 358 #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \ 359 CONFIG_SYS_PCI_MEM_SIZE) 360 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 361 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 362 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 363 #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 364 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ 365 366 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 367 368 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 369 370 #endif 371 372 /* I2C */ 373 #define CONFIG_HARD_I2C /* I2C with hardware support */ 374 #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ 375 #define CONFIG_I2C_MULTI_BUS 376 377 /* I2C speed and slave address */ 378 #define CONFIG_SYS_I2C_SPEED 100000 379 #define CONFIG_SYS_I2C_SLAVE 0x7F 380 #if 0 381 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 382 #endif 383 384 /* 385 * IIM - IC Identification Module 386 */ 387 #undef CONFIG_IIM 388 389 /* 390 * EEPROM configuration for Atmel AT24C32A-10TQ-2.7: 391 * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode 392 */ 393 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 394 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 395 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 396 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 397 398 /* 399 * Ethernet configuration 400 */ 401 #define CONFIG_MPC512x_FEC 1 402 #define CONFIG_NET_MULTI 403 #define CONFIG_PHY_ADDR 0x17 404 #define CONFIG_MII 1 /* MII PHY management */ 405 #define CONFIG_FEC_AN_TIMEOUT 1 406 #define CONFIG_HAS_ETH0 407 408 /* 409 * Environment 410 */ 411 #define CONFIG_ENV_IS_IN_FLASH 1 412 /* This has to be a multiple of the flash sector size */ 413 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 414 CONFIG_SYS_MONITOR_LEN) 415 #define CONFIG_ENV_SIZE 0x2000 416 #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */ 417 418 /* Address and size of Redundant Environment Sector */ 419 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 420 CONFIG_ENV_SECT_SIZE) 421 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 422 423 #define CONFIG_LOADS_ECHO 1 424 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 425 426 #include <config_cmd_default.h> 427 428 #define CONFIG_CMD_ASKENV 429 #define CONFIG_CMD_DHCP 430 #define CONFIG_CMD_EEPROM 431 #undef CONFIG_CMD_FUSE 432 #define CONFIG_CMD_I2C 433 #undef CONFIG_CMD_IDE 434 #define CONFIG_CMD_JFFS2 435 #define CONFIG_CMD_MII 436 #define CONFIG_CMD_NFS 437 #define CONFIG_CMD_PING 438 #define CONFIG_CMD_REGINFO 439 440 #if defined(CONFIG_PCI) 441 #define CONFIG_CMD_PCI 442 #endif 443 444 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) 445 #define CONFIG_DOS_PARTITION 446 #define CONFIG_MAC_PARTITION 447 #define CONFIG_ISO_PARTITION 448 #endif /* defined(CONFIG_CMD_IDE) */ 449 450 /* 451 * Dynamic MTD partition support 452 */ 453 #define CONFIG_CMD_MTDPARTS 454 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 455 #define CONFIG_FLASH_CFI_MTD 456 #define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand" 457 458 /* 459 * NOR flash layout: 460 * 461 * F8000000 - FEAFFFFF 107 MiB User Data 462 * FEB00000 - FFAFFFFF 16 MiB Root File System 463 * FFB00000 - FFFEFFFF 4 MiB Linux Kernel 464 * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env 465 * FFFC0000 - FFFFFFFF 256 KiB Device Tree 466 * 467 * NAND flash layout: one big partition 468 */ 469 #define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \ 470 "16m(rootfs)," \ 471 "4m(kernel)," \ 472 "768k(u-boot)," \ 473 "256k(dtb);" \ 474 "mpc5121.nand:-(data)" 475 476 /* 477 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. 478 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE 479 * is set to 0xFFFF, watchdog timeouts after about 64s. For details 480 * refer to chapter 36 of the MPC5121e Reference Manual. 481 */ 482 /* #define CONFIG_WATCHDOG */ /* enable watchdog */ 483 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF 484 485 /* 486 * Miscellaneous configurable options 487 */ 488 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 489 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 490 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 491 492 #ifdef CONFIG_CMD_KGDB 493 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 494 #else 495 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 496 #endif 497 498 /* Print Buffer Size */ 499 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 500 sizeof(CONFIG_SYS_PROMPT) + 16) 501 /* max number of command args */ 502 #define CONFIG_SYS_MAXARGS 32 503 /* Boot Argument Buffer Size */ 504 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 505 506 #define CONFIG_SYS_HZ 1000 507 508 /* 509 * For booting Linux, the board info and command line data 510 * have to be in the first 8 MB of memory, since this is 511 * the maximum mapped by the Linux kernel during initialization. 512 */ 513 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 514 515 /* Cache Configuration */ 516 #define CONFIG_SYS_DCACHE_SIZE 32768 517 #define CONFIG_SYS_CACHELINE_SIZE 32 518 #ifdef CONFIG_CMD_KGDB 519 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ 520 #endif 521 522 #define CONFIG_SYS_HID0_INIT 0x000000000 523 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 524 HID0_ICE) 525 #define CONFIG_SYS_HID2 HID2_HBE 526 527 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 528 529 /* 530 * Internal Definitions 531 * 532 * Boot Flags 533 */ 534 #define BOOTFLAG_COLD 0x01 535 #define BOOTFLAG_WARM 0x02 536 537 #ifdef CONFIG_CMD_KGDB 538 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 539 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 540 #endif 541 542 /* 543 * Environment Configuration 544 */ 545 #define CONFIG_ENV_OVERWRITE 546 #define CONFIG_TIMESTAMP 547 548 #define CONFIG_HOSTNAME aria 549 #define CONFIG_BOOTFILE aria/uImage 550 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx 551 552 #define CONFIG_LOADADDR 400000 /* default load addr */ 553 554 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 555 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 556 557 #define CONFIG_BAUDRATE 115200 558 559 #define CONFIG_PREBOOT "echo;" \ 560 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 561 "echo" 562 563 #define CONFIG_EXTRA_ENV_SETTINGS \ 564 "u-boot_addr_r=200000\0" \ 565 "kernel_addr_r=600000\0" \ 566 "fdt_addr_r=880000\0" \ 567 "ramdisk_addr_r=900000\0" \ 568 "u-boot_addr=FFF00000\0" \ 569 "kernel_addr=FFB00000\0" \ 570 "fdt_addr=FFFC0000\0" \ 571 "ramdisk_addr=FEB00000\0" \ 572 "ramdiskfile=aria/uRamdisk\0" \ 573 "u-boot=aria/u-boot.bin\0" \ 574 "fdtfile=aria/aria.dtb\0" \ 575 "netdev=eth0\0" \ 576 "consdev=ttyPSC0\0" \ 577 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 578 "nfsroot=${serverip}:${rootpath}\0" \ 579 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 580 "addip=setenv bootargs ${bootargs} " \ 581 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 582 ":${hostname}:${netdev}:off panic=1\0" \ 583 "addtty=setenv bootargs ${bootargs} " \ 584 "console=${consdev},${baudrate}\0" \ 585 "flash_nfs=run nfsargs addip addtty;" \ 586 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 587 "flash_self=run ramargs addip addtty;" \ 588 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 589 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 590 "tftp ${fdt_addr_r} ${fdtfile};" \ 591 "run nfsargs addip addtty;" \ 592 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 593 "net_self=tftp ${kernel_addr_r} ${bootfile};" \ 594 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ 595 "tftp ${fdt_addr_r} ${fdtfile};" \ 596 "run ramargs addip addtty;" \ 597 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ 598 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 599 "update=protect off ${u-boot_addr} +${filesize};" \ 600 "era ${u-boot_addr} +${filesize};" \ 601 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ 602 "upd=run load update\0" \ 603 "" 604 605 #define CONFIG_BOOTCOMMAND "run flash_self" 606 607 #define CONFIG_OF_LIBFDT 1 608 #define CONFIG_OF_BOARD_SETUP 1 609 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 610 611 #define OF_CPU "PowerPC,5121@0" 612 #define OF_SOC_COMPAT "fsl,mpc5121-immr" 613 #define OF_TBCLK (bd->bi_busfreq / 4) 614 #define OF_STDOUT_PATH "/soc@80000000/serial@11300" 615 616 /*----------------------------------------------------------------------- 617 * IDE/ATA stuff 618 *----------------------------------------------------------------------- 619 */ 620 621 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 622 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 623 #undef CONFIG_IDE_LED /* LED for IDE not supported */ 624 625 #define CONFIG_IDE_RESET /* reset for IDE supported */ 626 #define CONFIG_IDE_PREINIT 627 628 #define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ 629 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */ 630 631 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 632 #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() 633 634 /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ 635 #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) 636 637 /* Offset for normal register accesses */ 638 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 639 640 /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ 641 #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) 642 643 /* Interval between registers */ 644 #define CONFIG_SYS_ATA_STRIDE 4 645 646 #define ATA_BASE_ADDR get_pata_base() 647 648 /* 649 * Control register bit definitions 650 */ 651 #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 652 #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 653 #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 654 #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 655 #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 656 #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 657 #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 658 #define FSL_ATA_CTRL_IORDY_EN 0x01000000 659 660 #endif /* __CONFIG_H */ 661