1 /* 2 * (C) Copyright 2007 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef __CONFIG_H 25 #define __CONFIG_H 26 27 /* 28 * High Level Configuration Options 29 * (easy to change) 30 */ 31 32 #define CONFIG_MPC8247 1 33 #define CONFIG_MPC8272_FAMILY 1 34 #define CONFIG_MGCOGE 1 35 #define CONFIG_HOSTNAME mgcoge 36 37 #define CONFIG_CPM2 1 /* Has a CPM2 */ 38 39 /* include common defines/options for all Keymile boards */ 40 #include "keymile-common.h" 41 42 /* 43 * Select serial console configuration 44 * 45 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 46 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 47 * for SCC). 48 */ 49 #define CONFIG_CONS_ON_SMC /* Console is on SMC */ 50 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */ 51 #undef CONFIG_CONS_NONE /* It's not on external UART */ 52 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ 53 #define CONFIG_SYS_SMC_RXBUFLEN 128 54 #define CONFIG_SYS_MAXIDLE 10 55 56 /* 57 * Select ethernet configuration 58 * 59 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, 60 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for 61 * SCC, 1-3 for FCC) 62 * 63 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines 64 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET 65 * must be unset. 66 */ 67 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ 68 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ 69 #undef CONFIG_ETHER_NONE /* No external Ethernet */ 70 #define CONFIG_NET_MULTI 1 71 72 #define CONFIG_ETHER_INDEX 4 73 #define CONFIG_HAS_ETH0 74 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 75 76 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) 77 78 #ifndef CONFIG_8260_CLKIN 79 #define CONFIG_8260_CLKIN 66000000 /* in Hz */ 80 #endif 81 82 #define BOOTFLASH_START FE000000 83 #define CONFIG_PRAM 512 /* protected RAM [KBytes] */ 84 85 #define MTDIDS_DEFAULT "nor0=boot,nor1=app" 86 #define MTDPARTS_DEFAULT \ 87 "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \ 88 "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)" 89 90 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 91 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 92 #endif 93 /* 94 * Default environment settings 95 */ 96 #define CONFIG_EXTRA_ENV_SETTINGS \ 97 CONFIG_KM_DEF_ENV \ 98 "rootpath=/opt/eldk/ppc_82xx\0" \ 99 "addcon=setenv bootargs ${bootargs} " \ 100 "console=ttyCPM0,${baudrate}\0" \ 101 "mtdids=nor0=boot,nor1=app \0" \ 102 "partition=nor1,5 \0" \ 103 "new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0" \ 104 "EEprom_ivm=pca9544a:70:4 \0" \ 105 "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ 106 "unlock=yes\0" \ 107 "" 108 109 #define CONFIG_SYS_SDRAM_BASE 0x00000000 110 #define CONFIG_SYS_FLASH_BASE 0xFE000000 111 #define CONFIG_SYS_FLASH_SIZE 32 112 #define CONFIG_SYS_FLASH_CFI 113 #define CONFIG_FLASH_CFI_DRIVER 114 #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ 115 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 116 117 #define CONFIG_SYS_FLASH_BASE_1 0x50000000 118 #define CONFIG_SYS_FLASH_SIZE_1 32 119 #define CONFIG_SYS_FLASH_BASE_2 0x52000000 120 #define CONFIG_SYS_FLASH_SIZE_2 32 121 122 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ 123 CONFIG_SYS_FLASH_BASE_1, \ 124 CONFIG_SYS_FLASH_BASE_2 } 125 126 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 127 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 128 #define CONFIG_SYS_RAMBOOT 129 #endif 130 131 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */ 132 133 #define CONFIG_ENV_IS_IN_FLASH 134 135 #ifdef CONFIG_ENV_IS_IN_FLASH 136 #define CONFIG_ENV_SECT_SIZE 0x20000 137 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 138 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN 139 140 /* Address and size of Redundant Environment Sector */ 141 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 142 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 143 #endif /* CONFIG_ENV_IS_IN_FLASH */ 144 #define CONFIG_ENV_BUFFER_PRINT 1 145 146 /* enable I2C and select the hardware/software driver */ 147 #undef CONFIG_HARD_I2C /* I2C with hardware support */ 148 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 149 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ 150 #define CONFIG_SYS_I2C_SLAVE 0x7F 151 152 /* 153 * Software (bit-bang) I2C driver configuration 154 */ 155 156 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 157 #define I2C_ACTIVE (iop->pdir |= 0x00010000) 158 #define I2C_TRISTATE (iop->pdir &= ~0x00010000) 159 #define I2C_READ ((iop->pdat & 0x00010000) != 0) 160 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 161 else iop->pdat &= ~0x00010000 162 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 163 else iop->pdat &= ~0x00020000 164 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 165 166 /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 167 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 168 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 169 #define CONFIG_SYS_DTT_MAX_TEMP 70 170 #define CONFIG_SYS_DTT_LOW_TEMP -30 171 #define CONFIG_SYS_DTT_HYSTERESIS 3 172 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) 173 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 175 176 #define CONFIG_SYS_IMMR 0xF0000000 177 178 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 179 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ 180 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 181 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 182 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 183 184 /* Hard reset configuration word */ 185 #define CONFIG_SYS_HRCW_MASTER 0x0604b211 186 187 /* No slaves */ 188 #define CONFIG_SYS_HRCW_SLAVE1 0 189 #define CONFIG_SYS_HRCW_SLAVE2 0 190 #define CONFIG_SYS_HRCW_SLAVE3 0 191 #define CONFIG_SYS_HRCW_SLAVE4 0 192 #define CONFIG_SYS_HRCW_SLAVE5 0 193 #define CONFIG_SYS_HRCW_SLAVE6 0 194 #define CONFIG_SYS_HRCW_SLAVE7 0 195 196 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 197 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 198 199 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 200 201 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ 202 #if defined(CONFIG_CMD_KGDB) 203 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 204 #endif 205 206 #define CONFIG_SYS_HID0_INIT 0 207 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) 208 209 #define CONFIG_SYS_HID2 0 210 211 #define CONFIG_SYS_SIUMCR 0x4020c200 212 #define CONFIG_SYS_SYPCR 0xFFFFFFC3 213 #define CONFIG_SYS_BCR 0x10000000 214 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) 215 216 /*----------------------------------------------------------------------- 217 * RMR - Reset Mode Register 5-5 218 *----------------------------------------------------------------------- 219 * turn on Checkstop Reset Enable 220 */ 221 #define CONFIG_SYS_RMR 0 222 223 /*----------------------------------------------------------------------- 224 * TMCNTSC - Time Counter Status and Control 4-40 225 *----------------------------------------------------------------------- 226 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 227 * and enable Time Counter 228 */ 229 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 230 231 /*----------------------------------------------------------------------- 232 * PISCR - Periodic Interrupt Status and Control 4-42 233 *----------------------------------------------------------------------- 234 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 235 * Periodic timer 236 */ 237 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 238 239 /*----------------------------------------------------------------------- 240 * RCCR - RISC Controller Configuration 13-7 241 *----------------------------------------------------------------------- 242 */ 243 #define CONFIG_SYS_RCCR 0 244 245 /* 246 * Init Memory Controller: 247 * 248 * Bank Bus Machine PortSz Device 249 * ---- --- ------- ------ ------ 250 * 0 60x GPCM 8 bit FLASH 251 * 1 60x SDRAM 32 bit SDRAM 252 * 3 60x GPCM 8 bit GPIO/PIGGY 253 * 5 60x GPCM 16 bit CFG-Flash 254 * 255 */ 256 /* Bank 0 - FLASH 257 */ 258 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 259 BRx_PS_8 |\ 260 BRx_MS_GPCM_P |\ 261 BRx_V) 262 263 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 264 ORxG_CSNT |\ 265 ORxG_ACS_DIV2 |\ 266 ORxG_SCY_5_CLK |\ 267 ORxG_TRLX ) 268 269 270 /* Bank 1 - 60x bus SDRAM 271 */ 272 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ 273 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ 274 275 #define CONFIG_SYS_MPTPR 0x1800 276 277 /*----------------------------------------------------------------------------- 278 * Address for Mode Register Set (MRS) command 279 *----------------------------------------------------------------------------- 280 */ 281 #define CONFIG_SYS_MRS_OFFS 0x00000110 282 #define CONFIG_SYS_PSRT 0x0e 283 284 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 285 BRx_PS_64 |\ 286 BRx_MS_SDRAM_P |\ 287 BRx_V) 288 289 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 290 291 /* SDRAM initialization values 292 */ 293 294 #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 295 ORxS_BPD_8 |\ 296 ORxS_ROWST_PBI0_A7 |\ 297 ORxS_NUMR_13) 298 299 #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ 300 PSDMR_BSMA_A14_A16 |\ 301 PSDMR_SDA10_PBI0_A9 |\ 302 PSDMR_RFRC_5_CLK |\ 303 PSDMR_PRETOACT_2W |\ 304 PSDMR_ACTTORW_2W |\ 305 PSDMR_LDOTOPRE_1C |\ 306 PSDMR_WRC_1C |\ 307 PSDMR_CL_2) 308 309 /* GPIO/PIGGY on CS3 initialization values 310 */ 311 #define CONFIG_SYS_PIGGY_BASE 0x30000000 312 #define CONFIG_SYS_PIGGY_SIZE 128 313 314 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\ 315 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) 316 317 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\ 318 ORxG_CSNT | ORxG_ACS_DIV2 |\ 319 ORxG_SCY_3_CLK | ORxG_TRLX ) 320 321 /* Board FPGA on CS4 initialization values 322 */ 323 #define CONFIG_SYS_FPGA_BASE 0x40000000 324 #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ 325 326 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ 327 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) 328 329 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ 330 ORxG_CSNT | ORxG_ACS_DIV2 |\ 331 ORxG_SCY_3_CLK | ORxG_TRLX ) 332 333 /* CFG-Flash on CS5 initialization values 334 */ 335 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ 336 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) 337 338 #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ 339 CONFIG_SYS_FLASH_SIZE_2) |\ 340 ORxG_CSNT | ORxG_ACS_DIV2 |\ 341 ORxG_SCY_5_CLK | ORxG_TRLX ) 342 343 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 344 345 /* pass open firmware flat tree */ 346 #define CONFIG_FIT 1 347 #define CONFIG_OF_LIBFDT 1 348 #define CONFIG_OF_BOARD_SETUP 1 349 350 #define OF_TBCLK (bd->bi_busfreq / 4) 351 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" 352 353 #endif /* __CONFIG_H */ 354