1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <gregory.clement@bootlin.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2018 Microsemi Corporation
8 */
9
10 #include <common.h>
11 #include <asm-generic/gpio.h>
12 #include <asm/io.h>
13 #include <dm.h>
14 #include <errno.h>
15
16 enum {
17 SDI,
18 CS0,
19 CS1,
20 CS2,
21 CS3,
22 SDO,
23 SCK
24 };
25
26 static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
27
28 #define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
29 #define SW_SPI_CS0_OE BIT(1)
30 #define SW_SPI_SDO_OE BIT(9)
31 #define SW_SPI_SCK_OE BIT(11)
32 #define SW_PIN_CTRL_MODE BIT(13)
33
34 struct mscc_bb_spi_gpio {
35 void __iomem *regs;
36 u32 cache_val;
37 };
38
mscc_bb_spi_gpio_set(struct udevice * dev,unsigned oft,int val)39 static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
40 {
41 struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
42
43 if (val)
44 gpio->cache_val |= BIT(pinmap[oft]);
45 else
46 gpio->cache_val &= ~BIT(pinmap[oft]);
47
48 writel(gpio->cache_val, gpio->regs);
49
50 return 0;
51 }
52
mscc_bb_spi_gpio_direction_output(struct udevice * dev,unsigned oft,int val)53 static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
54 int val)
55 {
56 if (oft == 0) {
57 pr_err("SW_SPI_DSI can't be used as output\n");
58 return -ENOTSUPP;
59 }
60
61 mscc_bb_spi_gpio_set(dev, oft, val);
62
63 return 0;
64 }
65
mscc_bb_spi_gpio_direction_input(struct udevice * dev,unsigned oft)66 static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
67 {
68 return 0;
69 }
70
mscc_bb_spi_gpio_get(struct udevice * dev,unsigned int oft)71 static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
72 {
73 struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
74 u32 val = readl(gpio->regs);
75
76 return !!(val & BIT(pinmap[oft]));
77 }
78
79 static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
80 .direction_output = mscc_bb_spi_gpio_direction_output,
81 .direction_input = mscc_bb_spi_gpio_direction_input,
82 .set_value = mscc_bb_spi_gpio_set,
83 .get_value = mscc_bb_spi_gpio_get,
84 };
85
mscc_bb_spi_gpio_probe(struct udevice * dev)86 static int mscc_bb_spi_gpio_probe(struct udevice *dev)
87 {
88 struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
89 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
90
91 gpio->regs = dev_remap_addr(dev);
92 if (!gpio->regs)
93 return -EINVAL;
94
95 uc_priv->bank_name = dev->name;
96 uc_priv->gpio_count = ARRAY_SIZE(pinmap);
97 /*
98 * Enable software mode to control the SPI pin, enables the
99 * output mode for most of the pin and initialize the cache
100 * value in the same time
101 */
102
103 gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
104 SW_SPI_CS0_OE;
105 writel(gpio->cache_val, gpio->regs);
106
107 return 0;
108 }
109
110 static const struct udevice_id mscc_bb_spi_gpio_ids[] = {
111 {.compatible = "mscc,spi-bitbang-gpio"},
112 {}
113 };
114
115 U_BOOT_DRIVER(gpio_mscc_bb_spi) = {
116 .name = "gpio-mscc-spi-bitbang",
117 .id = UCLASS_GPIO,
118 .ops = &mscc_bb_spi_gpio_ops,
119 .probe = mscc_bb_spi_gpio_probe,
120 .of_match = of_match_ptr(mscc_bb_spi_gpio_ids),
121 .priv_auto_alloc_size = sizeof(struct mscc_bb_spi_gpio),
122 };
123