1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 instruction set, defining the instructions, and 11// properties of the instructions which are needed for code generation, machine 12// code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// X86 specific DAG Nodes. 18// 19 20def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33// Unary and binary operator instructions that set EFLAGS as a side-effect. 34def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisSameAs<0, 2>, 36 SDTCisInt<0>, SDTCisVT<1, i32>]>; 37 38def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 39 [SDTCisSameAs<0, 2>, 40 SDTCisSameAs<0, 3>, 41 SDTCisInt<0>, SDTCisVT<1, i32>]>; 42 43// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 44def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 45 [SDTCisSameAs<0, 2>, 46 SDTCisSameAs<0, 3>, 47 SDTCisInt<0>, 48 SDTCisVT<1, i32>, 49 SDTCisVT<4, i32>]>; 50// RES1, RES2, FLAGS = op LHS, RHS 51def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 52 [SDTCisSameAs<0, 1>, 53 SDTCisSameAs<0, 2>, 54 SDTCisSameAs<0, 3>, 55 SDTCisInt<0>, SDTCisVT<1, i32>]>; 56def SDTX86BrCond : SDTypeProfile<0, 3, 57 [SDTCisVT<0, OtherVT>, 58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 59 60def SDTX86SetCC : SDTypeProfile<1, 2, 61 [SDTCisVT<0, i8>, 62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 63def SDTX86SetCC_C : SDTypeProfile<1, 2, 64 [SDTCisInt<0>, 65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 66 67def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 68 69def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 70 71def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 72 SDTCisVT<2, i8>]>; 73def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 74def SDTX86caspairSaveEbx8 : SDTypeProfile<1, 3, 75 [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 76 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 77def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3, 78 [SDTCisVT<0, i64>, SDTCisPtrTy<1>, 79 SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; 80 81def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 82 SDTCisPtrTy<1>, 83 SDTCisInt<2>]>; 84 85def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, 86 SDTCisPtrTy<1>]>; 87 88def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 89 90def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, 91 SDTCisVT<1, i32>]>; 92def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 93 SDTCisVT<1, i32>]>; 94 95def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 96 97def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 98 99def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 100 SDTCisVT<1, iPTR>, 101 SDTCisVT<2, iPTR>]>; 102 103def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 104 SDTCisPtrTy<1>, 105 SDTCisVT<2, i32>, 106 SDTCisVT<3, i8>, 107 SDTCisVT<4, i32>]>; 108 109def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 110 111def SDTX86Void : SDTypeProfile<0, 0, []>; 112 113def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 114 115def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 116 117def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 118 119def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 120 121def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 122 123def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 124 125def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 126 127def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 128 129def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 130 131def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 132 [SDNPHasChain,SDNPSideEffect]>; 133def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 134 [SDNPHasChain]>; 135 136 137def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 138def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 139def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 140def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 141 142def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 143def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 144 145def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 146def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 147 [SDNPHasChain]>; 148def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 149def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 150 151def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 152 153def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 154 [SDNPHasChain, SDNPSideEffect]>; 155 156def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 157 [SDNPHasChain, SDNPSideEffect]>; 158 159def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 160 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 161 SDNPMayLoad, SDNPMemOperand]>; 162def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 163 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 164 SDNPMayLoad, SDNPMemOperand]>; 165def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 166 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 167 SDNPMayLoad, SDNPMemOperand]>; 168def X86cas8save_ebx : SDNode<"X86ISD::LCMPXCHG8_SAVE_EBX_DAG", 169 SDTX86caspairSaveEbx8, 170 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 171 SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 172def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG", 173 SDTX86caspairSaveRbx16, 174 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 175 SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 176 177def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 178 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 179def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, 180 [SDNPHasChain, SDNPOptInGlue]>; 181 182def X86vastart_save_xmm_regs : 183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 184 SDT_X86VASTART_SAVE_XMM_REGS, 185 [SDNPHasChain, SDNPVariadic]>; 186def X86vaarg64 : 187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 189 SDNPMemOperand]>; 190def X86callseq_start : 191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 192 [SDNPHasChain, SDNPOutGlue]>; 193def X86callseq_end : 194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 196 197def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 199 SDNPVariadic]>; 200 201def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, 202 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 203 SDNPVariadic]>; 204def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, 205 [SDNPHasChain]>; 206 207def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 208 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 209def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 210 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 211 SDNPMayLoad]>; 212 213def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 214 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 215def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, 216 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 217def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, 218 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 219 220def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 221def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 222 223def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", 224 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 225 SDTCisInt<1>]>>; 226 227def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 228 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 229 230def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 231 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 232 233def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 234 [SDNPHasChain]>; 235 236def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 237 SDTypeProfile<1, 1, [SDTCisInt<0>, 238 SDTCisPtrTy<1>]>, 239 [SDNPHasChain, SDNPSideEffect]>; 240def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 241 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 242 [SDNPHasChain, SDNPSideEffect]>; 243def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", 244 SDTypeProfile<0, 0, []>, 245 [SDNPHasChain, SDNPSideEffect]>; 246 247def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 248 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 249 250def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 251 [SDNPCommutative]>; 252def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 253def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 254 [SDNPCommutative]>; 255def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 256 [SDNPCommutative]>; 257def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 258def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 259 260def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 261def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 262def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 263 [SDNPCommutative]>; 264def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 265 [SDNPCommutative]>; 266def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 267 [SDNPCommutative]>; 268 269def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, 270 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 271 SDNPMemOperand]>; 272def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, 273 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 274 SDNPMemOperand]>; 275def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, 276 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 277 SDNPMemOperand]>; 278def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, 279 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 280 SDNPMemOperand]>; 281def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, 282 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 283 SDNPMemOperand]>; 284 285def X86lock_inc : SDNode<"X86ISD::LINC", SDTLockUnaryArithWithFlags, 286 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 287 SDNPMemOperand]>; 288def X86lock_dec : SDNode<"X86ISD::LDEC", SDTLockUnaryArithWithFlags, 289 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 290 SDNPMemOperand]>; 291 292def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 293 294def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 295 296def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, 297 [SDNPHasChain, SDNPOutGlue]>; 298 299def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 300 [SDNPHasChain]>; 301 302def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 303 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 304 305def X86lwpins : SDNode<"X86ISD::LWPINS", 306 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 307 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 308 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; 309 310def X86umwait : SDNode<"X86ISD::UMWAIT", 311 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 312 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 313 [SDNPHasChain, SDNPSideEffect]>; 314 315def X86tpause : SDNode<"X86ISD::TPAUSE", 316 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 317 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 318 [SDNPHasChain, SDNPSideEffect]>; 319 320//===----------------------------------------------------------------------===// 321// X86 Operand Definitions. 322// 323 324// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 325// the index operand of an address, to conform to x86 encoding restrictions. 326def ptr_rc_nosp : PointerLikeRegClass<1>; 327 328// *mem - Operand definitions for the funky X86 addressing mode operands. 329// 330def X86MemAsmOperand : AsmOperandClass { 331 let Name = "Mem"; 332} 333let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { 334 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 335 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 336 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 337 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 338 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 339 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 340 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 341 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 342 // Gather mem operands 343 def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } 344 def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } 345 def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } 346 def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } 347 def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } 348 349 def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } 350 def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } 351 def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } 352 def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } 353 def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } 354 def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } 355 def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } 356 def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } 357} 358 359def X86AbsMemAsmOperand : AsmOperandClass { 360 let Name = "AbsMem"; 361 let SuperClasses = [X86MemAsmOperand]; 362} 363 364class X86MemOperand<string printMethod, 365 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> { 366 let PrintMethod = printMethod; 367 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); 368 let ParserMatchClass = parserMatchClass; 369 let OperandType = "OPERAND_MEMORY"; 370} 371 372// Gather mem operands 373class X86VMemOperand<RegisterClass RC, string printMethod, 374 AsmOperandClass parserMatchClass> 375 : X86MemOperand<printMethod, parserMatchClass> { 376 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); 377} 378 379def anymem : X86MemOperand<"printanymem">; 380 381// FIXME: Right now we allow any size during parsing, but we might want to 382// restrict to only unsized memory. 383def opaquemem : X86MemOperand<"printopaquemem">; 384 385def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; 386def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; 387def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; 388def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; 389def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; 390def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; 391def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; 392def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; 393def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; 394def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; 395def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; 396def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; 397def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; 398 399def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>; 400 401// Gather mem operands 402def vx64mem : X86VMemOperand<VR128, "printi64mem", X86Mem64_RC128Operand>; 403def vx128mem : X86VMemOperand<VR128, "printi128mem", X86Mem128_RC128Operand>; 404def vx256mem : X86VMemOperand<VR128, "printi256mem", X86Mem256_RC128Operand>; 405def vy128mem : X86VMemOperand<VR256, "printi128mem", X86Mem128_RC256Operand>; 406def vy256mem : X86VMemOperand<VR256, "printi256mem", X86Mem256_RC256Operand>; 407 408def vx64xmem : X86VMemOperand<VR128X, "printi64mem", X86Mem64_RC128XOperand>; 409def vx128xmem : X86VMemOperand<VR128X, "printi128mem", X86Mem128_RC128XOperand>; 410def vx256xmem : X86VMemOperand<VR128X, "printi256mem", X86Mem256_RC128XOperand>; 411def vy128xmem : X86VMemOperand<VR256X, "printi128mem", X86Mem128_RC256XOperand>; 412def vy256xmem : X86VMemOperand<VR256X, "printi256mem", X86Mem256_RC256XOperand>; 413def vy512xmem : X86VMemOperand<VR256X, "printi512mem", X86Mem512_RC256XOperand>; 414def vz256mem : X86VMemOperand<VR512, "printi256mem", X86Mem256_RC512Operand>; 415def vz512mem : X86VMemOperand<VR512, "printi512mem", X86Mem512_RC512Operand>; 416 417// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead 418// of a plain GPR, so that it doesn't potentially require a REX prefix. 419def ptr_rc_norex : PointerLikeRegClass<2>; 420def ptr_rc_norex_nosp : PointerLikeRegClass<3>; 421 422def i8mem_NOREX : Operand<iPTR> { 423 let PrintMethod = "printi8mem"; 424 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, 425 SEGMENT_REG); 426 let ParserMatchClass = X86Mem8AsmOperand; 427 let OperandType = "OPERAND_MEMORY"; 428} 429 430// GPRs available for tailcall. 431// It represents GR32_TC, GR64_TC or GR64_TCW64. 432def ptr_rc_tailcall : PointerLikeRegClass<4>; 433 434// Special i32mem for addresses of load folding tail calls. These are not 435// allowed to use callee-saved registers since they must be scheduled 436// after callee-saved register are popped. 437def i32mem_TC : Operand<i32> { 438 let PrintMethod = "printi32mem"; 439 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 440 i32imm, SEGMENT_REG); 441 let ParserMatchClass = X86Mem32AsmOperand; 442 let OperandType = "OPERAND_MEMORY"; 443} 444 445// Special i64mem for addresses of load folding tail calls. These are not 446// allowed to use callee-saved registers since they must be scheduled 447// after callee-saved register are popped. 448def i64mem_TC : Operand<i64> { 449 let PrintMethod = "printi64mem"; 450 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 451 ptr_rc_tailcall, i32imm, SEGMENT_REG); 452 let ParserMatchClass = X86Mem64AsmOperand; 453 let OperandType = "OPERAND_MEMORY"; 454} 455 456let OperandType = "OPERAND_PCREL", 457 ParserMatchClass = X86AbsMemAsmOperand, 458 PrintMethod = "printPCRelImm" in { 459def i32imm_pcrel : Operand<i32>; 460def i16imm_pcrel : Operand<i16>; 461 462// Branch targets have OtherVT type and print as pc-relative values. 463def brtarget : Operand<OtherVT>; 464def brtarget8 : Operand<OtherVT>; 465 466} 467 468// Special parser to detect 16-bit mode to select 16-bit displacement. 469def X86AbsMem16AsmOperand : AsmOperandClass { 470 let Name = "AbsMem16"; 471 let RenderMethod = "addAbsMemOperands"; 472 let SuperClasses = [X86AbsMemAsmOperand]; 473} 474 475// Branch targets have OtherVT type and print as pc-relative values. 476let OperandType = "OPERAND_PCREL", 477 PrintMethod = "printPCRelImm" in { 478let ParserMatchClass = X86AbsMem16AsmOperand in 479 def brtarget16 : Operand<OtherVT>; 480let ParserMatchClass = X86AbsMemAsmOperand in 481 def brtarget32 : Operand<OtherVT>; 482} 483 484let RenderMethod = "addSrcIdxOperands" in { 485 def X86SrcIdx8Operand : AsmOperandClass { 486 let Name = "SrcIdx8"; 487 let SuperClasses = [X86Mem8AsmOperand]; 488 } 489 def X86SrcIdx16Operand : AsmOperandClass { 490 let Name = "SrcIdx16"; 491 let SuperClasses = [X86Mem16AsmOperand]; 492 } 493 def X86SrcIdx32Operand : AsmOperandClass { 494 let Name = "SrcIdx32"; 495 let SuperClasses = [X86Mem32AsmOperand]; 496 } 497 def X86SrcIdx64Operand : AsmOperandClass { 498 let Name = "SrcIdx64"; 499 let SuperClasses = [X86Mem64AsmOperand]; 500 } 501} // RenderMethod = "addSrcIdxOperands" 502 503let RenderMethod = "addDstIdxOperands" in { 504 def X86DstIdx8Operand : AsmOperandClass { 505 let Name = "DstIdx8"; 506 let SuperClasses = [X86Mem8AsmOperand]; 507 } 508 def X86DstIdx16Operand : AsmOperandClass { 509 let Name = "DstIdx16"; 510 let SuperClasses = [X86Mem16AsmOperand]; 511 } 512 def X86DstIdx32Operand : AsmOperandClass { 513 let Name = "DstIdx32"; 514 let SuperClasses = [X86Mem32AsmOperand]; 515 } 516 def X86DstIdx64Operand : AsmOperandClass { 517 let Name = "DstIdx64"; 518 let SuperClasses = [X86Mem64AsmOperand]; 519 } 520} // RenderMethod = "addDstIdxOperands" 521 522let RenderMethod = "addMemOffsOperands" in { 523 def X86MemOffs16_8AsmOperand : AsmOperandClass { 524 let Name = "MemOffs16_8"; 525 let SuperClasses = [X86Mem8AsmOperand]; 526 } 527 def X86MemOffs16_16AsmOperand : AsmOperandClass { 528 let Name = "MemOffs16_16"; 529 let SuperClasses = [X86Mem16AsmOperand]; 530 } 531 def X86MemOffs16_32AsmOperand : AsmOperandClass { 532 let Name = "MemOffs16_32"; 533 let SuperClasses = [X86Mem32AsmOperand]; 534 } 535 def X86MemOffs32_8AsmOperand : AsmOperandClass { 536 let Name = "MemOffs32_8"; 537 let SuperClasses = [X86Mem8AsmOperand]; 538 } 539 def X86MemOffs32_16AsmOperand : AsmOperandClass { 540 let Name = "MemOffs32_16"; 541 let SuperClasses = [X86Mem16AsmOperand]; 542 } 543 def X86MemOffs32_32AsmOperand : AsmOperandClass { 544 let Name = "MemOffs32_32"; 545 let SuperClasses = [X86Mem32AsmOperand]; 546 } 547 def X86MemOffs32_64AsmOperand : AsmOperandClass { 548 let Name = "MemOffs32_64"; 549 let SuperClasses = [X86Mem64AsmOperand]; 550 } 551 def X86MemOffs64_8AsmOperand : AsmOperandClass { 552 let Name = "MemOffs64_8"; 553 let SuperClasses = [X86Mem8AsmOperand]; 554 } 555 def X86MemOffs64_16AsmOperand : AsmOperandClass { 556 let Name = "MemOffs64_16"; 557 let SuperClasses = [X86Mem16AsmOperand]; 558 } 559 def X86MemOffs64_32AsmOperand : AsmOperandClass { 560 let Name = "MemOffs64_32"; 561 let SuperClasses = [X86Mem32AsmOperand]; 562 } 563 def X86MemOffs64_64AsmOperand : AsmOperandClass { 564 let Name = "MemOffs64_64"; 565 let SuperClasses = [X86Mem64AsmOperand]; 566 } 567} // RenderMethod = "addMemOffsOperands" 568 569class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 570 : X86MemOperand<printMethod, parserMatchClass> { 571 let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); 572} 573 574class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 575 : X86MemOperand<printMethod, parserMatchClass> { 576 let MIOperandInfo = (ops ptr_rc); 577} 578 579def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 580def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 581def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 582def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 583def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 584def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 585def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 586def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 587 588class X86MemOffsOperand<Operand immOperand, string printMethod, 589 AsmOperandClass parserMatchClass> 590 : X86MemOperand<printMethod, parserMatchClass> { 591 let MIOperandInfo = (ops immOperand, SEGMENT_REG); 592} 593 594def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 595 X86MemOffs16_8AsmOperand>; 596def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 597 X86MemOffs16_16AsmOperand>; 598def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 599 X86MemOffs16_32AsmOperand>; 600def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 601 X86MemOffs32_8AsmOperand>; 602def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 603 X86MemOffs32_16AsmOperand>; 604def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 605 X86MemOffs32_32AsmOperand>; 606def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 607 X86MemOffs32_64AsmOperand>; 608def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 609 X86MemOffs64_8AsmOperand>; 610def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 611 X86MemOffs64_16AsmOperand>; 612def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 613 X86MemOffs64_32AsmOperand>; 614def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 615 X86MemOffs64_64AsmOperand>; 616 617def SSECC : Operand<i8> { 618 let PrintMethod = "printSSEAVXCC"; 619 let OperandType = "OPERAND_IMMEDIATE"; 620} 621 622def AVXCC : Operand<i8> { 623 let PrintMethod = "printSSEAVXCC"; 624 let OperandType = "OPERAND_IMMEDIATE"; 625} 626 627def AVX512ICC : Operand<i8> { 628 let PrintMethod = "printSSEAVXCC"; 629 let OperandType = "OPERAND_IMMEDIATE"; 630} 631 632def XOPCC : Operand<i8> { 633 let PrintMethod = "printXOPCC"; 634 let OperandType = "OPERAND_IMMEDIATE"; 635} 636 637class ImmSExtAsmOperandClass : AsmOperandClass { 638 let SuperClasses = [ImmAsmOperand]; 639 let RenderMethod = "addImmOperands"; 640} 641 642def X86GR32orGR64AsmOperand : AsmOperandClass { 643 let Name = "GR32orGR64"; 644} 645 646def GR32orGR64 : RegisterOperand<GR32> { 647 let ParserMatchClass = X86GR32orGR64AsmOperand; 648} 649def AVX512RCOperand : AsmOperandClass { 650 let Name = "AVX512RC"; 651} 652def AVX512RC : Operand<i32> { 653 let PrintMethod = "printRoundingControl"; 654 let OperandType = "OPERAND_IMMEDIATE"; 655 let ParserMatchClass = AVX512RCOperand; 656} 657 658// Sign-extended immediate classes. We don't need to define the full lattice 659// here because there is no instruction with an ambiguity between ImmSExti64i32 660// and ImmSExti32i8. 661// 662// The strange ranges come from the fact that the assembler always works with 663// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 664// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 665 666// [0, 0x7FFFFFFF] | 667// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 668def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 669 let Name = "ImmSExti64i32"; 670} 671 672// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 673// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 674def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 675 let Name = "ImmSExti16i8"; 676 let SuperClasses = [ImmSExti64i32AsmOperand]; 677} 678 679// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 680// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 681def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 682 let Name = "ImmSExti32i8"; 683} 684 685// [0, 0x0000007F] | 686// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 687def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 688 let Name = "ImmSExti64i8"; 689 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 690 ImmSExti64i32AsmOperand]; 691} 692 693// Unsigned immediate used by SSE/AVX instructions 694// [0, 0xFF] 695// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 696def ImmUnsignedi8AsmOperand : AsmOperandClass { 697 let Name = "ImmUnsignedi8"; 698 let RenderMethod = "addImmOperands"; 699} 700 701// A couple of more descriptive operand definitions. 702// 16-bits but only 8 bits are significant. 703def i16i8imm : Operand<i16> { 704 let ParserMatchClass = ImmSExti16i8AsmOperand; 705 let OperandType = "OPERAND_IMMEDIATE"; 706} 707// 32-bits but only 8 bits are significant. 708def i32i8imm : Operand<i32> { 709 let ParserMatchClass = ImmSExti32i8AsmOperand; 710 let OperandType = "OPERAND_IMMEDIATE"; 711} 712 713// 64-bits but only 32 bits are significant. 714def i64i32imm : Operand<i64> { 715 let ParserMatchClass = ImmSExti64i32AsmOperand; 716 let OperandType = "OPERAND_IMMEDIATE"; 717} 718 719// 64-bits but only 8 bits are significant. 720def i64i8imm : Operand<i64> { 721 let ParserMatchClass = ImmSExti64i8AsmOperand; 722 let OperandType = "OPERAND_IMMEDIATE"; 723} 724 725// Unsigned 8-bit immediate used by SSE/AVX instructions. 726def u8imm : Operand<i8> { 727 let PrintMethod = "printU8Imm"; 728 let ParserMatchClass = ImmUnsignedi8AsmOperand; 729 let OperandType = "OPERAND_IMMEDIATE"; 730} 731 732// 32-bit immediate but only 8-bits are significant and they are unsigned. 733// Used by some SSE/AVX instructions that use intrinsics. 734def i32u8imm : Operand<i32> { 735 let PrintMethod = "printU8Imm"; 736 let ParserMatchClass = ImmUnsignedi8AsmOperand; 737 let OperandType = "OPERAND_IMMEDIATE"; 738} 739 740// 64-bits but only 32 bits are significant, and those bits are treated as being 741// pc relative. 742def i64i32imm_pcrel : Operand<i64> { 743 let PrintMethod = "printPCRelImm"; 744 let ParserMatchClass = X86AbsMemAsmOperand; 745 let OperandType = "OPERAND_PCREL"; 746} 747 748def lea64_32mem : Operand<i32> { 749 let PrintMethod = "printanymem"; 750 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 751 let ParserMatchClass = X86MemAsmOperand; 752} 753 754// Memory operands that use 64-bit pointers in both ILP32 and LP64. 755def lea64mem : Operand<i64> { 756 let PrintMethod = "printanymem"; 757 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 758 let ParserMatchClass = X86MemAsmOperand; 759} 760 761 762//===----------------------------------------------------------------------===// 763// X86 Complex Pattern Definitions. 764// 765 766// Define X86-specific addressing mode. 767def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>; 768def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr", 769 [add, sub, mul, X86mul_imm, shl, or, frameindex], 770 []>; 771// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 772def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr", 773 [add, sub, mul, X86mul_imm, shl, or, 774 frameindex, X86WrapperRIP], 775 []>; 776 777def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 778 [tglobaltlsaddr], []>; 779 780def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 781 [tglobaltlsaddr], []>; 782 783def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr", 784 [add, sub, mul, X86mul_imm, shl, or, frameindex, 785 X86WrapperRIP], []>; 786 787def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 788 [tglobaltlsaddr], []>; 789 790def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 791 [tglobaltlsaddr], []>; 792 793def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; 794 795// A relocatable immediate is either an immediate operand or an operand that can 796// be relocated by the linker to an immediate, such as a regular symbol in 797// non-PIC code. 798def relocImm : ComplexPattern<iAny, 1, "selectRelocImm", [imm, X86Wrapper], [], 799 0>; 800 801//===----------------------------------------------------------------------===// 802// X86 Instruction Predicate Definitions. 803def TruePredicate : Predicate<"true">; 804 805def HasCMov : Predicate<"Subtarget->hasCMov()">; 806def NoCMov : Predicate<"!Subtarget->hasCMov()">; 807 808def HasMMX : Predicate<"Subtarget->hasMMX()">; 809def Has3DNow : Predicate<"Subtarget->has3DNow()">; 810def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 811def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 812def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 813def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 814def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 815def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 816def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 817def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 818def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 819def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 820def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; 821def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 822def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 823def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 824def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 825def NoAVX : Predicate<"!Subtarget->hasAVX()">; 826def HasAVX : Predicate<"Subtarget->hasAVX()">; 827def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 828def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 829def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; 830def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 831def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 832def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 833def HasCDI : Predicate<"Subtarget->hasCDI()">; 834def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; 835def HasPFI : Predicate<"Subtarget->hasPFI()">; 836def HasERI : Predicate<"Subtarget->hasERI()">; 837def HasDQI : Predicate<"Subtarget->hasDQI()">; 838def NoDQI : Predicate<"!Subtarget->hasDQI()">; 839def HasBWI : Predicate<"Subtarget->hasBWI()">; 840def NoBWI : Predicate<"!Subtarget->hasBWI()">; 841def HasVLX : Predicate<"Subtarget->hasVLX()">; 842def NoVLX : Predicate<"!Subtarget->hasVLX()">; 843def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; 844def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; 845def PKU : Predicate<"Subtarget->hasPKU()">; 846def HasVNNI : Predicate<"Subtarget->hasVNNI()">; 847 848def HasBITALG : Predicate<"Subtarget->hasBITALG()">; 849def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 850def HasAES : Predicate<"Subtarget->hasAES()">; 851def HasVAES : Predicate<"Subtarget->hasVAES()">; 852def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; 853def HasFXSR : Predicate<"Subtarget->hasFXSR()">; 854def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; 855def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; 856def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; 857def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; 858def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 859def NoVLX_Or_NoVPCLMULQDQ : 860 Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; 861def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; 862def HasGFNI : Predicate<"Subtarget->hasGFNI()">; 863def HasFMA : Predicate<"Subtarget->hasFMA()">; 864def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 865def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; 866def HasXOP : Predicate<"Subtarget->hasXOP()">; 867def HasTBM : Predicate<"Subtarget->hasTBM()">; 868def NoTBM : Predicate<"!Subtarget->hasTBM()">; 869def HasLWP : Predicate<"Subtarget->hasLWP()">; 870def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 871def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 872def HasF16C : Predicate<"Subtarget->hasF16C()">; 873def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 874def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 875def HasBMI : Predicate<"Subtarget->hasBMI()">; 876def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 877def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; 878def HasVBMI : Predicate<"Subtarget->hasVBMI()">; 879def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; 880def HasIFMA : Predicate<"Subtarget->hasIFMA()">; 881def HasRTM : Predicate<"Subtarget->hasRTM()">; 882def HasADX : Predicate<"Subtarget->hasADX()">; 883def HasSHA : Predicate<"Subtarget->hasSHA()">; 884def HasSGX : Predicate<"Subtarget->hasSGX()">; 885def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 886def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 887def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; 888def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; 889def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; 890def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; 891def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; 892def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; 893def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; 894def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; 895def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; 896def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; 897def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; 898def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 899def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 900def HasMPX : Predicate<"Subtarget->hasMPX()">; 901def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; 902def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; 903def HasCLWB : Predicate<"Subtarget->hasCLWB()">; 904def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; 905def HasRDPID : Predicate<"Subtarget->hasRDPID()">; 906def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; 907def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; 908def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 909def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; 910def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 911 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; 912def In64BitMode : Predicate<"Subtarget->is64Bit()">, 913 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 914def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; 915def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; 916def In16BitMode : Predicate<"Subtarget->is16Bit()">, 917 AssemblerPredicate<"Mode16Bit", "16-bit mode">; 918def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 919 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; 920def In32BitMode : Predicate<"Subtarget->is32Bit()">, 921 AssemblerPredicate<"Mode32Bit", "32-bit mode">; 922def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 923def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; 924def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" 925 "Subtarget->getFrameLowering()->hasFP(*MF)"> { 926 let RecomputePerFunction = 1; 927} 928def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; 929def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; 930def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 931def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 932def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 933def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 934def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 935 "TM.getCodeModel() == CodeModel::Kernel">; 936def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; 937 938// We could compute these on a per-module basis but doing so requires accessing 939// the Function object through the <Target>Subtarget and objections were raised 940// to that (see post-commit review comments for r301750). 941let RecomputePerFunction = 1 in { 942 def OptForSize : Predicate<"MF->getFunction().optForSize()">; 943 def OptForMinSize : Predicate<"MF->getFunction().optForMinSize()">; 944 def OptForSpeed : Predicate<"!MF->getFunction().optForSize()">; 945 def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " 946 "MF->getFunction().optForSize()">; 947 def NoSSE41_Or_OptForSize : Predicate<"MF->getFunction().optForSize() || " 948 "!Subtarget->hasSSE41()">; 949} 950 951def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; 952def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; 953def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; 954def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; 955def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; 956def HasERMSB : Predicate<"Subtarget->hasERMSB()">; 957def HasMFence : Predicate<"Subtarget->hasMFence()">; 958def UseRetpoline : Predicate<"Subtarget->useRetpoline()">; 959def NotUseRetpoline : Predicate<"!Subtarget->useRetpoline()">; 960 961//===----------------------------------------------------------------------===// 962// X86 Instruction Format Definitions. 963// 964 965include "X86InstrFormats.td" 966 967//===----------------------------------------------------------------------===// 968// Pattern fragments. 969// 970 971// X86 specific condition code. These correspond to CondCode in 972// X86InstrInfo.h. They must be kept in synch. 973def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 974def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 975def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 976def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 977def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 978def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 979def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 980def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 981def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 982def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 983def X86_COND_NO : PatLeaf<(i8 10)>; 984def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 985def X86_COND_NS : PatLeaf<(i8 12)>; 986def X86_COND_O : PatLeaf<(i8 13)>; 987def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 988def X86_COND_S : PatLeaf<(i8 15)>; 989 990def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>; 991def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>; 992def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>; 993def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>; 994 995// FIXME: Ideally we would just replace the above i*immSExt* matchers with 996// relocImm-based matchers, but then FastISel would be unable to use them. 997def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ 998 return isSExtRelocImm<8>(N); 999}]>; 1000def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ 1001 return isSExtRelocImm<32>(N); 1002}]>; 1003 1004// If we have multiple users of an immediate, it's much smaller to reuse 1005// the register, rather than encode the immediate in every instruction. 1006// This has the risk of increasing register pressure from stretched live 1007// ranges, however, the immediates should be trivial to rematerialize by 1008// the RA in the event of high register pressure. 1009// TODO : This is currently enabled for stores and binary ops. There are more 1010// cases for which this can be enabled, though this catches the bulk of the 1011// issues. 1012// TODO2 : This should really also be enabled under O2, but there's currently 1013// an issue with RA where we don't pull the constants into their users 1014// when we rematerialize them. I'll follow-up on enabling O2 after we fix that 1015// issue. 1016// TODO3 : This is currently limited to single basic blocks (DAG creation 1017// pulls block immediates to the top and merges them if necessary). 1018// Eventually, it would be nice to allow ConstantHoisting to merge constants 1019// globally for potentially added savings. 1020// 1021def imm8_su : PatLeaf<(i8 relocImm), [{ 1022 return !shouldAvoidImmediateInstFormsForSize(N); 1023}]>; 1024def imm16_su : PatLeaf<(i16 relocImm), [{ 1025 return !shouldAvoidImmediateInstFormsForSize(N); 1026}]>; 1027def imm32_su : PatLeaf<(i32 relocImm), [{ 1028 return !shouldAvoidImmediateInstFormsForSize(N); 1029}]>; 1030def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ 1031 return !shouldAvoidImmediateInstFormsForSize(N); 1032}]>; 1033 1034def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ 1035 return !shouldAvoidImmediateInstFormsForSize(N); 1036}]>; 1037def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ 1038 return !shouldAvoidImmediateInstFormsForSize(N); 1039}]>; 1040def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ 1041 return !shouldAvoidImmediateInstFormsForSize(N); 1042}]>; 1043 1044def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ 1045 return !shouldAvoidImmediateInstFormsForSize(N); 1046}]>; 1047def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ 1048 return !shouldAvoidImmediateInstFormsForSize(N); 1049}]>; 1050 1051// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 1052// unsigned field. 1053def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>; 1054 1055def i64immZExt32SExt8 : ImmLeaf<i64, [{ 1056 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm)); 1057}]>; 1058 1059// Helper fragments for loads. 1060 1061// It's safe to fold a zextload/extload from i1 as a regular i8 load. The 1062// upper bits are guaranteed to be zero and we were going to emit a MOV8rm 1063// which might get folded during peephole anyway. 1064def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ 1065 LoadSDNode *LD = cast<LoadSDNode>(N); 1066 ISD::LoadExtType ExtType = LD->getExtensionType(); 1067 return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || 1068 ExtType == ISD::ZEXTLOAD; 1069}]>; 1070 1071// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 1072// known to be 32-bit aligned or better. Ditto for i8 to i16. 1073def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 1074 LoadSDNode *LD = cast<LoadSDNode>(N); 1075 ISD::LoadExtType ExtType = LD->getExtensionType(); 1076 if (ExtType == ISD::NON_EXTLOAD) 1077 return true; 1078 if (ExtType == ISD::EXTLOAD) 1079 return LD->getAlignment() >= 2 && !LD->isVolatile(); 1080 return false; 1081}]>; 1082 1083def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 1084 LoadSDNode *LD = cast<LoadSDNode>(N); 1085 ISD::LoadExtType ExtType = LD->getExtensionType(); 1086 if (ExtType == ISD::NON_EXTLOAD) 1087 return true; 1088 if (ExtType == ISD::EXTLOAD) 1089 return LD->getAlignment() >= 4 && !LD->isVolatile(); 1090 return false; 1091}]>; 1092 1093def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 1094def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 1095def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 1096def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 1097def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; 1098def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 1099 LoadSDNode *Ld = cast<LoadSDNode>(N); 1100 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1101}]>; 1102def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 1103 LoadSDNode *Ld = cast<LoadSDNode>(N); 1104 return Subtarget->hasSSEUnalignedMem() || 1105 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1106}]>; 1107 1108def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 1109def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 1110def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 1111def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 1112def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 1113def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 1114 1115def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 1116def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 1117def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 1118def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 1119def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 1120def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 1121def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 1122def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 1123def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 1124def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 1125 1126def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 1127def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 1128def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 1129def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 1130def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 1131def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 1132def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 1133def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 1134def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 1135def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 1136 1137 1138// An 'and' node with a single use. 1139def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 1140 return N->hasOneUse(); 1141}]>; 1142// An 'srl' node with a single use. 1143def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 1144 return N->hasOneUse(); 1145}]>; 1146// An 'trunc' node with a single use. 1147def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 1148 return N->hasOneUse(); 1149}]>; 1150 1151//===----------------------------------------------------------------------===// 1152// Instruction list. 1153// 1154 1155// Nop 1156let hasSideEffects = 0, SchedRW = [WriteNop] in { 1157 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; 1158 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 1159 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; 1160 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 1161 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; 1162 def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), 1163 "nop{q}\t$zero", []>, TB, NotMemoryFoldable, 1164 Requires<[In64BitMode]>; 1165 // Also allow register so we can assemble/disassemble 1166 def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), 1167 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; 1168 def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), 1169 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; 1170 def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), 1171 "nop{q}\t$zero", []>, TB, NotMemoryFoldable, 1172 Requires<[In64BitMode]>; 1173 def NOOPW_19 : I<0x19, MRMXm, (outs), (ins i16mem:$zero), 1174 "nop{w}\t$zero", []>, TB, OpSize16; 1175 def NOOPL_19 : I<0x19, MRMXm, (outs), (ins i32mem:$zero), 1176 "nop{l}\t$zero", []>, TB, OpSize32; 1177 //def NOOPW_1a : I<0x1a, MRMXm, (outs), (ins i16mem:$zero), 1178 // "nop{w}\t$zero", []>, TB, OpSize16; 1179 //def NOOPL_1a : I<0x1a, MRMXm, (outs), (ins i32mem:$zero), 1180 // "nop{l}\t$zero", []>, TB, OpSize32; 1181 //def NOOPW_1b : I<0x1b, MRMXm, (outs), (ins i16mem:$zero), 1182 // "nop{w}\t$zero", []>, TB, OpSize16; 1183 //def NOOPL_1b : I<0x1b, MRMXm, (outs), (ins i32mem:$zero), 1184 // "nop{l}\t$zero", []>, TB, OpSize32; 1185 def NOOPW_1c : I<0x1c, MRMXm, (outs), (ins i16mem:$zero), 1186 "nop{w}\t$zero", []>, TB, OpSize16; 1187 //def NOOPL_1c : I<0x1c, MRMXm, (outs), (ins i32mem:$zero), 1188 // "nop{l}\t$zero", []>, TB, OpSize32; 1189 def NOOPW_1d : I<0x1d, MRMXm, (outs), (ins i16mem:$zero), 1190 "nop{w}\t$zero", []>, TB, OpSize16; 1191 def NOOPL_1d : I<0x1d, MRMXm, (outs), (ins i32mem:$zero), 1192 "nop{l}\t$zero", []>, TB, OpSize32; 1193 def NOOPW_1e : I<0x1e, MRMXm, (outs), (ins i16mem:$zero), 1194 "nop{w}\t$zero", []>, TB, OpSize16; 1195 def NOOPL_1e : I<0x1e, MRMXm, (outs), (ins i32mem:$zero), 1196 "nop{l}\t$zero", []>, TB, OpSize32; 1197 1198 def NOOP18_16m4 : I<0x18, MRM4m, (outs), (ins i16mem:$zero), 1199 "nop{w}\t$zero", []>, TB, OpSize16; 1200 def NOOP18_m4 : I<0x18, MRM4m, (outs), (ins i32mem:$zero), 1201 "nop{l}\t$zero", []>, TB, OpSize32; 1202 1203 def NOOP18_16r4 : I<0x18, MRM4r, (outs), (ins GR16:$zero), 1204 "nop{w}\t$zero", []>, TB, OpSize16; 1205 def NOOP18_r4 : I<0x18, MRM4r, (outs), (ins GR32:$zero), 1206 "nop{l}\t$zero", []>, TB, OpSize32; 1207 1208 def NOOP18_16m5 : I<0x18, MRM5m, (outs), (ins i16mem:$zero), 1209 "nop{w}\t$zero", []>, TB, OpSize16; 1210 def NOOP18_m5 : I<0x18, MRM5m, (outs), (ins i32mem:$zero), 1211 "nop{l}\t$zero", []>, TB, OpSize32; 1212 1213 def NOOP18_16r5 : I<0x18, MRM5r, (outs), (ins GR16:$zero), 1214 "nop{w}\t$zero", []>, TB, OpSize16; 1215 def NOOP18_r5 : I<0x18, MRM5r, (outs), (ins GR32:$zero), 1216 "nop{l}\t$zero", []>, TB, OpSize32; 1217 1218 def NOOP18_16m6 : I<0x18, MRM6m, (outs), (ins i16mem:$zero), 1219 "nop{w}\t$zero", []>, TB, OpSize16; 1220 def NOOP18_m6 : I<0x18, MRM6m, (outs), (ins i32mem:$zero), 1221 "nop{l}\t$zero", []>, TB, OpSize32; 1222 1223 def NOOP18_16r6 : I<0x18, MRM6r, (outs), (ins GR16:$zero), 1224 "nop{w}\t$zero", []>, TB, OpSize16; 1225 def NOOP18_r6 : I<0x18, MRM6r, (outs), (ins GR32:$zero), 1226 "nop{l}\t$zero", []>, TB, OpSize32; 1227 1228 def NOOP18_16m7 : I<0x18, MRM7m, (outs), (ins i16mem:$zero), 1229 "nop{w}\t$zero", []>, TB, OpSize16; 1230 def NOOP18_m7 : I<0x18, MRM7m, (outs), (ins i32mem:$zero), 1231 "nop{l}\t$zero", []>, TB, OpSize32; 1232 1233 def NOOP18_16r7 : I<0x18, MRM7r, (outs), (ins GR16:$zero), 1234 "nop{w}\t$zero", []>, TB, OpSize16; 1235 def NOOP18_r7 : I<0x18, MRM7r, (outs), (ins GR32:$zero), 1236 "nop{l}\t$zero", []>, TB, OpSize32; 1237} 1238 1239 1240// Constructing a stack frame. 1241def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 1242 "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; 1243 1244let SchedRW = [WriteALU] in { 1245let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 1246def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 1247 Requires<[Not64BitMode]>; 1248 1249let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 1250def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 1251 Requires<[In64BitMode]>; 1252} // SchedRW 1253 1254//===----------------------------------------------------------------------===// 1255// Miscellaneous Instructions. 1256// 1257 1258let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, 1259 SchedRW = [WriteSystem] in 1260 def Int_eh_sjlj_setup_dispatch 1261 : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; 1262 1263let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 1264let mayLoad = 1, SchedRW = [WriteLoad] in { 1265def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 1266 OpSize16; 1267def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 1268 OpSize32, Requires<[Not64BitMode]>; 1269// Long form for the disassembler. 1270let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1271def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 1272 OpSize16, NotMemoryFoldable; 1273def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 1274 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; 1275} // isCodeGenOnly = 1, ForceDisassemble = 1 1276} // mayLoad, SchedRW 1277let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in { 1278def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, 1279 OpSize16; 1280def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, 1281 OpSize32, Requires<[Not64BitMode]>; 1282} // mayStore, mayLoad, WriteRMW 1283 1284let mayStore = 1, SchedRW = [WriteStore] in { 1285def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 1286 OpSize16; 1287def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 1288 OpSize32, Requires<[Not64BitMode]>; 1289// Long form for the disassembler. 1290let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1291def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 1292 OpSize16, NotMemoryFoldable; 1293def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 1294 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; 1295} // isCodeGenOnly = 1, ForceDisassemble = 1 1296 1297def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 1298 "push{w}\t$imm", []>, OpSize16; 1299def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1300 "push{w}\t$imm", []>, OpSize16; 1301 1302def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 1303 "push{l}\t$imm", []>, OpSize32, 1304 Requires<[Not64BitMode]>; 1305def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 1306 "push{l}\t$imm", []>, OpSize32, 1307 Requires<[Not64BitMode]>; 1308} // mayStore, SchedRW 1309 1310let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { 1311def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, 1312 OpSize16; 1313def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, 1314 OpSize32, Requires<[Not64BitMode]>; 1315} // mayLoad, mayStore, SchedRW 1316 1317} 1318 1319let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, 1320 SchedRW = [WriteRMW], Defs = [ESP] in { 1321 let Uses = [ESP] in 1322 def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), 1323 [(set GR32:$dst, (int_x86_flags_read_u32))]>, 1324 Requires<[Not64BitMode]>; 1325 1326 let Uses = [RSP] in 1327 def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), 1328 [(set GR64:$dst, (int_x86_flags_read_u64))]>, 1329 Requires<[In64BitMode]>; 1330} 1331 1332let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, 1333 SchedRW = [WriteRMW] in { 1334 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in 1335 def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), 1336 [(int_x86_flags_write_u32 GR32:$src)]>, 1337 Requires<[Not64BitMode]>; 1338 1339 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in 1340 def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), 1341 [(int_x86_flags_write_u64 GR64:$src)]>, 1342 Requires<[In64BitMode]>; 1343} 1344 1345let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 1346 SchedRW = [WriteLoad] in { 1347def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; 1348def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, 1349 Requires<[Not64BitMode]>; 1350} 1351 1352let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, 1353 SchedRW = [WriteStore] in { 1354def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; 1355def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, 1356 Requires<[Not64BitMode]>; 1357} 1358 1359let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 1360let mayLoad = 1, SchedRW = [WriteLoad] in { 1361def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 1362 OpSize32, Requires<[In64BitMode]>; 1363// Long form for the disassembler. 1364let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1365def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 1366 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; 1367} // isCodeGenOnly = 1, ForceDisassemble = 1 1368} // mayLoad, SchedRW 1369let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in 1370def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, 1371 OpSize32, Requires<[In64BitMode]>; 1372let mayStore = 1, SchedRW = [WriteStore] in { 1373def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 1374 OpSize32, Requires<[In64BitMode]>; 1375// Long form for the disassembler. 1376let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1377def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 1378 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; 1379} // isCodeGenOnly = 1, ForceDisassemble = 1 1380} // mayStore, SchedRW 1381let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in { 1382def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, 1383 OpSize32, Requires<[In64BitMode]>; 1384} // mayLoad, mayStore, SchedRW 1385} 1386 1387let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 1388 SchedRW = [WriteStore] in { 1389def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1390 "push{q}\t$imm", []>, OpSize32, 1391 Requires<[In64BitMode]>; 1392def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1393 "push{q}\t$imm", []>, OpSize32, 1394 Requires<[In64BitMode]>; 1395} 1396 1397let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 1398def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, 1399 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1400let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in 1401def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, 1402 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1403 1404let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1405 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 1406def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, 1407 OpSize32, Requires<[Not64BitMode]>; 1408def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, 1409 OpSize16, Requires<[Not64BitMode]>; 1410} 1411let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1412 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 1413def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, 1414 OpSize32, Requires<[Not64BitMode]>; 1415def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, 1416 OpSize16, Requires<[Not64BitMode]>; 1417} 1418 1419let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { 1420// This instruction is a consequence of BSWAP32r observing operand size. The 1421// encoding is valid, but the behavior is undefined. 1422let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in 1423def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 1424 "bswap{w}\t$dst", []>, OpSize16, TB; 1425// GR32 = bswap GR32 1426def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 1427 "bswap{l}\t$dst", 1428 [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; 1429 1430let SchedRW = [WriteBSWAP64] in 1431def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1432 "bswap{q}\t$dst", 1433 [(set GR64:$dst, (bswap GR64:$src))]>, TB; 1434} // Constraints = "$src = $dst", SchedRW 1435 1436// Bit scan instructions. 1437let Defs = [EFLAGS] in { 1438def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1439 "bsf{w}\t{$src, $dst|$dst, $src}", 1440 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, 1441 PS, OpSize16, Sched<[WriteBSF]>; 1442def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1443 "bsf{w}\t{$src, $dst|$dst, $src}", 1444 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, 1445 PS, OpSize16, Sched<[WriteBSFLd]>; 1446def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1447 "bsf{l}\t{$src, $dst|$dst, $src}", 1448 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, 1449 PS, OpSize32, Sched<[WriteBSF]>; 1450def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1451 "bsf{l}\t{$src, $dst|$dst, $src}", 1452 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, 1453 PS, OpSize32, Sched<[WriteBSFLd]>; 1454def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1455 "bsf{q}\t{$src, $dst|$dst, $src}", 1456 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, 1457 PS, Sched<[WriteBSF]>; 1458def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1459 "bsf{q}\t{$src, $dst|$dst, $src}", 1460 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, 1461 PS, Sched<[WriteBSFLd]>; 1462 1463def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1464 "bsr{w}\t{$src, $dst|$dst, $src}", 1465 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, 1466 PS, OpSize16, Sched<[WriteBSR]>; 1467def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1468 "bsr{w}\t{$src, $dst|$dst, $src}", 1469 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, 1470 PS, OpSize16, Sched<[WriteBSRLd]>; 1471def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1472 "bsr{l}\t{$src, $dst|$dst, $src}", 1473 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, 1474 PS, OpSize32, Sched<[WriteBSR]>; 1475def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1476 "bsr{l}\t{$src, $dst|$dst, $src}", 1477 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, 1478 PS, OpSize32, Sched<[WriteBSRLd]>; 1479def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1480 "bsr{q}\t{$src, $dst|$dst, $src}", 1481 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, 1482 PS, Sched<[WriteBSR]>; 1483def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1484 "bsr{q}\t{$src, $dst|$dst, $src}", 1485 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, 1486 PS, Sched<[WriteBSRLd]>; 1487} // Defs = [EFLAGS] 1488 1489let SchedRW = [WriteMicrocoded] in { 1490let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { 1491def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1492 "movsb\t{$src, $dst|$dst, $src}", []>; 1493def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1494 "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; 1495def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1496 "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; 1497def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1498 "movsq\t{$src, $dst|$dst, $src}", []>, 1499 Requires<[In64BitMode]>; 1500} 1501 1502let Defs = [EDI], Uses = [AL,EDI,DF] in 1503def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), 1504 "stosb\t{%al, $dst|$dst, al}", []>; 1505let Defs = [EDI], Uses = [AX,EDI,DF] in 1506def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), 1507 "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; 1508let Defs = [EDI], Uses = [EAX,EDI,DF] in 1509def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), 1510 "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; 1511let Defs = [RDI], Uses = [RAX,RDI,DF] in 1512def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), 1513 "stosq\t{%rax, $dst|$dst, rax}", []>, 1514 Requires<[In64BitMode]>; 1515 1516let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in 1517def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1518 "scasb\t{$dst, %al|al, $dst}", []>; 1519let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in 1520def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1521 "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; 1522let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in 1523def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1524 "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; 1525let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in 1526def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1527 "scasq\t{$dst, %rax|rax, $dst}", []>, 1528 Requires<[In64BitMode]>; 1529 1530let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { 1531def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1532 "cmpsb\t{$dst, $src|$src, $dst}", []>; 1533def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1534 "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; 1535def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1536 "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; 1537def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1538 "cmpsq\t{$dst, $src|$src, $dst}", []>, 1539 Requires<[In64BitMode]>; 1540} 1541} // SchedRW 1542 1543//===----------------------------------------------------------------------===// 1544// Move Instructions. 1545// 1546let SchedRW = [WriteMove] in { 1547let hasSideEffects = 0, isMoveReg = 1 in { 1548def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1549 "mov{b}\t{$src, $dst|$dst, $src}", []>; 1550def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1551 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 1552def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1553 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 1554def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1555 "mov{q}\t{$src, $dst|$dst, $src}", []>; 1556} 1557 1558let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1559def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1560 "mov{b}\t{$src, $dst|$dst, $src}", 1561 [(set GR8:$dst, imm:$src)]>; 1562def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1563 "mov{w}\t{$src, $dst|$dst, $src}", 1564 [(set GR16:$dst, imm:$src)]>, OpSize16; 1565def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1566 "mov{l}\t{$src, $dst|$dst, $src}", 1567 [(set GR32:$dst, relocImm:$src)]>, OpSize32; 1568def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1569 "mov{q}\t{$src, $dst|$dst, $src}", 1570 [(set GR64:$dst, i64immSExt32:$src)]>; 1571} 1572let isReMaterializable = 1 in { 1573def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1574 "movabs{q}\t{$src, $dst|$dst, $src}", 1575 [(set GR64:$dst, relocImm:$src)]>; 1576} 1577 1578// Longer forms that use a ModR/M byte. Needed for disassembler 1579let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1580def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1581 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1582 FoldGenData<"MOV8ri">; 1583def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1584 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 1585 FoldGenData<"MOV16ri">; 1586def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1587 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 1588 FoldGenData<"MOV32ri">; 1589} 1590} // SchedRW 1591 1592let SchedRW = [WriteStore] in { 1593def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1594 "mov{b}\t{$src, $dst|$dst, $src}", 1595 [(store (i8 imm8_su:$src), addr:$dst)]>; 1596def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1597 "mov{w}\t{$src, $dst|$dst, $src}", 1598 [(store (i16 imm16_su:$src), addr:$dst)]>, OpSize16; 1599def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1600 "mov{l}\t{$src, $dst|$dst, $src}", 1601 [(store (i32 imm32_su:$src), addr:$dst)]>, OpSize32; 1602def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1603 "mov{q}\t{$src, $dst|$dst, $src}", 1604 [(store i64immSExt32_su:$src, addr:$dst)]>, 1605 Requires<[In64BitMode]>; 1606} // SchedRW 1607 1608let hasSideEffects = 0 in { 1609 1610/// Memory offset versions of moves. The immediate is an address mode sized 1611/// offset from the segment base. 1612let SchedRW = [WriteALU] in { 1613let mayLoad = 1 in { 1614let Defs = [AL] in 1615def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 1616 "mov{b}\t{$src, %al|al, $src}", []>, 1617 AdSize32; 1618let Defs = [AX] in 1619def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 1620 "mov{w}\t{$src, %ax|ax, $src}", []>, 1621 OpSize16, AdSize32; 1622let Defs = [EAX] in 1623def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 1624 "mov{l}\t{$src, %eax|eax, $src}", []>, 1625 OpSize32, AdSize32; 1626let Defs = [RAX] in 1627def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 1628 "mov{q}\t{$src, %rax|rax, $src}", []>, 1629 AdSize32; 1630 1631let Defs = [AL] in 1632def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 1633 "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; 1634let Defs = [AX] in 1635def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 1636 "mov{w}\t{$src, %ax|ax, $src}", []>, 1637 OpSize16, AdSize16; 1638let Defs = [EAX] in 1639def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 1640 "mov{l}\t{$src, %eax|eax, $src}", []>, 1641 AdSize16, OpSize32; 1642} // mayLoad 1643let mayStore = 1 in { 1644let Uses = [AL] in 1645def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), 1646 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; 1647let Uses = [AX] in 1648def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), 1649 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 1650 OpSize16, AdSize32; 1651let Uses = [EAX] in 1652def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), 1653 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 1654 OpSize32, AdSize32; 1655let Uses = [RAX] in 1656def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), 1657 "mov{q}\t{%rax, $dst|$dst, rax}", []>, 1658 AdSize32; 1659 1660let Uses = [AL] in 1661def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), 1662 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; 1663let Uses = [AX] in 1664def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), 1665 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 1666 OpSize16, AdSize16; 1667let Uses = [EAX] in 1668def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), 1669 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 1670 OpSize32, AdSize16; 1671} // mayStore 1672 1673// These forms all have full 64-bit absolute addresses in their instructions 1674// and use the movabs mnemonic to indicate this specific form. 1675let mayLoad = 1 in { 1676let Defs = [AL] in 1677def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 1678 "movabs{b}\t{$src, %al|al, $src}", []>, 1679 AdSize64; 1680let Defs = [AX] in 1681def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 1682 "movabs{w}\t{$src, %ax|ax, $src}", []>, 1683 OpSize16, AdSize64; 1684let Defs = [EAX] in 1685def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 1686 "movabs{l}\t{$src, %eax|eax, $src}", []>, 1687 OpSize32, AdSize64; 1688let Defs = [RAX] in 1689def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 1690 "movabs{q}\t{$src, %rax|rax, $src}", []>, 1691 AdSize64; 1692} // mayLoad 1693 1694let mayStore = 1 in { 1695let Uses = [AL] in 1696def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), 1697 "movabs{b}\t{%al, $dst|$dst, al}", []>, 1698 AdSize64; 1699let Uses = [AX] in 1700def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), 1701 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, 1702 OpSize16, AdSize64; 1703let Uses = [EAX] in 1704def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), 1705 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, 1706 OpSize32, AdSize64; 1707let Uses = [RAX] in 1708def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), 1709 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, 1710 AdSize64; 1711} // mayStore 1712} // SchedRW 1713} // hasSideEffects = 0 1714 1715let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1716 SchedRW = [WriteMove], isMoveReg = 1 in { 1717def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1718 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1719 FoldGenData<"MOV8rr">; 1720def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1721 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 1722 FoldGenData<"MOV16rr">; 1723def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1724 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 1725 FoldGenData<"MOV32rr">; 1726def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1727 "mov{q}\t{$src, $dst|$dst, $src}", []>, 1728 FoldGenData<"MOV64rr">; 1729} 1730 1731// Reversed version with ".s" suffix for GAS compatibility. 1732//def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", 1733// (MOV8rr_REV GR8:$dst, GR8:$src), 0>; 1734//def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", 1735// (MOV16rr_REV GR16:$dst, GR16:$src), 0>; 1736//def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", 1737// (MOV32rr_REV GR32:$dst, GR32:$src), 0>; 1738//def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", 1739// (MOV64rr_REV GR64:$dst, GR64:$src), 0>; 1740//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1741// (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; 1742//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1743// (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; 1744//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1745// (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; 1746//def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1747// (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; 1748 1749let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1750def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1751 "mov{b}\t{$src, $dst|$dst, $src}", 1752 [(set GR8:$dst, (loadi8 addr:$src))]>; 1753def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1754 "mov{w}\t{$src, $dst|$dst, $src}", 1755 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; 1756def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1757 "mov{l}\t{$src, $dst|$dst, $src}", 1758 [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; 1759def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1760 "mov{q}\t{$src, $dst|$dst, $src}", 1761 [(set GR64:$dst, (load addr:$src))]>; 1762} 1763 1764let SchedRW = [WriteStore] in { 1765def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1766 "mov{b}\t{$src, $dst|$dst, $src}", 1767 [(store GR8:$src, addr:$dst)]>; 1768def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1769 "mov{w}\t{$src, $dst|$dst, $src}", 1770 [(store GR16:$src, addr:$dst)]>, OpSize16; 1771def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1772 "mov{l}\t{$src, $dst|$dst, $src}", 1773 [(store GR32:$src, addr:$dst)]>, OpSize32; 1774def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1775 "mov{q}\t{$src, $dst|$dst, $src}", 1776 [(store GR64:$src, addr:$dst)]>; 1777} // SchedRW 1778 1779// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1780// that they can be used for copying and storing h registers, which can't be 1781// encoded when a REX prefix is present. 1782let isCodeGenOnly = 1 in { 1783let hasSideEffects = 0, isMoveReg = 1 in 1784def MOV8rr_NOREX : I<0x88, MRMDestReg, 1785 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1786 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1787 Sched<[WriteMove]>; 1788let mayStore = 1, hasSideEffects = 0 in 1789def MOV8mr_NOREX : I<0x88, MRMDestMem, 1790 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1791 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1792 Sched<[WriteStore]>; 1793let mayLoad = 1, hasSideEffects = 0, 1794 canFoldAsLoad = 1, isReMaterializable = 1 in 1795def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1796 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1797 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1798 Sched<[WriteLoad]>; 1799} 1800 1801 1802// Condition code ops, incl. set if equal/not equal/... 1803let SchedRW = [WriteLAHFSAHF] in { 1804let Defs = [EFLAGS], Uses = [AH] in 1805def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1806 [(set EFLAGS, (X86sahf AH))]>, 1807 Requires<[HasLAHFSAHF]>; 1808let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 1809def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags 1810 Requires<[HasLAHFSAHF]>; 1811} // SchedRW 1812 1813//===----------------------------------------------------------------------===// 1814// Bit tests instructions: BT, BTS, BTR, BTC. 1815 1816let Defs = [EFLAGS] in { 1817let SchedRW = [WriteBitTest] in { 1818def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1819 "bt{w}\t{$src2, $src1|$src1, $src2}", 1820 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, 1821 OpSize16, TB, NotMemoryFoldable; 1822def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1823 "bt{l}\t{$src2, $src1|$src1, $src2}", 1824 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, 1825 OpSize32, TB, NotMemoryFoldable; 1826def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1827 "bt{q}\t{$src2, $src1|$src1, $src2}", 1828 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, 1829 NotMemoryFoldable; 1830} // SchedRW 1831 1832// Unlike with the register+register form, the memory+register form of the 1833// bt instruction does not ignore the high bits of the index. From ISel's 1834// perspective, this is pretty bizarre. Make these instructions disassembly 1835// only for now. These instructions are also slow on modern CPUs so that's 1836// another reason to avoid generating them. 1837 1838let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1839 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1840 "bt{w}\t{$src2, $src1|$src1, $src2}", 1841 []>, OpSize16, TB, NotMemoryFoldable; 1842 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1843 "bt{l}\t{$src2, $src1|$src1, $src2}", 1844 []>, OpSize32, TB, NotMemoryFoldable; 1845 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1846 "bt{q}\t{$src2, $src1|$src1, $src2}", 1847 []>, TB, NotMemoryFoldable; 1848} 1849 1850let SchedRW = [WriteBitTest] in { 1851def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1852 "bt{w}\t{$src2, $src1|$src1, $src2}", 1853 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, 1854 OpSize16, TB; 1855def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1856 "bt{l}\t{$src2, $src1|$src1, $src2}", 1857 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, 1858 OpSize32, TB; 1859def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1860 "bt{q}\t{$src2, $src1|$src1, $src2}", 1861 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; 1862} // SchedRW 1863 1864// Note that these instructions aren't slow because that only applies when the 1865// other operand is in a register. When it's an immediate, bt is still fast. 1866let SchedRW = [WriteALU] in { 1867def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1868 "bt{w}\t{$src2, $src1|$src1, $src2}", 1869 [(set EFLAGS, (X86bt (loadi16 addr:$src1), 1870 i16immSExt8:$src2))]>, 1871 OpSize16, TB; 1872def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1873 "bt{l}\t{$src2, $src1|$src1, $src2}", 1874 [(set EFLAGS, (X86bt (loadi32 addr:$src1), 1875 i32immSExt8:$src2))]>, 1876 OpSize32, TB; 1877def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1878 "bt{q}\t{$src2, $src1|$src1, $src2}", 1879 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1880 i64immSExt8:$src2))]>, TB, 1881 Requires<[In64BitMode]>; 1882} // SchedRW 1883 1884let hasSideEffects = 0 in { 1885let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1886def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1887 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 1888 OpSize16, TB, NotMemoryFoldable; 1889def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1890 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 1891 OpSize32, TB, NotMemoryFoldable; 1892def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1893 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1894 NotMemoryFoldable; 1895} // SchedRW 1896 1897let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1898def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1899 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 1900 OpSize16, TB, NotMemoryFoldable; 1901def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1902 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 1903 OpSize32, TB, NotMemoryFoldable; 1904def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1905 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1906 NotMemoryFoldable; 1907} 1908 1909let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1910def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1911 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 1912def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1913 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 1914def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1915 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1916} // SchedRW 1917 1918let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1919def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1920 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 1921def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1922 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 1923def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1924 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1925 Requires<[In64BitMode]>; 1926} 1927 1928let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1929def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1930 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1931 OpSize16, TB, NotMemoryFoldable; 1932def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1933 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1934 OpSize32, TB, NotMemoryFoldable; 1935def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1936 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1937 NotMemoryFoldable; 1938} // SchedRW 1939 1940let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1941def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1942 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1943 OpSize16, TB, NotMemoryFoldable; 1944def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1945 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1946 OpSize32, TB, NotMemoryFoldable; 1947def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1948 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1949 NotMemoryFoldable; 1950} 1951 1952let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1953def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1954 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1955 OpSize16, TB; 1956def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1957 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1958 OpSize32, TB; 1959def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1960 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1961} // SchedRW 1962 1963let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1964def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1965 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1966 OpSize16, TB; 1967def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1968 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1969 OpSize32, TB; 1970def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1971 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1972 Requires<[In64BitMode]>; 1973} 1974 1975let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 1976def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1977 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 1978 OpSize16, TB, NotMemoryFoldable; 1979def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1980 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 1981 OpSize32, TB, NotMemoryFoldable; 1982def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1983 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1984 NotMemoryFoldable; 1985} // SchedRW 1986 1987let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1988def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1989 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 1990 OpSize16, TB, NotMemoryFoldable; 1991def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1992 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 1993 OpSize32, TB, NotMemoryFoldable; 1994def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1995 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1996 NotMemoryFoldable; 1997} 1998 1999let SchedRW = [WriteBitTest], Constraints = "$src1 = $dst" in { 2000def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 2001 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 2002def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 2003 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 2004def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 2005 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2006} // SchedRW 2007 2008let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 2009def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 2010 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 2011def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 2012 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 2013def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 2014 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2015 Requires<[In64BitMode]>; 2016} 2017} // hasSideEffects = 0 2018} // Defs = [EFLAGS] 2019 2020 2021//===----------------------------------------------------------------------===// 2022// Atomic support 2023// 2024 2025// Atomic swap. These are just normal xchg instructions. But since a memory 2026// operand is referenced, the atomicity is ensured. 2027multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag> { 2028 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 2029 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 2030 (ins GR8:$val, i8mem:$ptr), 2031 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 2032 [(set 2033 GR8:$dst, 2034 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 2035 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 2036 (ins GR16:$val, i16mem:$ptr), 2037 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 2038 [(set 2039 GR16:$dst, 2040 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 2041 OpSize16; 2042 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 2043 (ins GR32:$val, i32mem:$ptr), 2044 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 2045 [(set 2046 GR32:$dst, 2047 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 2048 OpSize32; 2049 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 2050 (ins GR64:$val, i64mem:$ptr), 2051 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 2052 [(set 2053 GR64:$dst, 2054 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 2055 } 2056} 2057 2058defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable; 2059 2060// Swap between registers. 2061let SchedRW = [WriteALU] in { 2062let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { 2063def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), 2064 (ins GR8:$src1, GR8:$src2), 2065 "xchg{b}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; 2066def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), 2067 (ins GR16:$src1, GR16:$src2), 2068 "xchg{w}\t{$src1, $src2|$src2, $src1}", []>, 2069 OpSize16, NotMemoryFoldable; 2070def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), 2071 (ins GR32:$src1, GR32:$src2), 2072 "xchg{l}\t{$src1, $src2|$src2, $src1}", []>, 2073 OpSize32, NotMemoryFoldable; 2074def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), 2075 (ins GR64:$src1 ,GR64:$src2), 2076 "xchg{q}\t{$src1, $src2|$src2, $src1}", []>, NotMemoryFoldable; 2077} 2078 2079def NOOP19rr: I<0x19, MRMSrcReg, (outs), (ins GR32:$val, GR32:$src), 2080 "nop\t{$val, $src|$src, $val}", []>, TB, 2081 OpSize32; 2082 2083// Swap between EAX and other registers. 2084let Constraints = "$src = $dst", hasSideEffects = 0 in { 2085let Uses = [AX], Defs = [AX] in 2086def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 2087 "xchg{w}\t{%ax, $src|$src, ax}", []>, OpSize16; 2088let Uses = [EAX], Defs = [EAX] in 2089def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 2090 "xchg{l}\t{%eax, $src|$src, eax}", []>, OpSize32; 2091let Uses = [RAX], Defs = [RAX] in 2092def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 2093 "xchg{q}\t{%rax, $src|$src, rax}", []>; 2094} 2095} // SchedRW 2096 2097let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", 2098 Defs = [EFLAGS], SchedRW = [WriteALU] in { 2099def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), 2100 (ins GR8:$src1, GR8:$src2), 2101 "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; 2102def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), 2103 (ins GR16:$src1, GR16:$src2), 2104 "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; 2105def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), 2106 (ins GR32:$src1, GR32:$src2), 2107 "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; 2108def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), 2109 (ins GR64:$src1, GR64:$src2), 2110 "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2111} // SchedRW 2112 2113let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", 2114 Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { 2115def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), 2116 (ins GR8:$val, i8mem:$ptr), 2117 "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; 2118def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), 2119 (ins GR16:$val, i16mem:$ptr), 2120 "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, 2121 OpSize16; 2122def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), 2123 (ins GR32:$val, i32mem:$ptr), 2124 "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, 2125 OpSize32; 2126def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), 2127 (ins GR64:$val, i64mem:$ptr), 2128 "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; 2129 2130} 2131 2132let SchedRW = [WriteALU], hasSideEffects = 0 in { 2133let Defs = [AL, EFLAGS], Uses = [AL] in 2134def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 2135 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, 2136 NotMemoryFoldable; 2137let Defs = [AX, EFLAGS], Uses = [AX] in 2138def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 2139 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, 2140 NotMemoryFoldable; 2141let Defs = [EAX, EFLAGS], Uses = [EAX] in 2142def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 2143 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, 2144 NotMemoryFoldable; 2145let Defs = [RAX, EFLAGS], Uses = [RAX] in 2146def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 2147 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, 2148 NotMemoryFoldable; 2149} // SchedRW, hasSideEffects 2150 2151let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1, 2152 hasSideEffects = 0 in { 2153let Defs = [AL, EFLAGS], Uses = [AL] in 2154def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 2155 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, 2156 NotMemoryFoldable; 2157let Defs = [AX, EFLAGS], Uses = [AX] in 2158def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2159 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, 2160 NotMemoryFoldable; 2161let Defs = [EAX, EFLAGS], Uses = [EAX] in 2162def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2163 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, 2164 NotMemoryFoldable; 2165let Defs = [RAX, EFLAGS], Uses = [RAX] in 2166def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2167 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, 2168 NotMemoryFoldable; 2169 2170let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 2171def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 2172 "cmpxchg8b\t$dst", []>, TB; 2173 2174let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 2175def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 2176 "cmpxchg16b\t$dst", []>, 2177 TB, Requires<[HasCmpxchg16b, In64BitMode]>; 2178} // SchedRW, mayLoad, mayStore, hasSideEffects 2179 2180 2181// Lock instruction prefix 2182let SchedRW = [WriteMicrocoded] in 2183def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 2184 2185let SchedRW = [WriteNop] in { 2186 2187// Rex64 instruction prefix 2188def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, 2189 Requires<[In64BitMode]>; 2190 2191// Data16 instruction prefix 2192def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 2193} // SchedRW 2194 2195// Repeat string operation instruction prefixes 2196let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { 2197// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 2198def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 2199// Repeat while not equal (used with CMPS and SCAS) 2200def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 2201} 2202 2203// String manipulation instructions 2204let SchedRW = [WriteMicrocoded] in { 2205let Defs = [AL,ESI], Uses = [ESI,DF] in 2206def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 2207 "lodsb\t{$src, %al|al, $src}", []>; 2208let Defs = [AX,ESI], Uses = [ESI,DF] in 2209def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 2210 "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; 2211let Defs = [EAX,ESI], Uses = [ESI,DF] in 2212def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 2213 "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; 2214let Defs = [RAX,ESI], Uses = [ESI,DF] in 2215def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 2216 "lodsq\t{$src, %rax|rax, $src}", []>, 2217 Requires<[In64BitMode]>; 2218} 2219 2220let SchedRW = [WriteSystem] in { 2221let Defs = [ESI], Uses = [DX,ESI,DF] in { 2222def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 2223 "outsb\t{$src, %dx|dx, $src}", []>; 2224def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 2225 "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; 2226def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 2227 "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; 2228} 2229 2230let Defs = [EDI], Uses = [DX,EDI,DF] in { 2231def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), 2232 "insb\t{%dx, $dst|$dst, dx}", []>; 2233def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), 2234 "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; 2235def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), 2236 "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; 2237} 2238} 2239 2240// EFLAGS management instructions. 2241let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { 2242def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; 2243def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; 2244def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; 2245} 2246 2247// DF management instructions. 2248let SchedRW = [WriteALU], Defs = [DF] in { 2249def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; 2250def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; 2251} 2252 2253// Table lookup instructions 2254let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in 2255def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; 2256 2257let SchedRW = [WriteMicrocoded] in { 2258// ASCII Adjust After Addition 2259let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2260def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, 2261 Requires<[Not64BitMode]>; 2262 2263// ASCII Adjust AX Before Division 2264let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2265def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 2266 "aad\t$src", []>, Requires<[Not64BitMode]>; 2267 2268// ASCII Adjust AX After Multiply 2269let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2270def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 2271 "aam\t$src", []>, Requires<[Not64BitMode]>; 2272 2273// ASCII Adjust AL After Subtraction - sets 2274let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2275def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, 2276 Requires<[Not64BitMode]>; 2277 2278// Decimal Adjust AL after Addition 2279let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 2280def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, 2281 Requires<[Not64BitMode]>; 2282 2283// Decimal Adjust AL after Subtraction 2284let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 2285def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, 2286 Requires<[Not64BitMode]>; 2287} // SchedRW 2288 2289let SchedRW = [WriteSystem] in { 2290// Check Array Index Against Bounds 2291// Note: "bound" does not have reversed operands in at&t syntax. 2292def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), 2293 "bound\t$dst, $src", []>, OpSize16, 2294 Requires<[Not64BitMode]>; 2295def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i64mem:$src), 2296 "bound\t$dst, $src", []>, OpSize32, 2297 Requires<[Not64BitMode]>; 2298 2299// Adjust RPL Field of Segment Selector 2300def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 2301 "arpl\t{$src, $dst|$dst, $src}", []>, 2302 Requires<[Not64BitMode]>, NotMemoryFoldable; 2303let mayStore = 1 in 2304def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2305 "arpl\t{$src, $dst|$dst, $src}", []>, 2306 Requires<[Not64BitMode]>, NotMemoryFoldable; 2307} // SchedRW 2308 2309//===----------------------------------------------------------------------===// 2310// MOVBE Instructions 2311// 2312let Predicates = [HasMOVBE] in { 2313 let SchedRW = [WriteALULd] in { 2314 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2315 "movbe{w}\t{$src, $dst|$dst, $src}", 2316 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, 2317 OpSize16, T8PS; 2318 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2319 "movbe{l}\t{$src, $dst|$dst, $src}", 2320 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, 2321 OpSize32, T8PS; 2322 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2323 "movbe{q}\t{$src, $dst|$dst, $src}", 2324 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, 2325 T8PS; 2326 } 2327 let SchedRW = [WriteStore] in { 2328 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2329 "movbe{w}\t{$src, $dst|$dst, $src}", 2330 [(store (bswap GR16:$src), addr:$dst)]>, 2331 OpSize16, T8PS; 2332 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2333 "movbe{l}\t{$src, $dst|$dst, $src}", 2334 [(store (bswap GR32:$src), addr:$dst)]>, 2335 OpSize32, T8PS; 2336 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2337 "movbe{q}\t{$src, $dst|$dst, $src}", 2338 [(store (bswap GR64:$src), addr:$dst)]>, 2339 T8PS; 2340 } 2341} 2342 2343//===----------------------------------------------------------------------===// 2344// RDRAND Instruction 2345// 2346let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 2347 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 2348 "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, 2349 OpSize16, PS; 2350 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 2351 "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, 2352 OpSize32, PS; 2353 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 2354 "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, 2355 PS; 2356} 2357 2358//===----------------------------------------------------------------------===// 2359// RDSEED Instruction 2360// 2361let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 2362 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", 2363 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; 2364 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", 2365 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; 2366 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", 2367 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; 2368} 2369 2370//===----------------------------------------------------------------------===// 2371// LZCNT Instruction 2372// 2373let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 2374 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2375 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2376 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, 2377 XS, OpSize16, Sched<[WriteLZCNT]>; 2378 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2379 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2380 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 2381 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; 2382 2383 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2384 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2385 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, 2386 XS, OpSize32, Sched<[WriteLZCNT]>; 2387 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2388 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2389 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 2390 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; 2391 2392 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2393 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2394 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 2395 XS, Sched<[WriteLZCNT]>; 2396 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2397 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2398 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2399 (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; 2400} 2401 2402//===----------------------------------------------------------------------===// 2403// BMI Instructions 2404// 2405let Predicates = [HasBMI], Defs = [EFLAGS] in { 2406 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2407 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2408 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, 2409 XS, OpSize16, Sched<[WriteTZCNT]>; 2410 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2411 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2412 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2413 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; 2414 2415 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2416 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2417 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, 2418 XS, OpSize32, Sched<[WriteTZCNT]>; 2419 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2420 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2421 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2422 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; 2423 2424 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2425 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2426 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2427 XS, Sched<[WriteTZCNT]>; 2428 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2429 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2430 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2431 (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; 2432} 2433 2434multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2435 RegisterClass RC, X86MemOperand x86memop> { 2436let hasSideEffects = 0 in { 2437 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2438 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 2439 T8PS, VEX_4V, Sched<[WriteALU]>; 2440 let mayLoad = 1 in 2441 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2442 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 2443 T8PS, VEX_4V, Sched<[WriteALULd]>; 2444} 2445} 2446 2447let Predicates = [HasBMI], Defs = [EFLAGS] in { 2448 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2449 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; 2450 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; 2451 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; 2452 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; 2453 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; 2454} 2455 2456//===----------------------------------------------------------------------===// 2457// Pattern fragments to auto generate BMI instructions. 2458//===----------------------------------------------------------------------===// 2459 2460let Predicates = [HasBMI] in { 2461 // FIXME: patterns for the load versions are not implemented 2462 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2463 (BLSR32rr GR32:$src)>; 2464 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2465 (BLSR64rr GR64:$src)>; 2466 2467 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2468 (BLSMSK32rr GR32:$src)>; 2469 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2470 (BLSMSK64rr GR64:$src)>; 2471 2472 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2473 (BLSI32rr GR32:$src)>; 2474 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2475 (BLSI64rr GR64:$src)>; 2476} 2477 2478multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC, 2479 X86MemOperand x86memop, SDNode OpNode, 2480 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 2481 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2482 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2483 [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2484 T8PS, VEX, Sched<[Sched]>; 2485 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2486 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2487 [(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)), 2488 (implicit EFLAGS)]>, T8PS, VEX, 2489 Sched<[Sched.Folded, 2490 // x86memop:$src1 2491 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 2492 ReadDefault, 2493 // RC:$src2 2494 ReadAfterLd]>; 2495} 2496 2497let Predicates = [HasBMI], Defs = [EFLAGS] in { 2498 defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, 2499 X86bextr, loadi32, WriteBEXTR>; 2500 defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, 2501 X86bextr, loadi64, WriteBEXTR>, VEX_W; 2502} 2503 2504multiclass bmi_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2505 X86MemOperand x86memop, Intrinsic Int, 2506 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 2507 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2508 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2509 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2510 T8PS, VEX, Sched<[Sched]>; 2511 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2512 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2513 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2514 (implicit EFLAGS)]>, T8PS, VEX, 2515 Sched<[Sched.Folded, 2516 // x86memop:$src1 2517 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 2518 ReadDefault, 2519 // RC:$src2 2520 ReadAfterLd]>; 2521} 2522 2523let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2524 defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2525 int_x86_bmi_bzhi_32, loadi32, WriteBZHI>; 2526 defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2527 int_x86_bmi_bzhi_64, loadi64, WriteBZHI>, VEX_W; 2528} 2529 2530def CountTrailingOnes : SDNodeXForm<imm, [{ 2531 // Count the trailing ones in the immediate. 2532 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N)); 2533}]>; 2534 2535def BEXTRMaskXForm : SDNodeXForm<imm, [{ 2536 unsigned Length = countTrailingOnes(N->getZExtValue()); 2537 return getI32Imm(Length << 8, SDLoc(N)); 2538}]>; 2539 2540def AndMask64 : ImmLeaf<i64, [{ 2541 return isMask_64(Imm) && !isUInt<32>(Imm); 2542}]>; 2543 2544// Use BEXTR for 64-bit 'and' with large immediate 'mask'. 2545let Predicates = [HasBMI, NoBMI2, NoTBM] in { 2546 def : Pat<(and GR64:$src, AndMask64:$mask), 2547 (BEXTR64rr GR64:$src, 2548 (SUBREG_TO_REG (i64 0), 2549 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 2550 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2551 (BEXTR64rm addr:$src, 2552 (SUBREG_TO_REG (i64 0), 2553 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 2554} 2555 2556// Use BZHI for 64-bit 'and' with large immediate 'mask'. 2557let Predicates = [HasBMI2, NoTBM] in { 2558 def : Pat<(and GR64:$src, AndMask64:$mask), 2559 (BZHI64rr GR64:$src, 2560 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2561 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2562 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2563 (BZHI64rm addr:$src, 2564 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2565 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2566} 2567 2568let Predicates = [HasBMI2] in { 2569 multiclass _bmi_bzhi_pattern<dag regpattern, dag mempattern, RegisterClass RC, 2570 ValueType VT, Instruction DstInst, 2571 Instruction DstMemInst> { 2572 def : Pat<regpattern, 2573 (DstInst RC:$src, 2574 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2575 def : Pat<mempattern, 2576 (DstMemInst addr:$src, 2577 (INSERT_SUBREG (VT (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2578 } 2579 2580 multiclass bmi_bzhi_patterns<RegisterClass RC, int bitwidth, ValueType VT, 2581 Instruction DstInst, X86MemOperand x86memop, 2582 Instruction DstMemInst> { 2583 // x & ((1 << y) - 1) 2584 defm : _bmi_bzhi_pattern<(and RC:$src, (add (shl 1, GR8:$lz), -1)), 2585 (and (x86memop addr:$src), 2586 (add (shl 1, GR8:$lz), -1)), 2587 RC, VT, DstInst, DstMemInst>; 2588 2589 // x & ~(-1 << y) 2590 defm : _bmi_bzhi_pattern<(and RC:$src, (xor (shl -1, GR8:$lz), -1)), 2591 (and (x86memop addr:$src), 2592 (xor (shl -1, GR8:$lz), -1)), 2593 RC, VT, DstInst, DstMemInst>; 2594 2595 // x & (-1 >> (bitwidth - y)) 2596 defm : _bmi_bzhi_pattern<(and RC:$src, (srl -1, (sub bitwidth, GR8:$lz))), 2597 (and (x86memop addr:$src), 2598 (srl -1, (sub bitwidth, GR8:$lz))), 2599 RC, VT, DstInst, DstMemInst>; 2600 2601 // x << (bitwidth - y) >> (bitwidth - y) 2602 defm : _bmi_bzhi_pattern<(srl (shl RC:$src, (sub bitwidth, GR8:$lz)), 2603 (sub bitwidth, GR8:$lz)), 2604 (srl (shl (x86memop addr:$src), 2605 (sub bitwidth, GR8:$lz)), 2606 (sub bitwidth, GR8:$lz)), 2607 RC, VT, DstInst, DstMemInst>; 2608 } 2609 2610 defm : bmi_bzhi_patterns<GR32, 32, i32, BZHI32rr, loadi32, BZHI32rm>; 2611 defm : bmi_bzhi_patterns<GR64, 64, i64, BZHI64rr, loadi64, BZHI64rm>; 2612 2613 // x & (-1 >> (32 - y)) 2614 def : Pat<(and GR32:$src, (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), 2615 (BZHI32rr GR32:$src, GR32:$lz)>; 2616 def : Pat<(and (loadi32 addr:$src), (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), 2617 (BZHI32rm addr:$src, GR32:$lz)>; 2618 2619 // x & (-1 >> (64 - y)) 2620 def : Pat<(and GR64:$src, (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), 2621 (BZHI64rr GR64:$src, 2622 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; 2623 def : Pat<(and (loadi64 addr:$src), (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), 2624 (BZHI64rm addr:$src, 2625 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; 2626 2627 // x << (32 - y) >> (32 - y) 2628 def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))), 2629 (i8 (trunc (sub 32, GR32:$lz)))), 2630 (BZHI32rr GR32:$src, GR32:$lz)>; 2631 def : Pat<(srl (shl (loadi32 addr:$src), (i8 (trunc (sub 32, GR32:$lz)))), 2632 (i8 (trunc (sub 32, GR32:$lz)))), 2633 (BZHI32rm addr:$src, GR32:$lz)>; 2634 2635 // x << (64 - y) >> (64 - y) 2636 def : Pat<(srl (shl GR64:$src, (i8 (trunc (sub 64, GR32:$lz)))), 2637 (i8 (trunc (sub 64, GR32:$lz)))), 2638 (BZHI64rr GR64:$src, 2639 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; 2640 def : Pat<(srl (shl (loadi64 addr:$src), (i8 (trunc (sub 64, GR32:$lz)))), 2641 (i8 (trunc (sub 64, GR32:$lz)))), 2642 (BZHI64rm addr:$src, 2643 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; 2644} // HasBMI2 2645 2646multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2647 X86MemOperand x86memop, Intrinsic Int, 2648 PatFrag ld_frag> { 2649 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2650 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2651 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 2652 VEX_4V, Sched<[WriteALU]>; 2653 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2654 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2655 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, 2656 VEX_4V, Sched<[WriteALULd, ReadAfterLd]>; 2657} 2658 2659let Predicates = [HasBMI2] in { 2660 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2661 int_x86_bmi_pdep_32, loadi32>, T8XD; 2662 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2663 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 2664 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2665 int_x86_bmi_pext_32, loadi32>, T8XS; 2666 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2667 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 2668} 2669 2670//===----------------------------------------------------------------------===// 2671// TBM Instructions 2672// 2673let Predicates = [HasTBM], Defs = [EFLAGS] in { 2674 2675multiclass tbm_ternary_imm<bits<8> opc, RegisterClass RC, string OpcodeStr, 2676 X86MemOperand x86memop, PatFrag ld_frag, 2677 SDNode OpNode, Operand immtype, 2678 SDPatternOperator immoperator, 2679 X86FoldableSchedWrite Sched> { 2680 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2681 !strconcat(OpcodeStr, 2682 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2683 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>, 2684 XOP, XOPA, Sched<[Sched]>; 2685 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2686 (ins x86memop:$src1, immtype:$cntl), 2687 !strconcat(OpcodeStr, 2688 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2689 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>, 2690 XOP, XOPA, Sched<[Sched.Folded]>; 2691} 2692 2693defm BEXTRI32 : tbm_ternary_imm<0x10, GR32, "bextr{l}", i32mem, loadi32, 2694 X86bextr, i32imm, imm, WriteBEXTR>; 2695let ImmT = Imm32S in 2696defm BEXTRI64 : tbm_ternary_imm<0x10, GR64, "bextr{q}", i64mem, loadi64, 2697 X86bextr, i64i32imm, 2698 i64immSExt32, WriteBEXTR>, VEX_W; 2699 2700multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2701 RegisterClass RC, string OpcodeStr, 2702 X86MemOperand x86memop, X86FoldableSchedWrite Sched> { 2703let hasSideEffects = 0 in { 2704 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2705 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>, 2706 XOP_4V, XOP9, Sched<[Sched]>; 2707 let mayLoad = 1 in 2708 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2709 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>, 2710 XOP_4V, XOP9, Sched<[Sched.Folded]>; 2711} 2712} 2713 2714multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2715 X86FoldableSchedWrite Sched, 2716 Format FormReg, Format FormMem> { 2717 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr#"{l}", 2718 i32mem, Sched>; 2719 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr#"{q}", 2720 i64mem, Sched>, VEX_W; 2721} 2722 2723defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; 2724defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>; 2725defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>; 2726defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; 2727defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>; 2728defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>; 2729defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>; 2730defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>; 2731defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>; 2732} // HasTBM, EFLAGS 2733 2734// Use BEXTRI for 64-bit 'and' with large immediate 'mask'. 2735let Predicates = [HasTBM] in { 2736 def : Pat<(and GR64:$src, AndMask64:$mask), 2737 (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>; 2738 2739 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2740 (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>; 2741} 2742 2743//===----------------------------------------------------------------------===// 2744// Lightweight Profiling Instructions 2745 2746let Predicates = [HasLWP], SchedRW = [WriteSystem] in { 2747 2748def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", 2749 [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; 2750def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", 2751 [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; 2752 2753def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", 2754 [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; 2755def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", 2756 [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; 2757 2758multiclass lwpins_intr<RegisterClass RC> { 2759 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2760 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2761 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>, 2762 XOP_4V, XOPA; 2763 let mayLoad = 1 in 2764 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 2765 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2766 [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>, 2767 XOP_4V, XOPA; 2768} 2769 2770let Defs = [EFLAGS] in { 2771 defm LWPINS32 : lwpins_intr<GR32>; 2772 defm LWPINS64 : lwpins_intr<GR64>, VEX_W; 2773} // EFLAGS 2774 2775multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> { 2776 def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2777 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2778 [(Int RC:$src0, GR32:$src1, imm:$cntl)]>, XOP_4V, XOPA; 2779 let mayLoad = 1 in 2780 def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 2781 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2782 [(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)]>, 2783 XOP_4V, XOPA; 2784} 2785 2786defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>; 2787defm LWPVAL64 : lwpval_intr<GR64, int_x86_lwpval64>, VEX_W; 2788 2789} // HasLWP, SchedRW 2790 2791//===----------------------------------------------------------------------===// 2792// MONITORX/MWAITX Instructions 2793// 2794let SchedRW = [ WriteSystem ] in { 2795 let usesCustomInserter = 1 in { 2796 def MONITORX : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3), 2797 [(int_x86_monitorx addr:$src1, GR32:$src2, GR32:$src3)]>, 2798 Requires<[ HasMWAITX ]>; 2799 } 2800 2801 let Uses = [ EAX, ECX, EDX ] in { 2802 def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, 2803 TB, Requires<[ HasMWAITX ]>; 2804 } 2805 2806 let Uses = [ ECX, EAX, EBX ] in { 2807 def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", 2808 [(int_x86_mwaitx ECX, EAX, EBX)]>, 2809 TB, Requires<[ HasMWAITX ]>; 2810 } 2811} // SchedRW 2812 2813def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, 2814 Requires<[ Not64BitMode ]>; 2815def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, 2816 Requires<[ In64BitMode ]>; 2817 2818def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, 2819 Requires<[ Not64BitMode ]>; 2820def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, 2821 Requires<[ In64BitMode ]>; 2822 2823//===----------------------------------------------------------------------===// 2824// WAITPKG Instructions 2825// 2826let SchedRW = [WriteSystem] in { 2827 def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), 2828 "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, 2829 XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; 2830 def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), 2831 "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, 2832 XS, AdSize32, Requires<[HasWAITPKG]>; 2833 def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), 2834 "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, 2835 XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; 2836 let Uses = [EAX, EDX], Defs = [EFLAGS] in { 2837 def UMWAIT : I<0xAE, MRM6r, 2838 (outs), (ins GR32orGR64:$src), "umwait\t$src", 2839 [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, 2840 XD, Requires<[HasWAITPKG]>; 2841 def TPAUSE : I<0xAE, MRM6r, 2842 (outs), (ins GR32orGR64:$src), "tpause\t$src", 2843 [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, 2844 PD, Requires<[HasWAITPKG]>, NotMemoryFoldable; 2845 } 2846} // SchedRW 2847 2848//===----------------------------------------------------------------------===// 2849// MOVDIRI - Move doubleword/quadword as direct store 2850// 2851let SchedRW = [WriteStore] in { 2852def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2853 "movdiri\t{$src, $dst|$dst, $src}", 2854 [(int_x86_directstore32 addr:$dst, GR32:$src)]>, 2855 T8, Requires<[HasMOVDIRI]>; 2856def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2857 "movdiri\t{$src, $dst|$dst, $src}", 2858 [(int_x86_directstore64 addr:$dst, GR64:$src)]>, 2859 T8, Requires<[In64BitMode, HasMOVDIRI]>; 2860} // SchedRW 2861 2862//===----------------------------------------------------------------------===// 2863// MOVDIR64B - Move 64 bytes as direct store 2864// 2865let SchedRW = [WriteStore] in { 2866def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 2867 "movdir64b\t{$src, $dst|$dst, $src}", []>, 2868 T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; 2869def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 2870 "movdir64b\t{$src, $dst|$dst, $src}", 2871 [(int_x86_movdir64b GR32:$dst, addr:$src)]>, 2872 T8PD, AdSize32, Requires<[HasMOVDIR64B]>; 2873def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 2874 "movdir64b\t{$src, $dst|$dst, $src}", 2875 [(int_x86_movdir64b GR64:$dst, addr:$src)]>, 2876 T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; 2877} // SchedRW 2878 2879//===----------------------------------------------------------------------===// 2880// CLZERO Instruction 2881// 2882let SchedRW = [WriteSystem] in { 2883 let Uses = [EAX] in 2884 def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, 2885 TB, Requires<[HasCLZERO]>; 2886 2887 let usesCustomInserter = 1 in { 2888 def CLZERO : PseudoI<(outs), (ins i32mem:$src1), 2889 [(int_x86_clzero addr:$src1)]>, Requires<[HasCLZERO]>; 2890 } 2891} // SchedRW 2892 2893def : InstAlias<"clzero\t{%eax|eax}", (CLZEROr)>, Requires<[Not64BitMode]>; 2894def : InstAlias<"clzero\t{%rax|rax}", (CLZEROr)>, Requires<[In64BitMode]>; 2895 2896//===----------------------------------------------------------------------===// 2897// Pattern fragments to auto generate TBM instructions. 2898//===----------------------------------------------------------------------===// 2899 2900let Predicates = [HasTBM] in { 2901 // FIXME: patterns for the load versions are not implemented 2902 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2903 (BLCFILL32rr GR32:$src)>; 2904 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2905 (BLCFILL64rr GR64:$src)>; 2906 2907 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2908 (BLCI32rr GR32:$src)>; 2909 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2910 (BLCI64rr GR64:$src)>; 2911 2912 // Extra patterns because opt can optimize the above patterns to this. 2913 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2914 (BLCI32rr GR32:$src)>; 2915 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2916 (BLCI64rr GR64:$src)>; 2917 2918 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2919 (BLCIC32rr GR32:$src)>; 2920 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2921 (BLCIC64rr GR64:$src)>; 2922 2923 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2924 (BLCMSK32rr GR32:$src)>; 2925 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2926 (BLCMSK64rr GR64:$src)>; 2927 2928 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2929 (BLCS32rr GR32:$src)>; 2930 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2931 (BLCS64rr GR64:$src)>; 2932 2933 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2934 (BLSFILL32rr GR32:$src)>; 2935 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2936 (BLSFILL64rr GR64:$src)>; 2937 2938 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2939 (BLSIC32rr GR32:$src)>; 2940 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2941 (BLSIC64rr GR64:$src)>; 2942 2943 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2944 (T1MSKC32rr GR32:$src)>; 2945 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2946 (T1MSKC64rr GR64:$src)>; 2947 2948 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2949 (TZMSK32rr GR32:$src)>; 2950 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2951 (TZMSK64rr GR64:$src)>; 2952} // HasTBM 2953 2954//===----------------------------------------------------------------------===// 2955// Memory Instructions 2956// 2957 2958let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in 2959def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), 2960 "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; 2961 2962let Predicates = [HasCLWB], SchedRW = [WriteLoad] in 2963def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", 2964 [(int_x86_clwb addr:$src)]>, PD, NotMemoryFoldable; 2965 2966let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in 2967def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", 2968 [(int_x86_cldemote addr:$src)]>, TB; 2969 2970//===----------------------------------------------------------------------===// 2971// Subsystems. 2972//===----------------------------------------------------------------------===// 2973 2974include "X86Capstone.td" 2975 2976include "X86InstrArithmetic.td" 2977include "X86InstrCMovSetCC.td" 2978include "X86InstrExtension.td" 2979include "X86InstrControl.td" 2980include "X86InstrShiftRotate.td" 2981 2982// X87 Floating Point Stack. 2983//include "X86InstrFPStack.td" 2984 2985// SIMD support (SSE, MMX and AVX) 2986//include "X86InstrFragmentsSIMD.td" 2987 2988// FMA - Fused Multiply-Add support (requires FMA) 2989//include "X86InstrFMA.td" 2990 2991// XOP 2992//include "X86InstrXOP.td" 2993 2994// SSE, MMX and 3DNow! vector support. 2995//include "X86InstrSSE.td" 2996//include "X86InstrAVX512.td" 2997//include "X86InstrMMX.td" 2998//include "X86Instr3DNow.td" 2999 3000// MPX instructions 3001//include "X86InstrMPX.td" 3002 3003include "X86InstrVMX.td" 3004include "X86InstrSVM.td" 3005 3006//include "X86InstrTSX.td" 3007//include "X86InstrSGX.td" 3008 3009// System instructions. 3010include "X86InstrSystem.td" 3011 3012// Compiler Pseudo Instructions and Pat Patterns 3013//include "X86InstrCompiler.td" 3014//include "X86InstrVecCompiler.td" 3015 3016//===----------------------------------------------------------------------===// 3017// Assembler Mnemonic Aliases 3018//===----------------------------------------------------------------------===// 3019 3020def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 3021def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 3022def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 3023 3024def : MnemonicAlias<"cbw", "cbtw", "att">; 3025def : MnemonicAlias<"cwde", "cwtl", "att">; 3026def : MnemonicAlias<"cwd", "cwtd", "att">; 3027def : MnemonicAlias<"cdq", "cltd", "att">; 3028def : MnemonicAlias<"cdqe", "cltq", "att">; 3029def : MnemonicAlias<"cqo", "cqto", "att">; 3030 3031// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 3032def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 3033def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 3034 3035def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 3036def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 3037 3038def : MnemonicAlias<"loopz", "loope">; 3039def : MnemonicAlias<"loopnz", "loopne">; 3040 3041def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 3042def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 3043def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 3044def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 3045def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 3046def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 3047def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; 3048def : MnemonicAlias<"popfd", "popfl", "att">; 3049 3050// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 3051// all modes. However: "push (addr)" and "push $42" should default to 3052// pushl/pushq depending on the current mode. Similar for "pop %bx" 3053def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 3054def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 3055def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 3056def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 3057def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 3058def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 3059def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; 3060def : MnemonicAlias<"pushfd", "pushfl", "att">; 3061 3062def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 3063def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 3064def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 3065def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 3066def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 3067def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 3068 3069def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 3070def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 3071def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 3072def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 3073 3074def : MnemonicAlias<"repe", "rep">; 3075def : MnemonicAlias<"repz", "rep">; 3076def : MnemonicAlias<"repnz", "repne">; 3077 3078def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 3079def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 3080def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 3081 3082// Apply 'ret' behavior to 'retn' 3083def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; 3084def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; 3085def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; 3086def : MnemonicAlias<"retn", "ret", "intel">; 3087 3088def : MnemonicAlias<"sal", "shl", "intel">; 3089def : MnemonicAlias<"salb", "shlb", "att">; 3090def : MnemonicAlias<"salw", "shlw", "att">; 3091def : MnemonicAlias<"sall", "shll", "att">; 3092def : MnemonicAlias<"salq", "shlq", "att">; 3093 3094def : MnemonicAlias<"smovb", "movsb", "att">; 3095def : MnemonicAlias<"smovw", "movsw", "att">; 3096def : MnemonicAlias<"smovl", "movsl", "att">; 3097def : MnemonicAlias<"smovq", "movsq", "att">; 3098 3099def : MnemonicAlias<"ud2a", "ud2", "att">; 3100def : MnemonicAlias<"verrw", "verr", "att">; 3101 3102// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' 3103def : MnemonicAlias<"acquire", "xacquire", "intel">; 3104def : MnemonicAlias<"release", "xrelease", "intel">; 3105 3106// System instruction aliases. 3107def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 3108def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 3109def : MnemonicAlias<"sysret", "sysretl", "att">; 3110def : MnemonicAlias<"sysexit", "sysexitl", "att">; 3111 3112def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 3113def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 3114def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 3115def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 3116def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 3117def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 3118def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 3119def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 3120def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 3121def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 3122def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 3123def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 3124//def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; 3125//def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; 3126//def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; 3127//def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; 3128//def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; 3129//def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; 3130//def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; 3131//def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; 3132 3133 3134// Floating point stack aliases. 3135def : MnemonicAlias<"fcmovz", "fcmove", "att">; 3136def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 3137def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 3138def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 3139def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 3140def : MnemonicAlias<"fcomip", "fcompi">; 3141def : MnemonicAlias<"fildq", "fildll", "att">; 3142def : MnemonicAlias<"fistpq", "fistpll", "att">; 3143def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 3144def : MnemonicAlias<"fldcww", "fldcw", "att">; 3145def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 3146def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 3147def : MnemonicAlias<"fucomip", "fucompi">; 3148def : MnemonicAlias<"fwait", "wait">; 3149 3150def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 3151def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 3152def : MnemonicAlias<"xsaveq", "xsave64", "att">; 3153def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 3154def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 3155def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; 3156def : MnemonicAlias<"xsavecq", "xsavec64", "att">; 3157def : MnemonicAlias<"xsavesq", "xsaves64", "att">; 3158 3159class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 3160 string VariantName> 3161 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 3162 !strconcat(Prefix, NewCond, Suffix), VariantName>; 3163 3164/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 3165/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 3166/// example "setz" -> "sete". 3167multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 3168 string V = ""> { 3169 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 3170 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 3171 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 3172 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 3173 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 3174 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 3175 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 3176 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 3177 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 3178 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 3179 3180 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 3181 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 3182 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 3183 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 3184} 3185 3186// Aliases for set<CC> 3187defm : IntegerCondCodeMnemonicAlias<"set", "">; 3188// Aliases for j<CC> 3189defm : IntegerCondCodeMnemonicAlias<"j", "">; 3190// Aliases for cmov<CC>{w,l,q} 3191defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 3192defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 3193defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 3194// No size suffix for intel-style asm. 3195defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 3196 3197 3198//===----------------------------------------------------------------------===// 3199// Assembler Instruction Aliases 3200//===----------------------------------------------------------------------===// 3201 3202// aad/aam default to base 10 if no operand is specified. 3203def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; 3204def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; 3205 3206// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 3207// Likewise for btc/btr/bts. 3208def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", 3209 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; 3210def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", 3211 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; 3212def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", 3213 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; 3214def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", 3215 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0, "att">; 3216 3217// clr aliases. 3218def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 3219def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 3220def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 3221def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 3222 3223// lods aliases. Accept the destination being omitted because it's implicit 3224// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 3225// in the destination. 3226def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; 3227def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; 3228def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; 3229def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 3230def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 3231def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 3232def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 3233def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 3234def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; 3235def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; 3236def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; 3237def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3238 3239 3240// stos aliases. Accept the source being omitted because it's implicit in 3241// the mnemonic, or the mnemonic suffix being omitted because it's implicit 3242// in the source. 3243def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; 3244def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; 3245def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; 3246def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3247def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 3248def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 3249def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 3250def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3251def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; 3252def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; 3253def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; 3254def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 3255 3256 3257// scas aliases. Accept the destination being omitted because it's implicit 3258// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 3259// in the destination. 3260def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; 3261def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; 3262def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; 3263def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3264def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 3265def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 3266def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 3267def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3268def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; 3269def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; 3270def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; 3271def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 3272 3273// cmps aliases. Mnemonic suffix being omitted because it's implicit 3274// in the destination. 3275def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 3276def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 3277def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 3278def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3279 3280// movs aliases. Mnemonic suffix being omitted because it's implicit 3281// in the destination. 3282def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 3283def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 3284def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 3285def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3286 3287// div and idiv aliases for explicit A register. 3288def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 3289def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 3290def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 3291def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 3292def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 3293def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 3294def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 3295def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 3296def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 3297def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 3298def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 3299def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 3300def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 3301def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 3302def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 3303def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 3304 3305 3306 3307// Various unary fpstack operations default to operating on ST1. 3308// For example, "fxch" -> "fxch %st(1)" 3309def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 3310def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; 3311def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 3312def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 3313def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; 3314def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 3315def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 3316def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 3317def : InstAlias<"fxch", (XCH_F ST1), 0>; 3318def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 3319def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 3320def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 3321def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 3322def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 3323def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 3324def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 3325def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 3326 3327// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 3328// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 3329// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 3330// gas. 3331multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 3332 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 3333 (Inst RST:$op), EmitAlias>; 3334 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 3335 (Inst ST0), EmitAlias>; 3336} 3337 3338defm : FpUnaryAlias<"fadd", ADD_FST0r>; 3339defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 3340defm : FpUnaryAlias<"fsub", SUB_FST0r>; 3341defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 3342defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 3343defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 3344defm : FpUnaryAlias<"fmul", MUL_FST0r>; 3345defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 3346defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 3347defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 3348defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 3349defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 3350defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 3351defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 3352defm : FpUnaryAlias<"fcompi", COM_FIPr>; 3353defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 3354 3355 3356// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 3357// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 3358// solely because gas supports it. 3359def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 3360def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 3361def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 3362def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 3363def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 3364def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 3365 3366def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; 3367 3368// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 3369// this is compatible with what GAS does. 3370def : InstAlias<"lcall\t$seg : $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 3371def : InstAlias<"ljmp\t$seg : $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 3372def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 3373def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 3374def : InstAlias<"lcall\t$seg : $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 3375def : InstAlias<"ljmp\t$seg : $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 3376def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 3377def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 3378 3379def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; 3380def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; 3381def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; 3382 3383 3384// "imul <imm>, B" is an alias for "imul <imm>, B, B". 3385def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 3386def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 3387def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 3388def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 3389def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 3390def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 3391 3392// ins aliases. Accept the mnemonic suffix being omitted because it's implicit 3393// in the destination. 3394def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; 3395def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; 3396def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; 3397 3398// outs aliases. Accept the mnemonic suffix being omitted because it's implicit 3399// in the source. 3400def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; 3401def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; 3402def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; 3403 3404// inb %dx -> inb %al, %dx 3405def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 3406def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 3407def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 3408def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; 3409def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; 3410def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; 3411 3412 3413// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 3414def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 3415def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 3416def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 3417def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 3418def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3419def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3420def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3421def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3422 3423// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 3424def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 3425 3426// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, 3427// which supports this due to an old AMD documentation bug when 64-bit mode was 3428// created. 3429def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 3430 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 3431def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 3432 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 3433 3434// movsx aliases 3435def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; 3436def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 3437def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; 3438def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; 3439def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; 3440def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; 3441def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; 3442 3443// movzx aliases 3444def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; 3445def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 3446def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; 3447def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; 3448def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; 3449def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; 3450// Note: No GR32->GR64 movzx form. 3451 3452// outb %dx -> outb %al, %dx 3453def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 3454def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 3455def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 3456def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; 3457def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; 3458def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; 3459 3460// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 3461// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 3462// errors, since its encoding is the most compact. 3463def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 3464 3465// shld/shrd op,op -> shld op, op, CL 3466def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 3467def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 3468def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 3469def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 3470def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 3471def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 3472 3473def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 3474def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 3475def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 3476def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 3477def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 3478def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 3479 3480/* FIXME: This is disabled because the asm matcher is currently incapable of 3481 * matching a fixed immediate like $1. 3482// "shl X, $1" is an alias for "shl X". 3483multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 3484 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 3485 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 3486 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 3487 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 3488 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 3489 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 3490 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 3491 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 3492 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 3493 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 3494 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 3495 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 3496 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 3497 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 3498 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 3499 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 3500} 3501 3502defm : ShiftRotateByOneAlias<"rcl", "RCL">; 3503defm : ShiftRotateByOneAlias<"rcr", "RCR">; 3504defm : ShiftRotateByOneAlias<"rol", "ROL">; 3505defm : ShiftRotateByOneAlias<"ror", "ROR">; 3506FIXME */ 3507 3508// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 3509def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", 3510 (TEST8mr i8mem :$mem, GR8 :$val), 0>; 3511def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", 3512 (TEST16mr i16mem:$mem, GR16:$val), 0>; 3513def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", 3514 (TEST32mr i32mem:$mem, GR32:$val), 0>; 3515def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", 3516 (TEST64mr i64mem:$mem, GR64:$val), 0>; 3517 3518// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 3519def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 3520 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 3521def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 3522 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 3523def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 3524 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 3525def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 3526 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 3527 3528// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 3529def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 3530def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; 3531def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 3532 3533// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we 3534// would get by default because it's defined as NOP. But xchg %eax, %eax implies 3535// implicit zeroing of the upper 32 bits. So alias to the longer encoding. 3536def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", 3537 (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; 3538 3539// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this 3540// we emit an unneeded REX.w prefix. 3541def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; 3542 3543// These aliases exist to get the parser to prioritize matching 8-bit 3544// immediate encodings over matching the implicit ax/eax/rax encodings. By 3545// explicitly mentioning the A register here, these entries will be ordered 3546// first due to the more explicit immediate type. 3547def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; 3548def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; 3549def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; 3550def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; 3551def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; 3552def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; 3553def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; 3554def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; 3555 3556def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; 3557def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; 3558def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; 3559def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; 3560def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; 3561def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; 3562def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; 3563def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; 3564 3565def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; 3566def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; 3567def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; 3568def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; 3569def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; 3570def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; 3571def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; 3572def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; 3573