1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6
7 #include <capstone/platform.h>
8 #include <capstone/capstone.h>
9
10 struct platform {
11 cs_arch arch;
12 cs_mode mode;
13 unsigned char *code;
14 size_t size;
15 const char *comment;
16 cs_opt_type opt_type;
17 cs_opt_value opt_value;
18 };
19
print_string_hex(unsigned char * str,size_t len)20 static void print_string_hex(unsigned char *str, size_t len)
21 {
22 unsigned char *c;
23
24 printf("Code: ");
25 for (c = str; c < str + len; c++) {
26 printf("0x%02x ", *c & 0xff);
27 }
28 printf("\n");
29 }
30
test()31 static void test()
32 {
33 #ifdef CAPSTONE_HAS_X86
34 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
35 #define X86_CODE32 "\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
36 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
37 #endif
38 #ifdef CAPSTONE_HAS_ARM
39 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
40 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
41 #define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
42 #define THUMB_MCLASS "\xef\xf3\x02\x80"
43 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
44 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
45 #endif
46 #ifdef CAPSTONE_HAS_MIPS
47 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
48 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
49 #define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
50 #define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
51 #endif
52 #ifdef CAPSTONE_HAS_ARM64
53 #define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
54 #endif
55 #ifdef CAPSTONE_HAS_POWERPC
56 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
57 #define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
58 #endif
59 #ifdef CAPSTONE_HAS_SPARC
60 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
61 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
62 #endif
63 #ifdef CAPSTONE_HAS_SYSZ
64 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
65 #endif
66 #ifdef CAPSTONE_HAS_XCORE
67 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
68 #endif
69 #ifdef CAPSTONE_HAS_M68K
70 #define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28"
71 #endif
72 #ifdef CAPSTONE_HAS_TMS320C64X
73 #define TMS320C64X_CODE "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24"
74 #endif
75 #ifdef CAPSTONE_HAS_M680X
76 #define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
77 #endif
78 #ifdef CAPSTONE_HAS_EVM
79 #define EVM_CODE "\x60\x61"
80 #endif
81 #ifdef CAPSTONE_HAS_WASM
82 #define WASM_CODE "\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b"
83 #endif
84 #ifdef CAPSTONE_HAS_MOS65XX
85 #define MOS65XX_CODE "\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
86 #endif
87 #define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
88
89 #ifdef CAPSTONE_HAS_RISCV
90 #define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00"
91 #define RISCV_CODE64 "\x13\x04\xa8\x7a" // aaa80413
92 #endif
93
94 struct platform {
95 cs_arch arch;
96 cs_mode mode;
97 unsigned char *code;
98 size_t size;
99 const char *comment;
100 cs_opt_type opt_type;
101 cs_opt_value opt_value;
102 };
103 struct platform platforms[] = {
104 #ifdef CAPSTONE_HAS_X86
105 {
106 CS_ARCH_X86,
107 CS_MODE_16,
108 (unsigned char*)X86_CODE16,
109 sizeof(X86_CODE16) - 1,
110 "X86 16bit (Intel syntax)"
111 },
112 {
113 CS_ARCH_X86,
114 CS_MODE_32,
115 (unsigned char*)X86_CODE32,
116 sizeof(X86_CODE32) - 1,
117 "X86 32bit (ATT syntax)",
118 CS_OPT_SYNTAX,
119 CS_OPT_SYNTAX_ATT,
120 },
121 {
122 CS_ARCH_X86,
123 CS_MODE_32,
124 (unsigned char*)X86_CODE32,
125 sizeof(X86_CODE32) - 1,
126 "X86 32 (Intel syntax)"
127 },
128 {
129 CS_ARCH_X86,
130 CS_MODE_32,
131 (unsigned char*)X86_CODE32,
132 sizeof(X86_CODE32) - 1,
133 "X86 32 (MASM syntax)",
134 CS_OPT_SYNTAX,
135 CS_OPT_SYNTAX_MASM,
136 },
137 {
138 CS_ARCH_X86,
139 CS_MODE_64,
140 (unsigned char*)X86_CODE64,
141 sizeof(X86_CODE64) - 1,
142 "X86 64 (Intel syntax)"
143 },
144 #endif
145 #ifdef CAPSTONE_HAS_ARM
146 {
147 CS_ARCH_ARM,
148 CS_MODE_ARM,
149 (unsigned char*)ARM_CODE,
150 sizeof(ARM_CODE) - 1,
151 "ARM"
152 },
153 {
154 CS_ARCH_ARM,
155 CS_MODE_THUMB,
156 (unsigned char*)THUMB_CODE2,
157 sizeof(THUMB_CODE2) - 1,
158 "THUMB-2"
159 },
160 {
161 CS_ARCH_ARM,
162 CS_MODE_ARM,
163 (unsigned char*)ARM_CODE2,
164 sizeof(ARM_CODE2) - 1,
165 "ARM: Cortex-A15 + NEON"
166 },
167 {
168 CS_ARCH_ARM,
169 CS_MODE_THUMB,
170 (unsigned char*)THUMB_CODE,
171 sizeof(THUMB_CODE) - 1,
172 "THUMB"
173 },
174 {
175 CS_ARCH_ARM,
176 (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
177 (unsigned char*)THUMB_MCLASS,
178 sizeof(THUMB_MCLASS) - 1,
179 "Thumb-MClass"
180 },
181 {
182 CS_ARCH_ARM,
183 (cs_mode)(CS_MODE_ARM + CS_MODE_V8),
184 (unsigned char*)ARMV8,
185 sizeof(ARMV8) - 1,
186 "Arm-V8"
187 },
188 #endif
189 #ifdef CAPSTONE_HAS_MIPS
190 {
191 CS_ARCH_MIPS,
192 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
193 (unsigned char*)MIPS_CODE,
194 sizeof(MIPS_CODE) - 1,
195 "MIPS-32 (Big-endian)"
196 },
197 {
198 CS_ARCH_MIPS,
199 (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
200 (unsigned char*)MIPS_CODE2,
201 sizeof(MIPS_CODE2) - 1,
202 "MIPS-64-EL (Little-endian)"
203 },
204 {
205 CS_ARCH_MIPS,
206 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
207 (unsigned char*)MIPS_32R6M,
208 sizeof(MIPS_32R6M) - 1,
209 "MIPS-32R6 | Micro (Big-endian)"
210 },
211 {
212 CS_ARCH_MIPS,
213 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
214 (unsigned char*)MIPS_32R6,
215 sizeof(MIPS_32R6) - 1,
216 "MIPS-32R6 (Big-endian)"
217 },
218 #endif
219 #ifdef CAPSTONE_HAS_ARM64
220 {
221 CS_ARCH_ARM64,
222 CS_MODE_ARM,
223 (unsigned char*)ARM64_CODE,
224 sizeof(ARM64_CODE) - 1,
225 "ARM-64"
226 },
227 #endif
228 #ifdef CAPSTONE_HAS_POWERPC
229 {
230 CS_ARCH_PPC,
231 CS_MODE_BIG_ENDIAN,
232 (unsigned char*)PPC_CODE,
233 sizeof(PPC_CODE) - 1,
234 "PPC-64"
235 },
236 {
237 CS_ARCH_PPC,
238 CS_MODE_BIG_ENDIAN,
239 (unsigned char*)PPC_CODE,
240 sizeof(PPC_CODE) - 1,
241 "PPC-64, print register with number only",
242 CS_OPT_SYNTAX,
243 CS_OPT_SYNTAX_NOREGNAME
244 },
245 {
246 CS_ARCH_PPC,
247 CS_MODE_BIG_ENDIAN + CS_MODE_QPX,
248 (unsigned char*)PPC_CODE2,
249 sizeof(PPC_CODE2) - 1,
250 "PPC-64 + QPX",
251 },
252 #endif
253 #ifdef CAPSTONE_HAS_SPARC
254 {
255 CS_ARCH_SPARC,
256 CS_MODE_BIG_ENDIAN,
257 (unsigned char*)SPARC_CODE,
258 sizeof(SPARC_CODE) - 1,
259 "Sparc"
260 },
261 {
262 CS_ARCH_SPARC,
263 (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
264 (unsigned char*)SPARCV9_CODE,
265 sizeof(SPARCV9_CODE) - 1,
266 "SparcV9"
267 },
268 #endif
269 #ifdef CAPSTONE_HAS_SYSZ
270 {
271 CS_ARCH_SYSZ,
272 (cs_mode)0,
273 (unsigned char*)SYSZ_CODE,
274 sizeof(SYSZ_CODE) - 1,
275 "SystemZ"
276 },
277 #endif
278 #ifdef CAPSTONE_HAS_XCORE
279 {
280 CS_ARCH_XCORE,
281 (cs_mode)0,
282 (unsigned char*)XCORE_CODE,
283 sizeof(XCORE_CODE) - 1,
284 "XCore"
285 },
286 #endif
287 #ifdef CAPSTONE_HAS_M68K
288 {
289 CS_ARCH_M68K,
290 (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040),
291 (unsigned char*)M68K_CODE,
292 sizeof(M68K_CODE) - 1,
293 "M68K",
294 },
295 #endif
296 #ifdef CAPSTONE_HAS_TMS320C64X
297 {
298 CS_ARCH_TMS320C64X,
299 0,
300 (unsigned char*)TMS320C64X_CODE,
301 sizeof(TMS320C64X_CODE) - 1,
302 "TMS320C64x",
303 },
304 #endif
305 #ifdef CAPSTONE_HAS_M680X
306 {
307 CS_ARCH_M680X,
308 (cs_mode)(CS_MODE_M680X_6809),
309 (unsigned char*)M680X_CODE,
310 sizeof(M680X_CODE) - 1,
311 "M680X_M6809",
312 },
313 #endif
314 #ifdef CAPSTONE_HAS_EVM
315 {
316 CS_ARCH_EVM,
317 0,
318 (unsigned char*)EVM_CODE,
319 sizeof(EVM_CODE) - 1,
320 "EVM",
321 },
322 #endif
323 #ifdef CAPSTONE_HAS_WASM
324 {
325 CS_ARCH_WASM,
326 0,
327 (unsigned char*)WASM_CODE,
328 sizeof(WASM_CODE) - 1,
329 "WASM",
330 },
331 #endif
332 #ifdef CAPSTONE_HAS_MOS65XX
333 {
334 CS_ARCH_MOS65XX,
335 0,
336 (unsigned char *)MOS65XX_CODE,
337 sizeof(MOS65XX_CODE) - 1,
338 "MOS65XX"
339 },
340 #endif
341 #ifdef CAPSTONE_HAS_BPF
342 {
343 CS_ARCH_BPF,
344 CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
345 (unsigned char*) EBPF_CODE,
346 sizeof(EBPF_CODE) - 1,
347 "eBPF"
348 },
349 #endif
350 #ifdef CAPSTONE_HAS_RISCV
351 {
352 CS_ARCH_RISCV,
353 CS_MODE_RISCV32,
354 (unsigned char *)RISCV_CODE32,
355 sizeof(RISCV_CODE32) - 1,
356 "RISCV32"
357 },
358 {
359 CS_ARCH_RISCV,
360 CS_MODE_RISCV64,
361 (unsigned char *)RISCV_CODE64,
362 sizeof(RISCV_CODE64) - 1,
363 "RISCV64"
364 },
365 #endif
366 };
367
368 csh handle;
369 uint64_t address = 0x1000;
370 cs_insn *insn;
371 int i;
372 size_t count;
373 cs_err err;
374
375 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
376 printf("****************\n");
377 printf("Platform: %s\n", platforms[i].comment);
378 err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
379 if (err) {
380 printf("Failed on cs_open() with error returned: %u\n", err);
381 abort();
382 }
383
384 if (platforms[i].opt_type)
385 cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
386
387 count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
388 if (count) {
389 size_t j;
390
391 print_string_hex(platforms[i].code, platforms[i].size);
392 printf("Disasm:\n");
393
394 for (j = 0; j < count; j++) {
395 printf("0x%" PRIx64 ":\t%s\t\t%s\n",
396 insn[j].address, insn[j].mnemonic, insn[j].op_str);
397 }
398
399 // print out the next offset, after the last insn
400 printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
401
402 // free memory allocated by cs_disasm()
403 cs_free(insn, count);
404 } else {
405 printf("****************\n");
406 printf("Platform: %s\n", platforms[i].comment);
407 print_string_hex(platforms[i].code, platforms[i].size);
408 printf("ERROR: Failed to disasm given code!\n");
409 abort();
410 }
411
412 printf("\n");
413
414 cs_close(&handle);
415 }
416 }
417
main()418 int main()
419 {
420 test();
421
422 return 0;
423 }
424