1 /* Copyright 2013-2014 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <skiboot.h>
18 #include <cpu.h>
19 #include <pci.h>
20 #include <pci-cfg.h>
21 #include <pci-slot.h>
22 #include <pci-quirk.h>
23 #include <timebase.h>
24 #include <device.h>
25
26 #define MAX_PHB_ID 256
27 static struct phb *phbs[MAX_PHB_ID];
28 int last_phb_id = 0;
29
30 /*
31 * Generic PCI utilities
32 */
33
__pci_find_cap(struct phb * phb,uint16_t bdfn,uint8_t want,bool check_cap_indicator)34 static int64_t __pci_find_cap(struct phb *phb, uint16_t bdfn,
35 uint8_t want, bool check_cap_indicator)
36 {
37 int64_t rc;
38 uint16_t stat, cap;
39 uint8_t pos, next;
40
41 rc = pci_cfg_read16(phb, bdfn, PCI_CFG_STAT, &stat);
42 if (rc)
43 return rc;
44 if (check_cap_indicator && !(stat & PCI_CFG_STAT_CAP))
45 return OPAL_UNSUPPORTED;
46 rc = pci_cfg_read8(phb, bdfn, PCI_CFG_CAP, &pos);
47 if (rc)
48 return rc;
49 pos &= 0xfc;
50 while(pos) {
51 rc = pci_cfg_read16(phb, bdfn, pos, &cap);
52 if (rc)
53 return rc;
54 if ((cap & 0xff) == want)
55 return pos;
56 next = (cap >> 8) & 0xfc;
57 if (next == pos) {
58 PCIERR(phb, bdfn, "pci_find_cap hit a loop !\n");
59 break;
60 }
61 pos = next;
62 }
63 return OPAL_UNSUPPORTED;
64 }
65
66 /* pci_find_cap - Find a PCI capability in a device config space
67 *
68 * This will return a config space offset (positive) or a negative
69 * error (OPAL error codes).
70 *
71 * OPAL_UNSUPPORTED is returned if the capability doesn't exist
72 */
pci_find_cap(struct phb * phb,uint16_t bdfn,uint8_t want)73 int64_t pci_find_cap(struct phb *phb, uint16_t bdfn, uint8_t want)
74 {
75 return __pci_find_cap(phb, bdfn, want, true);
76 }
77
78 /* pci_find_ecap - Find a PCIe extended capability in a device
79 * config space
80 *
81 * This will return a config space offset (positive) or a negative
82 * error (OPAL error code). Additionally, if the "version" argument
83 * is non-NULL, the capability version will be returned there.
84 *
85 * OPAL_UNSUPPORTED is returned if the capability doesn't exist
86 */
pci_find_ecap(struct phb * phb,uint16_t bdfn,uint16_t want,uint8_t * version)87 int64_t pci_find_ecap(struct phb *phb, uint16_t bdfn, uint16_t want,
88 uint8_t *version)
89 {
90 int64_t rc;
91 uint32_t cap;
92 uint16_t off, prev = 0;
93
94 for (off = 0x100; off && off < 0x1000; off = (cap >> 20) & 0xffc ) {
95 if (off == prev) {
96 PCIERR(phb, bdfn, "pci_find_ecap hit a loop !\n");
97 break;
98 }
99 prev = off;
100 rc = pci_cfg_read32(phb, bdfn, off, &cap);
101 if (rc)
102 return rc;
103 if ((cap & 0xffff) == want) {
104 if (version)
105 *version = (cap >> 16) & 0xf;
106 return off;
107 }
108 }
109 return OPAL_UNSUPPORTED;
110 }
111
pci_init_pcie_cap(struct phb * phb,struct pci_device * pd)112 static void pci_init_pcie_cap(struct phb *phb, struct pci_device *pd)
113 {
114 int64_t ecap = 0;
115 uint16_t reg;
116 uint32_t val;
117
118 /* On the upstream port of PLX bridge 8724 (rev ba), PCI_STATUS
119 * register doesn't have capability indicator though it support
120 * various PCI capabilities. So we need ignore that bit when
121 * looking for PCI capabilities on the upstream port, which is
122 * limited to one that seats directly under root port.
123 */
124 if (pd->vdid == 0x872410b5 && pd->parent && !pd->parent->parent) {
125 uint8_t rev;
126
127 pci_cfg_read8(phb, pd->bdfn, PCI_CFG_REV_ID, &rev);
128 if (rev == 0xba)
129 ecap = __pci_find_cap(phb, pd->bdfn,
130 PCI_CFG_CAP_ID_EXP, false);
131 else
132 ecap = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_EXP);
133 } else {
134 ecap = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_EXP);
135 }
136
137 if (ecap <= 0) {
138 pd->dev_type = PCIE_TYPE_LEGACY;
139 return;
140 }
141
142 pci_set_cap(pd, PCI_CFG_CAP_ID_EXP, ecap, NULL, NULL, false);
143
144 /*
145 * XXX We observe a problem on some PLX switches where one
146 * of the downstream ports appears as an upstream port, we
147 * fix that up here otherwise, other code will misbehave
148 */
149 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_CAPABILITY_REG, ®);
150 pd->dev_type = GETFIELD(PCICAP_EXP_CAP_TYPE, reg);
151 if (pd->parent && pd->parent->dev_type == PCIE_TYPE_SWITCH_UPPORT &&
152 pd->vdid == 0x874810b5 && pd->dev_type == PCIE_TYPE_SWITCH_UPPORT) {
153 PCIDBG(phb, pd->bdfn, "Fixing up bad PLX downstream port !\n");
154 pd->dev_type = PCIE_TYPE_SWITCH_DNPORT;
155 }
156
157 /* XXX Handle ARI */
158 if (pd->dev_type == PCIE_TYPE_SWITCH_DNPORT ||
159 pd->dev_type == PCIE_TYPE_ROOT_PORT)
160 pd->scan_map = 0x1;
161
162 /* Read MPS capability, whose maximal size is 4096 */
163 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_DEVCAP, &val);
164 pd->mps = (128 << GETFIELD(PCICAP_EXP_DEVCAP_MPSS, val));
165 if (pd->mps > 4096)
166 pd->mps = 4096;
167 }
168
pci_init_aer_cap(struct phb * phb,struct pci_device * pd)169 static void pci_init_aer_cap(struct phb *phb, struct pci_device *pd)
170 {
171 int64_t pos;
172
173 if (!pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false))
174 return;
175
176 pos = pci_find_ecap(phb, pd->bdfn, PCIECAP_ID_AER, NULL);
177 if (pos > 0)
178 pci_set_cap(pd, PCIECAP_ID_AER, pos, NULL, NULL, true);
179 }
180
pci_init_pm_cap(struct phb * phb,struct pci_device * pd)181 static void pci_init_pm_cap(struct phb *phb, struct pci_device *pd)
182 {
183 int64_t pos;
184
185 pos = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_PM);
186 if (pos > 0)
187 pci_set_cap(pd, PCI_CFG_CAP_ID_PM, pos, NULL, NULL, false);
188 }
189
pci_init_capabilities(struct phb * phb,struct pci_device * pd)190 void pci_init_capabilities(struct phb *phb, struct pci_device *pd)
191 {
192 pci_init_pcie_cap(phb, pd);
193 pci_init_aer_cap(phb, pd);
194 pci_init_pm_cap(phb, pd);
195 }
196
pci_wait_crs(struct phb * phb,uint16_t bdfn,uint32_t * out_vdid)197 bool pci_wait_crs(struct phb *phb, uint16_t bdfn, uint32_t *out_vdid)
198 {
199 uint32_t retries, vdid;
200 int64_t rc;
201 bool had_crs = false;
202
203 for (retries = 0; retries < 40; retries++) {
204 rc = pci_cfg_read32(phb, bdfn, PCI_CFG_VENDOR_ID, &vdid);
205 if (rc)
206 return false;
207 if (vdid == 0xffffffff || vdid == 0x00000000)
208 return false;
209 if (vdid != 0xffff0001)
210 break;
211 had_crs = true;
212 time_wait_ms(100);
213 }
214 if (vdid == 0xffff0001) {
215 PCIERR(phb, bdfn, "CRS timeout !\n");
216 return false;
217 }
218 if (had_crs)
219 PCIDBG(phb, bdfn, "Probe success after %d CRS\n", retries);
220
221 if (out_vdid)
222 *out_vdid = vdid;
223 return true;
224 }
225
pci_scan_one(struct phb * phb,struct pci_device * parent,uint16_t bdfn)226 static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *parent,
227 uint16_t bdfn)
228 {
229 struct pci_device *pd = NULL;
230 uint32_t vdid;
231 int64_t rc;
232 uint8_t htype;
233
234 if (!pci_wait_crs(phb, bdfn, &vdid))
235 return NULL;
236
237 /* Perform a dummy write to the device in order for it to
238 * capture it's own bus number, so any subsequent error
239 * messages will be properly tagged
240 */
241 pci_cfg_write32(phb, bdfn, PCI_CFG_VENDOR_ID, vdid);
242
243 pd = zalloc(sizeof(struct pci_device));
244 if (!pd) {
245 PCIERR(phb, bdfn,"Failed to allocate structure pci_device !\n");
246 goto fail;
247 }
248 pd->phb = phb;
249 pd->bdfn = bdfn;
250 pd->vdid = vdid;
251 pci_cfg_read32(phb, bdfn, PCI_CFG_SUBSYS_VENDOR_ID, &pd->sub_vdid);
252 pci_cfg_read32(phb, bdfn, PCI_CFG_REV_ID, &pd->class);
253 pd->class >>= 8;
254
255 pd->parent = parent;
256 list_head_init(&pd->pcrf);
257 list_head_init(&pd->children);
258 rc = pci_cfg_read8(phb, bdfn, PCI_CFG_HDR_TYPE, &htype);
259 if (rc) {
260 PCIERR(phb, bdfn, "Failed to read header type !\n");
261 goto fail;
262 }
263 pd->is_multifunction = !!(htype & 0x80);
264 pd->is_bridge = (htype & 0x7f) != 0;
265 pd->is_vf = false;
266 pd->scan_map = 0xffffffff; /* Default */
267 pd->primary_bus = (bdfn >> 8);
268
269 pci_init_capabilities(phb, pd);
270
271 /* If it's a bridge, sanitize the bus numbers to avoid forwarding
272 *
273 * This will help when walking down those bridges later on
274 */
275 if (pd->is_bridge) {
276 pci_cfg_write8(phb, bdfn, PCI_CFG_PRIMARY_BUS, pd->primary_bus);
277 pci_cfg_write8(phb, bdfn, PCI_CFG_SECONDARY_BUS, 0);
278 pci_cfg_write8(phb, bdfn, PCI_CFG_SUBORDINATE_BUS, 0);
279 }
280
281 /* XXX Need to do some basic setups, such as MPSS, MRS,
282 * RCB, etc...
283 */
284
285 PCIDBG(phb, bdfn, "Found VID:%04x DEV:%04x TYP:%d MF%s BR%s EX%s\n",
286 vdid & 0xffff, vdid >> 16, pd->dev_type,
287 pd->is_multifunction ? "+" : "-",
288 pd->is_bridge ? "+" : "-",
289 pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false) ? "+" : "-");
290
291 /* Try to get PCI slot behind the device */
292 if (platform.pci_get_slot_info)
293 platform.pci_get_slot_info(phb, pd);
294
295 /* Put it to the child device of list of PHB or parent */
296 if (!parent)
297 list_add_tail(&phb->devices, &pd->link);
298 else
299 list_add_tail(&parent->children, &pd->link);
300
301 /*
302 * Call PHB hook
303 */
304 if (phb->ops->device_init)
305 phb->ops->device_init(phb, pd, NULL);
306
307 return pd;
308 fail:
309 if (pd)
310 free(pd);
311 return NULL;
312 }
313
314 /* pci_check_clear_freeze - Probing empty slot will result in an EEH
315 * freeze. Currently we have a single PE mapping
316 * everything (default state of our backend) so
317 * we just check and clear the state of PE#0
318 *
319 * NOTE: We currently only handle simple PE freeze, not PHB fencing
320 * (or rather our backend does)
321 */
pci_check_clear_freeze(struct phb * phb)322 static void pci_check_clear_freeze(struct phb *phb)
323 {
324 uint8_t freeze_state;
325 uint16_t pci_error_type, sev;
326 int64_t pe_number, rc;
327
328 /* Retrieve the reserved PE number */
329 pe_number = OPAL_PARAMETER;
330 if (phb->ops->get_reserved_pe_number)
331 pe_number = phb->ops->get_reserved_pe_number(phb);
332 if (pe_number < 0)
333 return;
334
335 /* Retrieve the frozen state */
336 rc = phb->ops->eeh_freeze_status(phb, pe_number, &freeze_state,
337 &pci_error_type, &sev);
338 if (rc)
339 return;
340 if (freeze_state == OPAL_EEH_STOPPED_NOT_FROZEN)
341 return;
342 /* We can't handle anything worse than an ER here */
343 if (sev > OPAL_EEH_SEV_NO_ERROR &&
344 sev < OPAL_EEH_SEV_PE_ER) {
345 PCIERR(phb, 0, "Fatal probe in %s error !\n", __func__);
346 return;
347 }
348 phb->ops->eeh_freeze_clear(phb, pe_number,
349 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
350 }
351
352 /*
353 * Turn off slot's power supply if there are nothing connected for
354 * 2 purposes: power saving obviously and initialize the slot to
355 * to initial power-off state for hotplug.
356 *
357 * The power should be turned on if the downstream link of the slot
358 * isn't up.
359 */
pci_slot_set_power_state(struct phb * phb,struct pci_device * pd,uint8_t state)360 static void pci_slot_set_power_state(struct phb *phb,
361 struct pci_device *pd,
362 uint8_t state)
363 {
364 struct pci_slot *slot;
365 uint8_t cur_state;
366 int32_t wait = 100;
367 int64_t rc;
368
369 if (!pd || !pd->slot)
370 return;
371
372 slot = pd->slot;
373 if (!slot->pluggable ||
374 !slot->ops.get_power_state ||
375 !slot->ops.set_power_state)
376 return;
377
378 if (state == PCI_SLOT_POWER_OFF) {
379 /* Bail if there're something connected */
380 if (!list_empty(&pd->children)) {
381 PCIERR(phb, pd->bdfn, "Attempted to power off slot with attached devices!\n");
382 return;
383 }
384
385 pci_slot_add_flags(slot, PCI_SLOT_FLAG_BOOTUP);
386 rc = slot->ops.get_power_state(slot, &cur_state);
387 if (rc != OPAL_SUCCESS) {
388 PCINOTICE(phb, pd->bdfn, "Error %lld getting slot power state\n", rc);
389 cur_state = PCI_SLOT_POWER_OFF;
390 }
391
392 pci_slot_remove_flags(slot, PCI_SLOT_FLAG_BOOTUP);
393 if (cur_state == PCI_SLOT_POWER_OFF)
394 return;
395 }
396
397 pci_slot_add_flags(slot,
398 (PCI_SLOT_FLAG_BOOTUP | PCI_SLOT_FLAG_ENFORCE));
399 rc = slot->ops.set_power_state(slot, state);
400 if (rc == OPAL_SUCCESS)
401 goto success;
402 if (rc != OPAL_ASYNC_COMPLETION) {
403 PCINOTICE(phb, pd->bdfn, "Error %lld powering %s slot\n",
404 rc, state == PCI_SLOT_POWER_ON ? "on" : "off");
405 goto error;
406 }
407
408 /* Wait until the operation is completed */
409 do {
410 if (slot->state == PCI_SLOT_STATE_SPOWER_DONE)
411 break;
412
413 check_timers(false);
414 time_wait_ms(10);
415 } while (--wait >= 0);
416
417 if (wait < 0) {
418 PCINOTICE(phb, pd->bdfn, "Timeout powering %s slot\n",
419 state == PCI_SLOT_POWER_ON ? "on" : "off");
420 goto error;
421 }
422
423 success:
424 PCIDBG(phb, pd->bdfn, "Powering %s hotpluggable slot\n",
425 state == PCI_SLOT_POWER_ON ? "on" : "off");
426 error:
427 pci_slot_remove_flags(slot,
428 (PCI_SLOT_FLAG_BOOTUP | PCI_SLOT_FLAG_ENFORCE));
429 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
430 }
431
pci_bridge_power_on(struct phb * phb,struct pci_device * pd)432 static bool pci_bridge_power_on(struct phb *phb, struct pci_device *pd)
433 {
434 int32_t ecap;
435 uint16_t pcie_cap, slot_sts, slot_ctl, link_ctl;
436 uint32_t slot_cap;
437 int64_t rc;
438
439 /*
440 * If there is a PCI slot associated with the bridge, to use
441 * the PCI slot's facality to power it on.
442 */
443 if (pd->slot) {
444 struct pci_slot *slot = pd->slot;
445 uint8_t presence;
446
447 /*
448 * We assume the presence state is OPAL_PCI_SLOT_PRESENT
449 * by default. In this way, we won't miss anything when
450 * the operation isn't supported or hitting error upon
451 * retrieving it.
452 */
453 if (slot->ops.get_presence_state) {
454 rc = slot->ops.get_presence_state(slot, &presence);
455 if (rc == OPAL_SUCCESS &&
456 presence == OPAL_PCI_SLOT_EMPTY)
457 return false;
458 }
459
460 /* To power it on */
461 pci_slot_set_power_state(phb, pd, PCI_SLOT_POWER_ON);
462 return true;
463 }
464
465 if (!pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false))
466 return true;
467
468 /* Check if slot is supported */
469 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
470 pci_cfg_read16(phb, pd->bdfn,
471 ecap + PCICAP_EXP_CAPABILITY_REG, &pcie_cap);
472 if (!(pcie_cap & PCICAP_EXP_CAP_SLOT))
473 return true;
474
475 /* Check presence */
476 pci_cfg_read16(phb, pd->bdfn,
477 ecap + PCICAP_EXP_SLOTSTAT, &slot_sts);
478 if (!(slot_sts & PCICAP_EXP_SLOTSTAT_PDETECTST))
479 return false;
480
481 /* Ensure that power control is supported */
482 pci_cfg_read32(phb, pd->bdfn,
483 ecap + PCICAP_EXP_SLOTCAP, &slot_cap);
484 if (!(slot_cap & PCICAP_EXP_SLOTCAP_PWCTRL))
485 return true;
486
487
488 /* Read the slot control register, check if the slot is off */
489 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &slot_ctl);
490 PCITRACE(phb, pd->bdfn, " SLOT_CTL=%04x\n", slot_ctl);
491 if (slot_ctl & PCICAP_EXP_SLOTCTL_PWRCTLR) {
492 PCIDBG(phb, pd->bdfn, "Bridge power is off, turning on ...\n");
493 slot_ctl &= ~PCICAP_EXP_SLOTCTL_PWRCTLR;
494 slot_ctl |= SETFIELD(PCICAP_EXP_SLOTCTL_PWRI, 0, PCIE_INDIC_ON);
495 pci_cfg_write16(phb, pd->bdfn,
496 ecap + PCICAP_EXP_SLOTCTL, slot_ctl);
497
498 /* Wait a couple of seconds */
499 time_wait_ms(2000);
500 }
501
502 /* Enable link */
503 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_LCTL, &link_ctl);
504 PCITRACE(phb, pd->bdfn, " LINK_CTL=%04x\n", link_ctl);
505 link_ctl &= ~PCICAP_EXP_LCTL_LINK_DIS;
506 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_LCTL, link_ctl);
507
508 return true;
509 }
510
pci_bridge_wait_link(struct phb * phb,struct pci_device * pd,bool was_reset)511 static bool pci_bridge_wait_link(struct phb *phb,
512 struct pci_device *pd,
513 bool was_reset)
514 {
515 int32_t ecap = 0;
516 uint32_t link_cap = 0, retries = 100;
517 uint16_t link_sts;
518
519 if (pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false)) {
520 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
521 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_LCAP, &link_cap);
522 }
523
524 /*
525 * If link state reporting isn't supported, wait 1 second
526 * if the downstream link was ever resetted.
527 */
528 if (!(link_cap & PCICAP_EXP_LCAP_DL_ACT_REP)) {
529 if (was_reset)
530 time_wait_ms(1000);
531
532 return true;
533 }
534
535 /*
536 * Link state reporting is supported, wait for the link to
537 * come up until timeout.
538 */
539 PCIDBG(phb, pd->bdfn, "waiting for link... \n");
540 while (retries--) {
541 pci_cfg_read16(phb, pd->bdfn,
542 ecap + PCICAP_EXP_LSTAT, &link_sts);
543 if (link_sts & PCICAP_EXP_LSTAT_DLLL_ACT)
544 break;
545
546 time_wait_ms(100);
547 }
548
549 if (!(link_sts & PCICAP_EXP_LSTAT_DLLL_ACT)) {
550 PCIERR(phb, pd->bdfn, "Timeout waiting for downstream link\n");
551 return false;
552 }
553
554 /* Need another 100ms before touching the config space */
555 time_wait_ms(100);
556 PCIDBG(phb, pd->bdfn, "link is up\n");
557
558 return true;
559 }
560
561 /* pci_enable_bridge - Called before scanning a bridge
562 *
563 * Ensures error flags are clean, disable master abort, and
564 * check if the subordinate bus isn't reset, the slot is enabled
565 * on PCIe, etc...
566 */
pci_enable_bridge(struct phb * phb,struct pci_device * pd)567 static bool pci_enable_bridge(struct phb *phb, struct pci_device *pd)
568 {
569 uint16_t bctl;
570 bool was_reset = false;
571
572 /* Disable master aborts, clear errors */
573 pci_cfg_read16(phb, pd->bdfn, PCI_CFG_BRCTL, &bctl);
574 bctl &= ~PCI_CFG_BRCTL_MABORT_REPORT;
575 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_BRCTL, bctl);
576
577
578 /* PCI-E bridge, check the slot state. We don't do that on the
579 * root complex as this is handled separately and not all our
580 * RCs implement the standard register set.
581 */
582 if ((pd->dev_type == PCIE_TYPE_ROOT_PORT && pd->primary_bus > 0) ||
583 pd->dev_type == PCIE_TYPE_SWITCH_DNPORT) {
584 if (pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false)) {
585 int32_t ecap;
586 uint32_t link_cap = 0;
587 uint16_t link_sts = 0;
588
589 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
590 pci_cfg_read32(phb, pd->bdfn,
591 ecap + PCICAP_EXP_LCAP, &link_cap);
592
593 /*
594 * No need to touch the power supply if the PCIe link has
595 * been up. Further more, the slot presence bit is lost while
596 * the PCIe link is up on the specific PCI topology. In that
597 * case, we need ignore the slot presence bit and go ahead for
598 * probing. Otherwise, the NVMe adapter won't be probed.
599 *
600 * PHB3 root port, PLX switch 8748 (10b5:8748), PLX swich 9733
601 * (10b5:9733), PMC 8546 swtich (11f8:8546), NVMe adapter
602 * (1c58:0023).
603 */
604 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
605 pci_cfg_read32(phb, pd->bdfn,
606 ecap + PCICAP_EXP_LCAP, &link_cap);
607 pci_cfg_read16(phb, pd->bdfn,
608 ecap + PCICAP_EXP_LSTAT, &link_sts);
609 if ((link_cap & PCICAP_EXP_LCAP_DL_ACT_REP) &&
610 (link_sts & PCICAP_EXP_LSTAT_DLLL_ACT))
611 return true;
612 }
613
614 /* Power on the downstream slot or link */
615 if (!pci_bridge_power_on(phb, pd))
616 return false;
617 }
618
619 /* Clear secondary reset */
620 if (bctl & PCI_CFG_BRCTL_SECONDARY_RESET) {
621 PCIDBG(phb, pd->bdfn,
622 "Bridge secondary reset is on, clearing it ...\n");
623 bctl &= ~PCI_CFG_BRCTL_SECONDARY_RESET;
624 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_BRCTL, bctl);
625 time_wait_ms(1000);
626 was_reset = true;
627 }
628
629 /* PCI-E bridge, wait for link */
630 if (pd->dev_type == PCIE_TYPE_ROOT_PORT ||
631 pd->dev_type == PCIE_TYPE_SWITCH_DNPORT) {
632 if (!pci_bridge_wait_link(phb, pd, was_reset))
633 return false;
634 }
635
636 /* Clear error status */
637 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_STAT, 0xffff);
638 return true;
639 }
640
641 /* Clear up bridge resources */
pci_cleanup_bridge(struct phb * phb,struct pci_device * pd)642 static void pci_cleanup_bridge(struct phb *phb, struct pci_device *pd)
643 {
644 uint16_t cmd;
645
646 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_IO_BASE_U16, 0xffff);
647 pci_cfg_write8(phb, pd->bdfn, PCI_CFG_IO_BASE, 0xf0);
648 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_IO_LIMIT_U16, 0);
649 pci_cfg_write8(phb, pd->bdfn, PCI_CFG_IO_LIMIT, 0);
650 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_MEM_BASE, 0xfff0);
651 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_MEM_LIMIT, 0);
652 pci_cfg_write32(phb, pd->bdfn, PCI_CFG_PREF_MEM_BASE_U32, 0xffffffff);
653 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_PREF_MEM_BASE, 0xfff0);
654 pci_cfg_write32(phb, pd->bdfn, PCI_CFG_PREF_MEM_LIMIT_U32, 0);
655 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_PREF_MEM_LIMIT, 0);
656
657 /* Note: This is a bit fishy but since we have closed all the
658 * bridge windows above, it shouldn't be a problem. Basically
659 * we enable Memory, IO and Bus Master on the bridge because
660 * some versions of Linux will fail to do it themselves.
661 */
662 pci_cfg_read16(phb, pd->bdfn, PCI_CFG_CMD, &cmd);
663 cmd |= PCI_CFG_CMD_IO_EN | PCI_CFG_CMD_MEM_EN;
664 cmd |= PCI_CFG_CMD_BUS_MASTER_EN;
665 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_CMD, cmd);
666 }
667
668 /* Remove all subordinate PCI devices leading from the indicated
669 * PCI bus. It's used to remove all PCI devices behind one PCI
670 * slot at unplugging time
671 */
pci_remove_bus(struct phb * phb,struct list_head * list)672 void pci_remove_bus(struct phb *phb, struct list_head *list)
673 {
674 struct pci_device *pd, *tmp;
675
676 list_for_each_safe(list, pd, tmp, link) {
677 pci_remove_bus(phb, &pd->children);
678
679 if (phb->ops->device_remove)
680 phb->ops->device_remove(phb, pd);
681
682 /* Release device node and PCI slot */
683 if (pd->dn)
684 dt_free(pd->dn);
685 if (pd->slot)
686 free(pd->slot);
687
688 /* Remove from parent list and release itself */
689 list_del(&pd->link);
690 free(pd);
691 }
692 }
693
pci_set_power_limit(struct pci_device * pd)694 static void pci_set_power_limit(struct pci_device *pd)
695 {
696 uint32_t offset, val;
697 uint16_t caps;
698
699 offset = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
700 if (!offset)
701 return; /* legacy dev */
702
703 pci_cfg_read16(pd->phb, pd->bdfn,
704 offset + PCICAP_EXP_CAPABILITY_REG, &caps);
705
706 if (!(caps & PCICAP_EXP_CAP_SLOT))
707 return; /* bridge has no slot capabilities */
708 if (!pd->slot || !pd->slot->power_limit)
709 return;
710
711 pci_cfg_read32(pd->phb, pd->bdfn, offset + PCICAP_EXP_SLOTCAP, &val);
712
713 val = SETFIELD(PCICAP_EXP_SLOTCAP_SPLSC, val, 0); /* 1W scale */
714 val = SETFIELD(PCICAP_EXP_SLOTCAP_SPLVA, val, pd->slot->power_limit);
715
716 pci_cfg_write32(pd->phb, pd->bdfn, offset + PCICAP_EXP_SLOTCAP, val);
717
718 /* update the cached copy in the slot */
719 pd->slot->slot_cap = val;
720
721 PCIDBG(pd->phb, pd->bdfn, "Slot power limit set to %dW\n",
722 pd->slot->power_limit);
723 }
724
725 /* Perform a recursive scan of the bus at bus_number populating
726 * the list passed as an argument. This also performs the bus
727 * numbering, so it returns the largest bus number that was
728 * assigned.
729 *
730 * Note: Eventually this might want to access some VPD information
731 * in order to know what slots to scan and what not etc..
732 *
733 * XXX NOTE: We might want to enable ARI along the way...
734 *
735 * XXX NOTE: We might also want to setup the PCIe MPS/MRSS properly
736 * here as Linux may or may not do it
737 */
pci_scan_bus(struct phb * phb,uint8_t bus,uint8_t max_bus,struct list_head * list,struct pci_device * parent,bool scan_downstream)738 uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
739 struct list_head *list, struct pci_device *parent,
740 bool scan_downstream)
741 {
742 struct pci_device *pd = NULL, *rc = NULL;
743 uint8_t dev, fn, next_bus, max_sub, save_max;
744 uint32_t scan_map;
745 bool use_max;
746
747 /* Decide what to scan */
748 scan_map = parent ? parent->scan_map : phb->scan_map;
749
750 /* Do scan */
751 for (dev = 0; dev < 32; dev++) {
752 if (!(scan_map & (1ul << dev)))
753 continue;
754
755 /* Scan the device */
756 pd = pci_scan_one(phb, parent, (bus << 8) | (dev << 3));
757 pci_check_clear_freeze(phb);
758 if (!pd)
759 continue;
760
761 /* Record RC when its downstream link is down */
762 if (!scan_downstream && dev == 0 && !rc)
763 rc = pd;
764
765 /* XXX Handle ARI */
766 if (!pd->is_multifunction)
767 continue;
768 for (fn = 1; fn < 8; fn++) {
769 pd = pci_scan_one(phb, parent,
770 ((uint16_t)bus << 8) | (dev << 3) | fn);
771 pci_check_clear_freeze(phb);
772 }
773 }
774
775 /* Reserve all possible buses if RC's downstream link is down
776 * if PCI hotplug is supported.
777 */
778 if (rc && rc->slot && rc->slot->pluggable) {
779 next_bus = phb->ops->choose_bus(phb, rc, bus + 1,
780 &max_bus, &use_max);
781 rc->secondary_bus = next_bus;
782 rc->subordinate_bus = max_bus;
783 pci_cfg_write8(phb, rc->bdfn, PCI_CFG_SECONDARY_BUS,
784 rc->secondary_bus);
785 pci_cfg_write8(phb, rc->bdfn, PCI_CFG_SUBORDINATE_BUS,
786 rc->subordinate_bus);
787 }
788
789 /* set the power limit for any downstream slots while we're here */
790 list_for_each(list, pd, link) {
791 if (pd->is_bridge)
792 pci_set_power_limit(pd);
793 }
794
795 /*
796 * We only scan downstream if instructed to do so by the
797 * caller. Typically we avoid the scan when we know the
798 * link is down already, which happens for the top level
799 * root complex, and avoids a long secondary timeout
800 */
801 if (!scan_downstream) {
802 list_for_each(list, pd, link)
803 pci_slot_set_power_state(phb, pd, PCI_SLOT_POWER_OFF);
804
805 return bus;
806 }
807
808 next_bus = bus + 1;
809 max_sub = bus;
810 save_max = max_bus;
811
812 /* Scan down bridges */
813 list_for_each(list, pd, link) {
814 bool do_scan;
815
816 if (!pd->is_bridge)
817 continue;
818
819 /* We need to figure out a new bus number to start from.
820 *
821 * This can be tricky due to our HW constraints which differ
822 * from bridge to bridge so we are going to let the phb
823 * driver decide what to do. This can return us a maximum
824 * bus number to assign as well
825 *
826 * This function will:
827 *
828 * - Return the bus number to use as secondary for the
829 * bridge or 0 for a failure
830 *
831 * - "max_bus" will be adjusted to represent the max
832 * subordinate that can be associated with the downstream
833 * device
834 *
835 * - "use_max" will be set to true if the returned max_bus
836 * *must* be used as the subordinate bus number of that
837 * bridge (when we need to give aligned powers of two's
838 * on P7IOC). If is is set to false, we just adjust the
839 * subordinate bus number based on what we probed.
840 *
841 */
842 max_bus = save_max;
843 next_bus = phb->ops->choose_bus(phb, pd, next_bus,
844 &max_bus, &use_max);
845
846 /* Configure the bridge with the returned values */
847 if (next_bus <= bus) {
848 PCIERR(phb, pd->bdfn, "Out of bus numbers !\n");
849 max_bus = next_bus = 0; /* Failure case */
850 }
851
852 pd->secondary_bus = next_bus;
853 pd->subordinate_bus = max_bus;
854 pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SECONDARY_BUS, next_bus);
855 pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SUBORDINATE_BUS, max_bus);
856 if (!next_bus)
857 break;
858
859 PCIDBG(phb, pd->bdfn, "Bus %02x..%02x %s scanning...\n",
860 next_bus, max_bus, use_max ? "[use max]" : "");
861
862 /* Clear up bridge resources */
863 pci_cleanup_bridge(phb, pd);
864
865 /* Configure the bridge. This will enable power to the slot
866 * if it's currently disabled, lift reset, etc...
867 *
868 * Return false if we know there's nothing behind the bridge
869 */
870 do_scan = pci_enable_bridge(phb, pd);
871
872 /* Perform recursive scan */
873 if (do_scan) {
874 max_sub = pci_scan_bus(phb, next_bus, max_bus,
875 &pd->children, pd, true);
876 } else if (!use_max) {
877 /* Empty bridge. We leave room for hotplug
878 * slots if the downstream port is pluggable.
879 */
880 if (pd->slot && !pd->slot->pluggable)
881 max_sub = next_bus;
882 else {
883 max_sub = next_bus + 4;
884 if (max_sub > max_bus)
885 max_sub = max_bus;
886 }
887 }
888
889 /* Update the max subordinate as described previously */
890 if (use_max)
891 max_sub = max_bus;
892 pd->subordinate_bus = max_sub;
893 pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SUBORDINATE_BUS, max_sub);
894 next_bus = max_sub + 1;
895
896 /* power off the slot if there's nothing below it */
897 if (list_empty(&pd->children))
898 pci_slot_set_power_state(phb, pd, PCI_SLOT_POWER_OFF);
899 }
900
901 return max_sub;
902 }
903
pci_get_mps(struct phb * phb,struct pci_device * pd,void * userdata)904 static int pci_get_mps(struct phb *phb,
905 struct pci_device *pd, void *userdata)
906 {
907 uint32_t *mps = (uint32_t *)userdata;
908
909 /* Only check PCI device that had MPS capacity */
910 if (phb && pd && pd->mps && *mps > pd->mps)
911 *mps = pd->mps;
912
913 return 0;
914 }
915
pci_configure_mps(struct phb * phb,struct pci_device * pd,void * userdata __unused)916 static int pci_configure_mps(struct phb *phb,
917 struct pci_device *pd,
918 void *userdata __unused)
919 {
920 uint32_t ecap, aercap, mps;
921 uint16_t val;
922
923 assert(phb);
924 assert(pd);
925
926 /* If the MPS isn't acceptable one, bail immediately */
927 mps = phb->mps;
928 if (mps < 128 || mps > 4096)
929 return 1;
930
931 /* Retrieve PCIe and AER capability */
932 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
933 aercap = pci_cap(pd, PCIECAP_ID_AER, true);
934
935 /* PCIe device always has MPS capacity */
936 if (pd->mps) {
937 mps = ilog2(mps) - 7;
938
939 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVCTL, &val);
940 val = SETFIELD(PCICAP_EXP_DEVCTL_MPS, val, mps);
941 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVCTL, val);
942 }
943
944 /* Changing MPS on upstream PCI bridge might cause some error
945 * bits in PCIe and AER capability. To clear them to avoid
946 * confusion.
947 */
948 if (aercap) {
949 pci_cfg_write32(phb, pd->bdfn, aercap + PCIECAP_AER_UE_STATUS,
950 0xffffffff);
951 pci_cfg_write32(phb, pd->bdfn, aercap + PCIECAP_AER_CE_STATUS,
952 0xffffffff);
953 }
954 if (ecap)
955 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVSTAT, 0xf);
956
957 return 0;
958 }
959
pci_disable_completion_timeout(struct phb * phb,struct pci_device * pd)960 static void pci_disable_completion_timeout(struct phb *phb, struct pci_device *pd)
961 {
962 uint32_t ecap;
963 uint32_t val;
964
965 /* PCIE capability required */
966 if (!pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false))
967 return;
968
969 /* Check if it has capability to disable completion timeout */
970 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
971 pci_cfg_read32(phb, pd->bdfn, ecap + PCIECAP_EXP_DCAP2, &val);
972 if (!(val & PCICAP_EXP_DCAP2_CMPTOUT_DIS))
973 return;
974
975 /* Disable completion timeout without more check */
976 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_DCTL2, &val);
977 val |= PCICAP_EXP_DCTL2_CMPTOUT_DIS;
978 pci_cfg_write32(phb, pd->bdfn, ecap + PCICAP_EXP_DCTL2, val);
979 }
980
pci_device_init(struct phb * phb,struct pci_device * pd)981 void pci_device_init(struct phb *phb, struct pci_device *pd)
982 {
983 pci_configure_mps(phb, pd, NULL);
984 pci_disable_completion_timeout(phb, pd);
985 }
986
pci_reset_phb(void * data)987 static void pci_reset_phb(void *data)
988 {
989 struct phb *phb = data;
990 struct pci_slot *slot = phb->slot;
991 int64_t rc;
992
993 if (!slot || !slot->ops.run_sm) {
994 PCINOTICE(phb, 0, "Cannot issue reset\n");
995 return;
996 }
997
998 pci_slot_add_flags(slot, PCI_SLOT_FLAG_BOOTUP);
999 rc = slot->ops.run_sm(slot);
1000 while (rc > 0) {
1001 PCITRACE(phb, 0, "Waiting %ld ms\n", tb_to_msecs(rc));
1002 time_wait(rc);
1003 rc = slot->ops.run_sm(slot);
1004 }
1005 pci_slot_remove_flags(slot, PCI_SLOT_FLAG_BOOTUP);
1006 if (rc < 0)
1007 PCIDBG(phb, 0, "Error %lld resetting\n", rc);
1008 }
1009
pci_scan_phb(void * data)1010 static void pci_scan_phb(void *data)
1011 {
1012 struct phb *phb = data;
1013 struct pci_slot *slot = phb->slot;
1014 uint8_t link;
1015 uint32_t mps = 0xffffffff;
1016 int64_t rc;
1017
1018 if (!slot || !slot->ops.get_link_state) {
1019 PCIERR(phb, 0, "Cannot query link status\n");
1020 link = 0;
1021 } else {
1022 rc = slot->ops.get_link_state(slot, &link);
1023 if (rc != OPAL_SUCCESS) {
1024 PCIERR(phb, 0, "Error %lld querying link status\n",
1025 rc);
1026 link = 0;
1027 }
1028 }
1029
1030 if (!link)
1031 PCIDBG(phb, 0, "Link down\n");
1032 else
1033 PCIDBG(phb, 0, "Link up at x%d width\n", link);
1034
1035 /* Scan root port and downstream ports if applicable */
1036 PCIDBG(phb, 0, "Scanning (upstream%s)...\n",
1037 link ? "+downsteam" : " only");
1038 pci_scan_bus(phb, 0, 0xff, &phb->devices, NULL, link);
1039
1040 /* Configure MPS (Max Payload Size) for PCIe domain */
1041 pci_walk_dev(phb, NULL, pci_get_mps, &mps);
1042 phb->mps = mps;
1043 pci_walk_dev(phb, NULL, pci_configure_mps, NULL);
1044 }
1045
pci_register_phb(struct phb * phb,int opal_id)1046 int64_t pci_register_phb(struct phb *phb, int opal_id)
1047 {
1048 /* The user didn't specify an opal_id, allocate one */
1049 if (opal_id == OPAL_DYNAMIC_PHB_ID) {
1050 /* This is called at init time in non-concurrent way, so no lock needed */
1051 for (opal_id = 0; opal_id < ARRAY_SIZE(phbs); opal_id++)
1052 if (!phbs[opal_id])
1053 break;
1054 if (opal_id >= ARRAY_SIZE(phbs)) {
1055 prerror("PHB: Failed to find a free ID slot\n");
1056 return OPAL_RESOURCE;
1057 }
1058 } else {
1059 if (opal_id >= ARRAY_SIZE(phbs)) {
1060 prerror("PHB: ID %x out of range !\n", opal_id);
1061 return OPAL_PARAMETER;
1062 }
1063 /* The user did specify an opal_id, check it's free */
1064 if (phbs[opal_id]) {
1065 prerror("PHB: Duplicate registration of ID %x\n", opal_id);
1066 return OPAL_PARAMETER;
1067 }
1068 }
1069
1070 phbs[opal_id] = phb;
1071 phb->opal_id = opal_id;
1072 if (opal_id > last_phb_id)
1073 last_phb_id = opal_id;
1074 dt_add_property_cells(phb->dt_node, "ibm,opal-phbid", 0, phb->opal_id);
1075 PCIDBG(phb, 0, "PCI: Registered PHB\n");
1076
1077 init_lock(&phb->lock);
1078 list_head_init(&phb->devices);
1079
1080 phb->filter_map = zalloc(BITMAP_BYTES(0x10000));
1081 assert(phb->filter_map);
1082
1083 return OPAL_SUCCESS;
1084 }
1085
pci_unregister_phb(struct phb * phb)1086 int64_t pci_unregister_phb(struct phb *phb)
1087 {
1088 /* XXX We want some kind of RCU or RWlock to make things
1089 * like that happen while no OPAL callback is in progress,
1090 * that way we avoid taking a lock in each of them.
1091 *
1092 * Right now we don't unregister so we are fine
1093 */
1094 phbs[phb->opal_id] = phb;
1095
1096 return OPAL_SUCCESS;
1097 }
1098
pci_get_phb(uint64_t phb_id)1099 struct phb *pci_get_phb(uint64_t phb_id)
1100 {
1101 if (phb_id >= ARRAY_SIZE(phbs))
1102 return NULL;
1103
1104 /* XXX See comment in pci_unregister_phb() about locking etc... */
1105 return phbs[phb_id];
1106 }
1107
pci_class_name(uint32_t class_code)1108 static const char *pci_class_name(uint32_t class_code)
1109 {
1110 uint8_t class = class_code >> 16;
1111 uint8_t sub = (class_code >> 8) & 0xff;
1112 uint8_t pif = class_code & 0xff;
1113
1114 switch(class) {
1115 case 0x00:
1116 switch(sub) {
1117 case 0x00: return "device";
1118 case 0x01: return "vga";
1119 }
1120 break;
1121 case 0x01:
1122 switch(sub) {
1123 case 0x00: return "scsi";
1124 case 0x01: return "ide";
1125 case 0x02: return "fdc";
1126 case 0x03: return "ipi";
1127 case 0x04: return "raid";
1128 case 0x05: return "ata";
1129 case 0x06: return "sata";
1130 case 0x07: return "sas";
1131 default: return "mass-storage";
1132 }
1133 case 0x02:
1134 switch(sub) {
1135 case 0x00: return "ethernet";
1136 case 0x01: return "token-ring";
1137 case 0x02: return "fddi";
1138 case 0x03: return "atm";
1139 case 0x04: return "isdn";
1140 case 0x05: return "worldfip";
1141 case 0x06: return "picmg";
1142 default: return "network";
1143 }
1144 case 0x03:
1145 switch(sub) {
1146 case 0x00: return "vga";
1147 case 0x01: return "xga";
1148 case 0x02: return "3d-controller";
1149 default: return "display";
1150 }
1151 case 0x04:
1152 switch(sub) {
1153 case 0x00: return "video";
1154 case 0x01: return "sound";
1155 case 0x02: return "telephony";
1156 default: return "multimedia-device";
1157 }
1158 case 0x05:
1159 switch(sub) {
1160 case 0x00: return "memory";
1161 case 0x01: return "flash";
1162 default: return "memory-controller";
1163 }
1164 case 0x06:
1165 switch(sub) {
1166 case 0x00: return "host";
1167 case 0x01: return "isa";
1168 case 0x02: return "eisa";
1169 case 0x03: return "mca";
1170 case 0x04: return "pci";
1171 case 0x05: return "pcmcia";
1172 case 0x06: return "nubus";
1173 case 0x07: return "cardbus";
1174 case 0x08: return "raceway";
1175 case 0x09: return "semi-transparent-pci";
1176 case 0x0a: return "infiniband";
1177 default: return "unknown-bridge";
1178 }
1179 case 0x07:
1180 switch(sub) {
1181 case 0x00:
1182 switch(pif) {
1183 case 0x01: return "16450-serial";
1184 case 0x02: return "16550-serial";
1185 case 0x03: return "16650-serial";
1186 case 0x04: return "16750-serial";
1187 case 0x05: return "16850-serial";
1188 case 0x06: return "16950-serial";
1189 default: return "serial";
1190 }
1191 case 0x01:
1192 switch(pif) {
1193 case 0x01: return "bi-directional-parallel";
1194 case 0x02: return "ecp-1.x-parallel";
1195 case 0x03: return "ieee1284-controller";
1196 case 0xfe: return "ieee1284-device";
1197 default: return "parallel";
1198 }
1199 case 0x02: return "multiport-serial";
1200 case 0x03:
1201 switch(pif) {
1202 case 0x01: return "16450-modem";
1203 case 0x02: return "16550-modem";
1204 case 0x03: return "16650-modem";
1205 case 0x04: return "16750-modem";
1206 default: return "modem";
1207 }
1208 case 0x04: return "gpib";
1209 case 0x05: return "smart-card";
1210 default: return "communication-controller";
1211 }
1212 case 0x08:
1213 switch(sub) {
1214 case 0x00:
1215 switch(pif) {
1216 case 0x01: return "isa-pic";
1217 case 0x02: return "eisa-pic";
1218 case 0x10: return "io-apic";
1219 case 0x20: return "iox-apic";
1220 default: return "interrupt-controller";
1221 }
1222 case 0x01:
1223 switch(pif) {
1224 case 0x01: return "isa-dma";
1225 case 0x02: return "eisa-dma";
1226 default: return "dma-controller";
1227 }
1228 case 0x02:
1229 switch(pif) {
1230 case 0x01: return "isa-system-timer";
1231 case 0x02: return "eisa-system-timer";
1232 default: return "timer";
1233 }
1234 case 0x03:
1235 switch(pif) {
1236 case 0x01: return "isa-rtc";
1237 default: return "rtc";
1238 }
1239 case 0x04: return "hotplug-controller";
1240 case 0x05: return "sd-host-controller";
1241 default: return "system-peripheral";
1242 }
1243 case 0x09:
1244 switch(sub) {
1245 case 0x00: return "keyboard";
1246 case 0x01: return "pen";
1247 case 0x02: return "mouse";
1248 case 0x03: return "scanner";
1249 case 0x04: return "gameport";
1250 default: return "input-controller";
1251 }
1252 case 0x0a:
1253 switch(sub) {
1254 case 0x00: return "clock";
1255 default: return "docking-station";
1256 }
1257 case 0x0b:
1258 switch(sub) {
1259 case 0x00: return "386";
1260 case 0x01: return "486";
1261 case 0x02: return "pentium";
1262 case 0x10: return "alpha";
1263 case 0x20: return "powerpc";
1264 case 0x30: return "mips";
1265 case 0x40: return "co-processor";
1266 default: return "cpu";
1267 }
1268 case 0x0c:
1269 switch(sub) {
1270 case 0x00: return "firewire";
1271 case 0x01: return "access-bus";
1272 case 0x02: return "ssa";
1273 case 0x03:
1274 switch(pif) {
1275 case 0x00: return "usb-uhci";
1276 case 0x10: return "usb-ohci";
1277 case 0x20: return "usb-ehci";
1278 case 0x30: return "usb-xhci";
1279 case 0xfe: return "usb-device";
1280 default: return "usb";
1281 }
1282 case 0x04: return "fibre-channel";
1283 case 0x05: return "smb";
1284 case 0x06: return "infiniband";
1285 case 0x07:
1286 switch(pif) {
1287 case 0x00: return "impi-smic";
1288 case 0x01: return "impi-kbrd";
1289 case 0x02: return "impi-bltr";
1290 default: return "impi";
1291 }
1292 case 0x08: return "secos";
1293 case 0x09: return "canbus";
1294 default: return "serial-bus";
1295 }
1296 case 0x0d:
1297 switch(sub) {
1298 case 0x00: return "irda";
1299 case 0x01: return "consumer-ir";
1300 case 0x10: return "rf-controller";
1301 case 0x11: return "bluetooth";
1302 case 0x12: return "broadband";
1303 case 0x20: return "enet-802.11a";
1304 case 0x21: return "enet-802.11b";
1305 default: return "wireless-controller";
1306 }
1307 case 0x0e: return "intelligent-controller";
1308 case 0x0f:
1309 switch(sub) {
1310 case 0x01: return "satellite-tv";
1311 case 0x02: return "satellite-audio";
1312 case 0x03: return "satellite-voice";
1313 case 0x04: return "satellite-data";
1314 default: return "satellite-device";
1315 }
1316 case 0x10:
1317 switch(sub) {
1318 case 0x00: return "network-encryption";
1319 case 0x01: return "entertainment-encryption";
1320 default: return "encryption";
1321 }
1322 case 0x011:
1323 switch(sub) {
1324 case 0x00: return "dpio";
1325 case 0x01: return "counter";
1326 case 0x10: return "measurement";
1327 case 0x20: return "management-card";
1328 default: return "data-processing";
1329 }
1330 }
1331 return "device";
1332 }
1333
pci_std_swizzle_irq_map(struct dt_node * np,struct pci_device * pd,struct pci_lsi_state * lstate,uint8_t swizzle)1334 void pci_std_swizzle_irq_map(struct dt_node *np,
1335 struct pci_device *pd,
1336 struct pci_lsi_state *lstate,
1337 uint8_t swizzle)
1338 {
1339 uint32_t *map, *p;
1340 int dev, irq, esize, edevcount;
1341 size_t map_size, isize;
1342
1343 /* Some emulated setups don't use standard interrupts
1344 * representation
1345 */
1346 if (lstate->int_size == 0)
1347 return;
1348
1349 /* Size in bytes of a target interrupt */
1350 isize = lstate->int_size * sizeof(uint32_t);
1351
1352 /* Calculate the size of a map entry:
1353 *
1354 * 3 cells : PCI Address
1355 * 1 cell : PCI IRQ
1356 * 1 cell : PIC phandle
1357 * n cells : PIC irq (n = lstate->int_size)
1358 *
1359 * Assumption: PIC address is 0-size
1360 */
1361 esize = 3 + 1 + 1 + lstate->int_size;
1362
1363 /* Number of map "device" entries
1364 *
1365 * A PCI Express root or downstream port needs only one
1366 * entry for device 0. Anything else will get a full map
1367 * for all possible 32 child device numbers
1368 *
1369 * If we have been passed a host bridge (pd == NULL) we also
1370 * do a simple per-pin map
1371 */
1372 if (!pd || (pd->dev_type == PCIE_TYPE_ROOT_PORT ||
1373 pd->dev_type == PCIE_TYPE_SWITCH_DNPORT)) {
1374 edevcount = 1;
1375 dt_add_property_cells(np, "interrupt-map-mask", 0, 0, 0, 7);
1376 } else {
1377 edevcount = 32;
1378 dt_add_property_cells(np, "interrupt-map-mask",
1379 0xf800, 0, 0, 7);
1380 }
1381 map_size = esize * edevcount * 4 * sizeof(uint32_t);
1382 map = p = zalloc(map_size);
1383 if (!map) {
1384 prerror("Failed to allocate interrupt-map-mask !\n");
1385 return;
1386 }
1387
1388 for (dev = 0; dev < edevcount; dev++) {
1389 for (irq = 0; irq < 4; irq++) {
1390 /* Calculate pin */
1391 uint32_t new_irq = (irq + dev + swizzle) % 4;
1392
1393 /* PCI address portion */
1394 *(p++) = dev << (8 + 3);
1395 *(p++) = 0;
1396 *(p++) = 0;
1397
1398 /* PCI interrupt portion */
1399 *(p++) = irq + 1;
1400
1401 /* Parent phandle */
1402 *(p++) = lstate->int_parent[new_irq];
1403
1404 /* Parent desc */
1405 memcpy(p, lstate->int_val[new_irq], isize);
1406 p += lstate->int_size;
1407 }
1408 }
1409
1410 dt_add_property(np, "interrupt-map", map, map_size);
1411 free(map);
1412 }
1413
pci_add_loc_code(struct dt_node * np,struct pci_device * pd)1414 static void pci_add_loc_code(struct dt_node *np, struct pci_device *pd)
1415 {
1416 struct dt_node *p = np->parent;
1417 const char *blcode = NULL;
1418 char *lcode;
1419 uint32_t class_code;
1420 uint8_t class, sub;
1421 uint8_t pos, len;
1422
1423 while (p) {
1424 /* if we have a slot label (i.e. openpower) use that */
1425 blcode = dt_prop_get_def(p, "ibm,slot-label", NULL);
1426 if (blcode)
1427 break;
1428
1429 /* otherwise use the fully qualified location code */
1430 blcode = dt_prop_get_def(p, "ibm,slot-location-code", NULL);
1431 if (blcode)
1432 break;
1433
1434 p = p->parent;
1435 }
1436
1437 if (!blcode)
1438 blcode = dt_prop_get_def(np, "ibm,slot-location-code", NULL);
1439
1440 if (!blcode) {
1441 /* Fall back to finding a ibm,loc-code */
1442 p = np->parent;
1443
1444 while (p) {
1445 blcode = dt_prop_get_def(p, "ibm,loc-code", NULL);
1446 if (blcode)
1447 break;
1448 p = p->parent;
1449 }
1450 }
1451
1452 if (!blcode)
1453 return;
1454
1455 /* ethernet devices get port codes */
1456 class_code = dt_prop_get_u32(np, "class-code");
1457 class = class_code >> 16;
1458 sub = (class_code >> 8) & 0xff;
1459
1460 /* XXX Don't do that on openpower for now, we will need to sort things
1461 * out later, otherwise the mezzanine slot on Habanero gets weird results
1462 */
1463 if (class == 0x02 && sub == 0x00 && !platform.bmc) {
1464 /* There's usually several spaces at the end of the property.
1465 Test for, but don't rely on, that being the case */
1466 len = strlen(blcode);
1467 for (pos = 0; pos < len; pos++)
1468 if (blcode[pos] == ' ') break;
1469 if (pos + 3 < len)
1470 lcode = strdup(blcode);
1471 else {
1472 lcode = malloc(pos + 3);
1473 memcpy(lcode, blcode, len);
1474 }
1475 lcode[pos++] = '-';
1476 lcode[pos++] = 'T';
1477 lcode[pos++] = (char)(pd->bdfn & 0x7) + '1';
1478 lcode[pos++] = '\0';
1479 dt_add_property_string(np, "ibm,loc-code", lcode);
1480 free(lcode);
1481 } else
1482 dt_add_property_string(np, "ibm,loc-code", blcode);
1483 }
1484
pci_print_summary_line(struct phb * phb,struct pci_device * pd,struct dt_node * np,u32 rev_class,const char * cname)1485 static void pci_print_summary_line(struct phb *phb, struct pci_device *pd,
1486 struct dt_node *np, u32 rev_class,
1487 const char *cname)
1488 {
1489 const char *label, *dtype, *s;
1490 u32 vdid;
1491 #define MAX_SLOTSTR 80
1492 char slotstr[MAX_SLOTSTR + 1] = { 0, };
1493
1494 pci_cfg_read32(phb, pd->bdfn, 0, &vdid);
1495
1496 /* If it's a slot, it has a slot-label */
1497 label = dt_prop_get_def(np, "ibm,slot-label", NULL);
1498 if (label) {
1499 u32 lanes = dt_prop_get_u32_def(np, "ibm,slot-wired-lanes", 0);
1500 static const char *lanestrs[] = {
1501 "", " x1", " x2", " x4", " x8", "x16", "x32", "32b", "64b"
1502 };
1503 const char *lstr = lanes > PCI_SLOT_WIRED_LANES_PCIX_64 ? "" : lanestrs[lanes];
1504 snprintf(slotstr, MAX_SLOTSTR, "SLOT=%3s %s", label, lstr);
1505 /* XXX Add more slot info */
1506 } else {
1507 /*
1508 * No label, ignore downstream switch legs and root complex,
1509 * Those would essentially be non-populated
1510 */
1511 if (pd->dev_type != PCIE_TYPE_ROOT_PORT &&
1512 pd->dev_type != PCIE_TYPE_SWITCH_DNPORT) {
1513 /* It's a mere device, get loc code */
1514 s = dt_prop_get_def(np, "ibm,loc-code", NULL);
1515 if (s)
1516 snprintf(slotstr, MAX_SLOTSTR, "LOC_CODE=%s", s);
1517 }
1518 }
1519
1520 if (pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false)) {
1521 static const char *pcie_types[] = {
1522 "EP ", "LGCY", "????", "????", "ROOT", "SWUP", "SWDN",
1523 "ETOX", "XTOE", "RINT", "EVTC" };
1524 if (pd->dev_type >= ARRAY_SIZE(pcie_types))
1525 dtype = "????";
1526 else
1527 dtype = pcie_types[pd->dev_type];
1528 } else
1529 dtype = pd->is_bridge ? "PCIB" : "PCID";
1530
1531 if (pd->is_bridge)
1532 PCINOTICE(phb, pd->bdfn,
1533 "[%s] %04x %04x R:%02x C:%06x B:%02x..%02x %s\n",
1534 dtype, vdid & 0xffff, vdid >> 16,
1535 rev_class & 0xff, rev_class >> 8, pd->secondary_bus,
1536 pd->subordinate_bus, slotstr);
1537 else
1538 PCINOTICE(phb, pd->bdfn,
1539 "[%s] %04x %04x R:%02x C:%06x (%14s) %s\n",
1540 dtype, vdid & 0xffff, vdid >> 16,
1541 rev_class & 0xff, rev_class >> 8, cname, slotstr);
1542 }
1543
pci_add_one_device_node(struct phb * phb,struct pci_device * pd,struct dt_node * parent_node,struct pci_lsi_state * lstate,uint8_t swizzle)1544 static void __noinline pci_add_one_device_node(struct phb *phb,
1545 struct pci_device *pd,
1546 struct dt_node *parent_node,
1547 struct pci_lsi_state *lstate,
1548 uint8_t swizzle)
1549 {
1550 struct dt_node *np;
1551 const char *cname;
1552 #define MAX_NAME 256
1553 char name[MAX_NAME];
1554 char compat[MAX_NAME];
1555 uint32_t rev_class, vdid;
1556 uint32_t reg[5];
1557 uint8_t intpin;
1558 bool is_pcie;
1559 const uint32_t ranges_direct[] = {
1560 /* 64-bit direct mapping. We know the bridges
1561 * don't cover the entire address space so
1562 * use 0xf00... as a good compromise. */
1563 0x02000000, 0x0, 0x0,
1564 0x02000000, 0x0, 0x0,
1565 0xf0000000, 0x0};
1566
1567 pci_cfg_read32(phb, pd->bdfn, 0, &vdid);
1568 pci_cfg_read32(phb, pd->bdfn, PCI_CFG_REV_ID, &rev_class);
1569 pci_cfg_read8(phb, pd->bdfn, PCI_CFG_INT_PIN, &intpin);
1570 is_pcie = pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false);
1571
1572 /*
1573 * Some IBM PHBs (p7ioc?) have an invalid PCI class code. Linux
1574 * uses prefers to read the class code from the DT rather than
1575 * re-reading config space we can hack around it here.
1576 */
1577 if (is_pcie && parent_node == phb->dt_node)
1578 rev_class = (rev_class & 0xff) | 0x6040000;
1579 cname = pci_class_name(rev_class >> 8);
1580
1581 if (pd->bdfn & 0x7)
1582 snprintf(name, MAX_NAME - 1, "%s@%x,%x",
1583 cname, (pd->bdfn >> 3) & 0x1f, pd->bdfn & 0x7);
1584 else
1585 snprintf(name, MAX_NAME - 1, "%s@%x",
1586 cname, (pd->bdfn >> 3) & 0x1f);
1587 pd->dn = np = dt_new(parent_node, name);
1588
1589 /*
1590 * NB: ibm,pci-config-space-type is the PAPR way of indicating the
1591 * device has a 4KB config space. It's got nothing to do with the
1592 * standard Type 0/1 config spaces defined by PCI.
1593 */
1594 if (is_pcie || phb->phb_type == phb_type_npu_v2_opencapi) {
1595 snprintf(compat, MAX_NAME, "pciex%x,%x",
1596 vdid & 0xffff, vdid >> 16);
1597 dt_add_property_cells(np, "ibm,pci-config-space-type", 1);
1598 } else {
1599 snprintf(compat, MAX_NAME, "pci%x,%x",
1600 vdid & 0xffff, vdid >> 16);
1601 dt_add_property_cells(np, "ibm,pci-config-space-type", 0);
1602 }
1603 dt_add_property_cells(np, "class-code", rev_class >> 8);
1604 dt_add_property_cells(np, "revision-id", rev_class & 0xff);
1605 dt_add_property_cells(np, "vendor-id", vdid & 0xffff);
1606 dt_add_property_cells(np, "device-id", vdid >> 16);
1607 if (intpin)
1608 dt_add_property_cells(np, "interrupts", intpin);
1609
1610 pci_handle_quirk(phb, pd);
1611
1612 /* XXX FIXME: Add a few missing ones such as
1613 *
1614 * - devsel-speed (!express)
1615 * - max-latency
1616 * - min-grant
1617 * - subsystem-id
1618 * - subsystem-vendor-id
1619 * - ...
1620 */
1621
1622 /* Add slot properties if needed and iff this is a bridge */
1623 if (pd->slot)
1624 pci_slot_add_dt_properties(pd->slot, np);
1625
1626 /*
1627 * Use the phb base location code for root ports if the platform
1628 * doesn't provide one via slot->add_properties() operation.
1629 */
1630 if (pd->dev_type == PCIE_TYPE_ROOT_PORT && phb->base_loc_code &&
1631 !dt_has_node_property(np, "ibm,slot-location-code", NULL))
1632 dt_add_property_string(np, "ibm,slot-location-code",
1633 phb->base_loc_code);
1634
1635 /* Make up location code */
1636 pci_add_loc_code(np, pd);
1637
1638 /* XXX FIXME: We don't look for BARs, we only put the config space
1639 * entry in the "reg" property. That's enough for Linux and we might
1640 * even want to make this legit in future ePAPR
1641 */
1642 reg[0] = pd->bdfn << 8;
1643 reg[1] = reg[2] = reg[3] = reg[4] = 0;
1644 dt_add_property(np, "reg", reg, sizeof(reg));
1645
1646 /* Print summary info about the device */
1647 pci_print_summary_line(phb, pd, np, rev_class, cname);
1648 if (!pd->is_bridge)
1649 return;
1650
1651 dt_add_property_cells(np, "#address-cells", 3);
1652 dt_add_property_cells(np, "#size-cells", 2);
1653 dt_add_property_cells(np, "#interrupt-cells", 1);
1654
1655 /* We want "device_type" for bridges */
1656 if (is_pcie)
1657 dt_add_property_string(np, "device_type", "pciex");
1658 else
1659 dt_add_property_string(np, "device_type", "pci");
1660
1661 /* Update the current interrupt swizzling level based on our own
1662 * device number
1663 */
1664 swizzle = (swizzle + ((pd->bdfn >> 3) & 0x1f)) & 3;
1665
1666 /* We generate a standard-swizzling interrupt map. This is pretty
1667 * big, we *could* try to be smarter for things that aren't hotplug
1668 * slots at least and only populate those entries for which there's
1669 * an actual children (especially on PCI Express), but for now that
1670 * will do
1671 */
1672 pci_std_swizzle_irq_map(np, pd, lstate, swizzle);
1673
1674 /* Parts of the OF address translation in the kernel will fail to
1675 * correctly translate a PCI address if translating a 1:1 mapping
1676 * (ie. an empty ranges property).
1677 * Instead add a ranges property that explicitly translates 1:1.
1678 */
1679 dt_add_property(np, "ranges", ranges_direct, sizeof(ranges_direct));
1680 }
1681
pci_add_device_nodes(struct phb * phb,struct list_head * list,struct dt_node * parent_node,struct pci_lsi_state * lstate,uint8_t swizzle)1682 void __noinline pci_add_device_nodes(struct phb *phb,
1683 struct list_head *list,
1684 struct dt_node *parent_node,
1685 struct pci_lsi_state *lstate,
1686 uint8_t swizzle)
1687 {
1688 struct pci_device *pd;
1689
1690 /* Add all child devices */
1691 list_for_each(list, pd, link) {
1692 pci_add_one_device_node(phb, pd, parent_node,
1693 lstate, swizzle);
1694 if (list_empty(&pd->children))
1695 continue;
1696
1697 pci_add_device_nodes(phb, &pd->children,
1698 pd->dn, lstate, swizzle);
1699 }
1700 }
1701
pci_do_jobs(void (* fn)(void *))1702 static void pci_do_jobs(void (*fn)(void *))
1703 {
1704 struct cpu_job **jobs;
1705 int i;
1706
1707 jobs = zalloc(sizeof(struct cpu_job *) * ARRAY_SIZE(phbs));
1708 assert(jobs);
1709 for (i = 0; i < ARRAY_SIZE(phbs); i++) {
1710 if (!phbs[i]) {
1711 jobs[i] = NULL;
1712 continue;
1713 }
1714
1715 jobs[i] = __cpu_queue_job(NULL, phbs[i]->dt_node->name,
1716 fn, phbs[i], false);
1717 assert(jobs[i]);
1718
1719 }
1720
1721 /* If no secondary CPUs, do everything sync */
1722 cpu_process_local_jobs();
1723
1724 /* Wait until all tasks are done */
1725 for (i = 0; i < ARRAY_SIZE(phbs); i++) {
1726 if (!jobs[i])
1727 continue;
1728
1729 cpu_wait_job(jobs[i], true);
1730 }
1731 free(jobs);
1732 }
1733
__pci_init_slots(void)1734 static void __pci_init_slots(void)
1735 {
1736 unsigned int i;
1737
1738 /* Some PHBs may need that long to debounce the presence detect
1739 * after HW initialization.
1740 */
1741 for (i = 0; i < ARRAY_SIZE(phbs); i++) {
1742 if (phbs[i]) {
1743 time_wait_ms(20);
1744 break;
1745 }
1746 }
1747
1748 if (platform.pre_pci_fixup)
1749 platform.pre_pci_fixup();
1750
1751 prlog(PR_NOTICE, "PCI: Resetting PHBs and training links...\n");
1752 pci_do_jobs(pci_reset_phb);
1753
1754 prlog(PR_NOTICE, "PCI: Probing slots...\n");
1755 pci_do_jobs(pci_scan_phb);
1756
1757 if (platform.pci_probe_complete)
1758 platform.pci_probe_complete();
1759
1760 prlog(PR_NOTICE, "PCI Summary:\n");
1761
1762 for (i = 0; i < ARRAY_SIZE(phbs); i++) {
1763 if (!phbs[i])
1764 continue;
1765
1766 pci_add_device_nodes(phbs[i], &phbs[i]->devices,
1767 phbs[i]->dt_node, &phbs[i]->lstate, 0);
1768 }
1769
1770 /* PHB final fixup */
1771 for (i = 0; i < ARRAY_SIZE(phbs); i++) {
1772 if (!phbs[i] || !phbs[i]->ops || !phbs[i]->ops->phb_final_fixup)
1773 continue;
1774
1775 phbs[i]->ops->phb_final_fixup(phbs[i]);
1776 }
1777 }
1778
__pci_reset(struct list_head * list)1779 static void __pci_reset(struct list_head *list)
1780 {
1781 struct pci_device *pd;
1782 struct pci_cfg_reg_filter *pcrf;
1783 int i;
1784
1785 while ((pd = list_pop(list, struct pci_device, link)) != NULL) {
1786 __pci_reset(&pd->children);
1787 dt_free(pd->dn);
1788 free(pd->slot);
1789 while((pcrf = list_pop(&pd->pcrf, struct pci_cfg_reg_filter, link)) != NULL) {
1790 free(pcrf);
1791 }
1792 for(i=0; i < 64; i++)
1793 if (pd->cap[i].free_func)
1794 pd->cap[i].free_func(pd->cap[i].data);
1795 free(pd);
1796 }
1797 }
1798
pci_reset(void)1799 int64_t pci_reset(void)
1800 {
1801 unsigned int i;
1802
1803 prlog(PR_NOTICE, "PCI: Clearing all devices...\n");
1804
1805 for (i = 0; i < ARRAY_SIZE(phbs); i++) {
1806 struct phb *phb = phbs[i];
1807 if (!phb)
1808 continue;
1809 __pci_reset(&phb->devices);
1810
1811 pci_slot_set_state(phb->slot, PCI_SLOT_STATE_CRESET_START);
1812 }
1813
1814 /* Do init and discovery of PCI slots in parallel */
1815 __pci_init_slots();
1816
1817 return 0;
1818 }
1819
pci_init_slots(void)1820 void pci_init_slots(void)
1821 {
1822 unsigned int i;
1823
1824 for (i = 0; i < ARRAY_SIZE(phbs); i++) {
1825 struct phb *phb = phbs[i];
1826 if (!phb)
1827 continue;
1828 pci_slot_set_state(phb->slot, PCI_SLOT_STATE_FRESET_POWER_OFF);
1829 }
1830 __pci_init_slots();
1831 }
1832
1833 /*
1834 * Complete iteration on current level before switching to
1835 * child level, which is the proper order for restoring
1836 * PCI bus range on bridges.
1837 */
__pci_walk_dev(struct phb * phb,struct list_head * l,int (* cb)(struct phb *,struct pci_device *,void *),void * userdata)1838 static struct pci_device *__pci_walk_dev(struct phb *phb,
1839 struct list_head *l,
1840 int (*cb)(struct phb *,
1841 struct pci_device *,
1842 void *),
1843 void *userdata)
1844 {
1845 struct pci_device *pd, *child;
1846
1847 if (list_empty(l))
1848 return NULL;
1849
1850 list_for_each(l, pd, link) {
1851 if (cb && cb(phb, pd, userdata))
1852 return pd;
1853 }
1854
1855 list_for_each(l, pd, link) {
1856 child = __pci_walk_dev(phb, &pd->children, cb, userdata);
1857 if (child)
1858 return child;
1859 }
1860
1861 return NULL;
1862 }
1863
pci_walk_dev(struct phb * phb,struct pci_device * pd,int (* cb)(struct phb *,struct pci_device *,void *),void * userdata)1864 struct pci_device *pci_walk_dev(struct phb *phb,
1865 struct pci_device *pd,
1866 int (*cb)(struct phb *,
1867 struct pci_device *,
1868 void *),
1869 void *userdata)
1870 {
1871 if (pd)
1872 return __pci_walk_dev(phb, &pd->children, cb, userdata);
1873
1874 return __pci_walk_dev(phb, &phb->devices, cb, userdata);
1875 }
1876
__pci_find_dev(struct phb * phb,struct pci_device * pd,void * userdata)1877 static int __pci_find_dev(struct phb *phb,
1878 struct pci_device *pd, void *userdata)
1879 {
1880 uint16_t bdfn = *((uint16_t *)userdata);
1881
1882 if (!phb || !pd)
1883 return 0;
1884
1885 if (pd->bdfn == bdfn)
1886 return 1;
1887
1888 return 0;
1889 }
1890
pci_find_dev(struct phb * phb,uint16_t bdfn)1891 struct pci_device *pci_find_dev(struct phb *phb, uint16_t bdfn)
1892 {
1893 return pci_walk_dev(phb, NULL, __pci_find_dev, &bdfn);
1894 }
1895
__pci_restore_bridge_buses(struct phb * phb,struct pci_device * pd,void * data __unused)1896 static int __pci_restore_bridge_buses(struct phb *phb,
1897 struct pci_device *pd,
1898 void *data __unused)
1899 {
1900 uint32_t vdid;
1901
1902 /* If the device is behind a switch, wait for the switch */
1903 if (!pd->is_vf && !(pd->bdfn & 7) && pd->parent != NULL &&
1904 pd->parent->dev_type == PCIE_TYPE_SWITCH_DNPORT) {
1905 if (!pci_bridge_wait_link(phb, pd->parent, true)) {
1906 PCIERR(phb, pd->bdfn, "Timeout waiting for switch\n");
1907 return -1;
1908 }
1909 }
1910
1911 /* Wait for config space to stop returning CRS */
1912 if (!pci_wait_crs(phb, pd->bdfn, &vdid))
1913 return -1;
1914
1915 /* Make all devices below a bridge "re-capture" the bdfn */
1916 pci_cfg_write32(phb, pd->bdfn, PCI_CFG_VENDOR_ID, vdid);
1917
1918 if (!pd->is_bridge)
1919 return 0;
1920
1921 pci_cfg_write8(phb, pd->bdfn, PCI_CFG_PRIMARY_BUS,
1922 pd->primary_bus);
1923 pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SECONDARY_BUS,
1924 pd->secondary_bus);
1925 pci_cfg_write8(phb, pd->bdfn, PCI_CFG_SUBORDINATE_BUS,
1926 pd->subordinate_bus);
1927 return 0;
1928 }
1929
pci_restore_bridge_buses(struct phb * phb,struct pci_device * pd)1930 void pci_restore_bridge_buses(struct phb *phb, struct pci_device *pd)
1931 {
1932 pci_walk_dev(phb, pd, __pci_restore_bridge_buses, NULL);
1933 }
1934
pci_restore_slot_bus_configs(struct pci_slot * slot)1935 void pci_restore_slot_bus_configs(struct pci_slot *slot)
1936 {
1937 /*
1938 * We might lose the bus numbers during the reset operation
1939 * and we need to restore them. Otherwise, some adapters (e.g.
1940 * IPR) can't be probed properly by the kernel. We don't need
1941 * to restore bus numbers for every kind of reset, however,
1942 * it's not harmful to always restore the bus numbers, which
1943 * simplifies the logic.
1944 */
1945 pci_restore_bridge_buses(slot->phb, slot->pd);
1946 if (slot->phb->ops->device_init)
1947 pci_walk_dev(slot->phb, slot->pd,
1948 slot->phb->ops->device_init, NULL);
1949 }
1950
pci_find_cfg_reg_filter(struct pci_device * pd,uint32_t start,uint32_t len)1951 struct pci_cfg_reg_filter *pci_find_cfg_reg_filter(struct pci_device *pd,
1952 uint32_t start, uint32_t len)
1953 {
1954 struct pci_cfg_reg_filter *pcrf;
1955
1956 /* Check on the cached range, which contains holes */
1957 if ((start + len) <= pd->pcrf_start ||
1958 pd->pcrf_end <= start)
1959 return NULL;
1960
1961 list_for_each(&pd->pcrf, pcrf, link) {
1962 if (start >= pcrf->start &&
1963 (start + len) <= (pcrf->start + pcrf->len))
1964 return pcrf;
1965 }
1966
1967 return NULL;
1968 }
1969
pci_device_has_cfg_reg_filters(struct phb * phb,uint16_t bdfn)1970 static bool pci_device_has_cfg_reg_filters(struct phb *phb, uint16_t bdfn)
1971 {
1972 return bitmap_tst_bit(*phb->filter_map, bdfn);
1973 }
1974
pci_handle_cfg_filters(struct phb * phb,uint32_t bdfn,uint32_t offset,uint32_t len,uint32_t * data,bool write)1975 int64_t pci_handle_cfg_filters(struct phb *phb, uint32_t bdfn,
1976 uint32_t offset, uint32_t len,
1977 uint32_t *data, bool write)
1978 {
1979 struct pci_device *pd;
1980 struct pci_cfg_reg_filter *pcrf;
1981 uint32_t flags;
1982
1983 if (!pci_device_has_cfg_reg_filters(phb, bdfn))
1984 return OPAL_PARTIAL;
1985 pd = pci_find_dev(phb, bdfn);
1986 pcrf = pd ? pci_find_cfg_reg_filter(pd, offset, len) : NULL;
1987 if (!pcrf || !pcrf->func)
1988 return OPAL_PARTIAL;
1989
1990 flags = write ? PCI_REG_FLAG_WRITE : PCI_REG_FLAG_READ;
1991 if ((pcrf->flags & flags) != flags)
1992 return OPAL_PARTIAL;
1993
1994 return pcrf->func(pd, pcrf, offset, len, data, write);
1995 }
1996
pci_add_cfg_reg_filter(struct pci_device * pd,uint32_t start,uint32_t len,uint32_t flags,pci_cfg_reg_func func)1997 struct pci_cfg_reg_filter *pci_add_cfg_reg_filter(struct pci_device *pd,
1998 uint32_t start, uint32_t len,
1999 uint32_t flags,
2000 pci_cfg_reg_func func)
2001 {
2002 struct pci_cfg_reg_filter *pcrf;
2003
2004 pcrf = pci_find_cfg_reg_filter(pd, start, len);
2005 if (pcrf)
2006 return pcrf;
2007
2008 pcrf = zalloc(sizeof(*pcrf) + ((len + 0x4) & ~0x3));
2009 if (!pcrf)
2010 return NULL;
2011
2012 /* Don't validate the flags so that the private flags
2013 * can be supported for debugging purpose.
2014 */
2015 pcrf->flags = flags;
2016 pcrf->start = start;
2017 pcrf->len = len;
2018 pcrf->func = func;
2019 pcrf->data = (uint8_t *)(pcrf + 1);
2020
2021 if (start < pd->pcrf_start)
2022 pd->pcrf_start = start;
2023 if (pd->pcrf_end < (start + len))
2024 pd->pcrf_end = start + len;
2025 list_add_tail(&pd->pcrf, &pcrf->link);
2026 bitmap_set_bit(*pd->phb->filter_map, pd->bdfn);
2027
2028 return pcrf;
2029 }
2030