1 /* Copyright 2013-2015 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __NPU_REGS_H 18 #define __NPU_REGS_H 19 20 /* Size of a single link */ 21 #define NPU_LINK_SIZE 0x40 22 23 /* Link registers */ 24 #define NX_PB_ERR_RPT_0 0x00 25 #define NX_PB_ERR_RPT_1 0x01 26 #define NX_MMIO_BAR_0 0x02 27 #define NX_MMIO_BAR_1 0x03 28 #define NX_MMIO_BAR_BASE PPC_BITMASK(14,51) 29 #define NX_MMIO_BAR_ENABLE PPC_BIT(52) 30 #define NX_MMIO_BAR_SIZE PPC_BITMASK(53,55) 31 #define NX_NODAL_BAR0 0x04 32 #define NX_NODAL_BAR1 0x05 33 #define NX_NODAL_BAR_ENABLE PPC_BIT(0) 34 #define NX_NODAL_BAR_MASK PPC_BITMASK(1,14) 35 #define NX_NODAL_BAR_BASE PPC_BITMASK(15,32) 36 #define NX_GROUP_BAR0 0x06 37 #define NX_GROUP_BAR1 0x07 38 #define NX_GROUP_BAR_ENABLE PPC_BIT(0) 39 #define NX_GROUP_BAR_MASK PPC_BITMASK(1,14) 40 #define NX_GROUP_BAR_BASE PPC_BITMASK(15,32) 41 #define NX_EPSILON_COUN 0x08 42 #define NX_EPSILON_COUN_DISABLE PPC_BIT(6) 43 #define NX_MISC_CONTROL 0x09 44 #define NX_PB_DEBUG 0x0a 45 #define NX_PB_ECC 0x0b 46 #define NX_DEBUG_SNAPSHOT_0 0x0c 47 #define NX_DEBUG_SNAPSHOT_1 0x0d 48 #define NX_CS_CTL 0x0e 49 #define NX_CONFIG_CQ 0x0f 50 #define NX_MRBO0 0x10 51 #define NX_MRBO1 0x11 52 #define NX_AS_CMD_CFG 0x12 53 #define NX_NP_BUID 0x13 54 #define NP_BUID_ENABLE PPC_BIT(0) 55 #define NP_BUID_BASE PPC_BITMASK(1,15) 56 #define NP_IRQ_LEVELS PPC_BITMASK(16,23) 57 #define NP_BUID_MASK PPC_BITMASK(24,32) 58 #define NX_TL_CMD_CR 0x20 59 #define NX_TL_CMD_D_CR 0x21 60 #define NX_TL_RSP_CR 0x22 61 #define NX_TL_RSP_D_CR 0x23 62 #define NX_DL_REG_ADDR 0x24 63 #define NX_DL_REG_DATA 0x25 64 #define NX_NTL_CONTROL 0x26 65 #define NX_NTL_PMU_CONTROL 0x27 66 #define NX_NTL_PMU_COUNT 0x28 67 #define NX_NTL_ER_HOLD 0x29 68 #define NX_NTL_FST_ERR 0x2a 69 #define NX_NTL_ECC 0x2b 70 #define NX_NTL_FST_MSK 0x2c 71 72 /* NP AT register */ 73 #define NX_FIR 0x00 74 #define NX_FIR_CLEAR 0x01 75 #define NX_FIR_SET 0x02 76 #define NX_FIR_MASK 0x03 77 #define NX_FIR_MASK_CLR 0x04 78 #define NX_FIR_MASK_SET 0x05 79 #define NX_FIR_ACTION0 0x06 80 #define NX_FIR_ACTION1 0x07 81 #define NX_FIR_WOF 0x08 82 #define NX_AT_PMU_CTRL 0x26 83 #define NX_AT_PMU_CNT 0x27 84 #define NX_AT_ERR_HOLD 0x28 85 #define NX_AT_ERR_HOLD_RESET PPC_BIT(63) 86 #define NX_AT_DEBUG 0x29 87 #define NX_AT_ECC 0x2a 88 #define NX_BAR 0x2b 89 90 /* AT MMIO registers */ 91 #define NPU_LSI_SOURCE_ID 0x00100 92 #define NPU_LSI_SRC_ID_BASE PPC_BITMASK(5,11) 93 #define NPU_DMA_CHAN_STATUS 0x00110 94 #define NPU_INTREP_TIMER 0x001f8 95 #define NPU_DMARD_SYNC 0x00200 96 #define NPU_DMARD_SYNC_START_RD PPC_BIT(0) 97 #define NPU_DMARD_SYNC_RD PPC_BIT(1) 98 #define NPU_DMARD_SYNC_START_WR PPC_BIT(2) 99 #define NPU_DMARD_SYNC_WR PPC_BIT(3) 100 #define NPU_TCE_KILL 0x00210 101 #define NPU_IODA_ADDR 0x00220 102 #define NPU_IODA_AD_AUTOINC PPC_BIT(0) 103 #define NPU_IODA_AD_TSEL PPC_BITMASK(11,15) 104 #define NPU_IODA_AD_TADR PPC_BITMASK(54,63) 105 #define NPU_IODA_DATA0 0x00228 106 #define NPU_XIVE_UPD 0x00248 107 #define NPU_GEN_CAP 0x00250 108 #define NPU_TCE_CAP 0x00258 109 #define NPU_INT_CAP 0x00260 110 #define NPU_EEH_CAP 0x00268 111 #define NPU_VR 0x00800 112 #define NPU_CTRLR 0x00810 113 #define NPU_TCR 0x00880 114 #define NPU_Q_DMA_R 0x00888 115 #define NPU_AT_ESR 0x00c80 116 #define NPU_AT_FESR 0x00c88 117 #define NPU_AT_LR_ER 0x00c98 118 #define NPU_AT_SI_ER 0x00ca0 119 #define NPU_AT_FR_ER 0x00ca8 120 #define NPU_AT_FE_ER 0x00cb0 121 #define NPU_AT_ESMR 0x00cd0 122 #define NPU_AT_FESMR 0x00cd8 123 #define NPU_AT_I_LR0 0x00d00 124 #define NPU_AT_I_LR1 0x00d08 125 #define NPU_AT_I_LR2 0x00d10 126 #define NPU_AT_I_LR3 0x00d18 127 128 /* AT */ 129 #define NPU_AT_SCOM_OFFSET 0x180 130 131 /* NTL */ 132 #define TL_CMD_CR 0x10000 133 #define TL_CMD_D_CR 0x10008 134 #define TL_RSP_CR 0x10010 135 #define TL_RSP_D_CR 0x10018 136 #define NTL_CONTROL 0x10020 137 #define NTL_CONTROL_RESET PPC_BIT(0) 138 139 /* IODA tables */ 140 #define NPU_IODA_TBL_LIST 1 141 #define NPU_IODA_TBL_LXIVT 2 142 #define NPU_IODA_TBL_PCT 4 143 #define NPU_IODA_TBL_PESTB 8 144 #define NPU_IODA_TBL_TVT 9 145 #define NPU_IODA_TBL_TCD 10 146 #define NPU_IODA_TBL_TDR 11 147 #define NPU_IODA_TBL_PESTB_ADDR 12 148 #define NPU_IODA_TBL_EA 16 149 150 /* LXIVT */ 151 #define NPU_IODA_LXIVT_SERVER PPC_BITMASK(8,23) 152 #define NPU_IODA_LXIVT_PRIORITY PPC_BITMASK(24,31) 153 154 /* PCT */ 155 #define NPU_IODA_PCT_LINK_ENABLED PPC_BIT(0) 156 #define NPU_IODA_PCT_PE PPC_BITMASK(2,3) 157 158 /* TVT */ 159 #define NPU_IODA_TVT_TTA PPC_BITMASK(0,47) 160 #define NPU_IODA_TVT_LEVELS PPC_BITMASK(48,50) 161 #define NPU_IODA_TVE_1_LEVEL 0 162 #define NPU_IODA_TVE_2_LEVELS 1 163 #define NPU_IODA_TVE_3_LEVELS 2 164 #define NPU_IODA_TVE_4_LEVELS 3 165 #define NPU_IODA_TVT_SIZE PPC_BITMASK(51,55) 166 #define NPU_IODA_TVT_PSIZE PPC_BITMASK(59,63) 167 168 /* NDL Registers */ 169 #define NDL_STATUS 0xfff0 170 #define NDL_CONTROL 0xfff4 171 172 /* BAR Sizes */ 173 #define NX_MMIO_PL_SIZE 0x200000 174 #define NX_MMIO_AT_SIZE 0x10000 175 #define NX_MMIO_DL_SIZE 0x20000 176 177 /* Translates a PHY SCOM address to an MMIO offset */ 178 #define PL_MMIO_ADDR(reg) (((reg >> 32) & 0xfffffull) << 1) 179 180 /* PHY register scom offsets & fields */ 181 #define RX_PR_CNTL_PL 0x0002180000000000UL 182 #define RX_PR_RESET PPC_BIT(63) 183 184 #define TX_MODE1_PL 0x0004040000000000UL 185 #define TX_LANE_PDWN PPC_BIT(48) 186 187 #define TX_MODE2_PL 0x00040c0000000000UL 188 #define TX_RXCAL PPC_BIT(57) 189 #define TX_UNLOAD_CLK_DISABLE PPC_BIT(56) 190 191 #define TX_CNTL_STAT2 0x00041c0000000000UL 192 #define TX_FIFO_INIT PPC_BIT(48) 193 194 #define RX_BANK_CONTROLS 0x0000f80000000000UL 195 #define RX_LANE_ANA_PDWN PPC_BIT(54) 196 197 #define RX_MODE 0x0002000000000000UL 198 #define RX_LANE_DIG_PDWN PPC_BIT(48) 199 200 #define RX_PR_MODE 0x0002100000000000UL 201 #define RX_PR_PHASE_STEP PPC_BITMASK(60, 63) 202 203 #define RX_A_DAC_CNTL 0x0000080000000000UL 204 #define RX_PR_IQ_RES_SEL PPC_BITMASK(58, 60) 205 206 #define RX_LANE_BUSY_VEC_0_15 0x000b000000000000UL 207 #define TX_FFE_TOTAL_2RSTEP_EN 0x000c240000000000UL 208 #define TX_FFE_TOTAL_ENABLE_P_ENC PPC_BITMASK(49,55) 209 #define TX_FFE_TOTAL_ENABLE_N_ENC PPC_BITMASK(57,63) 210 #define TX_FFE_PRE_2RSTEP_SEL 0x000c2c0000000000UL 211 #define TX_FFE_PRE_P_SEL_ENC PPC_BITMASK(51,54) 212 #define TX_FFE_PRE_N_SEL_ENC PPC_BITMASK(59,62) 213 #define TX_FFE_MARGIN_2RSTEP_SEL 0x000c34000000000UL 214 #define TX_FFE_MARGIN_PU_P_SEL_ENC PPC_BITMASK(51,55) 215 #define TX_FFE_MARGIN_PD_N_SEL_ENC PPC_BITMASK(59,63) 216 #define TX_IORESET_VEC_0_15 0x000d2c0000000000UL 217 #define TX_IMPCAL_PB 0x000f040000000000UL 218 #define TX_ZCAL_REQ PPC_BIT(49) 219 #define TX_ZCAL_DONE PPC_BIT(50) 220 #define TX_ZCAL_ERROR PPC_BIT(51) 221 #define TX_IMPCAL_NVAL_PB 0x000f0c0000000000UL 222 #define TX_ZCAL_N PPC_BITMASK(48,56) 223 #define TX_IMPCAL_PVAL_PB 0x000f140000000000UL 224 #define TX_ZCAL_P PPC_BITMASK(48,56) 225 #define RX_EO_STEP_CNTL_PG 0x0008300000000000UL 226 #define RX_EO_ENABLE_LATCH_OFFSET_CAL PPC_BIT(48) 227 #define RX_EO_ENABLE_CM_COARSE_CAL PPC_BIT(57) 228 #define RX_RUN_LANE_VEC_0_15 0x0009b80000000000UL 229 #define RX_RECAL_ABORT_VEC_0_15 0x0009c80000000000UL 230 #define RX_IORESET_VEC_0_15 0x0009d80000000000UL 231 #define RX_EO_RECAL_PG 0x000a800000000000UL 232 #define RX_INIT_DONE_VEC_0_15 0x000ac00000000000UL 233 #define TX_IMPCAL_SWO1_PB 0x000f240000000000UL 234 #define TX_ZCAL_SWO_EN PPC_BIT(48) 235 #define TX_IMPCAL_SWO2_PB 0x000f2c0000000000UL 236 237 #endif /* __NPU_REGS_H */ 238