1 /** 2 * @file IxNpeMhMacros_p.h 3 * 4 * @author Intel Corporation 5 * @date 21 Jan 2002 6 * 7 * @brief This file contains the macros for the IxNpeMh component. 8 * 9 * 10 * @par 11 * IXP400 SW Release version 2.0 12 * 13 * -- Copyright Notice -- 14 * 15 * @par 16 * Copyright 2001-2005, Intel Corporation. 17 * All rights reserved. 18 * 19 * @par 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 1. Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * 2. Redistributions in binary form must reproduce the above copyright 26 * notice, this list of conditions and the following disclaimer in the 27 * documentation and/or other materials provided with the distribution. 28 * 3. Neither the name of the Intel Corporation nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * @par 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * @par 46 * -- End of Copyright Notice -- 47 */ 48 49 /** 50 * @defgroup IxNpeMhMacros_p IxNpeMhMacros_p 51 * 52 * @brief Macros for the IxNpeMh component. 53 * 54 * @{ 55 */ 56 57 #ifndef IXNPEMHMACROS_P_H 58 #define IXNPEMHMACROS_P_H 59 60 /* if we are running as a unit test */ 61 #ifdef IX_UNIT_TEST 62 #undef NDEBUG 63 #endif /* #ifdef IX_UNIT_TEST */ 64 65 #include "IxOsal.h" 66 67 /* 68 * #defines for function return types, etc. 69 */ 70 71 #define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */ 72 #define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */ 73 74 /** 75 * @def IX_NPEMH_SHOW 76 * 77 * @brief Macro for displaying a stat preceded by a textual description. 78 */ 79 80 #define IX_NPEMH_SHOW(TEXT, STAT) \ 81 ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \ 82 "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0) 83 84 /* 85 * Prototypes for interface functions. 86 */ 87 88 /** 89 * @typedef IxNpeMhTraceTypes 90 * 91 * @brief Enumeration defining IxNpeMh trace levels 92 */ 93 94 typedef enum 95 { 96 IX_NPEMH_TRACE_OFF = IX_OSAL_LOG_LVL_NONE, /**< no trace */ 97 IX_NPEMH_WARNING = IX_OSAL_LOG_LVL_WARNING, /**< warning */ 98 IX_NPEMH_DEBUG = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */ 99 IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3 /**< function entry/exit */ 100 } IxNpeMhTraceTypes; 101 102 #ifdef IX_UNIT_TEST 103 #define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */ 104 #else 105 #define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */ 106 #endif 107 108 /** 109 * @def IX_NPEMH_TRACE0 110 * 111 * @brief Trace macro taking 0 arguments. 112 */ 113 114 #define IX_NPEMH_TRACE0(LEVEL, STR) \ 115 IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0) 116 117 /** 118 * @def IX_NPEMH_TRACE1 119 * 120 * @brief Trace macro taking 1 argument. 121 */ 122 123 #define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \ 124 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0) 125 126 /** 127 * @def IX_NPEMH_TRACE2 128 * 129 * @brief Trace macro taking 2 arguments. 130 */ 131 132 #define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \ 133 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0) 134 135 /** 136 * @def IX_NPEMH_TRACE3 137 * 138 * @brief Trace macro taking 3 arguments. 139 */ 140 141 #define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \ 142 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0) 143 144 /** 145 * @def IX_NPEMH_TRACE4 146 * 147 * @brief Trace macro taking 4 arguments. 148 */ 149 150 #define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \ 151 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0) 152 153 /** 154 * @def IX_NPEMH_TRACE5 155 * 156 * @brief Trace macro taking 5 arguments. 157 */ 158 159 #define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \ 160 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0) 161 162 /** 163 * @def IX_NPEMH_TRACE6 164 * 165 * @brief Trace macro taking 6 arguments. 166 */ 167 168 #define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \ 169 { \ 170 if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \ 171 { \ 172 (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \ 173 (int)(ARG1), (int)(ARG2), (int)(ARG3), \ 174 (int)(ARG4), (int)(ARG5), (int)(ARG6)); \ 175 } \ 176 } 177 178 /** 179 * @def IX_NPEMH_ERROR_REPORT 180 * 181 * @brief Error reporting facility. 182 */ 183 184 #define IX_NPEMH_ERROR_REPORT(STR) \ 185 { \ 186 (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \ 187 (STR), 0, 0, 0, 0, 0, 0); \ 188 } 189 190 /* if we are running on XScale, i.e. real environment */ 191 #if CPU==XSCALE 192 193 /** 194 * @def IX_NPEMH_REGISTER_READ 195 * 196 * @brief This macro reads a memory-mapped register. 197 */ 198 199 #define IX_NPEMH_REGISTER_READ(registerAddress, value) \ 200 { \ 201 *value = IX_OSAL_READ_LONG(registerAddress); \ 202 } 203 204 /** 205 * @def IX_NPEMH_REGISTER_READ_BITS 206 * 207 * @brief This macro partially reads a memory-mapped register. 208 */ 209 210 #define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \ 211 { \ 212 *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \ 213 } 214 215 /** 216 * @def IX_NPEMH_REGISTER_WRITE 217 * 218 * @brief This macro writes a memory-mapped register. 219 */ 220 221 #define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \ 222 { \ 223 IX_OSAL_WRITE_LONG(registerAddress, value); \ 224 } 225 226 /** 227 * @def IX_NPEMH_REGISTER_WRITE_BITS 228 * 229 * @brief This macro partially writes a memory-mapped register. 230 */ 231 232 #define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \ 233 { \ 234 UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \ 235 orig &= (~mask); \ 236 orig |= (value & mask); \ 237 IX_OSAL_WRITE_LONG(registerAddress, orig); \ 238 } 239 240 241 /* if we are running as a unit test */ 242 #else /* #if CPU==XSCALE */ 243 244 #include "IxNpeMhTestRegister.h" 245 246 /** 247 * @def IX_NPEMH_REGISTER_READ 248 * 249 * @brief This macro reads a memory-mapped register. 250 */ 251 252 #define IX_NPEMH_REGISTER_READ(registerAddress, value) \ 253 { \ 254 ixNpeMhTestRegisterRead (registerAddress, value); \ 255 } 256 257 /** 258 * @def IX_NPEMH_REGISTER_READ_BITS 259 * 260 * @brief This macro partially reads a memory-mapped register. 261 */ 262 263 #define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \ 264 { \ 265 ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \ 266 } 267 268 /** 269 * @def IX_NPEMH_REGISTER_WRITE 270 * 271 * @brief This macro writes a memory-mapped register. 272 */ 273 274 #define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \ 275 { \ 276 ixNpeMhTestRegisterWrite (registerAddress, value); \ 277 } 278 279 /** 280 * @def IX_NPEMH_REGISTER_WRITE_BITS 281 * 282 * @brief This macro partially writes a memory-mapped register. 283 */ 284 285 #define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \ 286 { \ 287 ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \ 288 } 289 290 #endif /* #if CPU==XSCALE */ 291 292 #endif /* IXNPEMHMACROS_P_H */ 293 294 /** 295 * @} defgroup IxNpeMhMacros_p 296 */ 297