1 /* 2 * (C) Copyright 2003 3 * Denis Peter d.peter@mpl.ch 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, 21 */ 22 23 /* 24 * File: PATI.h 25 */ 26 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* 31 * High Level Configuration Options 32 */ 33 34 #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ 35 #define CONFIG_PATI 1 /* ...On a PATI board */ 36 /* Serial Console Configuration */ 37 #define CONFIG_5xx_CONS_SCI1 38 #undef CONFIG_5xx_CONS_SCI2 39 40 #define CONFIG_BAUDRATE 9600 41 42 43 /* 44 * BOOTP options 45 */ 46 #define CONFIG_BOOTP_BOOTFILESIZE 47 #define CONFIG_BOOTP_BOOTPATH 48 #define CONFIG_BOOTP_GATEWAY 49 #define CONFIG_BOOTP_HOSTNAME 50 51 52 /* 53 * Command line configuration. 54 */ 55 #define CONFIG_CMD_MEMORY 56 #define CONFIG_CMD_LOADB 57 #define CONFIG_CMD_REGINFO 58 #define CONFIG_CMD_FLASH 59 #define CONFIG_CMD_LOADS 60 #define CONFIG_CMD_SAVEENV 61 #define CONFIG_CMD_REGINFO 62 #define CONFIG_CMD_BDI 63 #define CONFIG_CMD_CONSOLE 64 #define CONFIG_CMD_RUN 65 #define CONFIG_CMD_BSP 66 #define CONFIG_CMD_IMI 67 #define CONFIG_CMD_EEPROM 68 #define CONFIG_CMD_IRQ 69 #define CONFIG_CMD_MISC 70 71 72 #if 0 73 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 74 #else 75 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 76 #endif 77 #define CONFIG_BOOTCOMMAND "" /* autoboot command */ 78 79 #define CONFIG_BOOTARGS "" /* */ 80 81 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */ 82 83 /*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ 84 85 #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ 86 87 /* 88 * Miscellaneous configurable options 89 */ 90 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ 91 #define CONFIG_PREBOOT 92 93 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 94 #define CONFIG_SYS_PROMPT "pati=> " /* Monitor Command Prompt */ 95 #if defined(CONFIG_CMD_KGDB) 96 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 97 #else 98 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 99 #endif 100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 101 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 102 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 103 104 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ 105 #define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ 106 107 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 108 109 #define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ 110 111 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } 112 113 114 /*********************************************************************** 115 * Last Stage Init 116 ***********************************************************************/ 117 #define CONFIG_LAST_STAGE_INIT 118 119 /* 120 * Low Level Configuration Settings 121 */ 122 123 /* 124 * Internal Memory Mapped (This is not the IMMR content) 125 */ 126 #define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ 127 128 /* 129 * Definitions for initial stack pointer and data area 130 */ 131 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ 132 #define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ 133 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ 134 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */ 135 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ 136 /* 137 * Start addresses for the final memory configuration 138 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 139 */ 140 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ 141 #define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ 142 #define PCI_BASE 0x03000000 /* PCI Base (CS2) */ 143 #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ 144 #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ 145 146 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000 147 /* CONFIG_SYS_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ 148 /* This adress is given to the linker with -Ttext to */ 149 /* locate the text section at this adress. */ 150 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ 151 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 152 153 #define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ 154 155 /* 156 * For booting Linux, the board info and command line data 157 * have to be in the first 8 MB of memory, since this is 158 * the maximum mapped by the Linux kernel during initialization. 159 */ 160 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 161 162 163 /*----------------------------------------------------------------------- 164 * FLASH organization 165 *----------------------------------------------------------------------- 166 * 167 */ 168 169 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */ 170 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ 171 #define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ 172 #define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ 173 174 175 #define CONFIG_ENV_IS_IN_EEPROM 176 #ifdef CONFIG_ENV_IS_IN_EEPROM 177 #define CONFIG_ENV_OFFSET 0 178 #define CONFIG_ENV_SIZE 2048 179 #endif 180 181 #undef CONFIG_ENV_IS_IN_FLASH 182 #ifdef CONFIG_ENV_IS_IN_FLASH 183 #define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ 184 #define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ 185 #endif 186 187 188 #define CONFIG_SPI 1 189 #define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ 190 #define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ 191 #define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ 192 /*----------------------------------------------------------------------- 193 * SYPCR - System Protection Control 194 * SYPCR can only be written once after reset! 195 *----------------------------------------------------------------------- 196 * SW Watchdog freeze 197 */ 198 #undef CONFIG_WATCHDOG 199 #if defined(CONFIG_WATCHDOG) 200 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 201 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 202 #else 203 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 204 SYPCR_SWP) 205 #endif /* CONFIG_WATCHDOG */ 206 207 /*----------------------------------------------------------------------- 208 * TBSCR - Time Base Status and Control 209 *----------------------------------------------------------------------- 210 * Clear Reference Interrupt Status, Timebase freezing enabled 211 */ 212 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 213 214 /*----------------------------------------------------------------------- 215 * PISCR - Periodic Interrupt Status and Control 216 *----------------------------------------------------------------------- 217 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 218 */ 219 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 220 221 /*----------------------------------------------------------------------- 222 * SCCR - System Clock and reset Control Register 223 *----------------------------------------------------------------------- 224 * Set clock output, timebase and RTC source and divider, 225 * power management and some other internal clocks 226 */ 227 #define SCCR_MASK SCCR_EBDF00 228 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ 229 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) 230 231 /*----------------------------------------------------------------------- 232 * SIUMCR - SIU Module Configuration 233 *----------------------------------------------------------------------- 234 * Data show cycle 235 */ 236 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ 237 238 /*----------------------------------------------------------------------- 239 * PLPRCR - PLL, Low-Power, and Reset Control Register 240 *----------------------------------------------------------------------- 241 * Set all bits to 40 Mhz 242 * 243 */ 244 #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ 245 246 247 #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) 248 249 /*----------------------------------------------------------------------- 250 * UMCR - UIMB Module Configuration Register 251 *----------------------------------------------------------------------- 252 * 253 */ 254 #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ 255 256 /*----------------------------------------------------------------------- 257 * ICTRL - I-Bus Support Control Register 258 */ 259 #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ 260 261 /*----------------------------------------------------------------------- 262 * USIU - Memory Controller Register 263 *----------------------------------------------------------------------- 264 */ 265 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) 266 #define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ 267 /* SDRAM */ 268 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 269 #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ 270 /* PCI */ 271 #define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) 272 #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) 273 /* config registers: */ 274 #define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) 275 #define CONFIG_SYS_OR3_PRELIM (0xffff0000) 276 277 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ 278 279 /*----------------------------------------------------------------------- 280 * DER - Timer Decrementer 281 *----------------------------------------------------------------------- 282 * Initialise to zero 283 */ 284 #define CONFIG_SYS_DER 0x00000000 285 286 287 /* 288 * Internal Definitions 289 * 290 * Boot Flags 291 */ 292 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 293 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 294 295 296 #define VERSION_TAG "released" 297 #define CONFIG_ISO_STRING "MEV-10084-001" 298 299 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG 300 301 #endif /* __CONFIG_H */ 302