1 /* Capstone Disassembly Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
3
4 #ifdef CAPSTONE_HAS_X86
5
6 #if defined(CAPSTONE_HAS_OSXKERNEL)
7 #include <Availability.h>
8 #endif
9
10 #include <string.h>
11 #ifndef CAPSTONE_HAS_OSXKERNEL
12 #include <stdlib.h>
13 #endif
14
15 #include "X86Mapping.h"
16 #include "X86DisassemblerDecoder.h"
17
18 #include "../../utils.h"
19
20
21 const uint64_t arch_masks[9] = {
22 0, 0xff,
23 0xffff, // 16bit
24 0,
25 0xffffffff, // 32bit
26 0, 0, 0,
27 0xffffffffffffffffLL // 64bit
28 };
29
30 static const x86_reg sib_base_map[] = {
31 X86_REG_INVALID,
32 #define ENTRY(x) X86_REG_##x,
33 ALL_SIB_BASES
34 #undef ENTRY
35 };
36
37 // Fill-ins to make the compiler happy. These constants are never actually
38 // assigned; they are just filler to make an automatically-generated switch
39 // statement work.
40 enum {
41 X86_REG_BX_SI = 500,
42 X86_REG_BX_DI = 501,
43 X86_REG_BP_SI = 502,
44 X86_REG_BP_DI = 503,
45 X86_REG_sib = 504,
46 X86_REG_sib64 = 505
47 };
48
49 static const x86_reg sib_index_map[] = {
50 X86_REG_INVALID,
51 #define ENTRY(x) X86_REG_##x,
52 ALL_EA_BASES
53 REGS_XMM
54 REGS_YMM
55 REGS_ZMM
56 #undef ENTRY
57 };
58
59 static const x86_reg segment_map[] = {
60 X86_REG_INVALID,
61 X86_REG_CS,
62 X86_REG_SS,
63 X86_REG_DS,
64 X86_REG_ES,
65 X86_REG_FS,
66 X86_REG_GS,
67 };
68
x86_map_sib_base(int r)69 x86_reg x86_map_sib_base(int r)
70 {
71 return sib_base_map[r];
72 }
73
x86_map_sib_index(int r)74 x86_reg x86_map_sib_index(int r)
75 {
76 return sib_index_map[r];
77 }
78
x86_map_segment(int r)79 x86_reg x86_map_segment(int r)
80 {
81 return segment_map[r];
82 }
83
84 #ifndef CAPSTONE_DIET
85 static const name_map reg_name_maps[] = {
86 { X86_REG_INVALID, NULL },
87
88 { X86_REG_AH, "ah" },
89 { X86_REG_AL, "al" },
90 { X86_REG_AX, "ax" },
91 { X86_REG_BH, "bh" },
92 { X86_REG_BL, "bl" },
93 { X86_REG_BP, "bp" },
94 { X86_REG_BPL, "bpl" },
95 { X86_REG_BX, "bx" },
96 { X86_REG_CH, "ch" },
97 { X86_REG_CL, "cl" },
98 { X86_REG_CS, "cs" },
99 { X86_REG_CX, "cx" },
100 { X86_REG_DH, "dh" },
101 { X86_REG_DI, "di" },
102 { X86_REG_DIL, "dil" },
103 { X86_REG_DL, "dl" },
104 { X86_REG_DS, "ds" },
105 { X86_REG_DX, "dx" },
106 { X86_REG_EAX, "eax" },
107 { X86_REG_EBP, "ebp" },
108 { X86_REG_EBX, "ebx" },
109 { X86_REG_ECX, "ecx" },
110 { X86_REG_EDI, "edi" },
111 { X86_REG_EDX, "edx" },
112 { X86_REG_EFLAGS, "flags" },
113 { X86_REG_EIP, "eip" },
114 { X86_REG_EIZ, "eiz" },
115 { X86_REG_ES, "es" },
116 { X86_REG_ESI, "esi" },
117 { X86_REG_ESP, "esp" },
118 { X86_REG_FPSW, "fpsw" },
119 { X86_REG_FS, "fs" },
120 { X86_REG_GS, "gs" },
121 { X86_REG_IP, "ip" },
122 { X86_REG_RAX, "rax" },
123 { X86_REG_RBP, "rbp" },
124 { X86_REG_RBX, "rbx" },
125 { X86_REG_RCX, "rcx" },
126 { X86_REG_RDI, "rdi" },
127 { X86_REG_RDX, "rdx" },
128 { X86_REG_RIP, "rip" },
129 { X86_REG_RIZ, "riz" },
130 { X86_REG_RSI, "rsi" },
131 { X86_REG_RSP, "rsp" },
132 { X86_REG_SI, "si" },
133 { X86_REG_SIL, "sil" },
134 { X86_REG_SP, "sp" },
135 { X86_REG_SPL, "spl" },
136 { X86_REG_SS, "ss" },
137 { X86_REG_CR0, "cr0" },
138 { X86_REG_CR1, "cr1" },
139 { X86_REG_CR2, "cr2" },
140 { X86_REG_CR3, "cr3" },
141 { X86_REG_CR4, "cr4" },
142 { X86_REG_CR5, "cr5" },
143 { X86_REG_CR6, "cr6" },
144 { X86_REG_CR7, "cr7" },
145 { X86_REG_CR8, "cr8" },
146 { X86_REG_CR9, "cr9" },
147 { X86_REG_CR10, "cr10" },
148 { X86_REG_CR11, "cr11" },
149 { X86_REG_CR12, "cr12" },
150 { X86_REG_CR13, "cr13" },
151 { X86_REG_CR14, "cr14" },
152 { X86_REG_CR15, "cr15" },
153 { X86_REG_DR0, "dr0" },
154 { X86_REG_DR1, "dr1" },
155 { X86_REG_DR2, "dr2" },
156 { X86_REG_DR3, "dr3" },
157 { X86_REG_DR4, "dr4" },
158 { X86_REG_DR5, "dr5" },
159 { X86_REG_DR6, "dr6" },
160 { X86_REG_DR7, "dr7" },
161 { X86_REG_DR8, "dr8" },
162 { X86_REG_DR9, "dr9" },
163 { X86_REG_DR10, "dr10" },
164 { X86_REG_DR11, "dr11" },
165 { X86_REG_DR12, "dr12" },
166 { X86_REG_DR13, "dr13" },
167 { X86_REG_DR14, "dr14" },
168 { X86_REG_DR15, "dr15" },
169 { X86_REG_FP0, "fp0" },
170 { X86_REG_FP1, "fp1" },
171 { X86_REG_FP2, "fp2" },
172 { X86_REG_FP3, "fp3" },
173 { X86_REG_FP4, "fp4" },
174 { X86_REG_FP5, "fp5" },
175 { X86_REG_FP6, "fp6" },
176 { X86_REG_FP7, "fp7" },
177 { X86_REG_K0, "k0" },
178 { X86_REG_K1, "k1" },
179 { X86_REG_K2, "k2" },
180 { X86_REG_K3, "k3" },
181 { X86_REG_K4, "k4" },
182 { X86_REG_K5, "k5" },
183 { X86_REG_K6, "k6" },
184 { X86_REG_K7, "k7" },
185 { X86_REG_MM0, "mm0" },
186 { X86_REG_MM1, "mm1" },
187 { X86_REG_MM2, "mm2" },
188 { X86_REG_MM3, "mm3" },
189 { X86_REG_MM4, "mm4" },
190 { X86_REG_MM5, "mm5" },
191 { X86_REG_MM6, "mm6" },
192 { X86_REG_MM7, "mm7" },
193 { X86_REG_R8, "r8" },
194 { X86_REG_R9, "r9" },
195 { X86_REG_R10, "r10" },
196 { X86_REG_R11, "r11" },
197 { X86_REG_R12, "r12" },
198 { X86_REG_R13, "r13" },
199 { X86_REG_R14, "r14" },
200 { X86_REG_R15, "r15" },
201 { X86_REG_ST0, "st(0)" },
202 { X86_REG_ST1, "st(1)" },
203 { X86_REG_ST2, "st(2)" },
204 { X86_REG_ST3, "st(3)" },
205 { X86_REG_ST4, "st(4)" },
206 { X86_REG_ST5, "st(5)" },
207 { X86_REG_ST6, "st(6)" },
208 { X86_REG_ST7, "st(7)" },
209 { X86_REG_XMM0, "xmm0" },
210 { X86_REG_XMM1, "xmm1" },
211 { X86_REG_XMM2, "xmm2" },
212 { X86_REG_XMM3, "xmm3" },
213 { X86_REG_XMM4, "xmm4" },
214 { X86_REG_XMM5, "xmm5" },
215 { X86_REG_XMM6, "xmm6" },
216 { X86_REG_XMM7, "xmm7" },
217 { X86_REG_XMM8, "xmm8" },
218 { X86_REG_XMM9, "xmm9" },
219 { X86_REG_XMM10, "xmm10" },
220 { X86_REG_XMM11, "xmm11" },
221 { X86_REG_XMM12, "xmm12" },
222 { X86_REG_XMM13, "xmm13" },
223 { X86_REG_XMM14, "xmm14" },
224 { X86_REG_XMM15, "xmm15" },
225 { X86_REG_XMM16, "xmm16" },
226 { X86_REG_XMM17, "xmm17" },
227 { X86_REG_XMM18, "xmm18" },
228 { X86_REG_XMM19, "xmm19" },
229 { X86_REG_XMM20, "xmm20" },
230 { X86_REG_XMM21, "xmm21" },
231 { X86_REG_XMM22, "xmm22" },
232 { X86_REG_XMM23, "xmm23" },
233 { X86_REG_XMM24, "xmm24" },
234 { X86_REG_XMM25, "xmm25" },
235 { X86_REG_XMM26, "xmm26" },
236 { X86_REG_XMM27, "xmm27" },
237 { X86_REG_XMM28, "xmm28" },
238 { X86_REG_XMM29, "xmm29" },
239 { X86_REG_XMM30, "xmm30" },
240 { X86_REG_XMM31, "xmm31" },
241 { X86_REG_YMM0, "ymm0" },
242 { X86_REG_YMM1, "ymm1" },
243 { X86_REG_YMM2, "ymm2" },
244 { X86_REG_YMM3, "ymm3" },
245 { X86_REG_YMM4, "ymm4" },
246 { X86_REG_YMM5, "ymm5" },
247 { X86_REG_YMM6, "ymm6" },
248 { X86_REG_YMM7, "ymm7" },
249 { X86_REG_YMM8, "ymm8" },
250 { X86_REG_YMM9, "ymm9" },
251 { X86_REG_YMM10, "ymm10" },
252 { X86_REG_YMM11, "ymm11" },
253 { X86_REG_YMM12, "ymm12" },
254 { X86_REG_YMM13, "ymm13" },
255 { X86_REG_YMM14, "ymm14" },
256 { X86_REG_YMM15, "ymm15" },
257 { X86_REG_YMM16, "ymm16" },
258 { X86_REG_YMM17, "ymm17" },
259 { X86_REG_YMM18, "ymm18" },
260 { X86_REG_YMM19, "ymm19" },
261 { X86_REG_YMM20, "ymm20" },
262 { X86_REG_YMM21, "ymm21" },
263 { X86_REG_YMM22, "ymm22" },
264 { X86_REG_YMM23, "ymm23" },
265 { X86_REG_YMM24, "ymm24" },
266 { X86_REG_YMM25, "ymm25" },
267 { X86_REG_YMM26, "ymm26" },
268 { X86_REG_YMM27, "ymm27" },
269 { X86_REG_YMM28, "ymm28" },
270 { X86_REG_YMM29, "ymm29" },
271 { X86_REG_YMM30, "ymm30" },
272 { X86_REG_YMM31, "ymm31" },
273 { X86_REG_ZMM0, "zmm0" },
274 { X86_REG_ZMM1, "zmm1" },
275 { X86_REG_ZMM2, "zmm2" },
276 { X86_REG_ZMM3, "zmm3" },
277 { X86_REG_ZMM4, "zmm4" },
278 { X86_REG_ZMM5, "zmm5" },
279 { X86_REG_ZMM6, "zmm6" },
280 { X86_REG_ZMM7, "zmm7" },
281 { X86_REG_ZMM8, "zmm8" },
282 { X86_REG_ZMM9, "zmm9" },
283 { X86_REG_ZMM10, "zmm10" },
284 { X86_REG_ZMM11, "zmm11" },
285 { X86_REG_ZMM12, "zmm12" },
286 { X86_REG_ZMM13, "zmm13" },
287 { X86_REG_ZMM14, "zmm14" },
288 { X86_REG_ZMM15, "zmm15" },
289 { X86_REG_ZMM16, "zmm16" },
290 { X86_REG_ZMM17, "zmm17" },
291 { X86_REG_ZMM18, "zmm18" },
292 { X86_REG_ZMM19, "zmm19" },
293 { X86_REG_ZMM20, "zmm20" },
294 { X86_REG_ZMM21, "zmm21" },
295 { X86_REG_ZMM22, "zmm22" },
296 { X86_REG_ZMM23, "zmm23" },
297 { X86_REG_ZMM24, "zmm24" },
298 { X86_REG_ZMM25, "zmm25" },
299 { X86_REG_ZMM26, "zmm26" },
300 { X86_REG_ZMM27, "zmm27" },
301 { X86_REG_ZMM28, "zmm28" },
302 { X86_REG_ZMM29, "zmm29" },
303 { X86_REG_ZMM30, "zmm30" },
304 { X86_REG_ZMM31, "zmm31" },
305 { X86_REG_R8B, "r8b" },
306 { X86_REG_R9B, "r9b" },
307 { X86_REG_R10B, "r10b" },
308 { X86_REG_R11B, "r11b" },
309 { X86_REG_R12B, "r12b" },
310 { X86_REG_R13B, "r13b" },
311 { X86_REG_R14B, "r14b" },
312 { X86_REG_R15B, "r15b" },
313 { X86_REG_R8D, "r8d" },
314 { X86_REG_R9D, "r9d" },
315 { X86_REG_R10D, "r10d" },
316 { X86_REG_R11D, "r11d" },
317 { X86_REG_R12D, "r12d" },
318 { X86_REG_R13D, "r13d" },
319 { X86_REG_R14D, "r14d" },
320 { X86_REG_R15D, "r15d" },
321 { X86_REG_R8W, "r8w" },
322 { X86_REG_R9W, "r9w" },
323 { X86_REG_R10W, "r10w" },
324 { X86_REG_R11W, "r11w" },
325 { X86_REG_R12W, "r12w" },
326 { X86_REG_R13W, "r13w" },
327 { X86_REG_R14W, "r14w" },
328 { X86_REG_R15W, "r15w" },
329
330 { X86_REG_BND0, "bnd0" },
331 { X86_REG_BND1, "bnd1" },
332 { X86_REG_BND2, "bnd2" },
333 { X86_REG_BND3, "bnd3" },
334 };
335 #endif
336
337 // register size in non-64bit mode
338 const uint8_t regsize_map_32 [] = {
339 0, // { X86_REG_INVALID, NULL },
340 1, // { X86_REG_AH, "ah" },
341 1, // { X86_REG_AL, "al" },
342 2, // { X86_REG_AX, "ax" },
343 1, // { X86_REG_BH, "bh" },
344 1, // { X86_REG_BL, "bl" },
345 2, // { X86_REG_BP, "bp" },
346 1, // { X86_REG_BPL, "bpl" },
347 2, // { X86_REG_BX, "bx" },
348 1, // { X86_REG_CH, "ch" },
349 1, // { X86_REG_CL, "cl" },
350 2, // { X86_REG_CS, "cs" },
351 2, // { X86_REG_CX, "cx" },
352 1, // { X86_REG_DH, "dh" },
353 2, // { X86_REG_DI, "di" },
354 1, // { X86_REG_DIL, "dil" },
355 1, // { X86_REG_DL, "dl" },
356 2, // { X86_REG_DS, "ds" },
357 2, // { X86_REG_DX, "dx" },
358 4, // { X86_REG_EAX, "eax" },
359 4, // { X86_REG_EBP, "ebp" },
360 4, // { X86_REG_EBX, "ebx" },
361 4, // { X86_REG_ECX, "ecx" },
362 4, // { X86_REG_EDI, "edi" },
363 4, // { X86_REG_EDX, "edx" },
364 4, // { X86_REG_EFLAGS, "flags" },
365 4, // { X86_REG_EIP, "eip" },
366 4, // { X86_REG_EIZ, "eiz" },
367 2, // { X86_REG_ES, "es" },
368 4, // { X86_REG_ESI, "esi" },
369 4, // { X86_REG_ESP, "esp" },
370 10, // { X86_REG_FPSW, "fpsw" },
371 2, // { X86_REG_FS, "fs" },
372 2, // { X86_REG_GS, "gs" },
373 2, // { X86_REG_IP, "ip" },
374 8, // { X86_REG_RAX, "rax" },
375 8, // { X86_REG_RBP, "rbp" },
376 8, // { X86_REG_RBX, "rbx" },
377 8, // { X86_REG_RCX, "rcx" },
378 8, // { X86_REG_RDI, "rdi" },
379 8, // { X86_REG_RDX, "rdx" },
380 8, // { X86_REG_RIP, "rip" },
381 8, // { X86_REG_RIZ, "riz" },
382 8, // { X86_REG_RSI, "rsi" },
383 8, // { X86_REG_RSP, "rsp" },
384 2, // { X86_REG_SI, "si" },
385 1, // { X86_REG_SIL, "sil" },
386 2, // { X86_REG_SP, "sp" },
387 1, // { X86_REG_SPL, "spl" },
388 2, // { X86_REG_SS, "ss" },
389 4, // { X86_REG_CR0, "cr0" },
390 4, // { X86_REG_CR1, "cr1" },
391 4, // { X86_REG_CR2, "cr2" },
392 4, // { X86_REG_CR3, "cr3" },
393 4, // { X86_REG_CR4, "cr4" },
394 8, // { X86_REG_CR5, "cr5" },
395 8, // { X86_REG_CR6, "cr6" },
396 8, // { X86_REG_CR7, "cr7" },
397 8, // { X86_REG_CR8, "cr8" },
398 8, // { X86_REG_CR9, "cr9" },
399 8, // { X86_REG_CR10, "cr10" },
400 8, // { X86_REG_CR11, "cr11" },
401 8, // { X86_REG_CR12, "cr12" },
402 8, // { X86_REG_CR13, "cr13" },
403 8, // { X86_REG_CR14, "cr14" },
404 8, // { X86_REG_CR15, "cr15" },
405 4, // { X86_REG_DR0, "dr0" },
406 4, // { X86_REG_DR1, "dr1" },
407 4, // { X86_REG_DR2, "dr2" },
408 4, // { X86_REG_DR3, "dr3" },
409 4, // { X86_REG_DR4, "dr4" },
410 4, // { X86_REG_DR5, "dr5" },
411 4, // { X86_REG_DR6, "dr6" },
412 4, // { X86_REG_DR7, "dr7" },
413 4, // { X86_REG_DR8, "dr8" },
414 4, // { X86_REG_DR9, "dr9" },
415 4, // { X86_REG_DR10, "dr10" },
416 4, // { X86_REG_DR11, "dr11" },
417 4, // { X86_REG_DR12, "dr12" },
418 4, // { X86_REG_DR13, "dr13" },
419 4, // { X86_REG_DR14, "dr14" },
420 4, // { X86_REG_DR15, "dr15" },
421 10, // { X86_REG_FP0, "fp0" },
422 10, // { X86_REG_FP1, "fp1" },
423 10, // { X86_REG_FP2, "fp2" },
424 10, // { X86_REG_FP3, "fp3" },
425 10, // { X86_REG_FP4, "fp4" },
426 10, // { X86_REG_FP5, "fp5" },
427 10, // { X86_REG_FP6, "fp6" },
428 10, // { X86_REG_FP7, "fp7" },
429 2, // { X86_REG_K0, "k0" },
430 2, // { X86_REG_K1, "k1" },
431 2, // { X86_REG_K2, "k2" },
432 2, // { X86_REG_K3, "k3" },
433 2, // { X86_REG_K4, "k4" },
434 2, // { X86_REG_K5, "k5" },
435 2, // { X86_REG_K6, "k6" },
436 2, // { X86_REG_K7, "k7" },
437 8, // { X86_REG_MM0, "mm0" },
438 8, // { X86_REG_MM1, "mm1" },
439 8, // { X86_REG_MM2, "mm2" },
440 8, // { X86_REG_MM3, "mm3" },
441 8, // { X86_REG_MM4, "mm4" },
442 8, // { X86_REG_MM5, "mm5" },
443 8, // { X86_REG_MM6, "mm6" },
444 8, // { X86_REG_MM7, "mm7" },
445 8, // { X86_REG_R8, "r8" },
446 8, // { X86_REG_R9, "r9" },
447 8, // { X86_REG_R10, "r10" },
448 8, // { X86_REG_R11, "r11" },
449 8, // { X86_REG_R12, "r12" },
450 8, // { X86_REG_R13, "r13" },
451 8, // { X86_REG_R14, "r14" },
452 8, // { X86_REG_R15, "r15" },
453 10, // { X86_REG_ST0, "st0" },
454 10, // { X86_REG_ST1, "st1" },
455 10, // { X86_REG_ST2, "st2" },
456 10, // { X86_REG_ST3, "st3" },
457 10, // { X86_REG_ST4, "st4" },
458 10, // { X86_REG_ST5, "st5" },
459 10, // { X86_REG_ST6, "st6" },
460 10, // { X86_REG_ST7, "st7" },
461 16, // { X86_REG_XMM0, "xmm0" },
462 16, // { X86_REG_XMM1, "xmm1" },
463 16, // { X86_REG_XMM2, "xmm2" },
464 16, // { X86_REG_XMM3, "xmm3" },
465 16, // { X86_REG_XMM4, "xmm4" },
466 16, // { X86_REG_XMM5, "xmm5" },
467 16, // { X86_REG_XMM6, "xmm6" },
468 16, // { X86_REG_XMM7, "xmm7" },
469 16, // { X86_REG_XMM8, "xmm8" },
470 16, // { X86_REG_XMM9, "xmm9" },
471 16, // { X86_REG_XMM10, "xmm10" },
472 16, // { X86_REG_XMM11, "xmm11" },
473 16, // { X86_REG_XMM12, "xmm12" },
474 16, // { X86_REG_XMM13, "xmm13" },
475 16, // { X86_REG_XMM14, "xmm14" },
476 16, // { X86_REG_XMM15, "xmm15" },
477 16, // { X86_REG_XMM16, "xmm16" },
478 16, // { X86_REG_XMM17, "xmm17" },
479 16, // { X86_REG_XMM18, "xmm18" },
480 16, // { X86_REG_XMM19, "xmm19" },
481 16, // { X86_REG_XMM20, "xmm20" },
482 16, // { X86_REG_XMM21, "xmm21" },
483 16, // { X86_REG_XMM22, "xmm22" },
484 16, // { X86_REG_XMM23, "xmm23" },
485 16, // { X86_REG_XMM24, "xmm24" },
486 16, // { X86_REG_XMM25, "xmm25" },
487 16, // { X86_REG_XMM26, "xmm26" },
488 16, // { X86_REG_XMM27, "xmm27" },
489 16, // { X86_REG_XMM28, "xmm28" },
490 16, // { X86_REG_XMM29, "xmm29" },
491 16, // { X86_REG_XMM30, "xmm30" },
492 16, // { X86_REG_XMM31, "xmm31" },
493 32, // { X86_REG_YMM0, "ymm0" },
494 32, // { X86_REG_YMM1, "ymm1" },
495 32, // { X86_REG_YMM2, "ymm2" },
496 32, // { X86_REG_YMM3, "ymm3" },
497 32, // { X86_REG_YMM4, "ymm4" },
498 32, // { X86_REG_YMM5, "ymm5" },
499 32, // { X86_REG_YMM6, "ymm6" },
500 32, // { X86_REG_YMM7, "ymm7" },
501 32, // { X86_REG_YMM8, "ymm8" },
502 32, // { X86_REG_YMM9, "ymm9" },
503 32, // { X86_REG_YMM10, "ymm10" },
504 32, // { X86_REG_YMM11, "ymm11" },
505 32, // { X86_REG_YMM12, "ymm12" },
506 32, // { X86_REG_YMM13, "ymm13" },
507 32, // { X86_REG_YMM14, "ymm14" },
508 32, // { X86_REG_YMM15, "ymm15" },
509 32, // { X86_REG_YMM16, "ymm16" },
510 32, // { X86_REG_YMM17, "ymm17" },
511 32, // { X86_REG_YMM18, "ymm18" },
512 32, // { X86_REG_YMM19, "ymm19" },
513 32, // { X86_REG_YMM20, "ymm20" },
514 32, // { X86_REG_YMM21, "ymm21" },
515 32, // { X86_REG_YMM22, "ymm22" },
516 32, // { X86_REG_YMM23, "ymm23" },
517 32, // { X86_REG_YMM24, "ymm24" },
518 32, // { X86_REG_YMM25, "ymm25" },
519 32, // { X86_REG_YMM26, "ymm26" },
520 32, // { X86_REG_YMM27, "ymm27" },
521 32, // { X86_REG_YMM28, "ymm28" },
522 32, // { X86_REG_YMM29, "ymm29" },
523 32, // { X86_REG_YMM30, "ymm30" },
524 32, // { X86_REG_YMM31, "ymm31" },
525 64, // { X86_REG_ZMM0, "zmm0" },
526 64, // { X86_REG_ZMM1, "zmm1" },
527 64, // { X86_REG_ZMM2, "zmm2" },
528 64, // { X86_REG_ZMM3, "zmm3" },
529 64, // { X86_REG_ZMM4, "zmm4" },
530 64, // { X86_REG_ZMM5, "zmm5" },
531 64, // { X86_REG_ZMM6, "zmm6" },
532 64, // { X86_REG_ZMM7, "zmm7" },
533 64, // { X86_REG_ZMM8, "zmm8" },
534 64, // { X86_REG_ZMM9, "zmm9" },
535 64, // { X86_REG_ZMM10, "zmm10" },
536 64, // { X86_REG_ZMM11, "zmm11" },
537 64, // { X86_REG_ZMM12, "zmm12" },
538 64, // { X86_REG_ZMM13, "zmm13" },
539 64, // { X86_REG_ZMM14, "zmm14" },
540 64, // { X86_REG_ZMM15, "zmm15" },
541 64, // { X86_REG_ZMM16, "zmm16" },
542 64, // { X86_REG_ZMM17, "zmm17" },
543 64, // { X86_REG_ZMM18, "zmm18" },
544 64, // { X86_REG_ZMM19, "zmm19" },
545 64, // { X86_REG_ZMM20, "zmm20" },
546 64, // { X86_REG_ZMM21, "zmm21" },
547 64, // { X86_REG_ZMM22, "zmm22" },
548 64, // { X86_REG_ZMM23, "zmm23" },
549 64, // { X86_REG_ZMM24, "zmm24" },
550 64, // { X86_REG_ZMM25, "zmm25" },
551 64, // { X86_REG_ZMM26, "zmm26" },
552 64, // { X86_REG_ZMM27, "zmm27" },
553 64, // { X86_REG_ZMM28, "zmm28" },
554 64, // { X86_REG_ZMM29, "zmm29" },
555 64, // { X86_REG_ZMM30, "zmm30" },
556 64, // { X86_REG_ZMM31, "zmm31" },
557 1, // { X86_REG_R8B, "r8b" },
558 1, // { X86_REG_R9B, "r9b" },
559 1, // { X86_REG_R10B, "r10b" },
560 1, // { X86_REG_R11B, "r11b" },
561 1, // { X86_REG_R12B, "r12b" },
562 1, // { X86_REG_R13B, "r13b" },
563 1, // { X86_REG_R14B, "r14b" },
564 1, // { X86_REG_R15B, "r15b" },
565 4, // { X86_REG_R8D, "r8d" },
566 4, // { X86_REG_R9D, "r9d" },
567 4, // { X86_REG_R10D, "r10d" },
568 4, // { X86_REG_R11D, "r11d" },
569 4, // { X86_REG_R12D, "r12d" },
570 4, // { X86_REG_R13D, "r13d" },
571 4, // { X86_REG_R14D, "r14d" },
572 4, // { X86_REG_R15D, "r15d" },
573 2, // { X86_REG_R8W, "r8w" },
574 2, // { X86_REG_R9W, "r9w" },
575 2, // { X86_REG_R10W, "r10w" },
576 2, // { X86_REG_R11W, "r11w" },
577 2, // { X86_REG_R12W, "r12w" },
578 2, // { X86_REG_R13W, "r13w" },
579 2, // { X86_REG_R14W, "r14w" },
580 2, // { X86_REG_R15W, "r15w" },
581 16, // { X86_REG_BND0, "bnd0" },
582 16, // { X86_REG_BND1, "bnd0" },
583 16, // { X86_REG_BND2, "bnd0" },
584 16, // { X86_REG_BND3, "bnd0" },
585 };
586
587 // register size in 64bit mode
588 const uint8_t regsize_map_64 [] = {
589 0, // { X86_REG_INVALID, NULL },
590 1, // { X86_REG_AH, "ah" },
591 1, // { X86_REG_AL, "al" },
592 2, // { X86_REG_AX, "ax" },
593 1, // { X86_REG_BH, "bh" },
594 1, // { X86_REG_BL, "bl" },
595 2, // { X86_REG_BP, "bp" },
596 1, // { X86_REG_BPL, "bpl" },
597 2, // { X86_REG_BX, "bx" },
598 1, // { X86_REG_CH, "ch" },
599 1, // { X86_REG_CL, "cl" },
600 2, // { X86_REG_CS, "cs" },
601 2, // { X86_REG_CX, "cx" },
602 1, // { X86_REG_DH, "dh" },
603 2, // { X86_REG_DI, "di" },
604 1, // { X86_REG_DIL, "dil" },
605 1, // { X86_REG_DL, "dl" },
606 2, // { X86_REG_DS, "ds" },
607 2, // { X86_REG_DX, "dx" },
608 4, // { X86_REG_EAX, "eax" },
609 4, // { X86_REG_EBP, "ebp" },
610 4, // { X86_REG_EBX, "ebx" },
611 4, // { X86_REG_ECX, "ecx" },
612 4, // { X86_REG_EDI, "edi" },
613 4, // { X86_REG_EDX, "edx" },
614 8, // { X86_REG_EFLAGS, "flags" },
615 4, // { X86_REG_EIP, "eip" },
616 4, // { X86_REG_EIZ, "eiz" },
617 2, // { X86_REG_ES, "es" },
618 4, // { X86_REG_ESI, "esi" },
619 4, // { X86_REG_ESP, "esp" },
620 10, // { X86_REG_FPSW, "fpsw" },
621 2, // { X86_REG_FS, "fs" },
622 2, // { X86_REG_GS, "gs" },
623 2, // { X86_REG_IP, "ip" },
624 8, // { X86_REG_RAX, "rax" },
625 8, // { X86_REG_RBP, "rbp" },
626 8, // { X86_REG_RBX, "rbx" },
627 8, // { X86_REG_RCX, "rcx" },
628 8, // { X86_REG_RDI, "rdi" },
629 8, // { X86_REG_RDX, "rdx" },
630 8, // { X86_REG_RIP, "rip" },
631 8, // { X86_REG_RIZ, "riz" },
632 8, // { X86_REG_RSI, "rsi" },
633 8, // { X86_REG_RSP, "rsp" },
634 2, // { X86_REG_SI, "si" },
635 1, // { X86_REG_SIL, "sil" },
636 2, // { X86_REG_SP, "sp" },
637 1, // { X86_REG_SPL, "spl" },
638 2, // { X86_REG_SS, "ss" },
639 8, // { X86_REG_CR0, "cr0" },
640 8, // { X86_REG_CR1, "cr1" },
641 8, // { X86_REG_CR2, "cr2" },
642 8, // { X86_REG_CR3, "cr3" },
643 8, // { X86_REG_CR4, "cr4" },
644 8, // { X86_REG_CR5, "cr5" },
645 8, // { X86_REG_CR6, "cr6" },
646 8, // { X86_REG_CR7, "cr7" },
647 8, // { X86_REG_CR8, "cr8" },
648 8, // { X86_REG_CR9, "cr9" },
649 8, // { X86_REG_CR10, "cr10" },
650 8, // { X86_REG_CR11, "cr11" },
651 8, // { X86_REG_CR12, "cr12" },
652 8, // { X86_REG_CR13, "cr13" },
653 8, // { X86_REG_CR14, "cr14" },
654 8, // { X86_REG_CR15, "cr15" },
655 8, // { X86_REG_DR0, "dr0" },
656 8, // { X86_REG_DR1, "dr1" },
657 8, // { X86_REG_DR2, "dr2" },
658 8, // { X86_REG_DR3, "dr3" },
659 8, // { X86_REG_DR4, "dr4" },
660 8, // { X86_REG_DR5, "dr5" },
661 8, // { X86_REG_DR6, "dr6" },
662 8, // { X86_REG_DR7, "dr7" },
663 8, // { X86_REG_DR8, "dr8" },
664 8, // { X86_REG_DR9, "dr9" },
665 8, // { X86_REG_DR10, "dr10" },
666 8, // { X86_REG_DR11, "dr11" },
667 8, // { X86_REG_DR12, "dr12" },
668 8, // { X86_REG_DR13, "dr13" },
669 8, // { X86_REG_DR14, "dr14" },
670 8, // { X86_REG_DR15, "dr15" },
671 10, // { X86_REG_FP0, "fp0" },
672 10, // { X86_REG_FP1, "fp1" },
673 10, // { X86_REG_FP2, "fp2" },
674 10, // { X86_REG_FP3, "fp3" },
675 10, // { X86_REG_FP4, "fp4" },
676 10, // { X86_REG_FP5, "fp5" },
677 10, // { X86_REG_FP6, "fp6" },
678 10, // { X86_REG_FP7, "fp7" },
679 2, // { X86_REG_K0, "k0" },
680 2, // { X86_REG_K1, "k1" },
681 2, // { X86_REG_K2, "k2" },
682 2, // { X86_REG_K3, "k3" },
683 2, // { X86_REG_K4, "k4" },
684 2, // { X86_REG_K5, "k5" },
685 2, // { X86_REG_K6, "k6" },
686 2, // { X86_REG_K7, "k7" },
687 8, // { X86_REG_MM0, "mm0" },
688 8, // { X86_REG_MM1, "mm1" },
689 8, // { X86_REG_MM2, "mm2" },
690 8, // { X86_REG_MM3, "mm3" },
691 8, // { X86_REG_MM4, "mm4" },
692 8, // { X86_REG_MM5, "mm5" },
693 8, // { X86_REG_MM6, "mm6" },
694 8, // { X86_REG_MM7, "mm7" },
695 8, // { X86_REG_R8, "r8" },
696 8, // { X86_REG_R9, "r9" },
697 8, // { X86_REG_R10, "r10" },
698 8, // { X86_REG_R11, "r11" },
699 8, // { X86_REG_R12, "r12" },
700 8, // { X86_REG_R13, "r13" },
701 8, // { X86_REG_R14, "r14" },
702 8, // { X86_REG_R15, "r15" },
703 10, // { X86_REG_ST0, "st0" },
704 10, // { X86_REG_ST1, "st1" },
705 10, // { X86_REG_ST2, "st2" },
706 10, // { X86_REG_ST3, "st3" },
707 10, // { X86_REG_ST4, "st4" },
708 10, // { X86_REG_ST5, "st5" },
709 10, // { X86_REG_ST6, "st6" },
710 10, // { X86_REG_ST7, "st7" },
711 16, // { X86_REG_XMM0, "xmm0" },
712 16, // { X86_REG_XMM1, "xmm1" },
713 16, // { X86_REG_XMM2, "xmm2" },
714 16, // { X86_REG_XMM3, "xmm3" },
715 16, // { X86_REG_XMM4, "xmm4" },
716 16, // { X86_REG_XMM5, "xmm5" },
717 16, // { X86_REG_XMM6, "xmm6" },
718 16, // { X86_REG_XMM7, "xmm7" },
719 16, // { X86_REG_XMM8, "xmm8" },
720 16, // { X86_REG_XMM9, "xmm9" },
721 16, // { X86_REG_XMM10, "xmm10" },
722 16, // { X86_REG_XMM11, "xmm11" },
723 16, // { X86_REG_XMM12, "xmm12" },
724 16, // { X86_REG_XMM13, "xmm13" },
725 16, // { X86_REG_XMM14, "xmm14" },
726 16, // { X86_REG_XMM15, "xmm15" },
727 16, // { X86_REG_XMM16, "xmm16" },
728 16, // { X86_REG_XMM17, "xmm17" },
729 16, // { X86_REG_XMM18, "xmm18" },
730 16, // { X86_REG_XMM19, "xmm19" },
731 16, // { X86_REG_XMM20, "xmm20" },
732 16, // { X86_REG_XMM21, "xmm21" },
733 16, // { X86_REG_XMM22, "xmm22" },
734 16, // { X86_REG_XMM23, "xmm23" },
735 16, // { X86_REG_XMM24, "xmm24" },
736 16, // { X86_REG_XMM25, "xmm25" },
737 16, // { X86_REG_XMM26, "xmm26" },
738 16, // { X86_REG_XMM27, "xmm27" },
739 16, // { X86_REG_XMM28, "xmm28" },
740 16, // { X86_REG_XMM29, "xmm29" },
741 16, // { X86_REG_XMM30, "xmm30" },
742 16, // { X86_REG_XMM31, "xmm31" },
743 32, // { X86_REG_YMM0, "ymm0" },
744 32, // { X86_REG_YMM1, "ymm1" },
745 32, // { X86_REG_YMM2, "ymm2" },
746 32, // { X86_REG_YMM3, "ymm3" },
747 32, // { X86_REG_YMM4, "ymm4" },
748 32, // { X86_REG_YMM5, "ymm5" },
749 32, // { X86_REG_YMM6, "ymm6" },
750 32, // { X86_REG_YMM7, "ymm7" },
751 32, // { X86_REG_YMM8, "ymm8" },
752 32, // { X86_REG_YMM9, "ymm9" },
753 32, // { X86_REG_YMM10, "ymm10" },
754 32, // { X86_REG_YMM11, "ymm11" },
755 32, // { X86_REG_YMM12, "ymm12" },
756 32, // { X86_REG_YMM13, "ymm13" },
757 32, // { X86_REG_YMM14, "ymm14" },
758 32, // { X86_REG_YMM15, "ymm15" },
759 32, // { X86_REG_YMM16, "ymm16" },
760 32, // { X86_REG_YMM17, "ymm17" },
761 32, // { X86_REG_YMM18, "ymm18" },
762 32, // { X86_REG_YMM19, "ymm19" },
763 32, // { X86_REG_YMM20, "ymm20" },
764 32, // { X86_REG_YMM21, "ymm21" },
765 32, // { X86_REG_YMM22, "ymm22" },
766 32, // { X86_REG_YMM23, "ymm23" },
767 32, // { X86_REG_YMM24, "ymm24" },
768 32, // { X86_REG_YMM25, "ymm25" },
769 32, // { X86_REG_YMM26, "ymm26" },
770 32, // { X86_REG_YMM27, "ymm27" },
771 32, // { X86_REG_YMM28, "ymm28" },
772 32, // { X86_REG_YMM29, "ymm29" },
773 32, // { X86_REG_YMM30, "ymm30" },
774 32, // { X86_REG_YMM31, "ymm31" },
775 64, // { X86_REG_ZMM0, "zmm0" },
776 64, // { X86_REG_ZMM1, "zmm1" },
777 64, // { X86_REG_ZMM2, "zmm2" },
778 64, // { X86_REG_ZMM3, "zmm3" },
779 64, // { X86_REG_ZMM4, "zmm4" },
780 64, // { X86_REG_ZMM5, "zmm5" },
781 64, // { X86_REG_ZMM6, "zmm6" },
782 64, // { X86_REG_ZMM7, "zmm7" },
783 64, // { X86_REG_ZMM8, "zmm8" },
784 64, // { X86_REG_ZMM9, "zmm9" },
785 64, // { X86_REG_ZMM10, "zmm10" },
786 64, // { X86_REG_ZMM11, "zmm11" },
787 64, // { X86_REG_ZMM12, "zmm12" },
788 64, // { X86_REG_ZMM13, "zmm13" },
789 64, // { X86_REG_ZMM14, "zmm14" },
790 64, // { X86_REG_ZMM15, "zmm15" },
791 64, // { X86_REG_ZMM16, "zmm16" },
792 64, // { X86_REG_ZMM17, "zmm17" },
793 64, // { X86_REG_ZMM18, "zmm18" },
794 64, // { X86_REG_ZMM19, "zmm19" },
795 64, // { X86_REG_ZMM20, "zmm20" },
796 64, // { X86_REG_ZMM21, "zmm21" },
797 64, // { X86_REG_ZMM22, "zmm22" },
798 64, // { X86_REG_ZMM23, "zmm23" },
799 64, // { X86_REG_ZMM24, "zmm24" },
800 64, // { X86_REG_ZMM25, "zmm25" },
801 64, // { X86_REG_ZMM26, "zmm26" },
802 64, // { X86_REG_ZMM27, "zmm27" },
803 64, // { X86_REG_ZMM28, "zmm28" },
804 64, // { X86_REG_ZMM29, "zmm29" },
805 64, // { X86_REG_ZMM30, "zmm30" },
806 64, // { X86_REG_ZMM31, "zmm31" },
807 1, // { X86_REG_R8B, "r8b" },
808 1, // { X86_REG_R9B, "r9b" },
809 1, // { X86_REG_R10B, "r10b" },
810 1, // { X86_REG_R11B, "r11b" },
811 1, // { X86_REG_R12B, "r12b" },
812 1, // { X86_REG_R13B, "r13b" },
813 1, // { X86_REG_R14B, "r14b" },
814 1, // { X86_REG_R15B, "r15b" },
815 4, // { X86_REG_R8D, "r8d" },
816 4, // { X86_REG_R9D, "r9d" },
817 4, // { X86_REG_R10D, "r10d" },
818 4, // { X86_REG_R11D, "r11d" },
819 4, // { X86_REG_R12D, "r12d" },
820 4, // { X86_REG_R13D, "r13d" },
821 4, // { X86_REG_R14D, "r14d" },
822 4, // { X86_REG_R15D, "r15d" },
823 2, // { X86_REG_R8W, "r8w" },
824 2, // { X86_REG_R9W, "r9w" },
825 2, // { X86_REG_R10W, "r10w" },
826 2, // { X86_REG_R11W, "r11w" },
827 2, // { X86_REG_R12W, "r12w" },
828 2, // { X86_REG_R13W, "r13w" },
829 2, // { X86_REG_R14W, "r14w" },
830 2, // { X86_REG_R15W, "r15w" },
831 16, // { X86_REG_BND0, "bnd0" },
832 16, // { X86_REG_BND1, "bnd0" },
833 16, // { X86_REG_BND2, "bnd0" },
834 16, // { X86_REG_BND3, "bnd0" },
835 };
836
X86_reg_name(csh handle,unsigned int reg)837 const char *X86_reg_name(csh handle, unsigned int reg)
838 {
839 #ifndef CAPSTONE_DIET
840 cs_struct *ud = (cs_struct *)handle;
841
842 if (reg >= ARR_SIZE(reg_name_maps))
843 return NULL;
844
845 if (reg == X86_REG_EFLAGS) {
846 if (ud->mode & CS_MODE_32)
847 return "eflags";
848 if (ud->mode & CS_MODE_64)
849 return "rflags";
850 }
851
852 return reg_name_maps[reg].name;
853 #else
854 return NULL;
855 #endif
856 }
857
858 #ifndef CAPSTONE_DIET
859 static const char * const insn_name_maps[] = {
860 NULL, // X86_INS_INVALID
861 #ifndef CAPSTONE_X86_REDUCE
862 #include "X86MappingInsnName.inc"
863 #else
864 #include "X86MappingInsnName_reduce.inc"
865 #endif
866 };
867 #endif
868
869 // NOTE: insn_name_maps[] is sorted in order
X86_insn_name(csh handle,unsigned int id)870 const char *X86_insn_name(csh handle, unsigned int id)
871 {
872 #ifndef CAPSTONE_DIET
873 if (id >= ARR_SIZE(insn_name_maps))
874 return NULL;
875
876 return insn_name_maps[id];
877 #else
878 return NULL;
879 #endif
880 }
881
882 #ifndef CAPSTONE_DIET
883 static const name_map group_name_maps[] = {
884 // generic groups
885 { X86_GRP_INVALID, NULL },
886 { X86_GRP_JUMP, "jump" },
887 { X86_GRP_CALL, "call" },
888 { X86_GRP_RET, "ret" },
889 { X86_GRP_INT, "int" },
890 { X86_GRP_IRET, "iret" },
891 { X86_GRP_PRIVILEGE, "privilege" },
892 { X86_GRP_BRANCH_RELATIVE, "branch_relative" },
893
894 // architecture-specific groups
895 { X86_GRP_VM, "vm" },
896 { X86_GRP_3DNOW, "3dnow" },
897 { X86_GRP_AES, "aes" },
898 { X86_GRP_ADX, "adx" },
899 { X86_GRP_AVX, "avx" },
900 { X86_GRP_AVX2, "avx2" },
901 { X86_GRP_AVX512, "avx512" },
902 { X86_GRP_BMI, "bmi" },
903 { X86_GRP_BMI2, "bmi2" },
904 { X86_GRP_CMOV, "cmov" },
905 { X86_GRP_F16C, "fc16" },
906 { X86_GRP_FMA, "fma" },
907 { X86_GRP_FMA4, "fma4" },
908 { X86_GRP_FSGSBASE, "fsgsbase" },
909 { X86_GRP_HLE, "hle" },
910 { X86_GRP_MMX, "mmx" },
911 { X86_GRP_MODE32, "mode32" },
912 { X86_GRP_MODE64, "mode64" },
913 { X86_GRP_RTM, "rtm" },
914 { X86_GRP_SHA, "sha" },
915 { X86_GRP_SSE1, "sse1" },
916 { X86_GRP_SSE2, "sse2" },
917 { X86_GRP_SSE3, "sse3" },
918 { X86_GRP_SSE41, "sse41" },
919 { X86_GRP_SSE42, "sse42" },
920 { X86_GRP_SSE4A, "sse4a" },
921 { X86_GRP_SSSE3, "ssse3" },
922 { X86_GRP_PCLMUL, "pclmul" },
923 { X86_GRP_XOP, "xop" },
924 { X86_GRP_CDI, "cdi" },
925 { X86_GRP_ERI, "eri" },
926 { X86_GRP_TBM, "tbm" },
927 { X86_GRP_16BITMODE, "16bitmode" },
928 { X86_GRP_NOT64BITMODE, "not64bitmode" },
929 { X86_GRP_SGX, "sgx" },
930 { X86_GRP_DQI, "dqi" },
931 { X86_GRP_BWI, "bwi" },
932 { X86_GRP_PFI, "pfi" },
933 { X86_GRP_VLX, "vlx" },
934 { X86_GRP_SMAP, "smap" },
935 { X86_GRP_NOVLX, "novlx" },
936 { X86_GRP_FPU, "fpu" },
937 };
938 #endif
939
X86_group_name(csh handle,unsigned int id)940 const char *X86_group_name(csh handle, unsigned int id)
941 {
942 #ifndef CAPSTONE_DIET
943 return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
944 #else
945 return NULL;
946 #endif
947 }
948
949 #define GET_INSTRINFO_ENUM
950 #ifdef CAPSTONE_X86_REDUCE
951 #include "X86GenInstrInfo_reduce.inc"
952
953 const insn_map_x86 insns[] = { // reduce x86 instructions
954 #include "X86MappingInsn_reduce.inc"
955 };
956 #else
957 #include "X86GenInstrInfo.inc"
958
959 const insn_map_x86 insns[] = { // full x86 instructions
960 #include "X86MappingInsn.inc"
961 };
962 #endif
963
964 #ifndef CAPSTONE_DIET
965 // in arr, replace r1 = r2
arr_replace(uint16_t * arr,uint8_t max,x86_reg r1,x86_reg r2)966 static void arr_replace(uint16_t *arr, uint8_t max, x86_reg r1, x86_reg r2)
967 {
968 uint8_t i;
969
970 for(i = 0; i < max; i++) {
971 if (arr[i] == r1) {
972 arr[i] = r2;
973 break;
974 }
975 }
976 }
977 #endif
978
979 // look for @id in @insns
980 // return -1 if not found
find_insn(unsigned int id)981 unsigned int find_insn(unsigned int id)
982 {
983 // binary searching since the IDs are sorted in order
984 unsigned int left, right, m;
985 unsigned int max = ARR_SIZE(insns);
986
987 right = max - 1;
988
989 if (id < insns[0].id || id > insns[right].id)
990 // not found
991 return -1;
992
993 left = 0;
994
995 while(left <= right) {
996 m = (left + right) / 2;
997 if (id == insns[m].id) {
998 return m;
999 }
1000
1001 if (id < insns[m].id)
1002 right = m - 1;
1003 else
1004 left = m + 1;
1005 }
1006
1007 // not found
1008 // printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id);
1009 return -1;
1010 }
1011
1012 // given internal insn id, return public instruction info
X86_get_insn_id(cs_struct * h,cs_insn * insn,unsigned int id)1013 void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
1014 {
1015 unsigned int i = find_insn(id);
1016 if (i != -1) {
1017 insn->id = insns[i].mapid;
1018
1019 if (h->detail) {
1020 #ifndef CAPSTONE_DIET
1021 memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
1022 insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
1023
1024 // special cases when regs_write[] depends on arch
1025 switch(id) {
1026 default:
1027 memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
1028 insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
1029 break;
1030 case X86_RDTSC:
1031 if (h->mode == CS_MODE_64) {
1032 memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
1033 insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
1034 } else {
1035 insn->detail->regs_write[0] = X86_REG_EAX;
1036 insn->detail->regs_write[1] = X86_REG_EDX;
1037 insn->detail->regs_write_count = 2;
1038 }
1039 break;
1040 case X86_RDTSCP:
1041 if (h->mode == CS_MODE_64) {
1042 memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
1043 insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
1044 } else {
1045 insn->detail->regs_write[0] = X86_REG_EAX;
1046 insn->detail->regs_write[1] = X86_REG_ECX;
1047 insn->detail->regs_write[2] = X86_REG_EDX;
1048 insn->detail->regs_write_count = 3;
1049 }
1050 break;
1051 }
1052
1053 switch(insn->id) {
1054 default:
1055 break;
1056
1057 case X86_INS_LOOP:
1058 case X86_INS_LOOPE:
1059 case X86_INS_LOOPNE:
1060 switch(h->mode) {
1061 default: break;
1062 case CS_MODE_16:
1063 insn->detail->regs_read[0] = X86_REG_CX;
1064 insn->detail->regs_read_count = 1;
1065 insn->detail->regs_write[0] = X86_REG_CX;
1066 insn->detail->regs_write_count = 1;
1067 break;
1068 case CS_MODE_32:
1069 insn->detail->regs_read[0] = X86_REG_ECX;
1070 insn->detail->regs_read_count = 1;
1071 insn->detail->regs_write[0] = X86_REG_ECX;
1072 insn->detail->regs_write_count = 1;
1073 break;
1074 case CS_MODE_64:
1075 insn->detail->regs_read[0] = X86_REG_RCX;
1076 insn->detail->regs_read_count = 1;
1077 insn->detail->regs_write[0] = X86_REG_RCX;
1078 insn->detail->regs_write_count = 1;
1079 break;
1080 }
1081
1082 // LOOPE & LOOPNE also read EFLAGS
1083 if (insn->id != X86_INS_LOOP) {
1084 insn->detail->regs_read[1] = X86_REG_EFLAGS;
1085 insn->detail->regs_read_count = 2;
1086 }
1087
1088 break;
1089
1090 case X86_INS_LODSB:
1091 case X86_INS_LODSD:
1092 case X86_INS_LODSQ:
1093 case X86_INS_LODSW:
1094 switch(h->mode) {
1095 default:
1096 break;
1097 case CS_MODE_16:
1098 arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI);
1099 arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI);
1100 break;
1101 case CS_MODE_64:
1102 arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI);
1103 arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI);
1104 break;
1105 }
1106 break;
1107
1108 case X86_INS_SCASB:
1109 case X86_INS_SCASW:
1110 case X86_INS_SCASQ:
1111 case X86_INS_STOSB:
1112 case X86_INS_STOSD:
1113 case X86_INS_STOSQ:
1114 case X86_INS_STOSW:
1115 switch(h->mode) {
1116 default:
1117 break;
1118 case CS_MODE_16:
1119 arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI);
1120 arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI);
1121 break;
1122 case CS_MODE_64:
1123 arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI);
1124 arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI);
1125 break;
1126 }
1127 break;
1128
1129 case X86_INS_CMPSB:
1130 case X86_INS_CMPSD:
1131 case X86_INS_CMPSQ:
1132 case X86_INS_CMPSW:
1133 case X86_INS_MOVSB:
1134 case X86_INS_MOVSW:
1135 case X86_INS_MOVSD:
1136 case X86_INS_MOVSQ:
1137 switch(h->mode) {
1138 default:
1139 break;
1140 case CS_MODE_16:
1141 arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI);
1142 arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI);
1143 arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI);
1144 arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI);
1145 break;
1146 case CS_MODE_64:
1147 arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI);
1148 arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI);
1149 arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI);
1150 arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI);
1151 break;
1152 }
1153 break;
1154
1155 case X86_INS_RET:
1156 switch(h->mode) {
1157 case CS_MODE_16:
1158 insn->detail->regs_write[0] = X86_REG_SP;
1159 insn->detail->regs_read[0] = X86_REG_SP;
1160 break;
1161 case CS_MODE_32:
1162 insn->detail->regs_write[0] = X86_REG_ESP;
1163 insn->detail->regs_read[0] = X86_REG_ESP;
1164 break;
1165 default: // 64-bit
1166 insn->detail->regs_write[0] = X86_REG_RSP;
1167 insn->detail->regs_read[0] = X86_REG_RSP;
1168 break;
1169 }
1170 insn->detail->regs_write_count = 1;
1171 insn->detail->regs_read_count = 1;
1172 break;
1173 }
1174
1175 memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
1176 insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
1177
1178 if (insns[i].branch || insns[i].indirect_branch) {
1179 // this insn also belongs to JUMP group. add JUMP group
1180 insn->detail->groups[insn->detail->groups_count] = X86_GRP_JUMP;
1181 insn->detail->groups_count++;
1182 }
1183
1184 switch (insns[i].id) {
1185 case X86_OUT8ir:
1186 case X86_OUT16ir:
1187 case X86_OUT32ir:
1188 if (insn->detail->x86.operands[0].imm == -78) {
1189 // Writing to port 0xb2 causes an SMI on most platforms
1190 // See: http://cs.gmu.edu/~tr-admin/papers/GMU-CS-TR-2011-8.pdf
1191 insn->detail->groups[insn->detail->groups_count] = X86_GRP_INT;
1192 insn->detail->groups_count++;
1193 }
1194 break;
1195
1196 default:
1197 break;
1198 }
1199 #endif
1200 }
1201 }
1202 }
1203
1204 // map special instructions with accumulate registers.
1205 // this is needed because LLVM embeds these register names into AsmStrs[],
1206 // but not separately in operands
1207 struct insn_reg {
1208 uint16_t insn;
1209 x86_reg reg;
1210 enum cs_ac_type access;
1211 };
1212
1213 struct insn_reg2 {
1214 uint16_t insn;
1215 x86_reg reg1, reg2;
1216 enum cs_ac_type access1, access2;
1217 };
1218
1219 static const struct insn_reg insn_regs_att[] = {
1220 { X86_INSB, X86_REG_DX, CS_AC_READ },
1221 { X86_INSL, X86_REG_DX, CS_AC_READ },
1222 { X86_INSW, X86_REG_DX, CS_AC_READ },
1223 { X86_MOV16o16a, X86_REG_AX, CS_AC_READ },
1224 { X86_MOV16o32a, X86_REG_AX, CS_AC_READ },
1225 { X86_MOV16o64a, X86_REG_AX, CS_AC_READ },
1226 { X86_MOV32o16a, X86_REG_EAX, CS_AC_READ },
1227 { X86_MOV32o32a, X86_REG_EAX, CS_AC_READ },
1228 { X86_MOV32o64a, X86_REG_EAX, CS_AC_READ },
1229 { X86_MOV64o32a, X86_REG_RAX, CS_AC_READ },
1230 { X86_MOV64o64a, X86_REG_RAX, CS_AC_READ },
1231 { X86_MOV8o16a, X86_REG_AL, CS_AC_READ },
1232 { X86_MOV8o32a, X86_REG_AL, CS_AC_READ },
1233 { X86_MOV8o64a, X86_REG_AL, CS_AC_READ },
1234 { X86_OUT16ir, X86_REG_AX, CS_AC_READ },
1235 { X86_OUT32ir, X86_REG_EAX, CS_AC_READ },
1236 { X86_OUT8ir, X86_REG_AL, CS_AC_READ },
1237 { X86_POPDS16, X86_REG_DS, CS_AC_WRITE },
1238 { X86_POPDS32, X86_REG_DS, CS_AC_WRITE },
1239 { X86_POPES16, X86_REG_ES, CS_AC_WRITE },
1240 { X86_POPES32, X86_REG_ES, CS_AC_WRITE },
1241 { X86_POPFS16, X86_REG_FS, CS_AC_WRITE },
1242 { X86_POPFS32, X86_REG_FS, CS_AC_WRITE },
1243 { X86_POPFS64, X86_REG_FS, CS_AC_WRITE },
1244 { X86_POPGS16, X86_REG_GS, CS_AC_WRITE },
1245 { X86_POPGS32, X86_REG_GS, CS_AC_WRITE },
1246 { X86_POPGS64, X86_REG_GS, CS_AC_WRITE },
1247 { X86_POPSS16, X86_REG_SS, CS_AC_WRITE },
1248 { X86_POPSS32, X86_REG_SS, CS_AC_WRITE },
1249 { X86_PUSHCS16, X86_REG_CS, CS_AC_READ },
1250 { X86_PUSHCS32, X86_REG_CS, CS_AC_READ },
1251 { X86_PUSHDS16, X86_REG_DS, CS_AC_READ },
1252 { X86_PUSHDS32, X86_REG_DS, CS_AC_READ },
1253 { X86_PUSHES16, X86_REG_ES, CS_AC_READ },
1254 { X86_PUSHES32, X86_REG_ES, CS_AC_READ },
1255 { X86_PUSHFS16, X86_REG_FS, CS_AC_READ },
1256 { X86_PUSHFS32, X86_REG_FS, CS_AC_READ },
1257 { X86_PUSHFS64, X86_REG_FS, CS_AC_READ },
1258 { X86_PUSHGS16, X86_REG_GS, CS_AC_READ },
1259 { X86_PUSHGS32, X86_REG_GS, CS_AC_READ },
1260 { X86_PUSHGS64, X86_REG_GS, CS_AC_READ },
1261 { X86_PUSHSS16, X86_REG_SS, CS_AC_READ },
1262 { X86_PUSHSS32, X86_REG_SS, CS_AC_READ },
1263 { X86_RCL16rCL, X86_REG_CL, CS_AC_READ },
1264 { X86_RCL32rCL, X86_REG_CL, CS_AC_READ },
1265 { X86_RCL64rCL, X86_REG_CL, CS_AC_READ },
1266 { X86_RCL8rCL, X86_REG_CL, CS_AC_READ },
1267 { X86_RCR16rCL, X86_REG_CL, CS_AC_READ },
1268 { X86_RCR32rCL, X86_REG_CL, CS_AC_READ },
1269 { X86_RCR64rCL, X86_REG_CL, CS_AC_READ },
1270 { X86_RCR8rCL, X86_REG_CL, CS_AC_READ },
1271 { X86_ROL16rCL, X86_REG_CL, CS_AC_READ },
1272 { X86_ROL32rCL, X86_REG_CL, CS_AC_READ },
1273 { X86_ROL64rCL, X86_REG_CL, CS_AC_READ },
1274 { X86_ROL8rCL, X86_REG_CL, CS_AC_READ },
1275 { X86_ROR16rCL, X86_REG_CL, CS_AC_READ },
1276 { X86_ROR32rCL, X86_REG_CL, CS_AC_READ },
1277 { X86_ROR64rCL, X86_REG_CL, CS_AC_READ },
1278 { X86_ROR8rCL, X86_REG_CL, CS_AC_READ },
1279 { X86_SAL16rCL, X86_REG_CL, CS_AC_READ },
1280 { X86_SAL32rCL, X86_REG_CL, CS_AC_READ },
1281 { X86_SAL64rCL, X86_REG_CL, CS_AC_READ },
1282 { X86_SAL8rCL, X86_REG_CL, CS_AC_READ },
1283 { X86_SAR16rCL, X86_REG_CL, CS_AC_READ },
1284 { X86_SAR32rCL, X86_REG_CL, CS_AC_READ },
1285 { X86_SAR64rCL, X86_REG_CL, CS_AC_READ },
1286 { X86_SAR8rCL, X86_REG_CL, CS_AC_READ },
1287 { X86_SHL16rCL, X86_REG_CL, CS_AC_READ },
1288 { X86_SHL32rCL, X86_REG_CL, CS_AC_READ },
1289 { X86_SHL64rCL, X86_REG_CL, CS_AC_READ },
1290 { X86_SHL8rCL, X86_REG_CL, CS_AC_READ },
1291 { X86_SHLD16mrCL, X86_REG_CL, CS_AC_READ },
1292 { X86_SHLD16rrCL, X86_REG_CL, CS_AC_READ },
1293 { X86_SHLD32mrCL, X86_REG_CL, CS_AC_READ },
1294 { X86_SHLD32rrCL, X86_REG_CL, CS_AC_READ },
1295 { X86_SHLD64mrCL, X86_REG_CL, CS_AC_READ },
1296 { X86_SHLD64rrCL, X86_REG_CL, CS_AC_READ },
1297 { X86_SHR16rCL, X86_REG_CL, CS_AC_READ },
1298 { X86_SHR32rCL, X86_REG_CL, CS_AC_READ },
1299 { X86_SHR64rCL, X86_REG_CL, CS_AC_READ },
1300 { X86_SHR8rCL, X86_REG_CL, CS_AC_READ },
1301 { X86_SHRD16mrCL, X86_REG_CL, CS_AC_READ },
1302 { X86_SHRD16rrCL, X86_REG_CL, CS_AC_READ },
1303 { X86_SHRD32mrCL, X86_REG_CL, CS_AC_READ },
1304 { X86_SHRD32rrCL, X86_REG_CL, CS_AC_READ },
1305 { X86_SHRD64mrCL, X86_REG_CL, CS_AC_READ },
1306 { X86_SHRD64rrCL, X86_REG_CL, CS_AC_READ },
1307 { X86_XCHG16ar, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1308 { X86_XCHG32ar, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1309 { X86_XCHG64ar, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1310 };
1311
1312 static const struct insn_reg insn_regs_att_extra[] = {
1313 // dummy entry, to avoid empty array
1314 { 0, 0 },
1315 #ifndef CAPSTONE_X86_REDUCE
1316 { X86_ADD_FrST0, X86_REG_ST0, CS_AC_READ },
1317 { X86_DIVR_FrST0, X86_REG_ST0, CS_AC_READ },
1318 { X86_DIV_FrST0, X86_REG_ST0, CS_AC_READ },
1319 { X86_FNSTSW16r, X86_REG_AX, CS_AC_READ },
1320 { X86_MUL_FrST0, X86_REG_ST0, CS_AC_READ },
1321 { X86_SKINIT, X86_REG_EAX, CS_AC_READ },
1322 { X86_SUBR_FrST0, X86_REG_ST0, CS_AC_READ },
1323 { X86_SUB_FrST0, X86_REG_ST0, CS_AC_READ },
1324 { X86_VMLOAD32, X86_REG_EAX, CS_AC_READ },
1325 { X86_VMLOAD64, X86_REG_RAX, CS_AC_READ },
1326 { X86_VMRUN32, X86_REG_EAX, CS_AC_READ },
1327 { X86_VMRUN64, X86_REG_RAX, CS_AC_READ },
1328 { X86_VMSAVE32, X86_REG_EAX, CS_AC_READ },
1329 { X86_VMSAVE64, X86_REG_RAX, CS_AC_READ },
1330 #endif
1331 };
1332
1333 static const struct insn_reg insn_regs_intel[] = {
1334 { X86_ADC16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1335 { X86_ADC32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1336 { X86_ADC64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1337 { X86_ADC8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1338 { X86_ADD16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1339 { X86_ADD32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1340 { X86_ADD64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1341 { X86_ADD8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1342 { X86_AND16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1343 { X86_AND32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1344 { X86_AND64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1345 { X86_AND8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1346 { X86_CMP16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1347 { X86_CMP32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1348 { X86_CMP64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1349 { X86_CMP8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1350 { X86_IN16ri, X86_REG_AX, CS_AC_WRITE },
1351 { X86_IN32ri, X86_REG_EAX, CS_AC_WRITE },
1352 { X86_IN8ri, X86_REG_AL, CS_AC_WRITE },
1353 { X86_LODSB, X86_REG_AL, CS_AC_WRITE },
1354 { X86_LODSL, X86_REG_EAX, CS_AC_WRITE },
1355 { X86_LODSQ, X86_REG_RAX, CS_AC_WRITE },
1356 { X86_LODSW, X86_REG_AX, CS_AC_WRITE },
1357 { X86_MOV16ao16, X86_REG_AX, CS_AC_WRITE }, // 16-bit A1 1020 // mov ax, word ptr [0x2010]
1358 { X86_MOV16ao32, X86_REG_AX, CS_AC_WRITE }, // 32-bit A1 10203040 // mov ax, word ptr [0x40302010]
1359 { X86_MOV16ao64, X86_REG_AX, CS_AC_WRITE }, // 64-bit 66 A1 1020304050607080 // movabs ax, word ptr [0x8070605040302010]
1360 { X86_MOV32ao16, X86_REG_EAX, CS_AC_WRITE }, // 32-bit 67 A1 1020 // mov eax, dword ptr [0x2010]
1361 { X86_MOV32ao32, X86_REG_EAX, CS_AC_WRITE }, // 32-bit A1 10203040 // mov eax, dword ptr [0x40302010]
1362 { X86_MOV32ao64, X86_REG_EAX, CS_AC_WRITE }, // 64-bit A1 1020304050607080 // movabs eax, dword ptr [0x8070605040302010]
1363 { X86_MOV64ao32, X86_REG_RAX, CS_AC_WRITE }, // 64-bit 48 8B04 10203040 // mov rax, qword ptr [0x40302010]
1364 { X86_MOV64ao64, X86_REG_RAX, CS_AC_WRITE }, // 64-bit 48 A1 1020304050607080 // movabs rax, qword ptr [0x8070605040302010]
1365 { X86_MOV8ao16, X86_REG_AL, CS_AC_WRITE }, // 16-bit A0 1020 // mov al, byte ptr [0x2010]
1366 { X86_MOV8ao32, X86_REG_AL, CS_AC_WRITE }, // 32-bit A0 10203040 // mov al, byte ptr [0x40302010]
1367 { X86_MOV8ao64, X86_REG_AL, CS_AC_WRITE }, // 64-bit 66 A0 1020304050607080 // movabs al, byte ptr [0x8070605040302010]
1368 { X86_OR16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1369 { X86_OR32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1370 { X86_OR64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1371 { X86_OR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1372 { X86_OUTSB, X86_REG_DX, CS_AC_WRITE },
1373 { X86_OUTSL, X86_REG_DX, CS_AC_WRITE },
1374 { X86_OUTSW, X86_REG_DX, CS_AC_WRITE },
1375 { X86_POPDS16, X86_REG_DS, CS_AC_WRITE },
1376 { X86_POPDS32, X86_REG_DS, CS_AC_WRITE },
1377 { X86_POPES16, X86_REG_ES, CS_AC_WRITE },
1378 { X86_POPES32, X86_REG_ES, CS_AC_WRITE },
1379 { X86_POPFS16, X86_REG_FS, CS_AC_WRITE },
1380 { X86_POPFS32, X86_REG_FS, CS_AC_WRITE },
1381 { X86_POPFS64, X86_REG_FS, CS_AC_WRITE },
1382 { X86_POPGS16, X86_REG_GS, CS_AC_WRITE },
1383 { X86_POPGS32, X86_REG_GS, CS_AC_WRITE },
1384 { X86_POPGS64, X86_REG_GS, CS_AC_WRITE },
1385 { X86_POPSS16, X86_REG_SS, CS_AC_WRITE },
1386 { X86_POPSS32, X86_REG_SS, CS_AC_WRITE },
1387 { X86_PUSHCS16, X86_REG_CS, CS_AC_READ },
1388 { X86_PUSHCS32, X86_REG_CS, CS_AC_READ },
1389 { X86_PUSHDS16, X86_REG_DS, CS_AC_READ },
1390 { X86_PUSHDS32, X86_REG_DS, CS_AC_READ },
1391 { X86_PUSHES16, X86_REG_ES, CS_AC_READ },
1392 { X86_PUSHES32, X86_REG_ES, CS_AC_READ },
1393 { X86_PUSHFS16, X86_REG_FS, CS_AC_READ },
1394 { X86_PUSHFS32, X86_REG_FS, CS_AC_READ },
1395 { X86_PUSHFS64, X86_REG_FS, CS_AC_READ },
1396 { X86_PUSHGS16, X86_REG_GS, CS_AC_READ },
1397 { X86_PUSHGS32, X86_REG_GS, CS_AC_READ },
1398 { X86_PUSHGS64, X86_REG_GS, CS_AC_READ },
1399 { X86_PUSHSS16, X86_REG_SS, CS_AC_READ },
1400 { X86_PUSHSS32, X86_REG_SS, CS_AC_READ },
1401 { X86_SBB16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1402 { X86_SBB32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1403 { X86_SBB64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1404 { X86_SBB8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1405 { X86_SCASB, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1406 { X86_SCASL, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1407 { X86_SCASQ, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1408 { X86_SCASW, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1409 { X86_SUB16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1410 { X86_SUB32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1411 { X86_SUB64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1412 { X86_SUB8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1413 { X86_TEST16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1414 { X86_TEST32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1415 { X86_TEST64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1416 { X86_TEST8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1417 { X86_XOR16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ },
1418 { X86_XOR32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ },
1419 { X86_XOR64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ },
1420 { X86_XOR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ },
1421 };
1422
1423 static const struct insn_reg insn_regs_intel_extra[] = {
1424 // dummy entry, to avoid empty array
1425 { 0, 0, 0 },
1426 #ifndef CAPSTONE_X86_REDUCE
1427 { X86_CMOVBE_F, X86_REG_ST0, CS_AC_WRITE },
1428 { X86_CMOVB_F, X86_REG_ST0, CS_AC_WRITE },
1429 { X86_CMOVE_F, X86_REG_ST0, CS_AC_WRITE },
1430 { X86_CMOVNBE_F, X86_REG_ST0, CS_AC_WRITE },
1431 { X86_CMOVNB_F, X86_REG_ST0, CS_AC_WRITE },
1432 { X86_CMOVNE_F, X86_REG_ST0, CS_AC_WRITE },
1433 { X86_CMOVNP_F, X86_REG_ST0, CS_AC_WRITE },
1434 { X86_CMOVP_F, X86_REG_ST0, CS_AC_WRITE },
1435 // { X86_COMP_FST0r, X86_REG_ST0, CS_AC_WRITE },
1436 // { X86_COM_FST0r, X86_REG_ST0, CS_AC_WRITE },
1437 { X86_FNSTSW16r, X86_REG_AX, CS_AC_WRITE },
1438 { X86_SKINIT, X86_REG_EAX, CS_AC_WRITE },
1439 { X86_VMLOAD32, X86_REG_EAX, CS_AC_WRITE },
1440 { X86_VMLOAD64, X86_REG_RAX, CS_AC_WRITE },
1441 { X86_VMRUN32, X86_REG_EAX, CS_AC_WRITE },
1442 { X86_VMRUN64, X86_REG_RAX, CS_AC_WRITE },
1443 { X86_VMSAVE32, X86_REG_EAX, CS_AC_READ },
1444 { X86_VMSAVE64, X86_REG_RAX, CS_AC_READ },
1445 { X86_XCH_F, X86_REG_ST0, CS_AC_WRITE },
1446 #endif
1447 };
1448
1449 static const struct insn_reg2 insn_regs_intel2[] = {
1450 { X86_IN16rr, X86_REG_AX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
1451 { X86_IN32rr, X86_REG_EAX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
1452 { X86_IN8rr, X86_REG_AL, X86_REG_DX, CS_AC_WRITE, CS_AC_READ },
1453 { X86_INVLPGA32, X86_REG_EAX, X86_REG_ECX, CS_AC_READ, CS_AC_READ },
1454 { X86_INVLPGA64, X86_REG_RAX, X86_REG_ECX, CS_AC_READ, CS_AC_READ },
1455 { X86_OUT16rr, X86_REG_DX, X86_REG_AX, CS_AC_READ, CS_AC_READ },
1456 { X86_OUT32rr, X86_REG_DX, X86_REG_EAX, CS_AC_READ, CS_AC_READ },
1457 { X86_OUT8rr, X86_REG_DX, X86_REG_AL, CS_AC_READ, CS_AC_READ },
1458 };
1459
binary_search1(const struct insn_reg * insns,unsigned int max,unsigned int id)1460 static int binary_search1(const struct insn_reg *insns, unsigned int max, unsigned int id)
1461 {
1462 unsigned int first, last, mid;
1463
1464 first = 0;
1465 last = max -1;
1466
1467 if (insns[0].insn > id || insns[last].insn < id) {
1468 // not found
1469 return -1;
1470 }
1471
1472 while (first <= last) {
1473 mid = (first + last) / 2;
1474 if (insns[mid].insn < id) {
1475 first = mid + 1;
1476 } else if (insns[mid].insn == id) {
1477 return mid;
1478 } else {
1479 if (mid == 0)
1480 break;
1481 last = mid - 1;
1482 }
1483 }
1484
1485 // not found
1486 return -1;
1487 }
1488
binary_search2(const struct insn_reg2 * insns,unsigned int max,unsigned int id)1489 static int binary_search2(const struct insn_reg2 *insns, unsigned int max, unsigned int id)
1490 {
1491 unsigned int first, last, mid;
1492
1493 first = 0;
1494 last = max -1;
1495
1496 if (insns[0].insn > id || insns[last].insn < id) {
1497 // not found
1498 return -1;
1499 }
1500
1501 while (first <= last) {
1502 mid = (first + last) / 2;
1503 if (insns[mid].insn < id) {
1504 first = mid + 1;
1505 } else if (insns[mid].insn == id) {
1506 return mid;
1507 } else {
1508 if (mid == 0)
1509 break;
1510 last = mid - 1;
1511 }
1512 }
1513
1514 // not found
1515 return -1;
1516 }
1517
1518 // return register of given instruction id
1519 // return 0 if not found
1520 // this is to handle instructions embedding accumulate registers into AsmStrs[]
X86_insn_reg_intel(unsigned int id,enum cs_ac_type * access)1521 x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access)
1522 {
1523 int i;
1524
1525 i = binary_search1(insn_regs_intel, ARR_SIZE(insn_regs_intel), id);
1526 if (i != -1) {
1527 if (access) {
1528 *access = insn_regs_intel[i].access;
1529 }
1530 return insn_regs_intel[i].reg;
1531 }
1532
1533 i = binary_search1(insn_regs_intel_extra, ARR_SIZE(insn_regs_intel_extra), id);
1534 if (i != -1) {
1535 if (access) {
1536 *access = insn_regs_intel_extra[i].access;
1537 }
1538 return insn_regs_intel_extra[i].reg;
1539 }
1540
1541 // not found
1542 return 0;
1543 }
1544
X86_insn_reg_intel2(unsigned int id,x86_reg * reg1,enum cs_ac_type * access1,x86_reg * reg2,enum cs_ac_type * access2)1545 bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2)
1546 {
1547 int i = binary_search2(insn_regs_intel2, ARR_SIZE(insn_regs_intel2), id);
1548 if (i != -1) {
1549 *reg1 = insn_regs_intel2[i].reg1;
1550 *reg2 = insn_regs_intel2[i].reg2;
1551 if (access1)
1552 *access1 = insn_regs_intel2[i].access1;
1553 if (access2)
1554 *access2 = insn_regs_intel2[i].access2;
1555 return true;
1556 }
1557
1558 // not found
1559 return false;
1560 }
1561
X86_insn_reg_att(unsigned int id,enum cs_ac_type * access)1562 x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access)
1563 {
1564 int i;
1565
1566 i = binary_search1(insn_regs_att, ARR_SIZE(insn_regs_att), id);
1567 if (i != -1) {
1568 if (access)
1569 *access = insn_regs_att[i].access;
1570 return insn_regs_att[i].reg;
1571 }
1572
1573 i = binary_search1(insn_regs_att_extra, ARR_SIZE(insn_regs_att_extra), id);
1574 if (i != -1) {
1575 if (access)
1576 *access = insn_regs_att_extra[i].access;
1577 return insn_regs_att_extra[i].reg;
1578 }
1579
1580 // not found
1581 return 0;
1582 }
1583
1584 // ATT just reuses Intel data, but with the order of registers reversed
X86_insn_reg_att2(unsigned int id,x86_reg * reg1,enum cs_ac_type * access1,x86_reg * reg2,enum cs_ac_type * access2)1585 bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2)
1586 {
1587 int i = binary_search2(insn_regs_intel2, ARR_SIZE(insn_regs_intel2), id);
1588 if (i != -1) {
1589 *reg1 = insn_regs_intel2[i].reg2;
1590 *reg2 = insn_regs_intel2[i].reg1;
1591 if (access1)
1592 *access1 = insn_regs_intel2[i].access2;
1593 if (access2)
1594 *access2 = insn_regs_intel2[i].access1;
1595 return true;
1596 }
1597
1598 // not found
1599 return false;
1600 }
1601
1602 // given MCInst's id, find out if this insn is valid for REPNE prefix
valid_repne(cs_struct * h,unsigned int opcode)1603 static bool valid_repne(cs_struct *h, unsigned int opcode)
1604 {
1605 unsigned int id;
1606 unsigned int i = find_insn(opcode);
1607 if (i != -1) {
1608 id = insns[i].mapid;
1609 switch(id) {
1610 default:
1611 return false;
1612
1613 case X86_INS_CMPSB:
1614 case X86_INS_CMPSS:
1615 case X86_INS_CMPSW:
1616 case X86_INS_CMPSQ:
1617
1618 case X86_INS_SCASB:
1619 case X86_INS_SCASW:
1620 case X86_INS_SCASQ:
1621
1622 case X86_INS_MOVSB:
1623 case X86_INS_MOVSS:
1624 case X86_INS_MOVSW:
1625 case X86_INS_MOVSQ:
1626
1627 case X86_INS_LODSB:
1628 case X86_INS_LODSW:
1629 case X86_INS_LODSD:
1630 case X86_INS_LODSQ:
1631
1632 case X86_INS_STOSB:
1633 case X86_INS_STOSW:
1634 case X86_INS_STOSD:
1635 case X86_INS_STOSQ:
1636
1637 case X86_INS_INSB:
1638 case X86_INS_INSW:
1639 case X86_INS_INSD:
1640
1641 case X86_INS_OUTSB:
1642 case X86_INS_OUTSW:
1643 case X86_INS_OUTSD:
1644
1645 return true;
1646
1647 case X86_INS_MOVSD:
1648 if (opcode == X86_MOVSW) // REP MOVSB
1649 return true;
1650 return false;
1651
1652 case X86_INS_CMPSD:
1653 if (opcode == X86_CMPSL) // REP CMPSD
1654 return true;
1655 return false;
1656
1657 case X86_INS_SCASD:
1658 if (opcode == X86_SCASL) // REP SCASD
1659 return true;
1660 return false;
1661 }
1662 }
1663
1664 // not found
1665 return false;
1666 }
1667
1668 // given MCInst's id, find out if this insn is valid for BND prefix
1669 // BND prefix is valid for CALL/JMP/RET
1670 #ifndef CAPSTONE_DIET
valid_bnd(cs_struct * h,unsigned int opcode)1671 static bool valid_bnd(cs_struct *h, unsigned int opcode)
1672 {
1673 unsigned int id;
1674 unsigned int i = find_insn(opcode);
1675 if (i != -1) {
1676 id = insns[i].mapid;
1677 switch(id) {
1678 default:
1679 return false;
1680
1681 case X86_INS_JAE:
1682 case X86_INS_JA:
1683 case X86_INS_JBE:
1684 case X86_INS_JB:
1685 case X86_INS_JCXZ:
1686 case X86_INS_JECXZ:
1687 case X86_INS_JE:
1688 case X86_INS_JGE:
1689 case X86_INS_JG:
1690 case X86_INS_JLE:
1691 case X86_INS_JL:
1692 case X86_INS_JMP:
1693 case X86_INS_JNE:
1694 case X86_INS_JNO:
1695 case X86_INS_JNP:
1696 case X86_INS_JNS:
1697 case X86_INS_JO:
1698 case X86_INS_JP:
1699 case X86_INS_JRCXZ:
1700 case X86_INS_JS:
1701
1702 case X86_INS_CALL:
1703 case X86_INS_RET:
1704 case X86_INS_RETF:
1705 case X86_INS_RETFQ:
1706 return true;
1707 }
1708 }
1709
1710 // not found
1711 return false;
1712 }
1713 #endif
1714
1715 // return true if the opcode is XCHG [mem]
xchg_mem(unsigned int opcode)1716 static bool xchg_mem(unsigned int opcode)
1717 {
1718 switch(opcode) {
1719 default:
1720 return false;
1721 case X86_XCHG8rm:
1722 case X86_XCHG16rm:
1723 case X86_XCHG32rm:
1724 case X86_XCHG64rm:
1725 return true;
1726 }
1727 }
1728
1729 // given MCInst's id, find out if this insn is valid for REP prefix
valid_rep(cs_struct * h,unsigned int opcode)1730 static bool valid_rep(cs_struct *h, unsigned int opcode)
1731 {
1732 unsigned int id;
1733 unsigned int i = find_insn(opcode);
1734 if (i != -1) {
1735 id = insns[i].mapid;
1736 switch(id) {
1737 default:
1738 return false;
1739
1740 case X86_INS_MOVSB:
1741 case X86_INS_MOVSW:
1742 case X86_INS_MOVSQ:
1743
1744 case X86_INS_LODSB:
1745 case X86_INS_LODSW:
1746 case X86_INS_LODSQ:
1747
1748 case X86_INS_STOSB:
1749 case X86_INS_STOSW:
1750 case X86_INS_STOSQ:
1751
1752 case X86_INS_INSB:
1753 case X86_INS_INSW:
1754 case X86_INS_INSD:
1755
1756 case X86_INS_OUTSB:
1757 case X86_INS_OUTSW:
1758 case X86_INS_OUTSD:
1759 return true;
1760
1761 // following are some confused instructions, which have the same
1762 // mnemonics in 128bit media instructions. Intel is horribly crazy!
1763 case X86_INS_MOVSD:
1764 if (opcode == X86_MOVSL) // REP MOVSD
1765 return true;
1766 return false;
1767
1768 case X86_INS_LODSD:
1769 if (opcode == X86_LODSL) // REP LODSD
1770 return true;
1771 return false;
1772
1773 case X86_INS_STOSD:
1774 if (opcode == X86_STOSL) // REP STOSD
1775 return true;
1776 return false;
1777 }
1778 }
1779
1780 // not found
1781 return false;
1782 }
1783
1784 // given MCInst's id, find out if this insn is valid for REPE prefix
valid_repe(cs_struct * h,unsigned int opcode)1785 static bool valid_repe(cs_struct *h, unsigned int opcode)
1786 {
1787 unsigned int id;
1788 unsigned int i = find_insn(opcode);
1789 if (i != -1) {
1790 id = insns[i].mapid;
1791 switch(id) {
1792 default:
1793 return false;
1794
1795 case X86_INS_CMPSB:
1796 case X86_INS_CMPSW:
1797 case X86_INS_CMPSQ:
1798
1799 case X86_INS_SCASB:
1800 case X86_INS_SCASW:
1801 case X86_INS_SCASQ:
1802 return true;
1803
1804 // following are some confused instructions, which have the same
1805 // mnemonics in 128bit media instructions. Intel is horribly crazy!
1806 case X86_INS_CMPSD:
1807 if (opcode == X86_CMPSL) // REP CMPSD
1808 return true;
1809 return false;
1810
1811 case X86_INS_SCASD:
1812 if (opcode == X86_SCASL) // REP SCASD
1813 return true;
1814 return false;
1815 }
1816 }
1817
1818 // not found
1819 return false;
1820 }
1821
1822 #ifndef CAPSTONE_DIET
1823 // add *CX register to regs_read[] & regs_write[]
add_cx(MCInst * MI)1824 static void add_cx(MCInst *MI)
1825 {
1826 if (MI->csh->detail) {
1827 x86_reg cx;
1828
1829 if (MI->csh->mode & CS_MODE_16)
1830 cx = X86_REG_CX;
1831 else if (MI->csh->mode & CS_MODE_32)
1832 cx = X86_REG_ECX;
1833 else // 64-bit
1834 cx = X86_REG_RCX;
1835
1836 MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = cx;
1837 MI->flat_insn->detail->regs_read_count++;
1838
1839 MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = cx;
1840 MI->flat_insn->detail->regs_write_count++;
1841 }
1842 }
1843 #endif
1844
1845 // return true if we patch the mnemonic
X86_lockrep(MCInst * MI,SStream * O)1846 bool X86_lockrep(MCInst *MI, SStream *O)
1847 {
1848 unsigned int opcode;
1849 bool res = false;
1850
1851 switch(MI->x86_prefix[0]) {
1852 default:
1853 break;
1854 case 0xf0:
1855 #ifndef CAPSTONE_DIET
1856 if (MI->xAcquireRelease == 0xf2)
1857 SStream_concat(O, "xacquire|lock|");
1858 else if (MI->xAcquireRelease == 0xf3)
1859 SStream_concat(O, "xrelease|lock|");
1860 else
1861 SStream_concat(O, "lock|");
1862 #endif
1863 break;
1864 case 0xf2: // repne
1865 opcode = MCInst_getOpcode(MI);
1866
1867 #ifndef CAPSTONE_DIET // only care about memonic in standard (non-diet) mode
1868 if (xchg_mem(opcode) && MI->xAcquireRelease) {
1869 SStream_concat(O, "xacquire|");
1870 } else if (valid_repne(MI->csh, opcode)) {
1871 SStream_concat(O, "repne|");
1872 add_cx(MI);
1873 } else if (valid_bnd(MI->csh, opcode)) {
1874 SStream_concat(O, "bnd|");
1875 } else {
1876 // invalid prefix
1877 MI->x86_prefix[0] = 0;
1878
1879 // handle special cases
1880 #ifndef CAPSTONE_X86_REDUCE
1881 #if 0
1882 if (opcode == X86_MULPDrr) {
1883 MCInst_setOpcode(MI, X86_MULSDrr);
1884 SStream_concat(O, "mulsd\t");
1885 res = true;
1886 }
1887 #endif
1888 #endif
1889 }
1890 #else // diet mode -> only patch opcode in special cases
1891 if (!valid_repne(MI->csh, opcode)) {
1892 MI->x86_prefix[0] = 0;
1893 }
1894 #ifndef CAPSTONE_X86_REDUCE
1895 #if 0
1896 // handle special cases
1897 if (opcode == X86_MULPDrr) {
1898 MCInst_setOpcode(MI, X86_MULSDrr);
1899 }
1900 #endif
1901 #endif
1902 #endif
1903 break;
1904
1905 case 0xf3:
1906 opcode = MCInst_getOpcode(MI);
1907
1908 #ifndef CAPSTONE_DIET // only care about memonic in standard (non-diet) mode
1909 if (xchg_mem(opcode) && MI->xAcquireRelease) {
1910 SStream_concat(O, "xrelease|");
1911 } else if (valid_rep(MI->csh, opcode)) {
1912 SStream_concat(O, "rep|");
1913 add_cx(MI);
1914 } else if (valid_repe(MI->csh, opcode)) {
1915 SStream_concat(O, "repe|");
1916 add_cx(MI);
1917 } else {
1918 // invalid prefix
1919 MI->x86_prefix[0] = 0;
1920
1921 // handle special cases
1922 #ifndef CAPSTONE_X86_REDUCE
1923 #if 0
1924 // FIXME: remove this special case?
1925 if (opcode == X86_MULPDrr) {
1926 MCInst_setOpcode(MI, X86_MULSSrr);
1927 SStream_concat(O, "mulss\t");
1928 res = true;
1929 }
1930 #endif
1931 #endif
1932 }
1933 #else // diet mode -> only patch opcode in special cases
1934 if (!valid_rep(MI->csh, opcode) && !valid_repe(MI->csh, opcode)) {
1935 MI->x86_prefix[0] = 0;
1936 }
1937 #ifndef CAPSTONE_X86_REDUCE
1938 #if 0
1939 // handle special cases
1940 // FIXME: remove this special case?
1941 if (opcode == X86_MULPDrr) {
1942 MCInst_setOpcode(MI, X86_MULSSrr);
1943 }
1944 #endif
1945 #endif
1946 #endif
1947 break;
1948 }
1949
1950 // copy normalized prefix[] back to x86.prefix[]
1951 if (MI->csh->detail)
1952 memcpy(MI->flat_insn->detail->x86.prefix, MI->x86_prefix, ARR_SIZE(MI->x86_prefix));
1953
1954 return res;
1955 }
1956
op_addReg(MCInst * MI,int reg)1957 void op_addReg(MCInst *MI, int reg)
1958 {
1959 if (MI->csh->detail) {
1960 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
1961 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
1962 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
1963 MI->flat_insn->detail->x86.op_count++;
1964 }
1965
1966 if (MI->op1_size == 0)
1967 MI->op1_size = MI->csh->regsize_map[reg];
1968 }
1969
op_addImm(MCInst * MI,int v)1970 void op_addImm(MCInst *MI, int v)
1971 {
1972 if (MI->csh->detail) {
1973 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
1974 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = v;
1975 // if op_count > 0, then this operand's size is taken from the destination op
1976 if (MI->csh->syntax != CS_OPT_SYNTAX_ATT) {
1977 if (MI->flat_insn->detail->x86.op_count > 0)
1978 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size;
1979 else
1980 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
1981 } else
1982 MI->has_imm = true;
1983 MI->flat_insn->detail->x86.op_count++;
1984 }
1985
1986 if (MI->op1_size == 0)
1987 MI->op1_size = MI->imm_size;
1988 }
1989
op_addXopCC(MCInst * MI,int v)1990 void op_addXopCC(MCInst *MI, int v)
1991 {
1992 if (MI->csh->detail) {
1993 MI->flat_insn->detail->x86.xop_cc = v;
1994 }
1995 }
1996
op_addSseCC(MCInst * MI,int v)1997 void op_addSseCC(MCInst *MI, int v)
1998 {
1999 if (MI->csh->detail) {
2000 MI->flat_insn->detail->x86.sse_cc = v;
2001 }
2002 }
2003
op_addAvxCC(MCInst * MI,int v)2004 void op_addAvxCC(MCInst *MI, int v)
2005 {
2006 if (MI->csh->detail) {
2007 MI->flat_insn->detail->x86.avx_cc = v;
2008 }
2009 }
2010
op_addAvxRoundingMode(MCInst * MI,int v)2011 void op_addAvxRoundingMode(MCInst *MI, int v)
2012 {
2013 if (MI->csh->detail) {
2014 MI->flat_insn->detail->x86.avx_rm = v;
2015 }
2016 }
2017
2018 // below functions supply details to X86GenAsmWriter*.inc
op_addAvxZeroOpmask(MCInst * MI)2019 void op_addAvxZeroOpmask(MCInst *MI)
2020 {
2021 if (MI->csh->detail) {
2022 // link with the previous operand
2023 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_zero_opmask = true;
2024 }
2025 }
2026
op_addAvxSae(MCInst * MI)2027 void op_addAvxSae(MCInst *MI)
2028 {
2029 if (MI->csh->detail) {
2030 MI->flat_insn->detail->x86.avx_sae = true;
2031 }
2032 }
2033
op_addAvxBroadcast(MCInst * MI,x86_avx_bcast v)2034 void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v)
2035 {
2036 if (MI->csh->detail) {
2037 // link with the previous operand
2038 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_bcast = v;
2039 }
2040 }
2041
2042 #ifndef CAPSTONE_DIET
2043 // map instruction to its characteristics
2044 typedef struct insn_op {
2045 uint64_t flags; // how this instruction update EFLAGS(arithmetic instrcutions) of FPU FLAGS(for FPU instructions)
2046 uint8_t access[6];
2047 } insn_op;
2048
2049 static const insn_op insn_ops[] = {
2050 #ifdef CAPSTONE_X86_REDUCE
2051 #include "X86MappingInsnOp_reduce.inc"
2052 #else
2053 #include "X86MappingInsnOp.inc"
2054 #endif
2055 };
2056
2057 // given internal insn id, return operand access info
X86_get_op_access(cs_struct * h,unsigned int id,uint64_t * eflags)2058 const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags)
2059 {
2060 unsigned int i = find_insn(id);
2061 if (i != -1) {
2062 *eflags = insn_ops[i].flags;
2063 return insn_ops[i].access;
2064 }
2065
2066 return NULL;
2067 }
2068
X86_reg_access(const cs_insn * insn,cs_regs regs_read,uint8_t * regs_read_count,cs_regs regs_write,uint8_t * regs_write_count)2069 void X86_reg_access(const cs_insn *insn,
2070 cs_regs regs_read, uint8_t *regs_read_count,
2071 cs_regs regs_write, uint8_t *regs_write_count)
2072 {
2073 uint8_t i;
2074 uint8_t read_count, write_count;
2075 cs_x86 *x86 = &(insn->detail->x86);
2076
2077 read_count = insn->detail->regs_read_count;
2078 write_count = insn->detail->regs_write_count;
2079
2080 // implicit registers
2081 memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
2082 memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
2083
2084 // explicit registers
2085 for (i = 0; i < x86->op_count; i++) {
2086 cs_x86_op *op = &(x86->operands[i]);
2087 switch((int)op->type) {
2088 case X86_OP_REG:
2089 if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
2090 regs_read[read_count] = op->reg;
2091 read_count++;
2092 }
2093 if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
2094 regs_write[write_count] = op->reg;
2095 write_count++;
2096 }
2097 break;
2098 case X86_OP_MEM:
2099 // registers appeared in memory references always being read
2100 if ((op->mem.segment != X86_REG_INVALID)) {
2101 regs_read[read_count] = op->mem.segment;
2102 read_count++;
2103 }
2104 if ((op->mem.base != X86_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
2105 regs_read[read_count] = op->mem.base;
2106 read_count++;
2107 }
2108 if ((op->mem.index != X86_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
2109 regs_read[read_count] = op->mem.index;
2110 read_count++;
2111 }
2112 default:
2113 break;
2114 }
2115 }
2116
2117 *regs_read_count = read_count;
2118 *regs_write_count = write_count;
2119 }
2120 #endif
2121
2122 // map immediate size to instruction id
2123 // this array is sorted for binary searching
2124 static const struct size_id {
2125 uint8_t enc_size;
2126 uint8_t size;
2127 uint16_t id;
2128 } x86_imm_size[] = {
2129 #include "X86ImmSize.inc"
2130 };
2131
2132 // given the instruction name, return the size of its immediate operand (or 0)
X86_immediate_size(unsigned int id,uint8_t * enc_size)2133 uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size)
2134 {
2135 // binary searching since the IDs are sorted in order
2136 unsigned int left, right, m;
2137
2138 right = ARR_SIZE(x86_imm_size) - 1;
2139
2140 if (id < x86_imm_size[0].id || id > x86_imm_size[right].id)
2141 // not found
2142 return 0;
2143
2144 left = 0;
2145
2146 while (left <= right) {
2147 m = (left + right) / 2;
2148 if (id == x86_imm_size[m].id) {
2149 if (enc_size != NULL)
2150 *enc_size = x86_imm_size[m].enc_size;
2151
2152 return x86_imm_size[m].size;
2153 }
2154
2155 if (id > x86_imm_size[m].id)
2156 left = m + 1;
2157 else {
2158 if (m == 0)
2159 break;
2160 right = m - 1;
2161 }
2162 }
2163
2164 // not found
2165 return 0;
2166 }
2167
2168 #define GET_REGINFO_ENUM
2169 #include "X86GenRegisterInfo.inc"
2170
2171 // map internal register id to public register id
2172 static const struct register_map {
2173 unsigned short id;
2174 unsigned short pub_id;
2175 } reg_map [] = {
2176 // first dummy map
2177 { 0, 0 },
2178 #include "X86MappingReg.inc"
2179 };
2180
2181 // return 0 on invalid input, or public register ID otherwise
2182 // NOTE: reg_map is sorted in order of internal register
X86_register_map(unsigned short id)2183 unsigned short X86_register_map(unsigned short id)
2184 {
2185 if (id < ARR_SIZE(reg_map))
2186 return reg_map[id].pub_id;
2187
2188 return 0;
2189 }
2190
2191 #endif
2192