1 /** 2 Per an email message from Russ Nelson <nelson@crynwr.com> on 3 18 March 2008 this file is now licensed under GPL Version 2. 4 5 From: Russ Nelson <nelson@crynwr.com> 6 Date: Tue, 18 Mar 2008 12:42:00 -0400 7 Subject: Re: [Etherboot-developers] cs89x0 driver in etherboot 8 -- quote from email 9 As copyright holder, if I say it doesn't conflict with the GPL, 10 then it doesn't conflict with the GPL. 11 12 However, there's no point in causing people's brains to overheat, 13 so yes, I grant permission for the code to be relicensed under the 14 GPLv2. Please make sure that this change in licensing makes its 15 way upstream. -russ 16 -- quote from email 17 **/ 18 19 FILE_LICENCE ( GPL2_ONLY ); 20 21 /* Copyright, 1988-1992, Russell Nelson, Crynwr Software 22 23 This program is free software; you can redistribute it and/or modify 24 it under the terms of the GNU General Public License as published by 25 the Free Software Foundation, version 1. 26 27 This program is distributed in the hope that it will be useful, 28 but WITHOUT ANY WARRANTY; without even the implied warranty of 29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 GNU General Public License for more details. 31 32 You should have received a copy of the GNU General Public License 33 along with this program; if not, write to the Free Software 34 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 35 02110-1301, USA. */ 36 37 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ 38 /* offset 2h -> Model/Product Number */ 39 /* offset 3h -> Chip Revision Number */ 40 41 #define PP_ISAIOB 0x0020 /* IO base address */ 42 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ 43 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ 44 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ 45 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ 46 #define PP_ISASOF 0x0026 /* ISA DMA offset */ 47 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ 48 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ 49 #define PP_CS8900_ISAMemB 0x002C /* Memory base */ 50 #define PP_CS8920_ISAMemB 0x0348 /* */ 51 52 #define PP_ISABootBase 0x0030 /* Boot Prom base */ 53 #define PP_ISABootMask 0x0034 /* Boot Prom Mask */ 54 55 /* EEPROM data and command registers */ 56 #define PP_EECMD 0x0040 /* NVR Interface Command register */ 57 #define PP_EEData 0x0042 /* NVR Interface Data Register */ 58 #define PP_DebugReg 0x0044 /* Debug Register */ 59 60 #define PP_RxCFG 0x0102 /* Rx Bus config */ 61 #define PP_RxCTL 0x0104 /* Receive Control Register */ 62 #define PP_TxCFG 0x0106 /* Transmit Config Register */ 63 #define PP_TxCMD 0x0108 /* Transmit Command Register */ 64 #define PP_BufCFG 0x010A /* Bus configuration Register */ 65 #define PP_LineCTL 0x0112 /* Line Config Register */ 66 #define PP_SelfCTL 0x0114 /* Self Command Register */ 67 #define PP_BusCTL 0x0116 /* ISA bus control Register */ 68 #define PP_TestCTL 0x0118 /* Test Register */ 69 #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ 70 71 #define PP_ISQ 0x0120 /* Interrupt Status */ 72 #define PP_RxEvent 0x0124 /* Rx Event Register */ 73 #define PP_TxEvent 0x0128 /* Tx Event Register */ 74 #define PP_BufEvent 0x012C /* Bus Event Register */ 75 #define PP_RxMiss 0x0130 /* Receive Miss Count */ 76 #define PP_TxCol 0x0132 /* Transmit Collision Count */ 77 #define PP_LineST 0x0134 /* Line State Register */ 78 #define PP_SelfST 0x0136 /* Self State register */ 79 #define PP_BusST 0x0138 /* Bus Status */ 80 #define PP_TDR 0x013C /* Time Domain Reflectometry */ 81 #define PP_AutoNegST 0x013E /* Auto Neg Status */ 82 #define PP_TxCommand 0x0144 /* Tx Command */ 83 #define PP_TxLength 0x0146 /* Tx Length */ 84 #define PP_LAF 0x0150 /* Hash Table */ 85 #define PP_IA 0x0158 /* Physical Address Register */ 86 87 #define PP_RxStatus 0x0400 /* Receive start of frame */ 88 #define PP_RxLength 0x0402 /* Receive Length of frame */ 89 #define PP_RxFrame 0x0404 /* Receive frame pointer */ 90 #define PP_TxFrame 0x0A00 /* Transmit frame pointer */ 91 92 /* Primary I/O Base Address. If no I/O base is supplied by the user, then this */ 93 /* can be used as the default I/O base to access the PacketPage Area. */ 94 #define DEFAULTIOBASE 0x0300 95 #define FIRST_IO 0x020C /* First I/O port to check */ 96 #define LAST_IO 0x037C /* Last I/O port to check (+10h) */ 97 #define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ 98 #define ADD_SIG 0x3000 /* Expected ID signature */ 99 100 #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ 101 102 #ifdef IBMEIPKT 103 #define EISA_ID_SIG 0x4D24 /* IBM */ 104 #define PART_NO_SIG 0x1010 /* IBM */ 105 #define MONGOOSE_BIT 0x0000 /* IBM */ 106 #else 107 #define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */ 108 #define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */ 109 #define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */ 110 #endif 111 112 #define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ 113 114 /* Mask to find out the types of registers */ 115 #define REG_TYPE_MASK 0x001F 116 117 /* Eeprom Commands */ 118 #define ERSE_WR_ENBL 0x00F0 119 #define ERSE_WR_DISABLE 0x0000 120 121 /* Defines Control/Config register quintuplet numbers */ 122 #define RX_BUF_CFG 0x0003 123 #define RX_CONTROL 0x0005 124 #define TX_CFG 0x0007 125 #define TX_COMMAND 0x0009 126 #define BUF_CFG 0x000B 127 #define LINE_CONTROL 0x0013 128 #define SELF_CONTROL 0x0015 129 #define BUS_CONTROL 0x0017 130 #define TEST_CONTROL 0x0019 131 132 /* Defines Status/Count registers quintuplet numbers */ 133 #define RX_EVENT 0x0004 134 #define TX_EVENT 0x0008 135 #define BUF_EVENT 0x000C 136 #define RX_MISS_COUNT 0x0010 137 #define TX_COL_COUNT 0x0012 138 #define LINE_STATUS 0x0014 139 #define SELF_STATUS 0x0016 140 #define BUS_STATUS 0x0018 141 #define TDR 0x001C 142 143 /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */ 144 #define SKIP_1 0x0040 145 #define RX_STREAM_ENBL 0x0080 146 #define RX_OK_ENBL 0x0100 147 #define RX_DMA_ONLY 0x0200 148 #define AUTO_RX_DMA 0x0400 149 #define BUFFER_CRC 0x0800 150 #define RX_CRC_ERROR_ENBL 0x1000 151 #define RX_RUNT_ENBL 0x2000 152 #define RX_EXTRA_DATA_ENBL 0x4000 153 154 /* PP_RxCTL - Receive Control bit definition - Read/write */ 155 #define RX_IA_HASH_ACCEPT 0x0040 156 #define RX_PROM_ACCEPT 0x0080 157 #define RX_OK_ACCEPT 0x0100 158 #define RX_MULTCAST_ACCEPT 0x0200 159 #define RX_IA_ACCEPT 0x0400 160 #define RX_BROADCAST_ACCEPT 0x0800 161 #define RX_BAD_CRC_ACCEPT 0x1000 162 #define RX_RUNT_ACCEPT 0x2000 163 #define RX_EXTRA_DATA_ACCEPT 0x4000 164 #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT) 165 /* Default receive mode - individually addressed, broadcast, and error free */ 166 #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) 167 168 /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */ 169 #define TX_LOST_CRS_ENBL 0x0040 170 #define TX_SQE_ERROR_ENBL 0x0080 171 #define TX_OK_ENBL 0x0100 172 #define TX_LATE_COL_ENBL 0x0200 173 #define TX_JBR_ENBL 0x0400 174 #define TX_ANY_COL_ENBL 0x0800 175 #define TX_16_COL_ENBL 0x8000 176 177 /* PP_TxCMD - Transmit Command bit definition - Read-only */ 178 #define TX_START_4_BYTES 0x0000 179 #define TX_START_64_BYTES 0x0040 180 #define TX_START_128_BYTES 0x0080 181 #define TX_START_ALL_BYTES 0x00C0 182 #define TX_FORCE 0x0100 183 #define TX_ONE_COL 0x0200 184 #define TX_TWO_PART_DEFF_DISABLE 0x0400 185 #define TX_NO_CRC 0x1000 186 #define TX_RUNT 0x2000 187 188 /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */ 189 #define GENERATE_SW_INTERRUPT 0x0040 190 #define RX_DMA_ENBL 0x0080 191 #define READY_FOR_TX_ENBL 0x0100 192 #define TX_UNDERRUN_ENBL 0x0200 193 #define RX_MISS_ENBL 0x0400 194 #define RX_128_BYTE_ENBL 0x0800 195 #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 196 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 197 #define RX_DEST_MATCH_ENBL 0x8000 198 199 /* PP_LineCTL - Line Control bit definition - Read/write */ 200 #define SERIAL_RX_ON 0x0040 201 #define SERIAL_TX_ON 0x0080 202 #define AUI_ONLY 0x0100 203 #define AUTO_AUI_10BASET 0x0200 204 #define MODIFIED_BACKOFF 0x0800 205 #define NO_AUTO_POLARITY 0x1000 206 #define TWO_PART_DEFDIS 0x2000 207 #define LOW_RX_SQUELCH 0x4000 208 209 /* PP_SelfCTL - Software Self Control bit definition - Read/write */ 210 #define POWER_ON_RESET 0x0040 211 #define SW_STOP 0x0100 212 #define SLEEP_ON 0x0200 213 #define AUTO_WAKEUP 0x0400 214 #define HCB0_ENBL 0x1000 215 #define HCB1_ENBL 0x2000 216 #define HCB0 0x4000 217 #define HCB1 0x8000 218 219 /* PP_BusCTL - ISA Bus Control bit definition - Read/write */ 220 #define RESET_RX_DMA 0x0040 221 #define MEMORY_ON 0x0400 222 #define DMA_BURST_MODE 0x0800 223 #define IO_CHANNEL_READY_ON 0x1000 224 #define RX_DMA_SIZE_64K 0x2000 225 #define ENABLE_IRQ 0x8000 226 227 /* PP_TestCTL - Test Control bit definition - Read/write */ 228 #define LINK_OFF 0x0080 229 #define ENDEC_LOOPBACK 0x0200 230 #define AUI_LOOPBACK 0x0400 231 #define BACKOFF_OFF 0x0800 232 #define FAST_TEST 0x8000 233 234 /* PP_RxEvent - Receive Event Bit definition - Read-only */ 235 #define RX_IA_HASHED 0x0040 236 #define RX_DRIBBLE 0x0080 237 #define RX_OK 0x0100 238 #define RX_HASHED 0x0200 239 #define RX_IA 0x0400 240 #define RX_BROADCAST 0x0800 241 #define RX_CRC_ERROR 0x1000 242 #define RX_RUNT 0x2000 243 #define RX_EXTRA_DATA 0x4000 244 245 #define HASH_INDEX_MASK 0x0FC00 246 247 /* PP_TxEvent - Transmit Event Bit definition - Read-only */ 248 #define TX_LOST_CRS 0x0040 249 #define TX_SQE_ERROR 0x0080 250 #define TX_OK 0x0100 251 #define TX_LATE_COL 0x0200 252 #define TX_JBR 0x0400 253 #define TX_16_COL 0x8000 254 #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS) 255 #define TX_COL_COUNT_MASK 0x7800 256 257 /* PP_BufEvent - Buffer Event Bit definition - Read-only */ 258 #define SW_INTERRUPT 0x0040 259 #define RX_DMA 0x0080 260 #define READY_FOR_TX 0x0100 261 #define TX_UNDERRUN 0x0200 262 #define RX_MISS 0x0400 263 #define RX_128_BYTE 0x0800 264 #define TX_COL_OVRFLW 0x1000 265 #define RX_MISS_OVRFLW 0x2000 266 #define RX_DEST_MATCH 0x8000 267 268 /* PP_LineST - Ethernet Line Status bit definition - Read-only */ 269 #define LINK_OK 0x0080 270 #define AUI_ON 0x0100 271 #define TENBASET_ON 0x0200 272 #define POLARITY_OK 0x1000 273 #define CRS_OK 0x4000 274 275 /* PP_SelfST - Chip Software Status bit definition */ 276 #define ACTIVE_33V 0x0040 277 #define INIT_DONE 0x0080 278 #define SI_BUSY 0x0100 279 #define EEPROM_PRESENT 0x0200 280 #define EEPROM_OK 0x0400 281 #define EL_PRESENT 0x0800 282 #define EE_SIZE_64 0x1000 283 284 /* PP_BusST - ISA Bus Status bit definition */ 285 #define TX_BID_ERROR 0x0080 286 #define READY_FOR_TX_NOW 0x0100 287 288 /* PP_AutoNegCTL - Auto Negotiation Control bit definition */ 289 #define RE_NEG_NOW 0x0040 290 #define ALLOW_FDX 0x0080 291 #define AUTO_NEG_ENABLE 0x0100 292 #define NLP_ENABLE 0x0200 293 #define FORCE_FDX 0x8000 294 #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE) 295 #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW) 296 297 /* PP_AutoNegST - Auto Negotiation Status bit definition */ 298 #define AUTO_NEG_BUSY 0x0080 299 #define FLP_LINK 0x0100 300 #define FLP_LINK_GOOD 0x0800 301 #define LINK_FAULT 0x1000 302 #define HDX_ACTIVE 0x4000 303 #define FDX_ACTIVE 0x8000 304 305 /* The following block defines the ISQ event types */ 306 #define ISQ_RECEIVER_EVENT 0x04 307 #define ISQ_TRANSMITTER_EVENT 0x08 308 #define ISQ_BUFFER_EVENT 0x0c 309 #define ISQ_RX_MISS_EVENT 0x10 310 #define ISQ_TX_COL_EVENT 0x12 311 312 #define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ 313 #define ISQ_HIST 16 /* small history buffer */ 314 #define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ 315 316 #define TXRXBUFSIZE 0x0600 317 #define RXDMABUFSIZE 0x8000 318 #define RXDMASIZE 0x4000 319 #define TXRX_LENGTH_MASK 0x07FF 320 321 /* rx options bits */ 322 #define RCV_WITH_RXON 1 /* Set SerRx ON */ 323 #define RCV_COUNTS 2 /* Use Framecnt1 */ 324 #define RCV_PONG 4 /* Pong respondent */ 325 #define RCV_DONG 8 /* Dong operation */ 326 #define RCV_POLLING 0x10 /* Poll RxEvent */ 327 #define RCV_ISQ 0x20 /* Use ISQ, int */ 328 #define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ 329 #define RCV_DMA 0x200 /* Set RxDMA only */ 330 #define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ 331 #define RCV_FIXED_DATA 0x800 /* Every frame same */ 332 #define RCV_IO 0x1000 /* Use ISA IO only */ 333 #define RCV_MEMORY 0x2000 /* Use ISA Memory */ 334 335 #define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ 336 #define PKT_START PP_TxFrame /* Start of packet RAM */ 337 338 #define RX_FRAME_PORT 0x0000 339 #define TX_FRAME_PORT RX_FRAME_PORT 340 #define TX_CMD_PORT 0x0004 341 #define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */ 342 #define TX_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */ 343 #define TX_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */ 344 #define TX_LEN_PORT 0x0006 345 #define ISQ_PORT 0x0008 346 #define ADD_PORT 0x000A 347 #define DATA_PORT 0x000C 348 349 #define EEPROM_WRITE_EN 0x00F0 350 #define EEPROM_WRITE_DIS 0x0000 351 #define EEPROM_WRITE_CMD 0x0100 352 #define EEPROM_READ_CMD 0x0200 353 354 /* Receive Header */ 355 /* Description of header of each packet in receive area of memory */ 356 #define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ 357 #define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ 358 #define RBUF_LEN_LOW 2 /* Length of received data - low byte */ 359 #define RBUF_LEN_HI 3 /* Length of received data - high byte */ 360 #define RBUF_HEAD_LEN 4 /* Length of this header */ 361 362 #define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ 363 #define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ 364 365 /* for bios scan */ 366 /* */ 367 #ifdef CSDEBUG 368 /* use these values for debugging bios scan */ 369 #define BIOS_START_SEG 0x00000 370 #define BIOS_OFFSET_INC 0x0010 371 #else 372 #define BIOS_START_SEG 0x0c000 373 #define BIOS_OFFSET_INC 0x0200 374 #endif 375 376 #define BIOS_LAST_OFFSET 0x0fc00 377 378 /* Byte offsets into the EEPROM configuration buffer */ 379 #define ISA_CNF_OFFSET 0x6 380 #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */ 381 #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */ 382 383 /* the assumption here is that the bits in the eeprom are generally */ 384 /* in the same position as those in the autonegctl register. */ 385 /* Of course the IMM bit is not in that register so it must be */ 386 /* masked out */ 387 #define EE_FORCE_FDX 0x8000 388 #define EE_NLP_ENABLE 0x0200 389 #define EE_AUTO_NEG_ENABLE 0x0100 390 #define EE_ALLOW_FDX 0x0080 391 #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX) 392 393 #define IMM_BIT 0x0040 /* ignore missing media */ 394 395 #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) 396 #define A_CNF_10B_T 0x0001 397 #define A_CNF_AUI 0x0002 398 #define A_CNF_10B_2 0x0004 399 #define A_CNF_MEDIA_TYPE 0x0060 400 #define A_CNF_MEDIA_AUTO 0x0000 401 #define A_CNF_MEDIA_10B_T 0x0020 402 #define A_CNF_MEDIA_AUI 0x0040 403 #define A_CNF_MEDIA_10B_2 0x0060 404 #define A_CNF_DC_DC_POLARITY 0x0080 405 #define A_CNF_NO_AUTO_POLARITY 0x2000 406 #define A_CNF_LOW_RX_SQUELCH 0x4000 407 #define A_CNF_EXTND_10B_2 0x8000 408 409 #define PACKET_PAGE_OFFSET 0x8 410 411 /* Bit definitions for the ISA configuration word from the EEPROM */ 412 #define INT_NO_MASK 0x000F 413 #define DMA_NO_MASK 0x0070 414 #define ISA_DMA_SIZE 0x0200 415 #define ISA_AUTO_RxDMA 0x0400 416 #define ISA_RxDMA 0x0800 417 #define DMA_BURST 0x1000 418 #define STREAM_TRANSFER 0x2000 419 #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) 420 421 /* DMA controller registers */ 422 #define DMA_BASE 0x00 /* DMA controller base */ 423 #define DMA_BASE_2 0x0C0 /* DMA controller base */ 424 425 #define DMA_STAT 0x0D0 /* DMA controller status register */ 426 #define DMA_MASK 0x0D4 /* DMA controller mask register */ 427 #define DMA_MODE 0x0D6 /* DMA controller mode register */ 428 #define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ 429 430 /* DMA data */ 431 #define DMA_DISABLE 0x04 /* Disable channel n */ 432 #define DMA_ENABLE 0x00 /* Enable channel n */ 433 /* Demand transfers, incr. address, auto init, writes, ch. n */ 434 #define DMA_RX_MODE 0x14 435 /* Demand transfers, incr. address, auto init, reads, ch. n */ 436 #define DMA_TX_MODE 0x18 437 438 #define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ 439 440 #define CS8900 0x0000 441 #define CS8920 0x4000 442 #define CS8920M 0x6000 443 #define REVISON_BITS 0x1F00 444 #define EEVER_NUMBER 0x12 445 #define CHKSUM_LEN 0x14 446 #define CHKSUM_VAL 0x0000 447 #define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ 448 #define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ 449 #define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ 450 #define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ 451 #define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ 452 453 #define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ 454 455 #define PNP_ADD_PORT 0x0279 456 #define PNP_WRITE_PORT 0x0A79 457 458 #define GET_PNP_ISA_STRUCT 0x40 459 #define PNP_ISA_STRUCT_LEN 0x06 460 #define PNP_CSN_CNT_OFF 0x01 461 #define PNP_RD_PORT_OFF 0x02 462 #define PNP_FUNCTION_OK 0x00 463 #define PNP_WAKE 0x03 464 #define PNP_RSRC_DATA 0x04 465 #define PNP_RSRC_READY 0x01 466 #define PNP_STATUS 0x05 467 #define PNP_ACTIVATE 0x30 468 #define PNP_CNF_IO_H 0x60 469 #define PNP_CNF_IO_L 0x61 470 #define PNP_CNF_INT 0x70 471 #define PNP_CNF_DMA 0x74 472 #define PNP_CNF_MEM 0x48 473 474 /* 475 * Local variables: 476 * c-basic-offset: 8 477 * End: 478 */ 479 480