1 2 #ifndef __EEPRO100_H_ 3 #define __EEPRO100_H_ 4 5 FILE_LICENCE ( GPL2_OR_LATER ); 6 7 #define CONGENB 0 /* Enable congestion control in the DP83840. */ 8 #define TX_FIFO 8 /* Tx FIFO threshold in 4 byte units, 0-15 */ 9 #define RX_FIFO 8 /* Rx FIFO threshold, default 32 bytes. */ 10 #define TX_DMA_COUNT 0 /* Tx DMA burst length, 0-127, default 0. */ 11 #define RX_DMA_COUNT 0 /* Rx DMA length, 0 means no preemption. */ 12 #define CU_CMD_TIMEOUT 1000 /* CU command accept timeout in microseconds */ 13 #define LINK_CHECK_PERIOD 1000 /* # of poll() calls between link checks */ 14 15 #define RFD_PACKET_LEN 1518 16 #define RFD_IOB_LEN 1536 17 #define RFD_HEADER_LEN 16 18 #define CB_ALIGN 2 /* Alignment of command blocks */ 19 20 #define RFD_COUNT 4 21 #define TCB_COUNT 4 22 #define RX_RING_BYTES ( RFD_COUNT * sizeof ( struct ifec_rfd ) ) 23 #define TX_RING_BYTES ( TCB_COUNT * sizeof ( struct ifec_tcb ) ) 24 25 /* some EEPROM addresses */ 26 #define EEPROM_ADDR_MAC_0 0 27 #define EEPROM_ADDR_MDIO_REGISTER 6 28 29 /* Control / Status Register byte offsets - SDM Table 11 */ 30 enum CSROffsets { 31 SCBStatus=0, SCBCmd=2, SCBPointer = 4, 32 CSRPort=8, CSRFlash=12, CSREeprom = 14, 33 CSRCtrlMDI=16, CSREarlyRx=20 34 }; 35 36 /* System Control Block Command Word - SDM Table 12 */ 37 enum SCBCmdBits { 38 /* SCB Interrupt Masks - SDM Table 14 */ 39 SCBMaskCmdDone=0x8000, SCBMaskRxDone=0x4000, SCBMaskCmdIdle=0x2000, 40 SCBMaskRxSuspend=0x1000, SCBMaskEarlyRx=0x0800, SCBMaskFlowCtl=0x0400, 41 SCBTriggerIntr=0x0200, SCBMaskAll=0x0100, 42 /* SCB Control Commands - SDM Table 14-16 */ 43 CUStart=0x0010, CUResume=0x0020, CUStatsAddr=0x0040, 44 CUShowStats=0x0050, CUCmdBase=0x0060, CUDumpStats=0x0070, 45 RUStart=0x0001, RUResume=0x0002, RUAbort=0x0004, 46 RUAddrLoad=0x0006, RUResumeNoResources=0x0007 47 }; 48 49 enum SCBPortCmds { 50 PortReset=0, PortSelfTest=1, PortPartialReset=2, PortDump=3 51 }; 52 53 /* Action Commands - SDM Table 14,37 */ 54 enum ActionCommands { 55 CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, 56 CmdMulticastList = 3, CmdTx = 4, CmdTDR = 5, 57 CmdDump = 6, CmdDiagnose = 7, 58 /* And some extra flags: */ 59 CmdEndOfList = 0x8000, 60 CmdSuspend = 0x4000, CmdIntr = 0x2000, CmdTxFlex = 0x0008 61 }; 62 63 enum TCBBits { 64 TCB_C=0x8000, TCB_OK=0x2000, TCB_U=0x1000 65 }; 66 67 enum RFDBits { 68 /* Status Word Bits */ 69 RFDRxCol=0x0001, RFDIAMatch=0x0002, RFDNoMatch=0x0004, 70 RFDReserved3=0x0008, RFDRxErr=0x0010, RFDEthType=0x0020, 71 RFDReserved6=0x0040, RFDShort=0x0080, RFDDMAOverrun=0x0100, 72 RFDNoBufs=0x0200, RFDCRCAlign=0x0400, RFDCRCError=0x0800, 73 RFDReserved12=0x1000, RFD_OK=0x2000, RFDComplete=0x8000, 74 /* Command Word Bits */ 75 //RFD_SF=0x0008, RFDSuspend=0x4000, RFDEndOfList=0x8000, 76 /* Other */ 77 RFDMaskCount=0x3FFF 78 }; 79 80 enum phy_chips { 81 NonSuchPhy=0, I82553AB, I82553C, 82 I82503, DP83840, S80C240, 83 S80C24, PhyUndefined, DP83840A=10 84 }; 85 86 /* Serial EEPROM section. 87 A "bit" grungy, but we work our way through bit-by-bit :->. */ 88 /* EEPROM_Ctrl bits. */ 89 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ 90 #define EE_CS 0x02 /* EEPROM chip select. */ 91 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 92 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 93 #define EE_ENB ( 0x4800 | EE_CS ) 94 95 /* Elements of the dump_statistics block. This block must be lword aligned. */ 96 struct ifec_stats { 97 u32 98 tx_good_frames, tx_coll16_errs, tx_late_colls, 99 tx_underruns, tx_lost_carrier, tx_deferred, 100 tx_one_colls, tx_multi_colls, tx_total_colls, 101 rx_good_frames, rx_crc_errs, rx_align_errs, 102 rx_resource_errs, rx_overrun_errs, rx_colls_errs, 103 rx_runt_errs, done_marker; 104 }; 105 106 struct ifec_tcb { /* A Transmit Command Block & TBD. Must be */ 107 volatile s16 status; /* word (even address) aligned */ 108 u16 command; 109 u32 link; /* PHYSICAL next ifec_tcb, doesn't change */ 110 u32 tbda_addr; /* TBD Array, points to TBD below */ 111 s32 count; /* # of TBD, Tx start thresh., etc. */ 112 /* The following constitutes a Transmit Buffer Descriptor (TBD). 113 * TBDs must be aligned on an even address (word-aligned). */ 114 u32 tbd_addr0; /* PHYSICAL ptr to Tx data */ 115 s32 tbd_size0; /* Length of Tx data */ 116 /* Driver-specific data; not part of TCB format. */ 117 struct io_buffer *iob; /* Exists from tx() to completion poll() */ 118 struct ifec_tcb *next; /* VIRTUAL next ifec_tcb, doesn't change */ 119 }; 120 121 struct ifec_rfd { /* A Receive Frame Descriptor. Must be aligned */ 122 volatile s16 status; /* on a physical word (even address) */ 123 s16 command; 124 u32 link; /* PHYSICAL next ifec_rfd, doesn't change */ 125 u32 rx_buf_addr; /* Unused. Flex rx mode is not documented */ 126 u16 count; /* and may be impossible */ 127 u16 size; 128 char packet[RFD_PACKET_LEN]; 129 }; 130 131 struct ifec_ias { /* Individual Address Setup command block. */ 132 volatile s16 status; /* Must be word (even address) aligned. */ 133 u16 command; 134 u32 link; /* PHYSICAL next command block to process */ 135 u8 ia[6]; 136 }; 137 138 struct ifec_cfg { /* The configure command format. */ 139 volatile s16 status; 140 u16 command; 141 u32 link; /* PHYSICAL next command block to process */ 142 u8 byte[22]; /* 22 configuration bytes */ 143 }; 144 145 struct ifec_private { 146 unsigned long ioaddr; 147 struct ifec_stats stats; 148 unsigned short mdio_register; 149 150 struct ifec_tcb *tcbs; 151 struct ifec_rfd *rfds[RFD_COUNT]; 152 struct ifec_tcb *tcb_head, *tcb_tail; 153 struct io_buffer *tx_iobs[TCB_COUNT]; 154 struct io_buffer *rx_iobs[RFD_COUNT]; 155 int cur_rx; 156 int tx_curr; 157 int tx_tail; 158 int tx_cnt; 159 /* 160 * The configured flag indicates if a Config command was last issued. 161 * The following attempt to issue a command (in ifec_tx_wake) will 162 * use a START rather than RESUME SCB command. It seems the card won't 163 * RESUME after a configure command. 164 */ 165 int configured; 166 struct spi_bit_basher spi; 167 struct spi_device eeprom; 168 169 }; 170 171 /**************************** Function prototypes ****************************/ 172 173 /* PCI device API prototypes */ 174 static int ifec_pci_probe ( struct pci_device *pci ); 175 static void ifec_pci_remove ( struct pci_device *pci ); 176 177 /* Network device API prototypes */ 178 static void ifec_net_close ( struct net_device* ); 179 static void ifec_net_irq ( struct net_device*, int enable ); 180 static int ifec_net_open ( struct net_device* ); 181 static void ifec_net_poll ( struct net_device* ); 182 static int ifec_net_transmit ( struct net_device*, struct io_buffer *iobuf ); 183 184 /* Local function prototypes */ 185 static void ifec_init_eeprom ( struct net_device * ); 186 static int ifec_mdio_read ( struct net_device *, int phy, int location ); 187 static void ifec_mdio_setup ( struct net_device *, int options ); 188 static int ifec_mdio_write ( struct net_device *, int phy, int loc, int val); 189 static void ifec_reset ( struct net_device * ); 190 static void ifec_free ( struct net_device * ); 191 static void ifec_rfd_init ( struct ifec_rfd *rfd, s16 command, u32 link ); 192 static void ifec_rx_process ( struct net_device * ); 193 static void ifec_reprime_ru ( struct net_device * ); 194 static void ifec_check_ru_status ( struct net_device *, unsigned short ); 195 static int ifec_get_rx_desc ( struct net_device *, int ,int ,int ); 196 static void ifec_refill_rx_ring ( struct net_device * ); 197 static int ifec_rx_setup ( struct net_device * ); 198 static int ifec_scb_cmd ( struct net_device *, u32 ptr, u8 cmd ); 199 static int ifec_scb_cmd_wait ( struct net_device * ); 200 static void ifec_tx_process ( struct net_device * ); 201 static int ifec_tx_setup ( struct net_device * ); 202 static void ifec_tx_wake ( struct net_device * ); 203 204 #endif 205