1 #ifndef _INTELX_H
2 #define _INTELX_H
3
4 /** @file
5 *
6 * Intel 40 Gigabit Ethernet network card driver
7 *
8 */
9
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
12 #include <stdint.h>
13 #include <ipxe/if_ether.h>
14 #include <ipxe/pcimsix.h>
15
16 struct intelxl_nic;
17
18 /** BAR size */
19 #define INTELXL_BAR_SIZE 0x200000
20
21 /** Alignment
22 *
23 * No data structure requires greater than 256 byte alignment.
24 */
25 #define INTELXL_ALIGN 256
26
27 /******************************************************************************
28 *
29 * Admin queue
30 *
31 ******************************************************************************
32 */
33
34 /** PF Admin Command Queue register block */
35 #define INTELXL_ADMIN_CMD 0x080000
36
37 /** PF Admin Event Queue register block */
38 #define INTELXL_ADMIN_EVT 0x080080
39
40 /** Admin Queue Base Address Low Register (offset) */
41 #define INTELXL_ADMIN_BAL 0x000
42
43 /** Admin Queue Base Address High Register (offset) */
44 #define INTELXL_ADMIN_BAH 0x100
45
46 /** Admin Queue Length Register (offset) */
47 #define INTELXL_ADMIN_LEN 0x200
48 #define INTELXL_ADMIN_LEN_LEN(x) ( (x) << 0 ) /**< Queue length */
49 #define INTELXL_ADMIN_LEN_ENABLE 0x80000000UL /**< Queue enable */
50
51 /** Admin Queue Head Register (offset) */
52 #define INTELXL_ADMIN_HEAD 0x300
53
54 /** Admin Queue Tail Register (offset) */
55 #define INTELXL_ADMIN_TAIL 0x400
56
57 /** Admin queue register offsets
58 *
59 * The physical and virtual function register maps have no discernible
60 * relationship.
61 */
62 struct intelxl_admin_offsets {
63 /** Base Address Low Register offset */
64 unsigned int bal;
65 /** Base Address High Register offset */
66 unsigned int bah;
67 /** Length Register offset */
68 unsigned int len;
69 /** Head Register offset */
70 unsigned int head;
71 /** Tail Register offset */
72 unsigned int tail;
73 };
74
75 /** Admin queue data buffer command parameters */
76 struct intelxl_admin_buffer_params {
77 /** Reserved */
78 uint8_t reserved[8];
79 /** Buffer address high */
80 uint32_t high;
81 /** Buffer address low */
82 uint32_t low;
83 } __attribute__ (( packed ));
84
85 /** Admin queue Get Version command */
86 #define INTELXL_ADMIN_VERSION 0x0001
87
88 /** Admin queue version number */
89 struct intelxl_admin_version {
90 /** Major version number */
91 uint16_t major;
92 /** Minor version number */
93 uint16_t minor;
94 } __attribute__ (( packed ));
95
96 /** Admin queue Get Version command parameters */
97 struct intelxl_admin_version_params {
98 /** ROM version */
99 uint32_t rom;
100 /** Firmware build ID */
101 uint32_t build;
102 /** Firmware version */
103 struct intelxl_admin_version firmware;
104 /** API version */
105 struct intelxl_admin_version api;
106 } __attribute__ (( packed ));
107
108 /** Admin queue Driver Version command */
109 #define INTELXL_ADMIN_DRIVER 0x0002
110
111 /** Admin queue Driver Version command parameters */
112 struct intelxl_admin_driver_params {
113 /** Driver version */
114 uint8_t major;
115 /** Minor version */
116 uint8_t minor;
117 /** Build version */
118 uint8_t build;
119 /** Sub-build version */
120 uint8_t sub;
121 /** Reserved */
122 uint8_t reserved[4];
123 /** Data buffer address */
124 uint64_t address;
125 } __attribute__ (( packed ));
126
127 /** Admin queue Driver Version data buffer */
128 struct intelxl_admin_driver_buffer {
129 /** Driver name */
130 char name[32];
131 } __attribute__ (( packed ));
132
133 /** Admin queue Shutdown command */
134 #define INTELXL_ADMIN_SHUTDOWN 0x0003
135
136 /** Admin queue Shutdown command parameters */
137 struct intelxl_admin_shutdown_params {
138 /** Driver unloading */
139 uint8_t unloading;
140 /** Reserved */
141 uint8_t reserved[15];
142 } __attribute__ (( packed ));
143
144 /** Driver is unloading */
145 #define INTELXL_ADMIN_SHUTDOWN_UNLOADING 0x01
146
147 /** Admin queue Clear PXE Mode command */
148 #define INTELXL_ADMIN_CLEAR_PXE 0x0110
149
150 /** Admin queue Clear PXE Mode command parameters */
151 struct intelxl_admin_clear_pxe_params {
152 /** Magic value */
153 uint8_t magic;
154 /** Reserved */
155 uint8_t reserved[15];
156 } __attribute__ (( packed ));
157
158 /** Clear PXE Mode magic value */
159 #define INTELXL_ADMIN_CLEAR_PXE_MAGIC 0x02
160
161 /** Admin queue Get Switch Configuration command */
162 #define INTELXL_ADMIN_SWITCH 0x0200
163
164 /** Switching element configuration */
165 struct intelxl_admin_switch_config {
166 /** Switching element type */
167 uint8_t type;
168 /** Revision */
169 uint8_t revision;
170 /** Switching element ID */
171 uint16_t seid;
172 /** Uplink switching element ID */
173 uint16_t uplink;
174 /** Downlink switching element ID */
175 uint16_t downlink;
176 /** Reserved */
177 uint8_t reserved_b[3];
178 /** Connection type */
179 uint8_t connection;
180 /** Reserved */
181 uint8_t reserved_c[2];
182 /** Element specific information */
183 uint16_t info;
184 } __attribute__ (( packed ));
185
186 /** Virtual Station Inferface element type */
187 #define INTELXL_ADMIN_SWITCH_TYPE_VSI 19
188
189 /** Admin queue Get Switch Configuration command parameters */
190 struct intelxl_admin_switch_params {
191 /** Starting switching element identifier */
192 uint16_t next;
193 /** Reserved */
194 uint8_t reserved[6];
195 /** Data buffer address */
196 uint64_t address;
197 } __attribute__ (( packed ));
198
199 /** Admin queue Get Switch Configuration data buffer */
200 struct intelxl_admin_switch_buffer {
201 /** Number of switching elements reported */
202 uint16_t count;
203 /** Total number of switching elements */
204 uint16_t total;
205 /** Reserved */
206 uint8_t reserved_a[12];
207 /** Switch configuration */
208 struct intelxl_admin_switch_config cfg;
209 } __attribute__ (( packed ));
210
211 /** Admin queue Get VSI Parameters command */
212 #define INTELXL_ADMIN_VSI 0x0212
213
214 /** Admin queue Get VSI Parameters command parameters */
215 struct intelxl_admin_vsi_params {
216 /** VSI switching element ID */
217 uint16_t vsi;
218 /** Reserved */
219 uint8_t reserved[6];
220 /** Data buffer address */
221 uint64_t address;
222 } __attribute__ (( packed ));
223
224 /** Admin queue Get VSI Parameters data buffer */
225 struct intelxl_admin_vsi_buffer {
226 /** Reserved */
227 uint8_t reserved_a[30];
228 /** Queue numbers */
229 uint16_t queue[16];
230 /** Reserved */
231 uint8_t reserved_b[34];
232 /** Queue set handles for each traffic class */
233 uint16_t qset[8];
234 /** Reserved */
235 uint8_t reserved_c[16];
236 } __attribute__ (( packed ));
237
238 /** Admin queue Set VSI Promiscuous Modes command */
239 #define INTELXL_ADMIN_PROMISC 0x0254
240
241 /** Admin queue Set VSI Promiscuous Modes command parameters */
242 struct intelxl_admin_promisc_params {
243 /** Flags */
244 uint16_t flags;
245 /** Valid flags */
246 uint16_t valid;
247 /** VSI switching element ID */
248 uint16_t vsi;
249 /** Reserved */
250 uint8_t reserved[10];
251 } __attribute__ (( packed ));
252
253 /** Promiscuous unicast mode */
254 #define INTELXL_ADMIN_PROMISC_FL_UNICAST 0x0001
255
256 /** Promiscuous multicast mode */
257 #define INTELXL_ADMIN_PROMISC_FL_MULTICAST 0x0002
258
259 /** Promiscuous broadcast mode */
260 #define INTELXL_ADMIN_PROMISC_FL_BROADCAST 0x0004
261
262 /** Promiscuous VLAN mode */
263 #define INTELXL_ADMIN_PROMISC_FL_VLAN 0x0010
264
265 /** Admin queue Restart Autonegotiation command */
266 #define INTELXL_ADMIN_AUTONEG 0x0605
267
268 /** Admin queue Restart Autonegotiation command parameters */
269 struct intelxl_admin_autoneg_params {
270 /** Flags */
271 uint8_t flags;
272 /** Reserved */
273 uint8_t reserved[15];
274 } __attribute__ (( packed ));
275
276 /** Restart autonegotiation */
277 #define INTELXL_ADMIN_AUTONEG_FL_RESTART 0x02
278
279 /** Enable link */
280 #define INTELXL_ADMIN_AUTONEG_FL_ENABLE 0x04
281
282 /** Admin queue Get Link Status command */
283 #define INTELXL_ADMIN_LINK 0x0607
284
285 /** Admin queue Get Link Status command parameters */
286 struct intelxl_admin_link_params {
287 /** Link status notification */
288 uint8_t notify;
289 /** Reserved */
290 uint8_t reserved_a;
291 /** PHY type */
292 uint8_t phy;
293 /** Link speed */
294 uint8_t speed;
295 /** Link status */
296 uint8_t status;
297 /** Reserved */
298 uint8_t reserved_b[11];
299 } __attribute__ (( packed ));
300
301 /** Notify driver of link status changes */
302 #define INTELXL_ADMIN_LINK_NOTIFY 0x03
303
304 /** Link is up */
305 #define INTELXL_ADMIN_LINK_UP 0x01
306
307 /** Admin queue Send Message to PF command */
308 #define INTELXL_ADMIN_SEND_TO_PF 0x0801
309
310 /** Admin queue Send Message to VF command */
311 #define INTELXL_ADMIN_SEND_TO_VF 0x0802
312
313 /** Admin Queue VF Reset opcode */
314 #define INTELXL_ADMIN_VF_RESET 0x00000002
315
316 /** Admin Queue VF Get Resources opcode */
317 #define INTELXL_ADMIN_VF_GET_RESOURCES 0x00000003
318
319 /** Admin Queue VF Get Resources data buffer */
320 struct intelxl_admin_vf_get_resources_buffer {
321 /** Reserved */
322 uint8_t reserved_a[20];
323 /** VSI switching element ID */
324 uint16_t vsi;
325 /** Reserved */
326 uint8_t reserved_b[8];
327 /** MAC address */
328 uint8_t mac[ETH_ALEN];
329 } __attribute__ (( packed ));
330
331 /** Admin Queue VF Status Change Event opcode */
332 #define INTELXL_ADMIN_VF_STATUS 0x00000011
333
334 /** Link status change event type */
335 #define INTELXL_ADMIN_VF_STATUS_LINK 0x00000001
336
337 /** Link status change event data */
338 struct intelxl_admin_vf_status_link {
339 /** Link speed */
340 uint32_t speed;
341 /** Link status */
342 uint8_t status;
343 /** Reserved */
344 uint8_t reserved[3];
345 } __attribute__ (( packed ));
346
347 /** Admin Queue VF Status Change Event data buffer */
348 struct intelxl_admin_vf_status_buffer {
349 /** Event type */
350 uint32_t event;
351 /** Event data */
352 union {
353 /** Link change event data */
354 struct intelxl_admin_vf_status_link link;
355 } data;
356 /** Reserved */
357 uint8_t reserved[4];
358 } __attribute__ (( packed ));
359
360 /** Admin Queue VF Configure Queues opcode */
361 #define INTELXL_ADMIN_VF_CONFIGURE 0x00000006
362
363 /** Admin Queue VF Configure Queues data buffer */
364 struct intelxl_admin_vf_configure_buffer {
365 /** VSI switching element ID */
366 uint16_t vsi;
367 /** Number of queue pairs */
368 uint16_t count;
369 /** Reserved */
370 uint8_t reserved_a[4];
371 /** Transmit queue */
372 struct {
373 /** VSI switching element ID */
374 uint16_t vsi;
375 /** Queue ID */
376 uint16_t id;
377 /** Queue count */
378 uint16_t count;
379 /** Reserved */
380 uint8_t reserved_a[2];
381 /** Base address */
382 uint64_t base;
383 /** Reserved */
384 uint8_t reserved_b[8];
385 } __attribute__ (( packed )) tx;
386 /** Receive queue */
387 struct {
388 /** VSI switching element ID */
389 uint16_t vsi;
390 /** Queue ID */
391 uint16_t id;
392 /** Queue count */
393 uint32_t count;
394 /** Reserved */
395 uint8_t reserved_a[4];
396 /** Data buffer length */
397 uint32_t len;
398 /** Maximum frame size */
399 uint32_t mfs;
400 /** Reserved */
401 uint8_t reserved_b[4];
402 /** Base address */
403 uint64_t base;
404 /** Reserved */
405 uint8_t reserved_c[8];
406 } __attribute__ (( packed )) rx;
407 /** Reserved
408 *
409 * This field exists only due to a bug in the PF driver's
410 * message validation logic, which causes it to miscalculate
411 * the expected message length.
412 */
413 uint8_t reserved_b[64];
414 } __attribute__ (( packed ));
415
416 /** Admin Queue VF IRQ Map opcode */
417 #define INTELXL_ADMIN_VF_IRQ_MAP 0x00000007
418
419 /** Admin Queue VF IRQ Map data buffer */
420 struct intelxl_admin_vf_irq_map_buffer {
421 /** Number of interrupt vectors */
422 uint16_t count;
423 /** VSI switching element ID */
424 uint16_t vsi;
425 /** Interrupt vector ID */
426 uint16_t vec;
427 /** Receive queue bitmap */
428 uint16_t rxmap;
429 /** Transmit queue bitmap */
430 uint16_t txmap;
431 /** Receive interrupt throttling index */
432 uint16_t rxitr;
433 /** Transmit interrupt throttling index */
434 uint16_t txitr;
435 /** Reserved
436 *
437 * This field exists only due to a bug in the PF driver's
438 * message validation logic, which causes it to miscalculate
439 * the expected message length.
440 */
441 uint8_t reserved[12];
442 } __attribute__ (( packed ));
443
444 /** Admin Queue VF Enable Queues opcode */
445 #define INTELXL_ADMIN_VF_ENABLE 0x00000008
446
447 /** Admin Queue VF Disable Queues opcode */
448 #define INTELXL_ADMIN_VF_DISABLE 0x00000009
449
450 /** Admin Queue VF Enable/Disable Queues data buffer */
451 struct intelxl_admin_vf_queues_buffer {
452 /** VSI switching element ID */
453 uint16_t vsi;
454 /** Reserved */
455 uint8_t reserved[2];
456 /** Receive queue bitmask */
457 uint32_t rx;
458 /** Transmit queue bitmask */
459 uint32_t tx;
460 } __attribute__ (( packed ));
461
462 /** Admin Queue VF Configure Promiscuous Mode opcode */
463 #define INTELXL_ADMIN_VF_PROMISC 0x0000000e
464
465 /** Admin Queue VF Configure Promiscuous Mode data buffer */
466 struct intelxl_admin_vf_promisc_buffer {
467 /** VSI switching element ID */
468 uint16_t vsi;
469 /** Flags */
470 uint16_t flags;
471 } __attribute__ (( packed ));
472
473 /** Admin queue command parameters */
474 union intelxl_admin_params {
475 /** Additional data buffer command parameters */
476 struct intelxl_admin_buffer_params buffer;
477 /** Get Version command parameters */
478 struct intelxl_admin_version_params version;
479 /** Driver Version command parameters */
480 struct intelxl_admin_driver_params driver;
481 /** Shutdown command parameters */
482 struct intelxl_admin_shutdown_params shutdown;
483 /** Clear PXE Mode command parameters */
484 struct intelxl_admin_clear_pxe_params pxe;
485 /** Get Switch Configuration command parameters */
486 struct intelxl_admin_switch_params sw;
487 /** Get VSI Parameters command parameters */
488 struct intelxl_admin_vsi_params vsi;
489 /** Set VSI Promiscuous Modes command parameters */
490 struct intelxl_admin_promisc_params promisc;
491 /** Restart Autonegotiation command parameters */
492 struct intelxl_admin_autoneg_params autoneg;
493 /** Get Link Status command parameters */
494 struct intelxl_admin_link_params link;
495 } __attribute__ (( packed ));
496
497 /** Admin queue data buffer */
498 union intelxl_admin_buffer {
499 /** Driver Version data buffer */
500 struct intelxl_admin_driver_buffer driver;
501 /** Get Switch Configuration data buffer */
502 struct intelxl_admin_switch_buffer sw;
503 /** Get VSI Parameters data buffer */
504 struct intelxl_admin_vsi_buffer vsi;
505 /** VF Get Resources data buffer */
506 struct intelxl_admin_vf_get_resources_buffer res;
507 /** VF Status Change Event data buffer */
508 struct intelxl_admin_vf_status_buffer stat;
509 /** VF Configure Queues data buffer */
510 struct intelxl_admin_vf_configure_buffer cfg;
511 /** VF Enable/Disable Queues data buffer */
512 struct intelxl_admin_vf_queues_buffer queues;
513 /** VF Configure Promiscuous Mode data buffer */
514 struct intelxl_admin_vf_promisc_buffer promisc;
515 /*** VF IRQ Map data buffer */
516 struct intelxl_admin_vf_irq_map_buffer irq;
517 /** Alignment padding */
518 uint8_t pad[INTELXL_ALIGN];
519 } __attribute__ (( packed ));
520
521 /** Admin queue descriptor */
522 struct intelxl_admin_descriptor {
523 /** Flags */
524 uint16_t flags;
525 /** Opcode */
526 uint16_t opcode;
527 /** Data length */
528 uint16_t len;
529 /** Return value */
530 uint16_t ret;
531 /** Opaque cookie / VF opcode */
532 union {
533 /** Cookie */
534 uint32_t cookie;
535 /** VF opcode */
536 uint32_t vopcode;
537 };
538 /** VF return value */
539 int32_t vret;
540 /** Parameters */
541 union intelxl_admin_params params;
542 } __attribute__ (( packed ));
543
544 /** Admin descriptor done */
545 #define INTELXL_ADMIN_FL_DD 0x0001
546
547 /** Admin descriptor contains a completion */
548 #define INTELXL_ADMIN_FL_CMP 0x0002
549
550 /** Admin descriptor completed in error */
551 #define INTELXL_ADMIN_FL_ERR 0x0004
552
553 /** Admin descriptor uses data buffer for command parameters */
554 #define INTELXL_ADMIN_FL_RD 0x0400
555
556 /** Admin descriptor uses data buffer */
557 #define INTELXL_ADMIN_FL_BUF 0x1000
558
559 /** Admin queue */
560 struct intelxl_admin {
561 /** Descriptors */
562 struct intelxl_admin_descriptor *desc;
563 /** Data buffers */
564 union intelxl_admin_buffer *buf;
565 /** Queue index */
566 unsigned int index;
567
568 /** Register block base */
569 unsigned int base;
570 /** Register offsets */
571 const struct intelxl_admin_offsets *regs;
572 };
573
574 /**
575 * Initialise admin queue
576 *
577 * @v admin Admin queue
578 * @v base Register block base
579 * @v regs Register offsets
580 */
581 static inline __attribute__ (( always_inline )) void
intelxl_init_admin(struct intelxl_admin * admin,unsigned int base,const struct intelxl_admin_offsets * regs)582 intelxl_init_admin ( struct intelxl_admin *admin, unsigned int base,
583 const struct intelxl_admin_offsets *regs ) {
584
585 admin->base = base;
586 admin->regs = regs;
587 }
588
589 /** Number of admin queue descriptors */
590 #define INTELXL_ADMIN_NUM_DESC 4
591
592 /** Maximum time to wait for an admin request to complete */
593 #define INTELXL_ADMIN_MAX_WAIT_MS 100
594
595 /** Admin queue API major version */
596 #define INTELXL_ADMIN_API_MAJOR 1
597
598 /******************************************************************************
599 *
600 * Transmit and receive queue context
601 *
602 ******************************************************************************
603 */
604
605 /** CMLAN Context Data Register */
606 #define INTELXL_PFCM_LANCTXDATA(x) ( 0x10c100 + ( 0x80 * (x) ) )
607
608 /** CMLAN Context Control Register */
609 #define INTELXL_PFCM_LANCTXCTL 0x10c300
610 #define INTELXL_PFCM_LANCTXCTL_QUEUE_NUM(x) \
611 ( (x) << 0 ) /**< Queue number */
612 #define INTELXL_PFCM_LANCTXCTL_SUB_LINE(x) \
613 ( (x) << 12 ) /**< Sub-line */
614 #define INTELXL_PFCM_LANCTXCTL_TYPE(x) \
615 ( (x) << 15 ) /**< Queue type */
616 #define INTELXL_PFCM_LANCTXCTL_TYPE_RX \
617 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x0 ) /**< RX queue type */
618 #define INTELXL_PFCM_LANCTXCTL_TYPE_TX \
619 INTELXL_PFCM_LANCTXCTL_TYPE ( 0x1 ) /**< TX queue type */
620 #define INTELXL_PFCM_LANCTXCTL_OP_CODE(x) \
621 ( (x) << 17 ) /**< Op code */
622 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_READ \
623 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x0 ) /**< Read context */
624 #define INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE \
625 INTELXL_PFCM_LANCTXCTL_OP_CODE ( 0x1 ) /**< Write context */
626
627 /** CMLAN Context Status Register */
628 #define INTELXL_PFCM_LANCTXSTAT 0x10c380
629 #define INTELXL_PFCM_LANCTXSTAT_DONE 0x00000001UL /**< Complete */
630
631 /** Queue context line */
632 struct intelxl_context_line {
633 /** Raw data */
634 uint32_t raw[4];
635 } __attribute__ (( packed ));
636
637 /** Transmit queue context */
638 struct intelxl_context_tx {
639 /** Head pointer */
640 uint16_t head;
641 /** Flags */
642 uint16_t flags;
643 /** Base address */
644 uint64_t base;
645 /** Reserved */
646 uint8_t reserved_a[8];
647 /** Queue count */
648 uint16_t count;
649 /** Reserved */
650 uint8_t reserved_b[100];
651 /** Queue set */
652 uint16_t qset;
653 /** Reserved */
654 uint8_t reserved_c[4];
655 } __attribute__ (( packed ));
656
657 /** New transmit queue context */
658 #define INTELXL_CTX_TX_FL_NEW 0x4000
659
660 /** Transmit queue base address */
661 #define INTELXL_CTX_TX_BASE( base ) ( (base) >> 7 )
662
663 /** Transmit queue count */
664 #define INTELXL_CTX_TX_COUNT( count ) ( (count) << 1 )
665
666 /** Transmit queue set */
667 #define INTELXL_CTX_TX_QSET( qset) ( (qset) << 4 )
668
669 /** Receive queue context */
670 struct intelxl_context_rx {
671 /** Head pointer */
672 uint16_t head;
673 /** Reserved */
674 uint8_t reserved_a[2];
675 /** Base address and queue count */
676 uint64_t base_count;
677 /** Data buffer length */
678 uint16_t len;
679 /** Flags */
680 uint8_t flags;
681 /** Reserved */
682 uint8_t reserved_b[7];
683 /** Maximum frame size */
684 uint16_t mfs;
685 } __attribute__ (( packed ));
686
687 /** Receive queue base address and queue count */
688 #define INTELXL_CTX_RX_BASE_COUNT( base, count ) \
689 ( ( (base) >> 7 ) | ( ( ( uint64_t ) (count) ) << 57 ) )
690
691 /** Receive queue data buffer length */
692 #define INTELXL_CTX_RX_LEN( len ) ( (len) >> 1 )
693
694 /** Use 32-byte receive descriptors */
695 #define INTELXL_CTX_RX_FL_DSIZE 0x10
696
697 /** Strip CRC from received packets */
698 #define INTELXL_CTX_RX_FL_CRCSTRIP 0x20
699
700 /** Receive queue maximum frame size */
701 #define INTELXL_CTX_RX_MFS( mfs ) ( (mfs) >> 2 )
702
703 /** Maximum time to wait for a context operation to complete */
704 #define INTELXL_CTX_MAX_WAIT_MS 100
705
706 /** Time to wait for a queue to become enabled */
707 #define INTELXL_QUEUE_ENABLE_DELAY_US 20
708
709 /** Time to wait for a transmit queue to become pre-disabled */
710 #define INTELXL_QUEUE_PRE_DISABLE_DELAY_US 400
711
712 /** Maximum time to wait for a queue to become disabled */
713 #define INTELXL_QUEUE_DISABLE_MAX_WAIT_MS 1000
714
715 /******************************************************************************
716 *
717 * Transmit and receive descriptors
718 *
719 ******************************************************************************
720 */
721
722 /** Global Transmit Queue Head register */
723 #define INTELXL_QTX_HEAD(x) ( 0x0e4000 + ( 0x4 * (x) ) )
724
725 /** Global Transmit Pre Queue Disable register */
726 #define INTELXL_GLLAN_TXPRE_QDIS(x) ( 0x0e6500 + ( 0x4 * ( (x) / 0x80 ) ) )
727 #define INTELXL_GLLAN_TXPRE_QDIS_QINDX(x) \
728 ( (x) << 0 ) /**< Queue index */
729 #define INTELXL_GLLAN_TXPRE_QDIS_SET_QDIS \
730 0x40000000UL /**< Set disable */
731 #define INTELXL_GLLAN_TXPRE_QDIS_CLEAR_QDIS \
732 0x80000000UL /**< Clear disable */
733
734 /** Global Transmit Queue register block */
735 #define INTELXL_QTX(x) ( 0x100000 + ( 0x4 * (x) ) )
736
737 /** Global Receive Queue register block */
738 #define INTELXL_QRX(x) ( 0x120000 + ( 0x4 * (x) ) )
739
740 /** Queue Enable Register (offset) */
741 #define INTELXL_QXX_ENA 0x0000
742 #define INTELXL_QXX_ENA_REQ 0x00000001UL /**< Enable request */
743 #define INTELXL_QXX_ENA_STAT 0x00000004UL /**< Enabled status */
744
745 /** Queue Control Register (offset) */
746 #define INTELXL_QXX_CTL 0x4000
747 #define INTELXL_QXX_CTL_PFVF_Q(x) ( (x) << 0 ) /**< PF/VF queue */
748 #define INTELXL_QXX_CTL_PFVF_Q_PF \
749 INTELXL_QXX_CTL_PFVF_Q ( 0x2 ) /**< PF queue */
750 #define INTELXL_QXX_CTL_PFVF_PF_INDX(x) ( (x) << 2 ) /**< PF index */
751
752 /** Queue Tail Pointer Register (offset) */
753 #define INTELXL_QXX_TAIL 0x8000
754
755 /** Global RLAN Control 0 register */
756 #define INTELXL_GLLAN_RCTL_0 0x12a500
757 #define INTELXL_GLLAN_RCTL_0_PXE_MODE 0x00000001UL /**< PXE mode */
758
759 /** Transmit data descriptor */
760 struct intelxl_tx_data_descriptor {
761 /** Buffer address */
762 uint64_t address;
763 /** Flags */
764 uint32_t flags;
765 /** Length */
766 uint32_t len;
767 } __attribute__ (( packed ));
768
769 /** Transmit data descriptor type */
770 #define INTELXL_TX_DATA_DTYP 0x0
771
772 /** Transmit data descriptor end of packet */
773 #define INTELXL_TX_DATA_EOP 0x10
774
775 /** Transmit data descriptor report status */
776 #define INTELXL_TX_DATA_RS 0x20
777
778 /** Transmit data descriptor pretty please
779 *
780 * This bit is completely missing from older versions of the XL710
781 * datasheet. Later versions describe it innocuously as "reserved,
782 * must be 1". Without this bit, everything will appear to work (up
783 * to and including the port "transmit good octets" counter), but no
784 * packet will actually be sent.
785 */
786 #define INTELXL_TX_DATA_JFDI 0x40
787
788 /** Transmit data descriptor length */
789 #define INTELXL_TX_DATA_LEN( len ) ( (len) << 2 )
790
791 /** Transmit writeback descriptor */
792 struct intelxl_tx_writeback_descriptor {
793 /** Reserved */
794 uint8_t reserved_a[8];
795 /** Flags */
796 uint8_t flags;
797 /** Reserved */
798 uint8_t reserved_b[7];
799 } __attribute__ (( packed ));
800
801 /** Transmit writeback descriptor complete */
802 #define INTELXL_TX_WB_FL_DD 0x01
803
804 /** Transmit descriptor */
805 union intelxl_tx_descriptor {
806 /** Transmit data descriptor */
807 struct intelxl_tx_data_descriptor data;
808 /** Transmit writeback descriptor */
809 struct intelxl_tx_writeback_descriptor wb;
810 };
811
812 /** Receive data descriptor */
813 struct intelxl_rx_data_descriptor {
814 /** Buffer address */
815 uint64_t address;
816 /** Flags */
817 uint32_t flags;
818 /** Reserved */
819 uint8_t reserved[20];
820 } __attribute__ (( packed ));
821
822 /** Receive writeback descriptor */
823 struct intelxl_rx_writeback_descriptor {
824 /** Reserved */
825 uint8_t reserved_a[2];
826 /** VLAN tag */
827 uint16_t vlan;
828 /** Reserved */
829 uint8_t reserved_b[4];
830 /** Flags */
831 uint32_t flags;
832 /** Length */
833 uint32_t len;
834 /** Reserved */
835 uint8_t reserved_c[16];
836 } __attribute__ (( packed ));
837
838 /** Receive writeback descriptor complete */
839 #define INTELXL_RX_WB_FL_DD 0x00000001UL
840
841 /** Receive writeback descriptor VLAN tag present */
842 #define INTELXL_RX_WB_FL_VLAN 0x00000004UL
843
844 /** Receive writeback descriptor error */
845 #define INTELXL_RX_WB_FL_RXE 0x00080000UL
846
847 /** Receive writeback descriptor length */
848 #define INTELXL_RX_WB_LEN(len) ( ( (len) >> 6 ) & 0x3fff )
849
850 /** Packet descriptor */
851 union intelxl_rx_descriptor {
852 /** Receive data descriptor */
853 struct intelxl_rx_data_descriptor data;
854 /** Receive writeback descriptor */
855 struct intelxl_rx_writeback_descriptor wb;
856 };
857
858 /** Descriptor ring */
859 struct intelxl_ring {
860 /** Descriptors */
861 union {
862 /** Transmit descriptors */
863 union intelxl_tx_descriptor *tx;
864 /** Receive descriptors */
865 union intelxl_rx_descriptor *rx;
866 /** Raw data */
867 void *raw;
868 } desc;
869 /** Producer index */
870 unsigned int prod;
871 /** Consumer index */
872 unsigned int cons;
873
874 /** Register block */
875 unsigned int reg;
876 /** Tail register */
877 unsigned int tail;
878 /** Length (in bytes) */
879 size_t len;
880 /** Program queue context
881 *
882 * @v intelxl Intel device
883 * @v address Descriptor ring base address
884 */
885 int ( * context ) ( struct intelxl_nic *intelxl, physaddr_t address );
886 };
887
888 /**
889 * Initialise descriptor ring
890 *
891 * @v ring Descriptor ring
892 * @v count Number of descriptors
893 * @v len Length of a single descriptor
894 * @v context Method to program queue context
895 */
896 static inline __attribute__ (( always_inline)) void
intelxl_init_ring(struct intelxl_ring * ring,unsigned int count,size_t len,int (* context)(struct intelxl_nic * intelxl,physaddr_t address))897 intelxl_init_ring ( struct intelxl_ring *ring, unsigned int count, size_t len,
898 int ( * context ) ( struct intelxl_nic *intelxl,
899 physaddr_t address ) ) {
900
901 ring->len = ( count * len );
902 ring->context = context;
903 }
904
905 /** Number of transmit descriptors
906 *
907 * Chosen to exceed the receive ring fill level, in order to avoid
908 * running out of transmit descriptors when sending TCP ACKs.
909 */
910 #define INTELXL_TX_NUM_DESC 64
911
912 /** Transmit descriptor ring maximum fill level */
913 #define INTELXL_TX_FILL ( INTELXL_TX_NUM_DESC - 1 )
914
915 /** Number of receive descriptors
916 *
917 * Must be a multiple of 32.
918 */
919 #define INTELXL_RX_NUM_DESC 32
920
921 /** Receive descriptor ring fill level
922 *
923 * Must be a multiple of 8 and greater than 8.
924 */
925 #define INTELXL_RX_FILL 16
926
927 /******************************************************************************
928 *
929 * Top level
930 *
931 ******************************************************************************
932 */
933
934 /** PF Interrupt Zero Dynamic Control Register */
935 #define INTELXL_PFINT_DYN_CTL0 0x038480
936 #define INTELXL_INT_DYN_CTL_INTENA 0x00000001UL /**< Enable */
937 #define INTELXL_INT_DYN_CTL_CLEARPBA 0x00000002UL /**< Acknowledge */
938 #define INTELXL_INT_DYN_CTL_INTENA_MASK 0x80000000UL /**< Ignore enable */
939
940 /** PF Interrupt Zero Linked List Register */
941 #define INTELXL_PFINT_LNKLST0 0x038500
942 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX(x) \
943 ( (x) << 0 ) /**< Queue index */
944 #define INTELXL_PFINT_LNKLST0_FIRSTQ_INDX_NONE \
945 INTELXL_PFINT_LNKLST0_FIRSTQ_INDX ( 0x7ff ) /**< End of list */
946 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE(x) \
947 ( (x) << 11 ) /**< Queue type */
948 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_RX \
949 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x0 ) /**< Receive queue */
950 #define INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE_TX \
951 INTELXL_PFINT_LNKLST0_FIRSTQ_TYPE ( 0x1 ) /**< Transmit queue */
952
953 /** PF Interrupt Zero Cause Enablement Register */
954 #define INTELXL_PFINT_ICR0_ENA 0x038800
955 #define INTELXL_PFINT_ICR0_ENA_ADMINQ 0x40000000UL /**< Admin event */
956
957 /** Receive Queue Interrupt Cause Control Register */
958 #define INTELXL_QINT_RQCTL(x) ( 0x03a000 + ( 0x4 * (x) ) )
959 #define INTELXL_QINT_RQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
960 #define INTELXL_QINT_RQCTL_NEXTQ_INDX_NONE \
961 INTELXL_QINT_RQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
962 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
963 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_RX \
964 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
965 #define INTELXL_QINT_RQCTL_NEXTQ_TYPE_TX \
966 INTELXL_QINT_RQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
967 #define INTELXL_QINT_RQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
968
969 /** Transmit Queue Interrupt Cause Control Register */
970 #define INTELXL_QINT_TQCTL(x) ( 0x03c000 + ( 0x4 * (x) ) )
971 #define INTELXL_QINT_TQCTL_NEXTQ_INDX(x) ( (x) << 16 ) /**< Queue index */
972 #define INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE \
973 INTELXL_QINT_TQCTL_NEXTQ_INDX ( 0x7ff ) /**< End of list */
974 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE(x) ( (x) << 27 ) /**< Queue type */
975 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_RX \
976 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x0 ) /**< Receive queue */
977 #define INTELXL_QINT_TQCTL_NEXTQ_TYPE_TX \
978 INTELXL_QINT_TQCTL_NEXTQ_TYPE ( 0x1 ) /**< Transmit queue */
979 #define INTELXL_QINT_TQCTL_CAUSE_ENA 0x40000000UL /**< Enable */
980
981 /** PF Control Register */
982 #define INTELXL_PFGEN_CTRL 0x092400
983 #define INTELXL_PFGEN_CTRL_PFSWR 0x00000001UL /**< Software Reset */
984
985 /** Time to delay for device reset, in milliseconds */
986 #define INTELXL_RESET_DELAY_MS 100
987
988 /** PF Queue Allocation Register */
989 #define INTELXL_PFLAN_QALLOC 0x1c0400
990 #define INTELXL_PFLAN_QALLOC_FIRSTQ(x) \
991 ( ( (x) >> 0 ) & 0x7ff ) /**< First queue */
992 #define INTELXL_PFLAN_QALLOC_LASTQ(x) \
993 ( ( (x) >> 16 ) & 0x7ff ) /**< Last queue */
994
995 /** PF LAN Port Number Register */
996 #define INTELXL_PFGEN_PORTNUM 0x1c0480
997 #define INTELXL_PFGEN_PORTNUM_PORT_NUM(x) \
998 ( ( (x) >> 0 ) & 0x3 ) /**< Port number */
999
1000 /** Port MAC Address Low Register */
1001 #define INTELXL_PRTGL_SAL 0x1e2120
1002
1003 /** Port MAC Address High Register */
1004 #define INTELXL_PRTGL_SAH 0x1e2140
1005 #define INTELXL_PRTGL_SAH_MFS_GET(x) ( (x) >> 16 ) /**< Max frame size */
1006 #define INTELXL_PRTGL_SAH_MFS_SET(x) ( (x) << 16 ) /**< Max frame size */
1007
1008 /** Receive address */
1009 union intelxl_receive_address {
1010 struct {
1011 uint32_t low;
1012 uint32_t high;
1013 } __attribute__ (( packed )) reg;
1014 uint8_t raw[ETH_ALEN];
1015 };
1016
1017 /** An Intel 40Gigabit network card */
1018 struct intelxl_nic {
1019 /** Registers */
1020 void *regs;
1021 /** Maximum frame size */
1022 size_t mfs;
1023
1024 /** Physical function number */
1025 unsigned int pf;
1026 /** Absolute queue number base */
1027 unsigned int base;
1028 /** Port number */
1029 unsigned int port;
1030 /** Queue number */
1031 unsigned int queue;
1032 /** Virtual Station Interface switching element ID */
1033 unsigned int vsi;
1034 /** Queue set handle */
1035 unsigned int qset;
1036 /** Interrupt control register */
1037 unsigned int intr;
1038 /** MSI-X capability */
1039 struct pci_msix msix;
1040 /** MSI-X dummy interrupt target */
1041 uint32_t msg;
1042 /** PCI Express capability offset */
1043 unsigned int exp;
1044
1045 /** Admin command queue */
1046 struct intelxl_admin command;
1047 /** Admin event queue */
1048 struct intelxl_admin event;
1049
1050 /** Current VF opcode */
1051 unsigned int vopcode;
1052 /** Current VF return value */
1053 int vret;
1054 /** Current VF event data buffer */
1055 union intelxl_admin_buffer vbuf;
1056
1057 /** Transmit descriptor ring */
1058 struct intelxl_ring tx;
1059 /** Receive descriptor ring */
1060 struct intelxl_ring rx;
1061 /** Receive I/O buffers */
1062 struct io_buffer *rx_iobuf[INTELXL_RX_NUM_DESC];
1063 };
1064
1065 extern int intelxl_msix_enable ( struct intelxl_nic *intelxl,
1066 struct pci_device *pci );
1067 extern void intelxl_msix_disable ( struct intelxl_nic *intelxl,
1068 struct pci_device *pci );
1069 extern struct intelxl_admin_descriptor *
1070 intelxl_admin_command_descriptor ( struct intelxl_nic *intelxl );
1071 extern union intelxl_admin_buffer *
1072 intelxl_admin_command_buffer ( struct intelxl_nic *intelxl );
1073 extern int intelxl_admin_command ( struct intelxl_nic *intelxl );
1074 extern void intelxl_poll_admin ( struct net_device *netdev );
1075 extern int intelxl_open_admin ( struct intelxl_nic *intelxl );
1076 extern void intelxl_reopen_admin ( struct intelxl_nic *intelxl );
1077 extern void intelxl_close_admin ( struct intelxl_nic *intelxl );
1078 extern int intelxl_alloc_ring ( struct intelxl_nic *intelxl,
1079 struct intelxl_ring *ring );
1080 extern void intelxl_free_ring ( struct intelxl_nic *intelxl,
1081 struct intelxl_ring *ring );
1082 extern void intelxl_empty_rx ( struct intelxl_nic *intelxl );
1083 extern int intelxl_transmit ( struct net_device *netdev,
1084 struct io_buffer *iobuf );
1085 extern void intelxl_poll ( struct net_device *netdev );
1086
1087 extern void intelxlvf_admin_event ( struct net_device *netdev,
1088 struct intelxl_admin_descriptor *evt,
1089 union intelxl_admin_buffer *buf );
1090
1091 #endif /* _INTELXL_H */
1092