1 // Internal timer and Intel 8253 Programmable Interrupt Timer (PIT) support.
2 //
3 // Copyright (C) 2008-2013 Kevin O'Connor <kevin@koconnor.net>
4 //
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
6
7 #include "biosvar.h" // GET_LOW
8 #include "config.h" // CONFIG_*
9 #include "output.h" // dprintf
10 #include "stacks.h" // yield
11 #include "util.h" // timer_setup
12 #include "x86.h" // cpuid
13
14 #define PORT_PIT_COUNTER0 0x0040
15 #define PORT_PIT_COUNTER1 0x0041
16 #define PORT_PIT_COUNTER2 0x0042
17 #define PORT_PIT_MODE 0x0043
18 #define PORT_PS2_CTRLB 0x0061
19
20 // Bits for PORT_PIT_MODE
21 #define PM_SEL_TIMER0 (0<<6)
22 #define PM_SEL_TIMER1 (1<<6)
23 #define PM_SEL_TIMER2 (2<<6)
24 #define PM_SEL_READBACK (3<<6)
25 #define PM_ACCESS_LATCH (0<<4)
26 #define PM_ACCESS_LOBYTE (1<<4)
27 #define PM_ACCESS_HIBYTE (2<<4)
28 #define PM_ACCESS_WORD (3<<4)
29 #define PM_MODE0 (0<<1)
30 #define PM_MODE1 (1<<1)
31 #define PM_MODE2 (2<<1)
32 #define PM_MODE3 (3<<1)
33 #define PM_MODE4 (4<<1)
34 #define PM_MODE5 (5<<1)
35 #define PM_CNT_BINARY (0<<0)
36 #define PM_CNT_BCD (1<<0)
37 #define PM_READ_COUNTER0 (1<<1)
38 #define PM_READ_COUNTER1 (1<<2)
39 #define PM_READ_COUNTER2 (1<<3)
40 #define PM_READ_STATUSVALUE (0<<4)
41 #define PM_READ_VALUE (1<<4)
42 #define PM_READ_STATUS (2<<4)
43
44 // Bits for PORT_PS2_CTRLB
45 #define PPCB_T2GATE (1<<0)
46 #define PPCB_SPKR (1<<1)
47 #define PPCB_T2OUT (1<<5)
48
49 #define PMTIMER_HZ 3579545 // Underlying Hz of the PM Timer
50 #define PMTIMER_TO_PIT 3 // Ratio of pmtimer rate to pit rate
51
52 u32 TimerKHz VARFSEG = DIV_ROUND_UP(PMTIMER_HZ, 1000 * PMTIMER_TO_PIT);
53 u16 TimerPort VARFSEG = PORT_PIT_COUNTER0;
54 u8 ShiftTSC VARFSEG;
55
56
57 /****************************************************************
58 * Internal timer setup
59 ****************************************************************/
60
61 #define CALIBRATE_COUNT 0x800 // Approx 1.7ms
62
63 // Calibrate the CPU time-stamp-counter
64 static void
tsctimer_setup(void)65 tsctimer_setup(void)
66 {
67 // Setup "timer2"
68 u8 orig = inb(PORT_PS2_CTRLB);
69 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
70 /* binary, mode 0, LSB/MSB, Ch 2 */
71 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
72 /* LSB of ticks */
73 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
74 /* MSB of ticks */
75 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
76
77 u64 start = rdtscll();
78 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
79 ;
80 u64 end = rdtscll();
81
82 // Restore PORT_PS2_CTRLB
83 outb(orig, PORT_PS2_CTRLB);
84
85 // Store calibrated cpu khz.
86 u64 diff = end - start;
87 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
88 , (u32)start, (u32)end, (u32)diff);
89 u64 t = DIV_ROUND_UP(diff * PMTIMER_HZ, CALIBRATE_COUNT);
90 while (t >= (1<<24)) {
91 ShiftTSC++;
92 t = (t + 1) >> 1;
93 }
94 TimerKHz = DIV_ROUND_UP((u32)t, 1000 * PMTIMER_TO_PIT);
95 TimerPort = 0;
96
97 dprintf(1, "CPU Mhz=%u\n", (TimerKHz << ShiftTSC) / 1000);
98 }
99
100 // Setup internal timers.
101 void
timer_setup(void)102 timer_setup(void)
103 {
104 if (!CONFIG_TSC_TIMER || (CONFIG_PMTIMER && TimerPort != PORT_PIT_COUNTER0))
105 return;
106
107 // Check if CPU has a timestamp counter
108 u32 eax, ebx, ecx, edx, cpuid_features = 0;
109 cpuid(0, &eax, &ebx, &ecx, &edx);
110 if (eax > 0)
111 cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
112 if (cpuid_features & CPUID_TSC)
113 tsctimer_setup();
114 }
115
116 void
pmtimer_setup(u16 ioport)117 pmtimer_setup(u16 ioport)
118 {
119 if (!CONFIG_PMTIMER)
120 return;
121 dprintf(1, "Using pmtimer, ioport 0x%x\n", ioport);
122 TimerPort = ioport;
123 TimerKHz = DIV_ROUND_UP(PMTIMER_HZ, 1000);
124 }
125
126
127 /****************************************************************
128 * Internal timer reading
129 ****************************************************************/
130
131 u32 TimerLast VARLOW;
132
133 // Add extra high bits to timers that have less than 32bits of precision.
134 static u32
timer_adjust_bits(u32 value,u32 validbits)135 timer_adjust_bits(u32 value, u32 validbits)
136 {
137 u32 last = GET_LOW(TimerLast);
138 value = (last & ~validbits) | (value & validbits);
139 if (value < last)
140 value += validbits + 1;
141 SET_LOW(TimerLast, value);
142 return value;
143 }
144
145 // Sample the current timer value.
146 static u32
timer_read(void)147 timer_read(void)
148 {
149 u16 port = GET_GLOBAL(TimerPort);
150 if (CONFIG_TSC_TIMER && !port)
151 // Read from CPU TSC
152 return rdtscll() >> GET_GLOBAL(ShiftTSC);
153 if (CONFIG_PMTIMER && port != PORT_PIT_COUNTER0)
154 // Read from PMTIMER
155 return timer_adjust_bits(inl(port), 0xffffff);
156 // Read from PIT.
157 outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE);
158 u16 v = inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8);
159 return timer_adjust_bits(v, 0xffff);
160 }
161
162 // Return the TSC value that is 'msecs' time in the future.
163 u32
timer_calc(u32 msecs)164 timer_calc(u32 msecs)
165 {
166 return timer_read() + (GET_GLOBAL(TimerKHz) * msecs);
167 }
168 u32
timer_calc_usec(u32 usecs)169 timer_calc_usec(u32 usecs)
170 {
171 u32 cur = timer_read(), khz = GET_GLOBAL(TimerKHz);
172 if (usecs > 500000)
173 return cur + DIV_ROUND_UP(usecs, 1000) * khz;
174 return cur + DIV_ROUND_UP(usecs * khz, 1000);
175 }
176 static u32
timer_calc_nsec(u32 nsecs)177 timer_calc_nsec(u32 nsecs)
178 {
179 u32 cur = timer_read(), khz = GET_GLOBAL(TimerKHz);
180 if (nsecs > 500000)
181 return cur + DIV_ROUND_UP(nsecs, 1000000) * khz;
182 return cur + DIV_ROUND_UP(nsecs * khz, 1000000);
183 }
184
185 // Check if the current time is past a previously calculated end time.
186 int
timer_check(u32 end)187 timer_check(u32 end)
188 {
189 return (s32)(timer_read() - end) > 0;
190 }
191
192 static void
timer_delay(u32 end)193 timer_delay(u32 end)
194 {
195 while (!timer_check(end))
196 cpu_relax();
197 }
198
199 static void
timer_sleep(u32 end)200 timer_sleep(u32 end)
201 {
202 while (!timer_check(end))
203 yield();
204 }
205
ndelay(u32 count)206 void ndelay(u32 count) {
207 timer_delay(timer_calc_nsec(count));
208 }
udelay(u32 count)209 void udelay(u32 count) {
210 timer_delay(timer_calc_usec(count));
211 }
mdelay(u32 count)212 void mdelay(u32 count) {
213 timer_delay(timer_calc(count));
214 }
215
nsleep(u32 count)216 void nsleep(u32 count) {
217 timer_sleep(timer_calc_nsec(count));
218 }
usleep(u32 count)219 void usleep(u32 count) {
220 timer_sleep(timer_calc_usec(count));
221 }
msleep(u32 count)222 void msleep(u32 count) {
223 timer_sleep(timer_calc(count));
224 }
225
226
227 /****************************************************************
228 * PIT setup
229 ****************************************************************/
230
231 #define PIT_TICK_INTERVAL 65536 // Default interval for 18.2Hz timer
232
233 // Return the number of milliseconds in 'ticks' number of timer irqs.
234 u32
ticks_to_ms(u32 ticks)235 ticks_to_ms(u32 ticks)
236 {
237 u32 t = PIT_TICK_INTERVAL * 1000 * PMTIMER_TO_PIT * ticks;
238 return DIV_ROUND_UP(t, PMTIMER_HZ);
239 }
240
241 // Return the number of timer irqs in 'ms' number of milliseconds.
242 u32
ticks_from_ms(u32 ms)243 ticks_from_ms(u32 ms)
244 {
245 u32 t = DIV_ROUND_UP((u64)ms * PMTIMER_HZ, PIT_TICK_INTERVAL);
246 return DIV_ROUND_UP(t, 1000 * PMTIMER_TO_PIT);
247 }
248
249 void
pit_setup(void)250 pit_setup(void)
251 {
252 if (!CONFIG_HARDWARE_IRQ)
253 return;
254 // timer0: binary count, 16bit count, mode 2
255 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
256 // maximum count of 0000H = 18.2Hz
257 outb(0x0, PORT_PIT_COUNTER0);
258 outb(0x0, PORT_PIT_COUNTER0);
259 }
260