1 /* Copyright 2013-2016 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __PLATFORM_H 18 #define __PLATFORM_H 19 20 /* Some fwd declarations for types used further down */ 21 struct phb; 22 struct pci_device; 23 struct pci_slot; 24 struct errorlog; 25 struct npu2; 26 27 enum resource_id { 28 RESOURCE_ID_KERNEL, 29 RESOURCE_ID_INITRAMFS, 30 RESOURCE_ID_CAPP, 31 RESOURCE_ID_IMA_CATALOG, 32 RESOURCE_ID_VERSION, 33 RESOURCE_ID_KERNEL_FW, 34 }; 35 #define RESOURCE_SUBID_NONE 0 36 #define RESOURCE_SUBID_SUPPORTED 1 37 38 39 struct bmc_hw_config { 40 uint32_t scu_revision_id; 41 uint32_t mcr_configuration; 42 uint32_t mcr_scu_mpll; 43 uint32_t mcr_scu_strap; 44 }; 45 46 struct bmc_sw_config { 47 /* 48 * Map IPMI_OEM_X to vendor commands for this BMC 49 * 0 = unimplimented 50 */ 51 uint32_t ipmi_oem_partial_add_esel; 52 uint32_t ipmi_oem_pnor_access_status; 53 uint32_t ipmi_oem_hiomap_cmd; 54 }; 55 56 struct bmc_platform { 57 const char *name; 58 const struct bmc_hw_config *hw; 59 const struct bmc_sw_config *sw; 60 }; 61 62 /* OpenCAPI platform-specific I2C information */ 63 struct platform_ocapi { 64 uint8_t i2c_engine; /* I2C engine number */ 65 uint8_t i2c_port; /* I2C port number */ 66 uint8_t i2c_reset_addr; /* I2C address for reset */ 67 uint8_t i2c_reset_brick2; /* I2C pin to write to reset brick 2 */ 68 uint8_t i2c_reset_brick3; /* I2C pin to write to reset brick 3 */ 69 uint8_t i2c_reset_brick4; /* I2C pin to write to reset brick 4 */ 70 uint8_t i2c_reset_brick5; /* I2C pin to write to reset brick 5 */ 71 uint8_t i2c_presence_addr; /* I2C address for presence detection */ 72 uint8_t i2c_presence_brick2; /* I2C pin to read for presence on brick 2 */ 73 uint8_t i2c_presence_brick3; /* I2C pin to read for presence on brick 3 */ 74 uint8_t i2c_presence_brick4; /* I2C pin to read for presence on brick 4 */ 75 uint8_t i2c_presence_brick5; /* I2C pin to read for presence on brick 5 */ 76 bool odl_phy_swap; /* Swap ODL1 to use brick 2 rather than 77 * brick 1 lanes */ 78 }; 79 80 struct dt_node; 81 82 /* 83 * Just for FSP platforms, allows us to partly decouple 84 * FSP specific code from core code. 85 */ 86 struct platform_psi { 87 void (*psihb_interrupt)(void); 88 void (*link_established)(void); 89 void (*fsp_interrupt)(void); 90 }; 91 92 /* 93 * Some PRD functionality is platform specific. 94 */ 95 struct platform_prd { 96 void (*msg_response)(uint32_t rc); 97 int (*send_error_log)(uint32_t plid, uint32_t dsize, void *data); 98 int (*send_hbrt_msg)(void *data, u64 dsize); 99 int (*wakeup)(uint32_t i_core, uint32_t i_mode); 100 int (*fsp_occ_load_start_status)(u64 chipid, s64 status); 101 int (*fsp_occ_reset_status)(u64 chipid, s64 status); 102 }; 103 104 /* 105 * Each platform can provide a set of hooks 106 * that can affect the generic code 107 */ 108 struct platform { 109 const char *name; 110 111 /* 112 * If BMC is constant, bmc platform specified here. 113 * Platforms can also call set_bmc_platform() if BMC platform is 114 * not a constant. 115 */ 116 const struct bmc_platform *bmc; 117 118 /* 119 * PSI handling code. FSP specific. 120 */ 121 const struct platform_psi *psi; 122 123 /* 124 * Platform specific PRD handling 125 */ 126 const struct platform_prd *prd; 127 128 /* OpenCAPI platform-specific I2C information */ 129 const struct platform_ocapi *ocapi; 130 131 /* NPU2 device detection */ 132 void (*npu2_device_detect)(struct npu2 *npu); 133 134 /* 135 * Probe platform, return true on a match, called before 136 * any allocation has been performed outside of the heap 137 * so the platform can perform additional memory reservations 138 * here if needed. 139 * 140 * Only the boot CPU is running at this point and the cpu_thread 141 * structure for secondaries have not been initialized yet. The 142 * timebases are not synchronized. 143 * 144 * Services available: 145 * 146 * - Memory allocations / reservations 147 * - XSCOM 148 * - FSI 149 * - Host Services 150 */ 151 bool (*probe)(void); 152 153 /* 154 * This is called right after the secondary processors are brought 155 * up and the timebases in sync to perform any additional platform 156 * specific initializations. On FSP based machines, this is where 157 * the FSP driver is brought up. 158 */ 159 void (*init)(void); 160 161 /* 162 * Called once every thread is back in skiboot as part of fast reboot. 163 */ 164 void (*fast_reboot_init)(void); 165 166 /* 167 * These are used to power down and reboot the machine 168 */ 169 int64_t (*cec_power_down)(uint64_t request); 170 int64_t (*cec_reboot)(void); 171 172 /* 173 * This is called once per PHB before probing. It allows the 174 * platform to setup some PHB private data that can be used 175 * later on by calls such as pci_get_slot_info() below. The 176 * "index" argument is the PHB index within the IO HUB (or 177 * P8 chip). 178 * 179 * This is called before the PHB HW has been initialized. 180 */ 181 void (*pci_setup_phb)(struct phb *phb, unsigned int index); 182 183 /* 184 * This is called before resetting the PHBs (lift PERST) and 185 * probing the devices. The PHBs have already been initialized. 186 */ 187 void (*pre_pci_fixup)(void); 188 /* 189 * Called during PCI scan for each device. For bridges, this is 190 * called before its children are probed. This is called for 191 * every device and for the PHB itself with a NULL pd though 192 * typically the implementation will only populate the slot 193 * info structure for bridge ports 194 */ 195 void (*pci_get_slot_info)(struct phb *phb, 196 struct pci_device *pd); 197 198 /* 199 * Called after PCI probe is complete and before inventory is 200 * displayed in console. This can either run platform fixups or 201 * can be used to send the inventory to a service processor. 202 */ 203 void (*pci_probe_complete)(void); 204 205 /* 206 * If the above is set to skiboot, the handler is here 207 */ 208 void (*external_irq)(unsigned int chip_id); 209 210 /* 211 * nvram ops. 212 * 213 * Note: To keep the FSP driver simple, we only ever read the 214 * whole nvram once at boot and we do this passing a dst buffer 215 * that is 4K aligned. The read is asynchronous, the backend 216 * must call nvram_read_complete() when done (it's allowed to 217 * do it recursively from nvram_read though). 218 */ 219 int (*nvram_info)(uint32_t *total_size); 220 int (*nvram_start_read)(void *dst, uint32_t src, 221 uint32_t len); 222 int (*nvram_write)(uint32_t dst, void *src, uint32_t len); 223 224 /* 225 * OCC timeout. This return how long we should wait for the OCC 226 * before timing out. This lets us use a high value on larger FSP 227 * machines and cut it off completely on BML boots and OpenPower 228 * machines without pre-existing OCC firmware. Returns a value in 229 * seconds. 230 */ 231 uint32_t (*occ_timeout)(void); 232 233 int (*elog_commit)(struct errorlog *buf); 234 235 /* 236 * Initiate loading an external resource (e.g. kernel payload, OCC) 237 * into a preallocated buffer. 238 * This is designed to asynchronously load external resources. 239 * Returns OPAL_SUCCESS or error. 240 */ 241 int (*start_preload_resource)(enum resource_id id, 242 uint32_t idx, 243 void *buf, size_t *len); 244 245 /* 246 * Returns true when resource is loaded. 247 * Only has to return true once, for the 248 * preivous start_preload_resource call for this resource. 249 * If not implemented, will return true and start_preload_resource 250 * *must* have synchronously done the load. 251 * Retruns OPAL_SUCCESS, OPAL_BUSY or an error code 252 */ 253 int (*resource_loaded)(enum resource_id id, uint32_t idx); 254 255 /* 256 * Executed just prior to creating the dtb for the kernel. 257 */ 258 void (*finalise_dt)(bool is_reboot); 259 260 /* 261 * Executed just prior to handing control over to the payload. 262 * Used to terminate watchdogs, etc. 263 */ 264 void (*exit)(void); 265 266 /* 267 * Read a sensor value 268 */ 269 int64_t (*sensor_read)(uint32_t sensor_hndl, int token, 270 uint64_t *sensor_data); 271 /* 272 * Return the heartbeat time 273 */ 274 int (*heartbeat_time)(void); 275 276 /* 277 * OPAL terminate 278 */ 279 void __attribute__((noreturn)) (*terminate)(const char *msg); 280 281 /* 282 * SEEPROM update routine 283 */ 284 void (*seeprom_update)(void); 285 286 /* 287 * Operator Panel display 288 * Physical FSP op panel or LPC port 80h 289 * or any other "get boot status out to the user" thing. 290 */ 291 void (*op_display)(enum op_severity sev, enum op_module mod, 292 uint16_t code); 293 294 /* 295 * VPD load. 296 * Currently FSP specific. 297 */ 298 void (*vpd_iohub_load)(struct dt_node *hub_node); 299 }; 300 301 extern struct platform __platforms_start; 302 extern struct platform __platforms_end; 303 304 extern struct platform platform; 305 extern const struct bmc_platform *bmc_platform; 306 307 extern bool manufacturing_mode; 308 309 #define DECLARE_PLATFORM(name)\ 310 static const struct platform __used __section(".platforms") name ##_platform 311 312 extern void probe_platform(void); 313 314 extern int start_preload_resource(enum resource_id id, uint32_t subid, 315 void *buf, size_t *len); 316 317 extern int resource_loaded(enum resource_id id, uint32_t idx); 318 319 extern int wait_for_resource_loaded(enum resource_id id, uint32_t idx); 320 321 extern void set_bmc_platform(const struct bmc_platform *bmc); 322 323 #endif /* __PLATFORM_H */ 324