1 /* 2 * DMA Masks 3 */ 4 5 #ifndef __BFIN_PERIPHERAL_DMA__ 6 #define __BFIN_PERIPHERAL_DMA__ 7 8 /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ 9 #define DMAEN 0x0001 /* DMA Channel Enable */ 10 #define WNR 0x0002 /* Channel Direction (W/R*) */ 11 #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ 12 #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ 13 #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ 14 #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ 15 #define RESTART 0x0020 /* DMA Buffer Clear */ 16 #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ 17 #define DI_EN 0x0080 /* Data Interrupt Enable */ 18 #define NDSIZE 0x0F00 /* Next Descriptor bitmask */ 19 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ 20 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ 21 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ 22 #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ 23 #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ 24 #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ 25 #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ 26 #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ 27 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ 28 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ 29 #define FLOW_STOP 0x0000 /* Stop Mode */ 30 #define FLOW_AUTO 0x1000 /* Autobuffer Mode */ 31 #define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */ 32 #define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ 33 #define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ 34 35 #define DMAEN_P 0 /* Channel Enable */ 36 #define WNR_P 1 /* Channel Direction (W/R*) */ 37 #define DMA2D_P 4 /* 2D/1D* Mode */ 38 #define RESTART_P 5 /* Restart */ 39 #define DI_SEL_P 6 /* Data Interrupt Select */ 40 #define DI_EN_P 7 /* Data Interrupt Enable */ 41 42 /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ 43 #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ 44 #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ 45 #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ 46 #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ 47 48 #define DMA_DONE_P 0 /* DMA Done Indicator */ 49 #define DMA_ERR_P 1 /* DMA Error Indicator */ 50 #define DFETCH_P 2 /* Descriptor Fetch Indicator */ 51 #define DMA_RUN_P 3 /* DMA Running Indicator */ 52 53 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 54 #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ 55 #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ 56 #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ 57 58 #endif 59