1 /*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 #include <common.h>
28 #include <malloc.h>
29 #include <command.h>
30 #include <config.h>
31 #include <net.h>
32 #include <miiphy.h>
33
34 #undef ET_DEBUG
35 #undef MII_DEBUG
36
37 /* Ethernet Transmit and Receive Buffers */
38 #define DBUF_LENGTH 1520
39 #define PKT_MAXBUF_SIZE 1518
40 #define PKT_MINBUF_SIZE 64
41 #define PKT_MAXBLR_SIZE 1536
42 #define LAST_PKTBUFSRX PKTBUFSRX - 1
43 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
44 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
45 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
46
47 /* RxBD bits definitions */
48 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
49 BD_ENET_RX_OV | BD_ENET_RX_TR)
50
51 #include <asm/immap.h>
52 #include <asm/fsl_mcdmafec.h>
53
54 #include "MCD_dma.h"
55
56 DECLARE_GLOBAL_DATA_PTR;
57
58 struct fec_info_dma fec_info[] = {
59 #ifdef CONFIG_SYS_FEC0_IOBASE
60 {
61 0, /* index */
62 CONFIG_SYS_FEC0_IOBASE, /* io base */
63 CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
64 CONFIG_SYS_FEC0_MIIBASE, /* mii base */
65 -1, /* phy_addr */
66 0, /* duplex and speed */
67 0, /* phy name */
68 0, /* phyname init */
69 0, /* RX BD */
70 0, /* TX BD */
71 0, /* rx Index */
72 0, /* tx Index */
73 0, /* tx buffer */
74 0, /* initialized flag */
75 (struct fec_info_dma *)-1, /* next */
76 FEC0_RX_TASK, /* rxTask */
77 FEC0_TX_TASK, /* txTask */
78 FEC0_RX_PRIORITY, /* rxPri */
79 FEC0_TX_PRIORITY, /* txPri */
80 FEC0_RX_INIT, /* rxInit */
81 FEC0_TX_INIT, /* txInit */
82 0, /* usedTbdIndex */
83 0, /* cleanTbdNum */
84 },
85 #endif
86 #ifdef CONFIG_SYS_FEC1_IOBASE
87 {
88 1, /* index */
89 CONFIG_SYS_FEC1_IOBASE, /* io base */
90 CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
91 CONFIG_SYS_FEC1_MIIBASE, /* mii base */
92 -1, /* phy_addr */
93 0, /* duplex and speed */
94 0, /* phy name */
95 0, /* phy name init */
96 #ifdef CONFIG_SYS_DMA_USE_INTSRAM
97 (cbd_t *)DBUF_LENGTH, /* RX BD */
98 #else
99 0, /* RX BD */
100 #endif
101 0, /* TX BD */
102 0, /* rx Index */
103 0, /* tx Index */
104 0, /* tx buffer */
105 0, /* initialized flag */
106 (struct fec_info_dma *)-1, /* next */
107 FEC1_RX_TASK, /* rxTask */
108 FEC1_TX_TASK, /* txTask */
109 FEC1_RX_PRIORITY, /* rxPri */
110 FEC1_TX_PRIORITY, /* txPri */
111 FEC1_RX_INIT, /* rxInit */
112 FEC1_TX_INIT, /* txInit */
113 0, /* usedTbdIndex */
114 0, /* cleanTbdNum */
115 }
116 #endif
117 };
118
119 static int fec_send(struct eth_device *dev, volatile void *packet, int length);
120 static int fec_recv(struct eth_device *dev);
121 static int fec_init(struct eth_device *dev, bd_t * bd);
122 static void fec_halt(struct eth_device *dev);
123
124 #ifdef ET_DEBUG
dbg_fec_regs(struct eth_device * dev)125 static void dbg_fec_regs(struct eth_device *dev)
126 {
127 struct fec_info_dma *info = dev->priv;
128 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
129
130 printf("=====\n");
131 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
132 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
133 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
134 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
135 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
136 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
137 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
138 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
139 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
140 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
141 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
142 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
143 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
144 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
145 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
146 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
147 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
148 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
149 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
150 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
151 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
152 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
153 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
154 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
155 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
156 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
157 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
158 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
159 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
160 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
161 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
162 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
163 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
164 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
165 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
166 }
167 #endif
168
set_fec_duplex_speed(volatile fecdma_t * fecp,bd_t * bd,int dup_spd)169 static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
170 int dup_spd)
171 {
172 if ((dup_spd >> 16) == FULL) {
173 /* Set maximum frame length */
174 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
175 FEC_RCR_PROM | 0x100;
176 fecp->tcr = FEC_TCR_FDEN;
177 } else {
178 /* Half duplex mode */
179 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
180 FEC_RCR_MII_MODE | FEC_RCR_DRT;
181 fecp->tcr &= ~FEC_TCR_FDEN;
182 }
183
184 if ((dup_spd & 0xFFFF) == _100BASET) {
185 #ifdef MII_DEBUG
186 printf("100Mbps\n");
187 #endif
188 bd->bi_ethspeed = 100;
189 } else {
190 #ifdef MII_DEBUG
191 printf("10Mbps\n");
192 #endif
193 bd->bi_ethspeed = 10;
194 }
195 }
196
fec_send(struct eth_device * dev,volatile void * packet,int length)197 static int fec_send(struct eth_device *dev, volatile void *packet, int length)
198 {
199 struct fec_info_dma *info = dev->priv;
200 cbd_t *pTbd, *pUsedTbd;
201 u16 phyStatus;
202
203 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
204
205 /* process all the consumed TBDs */
206 while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
207 pUsedTbd = &info->txbd[info->usedTbdIdx];
208 if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
209 #ifdef ET_DEBUG
210 printf("Cannot clean TBD %d, in use\n",
211 info->cleanTbdNum);
212 #endif
213 return 0;
214 }
215
216 /* clean this buffer descriptor */
217 if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
218 pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
219 else
220 pUsedTbd->cbd_sc = 0;
221
222 /* update some indeces for a correct handling of the TBD ring */
223 info->cleanTbdNum++;
224 info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
225 }
226
227 /* Check for valid length of data. */
228 if ((length > 1500) || (length <= 0)) {
229 return -1;
230 }
231
232 /* Check the number of vacant TxBDs. */
233 if (info->cleanTbdNum < 1) {
234 printf("No available TxBDs ...\n");
235 return -1;
236 }
237
238 /* Get the first TxBD to send the mac header */
239 pTbd = &info->txbd[info->txIdx];
240 pTbd->cbd_datlen = length;
241 pTbd->cbd_bufaddr = (u32) packet;
242 pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
243 info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
244
245 /* Enable DMA transmit task */
246 MCD_continDma(info->txTask);
247
248 info->cleanTbdNum -= 1;
249
250 /* wait until frame is sent . */
251 while (pTbd->cbd_sc & BD_ENET_TX_READY) {
252 udelay(10);
253 }
254
255 return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
256 }
257
fec_recv(struct eth_device * dev)258 static int fec_recv(struct eth_device *dev)
259 {
260 struct fec_info_dma *info = dev->priv;
261 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
262
263 cbd_t *pRbd = &info->rxbd[info->rxIdx];
264 u32 ievent;
265 int frame_length, len = 0;
266
267 /* Check if any critical events have happened */
268 ievent = fecp->eir;
269 if (ievent != 0) {
270 fecp->eir = ievent;
271
272 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
273 printf("fec_recv: error\n");
274 fec_halt(dev);
275 fec_init(dev, NULL);
276 return 0;
277 }
278
279 if (ievent & FEC_EIR_HBERR) {
280 /* Heartbeat error */
281 fecp->tcr |= FEC_TCR_GTS;
282 }
283
284 if (ievent & FEC_EIR_GRA) {
285 /* Graceful stop complete */
286 if (fecp->tcr & FEC_TCR_GTS) {
287 printf("fec_recv: tcr_gts\n");
288 fec_halt(dev);
289 fecp->tcr &= ~FEC_TCR_GTS;
290 fec_init(dev, NULL);
291 }
292 }
293 }
294
295 if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) {
296 if ((pRbd->cbd_sc & BD_ENET_RX_LAST)
297 && !(pRbd->cbd_sc & BD_ENET_RX_ERR)
298 && ((pRbd->cbd_datlen - 4) > 14)) {
299
300 /* Get buffer address and size */
301 frame_length = pRbd->cbd_datlen - 4;
302
303 /* Fill the buffer and pass it to upper layers */
304 NetReceive((volatile uchar *)pRbd->cbd_bufaddr,
305 frame_length);
306 len = frame_length;
307 }
308
309 /* Reset buffer descriptor as empty */
310 if ((info->rxIdx) == (PKTBUFSRX - 1))
311 pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
312 else
313 pRbd->cbd_sc = BD_ENET_RX_EMPTY;
314
315 pRbd->cbd_datlen = PKTSIZE_ALIGN;
316
317 /* Now, we have an empty RxBD, restart the DMA receive task */
318 MCD_continDma(info->rxTask);
319
320 /* Increment BD count */
321 info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
322 }
323
324 return len;
325 }
326
fec_set_hwaddr(volatile fecdma_t * fecp,u8 * mac)327 static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
328 {
329 u8 currByte; /* byte for which to compute the CRC */
330 int byte; /* loop - counter */
331 int bit; /* loop - counter */
332 u32 crc = 0xffffffff; /* initial value */
333
334 for (byte = 0; byte < 6; byte++) {
335 currByte = mac[byte];
336 for (bit = 0; bit < 8; bit++) {
337 if ((currByte & 0x01) ^ (crc & 0x01)) {
338 crc >>= 1;
339 crc = crc ^ 0xedb88320;
340 } else {
341 crc >>= 1;
342 }
343 currByte >>= 1;
344 }
345 }
346
347 crc = crc >> 26;
348
349 /* Set individual hash table register */
350 if (crc >= 32) {
351 fecp->ialr = (1 << (crc - 32));
352 fecp->iaur = 0;
353 } else {
354 fecp->ialr = 0;
355 fecp->iaur = (1 << crc);
356 }
357
358 /* Set physical address */
359 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
360 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
361
362 /* Clear multicast address hash table */
363 fecp->gaur = 0;
364 fecp->galr = 0;
365 }
366
fec_init(struct eth_device * dev,bd_t * bd)367 static int fec_init(struct eth_device *dev, bd_t * bd)
368 {
369 struct fec_info_dma *info = dev->priv;
370 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
371 int i;
372 uchar enetaddr[6];
373
374 #ifdef ET_DEBUG
375 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
376 #endif
377
378 fecpin_setclear(dev, 1);
379
380 fec_halt(dev);
381
382 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
383 defined (CONFIG_SYS_DISCOVER_PHY)
384
385 mii_init();
386
387 set_fec_duplex_speed(fecp, bd, info->dup_spd);
388 #else
389 #ifndef CONFIG_SYS_DISCOVER_PHY
390 set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
391 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
392 #endif /* CONFIG_CMD_MII || CONFIG_MII */
393
394 /* We use strictly polling mode only */
395 fecp->eimr = 0;
396
397 /* Clear any pending interrupt */
398 fecp->eir = 0xffffffff;
399
400 /* Set station address */
401 if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
402 eth_getenv_enetaddr("ethaddr", enetaddr);
403 else
404 eth_getenv_enetaddr("eth1addr", enetaddr);
405 fec_set_hwaddr(fecp, enetaddr);
406
407 /* Set Opcode/Pause Duration Register */
408 fecp->opd = 0x00010020;
409
410 /* Setup Buffers and Buffer Desriptors */
411 info->rxIdx = 0;
412 info->txIdx = 0;
413
414 /* Setup Receiver Buffer Descriptors (13.14.24.18)
415 * Settings: Empty, Wrap */
416 for (i = 0; i < PKTBUFSRX; i++) {
417 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
418 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
419 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
420 }
421 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
422
423 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
424 * Settings: Last, Tx CRC */
425 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
426 info->txbd[i].cbd_sc = 0;
427 info->txbd[i].cbd_datlen = 0;
428 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
429 }
430 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
431
432 info->usedTbdIdx = 0;
433 info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
434
435 /* Set Rx FIFO alarm and granularity value */
436 fecp->rfcr = 0x0c000000;
437 fecp->rfar = 0x0000030c;
438
439 /* Set Tx FIFO granularity value */
440 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
441 fecp->tfar = 0x00000080;
442
443 fecp->tfwr = 0x2;
444 fecp->ctcwr = 0x03000000;
445
446 /* Enable DMA receive task */
447 MCD_startDma(info->rxTask, /* Dma channel */
448 (s8 *) info->rxbd, /*Source Address */
449 0, /* Source increment */
450 (s8 *) (&fecp->rfdr), /* dest */
451 4, /* dest increment */
452 0, /* DMA size */
453 4, /* xfer size */
454 info->rxInit, /* initiator */
455 info->rxPri, /* priority */
456 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
457 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
458 );
459
460 /* Enable DMA tx task with no ready buffer descriptors */
461 MCD_startDma(info->txTask, /* Dma channel */
462 (s8 *) info->txbd, /*Source Address */
463 0, /* Source increment */
464 (s8 *) (&fecp->tfdr), /* dest */
465 4, /* dest incr */
466 0, /* DMA size */
467 4, /* xfer size */
468 info->txInit, /* initiator */
469 info->txPri, /* priority */
470 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
471 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
472 );
473
474 /* Now enable the transmit and receive processing */
475 fecp->ecr |= FEC_ECR_ETHER_EN;
476
477 return 1;
478 }
479
fec_halt(struct eth_device * dev)480 static void fec_halt(struct eth_device *dev)
481 {
482 struct fec_info_dma *info = dev->priv;
483 volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
484 int counter = 0xffff;
485
486 /* issue graceful stop command to the FEC transmitter if necessary */
487 fecp->tcr |= FEC_TCR_GTS;
488
489 /* wait for graceful stop to register */
490 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
491
492 /* Disable DMA tasks */
493 MCD_killDma(info->txTask);
494 MCD_killDma(info->rxTask);;
495
496 /* Disable the Ethernet Controller */
497 fecp->ecr &= ~FEC_ECR_ETHER_EN;
498
499 /* Clear FIFO status registers */
500 fecp->rfsr &= FIFO_ERRSTAT;
501 fecp->tfsr &= FIFO_ERRSTAT;
502
503 fecp->frst = 0x01000000;
504
505 /* Issue a reset command to the FEC chip */
506 fecp->ecr |= FEC_ECR_RESET;
507
508 /* wait at least 20 clock cycles */
509 udelay(10000);
510
511 #ifdef ET_DEBUG
512 printf("Ethernet task stopped\n");
513 #endif
514 }
515
mcdmafec_initialize(bd_t * bis)516 int mcdmafec_initialize(bd_t * bis)
517 {
518 struct eth_device *dev;
519 int i;
520 #ifdef CONFIG_SYS_DMA_USE_INTSRAM
521 u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
522 #endif
523
524 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
525
526 dev =
527 (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
528 sizeof *dev);
529 if (dev == NULL)
530 hang();
531
532 memset(dev, 0, sizeof(*dev));
533
534 sprintf(dev->name, "FEC%d", fec_info[i].index);
535
536 dev->priv = &fec_info[i];
537 dev->init = fec_init;
538 dev->halt = fec_halt;
539 dev->send = fec_send;
540 dev->recv = fec_recv;
541
542 /* setup Receive and Transmit buffer descriptor */
543 #ifdef CONFIG_SYS_DMA_USE_INTSRAM
544 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
545 tmp = (u32)fec_info[i].rxbd;
546 fec_info[i].txbd =
547 (cbd_t *)((u32)fec_info[i].txbd + tmp +
548 (PKTBUFSRX * sizeof(cbd_t)));
549 tmp = (u32)fec_info[i].txbd;
550 fec_info[i].txbuf =
551 (char *)((u32)fec_info[i].txbuf + tmp +
552 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
553 tmp = (u32)fec_info[i].txbuf;
554 #else
555 fec_info[i].rxbd =
556 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
557 (PKTBUFSRX * sizeof(cbd_t)));
558 fec_info[i].txbd =
559 (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
560 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
561 fec_info[i].txbuf =
562 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
563 #endif
564
565 #ifdef ET_DEBUG
566 printf("rxbd %x txbd %x\n",
567 (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
568 #endif
569
570 fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
571
572 eth_register(dev);
573
574 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
575 miiphy_register(dev->name,
576 mcffec_miiphy_read, mcffec_miiphy_write);
577 #endif
578
579 if (i > 0)
580 fec_info[i - 1].next = &fec_info[i];
581 }
582 fec_info[i - 1].next = &fec_info[0];
583
584 /* default speed */
585 bis->bi_ethspeed = 10;
586
587 return 0;
588 }
589