1 /*
2 * Driver for AT91/AT32 LCD Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25 #include <common.h>
26 #include <asm/io.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/clk.h>
29 #include <lcd.h>
30 #include <atmel_lcdc.h>
31
32 int lcd_line_length;
33 int lcd_color_fg;
34 int lcd_color_bg;
35
36 void *lcd_base; /* Start of framebuffer memory */
37 void *lcd_console_address; /* Start of console buffer */
38
39 short console_col;
40 short console_row;
41
42 /* configurable parameters */
43 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
44 #define ATMEL_LCDC_DMA_BURST_LEN 8
45 #ifndef ATMEL_LCDC_GUARD_TIME
46 #define ATMEL_LCDC_GUARD_TIME 1
47 #endif
48
49 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9)
50 #define ATMEL_LCDC_FIFO_SIZE 2048
51 #else
52 #define ATMEL_LCDC_FIFO_SIZE 512
53 #endif
54
55 #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
56 #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
57
lcd_setcolreg(ushort regno,ushort red,ushort green,ushort blue)58 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
59 {
60 #if defined(CONFIG_ATMEL_LCD_BGR555)
61 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
62 (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
63 #else
64 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
65 (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
66 #endif
67 }
68
lcd_ctrl_init(void * lcdbase)69 void lcd_ctrl_init(void *lcdbase)
70 {
71 unsigned long value;
72
73 /* Turn off the LCD controller and the DMA controller */
74 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
75 ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
76
77 /* Wait for the LCDC core to become idle */
78 while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
79 udelay(10);
80
81 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
82
83 /* Reset LCDC DMA */
84 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
85
86 /* ...set frame size and burst length = 8 words (?) */
87 value = (panel_info.vl_col * panel_info.vl_row *
88 NBITS(panel_info.vl_bpix)) / 32;
89 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
90 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
91
92 /* Set pixel clock */
93 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
94 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
95 value++;
96 value = (value / 2) - 1;
97
98 if (!value) {
99 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
100 } else
101 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
102 value << ATMEL_LCDC_CLKVAL_OFFSET);
103
104 /* Initialize control register 2 */
105 #ifdef CONFIG_AVR32
106 value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
107 #else
108 value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
109 #endif
110 if (panel_info.vl_tft)
111 value |= ATMEL_LCDC_DISTYPE_TFT;
112
113 value |= panel_info.vl_sync;
114 value |= (panel_info.vl_bpix << 5);
115 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
116
117 /* Vertical timing */
118 value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
119 value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
120 value |= panel_info.vl_lower_margin;
121 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
122
123 /* Horizontal timing */
124 value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
125 value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
126 value |= (panel_info.vl_left_margin - 1);
127 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
128
129 /* Display size */
130 value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
131 value |= panel_info.vl_row - 1;
132 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
133
134 /* FIFO Threshold: Use formula from data sheet */
135 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
136 lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
137
138 /* Toggle LCD_MODE every frame */
139 lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
140
141 /* Disable all interrupts */
142 lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
143
144 /* Set contrast */
145 value = ATMEL_LCDC_PS_DIV8 |
146 ATMEL_LCDC_POL_POSITIVE |
147 ATMEL_LCDC_ENA_PWMENABLE;
148 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
149 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
150
151 /* Set framebuffer DMA base address and pixel offset */
152 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
153
154 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
155 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
156 (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
157 }
158
calc_fbsize(void)159 ulong calc_fbsize(void)
160 {
161 return ((panel_info.vl_col * panel_info.vl_row *
162 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
163 }
164