1 /* 2 * (C) Copyright 2001-2004 3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */ 37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38 #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ 39 #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ 40 41 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 42 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 43 44 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ 45 46 #define CONFIG_BAUDRATE 9600 47 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 48 49 #undef CONFIG_BOOTARGS 50 #undef CONFIG_BOOTCOMMAND 51 52 #define CONFIG_PREBOOT /* enable preboot variable */ 53 54 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 55 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 56 57 #define CONFIG_PPC4xx_EMAC 58 #define CONFIG_MII 1 /* MII PHY management */ 59 #define CONFIG_PHY_ADDR 0 /* PHY address */ 60 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 61 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ 62 63 #define CONFIG_NET_MULTI 1 64 #undef CONFIG_HAS_ETH1 65 66 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ 67 68 /* 69 * BOOTP options 70 */ 71 #define CONFIG_BOOTP_SUBNETMASK 72 #define CONFIG_BOOTP_GATEWAY 73 #define CONFIG_BOOTP_HOSTNAME 74 #define CONFIG_BOOTP_BOOTPATH 75 #define CONFIG_BOOTP_DNS 76 #define CONFIG_BOOTP_DNS2 77 #define CONFIG_BOOTP_SEND_HOSTNAME 78 79 80 /* 81 * Command line configuration. 82 */ 83 #include <config_cmd_default.h> 84 85 #define CONFIG_CMD_DHCP 86 #define CONFIG_CMD_PCI 87 #define CONFIG_CMD_IRQ 88 #define CONFIG_CMD_IDE 89 #define CONFIG_CMD_FAT 90 #define CONFIG_CMD_ELF 91 #define CONFIG_CMD_DATE 92 #define CONFIG_CMD_I2C 93 #define CONFIG_CMD_MII 94 #define CONFIG_CMD_PING 95 #define CONFIG_CMD_BSP 96 #define CONFIG_CMD_EEPROM 97 98 #define CONFIG_MAC_PARTITION 99 #define CONFIG_DOS_PARTITION 100 101 #define CONFIG_SUPPORT_VFAT 102 103 #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ 104 105 #undef CONFIG_WATCHDOG /* watchdog disabled */ 106 107 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 108 109 /* 110 * Miscellaneous configurable options 111 */ 112 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 113 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 114 115 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 116 #ifdef CONFIG_SYS_HUSH_PARSER 117 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 118 #endif 119 120 #if defined(CONFIG_CMD_KGDB) 121 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 122 #else 123 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 124 #endif 125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 126 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 128 129 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 130 131 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 132 133 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 134 135 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 136 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 137 138 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 139 #define CONFIG_SYS_BASE_BAUD 691200 140 141 /* The following table includes the supported baudrates */ 142 #define CONFIG_SYS_BAUDRATE_TABLE \ 143 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 144 57600, 115200, 230400, 460800, 921600 } 145 146 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 147 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 148 149 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 150 151 #define CONFIG_LOOPW 1 /* enable loopw command */ 152 153 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 154 155 /* Only interrupt boot if special string is typed */ 156 #define CONFIG_AUTOBOOT_KEYED 1 157 #define CONFIG_AUTOBOOT_PROMPT \ 158 "Autobooting in %d seconds\n", bootdelay 159 #undef CONFIG_AUTOBOOT_DELAY_STR 160 #undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ 161 #define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ 162 163 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 164 165 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ 166 167 /*----------------------------------------------------------------------- 168 * PCI stuff 169 *----------------------------------------------------------------------- 170 */ 171 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 172 #define PCI_HOST_FORCE 1 /* configure as pci host */ 173 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 174 175 #define CONFIG_PCI /* include pci support */ 176 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ 177 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 178 /* resource configuration */ 179 180 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 181 182 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ 183 184 #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ 185 186 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 187 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ 188 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ 189 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ 190 #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ 191 #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ 192 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 193 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ 194 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ 195 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 196 197 #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ 198 199 /*----------------------------------------------------------------------- 200 * IDE/ATA stuff 201 *----------------------------------------------------------------------- 202 */ 203 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 204 #undef CONFIG_IDE_LED /* no led for ide supported */ 205 #define CONFIG_IDE_RESET 1 /* reset for ide supported */ 206 207 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ 208 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ 209 210 #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 211 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 212 213 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ 214 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ 215 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ 216 217 /*----------------------------------------------------------------------- 218 * Start addresses for the final memory configuration 219 * (Set up by the startup code) 220 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 221 */ 222 #define CONFIG_SYS_SDRAM_BASE 0x00000000 223 #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 225 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 226 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 227 228 /* 229 * For booting Linux, the board info and command line data 230 * have to be in the first 8 MB of memory, since this is 231 * the maximum mapped by the Linux kernel during initialization. 232 */ 233 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 234 /*----------------------------------------------------------------------- 235 * FLASH organization 236 */ 237 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 238 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 239 240 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 242 243 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 244 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 245 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 246 /* 247 * The following defines are added for buggy IOP480 byte interface. 248 * All other boards should use the standard values (CPCI405 etc.) 249 */ 250 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 251 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 252 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 253 254 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 255 256 #if 0 /* Use NVRAM for environment variables */ 257 /*----------------------------------------------------------------------- 258 * NVRAM organization 259 */ 260 #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ 261 #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ 262 #define CONFIG_ENV_ADDR \ 263 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ 264 265 #else /* Use EEPROM for environment variables */ 266 267 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 268 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 269 #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ 270 /* total size of a CAT24WC16 is 2048 bytes */ 271 #endif 272 273 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ 274 #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ 275 #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ 276 277 /*----------------------------------------------------------------------- 278 * I2C EEPROM (CAT24WC16) for environment 279 */ 280 #define CONFIG_HARD_I2C /* I2c with hardware support */ 281 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 282 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 283 #define CONFIG_SYS_I2C_SLAVE 0x7F 284 285 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 286 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 287 /* mask of address bits that overflow into the "EEPROM chip address" */ 288 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 289 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 290 /* 16 byte page write mode using*/ 291 /* last 4 bits of the address */ 292 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 293 294 /* 295 * Init Memory Controller: 296 * 297 * BR0/1 and OR0/1 (FLASH) 298 */ 299 300 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ 301 #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ 302 303 /*----------------------------------------------------------------------- 304 * External Bus Controller (EBC) Setup 305 */ 306 307 /* Memory Bank 0 (Flash Bank 0) initialization */ 308 #define CONFIG_SYS_EBC_PB0AP 0x92015480 309 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 310 311 /* Memory Bank 1 (Flash Bank 1) initialization */ 312 #define CONFIG_SYS_EBC_PB1AP 0x92015480 313 #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ 314 315 /* Memory Bank 2 (CAN0, 1) initialization */ 316 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 317 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 318 #define CONFIG_SYS_LED_ADDR 0xF0000380 319 320 /* Memory Bank 3 (CompactFlash IDE) initialization */ 321 #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 322 #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ 323 324 /* Memory Bank 4 (NVRAM/RTC) initialization */ 325 /*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ 326 #define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ 327 #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ 328 329 /* Memory Bank 5 (optional Quart) initialization */ 330 #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ 331 #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ 332 333 /* Memory Bank 6 (FPGA internal) initialization */ 334 #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 335 #define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ 336 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 337 338 /*----------------------------------------------------------------------- 339 * FPGA stuff 340 */ 341 /* FPGA internal regs */ 342 #define CONFIG_SYS_FPGA_MODE 0x00 343 #define CONFIG_SYS_FPGA_STATUS 0x02 344 #define CONFIG_SYS_FPGA_TS 0x04 345 #define CONFIG_SYS_FPGA_TS_LOW 0x06 346 #define CONFIG_SYS_FPGA_TS_CAP0 0x10 347 #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 348 #define CONFIG_SYS_FPGA_TS_CAP1 0x14 349 #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 350 #define CONFIG_SYS_FPGA_TS_CAP2 0x18 351 #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a 352 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c 353 #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e 354 355 /* FPGA Mode Reg */ 356 #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 357 #define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 358 #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ 359 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 360 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 361 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 362 363 /* FPGA Status Reg */ 364 #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 365 #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 366 #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 367 #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 368 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 369 370 #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ 371 #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ 372 373 /* FPGA program pin configuration */ 374 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ 375 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ 376 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ 377 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ 378 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ 379 380 /*----------------------------------------------------------------------- 381 * Definitions for initial stack pointer and data area (in data cache) 382 */ 383 #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ 384 385 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ 386 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ 387 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 388 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 389 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 390 391 /* 392 * Internal Definitions 393 * 394 * Boot Flags 395 */ 396 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 397 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 398 399 #endif /* __CONFIG_H */ 400