1 /* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 37 #define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ 38 39 #ifdef CONFIG_LCD /* with LCD controller ? */ 40 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ 41 #endif 42 43 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 44 #define CONFIG_SYS_SMC_RXBUFLEN 128 45 #define CONFIG_SYS_MAXIDLE 10 46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 47 48 #define CONFIG_BOOTCOUNT_LIMIT 49 50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 51 52 #define CONFIG_BOARD_TYPES 1 /* support board types */ 53 54 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 55 56 #undef CONFIG_BOOTARGS 57 58 #define CONFIG_EXTRA_ENV_SETTINGS \ 59 "netdev=eth0\0" \ 60 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 61 "nfsroot=${serverip}:${rootpath}\0" \ 62 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 63 "addip=setenv bootargs ${bootargs} " \ 64 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 65 ":${hostname}:${netdev}:off panic=1\0" \ 66 "flash_nfs=run nfsargs addip;" \ 67 "bootm ${kernel_addr}\0" \ 68 "flash_self=run ramargs addip;" \ 69 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 70 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 71 "rootpath=/opt/eldk/ppc_8xx\0" \ 72 "hostname=TQM823M\0" \ 73 "bootfile=TQM823M/uImage\0" \ 74 "fdt_addr=40080000\0" \ 75 "kernel_addr=400A0000\0" \ 76 "ramdisk_addr=40280000\0" \ 77 "u-boot=TQM823M/u-image.bin\0" \ 78 "load=tftp 200000 ${u-boot}\0" \ 79 "update=prot off 40000000 +${filesize};" \ 80 "era 40000000 +${filesize};" \ 81 "cp.b 200000 40000000 ${filesize};" \ 82 "sete filesize;save\0" \ 83 "" 84 #define CONFIG_BOOTCOMMAND "run flash_self" 85 86 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 87 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 88 89 #undef CONFIG_WATCHDOG /* watchdog disabled */ 90 91 #ifdef CONFIG_LCD 92 # undef CONFIG_STATUS_LED /* disturbs display */ 93 #else 94 # define CONFIG_STATUS_LED 1 /* Status LED enabled */ 95 #endif /* CONFIG_LCD */ 96 97 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 98 99 /* 100 * BOOTP options 101 */ 102 #define CONFIG_BOOTP_SUBNETMASK 103 #define CONFIG_BOOTP_GATEWAY 104 #define CONFIG_BOOTP_HOSTNAME 105 #define CONFIG_BOOTP_BOOTPATH 106 #define CONFIG_BOOTP_BOOTFILESIZE 107 108 109 #define CONFIG_MAC_PARTITION 110 #define CONFIG_DOS_PARTITION 111 112 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 113 114 115 /* 116 * Command line configuration. 117 */ 118 #include <config_cmd_default.h> 119 120 #define CONFIG_CMD_ASKENV 121 #define CONFIG_CMD_DATE 122 #define CONFIG_CMD_DHCP 123 #define CONFIG_CMD_ELF 124 #define CONFIG_CMD_EXT2 125 #define CONFIG_CMD_IDE 126 #define CONFIG_CMD_JFFS2 127 #define CONFIG_CMD_NFS 128 #define CONFIG_CMD_SNTP 129 130 131 #define CONFIG_NETCONSOLE 132 133 134 /* 135 * Miscellaneous configurable options 136 */ 137 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 138 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 139 140 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 141 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 142 #ifdef CONFIG_SYS_HUSH_PARSER 143 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 144 #endif 145 146 #if defined(CONFIG_CMD_KGDB) 147 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 148 #else 149 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 150 #endif 151 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 152 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 153 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 154 155 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 156 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 157 158 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 159 160 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 161 162 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 163 164 /* 165 * Low Level Configuration Settings 166 * (address mappings, register initial values, etc.) 167 * You should know what you are doing if you make changes here. 168 */ 169 /*----------------------------------------------------------------------- 170 * Internal Memory Mapped Register 171 */ 172 #define CONFIG_SYS_IMMR 0xFFF00000 173 174 /*----------------------------------------------------------------------- 175 * Definitions for initial stack pointer and data area (in DPRAM) 176 */ 177 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 178 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 179 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 180 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 181 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 182 183 /*----------------------------------------------------------------------- 184 * Start addresses for the final memory configuration 185 * (Set up by the startup code) 186 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 187 */ 188 #define CONFIG_SYS_SDRAM_BASE 0x00000000 189 #define CONFIG_SYS_FLASH_BASE 0x40000000 190 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 192 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 193 194 /* 195 * For booting Linux, the board info and command line data 196 * have to be in the first 8 MB of memory, since this is 197 * the maximum mapped by the Linux kernel during initialization. 198 */ 199 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 200 201 /*----------------------------------------------------------------------- 202 * FLASH organization 203 */ 204 205 /* use CFI flash driver */ 206 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 207 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 208 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 209 #define CONFIG_SYS_FLASH_EMPTY_INFO 210 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 212 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 213 214 #define CONFIG_ENV_IS_IN_FLASH 1 215 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 216 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 217 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 218 219 /* Address and size of Redundant Environment Sector */ 220 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 221 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 222 223 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 224 225 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 226 227 /*----------------------------------------------------------------------- 228 * Dynamic MTD partition support 229 */ 230 #define CONFIG_CMD_MTDPARTS 231 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 232 #define CONFIG_FLASH_CFI_MTD 233 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 234 235 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 236 "128k(dtb)," \ 237 "1920k(kernel)," \ 238 "5632(rootfs)," \ 239 "4m(data)" 240 241 /*----------------------------------------------------------------------- 242 * Hardware Information Block 243 */ 244 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 245 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 246 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 247 248 /*----------------------------------------------------------------------- 249 * Cache Configuration 250 */ 251 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 252 #if defined(CONFIG_CMD_KGDB) 253 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 254 #endif 255 256 /*----------------------------------------------------------------------- 257 * SYPCR - System Protection Control 11-9 258 * SYPCR can only be written once after reset! 259 *----------------------------------------------------------------------- 260 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 261 */ 262 #if defined(CONFIG_WATCHDOG) 263 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 264 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 265 #else 266 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 267 #endif 268 269 /*----------------------------------------------------------------------- 270 * SIUMCR - SIU Module Configuration 11-6 271 *----------------------------------------------------------------------- 272 * PCMCIA config., multi-function pin tri-state 273 */ 274 #ifndef CONFIG_CAN_DRIVER 275 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 276 #else /* we must activate GPL5 in the SIUMCR for CAN */ 277 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 278 #endif /* CONFIG_CAN_DRIVER */ 279 280 /*----------------------------------------------------------------------- 281 * TBSCR - Time Base Status and Control 11-26 282 *----------------------------------------------------------------------- 283 * Clear Reference Interrupt Status, Timebase freezing enabled 284 */ 285 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 286 287 /*----------------------------------------------------------------------- 288 * RTCSC - Real-Time Clock Status and Control Register 11-27 289 *----------------------------------------------------------------------- 290 */ 291 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 292 293 /*----------------------------------------------------------------------- 294 * PISCR - Periodic Interrupt Status and Control 11-31 295 *----------------------------------------------------------------------- 296 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 297 */ 298 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 299 300 /*----------------------------------------------------------------------- 301 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 302 *----------------------------------------------------------------------- 303 * Reset PLL lock status sticky bit, timer expired status bit and timer 304 * interrupt status bit 305 */ 306 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 307 308 /*----------------------------------------------------------------------- 309 * SCCR - System Clock and reset Control Register 15-27 310 *----------------------------------------------------------------------- 311 * Set clock output, timebase and RTC source and divider, 312 * power management and some other internal clocks 313 */ 314 #define SCCR_MASK SCCR_EBDF11 315 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 316 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 317 SCCR_DFALCD00) 318 319 /*----------------------------------------------------------------------- 320 * PCMCIA stuff 321 *----------------------------------------------------------------------- 322 * 323 */ 324 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 325 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 326 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 327 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 328 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 329 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 330 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 331 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 332 333 /*----------------------------------------------------------------------- 334 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 335 *----------------------------------------------------------------------- 336 */ 337 338 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 339 340 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 341 #undef CONFIG_IDE_LED /* LED for ide not supported */ 342 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 343 344 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 345 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 346 347 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 348 349 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 350 351 /* Offset for data I/O */ 352 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 353 354 /* Offset for normal register accesses */ 355 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 356 357 /* Offset for alternate registers */ 358 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 359 360 /*----------------------------------------------------------------------- 361 * 362 *----------------------------------------------------------------------- 363 * 364 */ 365 #define CONFIG_SYS_DER 0 366 367 /* 368 * Init Memory Controller: 369 * 370 * BR0/1 and OR0/1 (FLASH) 371 */ 372 373 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 374 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 375 376 /* used to re-map FLASH both when starting from SRAM or FLASH: 377 * restrict access enough to keep SRAM working (if any) 378 * but not too much to meddle with FLASH accesses 379 */ 380 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 381 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 382 383 /* 384 * FLASH timing: 385 */ 386 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 387 OR_SCY_3_CLK | OR_EHTR | OR_BI) 388 389 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 390 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 391 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 392 393 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 394 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 395 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 396 397 /* 398 * BR2/3 and OR2/3 (SDRAM) 399 * 400 */ 401 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 402 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 403 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 404 405 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 406 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 407 408 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 409 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 410 411 #ifndef CONFIG_CAN_DRIVER 412 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 413 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 414 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 415 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 416 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 417 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 418 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 419 BR_PS_8 | BR_MS_UPMB | BR_V ) 420 #endif /* CONFIG_CAN_DRIVER */ 421 422 /* 423 * Memory Periodic Timer Prescaler 424 * 425 * The Divider for PTA (refresh timer) configuration is based on an 426 * example SDRAM configuration (64 MBit, one bank). The adjustment to 427 * the number of chip selects (NCS) and the actually needed refresh 428 * rate is done by setting MPTPR. 429 * 430 * PTA is calculated from 431 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 432 * 433 * gclk CPU clock (not bus clock!) 434 * Trefresh Refresh cycle * 4 (four word bursts used) 435 * 436 * 4096 Rows from SDRAM example configuration 437 * 1000 factor s -> ms 438 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 439 * 4 Number of refresh cycles per period 440 * 64 Refresh cycle in ms per number of rows 441 * -------------------------------------------- 442 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 443 * 444 * 50 MHz => 50.000.000 / Divider = 98 445 * 66 Mhz => 66.000.000 / Divider = 129 446 * 80 Mhz => 80.000.000 / Divider = 156 447 */ 448 449 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 450 #define CONFIG_SYS_MAMR_PTA 98 451 452 /* 453 * For 16 MBit, refresh rates could be 31.3 us 454 * (= 64 ms / 2K = 125 / quad bursts). 455 * For a simpler initialization, 15.6 us is used instead. 456 * 457 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 458 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 459 */ 460 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 461 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 462 463 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 464 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 465 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 466 467 /* 468 * MAMR settings for SDRAM 469 */ 470 471 /* 8 column SDRAM */ 472 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 473 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 475 /* 9 column SDRAM */ 476 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 477 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 478 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 479 480 481 /* 482 * Internal Definitions 483 * 484 * Boot Flags 485 */ 486 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 487 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 488 489 /* pass open firmware flat tree */ 490 #define CONFIG_OF_LIBFDT 1 491 #define CONFIG_OF_BOARD_SETUP 1 492 #define CONFIG_HWCONFIG 1 493 494 #endif /* __CONFIG_H */ 495