1 /* 2 * Copyright (c) 2005 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2006 5 * Alex Bounine , Tundra Semiconductor Corp. 6 * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * board specific configuration options for Freescale 29 * MPC7448HPC2 (High-Performance Computing II) (Taiga) board 30 * 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* Board Configuration Definitions */ 37 /* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */ 38 39 #define CONFIG_MPC7448HPC2 40 41 #define CONFIG_74xx 42 #define CONFIG_HIGH_BATS /* High BATs supported */ 43 #define CONFIG_ALTIVEC /* undef to disable */ 44 45 #define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II" 46 #define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" 47 48 #define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */ 49 #define CONFIG_SYS_CONFIG_BUS_CLK 133000000 50 51 #define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ 52 53 #undef CONFIG_ECC /* disable ECC support */ 54 55 /* Board-specific Initialization Functions to be called */ 56 #define CONFIG_SYS_BOARD_ASM_INIT 57 #define CONFIG_BOARD_EARLY_INIT_F 58 #define CONFIG_BOARD_EARLY_INIT_R 59 #define CONFIG_MISC_INIT_R 60 61 #define CONFIG_HAS_ETH0 62 #define CONFIG_HAS_ETH1 63 64 #define CONFIG_ENV_OVERWRITE 65 66 /* 67 * High Level Configuration Options 68 * (easy to change) 69 */ 70 71 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ 72 73 /*#define CONFIG_SYS_HUSH_PARSER */ 74 #undef CONFIG_SYS_HUSH_PARSER 75 76 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 77 78 /* Pass open firmware flat tree */ 79 #define CONFIG_OF_LIBFDT 1 80 #define CONFIG_OF_BOARD_SETUP 1 81 82 #define OF_TSI "tsi108@c0000000" 83 #define OF_TBCLK (bd->bi_busfreq / 8) 84 #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" 85 86 /* 87 * The following defines let you select what serial you want to use 88 * for your console driver. 89 * 90 * what to do: 91 * If you have hacked a serial cable onto the second DUART channel, 92 * change the CONFIG_SYS_DUART port from 1 to 0 below. 93 * 94 */ 95 96 #define CONFIG_CONS_INDEX 1 97 #define CONFIG_SYS_NS16550 98 #define CONFIG_SYS_NS16550_SERIAL 99 #define CONFIG_SYS_NS16550_REG_SIZE 1 100 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8 101 102 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808) 103 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08) 104 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 105 106 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 107 #define CONFIG_ZERO_BOOTDELAY_CHECK 108 109 #undef CONFIG_BOOTARGS 110 /* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ 111 112 #if (CONFIG_BOOTDELAY >= 0) 113 #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ 114 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ 115 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " 116 117 #define CONFIG_BOOTARGS "console=ttyS0,115200" 118 #endif 119 120 #undef CONFIG_EXTRA_ENV_SETTINGS 121 122 #define CONFIG_SERIAL "No. 1" 123 124 /* Networking Configuration */ 125 126 #define CONFIG_TSI108_ETH 127 #define CONFIG_TSI108_ETH_NUM_PORTS 2 128 129 #define CONFIG_NET_MULTI 130 131 #define CONFIG_BOOTFILE zImage.initrd.elf 132 #define CONFIG_LOADADDR 0x400000 133 134 /*-------------------------------------------------------------------------- */ 135 136 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 137 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ 138 139 #undef CONFIG_WATCHDOG /* watchdog disabled */ 140 141 /* 142 * BOOTP options 143 */ 144 #define CONFIG_BOOTP_SUBNETMASK 145 #define CONFIG_BOOTP_GATEWAY 146 #define CONFIG_BOOTP_HOSTNAME 147 #define CONFIG_BOOTP_BOOTPATH 148 #define CONFIG_BOOTP_BOOTFILESIZE 149 150 151 /* 152 * Command line configuration. 153 */ 154 #include <config_cmd_default.h> 155 156 #define CONFIG_CMD_ASKENV 157 #define CONFIG_CMD_CACHE 158 #define CONFIG_CMD_PCI 159 #define CONFIG_CMD_I2C 160 #define CONFIG_CMD_SDRAM 161 #define CONFIG_CMD_EEPROM 162 #define CONFIG_CMD_FLASH 163 #define CONFIG_CMD_SAVEENV 164 #define CONFIG_CMD_BSP 165 #define CONFIG_CMD_DHCP 166 #define CONFIG_CMD_PING 167 #define CONFIG_CMD_DATE 168 169 170 /*set date in u-boot*/ 171 #define CONFIG_RTC_M48T35A 172 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 173 #define CONFIG_SYS_NVRAM_SIZE 0x8000 174 /* 175 * Miscellaneous configurable options 176 */ 177 #define CONFIG_VERSION_VARIABLE 1 178 #define CONFIG_TSI108_I2C 179 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ 180 181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 183 184 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 185 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 186 187 #if defined(CONFIG_CMD_KGDB) 188 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 189 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ 190 #else 191 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 192 #endif 193 194 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */ 195 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 196 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 197 198 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 199 #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ 200 201 #define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ 202 203 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 204 205 /* 206 * Low Level Configuration Settings 207 * (address mappings, register initial values, etc.) 208 * You should know what you are doing if you make changes here. 209 */ 210 211 /*----------------------------------------------------------------------- 212 * Definitions for initial stack pointer and data area 213 */ 214 215 /* 216 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS 217 * To an unused memory region. The stack will remain in cache until RAM 218 * is initialized 219 */ 220 #undef CONFIG_SYS_INIT_RAM_LOCK 221 #define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ 222 #define CONFIG_SYS_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */ 223 224 #define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for init data */ 225 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 226 227 /*----------------------------------------------------------------------- 228 * Start addresses for the final memory configuration 229 * (Set up by the startup code) 230 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 231 */ 232 233 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ 234 #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ 235 236 #define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ 237 #define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ 238 239 #define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ 240 241 #define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ 242 243 #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ 244 245 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */ 246 #define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ 247 248 #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ 249 250 #define PCI0_IO_BASE_BOOTM 0xfd000000 251 252 #define CONFIG_SYS_RESET_ADDRESS 0x3fffff00 253 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 254 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* u-boot code base */ 255 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ 256 257 /* Peripheral Device section */ 258 259 /* 260 * Resources on the Tsi108 261 */ 262 263 #define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ 264 #define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ 265 266 #define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ 267 268 #undef DISABLE_PBM 269 270 /* 271 * PCI stuff 272 * 273 */ 274 275 #define CONFIG_PCI /* include pci support */ 276 #define CONFIG_TSI108_PCI /* include tsi108 pci support */ 277 278 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 279 #define PCI_HOST_FORCE 1 /* configure as pci host */ 280 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 281 282 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 283 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 284 285 /* PCI MEMORY MAP section */ 286 287 /* PCI view of System Memory */ 288 #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 289 #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 290 #define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000 291 292 /* PCI Memory Space */ 293 #define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS) 294 #define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */ 295 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ 296 297 /* PCI I/O Space */ 298 #define CONFIG_SYS_PCI_IO_BUS 0x00000000 299 #define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ 300 301 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */ 302 303 /* PCI Config Space mapping */ 304 #define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ 305 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */ 306 307 #define CONFIG_SYS_IBAT0U 0xFE0003FF 308 #define CONFIG_SYS_IBAT0L 0xFE000002 309 310 #define CONFIG_SYS_IBAT1U 0x00007FFF 311 #define CONFIG_SYS_IBAT1L 0x00000012 312 313 #define CONFIG_SYS_IBAT2U 0x80007FFF 314 #define CONFIG_SYS_IBAT2L 0x80000022 315 316 #define CONFIG_SYS_IBAT3U 0x00000000 317 #define CONFIG_SYS_IBAT3L 0x00000000 318 319 #define CONFIG_SYS_IBAT4U 0x00000000 320 #define CONFIG_SYS_IBAT4L 0x00000000 321 322 #define CONFIG_SYS_IBAT5U 0x00000000 323 #define CONFIG_SYS_IBAT5L 0x00000000 324 325 #define CONFIG_SYS_IBAT6U 0x00000000 326 #define CONFIG_SYS_IBAT6L 0x00000000 327 328 #define CONFIG_SYS_IBAT7U 0x00000000 329 #define CONFIG_SYS_IBAT7L 0x00000000 330 331 #define CONFIG_SYS_DBAT0U 0xE0003FFF 332 #define CONFIG_SYS_DBAT0L 0xE000002A 333 334 #define CONFIG_SYS_DBAT1U 0x00007FFF 335 #define CONFIG_SYS_DBAT1L 0x00000012 336 337 #define CONFIG_SYS_DBAT2U 0x00000000 338 #define CONFIG_SYS_DBAT2L 0x00000000 339 340 #define CONFIG_SYS_DBAT3U 0xC0000003 341 #define CONFIG_SYS_DBAT3L 0xC000002A 342 343 #define CONFIG_SYS_DBAT4U 0x00000000 344 #define CONFIG_SYS_DBAT4L 0x00000000 345 346 #define CONFIG_SYS_DBAT5U 0x00000000 347 #define CONFIG_SYS_DBAT5L 0x00000000 348 349 #define CONFIG_SYS_DBAT6U 0x00000000 350 #define CONFIG_SYS_DBAT6L 0x00000000 351 352 #define CONFIG_SYS_DBAT7U 0x00000000 353 #define CONFIG_SYS_DBAT7L 0x00000000 354 355 /* I2C addresses for the two DIMM SPD chips */ 356 #define DIMM0_I2C_ADDR 0x51 357 #define DIMM1_I2C_ADDR 0x52 358 359 /* 360 * For booting Linux, the board info and command line data 361 * have to be in the first 8 MB of memory, since this is 362 * the maximum mapped by the Linux kernel during initialization. 363 */ 364 #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ 365 366 /*----------------------------------------------------------------------- 367 * FLASH organization 368 */ 369 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ 370 #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ 371 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ } 372 373 #define CONFIG_FLASH_CFI_DRIVER 374 #define CONFIG_SYS_FLASH_CFI 375 #define CONFIG_SYS_WRITE_SWAPPED_DATA 376 377 #define PHYS_FLASH_SIZE 0x01000000 378 #define CONFIG_SYS_MAX_FLASH_SECT (128) 379 380 #define CONFIG_ENV_IS_IN_NVRAM 381 #define CONFIG_ENV_ADDR 0xFC000000 382 383 #define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ 384 #define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ 385 386 /*----------------------------------------------------------------------- 387 * Cache Configuration 388 */ 389 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ 390 #if defined(CONFIG_CMD_KGDB) 391 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 392 #endif 393 394 /*----------------------------------------------------------------------- 395 * L2CR setup -- make sure this is right for your board! 396 * look in include/mpc74xx.h for the defines used here 397 */ 398 #undef CONFIG_SYS_L2 399 400 #define L2_INIT 0 401 #define L2_ENABLE (L2_INIT | L2CR_L2E) 402 403 /* 404 * Internal Definitions 405 * 406 * Boot Flags 407 */ 408 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 409 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 410 #define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION 411 #endif /* __CONFIG_H */ 412