1 #include "qemu/osdep.h"
2 #include "cpu.h"
3 #include "internal.h"
4 #include "migration/cpu.h"
5 #include "fpu_helper.h"
6 
cpu_post_load(void * opaque,int version_id)7 static int cpu_post_load(void *opaque, int version_id)
8 {
9     MIPSCPU *cpu = opaque;
10     CPUMIPSState *env = &cpu->env;
11 
12     restore_fp_status(env);
13     restore_msa_fp_status(env);
14     compute_hflags(env);
15     restore_pamask(env);
16 
17     return 0;
18 }
19 
20 /* FPU state */
21 
get_fpr(QEMUFile * f,void * pv,size_t size,const VMStateField * field)22 static int get_fpr(QEMUFile *f, void *pv, size_t size,
23                    const VMStateField *field)
24 {
25     int i;
26     fpr_t *v = pv;
27     /* Restore entire MSA vector register */
28     for (i = 0; i < MSA_WRLEN / 64; i++) {
29         qemu_get_sbe64s(f, &v->wr.d[i]);
30     }
31     return 0;
32 }
33 
put_fpr(QEMUFile * f,void * pv,size_t size,const VMStateField * field,JSONWriter * vmdesc)34 static int put_fpr(QEMUFile *f, void *pv, size_t size,
35                    const VMStateField *field, JSONWriter *vmdesc)
36 {
37     int i;
38     fpr_t *v = pv;
39     /* Save entire MSA vector register */
40     for (i = 0; i < MSA_WRLEN / 64; i++) {
41         qemu_put_sbe64s(f, &v->wr.d[i]);
42     }
43 
44     return 0;
45 }
46 
47 const VMStateInfo vmstate_info_fpr = {
48     .name = "fpr",
49     .get  = get_fpr,
50     .put  = put_fpr,
51 };
52 
53 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                     \
54     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
55 
56 #define VMSTATE_FPR_ARRAY(_f, _s, _n)                           \
57     VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
58 
59 static VMStateField vmstate_fpu_fields[] = {
60     VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
61     VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
62     VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
63     VMSTATE_END_OF_LIST()
64 };
65 
66 const VMStateDescription vmstate_fpu = {
67     .name = "cpu/fpu",
68     .version_id = 1,
69     .minimum_version_id = 1,
70     .fields = vmstate_fpu_fields
71 };
72 
73 const VMStateDescription vmstate_inactive_fpu = {
74     .name = "cpu/inactive_fpu",
75     .version_id = 1,
76     .minimum_version_id = 1,
77     .fields = vmstate_fpu_fields
78 };
79 
80 /* TC state */
81 
82 static VMStateField vmstate_tc_fields[] = {
83     VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
84     VMSTATE_UINTTL(PC, TCState),
85     VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
86     VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
87     VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
88     VMSTATE_UINTTL(DSPControl, TCState),
89     VMSTATE_INT32(CP0_TCStatus, TCState),
90     VMSTATE_INT32(CP0_TCBind, TCState),
91     VMSTATE_UINTTL(CP0_TCHalt, TCState),
92     VMSTATE_UINTTL(CP0_TCContext, TCState),
93     VMSTATE_UINTTL(CP0_TCSchedule, TCState),
94     VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
95     VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
96     VMSTATE_UINTTL(CP0_UserLocal, TCState),
97     VMSTATE_INT32(msacsr, TCState),
98     VMSTATE_END_OF_LIST()
99 };
100 
101 const VMStateDescription vmstate_tc = {
102     .name = "cpu/tc",
103     .version_id = 1,
104     .minimum_version_id = 1,
105     .fields = vmstate_tc_fields
106 };
107 
108 const VMStateDescription vmstate_inactive_tc = {
109     .name = "cpu/inactive_tc",
110     .version_id = 1,
111     .minimum_version_id = 1,
112     .fields = vmstate_tc_fields
113 };
114 
115 /* MVP state */
116 
117 const VMStateDescription vmstate_mvp = {
118     .name = "cpu/mvp",
119     .version_id = 1,
120     .minimum_version_id = 1,
121     .fields = (VMStateField[]) {
122         VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
123         VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
124         VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
125         VMSTATE_END_OF_LIST()
126     }
127 };
128 
129 /* TLB state */
130 
get_tlb(QEMUFile * f,void * pv,size_t size,const VMStateField * field)131 static int get_tlb(QEMUFile *f, void *pv, size_t size,
132                    const VMStateField *field)
133 {
134     r4k_tlb_t *v = pv;
135     uint16_t flags;
136 
137     qemu_get_betls(f, &v->VPN);
138     qemu_get_be32s(f, &v->PageMask);
139     qemu_get_be16s(f, &v->ASID);
140     qemu_get_be16s(f, &flags);
141     v->G = (flags >> 10) & 1;
142     v->C0 = (flags >> 7) & 3;
143     v->C1 = (flags >> 4) & 3;
144     v->V0 = (flags >> 3) & 1;
145     v->V1 = (flags >> 2) & 1;
146     v->D0 = (flags >> 1) & 1;
147     v->D1 = (flags >> 0) & 1;
148     v->EHINV = (flags >> 15) & 1;
149     v->RI1 = (flags >> 14) & 1;
150     v->RI0 = (flags >> 13) & 1;
151     v->XI1 = (flags >> 12) & 1;
152     v->XI0 = (flags >> 11) & 1;
153     qemu_get_be64s(f, &v->PFN[0]);
154     qemu_get_be64s(f, &v->PFN[1]);
155 
156     return 0;
157 }
158 
put_tlb(QEMUFile * f,void * pv,size_t size,const VMStateField * field,JSONWriter * vmdesc)159 static int put_tlb(QEMUFile *f, void *pv, size_t size,
160                    const VMStateField *field, JSONWriter *vmdesc)
161 {
162     r4k_tlb_t *v = pv;
163 
164     uint16_t asid = v->ASID;
165     uint16_t flags = ((v->EHINV << 15) |
166                       (v->RI1 << 14) |
167                       (v->RI0 << 13) |
168                       (v->XI1 << 12) |
169                       (v->XI0 << 11) |
170                       (v->G << 10) |
171                       (v->C0 << 7) |
172                       (v->C1 << 4) |
173                       (v->V0 << 3) |
174                       (v->V1 << 2) |
175                       (v->D0 << 1) |
176                       (v->D1 << 0));
177 
178     qemu_put_betls(f, &v->VPN);
179     qemu_put_be32s(f, &v->PageMask);
180     qemu_put_be16s(f, &asid);
181     qemu_put_be16s(f, &flags);
182     qemu_put_be64s(f, &v->PFN[0]);
183     qemu_put_be64s(f, &v->PFN[1]);
184 
185     return 0;
186 }
187 
188 const VMStateInfo vmstate_info_tlb = {
189     .name = "tlb_entry",
190     .get  = get_tlb,
191     .put  = put_tlb,
192 };
193 
194 #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v)                     \
195     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
196 
197 #define VMSTATE_TLB_ARRAY(_f, _s, _n)                           \
198     VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
199 
200 const VMStateDescription vmstate_tlb = {
201     .name = "cpu/tlb",
202     .version_id = 2,
203     .minimum_version_id = 2,
204     .fields = (VMStateField[]) {
205         VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
206         VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
207         VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
208         VMSTATE_END_OF_LIST()
209     }
210 };
211 
212 /* MIPS CPU state */
213 
214 const VMStateDescription vmstate_mips_cpu = {
215     .name = "cpu",
216     .version_id = 20,
217     .minimum_version_id = 20,
218     .post_load = cpu_post_load,
219     .fields = (VMStateField[]) {
220         /* Active TC */
221         VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
222 
223         /* Active FPU */
224         VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
225                        CPUMIPSFPUContext),
226 
227         /* MVP */
228         VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
229                                CPUMIPSMVPContext),
230 
231         /* TLB */
232         VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
233                                CPUMIPSTLBContext),
234 
235         /* CPU metastate */
236         VMSTATE_UINT32(env.current_tc, MIPSCPU),
237         VMSTATE_UINT32(env.current_fpu, MIPSCPU),
238         VMSTATE_INT32(env.error_code, MIPSCPU),
239         VMSTATE_UINTTL(env.btarget, MIPSCPU),
240         VMSTATE_UINTTL(env.bcond, MIPSCPU),
241 
242         /* Remaining CP0 registers */
243         VMSTATE_INT32(env.CP0_Index, MIPSCPU),
244         VMSTATE_INT32(env.CP0_Random, MIPSCPU),
245         VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
246         VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
247         VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
248         VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
249         VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
250         VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
251         VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
252         VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
253         VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
254         VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
255         VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
256         VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
257         VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
258         VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
259         VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
260         VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
261         VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
262         VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
263         VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
264         VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
265         VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
266         VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
267         VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
268         VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
269         VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
270         VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
271         VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
272         VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
273         VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
274         VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
275         VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
276         VMSTATE_INT32(env.CP0_Count, MIPSCPU),
277         VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
278         VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
279         VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
280         VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
281         VMSTATE_INT32(env.CP0_Status, MIPSCPU),
282         VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
283         VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
284         VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
285         VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
286         VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
287         VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
288         VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
289         VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
290         VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
291         VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
292         VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
293         VMSTATE_INT32(env.CP0_Config4, MIPSCPU),
294         VMSTATE_INT32(env.CP0_Config5, MIPSCPU),
295         VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
296         VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
297         VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU),
298         VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
299         VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
300         VMSTATE_UINTTL(env.lladdr, MIPSCPU),
301         VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
302         VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
303         VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
304         VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
305         VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
306         VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
307         VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
308         VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
309         VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
310         VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
311         VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
312         VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
313         VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
314         VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
315 
316         /* Inactive TC */
317         VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
318                              vmstate_inactive_tc, TCState),
319         VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
320                              vmstate_inactive_fpu, CPUMIPSFPUContext),
321 
322         VMSTATE_END_OF_LIST()
323     },
324 };
325