1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
3
4 /* internal defines */
5 typedef struct DisasContext {
6 target_ulong pc;
7 uint32_t insn;
8 int is_jmp;
9 /* Nonzero if this instruction has been conditionally skipped. */
10 int condjmp;
11 /* The label that will be jumped to when the instruction is skipped. */
12 int condlabel;
13 /* Thumb-2 conditional execution bits. */
14 int condexec_mask;
15 int condexec_cond;
16 struct TranslationBlock *tb;
17 int singlestep_enabled;
18 int thumb;
19 int bswap_code;
20 #if !defined(CONFIG_USER_ONLY)
21 int user;
22 #endif
23 bool cpacr_fpen; /* FP enabled via CPACR.FPEN */
24 bool vfp_enabled; /* FP enabled via FPSCR.EN */
25 int vec_len;
26 int vec_stride;
27 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
28 * so that top level loop can generate correct syndrome information.
29 */
30 uint32_t svc_imm;
31 int aarch64;
32 int current_el;
33 GHashTable *cp_regs;
34 uint64_t features; /* CPU features bits */
35 /* Because unallocated encodings generate different exception syndrome
36 * information from traps due to FP being disabled, we can't do a single
37 * "is fp access disabled" check at a high level in the decode tree.
38 * To help in catching bugs where the access check was forgotten in some
39 * code path, we set this flag when the access check is done, and assert
40 * that it is set at the point where we actually touch the FP regs.
41 */
42 bool fp_access_checked;
43 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
44 * single-step support).
45 */
46 bool ss_active;
47 bool pstate_ss;
48 /* True if the insn just emitted was a load-exclusive instruction
49 * (necessary for syndrome information for single step exceptions),
50 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
51 */
52 bool is_ldex;
53 /* True if a single-step exception will be taken to the current EL */
54 bool ss_same_el;
55 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
56 int c15_cpar;
57 #define TMP_A64_MAX 16
58 int tmp_a64_count;
59 TCGv_i64 tmp_a64[TMP_A64_MAX];
60
61 // Unicorn engine
62 struct uc_struct *uc;
63 } DisasContext;
64
65
arm_dc_feature(DisasContext * dc,int feature)66 static inline int arm_dc_feature(DisasContext *dc, int feature)
67 {
68 return (dc->features & (1ULL << feature)) != 0;
69 }
70
get_mem_index(DisasContext * s)71 static inline int get_mem_index(DisasContext *s)
72 {
73 return s->current_el;
74 }
75
76 /* target-specific extra values for is_jmp */
77 /* These instructions trap after executing, so the A32/T32 decoder must
78 * defer them until after the conditional execution state has been updated.
79 * WFI also needs special handling when single-stepping.
80 */
81 #define DISAS_WFI 4
82 #define DISAS_SWI 5
83 /* For instructions which unconditionally cause an exception we can skip
84 * emitting unreachable code at the end of the TB in the A64 decoder
85 */
86 #define DISAS_EXC 6
87 /* WFE */
88 #define DISAS_WFE 7
89 #define DISAS_HVC 8
90 #define DISAS_SMC 9
91
92 #ifdef TARGET_AARCH64
93 void a64_translate_init(struct uc_struct *uc);
94 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
95 TranslationBlock *tb,
96 bool search_pc);
97 void gen_a64_set_pc_im(DisasContext *s, uint64_t val);
98 #else
a64_translate_init(struct uc_struct * uc)99 static inline void a64_translate_init(struct uc_struct *uc)
100 {
101 }
102
gen_intermediate_code_internal_a64(ARMCPU * cpu,TranslationBlock * tb,bool search_pc)103 static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
104 TranslationBlock *tb,
105 bool search_pc)
106 {
107 }
108
gen_a64_set_pc_im(uint64_t val)109 static inline void gen_a64_set_pc_im(uint64_t val)
110 {
111 }
112 #endif
113
114 void arm_gen_test_cc(TCGContext *tcg_ctx, int cc, int label);
115
116 #endif /* TARGET_ARM_TRANSLATE_H */
117