1 // 2 // Copyright (C) 2013-2018 Alexey Khokholov (Nuke.YKT) 3 // 4 // This program is free software; you can redistribute it and/or 5 // modify it under the terms of the GNU General Public License 6 // as published by the Free Software Foundation; either version 2 7 // of the License, or (at your option) any later version. 8 // 9 // This program is distributed in the hope that it will be useful, 10 // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 // GNU General Public License for more details. 13 // 14 // 15 // Nuked OPL3 emulator. 16 // Thanks: 17 // MAME Development Team(Jarek Burczynski, Tatsuyuki Satoh): 18 // Feedback and Rhythm part calculation information. 19 // forums.submarine.org.uk(carbon14, opl3): 20 // Tremolo and phase generator calculation information. 21 // OPLx decapsulated(Matthew Gambrell, Olli Niemitalo): 22 // OPL2 ROMs. 23 // siliconpr0n.org(John McMaster, digshadow): 24 // YMF262 and VRC VII decaps and die shots. 25 // 26 // version: 1.8 27 // 28 29 #ifndef OPL_OPL3_H 30 #define OPL_OPL3_H 31 32 #include <inttypes.h> 33 34 #define OPL_WRITEBUF_SIZE 1024 35 #define OPL_WRITEBUF_DELAY 2 36 37 typedef uintptr_t Bitu; 38 typedef intptr_t Bits; 39 typedef uint64_t Bit64u; 40 typedef int64_t Bit64s; 41 typedef uint32_t Bit32u; 42 typedef int32_t Bit32s; 43 typedef uint16_t Bit16u; 44 typedef int16_t Bit16s; 45 typedef uint8_t Bit8u; 46 typedef int8_t Bit8s; 47 48 typedef struct _opl3_slot opl3_slot; 49 typedef struct _opl3_channel opl3_channel; 50 typedef struct _opl3_chip opl3_chip; 51 52 struct _opl3_slot { 53 opl3_channel *channel; 54 opl3_chip *chip; 55 Bit16s out; 56 Bit16s fbmod; 57 Bit16s *mod; 58 Bit16s prout; 59 Bit16s eg_rout; 60 Bit16s eg_out; 61 Bit8u eg_inc; 62 Bit8u eg_gen; 63 Bit8u eg_rate; 64 Bit8u eg_ksl; 65 Bit8u *trem; 66 Bit8u reg_vib; 67 Bit8u reg_type; 68 Bit8u reg_ksr; 69 Bit8u reg_mult; 70 Bit8u reg_ksl; 71 Bit8u reg_tl; 72 Bit8u reg_ar; 73 Bit8u reg_dr; 74 Bit8u reg_sl; 75 Bit8u reg_rr; 76 Bit8u reg_wf; 77 Bit8u key; 78 Bit32u pg_reset; 79 Bit32u pg_phase; 80 Bit16u pg_phase_out; 81 Bit8u slot_num; 82 }; 83 84 struct _opl3_channel { 85 opl3_slot *slots[2]; 86 opl3_channel *pair; 87 opl3_chip *chip; 88 Bit16s *out[4]; 89 Bit8u chtype; 90 Bit16u f_num; 91 Bit8u block; 92 Bit8u fb; 93 Bit8u con; 94 Bit8u alg; 95 Bit8u ksv; 96 Bit16u cha, chb; 97 Bit8u ch_num; 98 }; 99 100 typedef struct _opl3_writebuf { 101 Bit64u time; 102 Bit16u reg; 103 Bit8u data; 104 } opl3_writebuf; 105 106 struct _opl3_chip { 107 opl3_channel channel[18]; 108 opl3_slot slot[36]; 109 Bit16u timer; 110 Bit64u eg_timer; 111 Bit8u eg_timerrem; 112 Bit8u eg_state; 113 Bit8u eg_add; 114 Bit8u newm; 115 Bit8u nts; 116 Bit8u rhy; 117 Bit8u vibpos; 118 Bit8u vibshift; 119 Bit8u tremolo; 120 Bit8u tremolopos; 121 Bit8u tremoloshift; 122 Bit32u noise; 123 Bit16s zeromod; 124 Bit32s mixbuff[2]; 125 Bit8u rm_hh_bit2; 126 Bit8u rm_hh_bit3; 127 Bit8u rm_hh_bit7; 128 Bit8u rm_hh_bit8; 129 Bit8u rm_tc_bit3; 130 Bit8u rm_tc_bit5; 131 //OPL3L 132 Bit32s rateratio; 133 Bit32s samplecnt; 134 Bit16s oldsamples[2]; 135 Bit16s samples[2]; 136 137 Bit64u writebuf_samplecnt; 138 Bit32u writebuf_cur; 139 Bit32u writebuf_last; 140 Bit64u writebuf_lasttime; 141 opl3_writebuf writebuf[OPL_WRITEBUF_SIZE]; 142 }; 143 144 void OPL3_Generate(opl3_chip *chip, Bit16s *buf); 145 void OPL3_GenerateResampled(opl3_chip *chip, Bit16s *buf); 146 void OPL3_Reset(opl3_chip *chip, Bit32u samplerate); 147 void OPL3_WriteReg(opl3_chip *chip, Bit16u reg, Bit8u v); 148 void OPL3_WriteRegBuffered(opl3_chip *chip, Bit16u reg, Bit8u v); 149 void OPL3_GenerateStream(opl3_chip *chip, Bit16s *sndptr, Bit32u numsamples); 150 #endif 151