1 /*
2 ===========================================================================
3 Copyright (C) 2008 Przemyslaw Iskra <sparky@pld-linux.org>
4
5 This file is part of Quake III Arena source code.
6
7 Quake III Arena source code is free software; you can redistribute it
8 and/or modify it under the terms of the GNU General Public License as
9 published by the Free Software Foundation; either version 2 of the License,
10 or (at your option) any later version.
11
12 Quake III Arena source code is distributed in the hope that it will be
13 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with Quake III Arena source code; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 ===========================================================================
21
22 * File includes code from GNU binutils, exactly:
23 * - include/opcode/ppc.h - licensed under GPL v1 or later
24 * - opcodes/ppc-opc.c - licensed under GPL v2 or later
25 *
26 * ppc.h -- Header file for PowerPC opcode table
27 * Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
28 * 2007 Free Software Foundation, Inc.
29 * Written by Ian Lance Taylor, Cygnus Suppor
30 *
31 * This file is part of GDB, GAS, and the GNU binutils.
32 *
33 * ppc-opc.c -- PowerPC opcode list
34 * Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
35 * 2005, 2006, 2007 Free Software Foundation, Inc.
36 * Written by Ian Lance Taylor, Cygnus Support
37 *
38 * This file is part of GDB, GAS, and the GNU binutils.
39 *
40 */
41
42 #include "vm_local.h"
43 #include "vm_powerpc_asm.h"
44
45 #include <string.h>
46 #include <stdio.h>
47 #include <inttypes.h>
48
49 /* return nop on error */
50 #define ASM_ERROR_OPC (0x60000000)
51
52 /*
53 * BEGIN OF ppc.h
54 */
55
56 #define ppc_cpu_t int
57
58 struct powerpc_opcode
59 {
60 const char *name;
61 unsigned long opcode;
62 unsigned long mask;
63 ppc_cpu_t flags;
64 unsigned char operands[8];
65 };
66
67 static const struct powerpc_opcode powerpc_opcodes[];
68
69 #define PPC_OPCODE_PPC 1
70 #define PPC_OPCODE_POWER 2
71 #define PPC_OPCODE_POWER2 4
72 #define PPC_OPCODE_32 8
73 #define PPC_OPCODE_64 0x10
74 #define PPC_OPCODE_601 0x20
75 #define PPC_OPCODE_COMMON 0x40
76 #define PPC_OPCODE_ANY 0x80
77 #define PPC_OPCODE_64_BRIDGE 0x100
78 #define PPC_OPCODE_ALTIVEC 0x200
79 #define PPC_OPCODE_403 0x400
80 #define PPC_OPCODE_BOOKE 0x800
81 #define PPC_OPCODE_BOOKE64 0x1000
82 #define PPC_OPCODE_440 0x2000
83 #define PPC_OPCODE_POWER4 0x4000
84 #define PPC_OPCODE_NOPOWER4 0x8000
85 #define PPC_OPCODE_CLASSIC 0x10000
86 #define PPC_OPCODE_SPE 0x20000
87 #define PPC_OPCODE_ISEL 0x40000
88 #define PPC_OPCODE_EFS 0x80000
89 #define PPC_OPCODE_BRLOCK 0x100000
90 #define PPC_OPCODE_PMR 0x200000
91 #define PPC_OPCODE_CACHELCK 0x400000
92 #define PPC_OPCODE_RFMCI 0x800000
93 #define PPC_OPCODE_POWER5 0x1000000
94 #define PPC_OPCODE_E300 0x2000000
95 #define PPC_OPCODE_POWER6 0x4000000
96 #define PPC_OPCODE_CELL 0x8000000
97 #define PPC_OPCODE_PPCPS 0x10000000
98 #define PPC_OPCODE_E500MC 0x20000000
99 #define PPC_OPCODE_405 0x40000000
100 #define PPC_OPCODE_VSX 0x80000000
101
102 #define PPC_OP(i) (((i) >> 26) & 0x3f)
103
104 struct powerpc_operand
105 {
106 unsigned int bitm;
107 int shift;
108 unsigned long (*insert)
109 (unsigned long, long, int, const char **);
110 unsigned long flags;
111 };
112
113 static const struct powerpc_operand powerpc_operands[];
114
115 #define PPC_OPERAND_SIGNED (0x1)
116 #define PPC_OPERAND_SIGNOPT (0x2)
117 #define PPC_OPERAND_FAKE (0x4)
118 #define PPC_OPERAND_PARENS (0x8)
119 #define PPC_OPERAND_CR (0x10)
120 #define PPC_OPERAND_GPR (0x20)
121 #define PPC_OPERAND_GPR_0 (0x40)
122 #define PPC_OPERAND_FPR (0x80)
123 #define PPC_OPERAND_RELATIVE (0x100)
124 #define PPC_OPERAND_ABSOLUTE (0x200)
125 #define PPC_OPERAND_OPTIONAL (0x400)
126 #define PPC_OPERAND_NEXT (0x800)
127 #define PPC_OPERAND_NEGATIVE (0x1000)
128 #define PPC_OPERAND_VR (0x2000)
129 #define PPC_OPERAND_DS (0x4000)
130 #define PPC_OPERAND_DQ (0x8000)
131 #define PPC_OPERAND_PLUS1 (0x10000)
132 #define PPC_OPERAND_FSL (0x20000)
133 #define PPC_OPERAND_FCR (0x40000)
134 #define PPC_OPERAND_UDI (0x80000)
135 #define PPC_OPERAND_VSR (0x100000)
136
137 /*
138 * END OF ppc.h
139 */
140
141 #define PPC_DEST_ARCH PPC_OPCODE_PPC
142
143 ppc_instruction_t
asm_instruction(powerpc_iname_t sname,const int argc,const long int * argv)144 asm_instruction( powerpc_iname_t sname, const int argc, const long int *argv )
145 {
146 const char *errmsg = NULL;
147 const char *name;
148 unsigned long int ret;
149 const struct powerpc_opcode *opcode = NULL;
150 int argi, argj;
151
152 opcode = &powerpc_opcodes[ sname ];
153 name = opcode->name;
154
155 if ( ! opcode ) {
156 printf( "Can't find opcode %d\n", sname );
157 return ASM_ERROR_OPC;
158 }
159 if ( ( opcode->flags & PPC_DEST_ARCH ) != PPC_DEST_ARCH ) {
160 printf( "opcode %s not defined for this arch\n", name );
161 return ASM_ERROR_OPC;
162 }
163
164 ret = opcode->opcode;
165
166 argi = argj = 0;
167 while ( opcode->operands[ argi ] != 0 ) {
168 long int op = 0;
169 const struct powerpc_operand *operand = &powerpc_operands[ opcode->operands[ argi ] ];
170
171 if ( ! (operand->flags & PPC_OPERAND_FAKE) ) {
172 if ( argj >= argc ) {
173 printf( "Not enough arguments for %s, got %d\n", name, argc );
174 return ASM_ERROR_OPC;
175 }
176
177 op = argv[ argj++ ];
178 }
179
180 if ( operand->insert ) {
181 errmsg = NULL;
182 ret = operand->insert( ret, op, PPC_DEST_ARCH, &errmsg );
183 if ( errmsg ) {
184 printf( "%s: error while inserting operand %d (0x%.2lx): %s\n",
185 name, argi, op, errmsg );
186 }
187 } else {
188 unsigned long int opu = *(unsigned long int *)&op;
189 unsigned long int bitm = operand->bitm;
190 unsigned long int bitm_full = bitm | ( bitm & 1 ? 0 : 0xf );
191
192 if ( operand->flags & PPC_OPERAND_SIGNED ) {
193 bitm_full >>= 1;
194
195 if ( ( opu & ~bitm_full ) != 0 && ( opu | bitm_full ) != -1 )
196 printf( "%s: signed operand nr.%d to wide. op: %.8lx, mask: %.8lx\n",
197 name, argi, opu, bitm );
198 } else {
199 if ( ( opu & ~bitm_full ) != 0 )
200 printf( "%s: unsigned operand nr.%d to wide. op: %.8lx, mask: %.8lx\n",
201 name, argi, opu, bitm );
202 }
203 if ( (bitm & 1) == 0 ) {
204 if ( opu & 0xf & ~bitm )
205 printf( "%s: operand nr.%d not aligned correctly. op: %.8lx, mask: %.8lx\n",
206 name, argi, opu, bitm );
207 }
208
209 ret |= ( op & operand->bitm ) << operand->shift;
210 }
211 argi++;
212 }
213 if ( argc > argj ) {
214 printf( "Too many arguments for %s, got %d\n", name, argc );
215 return ASM_ERROR_OPC;
216 }
217
218 return ret;
219 }
220
221
222 /*
223 * BEGIN OF ppc-opc.c
224 */
225
226 #define ATTRIBUTE_UNUSED
227 #define _(x) (x)
228
229 /* Local insertion and extraction functions. */
230
231 static unsigned long insert_bdm (unsigned long, long, int, const char **);
232 static unsigned long insert_bo (unsigned long, long, int, const char **);
233 static unsigned long insert_ras (unsigned long, long, int, const char **);
234 static unsigned long insert_rbs (unsigned long, long, int, const char **);
235
236 /* The operands table.
237
238 The fields are bitm, shift, insert, extract, flags.
239 */
240
241 static const struct powerpc_operand powerpc_operands[] =
242 {
243 /* The zero index is used to indicate the end of the list of
244 operands. */
245 #define UNUSED 0
246 { 0, 0, NULL, 0 },
247
248 /* The BA field in an XL form instruction. */
249 #define BA UNUSED + 1
250 /* The BI field in a B form or XL form instruction. */
251 #define BI BA
252 #define BI_MASK (0x1f << 16)
253 { 0x1f, 16, NULL, PPC_OPERAND_CR },
254
255 /* The BD field in a B form instruction. The lower two bits are
256 forced to zero. */
257 #define BD BA + 1
258 { 0xfffc, 0, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
259
260 /* The BD field in a B form instruction when the - modifier is used.
261 This sets the y bit of the BO field appropriately. */
262 #define BDM BD + 1
263 { 0xfffc, 0, insert_bdm,
264 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
265
266 /* The BF field in an X or XL form instruction. */
267 #define BF BDM + 1
268 /* The CRFD field in an X form instruction. */
269 #define CRFD BF
270 { 0x7, 23, NULL, PPC_OPERAND_CR },
271
272 /* An optional BF field. This is used for comparison instructions,
273 in which an omitted BF field is taken as zero. */
274 #define OBF BF + 1
275 { 0x7, 23, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
276
277 /* The BO field in a B form instruction. Certain values are
278 illegal. */
279 #define BO OBF + 1
280 #define BO_MASK (0x1f << 21)
281 { 0x1f, 21, insert_bo, 0 },
282
283 /* The condition register number portion of the BI field in a B form
284 or XL form instruction. This is used for the extended
285 conditional branch mnemonics, which set the lower two bits of the
286 BI field. This field is optional. */
287 #define CR BO + 1
288 { 0x7, 18, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
289
290 /* The D field in a D form instruction. This is a displacement off
291 a register, and implies that the next operand is a register in
292 parentheses. */
293 #define D CR + 1
294 { 0xffff, 0, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
295
296 /* The DS field in a DS form instruction. This is like D, but the
297 lower two bits are forced to zero. */
298 #define DS D + 1
299 { 0xfffc, 0, NULL,
300 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
301
302 /* The FRA field in an X or A form instruction. */
303 #define FRA DS + 1
304 #define FRA_MASK (0x1f << 16)
305 { 0x1f, 16, NULL, PPC_OPERAND_FPR },
306
307 /* The FRB field in an X or A form instruction. */
308 #define FRB FRA + 1
309 #define FRB_MASK (0x1f << 11)
310 { 0x1f, 11, NULL, PPC_OPERAND_FPR },
311
312 /* The FRC field in an A form instruction. */
313 #define FRC FRB + 1
314 #define FRC_MASK (0x1f << 6)
315 { 0x1f, 6, NULL, PPC_OPERAND_FPR },
316
317 /* The FRS field in an X form instruction or the FRT field in a D, X
318 or A form instruction. */
319 #define FRS FRC + 1
320 #define FRT FRS
321 { 0x1f, 21, NULL, PPC_OPERAND_FPR },
322
323 /* The LI field in an I form instruction. The lower two bits are
324 forced to zero. */
325 #define LI FRS + 1
326 { 0x3fffffc, 0, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
327
328 /* The ME field in an M form instruction. */
329 #define ME LI + 1
330 #define ME_MASK (0x1f << 1)
331 { 0x1f, 1, NULL, 0 },
332
333 /* The MB and ME fields in an M form instruction expressed a single
334 operand which is a bitmask indicating which bits to select. This
335 is a two operand form using PPC_OPERAND_NEXT. See the
336 description in opcode/ppc.h for what this means. */
337 #define MBE ME + 1
338 { 0x1f, 6, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
339
340 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
341 #define RA MBE + 1
342 #define RA_MASK (0x1f << 16)
343 { 0x1f, 16, NULL, PPC_OPERAND_GPR },
344
345 /* As above, but 0 in the RA field means zero, not r0. */
346 #define RA0 RA + 1
347 { 0x1f, 16, NULL, PPC_OPERAND_GPR_0 },
348
349 /* The RA field in a D or X form instruction which is an updating
350 store or an updating floating point load, which means that the RA
351 field may not be zero. */
352 #define RAS RA0 + 1
353 { 0x1f, 16, insert_ras, PPC_OPERAND_GPR_0 },
354
355 /* The RB field in an X, XO, M, or MDS form instruction. */
356 #define RB RAS + 1
357 #define RB_MASK (0x1f << 11)
358 { 0x1f, 11, NULL, PPC_OPERAND_GPR },
359
360 /* The RB field in an X form instruction when it must be the same as
361 the RS field in the instruction. This is used for extended
362 mnemonics like mr. */
363 #define RBS RB + 1
364 { 0x1f, 11, insert_rbs, PPC_OPERAND_FAKE },
365
366 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
367 instruction or the RT field in a D, DS, X, XFX or XO form
368 instruction. */
369 #define RS RBS + 1
370 #define RT RS
371 #define RT_MASK (0x1f << 21)
372 { 0x1f, 21, NULL, PPC_OPERAND_GPR },
373
374 /* The SH field in an X or M form instruction. */
375 #define SH RS + 1
376 #define SH_MASK (0x1f << 11)
377 /* The other UIMM field in an EVX form instruction. */
378 #define EVUIMM SH
379 { 0x1f, 11, NULL, 0 },
380
381 /* The SI field in a D form instruction. */
382 #define SI SH + 1
383 { 0xffff, 0, NULL, PPC_OPERAND_SIGNED },
384
385 /* The UI field in a D form instruction. */
386 #define UI SI + 1
387 { 0xffff, 0, NULL, 0 },
388
389 };
390
391
392 /* The functions used to insert and extract complicated operands. */
393
394 /* The BD field in a B form instruction when the - modifier is used.
395 This modifier means that the branch is not expected to be taken.
396 For chips built to versions of the architecture prior to version 2
397 (ie. not Power4 compatible), we set the y bit of the BO field to 1
398 if the offset is negative. When extracting, we require that the y
399 bit be 1 and that the offset be positive, since if the y bit is 0
400 we just want to print the normal form of the instruction.
401 Power4 compatible targets use two bits, "a", and "t", instead of
402 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
403 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
404 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
405 for branch on CTR. We only handle the taken/not-taken hint here.
406 Note that we don't relax the conditions tested here when
407 disassembling with -Many because insns using extract_bdm and
408 extract_bdp always occur in pairs. One or the other will always
409 be valid. */
410
411 static unsigned long
insert_bdm(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)412 insert_bdm (unsigned long insn,
413 long value,
414 int dialect,
415 const char **errmsg ATTRIBUTE_UNUSED)
416 {
417 if ((dialect & PPC_OPCODE_POWER4) == 0)
418 {
419 if ((value & 0x8000) != 0)
420 insn |= 1 << 21;
421 }
422 else
423 {
424 if ((insn & (0x14 << 21)) == (0x04 << 21))
425 insn |= 0x02 << 21;
426 else if ((insn & (0x14 << 21)) == (0x10 << 21))
427 insn |= 0x08 << 21;
428 }
429 return insn | (value & 0xfffc);
430 }
431
432
433 /* Check for legal values of a BO field. */
434
435 static int
valid_bo(long value,int dialect,int extract)436 valid_bo (long value, int dialect, int extract)
437 {
438 if ((dialect & PPC_OPCODE_POWER4) == 0)
439 {
440 int valid;
441 /* Certain encodings have bits that are required to be zero.
442 These are (z must be zero, y may be anything):
443 001zy
444 011zy
445 1z00y
446 1z01y
447 1z1zz
448 */
449 switch (value & 0x14)
450 {
451 default:
452 case 0:
453 valid = 1;
454 break;
455 case 0x4:
456 valid = (value & 0x2) == 0;
457 break;
458 case 0x10:
459 valid = (value & 0x8) == 0;
460 break;
461 case 0x14:
462 valid = value == 0x14;
463 break;
464 }
465 /* When disassembling with -Many, accept power4 encodings too. */
466 if (valid
467 || (dialect & PPC_OPCODE_ANY) == 0
468 || !extract)
469 return valid;
470 }
471
472 /* Certain encodings have bits that are required to be zero.
473 These are (z must be zero, a & t may be anything):
474 0000z
475 0001z
476 0100z
477 0101z
478 001at
479 011at
480 1a00t
481 1a01t
482 1z1zz
483 */
484 if ((value & 0x14) == 0)
485 return (value & 0x1) == 0;
486 else if ((value & 0x14) == 0x14)
487 return value == 0x14;
488 else
489 return 1;
490 }
491
492 /* The BO field in a B form instruction. Warn about attempts to set
493 the field to an illegal value. */
494
495 static unsigned long
insert_bo(unsigned long insn,long value,int dialect,const char ** errmsg)496 insert_bo (unsigned long insn,
497 long value,
498 int dialect,
499 const char **errmsg)
500 {
501 if (!valid_bo (value, dialect, 0))
502 *errmsg = _("invalid conditional option");
503 return insn | ((value & 0x1f) << 21);
504 }
505
506 /* The RA field in a D or X form instruction which is an updating
507 store or an updating floating point load, which means that the RA
508 field may not be zero. */
509
510 static unsigned long
insert_ras(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)511 insert_ras (unsigned long insn,
512 long value,
513 int dialect ATTRIBUTE_UNUSED,
514 const char **errmsg)
515 {
516 if (value == 0)
517 *errmsg = _("invalid register operand when updating");
518 return insn | ((value & 0x1f) << 16);
519 }
520
521 /* The RB field in an X form instruction when it must be the same as
522 the RS field in the instruction. This is used for extended
523 mnemonics like mr. This operand is marked FAKE. The insertion
524 function just copies the BT field into the BA field, and the
525 extraction function just checks that the fields are the same. */
526
527 static unsigned long
insert_rbs(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)528 insert_rbs (unsigned long insn,
529 long value ATTRIBUTE_UNUSED,
530 int dialect ATTRIBUTE_UNUSED,
531 const char **errmsg ATTRIBUTE_UNUSED)
532 {
533 return insn | (((insn >> 21) & 0x1f) << 11);
534 }
535
536
537 /* Macros used to form opcodes. */
538
539 /* The main opcode. */
540 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
541 #define OP_MASK OP (0x3f)
542
543 /* The main opcode combined with a trap code in the TO field of a D
544 form instruction. Used for extended mnemonics for the trap
545 instructions. */
546 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
547 #define OPTO_MASK (OP_MASK | TO_MASK)
548
549 /* The main opcode combined with a comparison size bit in the L field
550 of a D form or X form instruction. Used for extended mnemonics for
551 the comparison instructions. */
552 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
553 #define OPL_MASK OPL (0x3f,1)
554
555 /* An A form instruction. */
556 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
557 #define A_MASK A (0x3f, 0x1f, 1)
558
559 /* An A_MASK with the FRB field fixed. */
560 #define AFRB_MASK (A_MASK | FRB_MASK)
561
562 /* An A_MASK with the FRC field fixed. */
563 #define AFRC_MASK (A_MASK | FRC_MASK)
564
565 /* An A_MASK with the FRA and FRC fields fixed. */
566 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
567
568 /* An AFRAFRC_MASK, but with L bit clear. */
569 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
570
571 /* A B form instruction. */
572 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
573 #define B_MASK B (0x3f, 1, 1)
574
575 /* A B form instruction setting the BO field. */
576 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
577 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
578
579 /* A BBO_MASK with the y bit of the BO field removed. This permits
580 matching a conditional branch regardless of the setting of the y
581 bit. Similarly for the 'at' bits used for power4 branch hints. */
582 #define Y_MASK (((unsigned long) 1) << 21)
583 #define AT1_MASK (((unsigned long) 3) << 21)
584 #define AT2_MASK (((unsigned long) 9) << 21)
585 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
586 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
587
588 /* A B form instruction setting the BO field and the condition bits of
589 the BI field. */
590 #define BBOCB(op, bo, cb, aa, lk) \
591 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
592 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
593
594 /* A BBOCB_MASK with the y bit of the BO field removed. */
595 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
596 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
597 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
598
599 /* A BBOYCB_MASK in which the BI field is fixed. */
600 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
601 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
602
603 /* An Context form instruction. */
604 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
605 #define CTX_MASK CTX(0x3f, 0x7)
606
607 /* An User Context form instruction. */
608 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
609 #define UCTX_MASK UCTX(0x3f, 0x1f)
610
611 /* The main opcode mask with the RA field clear. */
612 #define DRA_MASK (OP_MASK | RA_MASK)
613
614 /* A DS form instruction. */
615 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
616 #define DS_MASK DSO (0x3f, 3)
617
618 /* A DE form instruction. */
619 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
620 #define DE_MASK DEO (0x3e, 0xf)
621
622 /* An EVSEL form instruction. */
623 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
624 #define EVSEL_MASK EVSEL(0x3f, 0xff)
625
626 /* An M form instruction. */
627 #define M(op, rc) (OP (op) | ((rc) & 1))
628 #define M_MASK M (0x3f, 1)
629
630 /* An M form instruction with the ME field specified. */
631 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
632
633 /* An M_MASK with the MB and ME fields fixed. */
634 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
635
636 /* An M_MASK with the SH and ME fields fixed. */
637 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
638
639 /* An MD form instruction. */
640 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
641 #define MD_MASK MD (0x3f, 0x7, 1)
642
643 /* An MD_MASK with the MB field fixed. */
644 #define MDMB_MASK (MD_MASK | MB6_MASK)
645
646 /* An MD_MASK with the SH field fixed. */
647 #define MDSH_MASK (MD_MASK | SH6_MASK)
648
649 /* An MDS form instruction. */
650 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
651 #define MDS_MASK MDS (0x3f, 0xf, 1)
652
653 /* An MDS_MASK with the MB field fixed. */
654 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
655
656 /* An SC form instruction. */
657 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
658 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
659
660 /* A VX form instruction. */
661 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
662
663 /* The mask for a VX form instruction. */
664 #define VX_MASK VX(0x3f, 0x7ff)
665
666 /* A VA form instruction. */
667 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
668
669 /* The mask for a VA form instruction. */
670 #define VXA_MASK VXA(0x3f, 0x3f)
671
672 /* A VXR form instruction. */
673 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
674
675 /* The mask for a VXR form instruction. */
676 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
677
678 /* An X form instruction. */
679 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
680
681 /* A Z form instruction. */
682 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
683
684 /* An X form instruction with the RC bit specified. */
685 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
686
687 /* A Z form instruction with the RC bit specified. */
688 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
689
690 /* The mask for an X form instruction. */
691 #define X_MASK XRC (0x3f, 0x3ff, 1)
692
693 /* The mask for a Z form instruction. */
694 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
695 #define Z2_MASK ZRC (0x3f, 0xff, 1)
696
697 /* An X_MASK with the RA field fixed. */
698 #define XRA_MASK (X_MASK | RA_MASK)
699
700 /* An XRA_MASK with the W field clear. */
701 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
702
703 /* An X_MASK with the RB field fixed. */
704 #define XRB_MASK (X_MASK | RB_MASK)
705
706 /* An X_MASK with the RT field fixed. */
707 #define XRT_MASK (X_MASK | RT_MASK)
708
709 /* An XRT_MASK mask with the L bits clear. */
710 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
711
712 /* An X_MASK with the RA and RB fields fixed. */
713 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
714
715 /* An XRARB_MASK, but with the L bit clear. */
716 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
717
718 /* An X_MASK with the RT and RA fields fixed. */
719 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
720
721 /* An XRTRA_MASK, but with L bit clear. */
722 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
723
724 /* An X form instruction with the L bit specified. */
725 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
726
727 /* The mask for an X form comparison instruction. */
728 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
729
730 /* The mask for an X form comparison instruction with the L field
731 fixed. */
732 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
733
734 /* An X form trap instruction with the TO field specified. */
735 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
736 #define XTO_MASK (X_MASK | TO_MASK)
737
738 /* An X form tlb instruction with the SH field specified. */
739 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
740 #define XTLB_MASK (X_MASK | SH_MASK)
741
742 /* An X form sync instruction. */
743 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
744
745 /* An X form sync instruction with everything filled in except the LS field. */
746 #define XSYNC_MASK (0xff9fffff)
747
748 /* An X_MASK, but with the EH bit clear. */
749 #define XEH_MASK (X_MASK & ~((unsigned long )1))
750
751 /* An X form AltiVec dss instruction. */
752 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
753 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
754
755 /* An XFL form instruction. */
756 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
757 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
758
759 /* An X form isel instruction. */
760 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
761 #define XISEL_MASK XISEL(0x3f, 0x1f)
762
763 /* An XL form instruction with the LK field set to 0. */
764 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
765
766 /* An XL form instruction which uses the LK field. */
767 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
768
769 /* The mask for an XL form instruction. */
770 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
771
772 /* An XL form instruction which explicitly sets the BO field. */
773 #define XLO(op, bo, xop, lk) \
774 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
775 #define XLO_MASK (XL_MASK | BO_MASK)
776
777 /* An XL form instruction which explicitly sets the y bit of the BO
778 field. */
779 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
780 #define XLYLK_MASK (XL_MASK | Y_MASK)
781
782 /* An XL form instruction which sets the BO field and the condition
783 bits of the BI field. */
784 #define XLOCB(op, bo, cb, xop, lk) \
785 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
786 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
787
788 #define BB_MASK (0x1f << 11)
789 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
790 #define XLBB_MASK (XL_MASK | BB_MASK)
791 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
792 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
793
794 /* A mask for branch instructions using the BH field. */
795 #define XLBH_MASK (XL_MASK | (0x1c << 11))
796
797 /* An XL_MASK with the BO and BB fields fixed. */
798 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
799
800 /* An XL_MASK with the BO, BI and BB fields fixed. */
801 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
802
803 /* An XO form instruction. */
804 #define XO(op, xop, oe, rc) \
805 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
806 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
807
808 /* An XO_MASK with the RB field fixed. */
809 #define XORB_MASK (XO_MASK | RB_MASK)
810
811 /* An XS form instruction. */
812 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
813 #define XS_MASK XS (0x3f, 0x1ff, 1)
814
815 /* A mask for the FXM version of an XFX form instruction. */
816 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
817
818 /* An XFX form instruction with the FXM field filled in. */
819 #define XFXM(op, xop, fxm, p4) \
820 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
821 | ((unsigned long)(p4) << 20))
822
823 #define SPR_MASK (0x3ff << 11)
824 /* An XFX form instruction with the SPR field filled in. */
825 #define XSPR(op, xop, spr) \
826 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
827 #define XSPR_MASK (X_MASK | SPR_MASK)
828
829 /* An XFX form instruction with the SPR field filled in except for the
830 SPRBAT field. */
831 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
832
833 /* An XFX form instruction with the SPR field filled in except for the
834 SPRG field. */
835 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
836
837 /* An X form instruction with everything filled in except the E field. */
838 #define XE_MASK (0xffff7fff)
839
840 /* An X form user context instruction. */
841 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
842 #define XUC_MASK XUC(0x3f, 0x1f)
843
844 /* The BO encodings used in extended conditional branch mnemonics. */
845 #define BODNZF (0x0)
846 #define BODNZFP (0x1)
847 #define BODZF (0x2)
848 #define BODZFP (0x3)
849 #define BODNZT (0x8)
850 #define BODNZTP (0x9)
851 #define BODZT (0xa)
852 #define BODZTP (0xb)
853
854 #define BOF (0x4)
855 #define BOFP (0x5)
856 #define BOFM4 (0x6)
857 #define BOFP4 (0x7)
858 #define BOT (0xc)
859 #define BOTP (0xd)
860 #define BOTM4 (0xe)
861 #define BOTP4 (0xf)
862
863 #define BODNZ (0x10)
864 #define BODNZP (0x11)
865 #define BODZ (0x12)
866 #define BODZP (0x13)
867 #define BODNZM4 (0x18)
868 #define BODNZP4 (0x19)
869 #define BODZM4 (0x1a)
870 #define BODZP4 (0x1b)
871
872 #define BOU (0x14)
873
874 /* The BI condition bit encodings used in extended conditional branch
875 mnemonics. */
876 #define CBLT (0)
877 #define CBGT (1)
878 #define CBEQ (2)
879 #define CBSO (3)
880
881 /* The TO encodings used in extended trap mnemonics. */
882 #define TOLGT (0x1)
883 #define TOLLT (0x2)
884 #define TOEQ (0x4)
885 #define TOLGE (0x5)
886 #define TOLNL (0x5)
887 #define TOLLE (0x6)
888 #define TOLNG (0x6)
889 #define TOGT (0x8)
890 #define TOGE (0xc)
891 #define TONL (0xc)
892 #define TOLT (0x10)
893 #define TOLE (0x14)
894 #define TONG (0x14)
895 #define TONE (0x18)
896 #define TOU (0x1f)
897
898 /* Smaller names for the flags so each entry in the opcodes table will
899 fit on a single line. */
900 #undef PPC
901 #define PPC PPC_OPCODE_PPC
902 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
903 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
904 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
905 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
906
907 /* The opcode table.
908
909 The format of the opcode table is:
910
911 NAME OPCODE MASK FLAGS { OPERANDS }
912
913 NAME is the name of the instruction.
914 OPCODE is the instruction opcode.
915 MASK is the opcode mask; this is used to tell the disassembler
916 which bits in the actual opcode must match OPCODE.
917 FLAGS are flags indicated what processors support the instruction.
918 OPERANDS is the list of operands.
919
920 The disassembler reads the table in order and prints the first
921 instruction which matches, so this table is sorted to put more
922 specific instructions before more general instructions. It is also
923 sorted by major opcode. */
924
925 static const struct powerpc_opcode powerpc_opcodes[] = {
926
927 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
928 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
929 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
930 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
931 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
932
933 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
934 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SI } },
935
936 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
937 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SI } },
938 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
939 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
940 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
941 { "b", B(18,0,0), B_MASK, COM, { LI } },
942 { "bl", B(18,0,1), B_MASK, COM, { LI } },
943 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
944 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
945 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
946
947 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
948 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
949 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
950 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
951 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
952 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
953 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
954 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
955 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
956 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
957 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
958 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
959 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
960 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
961 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
962 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
963 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
964 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
965 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
966 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
967 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
968 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
969 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
970 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
971 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
972 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
973 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
974 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
975 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
976 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
977 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
978 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
979
980 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
981 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
982 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
983 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
984 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
985 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
986 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
987 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
988 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
989 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
990 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
991 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
992
993 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
994 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
995 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
996 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
997 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
998 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
999 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
1000 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
1001 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
1002 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
1003 };
1004