1 # MIPS Make68K - V0.30 - Copyright 2005, Manuel Geran (bdiamond@free.fr)
2 #   based on Make68K - Copyright 1998, Mike Coates (mame@btinternet.com)
3 #                                    & Darren Olafson (deo@mail.island.net)
4		 .set arch=allegrex
5
6		 .set noreorder
7		 .set nomacro
8		 .set nobopt
9 #		 .set noat
10
11		 .globl M68000_RUN
12		 .globl M68000_RESET
13		 .globl M68000_regs
14		 .globl M68000_OPCODETABLE
15		 .globl a68k_memory_intf
16
17
18 # Vars Mame declares / needs access to
19
20		 .extern m68k_ICount,4
21		 .extern OP_ROM,4
22		 .extern OP_RAM,4
23		 .extern mem_amask,4
24		 .extern mame_debug,4
25		 .extern illegal_op,4
26		 .extern illegal_pc,4
27		 .extern opcode_entry,4
28		 .extern cur_mrhard,4
29
30
31
32		 .text
33
34	 .ent   M68000_RESET
35M68000_RESET:
36		 .frame $29, 0, $31
37		 jr    $31
38		 nop			 # Delay slot
39
40	 .end   M68000_RESET
41
42
43	 .ent   M68000_RUN
44M68000_RUN:
45		 addiu $29,$29,-112
46		 .frame $29, 112, $31
47
48		 sw    $16,0x48($29)
49		 sw    $17,0x4C($29)
50		 sw    $18,0x50($29)
51		 sw    $19,0x54($29)
52		 sw    $20,0x58($29)
53		 sw    $21,0x5C($29)
54		 sw    $22,0x60($29)
55		 sw    $23,0x64($29)
56		 sw    $30,0x68($29)
57		 sw    $31,0x6C($29)
58		 la    $21,M68000_regs
59		 lbu   $8,0x50($21)
60		 xori  $9,$8,0x80
61		 lw    $15,m68k_ICount
62		 beq   $9,$0,MC68Kexit
63		 movz  $15,$0,$9		 # Delay slot
64		 la    $30,M68000_OPCODETABLE
65		 lw    $22,OP_ROM
66		 lw    $23,0x4C($21)
67		 lw    $2,0x48($21)
68		 addu  $23,$22,$23
69		 or    $20,$0,$2
70		 or    $19,$0,$2
71		 or    $18,$0,$2
72		 or    $17,$0,$2
73		 or    $16,$0,$2
74		 andi  $20,$20,0x10
75		 andi  $19,$19,0x08
76		 andi  $18,$18,0x04
77		 andi  $17,$17,0x02
78		 andi  $16,$16,0x01
79		 srl   $20,$20,4
80		 srl   $19,$19,3
81		 srl   $18,$18,2
82		 srl   $17,$17,1
83 # Check for Interrupt waiting
84
85		 andi  $8,$8,0x07
86		 bne   $8,$0,interrupt
87
88		 nop			 # Delay slot
89
90IntCont:
91		 bltz  $15,MainExit
92		 lhu   $24,0x00($23)		 # Delay slot
93
94		 sll   $7,$24,2
95		 addu  $7,$7,$30
96
97		 lw    $7,0x00($7)
98
99		 jr    $7
100		 nop			 # Delay slot
101
102MainExit:
103		 subu  $23,$23,$22
104		 sw    $23,0x4C($21)		 # Save PC
105		 or    $2,$0,$20
106		 sll   $2,$2,1
107		 or    $2,$2,$19
108		 sll   $2,$2,1
109		 or    $2,$2,$18
110		 sll   $2,$2,1
111		 or    $2,$2,$17
112		 sll   $2,$2,1
113		 or    $2,$2,$16
114		 lw    $8,0x44($21)
115		 sw    $2,0x48($21)
116		 andi  $8,$8,0x20
117		 bne   $8,$0,ME1		 # Mode ?
118		 lw    $2,0x3C($21)		 # Delay slot - Get A7
119		 bgez  $0,MC68Kexit
120		 sw    $2,0x68($21)		 # Delay slot - Save in USP
121ME1:
122		 sw    $2,0x40($21)		 # Save in ISP
123MC68Kexit:
124		 sw    $15,m68k_ICount
125		 lw    $16,0x48($29)
126		 lw    $17,0x4C($29)
127		 lw    $18,0x50($29)
128		 lw    $19,0x54($29)
129		 lw    $20,0x58($29)
130		 lw    $21,0x5C($29)
131		 lw    $22,0x60($29)
132		 lw    $23,0x64($29)
133		 lw    $30,0x68($29)
134		 lw    $31,0x6C($29)
135		 jr    $31
136		 addiu $29,$29,112		 # Delay slot
137	 .end   M68000_RUN
138
139
140 # Interrupt check
141
142interrupt:
143		 lbu   $9,0x50($21)
144		 andi  $2,$9,0x07
145		 xori  $8,$2,0x07		 # Always take 7
146		 beq   $8,$0,procint
147		 nop			 # Delay slot
148
149		 lbu   $3,0x44($21)		 # int mask
150		 andi  $3,$3,0x07
151		 subu  $8,$2,$3
152		 blez  $8,IntCont
153		 nop			 # Delay slot
154
155procint:
156		 andi  $9,$9,0x7f		 # remove stop
157		 sb    $9,0x50($21)
158
159		 lw    $25,0x54($21)
160		 sw    $2,0x44($29)		 # save level
161
162		 sw    $2,0x40($29)
163		 sw    $15,m68k_ICount
164		 jalr  $25	 # get the IRQ level
165		 or    $4,$0,$2		 # irq line #		    Delay slot
166		 lw    $15,m68k_ICount
167		 bgez  $2,AUTOVECTOR
168		 lw    $3,0x40($29)		 # Delay slot
169		 addiu $2,$3,24		 # Vector
170
171AUTOVECTOR:
172
173		 jal   Exception
174		 nop                    	 # Delay slot
175
176		 lbu   $3,0x44($21)		 # set Int mask
177		 lw    $2,0x44($29)
178		 andi  $3,$3,0xF8
179		 or    $3,$3,$2
180		 bgez  $0,IntCont
181		 sb    $3,0x44($21)		 # Delay slot
182
183	 .ent   Exception
184Exception:
185		 addiu $29,$29,-48
186		 .frame $29, 48, $31
187
188		 sw    $31,0x2C($29)
189		 sb    $2,0x28($29)		 # Save IRQ Vector for Later
190		 la    $8,exception_cycles
191		 addu  $2,$2,$8
192		 lbu   $2,0x00($2)		 # Get Cycles
193		 subu  $15,$15,$2		 # Decrement ICount
194		 lbu   $2,0x44($21)
195		 sll   $2,$2,4
196		 or    $2,$2,$20
197		 sll   $2,$2,1
198		 or    $2,$2,$19
199		 sll   $2,$2,1
200		 or    $2,$2,$18
201		 sll   $2,$2,1
202		 or    $2,$2,$17
203		 sll   $2,$2,1
204		 or    $2,$2,$16
205		 andi  $25,$2,0x2000			 # Which Mode ?
206		 bne   $25,$0,ExSuperMode		 # Supervisor
207		 lw    $4,0x3C($21)			 # Delay slot - Get A7
208		 srl   $25,$2,8
209		 ori   $25,$25,0x20
210		 sb    $25,0x44($21)			 # Set Supervisor Mode
211		 sw    $4,0x68($21)			 # Save in USP
212		 lw    $4,0x40($21)			 # Get ISP
213ExSuperMode:
214		 addiu $4,$4,-6
215		 sw    $4,0x3C($21)			 # Put in A7
216		 lw    $25,0x8C($21)
217		 sw    $15,m68k_ICount
218		 sw    $4,0x24($29)
219		 or    $5,$0,$2
220		 jalr  $25
221		 sw    $23,0x4C($21)    	 # Delay slot
222		 lw    $4,0x24($29)
223		 lw    $15,m68k_ICount
224		 subu  $5,$23,$22
225		 addiu $4,$4,2
226		 lw    $25,0x90($21)
227		 sw    $15,m68k_ICount
228		 jalr  $25
229		 sw    $23,0x4C($21)    	 # Delay slot
230		 lw    $15,m68k_ICount
231		 lbu   $2,0x28($29)		 # Level
232		 lw    $25,0x6C($21)
233		 sll   $2,$2,2
234		 addu  $4,$2,$25
235		 lw    $25,0x84($21)
236		 sw    $15,m68k_ICount
237		 jalr  $25
238		 sw    $23,0x4C($21)    	 # Delay slot
239		 lw    $15,m68k_ICount
240		 andi  $25,$2,0x01
241		 beq   $25,$0,2f
242		 addu  $23,$22,$2     	 # Delay slot
243		 addiu $23,$23,-2
244		 jal   Exception
245		 ori   $2,$0,3
246
247		 bgez  $15,3f
248		 lhu   $24,0x00($23)    	 # Delay slot
249		 j     MainExit
250	3:
251		 sll   $7,$24,2         	 # Delay slot
252		 addu  $7,$7,$30
253		 lw    $7,0x00($7)
254		 jr    $7
255		 nop                    	 # Delay slot
256
257	2:
258		 sw    $2,0x74($21)
259		 lw    $6,mem_amask
260		 lw    $25,0x94($21)
261		 and   $23,$2,$6
262		 sw    $15,m68k_ICount
263		 jalr  $25
264		 or    $4,$0,$23   	 # Delay slot
265		 lw    $15,m68k_ICount
266		 lw    $22,OP_ROM
267		 addu  $23,$23,$22
268 # End of Banking code:
269		 lw    $31,0x2C($29)
270		 jr    $31
271		 addiu $29,$29,48		 # Delay slot
272
273	 .end   Exception
274
275
276
277
278OP0_1000:				#:
279		 addiu $23,$23,2
280
281		 and   $8,$24,0x0f
282		 sll   $8,$8,2
283		 addu  $8,$8,$21
284		 lbu   $2,0x00($8)
285		 and   $16,$0,$0        	 # Clear Carry
286		 and   $17,$0,$0        	 # Clear Overflow
287		 srl   $19,$2,7         	 # Set Sign
288		 sltiu $18,$2,1         	 # Set Zero
289		 srl   $24,$24,7
290		 andi  $24,$24,0x1C
291		 addu  $24,$24,$21
292		 sb    $2,0x00($24)
293		 addiu $15,$15,-4
294		 bgez  $15,3f
295		 lhu   $24,0x00($23)    	 # Delay slot
296		 j     MainExit
297	3:
298		 sll   $7,$24,2         	 # Delay slot
299		 addu  $7,$7,$30
300		 lw    $7,0x00($7)
301		 jr    $7
302		 nop                    	 # Delay slot
303
304OP0_1010:				#:
305		 addiu $23,$23,2
306
307		 and   $8,$24,0x07
308		 sll   $8,$8,2
309		 addu  $8,$8,$21
310		 lw    $14,0x20($8)
311		 lw    $25,0x7C($21)
312		 sw    $15,m68k_ICount
313		 sw    $24,0x44($29)
314		 or    $4,$0,$14
315		 jalr  $25
316		 sw    $23,0x4C($21)    	 # Delay slot
317		 lw    $24,0x44($29)
318		 lw    $15,m68k_ICount
319		 and   $16,$0,$0        	 # Clear Carry
320		 and   $17,$0,$0        	 # Clear Overflow
321		 srl   $19,$2,7         	 # Set Sign
322		 sltiu $18,$2,1         	 # Set Zero
323		 srl   $24,$24,7
324		 andi  $24,$24,0x1C
325		 addu  $24,$24,$21
326		 sb    $2,0x00($24)
327		 addiu $15,$15,-8
328		 bgez  $15,3f
329		 lhu   $24,0x00($23)    	 # Delay slot
330		 j     MainExit
331	3:
332		 sll   $7,$24,2         	 # Delay slot
333		 addu  $7,$7,$30
334		 lw    $7,0x00($7)
335		 jr    $7
336		 nop                    	 # Delay slot
337
338OP0_1018:				#:
339		 addiu $23,$23,2
340
341		 and   $8,$24,0x07
342		 sll   $8,$8,2
343		 addu  $8,$8,$21
344		 lw    $14,0x20($8)
345		 addiu $25,$14,1
346		 sw    $25,0x20($8)
347		 lw    $25,0x7C($21)
348		 sw    $15,m68k_ICount
349		 sw    $24,0x44($29)
350		 or    $4,$0,$14
351		 jalr  $25
352		 sw    $23,0x4C($21)    	 # Delay slot
353		 lw    $24,0x44($29)
354		 lw    $15,m68k_ICount
355		 and   $16,$0,$0        	 # Clear Carry
356		 and   $17,$0,$0        	 # Clear Overflow
357		 srl   $19,$2,7         	 # Set Sign
358		 sltiu $18,$2,1         	 # Set Zero
359		 srl   $24,$24,7
360		 andi  $24,$24,0x1C
361		 addu  $24,$24,$21
362		 sb    $2,0x00($24)
363		 addiu $15,$15,-8
364		 bgez  $15,3f
365		 lhu   $24,0x00($23)    	 # Delay slot
366		 j     MainExit
367	3:
368		 sll   $7,$24,2         	 # Delay slot
369		 addu  $7,$7,$30
370		 lw    $7,0x00($7)
371		 jr    $7
372		 nop                    	 # Delay slot
373
374OP0_101f:				#:
375		 addiu $23,$23,2
376
377		 lw    $14,0x3C($21)    	 # Get A7
378		 addiu $25,$14,2
379		 sw    $25,0x3C($21)
380		 lw    $25,0x7C($21)
381		 sw    $15,m68k_ICount
382		 sw    $24,0x44($29)
383		 or    $4,$0,$14
384		 jalr  $25
385		 sw    $23,0x4C($21)    	 # Delay slot
386		 lw    $24,0x44($29)
387		 lw    $15,m68k_ICount
388		 and   $16,$0,$0        	 # Clear Carry
389		 and   $17,$0,$0        	 # Clear Overflow
390		 srl   $19,$2,7         	 # Set Sign
391		 sltiu $18,$2,1         	 # Set Zero
392		 srl   $24,$24,7
393		 andi  $24,$24,0x1C
394		 addu  $24,$24,$21
395		 sb    $2,0x00($24)
396		 addiu $15,$15,-8
397		 bgez  $15,3f
398		 lhu   $24,0x00($23)    	 # Delay slot
399		 j     MainExit
400	3:
401		 sll   $7,$24,2         	 # Delay slot
402		 addu  $7,$7,$30
403		 lw    $7,0x00($7)
404		 jr    $7
405		 nop                    	 # Delay slot
406
407OP0_1020:				#:
408		 addiu $23,$23,2
409
410		 and   $8,$24,0x07
411		 sll   $8,$8,2
412		 addu  $8,$8,$21
413		 lw    $14,0x20($8)
414		 addiu $14,$14,-1
415		 sw    $14,0x20($8)
416		 lw    $25,0x7C($21)
417		 sw    $15,m68k_ICount
418		 sw    $24,0x44($29)
419		 or    $4,$0,$14
420		 jalr  $25
421		 sw    $23,0x4C($21)    	 # Delay slot
422		 lw    $24,0x44($29)
423		 lw    $15,m68k_ICount
424		 and   $16,$0,$0        	 # Clear Carry
425		 and   $17,$0,$0        	 # Clear Overflow
426		 srl   $19,$2,7         	 # Set Sign
427		 sltiu $18,$2,1         	 # Set Zero
428		 srl   $24,$24,7
429		 andi  $24,$24,0x1C
430		 addu  $24,$24,$21
431		 sb    $2,0x00($24)
432		 addiu $15,$15,-10
433		 bgez  $15,3f
434		 lhu   $24,0x00($23)    	 # Delay slot
435		 j     MainExit
436	3:
437		 sll   $7,$24,2         	 # Delay slot
438		 addu  $7,$7,$30
439		 lw    $7,0x00($7)
440		 jr    $7
441		 nop                    	 # Delay slot
442
443OP0_1027:				#:
444		 addiu $23,$23,2
445
446		 lw    $14,0x3C($21)    	 # Get A7
447		 addiu $14,$14,-2
448		 sw    $14,0x3C($21)
449		 lw    $25,0x7C($21)
450		 sw    $15,m68k_ICount
451		 sw    $24,0x44($29)
452		 or    $4,$0,$14
453		 jalr  $25
454		 sw    $23,0x4C($21)    	 # Delay slot
455		 lw    $24,0x44($29)
456		 lw    $15,m68k_ICount
457		 and   $16,$0,$0        	 # Clear Carry
458		 and   $17,$0,$0        	 # Clear Overflow
459		 srl   $19,$2,7         	 # Set Sign
460		 sltiu $18,$2,1         	 # Set Zero
461		 srl   $24,$24,7
462		 andi  $24,$24,0x1C
463		 addu  $24,$24,$21
464		 sb    $2,0x00($24)
465		 addiu $15,$15,-10
466		 bgez  $15,3f
467		 lhu   $24,0x00($23)    	 # Delay slot
468		 j     MainExit
469	3:
470		 sll   $7,$24,2         	 # Delay slot
471		 addu  $7,$7,$30
472		 lw    $7,0x00($7)
473		 jr    $7
474		 nop                    	 # Delay slot
475
476OP0_1028:				#:
477		 addiu $23,$23,2
478
479		 and   $8,$24,0x07
480		 lh    $7,0x00($23)
481		 sll   $8,$8,2
482		 addu  $8,$8,$21
483		 lw    $14,0x20($8)
484		 addiu $23,$23,2
485		 addu  $14,$14,$7
486		 lw    $25,0x7C($21)
487		 sw    $15,m68k_ICount
488		 sw    $24,0x44($29)
489		 or    $4,$0,$14
490		 jalr  $25
491		 sw    $23,0x4C($21)    	 # Delay slot
492		 lw    $24,0x44($29)
493		 lw    $15,m68k_ICount
494		 and   $16,$0,$0        	 # Clear Carry
495		 and   $17,$0,$0        	 # Clear Overflow
496		 srl   $19,$2,7         	 # Set Sign
497		 sltiu $18,$2,1         	 # Set Zero
498		 srl   $24,$24,7
499		 andi  $24,$24,0x1C
500		 addu  $24,$24,$21
501		 sb    $2,0x00($24)
502		 addiu $15,$15,-12
503		 bgez  $15,3f
504		 lhu   $24,0x00($23)    	 # Delay slot
505		 j     MainExit
506	3:
507		 sll   $7,$24,2         	 # Delay slot
508		 addu  $7,$7,$30
509		 lw    $7,0x00($7)
510		 jr    $7
511		 nop                    	 # Delay slot
512
513OP0_1030:				#:
514		 addiu $23,$23,2
515
516		 and   $8,$24,0x07
517		 sll   $8,$8,2
518		 addu  $8,$8,$21
519		 lw    $14,0x20($8)
520		 lhu   $7,0x00($23)
521		 addiu $23,$23,2
522		 seb   $6,$7
523		 or    $25,$0,$7
524		 srl   $7,$7,12
525		 andi  $25,$25,0x0800
526		 sll   $7,$7,2
527		 addu  $7,$7,$21
528		 bne   $25,$0,0f
529		 lw    $25,0x00($7)      	 # Delay slot
530		 seh   $25,$25
531	0:
532		 addu  $25,$14,$25
533		 addu  $14,$25,$6
534		 lw    $25,0x7C($21)
535		 sw    $15,m68k_ICount
536		 sw    $24,0x44($29)
537		 or    $4,$0,$14
538		 jalr  $25
539		 sw    $23,0x4C($21)    	 # Delay slot
540		 lw    $24,0x44($29)
541		 lw    $15,m68k_ICount
542		 and   $16,$0,$0        	 # Clear Carry
543		 and   $17,$0,$0        	 # Clear Overflow
544		 srl   $19,$2,7         	 # Set Sign
545		 sltiu $18,$2,1         	 # Set Zero
546		 srl   $24,$24,7
547		 andi  $24,$24,0x1C
548		 addu  $24,$24,$21
549		 sb    $2,0x00($24)
550		 addiu $15,$15,-14
551		 bgez  $15,3f
552		 lhu   $24,0x00($23)    	 # Delay slot
553		 j     MainExit
554	3:
555		 sll   $7,$24,2         	 # Delay slot
556		 addu  $7,$7,$30
557		 lw    $7,0x00($7)
558		 jr    $7
559		 nop                    	 # Delay slot
560
561OP0_1038:				#:
562		 addiu $23,$23,2
563
564		 lh    $14,0x00($23)
565		 addiu $23,$23,2
566		 lw    $25,0x7C($21)
567		 sw    $15,m68k_ICount
568		 sw    $24,0x44($29)
569		 or    $4,$0,$14
570		 jalr  $25
571		 sw    $23,0x4C($21)    	 # Delay slot
572		 lw    $24,0x44($29)
573		 lw    $15,m68k_ICount
574		 and   $16,$0,$0        	 # Clear Carry
575		 and   $17,$0,$0        	 # Clear Overflow
576		 srl   $19,$2,7         	 # Set Sign
577		 sltiu $18,$2,1         	 # Set Zero
578		 srl   $24,$24,7
579		 andi  $24,$24,0x1C
580		 addu  $24,$24,$21
581		 sb    $2,0x00($24)
582		 addiu $15,$15,-12
583		 bgez  $15,3f
584		 lhu   $24,0x00($23)    	 # Delay slot
585		 j     MainExit
586	3:
587		 sll   $7,$24,2         	 # Delay slot
588		 addu  $7,$7,$30
589		 lw    $7,0x00($7)
590		 jr    $7
591		 nop                    	 # Delay slot
592
593OP0_1039:				#:
594		 addiu $23,$23,2
595
596		 lhu   $14,0x00($23)
597		 lhu   $25,0x02($23)
598		 sll   $14,$14,16
599		 or    $14,$14,$25
600		 addiu $23,$23,4
601		 lw    $25,0x7C($21)
602		 sw    $15,m68k_ICount
603		 sw    $24,0x44($29)
604		 or    $4,$0,$14
605		 jalr  $25
606		 sw    $23,0x4C($21)    	 # Delay slot
607		 lw    $24,0x44($29)
608		 lw    $15,m68k_ICount
609		 and   $16,$0,$0        	 # Clear Carry
610		 and   $17,$0,$0        	 # Clear Overflow
611		 srl   $19,$2,7         	 # Set Sign
612		 sltiu $18,$2,1         	 # Set Zero
613		 srl   $24,$24,7
614		 andi  $24,$24,0x1C
615		 addu  $24,$24,$21
616		 sb    $2,0x00($24)
617		 addiu $15,$15,-16
618		 bgez  $15,3f
619		 lhu   $24,0x00($23)    	 # Delay slot
620		 j     MainExit
621	3:
622		 sll   $7,$24,2         	 # Delay slot
623		 addu  $7,$7,$30
624		 lw    $7,0x00($7)
625		 jr    $7
626		 nop                    	 # Delay slot
627
628OP0_103a:				#:
629		 addiu $23,$23,2
630
631		 lh    $7,0x00($23)
632		 subu  $25,$23,$22
633		 addu  $14,$25,$7       	 # Add Offset to PC
634		 addiu $23,$23,2
635		 lw    $25,0x98($21)
636		 sw    $15,m68k_ICount
637		 sw    $24,0x44($29)
638		 or    $4,$0,$14
639		 jalr  $25
640		 sw    $23,0x4C($21)    	 # Delay slot
641		 lw    $24,0x44($29)
642		 lw    $15,m68k_ICount
643		 and   $16,$0,$0        	 # Clear Carry
644		 and   $17,$0,$0        	 # Clear Overflow
645		 srl   $19,$2,7         	 # Set Sign
646		 sltiu $18,$2,1         	 # Set Zero
647		 srl   $24,$24,7
648		 andi  $24,$24,0x1C
649		 addu  $24,$24,$21
650		 sb    $2,0x00($24)
651		 addiu $15,$15,-12
652		 bgez  $15,3f
653		 lhu   $24,0x00($23)    	 # Delay slot
654		 j     MainExit
655	3:
656		 sll   $7,$24,2         	 # Delay slot
657		 addu  $7,$7,$30
658		 lw    $7,0x00($7)
659		 jr    $7
660		 nop                    	 # Delay slot
661
662OP0_103b:				#:
663		 addiu $23,$23,2
664
665		 subu  $14,$23,$22       	 # Get PC
666		 lhu   $7,0x00($23)
667		 addiu $23,$23,2
668		 seb   $6,$7
669		 or    $25,$0,$7
670		 srl   $7,$7,12
671		 andi  $25,$25,0x0800
672		 sll   $7,$7,2
673		 addu  $7,$7,$21
674		 bne   $25,$0,0f
675		 lw    $25,0x00($7)      	 # Delay slot
676		 seh   $25,$25
677	0:
678		 addu  $25,$14,$25
679		 addu  $14,$25,$6
680		 lw    $25,0x98($21)
681		 sw    $15,m68k_ICount
682		 sw    $24,0x44($29)
683		 or    $4,$0,$14
684		 jalr  $25
685		 sw    $23,0x4C($21)    	 # Delay slot
686		 lw    $24,0x44($29)
687		 lw    $15,m68k_ICount
688		 and   $16,$0,$0        	 # Clear Carry
689		 and   $17,$0,$0        	 # Clear Overflow
690		 srl   $19,$2,7         	 # Set Sign
691		 sltiu $18,$2,1         	 # Set Zero
692		 srl   $24,$24,7
693		 andi  $24,$24,0x1C
694		 addu  $24,$24,$21
695		 sb    $2,0x00($24)
696		 addiu $15,$15,-14
697		 bgez  $15,3f
698		 lhu   $24,0x00($23)    	 # Delay slot
699		 j     MainExit
700	3:
701		 sll   $7,$24,2         	 # Delay slot
702		 addu  $7,$7,$30
703		 lw    $7,0x00($7)
704		 jr    $7
705		 nop                    	 # Delay slot
706
707OP0_103c:				#:
708		 addiu $23,$23,2
709
710		 lbu   $2,0x00($23)
711		 addiu $23,$23,2
712		 and   $16,$0,$0        	 # Clear Carry
713		 and   $17,$0,$0        	 # Clear Overflow
714		 srl   $19,$2,7         	 # Set Sign
715		 sltiu $18,$2,1         	 # Set Zero
716		 srl   $24,$24,7
717		 andi  $24,$24,0x1C
718		 addu  $24,$24,$21
719		 sb    $2,0x00($24)
720		 addiu $15,$15,-4
721		 bgez  $15,3f
722		 lhu   $24,0x00($23)    	 # Delay slot
723		 j     MainExit
724	3:
725		 sll   $7,$24,2         	 # Delay slot
726		 addu  $7,$7,$30
727		 lw    $7,0x00($7)
728		 jr    $7
729		 nop                    	 # Delay slot
730
731OP0_1080:				#:
732		 addiu $23,$23,2
733
734		 and   $8,$24,0x0f
735		 sll   $8,$8,2
736		 addu  $8,$8,$21
737		 lbu   $2,0x00($8)
738		 and   $16,$0,$0        	 # Clear Carry
739		 and   $17,$0,$0        	 # Clear Overflow
740		 srl   $19,$2,7         	 # Set Sign
741		 sltiu $18,$2,1         	 # Set Zero
742		 srl   $24,$24,7
743		 andi  $24,$24,0x1C
744		 addu  $24,$24,$21
745		 lw    $14,0x20($24)
746		 lw    $25,0x88($21)
747		 sw    $15,m68k_ICount
748		 or    $5,$0,$2
749		 or    $4,$0,$14
750		 jalr  $25
751		 sw    $23,0x4C($21)    	 # Delay slot
752		 lw    $15,m68k_ICount
753		 addiu $15,$15,-8
754		 bgez  $15,3f
755		 lhu   $24,0x00($23)    	 # Delay slot
756		 j     MainExit
757	3:
758		 sll   $7,$24,2         	 # Delay slot
759		 addu  $7,$7,$30
760		 lw    $7,0x00($7)
761		 jr    $7
762		 nop                    	 # Delay slot
763
764OP0_1090:				#:
765		 addiu $23,$23,2
766
767		 and   $8,$24,0x07
768		 sll   $8,$8,2
769		 addu  $8,$8,$21
770		 lw    $14,0x20($8)
771		 lw    $25,0x7C($21)
772		 sw    $15,m68k_ICount
773		 sw    $24,0x44($29)
774		 or    $4,$0,$14
775		 jalr  $25
776		 sw    $23,0x4C($21)    	 # Delay slot
777		 lw    $24,0x44($29)
778		 lw    $15,m68k_ICount
779		 and   $16,$0,$0        	 # Clear Carry
780		 and   $17,$0,$0        	 # Clear Overflow
781		 srl   $19,$2,7         	 # Set Sign
782		 sltiu $18,$2,1         	 # Set Zero
783		 srl   $24,$24,7
784		 andi  $24,$24,0x1C
785		 addu  $24,$24,$21
786		 lw    $14,0x20($24)
787		 lw    $25,0x88($21)
788		 sw    $15,m68k_ICount
789		 or    $5,$0,$2
790		 or    $4,$0,$14
791		 jalr  $25
792		 sw    $23,0x4C($21)    	 # Delay slot
793		 lw    $15,m68k_ICount
794		 addiu $15,$15,-12
795		 bgez  $15,3f
796		 lhu   $24,0x00($23)    	 # Delay slot
797		 j     MainExit
798	3:
799		 sll   $7,$24,2         	 # Delay slot
800		 addu  $7,$7,$30
801		 lw    $7,0x00($7)
802		 jr    $7
803		 nop                    	 # Delay slot
804
805OP0_1098:				#:
806		 addiu $23,$23,2
807
808		 and   $8,$24,0x07
809		 sll   $8,$8,2
810		 addu  $8,$8,$21
811		 lw    $14,0x20($8)
812		 addiu $25,$14,1
813		 sw    $25,0x20($8)
814		 lw    $25,0x7C($21)
815		 sw    $15,m68k_ICount
816		 sw    $24,0x44($29)
817		 or    $4,$0,$14
818		 jalr  $25
819		 sw    $23,0x4C($21)    	 # Delay slot
820		 lw    $24,0x44($29)
821		 lw    $15,m68k_ICount
822		 and   $16,$0,$0        	 # Clear Carry
823		 and   $17,$0,$0        	 # Clear Overflow
824		 srl   $19,$2,7         	 # Set Sign
825		 sltiu $18,$2,1         	 # Set Zero
826		 srl   $24,$24,7
827		 andi  $24,$24,0x1C
828		 addu  $24,$24,$21
829		 lw    $14,0x20($24)
830		 lw    $25,0x88($21)
831		 sw    $15,m68k_ICount
832		 or    $5,$0,$2
833		 or    $4,$0,$14
834		 jalr  $25
835		 sw    $23,0x4C($21)    	 # Delay slot
836		 lw    $15,m68k_ICount
837		 addiu $15,$15,-12
838		 bgez  $15,3f
839		 lhu   $24,0x00($23)    	 # Delay slot
840		 j     MainExit
841	3:
842		 sll   $7,$24,2         	 # Delay slot
843		 addu  $7,$7,$30
844		 lw    $7,0x00($7)
845		 jr    $7
846		 nop                    	 # Delay slot
847
848OP0_109f:				#:
849		 addiu $23,$23,2
850
851		 lw    $14,0x3C($21)    	 # Get A7
852		 addiu $25,$14,2
853		 sw    $25,0x3C($21)
854		 lw    $25,0x7C($21)
855		 sw    $15,m68k_ICount
856		 sw    $24,0x44($29)
857		 or    $4,$0,$14
858		 jalr  $25
859		 sw    $23,0x4C($21)    	 # Delay slot
860		 lw    $24,0x44($29)
861		 lw    $15,m68k_ICount
862		 and   $16,$0,$0        	 # Clear Carry
863		 and   $17,$0,$0        	 # Clear Overflow
864		 srl   $19,$2,7         	 # Set Sign
865		 sltiu $18,$2,1         	 # Set Zero
866		 srl   $24,$24,7
867		 andi  $24,$24,0x1C
868		 addu  $24,$24,$21
869		 lw    $14,0x20($24)
870		 lw    $25,0x88($21)
871		 sw    $15,m68k_ICount
872		 or    $5,$0,$2
873		 or    $4,$0,$14
874		 jalr  $25
875		 sw    $23,0x4C($21)    	 # Delay slot
876		 lw    $15,m68k_ICount
877		 addiu $15,$15,-12
878		 bgez  $15,3f
879		 lhu   $24,0x00($23)    	 # Delay slot
880		 j     MainExit
881	3:
882		 sll   $7,$24,2         	 # Delay slot
883		 addu  $7,$7,$30
884		 lw    $7,0x00($7)
885		 jr    $7
886		 nop                    	 # Delay slot
887
888OP0_10a0:				#:
889		 addiu $23,$23,2
890
891		 and   $8,$24,0x07
892		 sll   $8,$8,2
893		 addu  $8,$8,$21
894		 lw    $14,0x20($8)
895		 addiu $14,$14,-1
896		 sw    $14,0x20($8)
897		 lw    $25,0x7C($21)
898		 sw    $15,m68k_ICount
899		 sw    $24,0x44($29)
900		 or    $4,$0,$14
901		 jalr  $25
902		 sw    $23,0x4C($21)    	 # Delay slot
903		 lw    $24,0x44($29)
904		 lw    $15,m68k_ICount
905		 and   $16,$0,$0        	 # Clear Carry
906		 and   $17,$0,$0        	 # Clear Overflow
907		 srl   $19,$2,7         	 # Set Sign
908		 sltiu $18,$2,1         	 # Set Zero
909		 srl   $24,$24,7
910		 andi  $24,$24,0x1C
911		 addu  $24,$24,$21
912		 lw    $14,0x20($24)
913		 lw    $25,0x88($21)
914		 sw    $15,m68k_ICount
915		 or    $5,$0,$2
916		 or    $4,$0,$14
917		 jalr  $25
918		 sw    $23,0x4C($21)    	 # Delay slot
919		 lw    $15,m68k_ICount
920		 addiu $15,$15,-14
921		 bgez  $15,3f
922		 lhu   $24,0x00($23)    	 # Delay slot
923		 j     MainExit
924	3:
925		 sll   $7,$24,2         	 # Delay slot
926		 addu  $7,$7,$30
927		 lw    $7,0x00($7)
928		 jr    $7
929		 nop                    	 # Delay slot
930
931OP0_10a7:				#:
932		 addiu $23,$23,2
933
934		 lw    $14,0x3C($21)    	 # Get A7
935		 addiu $14,$14,-2
936		 sw    $14,0x3C($21)
937		 lw    $25,0x7C($21)
938		 sw    $15,m68k_ICount
939		 sw    $24,0x44($29)
940		 or    $4,$0,$14
941		 jalr  $25
942		 sw    $23,0x4C($21)    	 # Delay slot
943		 lw    $24,0x44($29)
944		 lw    $15,m68k_ICount
945		 and   $16,$0,$0        	 # Clear Carry
946		 and   $17,$0,$0        	 # Clear Overflow
947		 srl   $19,$2,7         	 # Set Sign
948		 sltiu $18,$2,1         	 # Set Zero
949		 srl   $24,$24,7
950		 andi  $24,$24,0x1C
951		 addu  $24,$24,$21
952		 lw    $14,0x20($24)
953		 lw    $25,0x88($21)
954		 sw    $15,m68k_ICount
955		 or    $5,$0,$2
956		 or    $4,$0,$14
957		 jalr  $25
958		 sw    $23,0x4C($21)    	 # Delay slot
959		 lw    $15,m68k_ICount
960		 addiu $15,$15,-14
961		 bgez  $15,3f
962		 lhu   $24,0x00($23)    	 # Delay slot
963		 j     MainExit
964	3:
965		 sll   $7,$24,2         	 # Delay slot
966		 addu  $7,$7,$30
967		 lw    $7,0x00($7)
968		 jr    $7
969		 nop                    	 # Delay slot
970
971OP0_10a8:				#:
972		 addiu $23,$23,2
973
974		 and   $8,$24,0x07
975		 lh    $7,0x00($23)
976		 sll   $8,$8,2
977		 addu  $8,$8,$21
978		 lw    $14,0x20($8)
979		 addiu $23,$23,2
980		 addu  $14,$14,$7
981		 lw    $25,0x7C($21)
982		 sw    $15,m68k_ICount
983		 sw    $24,0x44($29)
984		 or    $4,$0,$14
985		 jalr  $25
986		 sw    $23,0x4C($21)    	 # Delay slot
987		 lw    $24,0x44($29)
988		 lw    $15,m68k_ICount
989		 and   $16,$0,$0        	 # Clear Carry
990		 and   $17,$0,$0        	 # Clear Overflow
991		 srl   $19,$2,7         	 # Set Sign
992		 sltiu $18,$2,1         	 # Set Zero
993		 srl   $24,$24,7
994		 andi  $24,$24,0x1C
995		 addu  $24,$24,$21
996		 lw    $14,0x20($24)
997		 lw    $25,0x88($21)
998		 sw    $15,m68k_ICount
999		 or    $5,$0,$2
1000		 or    $4,$0,$14
1001		 jalr  $25
1002		 sw    $23,0x4C($21)    	 # Delay slot
1003		 lw    $15,m68k_ICount
1004		 addiu $15,$15,-16
1005		 bgez  $15,3f
1006		 lhu   $24,0x00($23)    	 # Delay slot
1007		 j     MainExit
1008	3:
1009		 sll   $7,$24,2         	 # Delay slot
1010		 addu  $7,$7,$30
1011		 lw    $7,0x00($7)
1012		 jr    $7
1013		 nop                    	 # Delay slot
1014
1015OP0_10b0:				#:
1016		 addiu $23,$23,2
1017
1018		 and   $8,$24,0x07
1019		 sll   $8,$8,2
1020		 addu  $8,$8,$21
1021		 lw    $14,0x20($8)
1022		 lhu   $7,0x00($23)
1023		 addiu $23,$23,2
1024		 seb   $6,$7
1025		 or    $25,$0,$7
1026		 srl   $7,$7,12
1027		 andi  $25,$25,0x0800
1028		 sll   $7,$7,2
1029		 addu  $7,$7,$21
1030		 bne   $25,$0,0f
1031		 lw    $25,0x00($7)      	 # Delay slot
1032		 seh   $25,$25
1033	0:
1034		 addu  $25,$14,$25
1035		 addu  $14,$25,$6
1036		 lw    $25,0x7C($21)
1037		 sw    $15,m68k_ICount
1038		 sw    $24,0x44($29)
1039		 or    $4,$0,$14
1040		 jalr  $25
1041		 sw    $23,0x4C($21)    	 # Delay slot
1042		 lw    $24,0x44($29)
1043		 lw    $15,m68k_ICount
1044		 and   $16,$0,$0        	 # Clear Carry
1045		 and   $17,$0,$0        	 # Clear Overflow
1046		 srl   $19,$2,7         	 # Set Sign
1047		 sltiu $18,$2,1         	 # Set Zero
1048		 srl   $24,$24,7
1049		 andi  $24,$24,0x1C
1050		 addu  $24,$24,$21
1051		 lw    $14,0x20($24)
1052		 lw    $25,0x88($21)
1053		 sw    $15,m68k_ICount
1054		 or    $5,$0,$2
1055		 or    $4,$0,$14
1056		 jalr  $25
1057		 sw    $23,0x4C($21)    	 # Delay slot
1058		 lw    $15,m68k_ICount
1059		 addiu $15,$15,-18
1060		 bgez  $15,3f
1061		 lhu   $24,0x00($23)    	 # Delay slot
1062		 j     MainExit
1063	3:
1064		 sll   $7,$24,2         	 # Delay slot
1065		 addu  $7,$7,$30
1066		 lw    $7,0x00($7)
1067		 jr    $7
1068		 nop                    	 # Delay slot
1069
1070OP0_10b8:				#:
1071		 addiu $23,$23,2
1072
1073		 lh    $14,0x00($23)
1074		 addiu $23,$23,2
1075		 lw    $25,0x7C($21)
1076		 sw    $15,m68k_ICount
1077		 sw    $24,0x44($29)
1078		 or    $4,$0,$14
1079		 jalr  $25
1080		 sw    $23,0x4C($21)    	 # Delay slot
1081		 lw    $24,0x44($29)
1082		 lw    $15,m68k_ICount
1083		 and   $16,$0,$0        	 # Clear Carry
1084		 and   $17,$0,$0        	 # Clear Overflow
1085		 srl   $19,$2,7         	 # Set Sign
1086		 sltiu $18,$2,1         	 # Set Zero
1087		 srl   $24,$24,7
1088		 andi  $24,$24,0x1C
1089		 addu  $24,$24,$21
1090		 lw    $14,0x20($24)
1091		 lw    $25,0x88($21)
1092		 sw    $15,m68k_ICount
1093		 or    $5,$0,$2
1094		 or    $4,$0,$14
1095		 jalr  $25
1096		 sw    $23,0x4C($21)    	 # Delay slot
1097		 lw    $15,m68k_ICount
1098		 addiu $15,$15,-16
1099		 bgez  $15,3f
1100		 lhu   $24,0x00($23)    	 # Delay slot
1101		 j     MainExit
1102	3:
1103		 sll   $7,$24,2         	 # Delay slot
1104		 addu  $7,$7,$30
1105		 lw    $7,0x00($7)
1106		 jr    $7
1107		 nop                    	 # Delay slot
1108
1109OP0_10b9:				#:
1110		 addiu $23,$23,2
1111
1112		 lhu   $14,0x00($23)
1113		 lhu   $25,0x02($23)
1114		 sll   $14,$14,16
1115		 or    $14,$14,$25
1116		 addiu $23,$23,4
1117		 lw    $25,0x7C($21)
1118		 sw    $15,m68k_ICount
1119		 sw    $24,0x44($29)
1120		 or    $4,$0,$14
1121		 jalr  $25
1122		 sw    $23,0x4C($21)    	 # Delay slot
1123		 lw    $24,0x44($29)
1124		 lw    $15,m68k_ICount
1125		 and   $16,$0,$0        	 # Clear Carry
1126		 and   $17,$0,$0        	 # Clear Overflow
1127		 srl   $19,$2,7         	 # Set Sign
1128		 sltiu $18,$2,1         	 # Set Zero
1129		 srl   $24,$24,7
1130		 andi  $24,$24,0x1C
1131		 addu  $24,$24,$21
1132		 lw    $14,0x20($24)
1133		 lw    $25,0x88($21)
1134		 sw    $15,m68k_ICount
1135		 or    $5,$0,$2
1136		 or    $4,$0,$14
1137		 jalr  $25
1138		 sw    $23,0x4C($21)    	 # Delay slot
1139		 lw    $15,m68k_ICount
1140		 addiu $15,$15,-20
1141		 bgez  $15,3f
1142		 lhu   $24,0x00($23)    	 # Delay slot
1143		 j     MainExit
1144	3:
1145		 sll   $7,$24,2         	 # Delay slot
1146		 addu  $7,$7,$30
1147		 lw    $7,0x00($7)
1148		 jr    $7
1149		 nop                    	 # Delay slot
1150
1151OP0_10ba:				#:
1152		 addiu $23,$23,2
1153
1154		 lh    $7,0x00($23)
1155		 subu  $25,$23,$22
1156		 addu  $14,$25,$7       	 # Add Offset to PC
1157		 addiu $23,$23,2
1158		 lw    $25,0x98($21)
1159		 sw    $15,m68k_ICount
1160		 sw    $24,0x44($29)
1161		 or    $4,$0,$14
1162		 jalr  $25
1163		 sw    $23,0x4C($21)    	 # Delay slot
1164		 lw    $24,0x44($29)
1165		 lw    $15,m68k_ICount
1166		 and   $16,$0,$0        	 # Clear Carry
1167		 and   $17,$0,$0        	 # Clear Overflow
1168		 srl   $19,$2,7         	 # Set Sign
1169		 sltiu $18,$2,1         	 # Set Zero
1170		 srl   $24,$24,7
1171		 andi  $24,$24,0x1C
1172		 addu  $24,$24,$21
1173		 lw    $14,0x20($24)
1174		 lw    $25,0x88($21)
1175		 sw    $15,m68k_ICount
1176		 or    $5,$0,$2
1177		 or    $4,$0,$14
1178		 jalr  $25
1179		 sw    $23,0x4C($21)    	 # Delay slot
1180		 lw    $15,m68k_ICount
1181		 addiu $15,$15,-16
1182		 bgez  $15,3f
1183		 lhu   $24,0x00($23)    	 # Delay slot
1184		 j     MainExit
1185	3:
1186		 sll   $7,$24,2         	 # Delay slot
1187		 addu  $7,$7,$30
1188		 lw    $7,0x00($7)
1189		 jr    $7
1190		 nop                    	 # Delay slot
1191
1192OP0_10bb:				#:
1193		 addiu $23,$23,2
1194
1195		 subu  $14,$23,$22       	 # Get PC
1196		 lhu   $7,0x00($23)
1197		 addiu $23,$23,2
1198		 seb   $6,$7
1199		 or    $25,$0,$7
1200		 srl   $7,$7,12
1201		 andi  $25,$25,0x0800
1202		 sll   $7,$7,2
1203		 addu  $7,$7,$21
1204		 bne   $25,$0,0f
1205		 lw    $25,0x00($7)      	 # Delay slot
1206		 seh   $25,$25
1207	0:
1208		 addu  $25,$14,$25
1209		 addu  $14,$25,$6
1210		 lw    $25,0x98($21)
1211		 sw    $15,m68k_ICount
1212		 sw    $24,0x44($29)
1213		 or    $4,$0,$14
1214		 jalr  $25
1215		 sw    $23,0x4C($21)    	 # Delay slot
1216		 lw    $24,0x44($29)
1217		 lw    $15,m68k_ICount
1218		 and   $16,$0,$0        	 # Clear Carry
1219		 and   $17,$0,$0        	 # Clear Overflow
1220		 srl   $19,$2,7         	 # Set Sign
1221		 sltiu $18,$2,1         	 # Set Zero
1222		 srl   $24,$24,7
1223		 andi  $24,$24,0x1C
1224		 addu  $24,$24,$21
1225		 lw    $14,0x20($24)
1226		 lw    $25,0x88($21)
1227		 sw    $15,m68k_ICount
1228		 or    $5,$0,$2
1229		 or    $4,$0,$14
1230		 jalr  $25
1231		 sw    $23,0x4C($21)    	 # Delay slot
1232		 lw    $15,m68k_ICount
1233		 addiu $15,$15,-18
1234		 bgez  $15,3f
1235		 lhu   $24,0x00($23)    	 # Delay slot
1236		 j     MainExit
1237	3:
1238		 sll   $7,$24,2         	 # Delay slot
1239		 addu  $7,$7,$30
1240		 lw    $7,0x00($7)
1241		 jr    $7
1242		 nop                    	 # Delay slot
1243
1244OP0_10bc:				#:
1245		 addiu $23,$23,2
1246
1247		 lbu   $2,0x00($23)
1248		 addiu $23,$23,2
1249		 and   $16,$0,$0        	 # Clear Carry
1250		 and   $17,$0,$0        	 # Clear Overflow
1251		 srl   $19,$2,7         	 # Set Sign
1252		 sltiu $18,$2,1         	 # Set Zero
1253		 srl   $24,$24,7
1254		 andi  $24,$24,0x1C
1255		 addu  $24,$24,$21
1256		 lw    $14,0x20($24)
1257		 lw    $25,0x88($21)
1258		 sw    $15,m68k_ICount
1259		 or    $5,$0,$2
1260		 or    $4,$0,$14
1261		 jalr  $25
1262		 sw    $23,0x4C($21)    	 # Delay slot
1263		 lw    $15,m68k_ICount
1264		 addiu $15,$15,-8
1265		 bgez  $15,3f
1266		 lhu   $24,0x00($23)    	 # Delay slot
1267		 j     MainExit
1268	3:
1269		 sll   $7,$24,2         	 # Delay slot
1270		 addu  $7,$7,$30
1271		 lw    $7,0x00($7)
1272		 jr    $7
1273		 nop                    	 # Delay slot
1274
1275OP0_10c0:				#:
1276		 addiu $23,$23,2
1277
1278		 and   $8,$24,0x0f
1279		 sll   $8,$8,2
1280		 addu  $8,$8,$21
1281		 lbu   $2,0x00($8)
1282		 and   $16,$0,$0        	 # Clear Carry
1283		 and   $17,$0,$0        	 # Clear Overflow
1284		 srl   $19,$2,7         	 # Set Sign
1285		 sltiu $18,$2,1         	 # Set Zero
1286		 srl   $24,$24,7
1287		 andi  $24,$24,0x1C
1288		 addu  $24,$24,$21
1289		 lw    $14,0x20($24)
1290		 addiu $25,$14,1
1291		 sw    $25,0x20($24)
1292		 lw    $25,0x88($21)
1293		 sw    $15,m68k_ICount
1294		 or    $5,$0,$2
1295		 or    $4,$0,$14
1296		 jalr  $25
1297		 sw    $23,0x4C($21)    	 # Delay slot
1298		 lw    $15,m68k_ICount
1299		 addiu $15,$15,-8
1300		 bgez  $15,3f
1301		 lhu   $24,0x00($23)    	 # Delay slot
1302		 j     MainExit
1303	3:
1304		 sll   $7,$24,2         	 # Delay slot
1305		 addu  $7,$7,$30
1306		 lw    $7,0x00($7)
1307		 jr    $7
1308		 nop                    	 # Delay slot
1309
1310OP0_10d0:				#:
1311		 addiu $23,$23,2
1312
1313		 and   $8,$24,0x07
1314		 sll   $8,$8,2
1315		 addu  $8,$8,$21
1316		 lw    $14,0x20($8)
1317		 lw    $25,0x7C($21)
1318		 sw    $15,m68k_ICount
1319		 sw    $24,0x44($29)
1320		 or    $4,$0,$14
1321		 jalr  $25
1322		 sw    $23,0x4C($21)    	 # Delay slot
1323		 lw    $24,0x44($29)
1324		 lw    $15,m68k_ICount
1325		 and   $16,$0,$0        	 # Clear Carry
1326		 and   $17,$0,$0        	 # Clear Overflow
1327		 srl   $19,$2,7         	 # Set Sign
1328		 sltiu $18,$2,1         	 # Set Zero
1329		 srl   $24,$24,7
1330		 andi  $24,$24,0x1C
1331		 addu  $24,$24,$21
1332		 lw    $14,0x20($24)
1333		 addiu $25,$14,1
1334		 sw    $25,0x20($24)
1335		 lw    $25,0x88($21)
1336		 sw    $15,m68k_ICount
1337		 or    $5,$0,$2
1338		 or    $4,$0,$14
1339		 jalr  $25
1340		 sw    $23,0x4C($21)    	 # Delay slot
1341		 lw    $15,m68k_ICount
1342		 addiu $15,$15,-12
1343		 bgez  $15,3f
1344		 lhu   $24,0x00($23)    	 # Delay slot
1345		 j     MainExit
1346	3:
1347		 sll   $7,$24,2         	 # Delay slot
1348		 addu  $7,$7,$30
1349		 lw    $7,0x00($7)
1350		 jr    $7
1351		 nop                    	 # Delay slot
1352
1353OP0_10d8:				#:
1354		 addiu $23,$23,2
1355
1356		 and   $8,$24,0x07
1357		 sll   $8,$8,2
1358		 addu  $8,$8,$21
1359		 lw    $14,0x20($8)
1360		 addiu $25,$14,1
1361		 sw    $25,0x20($8)
1362		 lw    $25,0x7C($21)
1363		 sw    $15,m68k_ICount
1364		 sw    $24,0x44($29)
1365		 or    $4,$0,$14
1366		 jalr  $25
1367		 sw    $23,0x4C($21)    	 # Delay slot
1368		 lw    $24,0x44($29)
1369		 lw    $15,m68k_ICount
1370		 and   $16,$0,$0        	 # Clear Carry
1371		 and   $17,$0,$0        	 # Clear Overflow
1372		 srl   $19,$2,7         	 # Set Sign
1373		 sltiu $18,$2,1         	 # Set Zero
1374		 srl   $24,$24,7
1375		 andi  $24,$24,0x1C
1376		 addu  $24,$24,$21
1377		 lw    $14,0x20($24)
1378		 addiu $25,$14,1
1379		 sw    $25,0x20($24)
1380		 lw    $25,0x88($21)
1381		 sw    $15,m68k_ICount
1382		 or    $5,$0,$2
1383		 or    $4,$0,$14
1384		 jalr  $25
1385		 sw    $23,0x4C($21)    	 # Delay slot
1386		 lw    $15,m68k_ICount
1387		 addiu $15,$15,-12
1388		 bgez  $15,3f
1389		 lhu   $24,0x00($23)    	 # Delay slot
1390		 j     MainExit
1391	3:
1392		 sll   $7,$24,2         	 # Delay slot
1393		 addu  $7,$7,$30
1394		 lw    $7,0x00($7)
1395		 jr    $7
1396		 nop                    	 # Delay slot
1397
1398OP0_10df:				#:
1399		 addiu $23,$23,2
1400
1401		 lw    $14,0x3C($21)    	 # Get A7
1402		 addiu $25,$14,2
1403		 sw    $25,0x3C($21)
1404		 lw    $25,0x7C($21)
1405		 sw    $15,m68k_ICount
1406		 sw    $24,0x44($29)
1407		 or    $4,$0,$14
1408		 jalr  $25
1409		 sw    $23,0x4C($21)    	 # Delay slot
1410		 lw    $24,0x44($29)
1411		 lw    $15,m68k_ICount
1412		 and   $16,$0,$0        	 # Clear Carry
1413		 and   $17,$0,$0        	 # Clear Overflow
1414		 srl   $19,$2,7         	 # Set Sign
1415		 sltiu $18,$2,1         	 # Set Zero
1416		 srl   $24,$24,7
1417		 andi  $24,$24,0x1C
1418		 addu  $24,$24,$21
1419		 lw    $14,0x20($24)
1420		 addiu $25,$14,1
1421		 sw    $25,0x20($24)
1422		 lw    $25,0x88($21)
1423		 sw    $15,m68k_ICount
1424		 or    $5,$0,$2
1425		 or    $4,$0,$14
1426		 jalr  $25
1427		 sw    $23,0x4C($21)    	 # Delay slot
1428		 lw    $15,m68k_ICount
1429		 addiu $15,$15,-12
1430		 bgez  $15,3f
1431		 lhu   $24,0x00($23)    	 # Delay slot
1432		 j     MainExit
1433	3:
1434		 sll   $7,$24,2         	 # Delay slot
1435		 addu  $7,$7,$30
1436		 lw    $7,0x00($7)
1437		 jr    $7
1438		 nop                    	 # Delay slot
1439
1440OP0_10e0:				#:
1441		 addiu $23,$23,2
1442
1443		 and   $8,$24,0x07
1444		 sll   $8,$8,2
1445		 addu  $8,$8,$21
1446		 lw    $14,0x20($8)
1447		 addiu $14,$14,-1
1448		 sw    $14,0x20($8)
1449		 lw    $25,0x7C($21)
1450		 sw    $15,m68k_ICount
1451		 sw    $24,0x44($29)
1452		 or    $4,$0,$14
1453		 jalr  $25
1454		 sw    $23,0x4C($21)    	 # Delay slot
1455		 lw    $24,0x44($29)
1456		 lw    $15,m68k_ICount
1457		 and   $16,$0,$0        	 # Clear Carry
1458		 and   $17,$0,$0        	 # Clear Overflow
1459		 srl   $19,$2,7         	 # Set Sign
1460		 sltiu $18,$2,1         	 # Set Zero
1461		 srl   $24,$24,7
1462		 andi  $24,$24,0x1C
1463		 addu  $24,$24,$21
1464		 lw    $14,0x20($24)
1465		 addiu $25,$14,1
1466		 sw    $25,0x20($24)
1467		 lw    $25,0x88($21)
1468		 sw    $15,m68k_ICount
1469		 or    $5,$0,$2
1470		 or    $4,$0,$14
1471		 jalr  $25
1472		 sw    $23,0x4C($21)    	 # Delay slot
1473		 lw    $15,m68k_ICount
1474		 addiu $15,$15,-14
1475		 bgez  $15,3f
1476		 lhu   $24,0x00($23)    	 # Delay slot
1477		 j     MainExit
1478	3:
1479		 sll   $7,$24,2         	 # Delay slot
1480		 addu  $7,$7,$30
1481		 lw    $7,0x00($7)
1482		 jr    $7
1483		 nop                    	 # Delay slot
1484
1485OP0_10e7:				#:
1486		 addiu $23,$23,2
1487
1488		 lw    $14,0x3C($21)    	 # Get A7
1489		 addiu $14,$14,-2
1490		 sw    $14,0x3C($21)
1491		 lw    $25,0x7C($21)
1492		 sw    $15,m68k_ICount
1493		 sw    $24,0x44($29)
1494		 or    $4,$0,$14
1495		 jalr  $25
1496		 sw    $23,0x4C($21)    	 # Delay slot
1497		 lw    $24,0x44($29)
1498		 lw    $15,m68k_ICount
1499		 and   $16,$0,$0        	 # Clear Carry
1500		 and   $17,$0,$0        	 # Clear Overflow
1501		 srl   $19,$2,7         	 # Set Sign
1502		 sltiu $18,$2,1         	 # Set Zero
1503		 srl   $24,$24,7
1504		 andi  $24,$24,0x1C
1505		 addu  $24,$24,$21
1506		 lw    $14,0x20($24)
1507		 addiu $25,$14,1
1508		 sw    $25,0x20($24)
1509		 lw    $25,0x88($21)
1510		 sw    $15,m68k_ICount
1511		 or    $5,$0,$2
1512		 or    $4,$0,$14
1513		 jalr  $25
1514		 sw    $23,0x4C($21)    	 # Delay slot
1515		 lw    $15,m68k_ICount
1516		 addiu $15,$15,-14
1517		 bgez  $15,3f
1518		 lhu   $24,0x00($23)    	 # Delay slot
1519		 j     MainExit
1520	3:
1521		 sll   $7,$24,2         	 # Delay slot
1522		 addu  $7,$7,$30
1523		 lw    $7,0x00($7)
1524		 jr    $7
1525		 nop                    	 # Delay slot
1526
1527OP0_10e8:				#:
1528		 addiu $23,$23,2
1529
1530		 and   $8,$24,0x07
1531		 lh    $7,0x00($23)
1532		 sll   $8,$8,2
1533		 addu  $8,$8,$21
1534		 lw    $14,0x20($8)
1535		 addiu $23,$23,2
1536		 addu  $14,$14,$7
1537		 lw    $25,0x7C($21)
1538		 sw    $15,m68k_ICount
1539		 sw    $24,0x44($29)
1540		 or    $4,$0,$14
1541		 jalr  $25
1542		 sw    $23,0x4C($21)    	 # Delay slot
1543		 lw    $24,0x44($29)
1544		 lw    $15,m68k_ICount
1545		 and   $16,$0,$0        	 # Clear Carry
1546		 and   $17,$0,$0        	 # Clear Overflow
1547		 srl   $19,$2,7         	 # Set Sign
1548		 sltiu $18,$2,1         	 # Set Zero
1549		 srl   $24,$24,7
1550		 andi  $24,$24,0x1C
1551		 addu  $24,$24,$21
1552		 lw    $14,0x20($24)
1553		 addiu $25,$14,1
1554		 sw    $25,0x20($24)
1555		 lw    $25,0x88($21)
1556		 sw    $15,m68k_ICount
1557		 or    $5,$0,$2
1558		 or    $4,$0,$14
1559		 jalr  $25
1560		 sw    $23,0x4C($21)    	 # Delay slot
1561		 lw    $15,m68k_ICount
1562		 addiu $15,$15,-16
1563		 bgez  $15,3f
1564		 lhu   $24,0x00($23)    	 # Delay slot
1565		 j     MainExit
1566	3:
1567		 sll   $7,$24,2         	 # Delay slot
1568		 addu  $7,$7,$30
1569		 lw    $7,0x00($7)
1570		 jr    $7
1571		 nop                    	 # Delay slot
1572
1573OP0_10f0:				#:
1574		 addiu $23,$23,2
1575
1576		 and   $8,$24,0x07
1577		 sll   $8,$8,2
1578		 addu  $8,$8,$21
1579		 lw    $14,0x20($8)
1580		 lhu   $7,0x00($23)
1581		 addiu $23,$23,2
1582		 seb   $6,$7
1583		 or    $25,$0,$7
1584		 srl   $7,$7,12
1585		 andi  $25,$25,0x0800
1586		 sll   $7,$7,2
1587		 addu  $7,$7,$21
1588		 bne   $25,$0,0f
1589		 lw    $25,0x00($7)      	 # Delay slot
1590		 seh   $25,$25
1591	0:
1592		 addu  $25,$14,$25
1593		 addu  $14,$25,$6
1594		 lw    $25,0x7C($21)
1595		 sw    $15,m68k_ICount
1596		 sw    $24,0x44($29)
1597		 or    $4,$0,$14
1598		 jalr  $25
1599		 sw    $23,0x4C($21)    	 # Delay slot
1600		 lw    $24,0x44($29)
1601		 lw    $15,m68k_ICount
1602		 and   $16,$0,$0        	 # Clear Carry
1603		 and   $17,$0,$0        	 # Clear Overflow
1604		 srl   $19,$2,7         	 # Set Sign
1605		 sltiu $18,$2,1         	 # Set Zero
1606		 srl   $24,$24,7
1607		 andi  $24,$24,0x1C
1608		 addu  $24,$24,$21
1609		 lw    $14,0x20($24)
1610		 addiu $25,$14,1
1611		 sw    $25,0x20($24)
1612		 lw    $25,0x88($21)
1613		 sw    $15,m68k_ICount
1614		 or    $5,$0,$2
1615		 or    $4,$0,$14
1616		 jalr  $25
1617		 sw    $23,0x4C($21)    	 # Delay slot
1618		 lw    $15,m68k_ICount
1619		 addiu $15,$15,-18
1620		 bgez  $15,3f
1621		 lhu   $24,0x00($23)    	 # Delay slot
1622		 j     MainExit
1623	3:
1624		 sll   $7,$24,2         	 # Delay slot
1625		 addu  $7,$7,$30
1626		 lw    $7,0x00($7)
1627		 jr    $7
1628		 nop                    	 # Delay slot
1629
1630OP0_10f8:				#:
1631		 addiu $23,$23,2
1632
1633		 lh    $14,0x00($23)
1634		 addiu $23,$23,2
1635		 lw    $25,0x7C($21)
1636		 sw    $15,m68k_ICount
1637		 sw    $24,0x44($29)
1638		 or    $4,$0,$14
1639		 jalr  $25
1640		 sw    $23,0x4C($21)    	 # Delay slot
1641		 lw    $24,0x44($29)
1642		 lw    $15,m68k_ICount
1643		 and   $16,$0,$0        	 # Clear Carry
1644		 and   $17,$0,$0        	 # Clear Overflow
1645		 srl   $19,$2,7         	 # Set Sign
1646		 sltiu $18,$2,1         	 # Set Zero
1647		 srl   $24,$24,7
1648		 andi  $24,$24,0x1C
1649		 addu  $24,$24,$21
1650		 lw    $14,0x20($24)
1651		 addiu $25,$14,1
1652		 sw    $25,0x20($24)
1653		 lw    $25,0x88($21)
1654		 sw    $15,m68k_ICount
1655		 or    $5,$0,$2
1656		 or    $4,$0,$14
1657		 jalr  $25
1658		 sw    $23,0x4C($21)    	 # Delay slot
1659		 lw    $15,m68k_ICount
1660		 addiu $15,$15,-16
1661		 bgez  $15,3f
1662		 lhu   $24,0x00($23)    	 # Delay slot
1663		 j     MainExit
1664	3:
1665		 sll   $7,$24,2         	 # Delay slot
1666		 addu  $7,$7,$30
1667		 lw    $7,0x00($7)
1668		 jr    $7
1669		 nop                    	 # Delay slot
1670
1671OP0_10f9:				#:
1672		 addiu $23,$23,2
1673
1674		 lhu   $14,0x00($23)
1675		 lhu   $25,0x02($23)
1676		 sll   $14,$14,16
1677		 or    $14,$14,$25
1678		 addiu $23,$23,4
1679		 lw    $25,0x7C($21)
1680		 sw    $15,m68k_ICount
1681		 sw    $24,0x44($29)
1682		 or    $4,$0,$14
1683		 jalr  $25
1684		 sw    $23,0x4C($21)    	 # Delay slot
1685		 lw    $24,0x44($29)
1686		 lw    $15,m68k_ICount
1687		 and   $16,$0,$0        	 # Clear Carry
1688		 and   $17,$0,$0        	 # Clear Overflow
1689		 srl   $19,$2,7         	 # Set Sign
1690		 sltiu $18,$2,1         	 # Set Zero
1691		 srl   $24,$24,7
1692		 andi  $24,$24,0x1C
1693		 addu  $24,$24,$21
1694		 lw    $14,0x20($24)
1695		 addiu $25,$14,1
1696		 sw    $25,0x20($24)
1697		 lw    $25,0x88($21)
1698		 sw    $15,m68k_ICount
1699		 or    $5,$0,$2
1700		 or    $4,$0,$14
1701		 jalr  $25
1702		 sw    $23,0x4C($21)    	 # Delay slot
1703		 lw    $15,m68k_ICount
1704		 addiu $15,$15,-20
1705		 bgez  $15,3f
1706		 lhu   $24,0x00($23)    	 # Delay slot
1707		 j     MainExit
1708	3:
1709		 sll   $7,$24,2         	 # Delay slot
1710		 addu  $7,$7,$30
1711		 lw    $7,0x00($7)
1712		 jr    $7
1713		 nop                    	 # Delay slot
1714
1715OP0_10fa:				#:
1716		 addiu $23,$23,2
1717
1718		 lh    $7,0x00($23)
1719		 subu  $25,$23,$22
1720		 addu  $14,$25,$7       	 # Add Offset to PC
1721		 addiu $23,$23,2
1722		 lw    $25,0x98($21)
1723		 sw    $15,m68k_ICount
1724		 sw    $24,0x44($29)
1725		 or    $4,$0,$14
1726		 jalr  $25
1727		 sw    $23,0x4C($21)    	 # Delay slot
1728		 lw    $24,0x44($29)
1729		 lw    $15,m68k_ICount
1730		 and   $16,$0,$0        	 # Clear Carry
1731		 and   $17,$0,$0        	 # Clear Overflow
1732		 srl   $19,$2,7         	 # Set Sign
1733		 sltiu $18,$2,1         	 # Set Zero
1734		 srl   $24,$24,7
1735		 andi  $24,$24,0x1C
1736		 addu  $24,$24,$21
1737		 lw    $14,0x20($24)
1738		 addiu $25,$14,1
1739		 sw    $25,0x20($24)
1740		 lw    $25,0x88($21)
1741		 sw    $15,m68k_ICount
1742		 or    $5,$0,$2
1743		 or    $4,$0,$14
1744		 jalr  $25
1745		 sw    $23,0x4C($21)    	 # Delay slot
1746		 lw    $15,m68k_ICount
1747		 addiu $15,$15,-16
1748		 bgez  $15,3f
1749		 lhu   $24,0x00($23)    	 # Delay slot
1750		 j     MainExit
1751	3:
1752		 sll   $7,$24,2         	 # Delay slot
1753		 addu  $7,$7,$30
1754		 lw    $7,0x00($7)
1755		 jr    $7
1756		 nop                    	 # Delay slot
1757
1758OP0_10fb:				#:
1759		 addiu $23,$23,2
1760
1761		 subu  $14,$23,$22       	 # Get PC
1762		 lhu   $7,0x00($23)
1763		 addiu $23,$23,2
1764		 seb   $6,$7
1765		 or    $25,$0,$7
1766		 srl   $7,$7,12
1767		 andi  $25,$25,0x0800
1768		 sll   $7,$7,2
1769		 addu  $7,$7,$21
1770		 bne   $25,$0,0f
1771		 lw    $25,0x00($7)      	 # Delay slot
1772		 seh   $25,$25
1773	0:
1774		 addu  $25,$14,$25
1775		 addu  $14,$25,$6
1776		 lw    $25,0x98($21)
1777		 sw    $15,m68k_ICount
1778		 sw    $24,0x44($29)
1779		 or    $4,$0,$14
1780		 jalr  $25
1781		 sw    $23,0x4C($21)    	 # Delay slot
1782		 lw    $24,0x44($29)
1783		 lw    $15,m68k_ICount
1784		 and   $16,$0,$0        	 # Clear Carry
1785		 and   $17,$0,$0        	 # Clear Overflow
1786		 srl   $19,$2,7         	 # Set Sign
1787		 sltiu $18,$2,1         	 # Set Zero
1788		 srl   $24,$24,7
1789		 andi  $24,$24,0x1C
1790		 addu  $24,$24,$21
1791		 lw    $14,0x20($24)
1792		 addiu $25,$14,1
1793		 sw    $25,0x20($24)
1794		 lw    $25,0x88($21)
1795		 sw    $15,m68k_ICount
1796		 or    $5,$0,$2
1797		 or    $4,$0,$14
1798		 jalr  $25
1799		 sw    $23,0x4C($21)    	 # Delay slot
1800		 lw    $15,m68k_ICount
1801		 addiu $15,$15,-18
1802		 bgez  $15,3f
1803		 lhu   $24,0x00($23)    	 # Delay slot
1804		 j     MainExit
1805	3:
1806		 sll   $7,$24,2         	 # Delay slot
1807		 addu  $7,$7,$30
1808		 lw    $7,0x00($7)
1809		 jr    $7
1810		 nop                    	 # Delay slot
1811
1812OP0_10fc:				#:
1813		 addiu $23,$23,2
1814
1815		 lbu   $2,0x00($23)
1816		 addiu $23,$23,2
1817		 and   $16,$0,$0        	 # Clear Carry
1818		 and   $17,$0,$0        	 # Clear Overflow
1819		 srl   $19,$2,7         	 # Set Sign
1820		 sltiu $18,$2,1         	 # Set Zero
1821		 srl   $24,$24,7
1822		 andi  $24,$24,0x1C
1823		 addu  $24,$24,$21
1824		 lw    $14,0x20($24)
1825		 addiu $25,$14,1
1826		 sw    $25,0x20($24)
1827		 lw    $25,0x88($21)
1828		 sw    $15,m68k_ICount
1829		 or    $5,$0,$2
1830		 or    $4,$0,$14
1831		 jalr  $25
1832		 sw    $23,0x4C($21)    	 # Delay slot
1833		 lw    $15,m68k_ICount
1834		 addiu $15,$15,-8
1835		 bgez  $15,3f
1836		 lhu   $24,0x00($23)    	 # Delay slot
1837		 j     MainExit
1838	3:
1839		 sll   $7,$24,2         	 # Delay slot
1840		 addu  $7,$7,$30
1841		 lw    $7,0x00($7)
1842		 jr    $7
1843		 nop                    	 # Delay slot
1844
1845OP0_1100:				#:
1846		 addiu $23,$23,2
1847
1848		 and   $8,$24,0x0f
1849		 sll   $8,$8,2
1850		 addu  $8,$8,$21
1851		 lbu   $2,0x00($8)
1852		 and   $16,$0,$0        	 # Clear Carry
1853		 and   $17,$0,$0        	 # Clear Overflow
1854		 srl   $19,$2,7         	 # Set Sign
1855		 sltiu $18,$2,1         	 # Set Zero
1856		 srl   $24,$24,7
1857		 andi  $24,$24,0x1C
1858		 addu  $24,$24,$21
1859		 lw    $14,0x20($24)
1860		 addiu $14,$14,-1
1861		 sw    $14,0x20($24)
1862		 lw    $25,0x88($21)
1863		 sw    $15,m68k_ICount
1864		 or    $5,$0,$2
1865		 or    $4,$0,$14
1866		 jalr  $25
1867		 sw    $23,0x4C($21)    	 # Delay slot
1868		 lw    $15,m68k_ICount
1869		 addiu $15,$15,-10
1870		 bgez  $15,3f
1871		 lhu   $24,0x00($23)    	 # Delay slot
1872		 j     MainExit
1873	3:
1874		 sll   $7,$24,2         	 # Delay slot
1875		 addu  $7,$7,$30
1876		 lw    $7,0x00($7)
1877		 jr    $7
1878		 nop                    	 # Delay slot
1879
1880OP0_1110:				#:
1881		 addiu $23,$23,2
1882
1883		 and   $8,$24,0x07
1884		 sll   $8,$8,2
1885		 addu  $8,$8,$21
1886		 lw    $14,0x20($8)
1887		 lw    $25,0x7C($21)
1888		 sw    $15,m68k_ICount
1889		 sw    $24,0x44($29)
1890		 or    $4,$0,$14
1891		 jalr  $25
1892		 sw    $23,0x4C($21)    	 # Delay slot
1893		 lw    $24,0x44($29)
1894		 lw    $15,m68k_ICount
1895		 and   $16,$0,$0        	 # Clear Carry
1896		 and   $17,$0,$0        	 # Clear Overflow
1897		 srl   $19,$2,7         	 # Set Sign
1898		 sltiu $18,$2,1         	 # Set Zero
1899		 srl   $24,$24,7
1900		 andi  $24,$24,0x1C
1901		 addu  $24,$24,$21
1902		 lw    $14,0x20($24)
1903		 addiu $14,$14,-1
1904		 sw    $14,0x20($24)
1905		 lw    $25,0x88($21)
1906		 sw    $15,m68k_ICount
1907		 or    $5,$0,$2
1908		 or    $4,$0,$14
1909		 jalr  $25
1910		 sw    $23,0x4C($21)    	 # Delay slot
1911		 lw    $15,m68k_ICount
1912		 addiu $15,$15,-14
1913		 bgez  $15,3f
1914		 lhu   $24,0x00($23)    	 # Delay slot
1915		 j     MainExit
1916	3:
1917		 sll   $7,$24,2         	 # Delay slot
1918		 addu  $7,$7,$30
1919		 lw    $7,0x00($7)
1920		 jr    $7
1921		 nop                    	 # Delay slot
1922
1923OP0_1118:				#:
1924		 addiu $23,$23,2
1925
1926		 and   $8,$24,0x07
1927		 sll   $8,$8,2
1928		 addu  $8,$8,$21
1929		 lw    $14,0x20($8)
1930		 addiu $25,$14,1
1931		 sw    $25,0x20($8)
1932		 lw    $25,0x7C($21)
1933		 sw    $15,m68k_ICount
1934		 sw    $24,0x44($29)
1935		 or    $4,$0,$14
1936		 jalr  $25
1937		 sw    $23,0x4C($21)    	 # Delay slot
1938		 lw    $24,0x44($29)
1939		 lw    $15,m68k_ICount
1940		 and   $16,$0,$0        	 # Clear Carry
1941		 and   $17,$0,$0        	 # Clear Overflow
1942		 srl   $19,$2,7         	 # Set Sign
1943		 sltiu $18,$2,1         	 # Set Zero
1944		 srl   $24,$24,7
1945		 andi  $24,$24,0x1C
1946		 addu  $24,$24,$21
1947		 lw    $14,0x20($24)
1948		 addiu $14,$14,-1
1949		 sw    $14,0x20($24)
1950		 lw    $25,0x88($21)
1951		 sw    $15,m68k_ICount
1952		 or    $5,$0,$2
1953		 or    $4,$0,$14
1954		 jalr  $25
1955		 sw    $23,0x4C($21)    	 # Delay slot
1956		 lw    $15,m68k_ICount
1957		 addiu $15,$15,-14
1958		 bgez  $15,3f
1959		 lhu   $24,0x00($23)    	 # Delay slot
1960		 j     MainExit
1961	3:
1962		 sll   $7,$24,2         	 # Delay slot
1963		 addu  $7,$7,$30
1964		 lw    $7,0x00($7)
1965		 jr    $7
1966		 nop                    	 # Delay slot
1967
1968OP0_111f:				#:
1969		 addiu $23,$23,2
1970
1971		 lw    $14,0x3C($21)    	 # Get A7
1972		 addiu $25,$14,2
1973		 sw    $25,0x3C($21)
1974		 lw    $25,0x7C($21)
1975		 sw    $15,m68k_ICount
1976		 sw    $24,0x44($29)
1977		 or    $4,$0,$14
1978		 jalr  $25
1979		 sw    $23,0x4C($21)    	 # Delay slot
1980		 lw    $24,0x44($29)
1981		 lw    $15,m68k_ICount
1982		 and   $16,$0,$0        	 # Clear Carry
1983		 and   $17,$0,$0        	 # Clear Overflow
1984		 srl   $19,$2,7         	 # Set Sign
1985		 sltiu $18,$2,1         	 # Set Zero
1986		 srl   $24,$24,7
1987		 andi  $24,$24,0x1C
1988		 addu  $24,$24,$21
1989		 lw    $14,0x20($24)
1990		 addiu $14,$14,-1
1991		 sw    $14,0x20($24)
1992		 lw    $25,0x88($21)
1993		 sw    $15,m68k_ICount
1994		 or    $5,$0,$2
1995		 or    $4,$0,$14
1996		 jalr  $25
1997		 sw    $23,0x4C($21)    	 # Delay slot
1998		 lw    $15,m68k_ICount
1999		 addiu $15,$15,-14
2000		 bgez  $15,3f
2001		 lhu   $24,0x00($23)    	 # Delay slot
2002		 j     MainExit
2003	3:
2004		 sll   $7,$24,2         	 # Delay slot
2005		 addu  $7,$7,$30
2006		 lw    $7,0x00($7)
2007		 jr    $7
2008		 nop                    	 # Delay slot
2009
2010OP0_1120:				#:
2011		 addiu $23,$23,2
2012
2013		 and   $8,$24,0x07
2014		 sll   $8,$8,2
2015		 addu  $8,$8,$21
2016		 lw    $14,0x20($8)
2017		 addiu $14,$14,-1
2018		 sw    $14,0x20($8)
2019		 lw    $25,0x7C($21)
2020		 sw    $15,m68k_ICount
2021		 sw    $24,0x44($29)
2022		 or    $4,$0,$14
2023		 jalr  $25
2024		 sw    $23,0x4C($21)    	 # Delay slot
2025		 lw    $24,0x44($29)
2026		 lw    $15,m68k_ICount
2027		 and   $16,$0,$0        	 # Clear Carry
2028		 and   $17,$0,$0        	 # Clear Overflow
2029		 srl   $19,$2,7         	 # Set Sign
2030		 sltiu $18,$2,1         	 # Set Zero
2031		 srl   $24,$24,7
2032		 andi  $24,$24,0x1C
2033		 addu  $24,$24,$21
2034		 lw    $14,0x20($24)
2035		 addiu $14,$14,-1
2036		 sw    $14,0x20($24)
2037		 lw    $25,0x88($21)
2038		 sw    $15,m68k_ICount
2039		 or    $5,$0,$2
2040		 or    $4,$0,$14
2041		 jalr  $25
2042		 sw    $23,0x4C($21)    	 # Delay slot
2043		 lw    $15,m68k_ICount
2044		 addiu $15,$15,-16
2045		 bgez  $15,3f
2046		 lhu   $24,0x00($23)    	 # Delay slot
2047		 j     MainExit
2048	3:
2049		 sll   $7,$24,2         	 # Delay slot
2050		 addu  $7,$7,$30
2051		 lw    $7,0x00($7)
2052		 jr    $7
2053		 nop                    	 # Delay slot
2054
2055OP0_1127:				#:
2056		 addiu $23,$23,2
2057
2058		 lw    $14,0x3C($21)    	 # Get A7
2059		 addiu $14,$14,-2
2060		 sw    $14,0x3C($21)
2061		 lw    $25,0x7C($21)
2062		 sw    $15,m68k_ICount
2063		 sw    $24,0x44($29)
2064		 or    $4,$0,$14
2065		 jalr  $25
2066		 sw    $23,0x4C($21)    	 # Delay slot
2067		 lw    $24,0x44($29)
2068		 lw    $15,m68k_ICount
2069		 and   $16,$0,$0        	 # Clear Carry
2070		 and   $17,$0,$0        	 # Clear Overflow
2071		 srl   $19,$2,7         	 # Set Sign
2072		 sltiu $18,$2,1         	 # Set Zero
2073		 srl   $24,$24,7
2074		 andi  $24,$24,0x1C
2075		 addu  $24,$24,$21
2076		 lw    $14,0x20($24)
2077		 addiu $14,$14,-1
2078		 sw    $14,0x20($24)
2079		 lw    $25,0x88($21)
2080		 sw    $15,m68k_ICount
2081		 or    $5,$0,$2
2082		 or    $4,$0,$14
2083		 jalr  $25
2084		 sw    $23,0x4C($21)    	 # Delay slot
2085		 lw    $15,m68k_ICount
2086		 addiu $15,$15,-16
2087		 bgez  $15,3f
2088		 lhu   $24,0x00($23)    	 # Delay slot
2089		 j     MainExit
2090	3:
2091		 sll   $7,$24,2         	 # Delay slot
2092		 addu  $7,$7,$30
2093		 lw    $7,0x00($7)
2094		 jr    $7
2095		 nop                    	 # Delay slot
2096
2097OP0_1128:				#:
2098		 addiu $23,$23,2
2099
2100		 and   $8,$24,0x07
2101		 lh    $7,0x00($23)
2102		 sll   $8,$8,2
2103		 addu  $8,$8,$21
2104		 lw    $14,0x20($8)
2105		 addiu $23,$23,2
2106		 addu  $14,$14,$7
2107		 lw    $25,0x7C($21)
2108		 sw    $15,m68k_ICount
2109		 sw    $24,0x44($29)
2110		 or    $4,$0,$14
2111		 jalr  $25
2112		 sw    $23,0x4C($21)    	 # Delay slot
2113		 lw    $24,0x44($29)
2114		 lw    $15,m68k_ICount
2115		 and   $16,$0,$0        	 # Clear Carry
2116		 and   $17,$0,$0        	 # Clear Overflow
2117		 srl   $19,$2,7         	 # Set Sign
2118		 sltiu $18,$2,1         	 # Set Zero
2119		 srl   $24,$24,7
2120		 andi  $24,$24,0x1C
2121		 addu  $24,$24,$21
2122		 lw    $14,0x20($24)
2123		 addiu $14,$14,-1
2124		 sw    $14,0x20($24)
2125		 lw    $25,0x88($21)
2126		 sw    $15,m68k_ICount
2127		 or    $5,$0,$2
2128		 or    $4,$0,$14
2129		 jalr  $25
2130		 sw    $23,0x4C($21)    	 # Delay slot
2131		 lw    $15,m68k_ICount
2132		 addiu $15,$15,-18
2133		 bgez  $15,3f
2134		 lhu   $24,0x00($23)    	 # Delay slot
2135		 j     MainExit
2136	3:
2137		 sll   $7,$24,2         	 # Delay slot
2138		 addu  $7,$7,$30
2139		 lw    $7,0x00($7)
2140		 jr    $7
2141		 nop                    	 # Delay slot
2142
2143OP0_1130:				#:
2144		 addiu $23,$23,2
2145
2146		 and   $8,$24,0x07
2147		 sll   $8,$8,2
2148		 addu  $8,$8,$21
2149		 lw    $14,0x20($8)
2150		 lhu   $7,0x00($23)
2151		 addiu $23,$23,2
2152		 seb   $6,$7
2153		 or    $25,$0,$7
2154		 srl   $7,$7,12
2155		 andi  $25,$25,0x0800
2156		 sll   $7,$7,2
2157		 addu  $7,$7,$21
2158		 bne   $25,$0,0f
2159		 lw    $25,0x00($7)      	 # Delay slot
2160		 seh   $25,$25
2161	0:
2162		 addu  $25,$14,$25
2163		 addu  $14,$25,$6
2164		 lw    $25,0x7C($21)
2165		 sw    $15,m68k_ICount
2166		 sw    $24,0x44($29)
2167		 or    $4,$0,$14
2168		 jalr  $25
2169		 sw    $23,0x4C($21)    	 # Delay slot
2170		 lw    $24,0x44($29)
2171		 lw    $15,m68k_ICount
2172		 and   $16,$0,$0        	 # Clear Carry
2173		 and   $17,$0,$0        	 # Clear Overflow
2174		 srl   $19,$2,7         	 # Set Sign
2175		 sltiu $18,$2,1         	 # Set Zero
2176		 srl   $24,$24,7
2177		 andi  $24,$24,0x1C
2178		 addu  $24,$24,$21
2179		 lw    $14,0x20($24)
2180		 addiu $14,$14,-1
2181		 sw    $14,0x20($24)
2182		 lw    $25,0x88($21)
2183		 sw    $15,m68k_ICount
2184		 or    $5,$0,$2
2185		 or    $4,$0,$14
2186		 jalr  $25
2187		 sw    $23,0x4C($21)    	 # Delay slot
2188		 lw    $15,m68k_ICount
2189		 addiu $15,$15,-20
2190		 bgez  $15,3f
2191		 lhu   $24,0x00($23)    	 # Delay slot
2192		 j     MainExit
2193	3:
2194		 sll   $7,$24,2         	 # Delay slot
2195		 addu  $7,$7,$30
2196		 lw    $7,0x00($7)
2197		 jr    $7
2198		 nop                    	 # Delay slot
2199
2200OP0_1138:				#:
2201		 addiu $23,$23,2
2202
2203		 lh    $14,0x00($23)
2204		 addiu $23,$23,2
2205		 lw    $25,0x7C($21)
2206		 sw    $15,m68k_ICount
2207		 sw    $24,0x44($29)
2208		 or    $4,$0,$14
2209		 jalr  $25
2210		 sw    $23,0x4C($21)    	 # Delay slot
2211		 lw    $24,0x44($29)
2212		 lw    $15,m68k_ICount
2213		 and   $16,$0,$0        	 # Clear Carry
2214		 and   $17,$0,$0        	 # Clear Overflow
2215		 srl   $19,$2,7         	 # Set Sign
2216		 sltiu $18,$2,1         	 # Set Zero
2217		 srl   $24,$24,7
2218		 andi  $24,$24,0x1C
2219		 addu  $24,$24,$21
2220		 lw    $14,0x20($24)
2221		 addiu $14,$14,-1
2222		 sw    $14,0x20($24)
2223		 lw    $25,0x88($21)
2224		 sw    $15,m68k_ICount
2225		 or    $5,$0,$2
2226		 or    $4,$0,$14
2227		 jalr  $25
2228		 sw    $23,0x4C($21)    	 # Delay slot
2229		 lw    $15,m68k_ICount
2230		 addiu $15,$15,-18
2231		 bgez  $15,3f
2232		 lhu   $24,0x00($23)    	 # Delay slot
2233		 j     MainExit
2234	3:
2235		 sll   $7,$24,2         	 # Delay slot
2236		 addu  $7,$7,$30
2237		 lw    $7,0x00($7)
2238		 jr    $7
2239		 nop                    	 # Delay slot
2240
2241OP0_1139:				#:
2242		 addiu $23,$23,2
2243
2244		 lhu   $14,0x00($23)
2245		 lhu   $25,0x02($23)
2246		 sll   $14,$14,16
2247		 or    $14,$14,$25
2248		 addiu $23,$23,4
2249		 lw    $25,0x7C($21)
2250		 sw    $15,m68k_ICount
2251		 sw    $24,0x44($29)
2252		 or    $4,$0,$14
2253		 jalr  $25
2254		 sw    $23,0x4C($21)    	 # Delay slot
2255		 lw    $24,0x44($29)
2256		 lw    $15,m68k_ICount
2257		 and   $16,$0,$0        	 # Clear Carry
2258		 and   $17,$0,$0        	 # Clear Overflow
2259		 srl   $19,$2,7         	 # Set Sign
2260		 sltiu $18,$2,1         	 # Set Zero
2261		 srl   $24,$24,7
2262		 andi  $24,$24,0x1C
2263		 addu  $24,$24,$21
2264		 lw    $14,0x20($24)
2265		 addiu $14,$14,-1
2266		 sw    $14,0x20($24)
2267		 lw    $25,0x88($21)
2268		 sw    $15,m68k_ICount
2269		 or    $5,$0,$2
2270		 or    $4,$0,$14
2271		 jalr  $25
2272		 sw    $23,0x4C($21)    	 # Delay slot
2273		 lw    $15,m68k_ICount
2274		 addiu $15,$15,-22
2275		 bgez  $15,3f
2276		 lhu   $24,0x00($23)    	 # Delay slot
2277		 j     MainExit
2278	3:
2279		 sll   $7,$24,2         	 # Delay slot
2280		 addu  $7,$7,$30
2281		 lw    $7,0x00($7)
2282		 jr    $7
2283		 nop                    	 # Delay slot
2284
2285OP0_113a:				#:
2286		 addiu $23,$23,2
2287
2288		 lh    $7,0x00($23)
2289		 subu  $25,$23,$22
2290		 addu  $14,$25,$7       	 # Add Offset to PC
2291		 addiu $23,$23,2
2292		 lw    $25,0x98($21)
2293		 sw    $15,m68k_ICount
2294		 sw    $24,0x44($29)
2295		 or    $4,$0,$14
2296		 jalr  $25
2297		 sw    $23,0x4C($21)    	 # Delay slot
2298		 lw    $24,0x44($29)
2299		 lw    $15,m68k_ICount
2300		 and   $16,$0,$0        	 # Clear Carry
2301		 and   $17,$0,$0        	 # Clear Overflow
2302		 srl   $19,$2,7         	 # Set Sign
2303		 sltiu $18,$2,1         	 # Set Zero
2304		 srl   $24,$24,7
2305		 andi  $24,$24,0x1C
2306		 addu  $24,$24,$21
2307		 lw    $14,0x20($24)
2308		 addiu $14,$14,-1
2309		 sw    $14,0x20($24)
2310		 lw    $25,0x88($21)
2311		 sw    $15,m68k_ICount
2312		 or    $5,$0,$2
2313		 or    $4,$0,$14
2314		 jalr  $25
2315		 sw    $23,0x4C($21)    	 # Delay slot
2316		 lw    $15,m68k_ICount
2317		 addiu $15,$15,-18
2318		 bgez  $15,3f
2319		 lhu   $24,0x00($23)    	 # Delay slot
2320		 j     MainExit
2321	3:
2322		 sll   $7,$24,2         	 # Delay slot
2323		 addu  $7,$7,$30
2324		 lw    $7,0x00($7)
2325		 jr    $7
2326		 nop                    	 # Delay slot
2327
2328OP0_113b:				#:
2329		 addiu $23,$23,2
2330
2331		 subu  $14,$23,$22       	 # Get PC
2332		 lhu   $7,0x00($23)
2333		 addiu $23,$23,2
2334		 seb   $6,$7
2335		 or    $25,$0,$7
2336		 srl   $7,$7,12
2337		 andi  $25,$25,0x0800
2338		 sll   $7,$7,2
2339		 addu  $7,$7,$21
2340		 bne   $25,$0,0f
2341		 lw    $25,0x00($7)      	 # Delay slot
2342		 seh   $25,$25
2343	0:
2344		 addu  $25,$14,$25
2345		 addu  $14,$25,$6
2346		 lw    $25,0x98($21)
2347		 sw    $15,m68k_ICount
2348		 sw    $24,0x44($29)
2349		 or    $4,$0,$14
2350		 jalr  $25
2351		 sw    $23,0x4C($21)    	 # Delay slot
2352		 lw    $24,0x44($29)
2353		 lw    $15,m68k_ICount
2354		 and   $16,$0,$0        	 # Clear Carry
2355		 and   $17,$0,$0        	 # Clear Overflow
2356		 srl   $19,$2,7         	 # Set Sign
2357		 sltiu $18,$2,1         	 # Set Zero
2358		 srl   $24,$24,7
2359		 andi  $24,$24,0x1C
2360		 addu  $24,$24,$21
2361		 lw    $14,0x20($24)
2362		 addiu $14,$14,-1
2363		 sw    $14,0x20($24)
2364		 lw    $25,0x88($21)
2365		 sw    $15,m68k_ICount
2366		 or    $5,$0,$2
2367		 or    $4,$0,$14
2368		 jalr  $25
2369		 sw    $23,0x4C($21)    	 # Delay slot
2370		 lw    $15,m68k_ICount
2371		 addiu $15,$15,-20
2372		 bgez  $15,3f
2373		 lhu   $24,0x00($23)    	 # Delay slot
2374		 j     MainExit
2375	3:
2376		 sll   $7,$24,2         	 # Delay slot
2377		 addu  $7,$7,$30
2378		 lw    $7,0x00($7)
2379		 jr    $7
2380		 nop                    	 # Delay slot
2381
2382OP0_113c:				#:
2383		 addiu $23,$23,2
2384
2385		 lbu   $2,0x00($23)
2386		 addiu $23,$23,2
2387		 and   $16,$0,$0        	 # Clear Carry
2388		 and   $17,$0,$0        	 # Clear Overflow
2389		 srl   $19,$2,7         	 # Set Sign
2390		 sltiu $18,$2,1         	 # Set Zero
2391		 srl   $24,$24,7
2392		 andi  $24,$24,0x1C
2393		 addu  $24,$24,$21
2394		 lw    $14,0x20($24)
2395		 addiu $14,$14,-1
2396		 sw    $14,0x20($24)
2397		 lw    $25,0x88($21)
2398		 sw    $15,m68k_ICount
2399		 or    $5,$0,$2
2400		 or    $4,$0,$14
2401		 jalr  $25
2402		 sw    $23,0x4C($21)    	 # Delay slot
2403		 lw    $15,m68k_ICount
2404		 addiu $15,$15,-10
2405		 bgez  $15,3f
2406		 lhu   $24,0x00($23)    	 # Delay slot
2407		 j     MainExit
2408	3:
2409		 sll   $7,$24,2         	 # Delay slot
2410		 addu  $7,$7,$30
2411		 lw    $7,0x00($7)
2412		 jr    $7
2413		 nop                    	 # Delay slot
2414
2415OP0_1140:				#:
2416		 addiu $23,$23,2
2417
2418		 and   $8,$24,0x0f
2419		 sll   $8,$8,2
2420		 addu  $8,$8,$21
2421		 lbu   $2,0x00($8)
2422		 and   $16,$0,$0        	 # Clear Carry
2423		 and   $17,$0,$0        	 # Clear Overflow
2424		 srl   $19,$2,7         	 # Set Sign
2425		 sltiu $18,$2,1         	 # Set Zero
2426		 srl   $24,$24,7
2427		 andi  $24,$24,0x1C
2428		 lh    $7,0x00($23)
2429		 addu  $24,$24,$21
2430		 lw    $14,0x20($24)
2431		 addiu $23,$23,2
2432		 addu  $14,$14,$7
2433		 lw    $25,0x88($21)
2434		 sw    $15,m68k_ICount
2435		 or    $5,$0,$2
2436		 or    $4,$0,$14
2437		 jalr  $25
2438		 sw    $23,0x4C($21)    	 # Delay slot
2439		 lw    $15,m68k_ICount
2440		 addiu $15,$15,-12
2441		 bgez  $15,3f
2442		 lhu   $24,0x00($23)    	 # Delay slot
2443		 j     MainExit
2444	3:
2445		 sll   $7,$24,2         	 # Delay slot
2446		 addu  $7,$7,$30
2447		 lw    $7,0x00($7)
2448		 jr    $7
2449		 nop                    	 # Delay slot
2450
2451OP0_1150:				#:
2452		 addiu $23,$23,2
2453
2454		 and   $8,$24,0x07
2455		 sll   $8,$8,2
2456		 addu  $8,$8,$21
2457		 lw    $14,0x20($8)
2458		 lw    $25,0x7C($21)
2459		 sw    $15,m68k_ICount
2460		 sw    $24,0x44($29)
2461		 or    $4,$0,$14
2462		 jalr  $25
2463		 sw    $23,0x4C($21)    	 # Delay slot
2464		 lw    $24,0x44($29)
2465		 lw    $15,m68k_ICount
2466		 and   $16,$0,$0        	 # Clear Carry
2467		 and   $17,$0,$0        	 # Clear Overflow
2468		 srl   $19,$2,7         	 # Set Sign
2469		 sltiu $18,$2,1         	 # Set Zero
2470		 srl   $24,$24,7
2471		 andi  $24,$24,0x1C
2472		 lh    $7,0x00($23)
2473		 addu  $24,$24,$21
2474		 lw    $14,0x20($24)
2475		 addiu $23,$23,2
2476		 addu  $14,$14,$7
2477		 lw    $25,0x88($21)
2478		 sw    $15,m68k_ICount
2479		 or    $5,$0,$2
2480		 or    $4,$0,$14
2481		 jalr  $25
2482		 sw    $23,0x4C($21)    	 # Delay slot
2483		 lw    $15,m68k_ICount
2484		 addiu $15,$15,-16
2485		 bgez  $15,3f
2486		 lhu   $24,0x00($23)    	 # Delay slot
2487		 j     MainExit
2488	3:
2489		 sll   $7,$24,2         	 # Delay slot
2490		 addu  $7,$7,$30
2491		 lw    $7,0x00($7)
2492		 jr    $7
2493		 nop                    	 # Delay slot
2494
2495OP0_1158:				#:
2496		 addiu $23,$23,2
2497
2498		 and   $8,$24,0x07
2499		 sll   $8,$8,2
2500		 addu  $8,$8,$21
2501		 lw    $14,0x20($8)
2502		 addiu $25,$14,1
2503		 sw    $25,0x20($8)
2504		 lw    $25,0x7C($21)
2505		 sw    $15,m68k_ICount
2506		 sw    $24,0x44($29)
2507		 or    $4,$0,$14
2508		 jalr  $25
2509		 sw    $23,0x4C($21)    	 # Delay slot
2510		 lw    $24,0x44($29)
2511		 lw    $15,m68k_ICount
2512		 and   $16,$0,$0        	 # Clear Carry
2513		 and   $17,$0,$0        	 # Clear Overflow
2514		 srl   $19,$2,7         	 # Set Sign
2515		 sltiu $18,$2,1         	 # Set Zero
2516		 srl   $24,$24,7
2517		 andi  $24,$24,0x1C
2518		 lh    $7,0x00($23)
2519		 addu  $24,$24,$21
2520		 lw    $14,0x20($24)
2521		 addiu $23,$23,2
2522		 addu  $14,$14,$7
2523		 lw    $25,0x88($21)
2524		 sw    $15,m68k_ICount
2525		 or    $5,$0,$2
2526		 or    $4,$0,$14
2527		 jalr  $25
2528		 sw    $23,0x4C($21)    	 # Delay slot
2529		 lw    $15,m68k_ICount
2530		 addiu $15,$15,-16
2531		 bgez  $15,3f
2532		 lhu   $24,0x00($23)    	 # Delay slot
2533		 j     MainExit
2534	3:
2535		 sll   $7,$24,2         	 # Delay slot
2536		 addu  $7,$7,$30
2537		 lw    $7,0x00($7)
2538		 jr    $7
2539		 nop                    	 # Delay slot
2540
2541OP0_115f:				#:
2542		 addiu $23,$23,2
2543
2544		 lw    $14,0x3C($21)    	 # Get A7
2545		 addiu $25,$14,2
2546		 sw    $25,0x3C($21)
2547		 lw    $25,0x7C($21)
2548		 sw    $15,m68k_ICount
2549		 sw    $24,0x44($29)
2550		 or    $4,$0,$14
2551		 jalr  $25
2552		 sw    $23,0x4C($21)    	 # Delay slot
2553		 lw    $24,0x44($29)
2554		 lw    $15,m68k_ICount
2555		 and   $16,$0,$0        	 # Clear Carry
2556		 and   $17,$0,$0        	 # Clear Overflow
2557		 srl   $19,$2,7         	 # Set Sign
2558		 sltiu $18,$2,1         	 # Set Zero
2559		 srl   $24,$24,7
2560		 andi  $24,$24,0x1C
2561		 lh    $7,0x00($23)
2562		 addu  $24,$24,$21
2563		 lw    $14,0x20($24)
2564		 addiu $23,$23,2
2565		 addu  $14,$14,$7
2566		 lw    $25,0x88($21)
2567		 sw    $15,m68k_ICount
2568		 or    $5,$0,$2
2569		 or    $4,$0,$14
2570		 jalr  $25
2571		 sw    $23,0x4C($21)    	 # Delay slot
2572		 lw    $15,m68k_ICount
2573		 addiu $15,$15,-16
2574		 bgez  $15,3f
2575		 lhu   $24,0x00($23)    	 # Delay slot
2576		 j     MainExit
2577	3:
2578		 sll   $7,$24,2         	 # Delay slot
2579		 addu  $7,$7,$30
2580		 lw    $7,0x00($7)
2581		 jr    $7
2582		 nop                    	 # Delay slot
2583
2584OP0_1160:				#:
2585		 addiu $23,$23,2
2586
2587		 and   $8,$24,0x07
2588		 sll   $8,$8,2
2589		 addu  $8,$8,$21
2590		 lw    $14,0x20($8)
2591		 addiu $14,$14,-1
2592		 sw    $14,0x20($8)
2593		 lw    $25,0x7C($21)
2594		 sw    $15,m68k_ICount
2595		 sw    $24,0x44($29)
2596		 or    $4,$0,$14
2597		 jalr  $25
2598		 sw    $23,0x4C($21)    	 # Delay slot
2599		 lw    $24,0x44($29)
2600		 lw    $15,m68k_ICount
2601		 and   $16,$0,$0        	 # Clear Carry
2602		 and   $17,$0,$0        	 # Clear Overflow
2603		 srl   $19,$2,7         	 # Set Sign
2604		 sltiu $18,$2,1         	 # Set Zero
2605		 srl   $24,$24,7
2606		 andi  $24,$24,0x1C
2607		 lh    $7,0x00($23)
2608		 addu  $24,$24,$21
2609		 lw    $14,0x20($24)
2610		 addiu $23,$23,2
2611		 addu  $14,$14,$7
2612		 lw    $25,0x88($21)
2613		 sw    $15,m68k_ICount
2614		 or    $5,$0,$2
2615		 or    $4,$0,$14
2616		 jalr  $25
2617		 sw    $23,0x4C($21)    	 # Delay slot
2618		 lw    $15,m68k_ICount
2619		 addiu $15,$15,-18
2620		 bgez  $15,3f
2621		 lhu   $24,0x00($23)    	 # Delay slot
2622		 j     MainExit
2623	3:
2624		 sll   $7,$24,2         	 # Delay slot
2625		 addu  $7,$7,$30
2626		 lw    $7,0x00($7)
2627		 jr    $7
2628		 nop                    	 # Delay slot
2629
2630OP0_1167:				#:
2631		 addiu $23,$23,2
2632
2633		 lw    $14,0x3C($21)    	 # Get A7
2634		 addiu $14,$14,-2
2635		 sw    $14,0x3C($21)
2636		 lw    $25,0x7C($21)
2637		 sw    $15,m68k_ICount
2638		 sw    $24,0x44($29)
2639		 or    $4,$0,$14
2640		 jalr  $25
2641		 sw    $23,0x4C($21)    	 # Delay slot
2642		 lw    $24,0x44($29)
2643		 lw    $15,m68k_ICount
2644		 and   $16,$0,$0        	 # Clear Carry
2645		 and   $17,$0,$0        	 # Clear Overflow
2646		 srl   $19,$2,7         	 # Set Sign
2647		 sltiu $18,$2,1         	 # Set Zero
2648		 srl   $24,$24,7
2649		 andi  $24,$24,0x1C
2650		 lh    $7,0x00($23)
2651		 addu  $24,$24,$21
2652		 lw    $14,0x20($24)
2653		 addiu $23,$23,2
2654		 addu  $14,$14,$7
2655		 lw    $25,0x88($21)
2656		 sw    $15,m68k_ICount
2657		 or    $5,$0,$2
2658		 or    $4,$0,$14
2659		 jalr  $25
2660		 sw    $23,0x4C($21)    	 # Delay slot
2661		 lw    $15,m68k_ICount
2662		 addiu $15,$15,-18
2663		 bgez  $15,3f
2664		 lhu   $24,0x00($23)    	 # Delay slot
2665		 j     MainExit
2666	3:
2667		 sll   $7,$24,2         	 # Delay slot
2668		 addu  $7,$7,$30
2669		 lw    $7,0x00($7)
2670		 jr    $7
2671		 nop                    	 # Delay slot
2672
2673OP0_1168:				#:
2674		 addiu $23,$23,2
2675
2676		 and   $8,$24,0x07
2677		 lh    $7,0x00($23)
2678		 sll   $8,$8,2
2679		 addu  $8,$8,$21
2680		 lw    $14,0x20($8)
2681		 addiu $23,$23,2
2682		 addu  $14,$14,$7
2683		 lw    $25,0x7C($21)
2684		 sw    $15,m68k_ICount
2685		 sw    $24,0x44($29)
2686		 or    $4,$0,$14
2687		 jalr  $25
2688		 sw    $23,0x4C($21)    	 # Delay slot
2689		 lw    $24,0x44($29)
2690		 lw    $15,m68k_ICount
2691		 and   $16,$0,$0        	 # Clear Carry
2692		 and   $17,$0,$0        	 # Clear Overflow
2693		 srl   $19,$2,7         	 # Set Sign
2694		 sltiu $18,$2,1         	 # Set Zero
2695		 srl   $24,$24,7
2696		 andi  $24,$24,0x1C
2697		 lh    $7,0x00($23)
2698		 addu  $24,$24,$21
2699		 lw    $14,0x20($24)
2700		 addiu $23,$23,2
2701		 addu  $14,$14,$7
2702		 lw    $25,0x88($21)
2703		 sw    $15,m68k_ICount
2704		 or    $5,$0,$2
2705		 or    $4,$0,$14
2706		 jalr  $25
2707		 sw    $23,0x4C($21)    	 # Delay slot
2708		 lw    $15,m68k_ICount
2709		 addiu $15,$15,-20
2710		 bgez  $15,3f
2711		 lhu   $24,0x00($23)    	 # Delay slot
2712		 j     MainExit
2713	3:
2714		 sll   $7,$24,2         	 # Delay slot
2715		 addu  $7,$7,$30
2716		 lw    $7,0x00($7)
2717		 jr    $7
2718		 nop                    	 # Delay slot
2719
2720OP0_1170:				#:
2721		 addiu $23,$23,2
2722
2723		 and   $8,$24,0x07
2724		 sll   $8,$8,2
2725		 addu  $8,$8,$21
2726		 lw    $14,0x20($8)
2727		 lhu   $7,0x00($23)
2728		 addiu $23,$23,2
2729		 seb   $6,$7
2730		 or    $25,$0,$7
2731		 srl   $7,$7,12
2732		 andi  $25,$25,0x0800
2733		 sll   $7,$7,2
2734		 addu  $7,$7,$21
2735		 bne   $25,$0,0f
2736		 lw    $25,0x00($7)      	 # Delay slot
2737		 seh   $25,$25
2738	0:
2739		 addu  $25,$14,$25
2740		 addu  $14,$25,$6
2741		 lw    $25,0x7C($21)
2742		 sw    $15,m68k_ICount
2743		 sw    $24,0x44($29)
2744		 or    $4,$0,$14
2745		 jalr  $25
2746		 sw    $23,0x4C($21)    	 # Delay slot
2747		 lw    $24,0x44($29)
2748		 lw    $15,m68k_ICount
2749		 and   $16,$0,$0        	 # Clear Carry
2750		 and   $17,$0,$0        	 # Clear Overflow
2751		 srl   $19,$2,7         	 # Set Sign
2752		 sltiu $18,$2,1         	 # Set Zero
2753		 srl   $24,$24,7
2754		 andi  $24,$24,0x1C
2755		 lh    $7,0x00($23)
2756		 addu  $24,$24,$21
2757		 lw    $14,0x20($24)
2758		 addiu $23,$23,2
2759		 addu  $14,$14,$7
2760		 lw    $25,0x88($21)
2761		 sw    $15,m68k_ICount
2762		 or    $5,$0,$2
2763		 or    $4,$0,$14
2764		 jalr  $25
2765		 sw    $23,0x4C($21)    	 # Delay slot
2766		 lw    $15,m68k_ICount
2767		 addiu $15,$15,-22
2768		 bgez  $15,3f
2769		 lhu   $24,0x00($23)    	 # Delay slot
2770		 j     MainExit
2771	3:
2772		 sll   $7,$24,2         	 # Delay slot
2773		 addu  $7,$7,$30
2774		 lw    $7,0x00($7)
2775		 jr    $7
2776		 nop                    	 # Delay slot
2777
2778OP0_1178:				#:
2779		 addiu $23,$23,2
2780
2781		 lh    $14,0x00($23)
2782		 addiu $23,$23,2
2783		 lw    $25,0x7C($21)
2784		 sw    $15,m68k_ICount
2785		 sw    $24,0x44($29)
2786		 or    $4,$0,$14
2787		 jalr  $25
2788		 sw    $23,0x4C($21)    	 # Delay slot
2789		 lw    $24,0x44($29)
2790		 lw    $15,m68k_ICount
2791		 and   $16,$0,$0        	 # Clear Carry
2792		 and   $17,$0,$0        	 # Clear Overflow
2793		 srl   $19,$2,7         	 # Set Sign
2794		 sltiu $18,$2,1         	 # Set Zero
2795		 srl   $24,$24,7
2796		 andi  $24,$24,0x1C
2797		 lh    $7,0x00($23)
2798		 addu  $24,$24,$21
2799		 lw    $14,0x20($24)
2800		 addiu $23,$23,2
2801		 addu  $14,$14,$7
2802		 lw    $25,0x88($21)
2803		 sw    $15,m68k_ICount
2804		 or    $5,$0,$2
2805		 or    $4,$0,$14
2806		 jalr  $25
2807		 sw    $23,0x4C($21)    	 # Delay slot
2808		 lw    $15,m68k_ICount
2809		 addiu $15,$15,-20
2810		 bgez  $15,3f
2811		 lhu   $24,0x00($23)    	 # Delay slot
2812		 j     MainExit
2813	3:
2814		 sll   $7,$24,2         	 # Delay slot
2815		 addu  $7,$7,$30
2816		 lw    $7,0x00($7)
2817		 jr    $7
2818		 nop                    	 # Delay slot
2819
2820OP0_1179:				#:
2821		 addiu $23,$23,2
2822
2823		 lhu   $14,0x00($23)
2824		 lhu   $25,0x02($23)
2825		 sll   $14,$14,16
2826		 or    $14,$14,$25
2827		 addiu $23,$23,4
2828		 lw    $25,0x7C($21)
2829		 sw    $15,m68k_ICount
2830		 sw    $24,0x44($29)
2831		 or    $4,$0,$14
2832		 jalr  $25
2833		 sw    $23,0x4C($21)    	 # Delay slot
2834		 lw    $24,0x44($29)
2835		 lw    $15,m68k_ICount
2836		 and   $16,$0,$0        	 # Clear Carry
2837		 and   $17,$0,$0        	 # Clear Overflow
2838		 srl   $19,$2,7         	 # Set Sign
2839		 sltiu $18,$2,1         	 # Set Zero
2840		 srl   $24,$24,7
2841		 andi  $24,$24,0x1C
2842		 lh    $7,0x00($23)
2843		 addu  $24,$24,$21
2844		 lw    $14,0x20($24)
2845		 addiu $23,$23,2
2846		 addu  $14,$14,$7
2847		 lw    $25,0x88($21)
2848		 sw    $15,m68k_ICount
2849		 or    $5,$0,$2
2850		 or    $4,$0,$14
2851		 jalr  $25
2852		 sw    $23,0x4C($21)    	 # Delay slot
2853		 lw    $15,m68k_ICount
2854		 addiu $15,$15,-24
2855		 bgez  $15,3f
2856		 lhu   $24,0x00($23)    	 # Delay slot
2857		 j     MainExit
2858	3:
2859		 sll   $7,$24,2         	 # Delay slot
2860		 addu  $7,$7,$30
2861		 lw    $7,0x00($7)
2862		 jr    $7
2863		 nop                    	 # Delay slot
2864
2865OP0_117a:				#:
2866		 addiu $23,$23,2
2867
2868		 lh    $7,0x00($23)
2869		 subu  $25,$23,$22
2870		 addu  $14,$25,$7       	 # Add Offset to PC
2871		 addiu $23,$23,2
2872		 lw    $25,0x98($21)
2873		 sw    $15,m68k_ICount
2874		 sw    $24,0x44($29)
2875		 or    $4,$0,$14
2876		 jalr  $25
2877		 sw    $23,0x4C($21)    	 # Delay slot
2878		 lw    $24,0x44($29)
2879		 lw    $15,m68k_ICount
2880		 and   $16,$0,$0        	 # Clear Carry
2881		 and   $17,$0,$0        	 # Clear Overflow
2882		 srl   $19,$2,7         	 # Set Sign
2883		 sltiu $18,$2,1         	 # Set Zero
2884		 srl   $24,$24,7
2885		 andi  $24,$24,0x1C
2886		 lh    $7,0x00($23)
2887		 addu  $24,$24,$21
2888		 lw    $14,0x20($24)
2889		 addiu $23,$23,2
2890		 addu  $14,$14,$7
2891		 lw    $25,0x88($21)
2892		 sw    $15,m68k_ICount
2893		 or    $5,$0,$2
2894		 or    $4,$0,$14
2895		 jalr  $25
2896		 sw    $23,0x4C($21)    	 # Delay slot
2897		 lw    $15,m68k_ICount
2898		 addiu $15,$15,-20
2899		 bgez  $15,3f
2900		 lhu   $24,0x00($23)    	 # Delay slot
2901		 j     MainExit
2902	3:
2903		 sll   $7,$24,2         	 # Delay slot
2904		 addu  $7,$7,$30
2905		 lw    $7,0x00($7)
2906		 jr    $7
2907		 nop                    	 # Delay slot
2908
2909OP0_117b:				#:
2910		 addiu $23,$23,2
2911
2912		 subu  $14,$23,$22       	 # Get PC
2913		 lhu   $7,0x00($23)
2914		 addiu $23,$23,2
2915		 seb   $6,$7
2916		 or    $25,$0,$7
2917		 srl   $7,$7,12
2918		 andi  $25,$25,0x0800
2919		 sll   $7,$7,2
2920		 addu  $7,$7,$21
2921		 bne   $25,$0,0f
2922		 lw    $25,0x00($7)      	 # Delay slot
2923		 seh   $25,$25
2924	0:
2925		 addu  $25,$14,$25
2926		 addu  $14,$25,$6
2927		 lw    $25,0x98($21)
2928		 sw    $15,m68k_ICount
2929		 sw    $24,0x44($29)
2930		 or    $4,$0,$14
2931		 jalr  $25
2932		 sw    $23,0x4C($21)    	 # Delay slot
2933		 lw    $24,0x44($29)
2934		 lw    $15,m68k_ICount
2935		 and   $16,$0,$0        	 # Clear Carry
2936		 and   $17,$0,$0        	 # Clear Overflow
2937		 srl   $19,$2,7         	 # Set Sign
2938		 sltiu $18,$2,1         	 # Set Zero
2939		 srl   $24,$24,7
2940		 andi  $24,$24,0x1C
2941		 lh    $7,0x00($23)
2942		 addu  $24,$24,$21
2943		 lw    $14,0x20($24)
2944		 addiu $23,$23,2
2945		 addu  $14,$14,$7
2946		 lw    $25,0x88($21)
2947		 sw    $15,m68k_ICount
2948		 or    $5,$0,$2
2949		 or    $4,$0,$14
2950		 jalr  $25
2951		 sw    $23,0x4C($21)    	 # Delay slot
2952		 lw    $15,m68k_ICount
2953		 addiu $15,$15,-22
2954		 bgez  $15,3f
2955		 lhu   $24,0x00($23)    	 # Delay slot
2956		 j     MainExit
2957	3:
2958		 sll   $7,$24,2         	 # Delay slot
2959		 addu  $7,$7,$30
2960		 lw    $7,0x00($7)
2961		 jr    $7
2962		 nop                    	 # Delay slot
2963
2964OP0_117c:				#:
2965		 addiu $23,$23,2
2966
2967		 lbu   $2,0x00($23)
2968		 addiu $23,$23,2
2969		 and   $16,$0,$0        	 # Clear Carry
2970		 and   $17,$0,$0        	 # Clear Overflow
2971		 srl   $19,$2,7         	 # Set Sign
2972		 sltiu $18,$2,1         	 # Set Zero
2973		 srl   $24,$24,7
2974		 andi  $24,$24,0x1C
2975		 lh    $7,0x00($23)
2976		 addu  $24,$24,$21
2977		 lw    $14,0x20($24)
2978		 addiu $23,$23,2
2979		 addu  $14,$14,$7
2980		 lw    $25,0x88($21)
2981		 sw    $15,m68k_ICount
2982		 or    $5,$0,$2
2983		 or    $4,$0,$14
2984		 jalr  $25
2985		 sw    $23,0x4C($21)    	 # Delay slot
2986		 lw    $15,m68k_ICount
2987		 addiu $15,$15,-12
2988		 bgez  $15,3f
2989		 lhu   $24,0x00($23)    	 # Delay slot
2990		 j     MainExit
2991	3:
2992		 sll   $7,$24,2         	 # Delay slot
2993		 addu  $7,$7,$30
2994		 lw    $7,0x00($7)
2995		 jr    $7
2996		 nop                    	 # Delay slot
2997
2998OP0_1180:				#:
2999		 addiu $23,$23,2
3000
3001		 and   $8,$24,0x0f
3002		 sll   $8,$8,2
3003		 addu  $8,$8,$21
3004		 lbu   $2,0x00($8)
3005		 and   $16,$0,$0        	 # Clear Carry
3006		 and   $17,$0,$0        	 # Clear Overflow
3007		 srl   $19,$2,7         	 # Set Sign
3008		 sltiu $18,$2,1         	 # Set Zero
3009		 srl   $24,$24,7
3010		 andi  $24,$24,0x1C
3011		 addu  $24,$24,$21
3012		 lw    $14,0x20($24)
3013		 lhu   $7,0x00($23)
3014		 addiu $23,$23,2
3015		 seb   $6,$7
3016		 or    $25,$0,$7
3017		 srl   $7,$7,12
3018		 andi  $25,$25,0x0800
3019		 sll   $7,$7,2
3020		 addu  $7,$7,$21
3021		 bne   $25,$0,0f
3022		 lw    $25,0x00($7)      	 # Delay slot
3023		 seh   $25,$25
3024	0:
3025		 addu  $25,$14,$25
3026		 addu  $14,$25,$6
3027		 lw    $25,0x88($21)
3028		 sw    $15,m68k_ICount
3029		 or    $5,$0,$2
3030		 or    $4,$0,$14
3031		 jalr  $25
3032		 sw    $23,0x4C($21)    	 # Delay slot
3033		 lw    $15,m68k_ICount
3034		 addiu $15,$15,-14
3035		 bgez  $15,3f
3036		 lhu   $24,0x00($23)    	 # Delay slot
3037		 j     MainExit
3038	3:
3039		 sll   $7,$24,2         	 # Delay slot
3040		 addu  $7,$7,$30
3041		 lw    $7,0x00($7)
3042		 jr    $7
3043		 nop                    	 # Delay slot
3044
3045OP0_1190:				#:
3046		 addiu $23,$23,2
3047
3048		 and   $8,$24,0x07
3049		 sll   $8,$8,2
3050		 addu  $8,$8,$21
3051		 lw    $14,0x20($8)
3052		 lw    $25,0x7C($21)
3053		 sw    $15,m68k_ICount
3054		 sw    $24,0x44($29)
3055		 or    $4,$0,$14
3056		 jalr  $25
3057		 sw    $23,0x4C($21)    	 # Delay slot
3058		 lw    $24,0x44($29)
3059		 lw    $15,m68k_ICount
3060		 and   $16,$0,$0        	 # Clear Carry
3061		 and   $17,$0,$0        	 # Clear Overflow
3062		 srl   $19,$2,7         	 # Set Sign
3063		 sltiu $18,$2,1         	 # Set Zero
3064		 srl   $24,$24,7
3065		 andi  $24,$24,0x1C
3066		 addu  $24,$24,$21
3067		 lw    $14,0x20($24)
3068		 lhu   $7,0x00($23)
3069		 addiu $23,$23,2
3070		 seb   $6,$7
3071		 or    $25,$0,$7
3072		 srl   $7,$7,12
3073		 andi  $25,$25,0x0800
3074		 sll   $7,$7,2
3075		 addu  $7,$7,$21
3076		 bne   $25,$0,0f
3077		 lw    $25,0x00($7)      	 # Delay slot
3078		 seh   $25,$25
3079	0:
3080		 addu  $25,$14,$25
3081		 addu  $14,$25,$6
3082		 lw    $25,0x88($21)
3083		 sw    $15,m68k_ICount
3084		 or    $5,$0,$2
3085		 or    $4,$0,$14
3086		 jalr  $25
3087		 sw    $23,0x4C($21)    	 # Delay slot
3088		 lw    $15,m68k_ICount
3089		 addiu $15,$15,-18
3090		 bgez  $15,3f
3091		 lhu   $24,0x00($23)    	 # Delay slot
3092		 j     MainExit
3093	3:
3094		 sll   $7,$24,2         	 # Delay slot
3095		 addu  $7,$7,$30
3096		 lw    $7,0x00($7)
3097		 jr    $7
3098		 nop                    	 # Delay slot
3099
3100OP0_1198:				#:
3101		 addiu $23,$23,2
3102
3103		 and   $8,$24,0x07
3104		 sll   $8,$8,2
3105		 addu  $8,$8,$21
3106		 lw    $14,0x20($8)
3107		 addiu $25,$14,1
3108		 sw    $25,0x20($8)
3109		 lw    $25,0x7C($21)
3110		 sw    $15,m68k_ICount
3111		 sw    $24,0x44($29)
3112		 or    $4,$0,$14
3113		 jalr  $25
3114		 sw    $23,0x4C($21)    	 # Delay slot
3115		 lw    $24,0x44($29)
3116		 lw    $15,m68k_ICount
3117		 and   $16,$0,$0        	 # Clear Carry
3118		 and   $17,$0,$0        	 # Clear Overflow
3119		 srl   $19,$2,7         	 # Set Sign
3120		 sltiu $18,$2,1         	 # Set Zero
3121		 srl   $24,$24,7
3122		 andi  $24,$24,0x1C
3123		 addu  $24,$24,$21
3124		 lw    $14,0x20($24)
3125		 lhu   $7,0x00($23)
3126		 addiu $23,$23,2
3127		 seb   $6,$7
3128		 or    $25,$0,$7
3129		 srl   $7,$7,12
3130		 andi  $25,$25,0x0800
3131		 sll   $7,$7,2
3132		 addu  $7,$7,$21
3133		 bne   $25,$0,0f
3134		 lw    $25,0x00($7)      	 # Delay slot
3135		 seh   $25,$25
3136	0:
3137		 addu  $25,$14,$25
3138		 addu  $14,$25,$6
3139		 lw    $25,0x88($21)
3140		 sw    $15,m68k_ICount
3141		 or    $5,$0,$2
3142		 or    $4,$0,$14
3143		 jalr  $25
3144		 sw    $23,0x4C($21)    	 # Delay slot
3145		 lw    $15,m68k_ICount
3146		 addiu $15,$15,-18
3147		 bgez  $15,3f
3148		 lhu   $24,0x00($23)    	 # Delay slot
3149		 j     MainExit
3150	3:
3151		 sll   $7,$24,2         	 # Delay slot
3152		 addu  $7,$7,$30
3153		 lw    $7,0x00($7)
3154		 jr    $7
3155		 nop                    	 # Delay slot
3156
3157OP0_119f:				#:
3158		 addiu $23,$23,2
3159
3160		 lw    $14,0x3C($21)    	 # Get A7
3161		 addiu $25,$14,2
3162		 sw    $25,0x3C($21)
3163		 lw    $25,0x7C($21)
3164		 sw    $15,m68k_ICount
3165		 sw    $24,0x44($29)
3166		 or    $4,$0,$14
3167		 jalr  $25
3168		 sw    $23,0x4C($21)    	 # Delay slot
3169		 lw    $24,0x44($29)
3170		 lw    $15,m68k_ICount
3171		 and   $16,$0,$0        	 # Clear Carry
3172		 and   $17,$0,$0        	 # Clear Overflow
3173		 srl   $19,$2,7         	 # Set Sign
3174		 sltiu $18,$2,1         	 # Set Zero
3175		 srl   $24,$24,7
3176		 andi  $24,$24,0x1C
3177		 addu  $24,$24,$21
3178		 lw    $14,0x20($24)
3179		 lhu   $7,0x00($23)
3180		 addiu $23,$23,2
3181		 seb   $6,$7
3182		 or    $25,$0,$7
3183		 srl   $7,$7,12
3184		 andi  $25,$25,0x0800
3185		 sll   $7,$7,2
3186		 addu  $7,$7,$21
3187		 bne   $25,$0,0f
3188		 lw    $25,0x00($7)      	 # Delay slot
3189		 seh   $25,$25
3190	0:
3191		 addu  $25,$14,$25
3192		 addu  $14,$25,$6
3193		 lw    $25,0x88($21)
3194		 sw    $15,m68k_ICount
3195		 or    $5,$0,$2
3196		 or    $4,$0,$14
3197		 jalr  $25
3198		 sw    $23,0x4C($21)    	 # Delay slot
3199		 lw    $15,m68k_ICount
3200		 addiu $15,$15,-18
3201		 bgez  $15,3f
3202		 lhu   $24,0x00($23)    	 # Delay slot
3203		 j     MainExit
3204	3:
3205		 sll   $7,$24,2         	 # Delay slot
3206		 addu  $7,$7,$30
3207		 lw    $7,0x00($7)
3208		 jr    $7
3209		 nop                    	 # Delay slot
3210
3211OP0_11a0:				#:
3212		 addiu $23,$23,2
3213
3214		 and   $8,$24,0x07
3215		 sll   $8,$8,2
3216		 addu  $8,$8,$21
3217		 lw    $14,0x20($8)
3218		 addiu $14,$14,-1
3219		 sw    $14,0x20($8)
3220		 lw    $25,0x7C($21)
3221		 sw    $15,m68k_ICount
3222		 sw    $24,0x44($29)
3223		 or    $4,$0,$14
3224		 jalr  $25
3225		 sw    $23,0x4C($21)    	 # Delay slot
3226		 lw    $24,0x44($29)
3227		 lw    $15,m68k_ICount
3228		 and   $16,$0,$0        	 # Clear Carry
3229		 and   $17,$0,$0        	 # Clear Overflow
3230		 srl   $19,$2,7         	 # Set Sign
3231		 sltiu $18,$2,1         	 # Set Zero
3232		 srl   $24,$24,7
3233		 andi  $24,$24,0x1C
3234		 addu  $24,$24,$21
3235		 lw    $14,0x20($24)
3236		 lhu   $7,0x00($23)
3237		 addiu $23,$23,2
3238		 seb   $6,$7
3239		 or    $25,$0,$7
3240		 srl   $7,$7,12
3241		 andi  $25,$25,0x0800
3242		 sll   $7,$7,2
3243		 addu  $7,$7,$21
3244		 bne   $25,$0,0f
3245		 lw    $25,0x00($7)      	 # Delay slot
3246		 seh   $25,$25
3247	0:
3248		 addu  $25,$14,$25
3249		 addu  $14,$25,$6
3250		 lw    $25,0x88($21)
3251		 sw    $15,m68k_ICount
3252		 or    $5,$0,$2
3253		 or    $4,$0,$14
3254		 jalr  $25
3255		 sw    $23,0x4C($21)    	 # Delay slot
3256		 lw    $15,m68k_ICount
3257		 addiu $15,$15,-20
3258		 bgez  $15,3f
3259		 lhu   $24,0x00($23)    	 # Delay slot
3260		 j     MainExit
3261	3:
3262		 sll   $7,$24,2         	 # Delay slot
3263		 addu  $7,$7,$30
3264		 lw    $7,0x00($7)
3265		 jr    $7
3266		 nop                    	 # Delay slot
3267
3268OP0_11a7:				#:
3269		 addiu $23,$23,2
3270
3271		 lw    $14,0x3C($21)    	 # Get A7
3272		 addiu $14,$14,-2
3273		 sw    $14,0x3C($21)
3274		 lw    $25,0x7C($21)
3275		 sw    $15,m68k_ICount
3276		 sw    $24,0x44($29)
3277		 or    $4,$0,$14
3278		 jalr  $25
3279		 sw    $23,0x4C($21)    	 # Delay slot
3280		 lw    $24,0x44($29)
3281		 lw    $15,m68k_ICount
3282		 and   $16,$0,$0        	 # Clear Carry
3283		 and   $17,$0,$0        	 # Clear Overflow
3284		 srl   $19,$2,7         	 # Set Sign
3285		 sltiu $18,$2,1         	 # Set Zero
3286		 srl   $24,$24,7
3287		 andi  $24,$24,0x1C
3288		 addu  $24,$24,$21
3289		 lw    $14,0x20($24)
3290		 lhu   $7,0x00($23)
3291		 addiu $23,$23,2
3292		 seb   $6,$7
3293		 or    $25,$0,$7
3294		 srl   $7,$7,12
3295		 andi  $25,$25,0x0800
3296		 sll   $7,$7,2
3297		 addu  $7,$7,$21
3298		 bne   $25,$0,0f
3299		 lw    $25,0x00($7)      	 # Delay slot
3300		 seh   $25,$25
3301	0:
3302		 addu  $25,$14,$25
3303		 addu  $14,$25,$6
3304		 lw    $25,0x88($21)
3305		 sw    $15,m68k_ICount
3306		 or    $5,$0,$2
3307		 or    $4,$0,$14
3308		 jalr  $25
3309		 sw    $23,0x4C($21)    	 # Delay slot
3310		 lw    $15,m68k_ICount
3311		 addiu $15,$15,-20
3312		 bgez  $15,3f
3313		 lhu   $24,0x00($23)    	 # Delay slot
3314		 j     MainExit
3315	3:
3316		 sll   $7,$24,2         	 # Delay slot
3317		 addu  $7,$7,$30
3318		 lw    $7,0x00($7)
3319		 jr    $7
3320		 nop                    	 # Delay slot
3321
3322OP0_11a8:				#:
3323		 addiu $23,$23,2
3324
3325		 and   $8,$24,0x07
3326		 lh    $7,0x00($23)
3327		 sll   $8,$8,2
3328		 addu  $8,$8,$21
3329		 lw    $14,0x20($8)
3330		 addiu $23,$23,2
3331		 addu  $14,$14,$7
3332		 lw    $25,0x7C($21)
3333		 sw    $15,m68k_ICount
3334		 sw    $24,0x44($29)
3335		 or    $4,$0,$14
3336		 jalr  $25
3337		 sw    $23,0x4C($21)    	 # Delay slot
3338		 lw    $24,0x44($29)
3339		 lw    $15,m68k_ICount
3340		 and   $16,$0,$0        	 # Clear Carry
3341		 and   $17,$0,$0        	 # Clear Overflow
3342		 srl   $19,$2,7         	 # Set Sign
3343		 sltiu $18,$2,1         	 # Set Zero
3344		 srl   $24,$24,7
3345		 andi  $24,$24,0x1C
3346		 addu  $24,$24,$21
3347		 lw    $14,0x20($24)
3348		 lhu   $7,0x00($23)
3349		 addiu $23,$23,2
3350		 seb   $6,$7
3351		 or    $25,$0,$7
3352		 srl   $7,$7,12
3353		 andi  $25,$25,0x0800
3354		 sll   $7,$7,2
3355		 addu  $7,$7,$21
3356		 bne   $25,$0,0f
3357		 lw    $25,0x00($7)      	 # Delay slot
3358		 seh   $25,$25
3359	0:
3360		 addu  $25,$14,$25
3361		 addu  $14,$25,$6
3362		 lw    $25,0x88($21)
3363		 sw    $15,m68k_ICount
3364		 or    $5,$0,$2
3365		 or    $4,$0,$14
3366		 jalr  $25
3367		 sw    $23,0x4C($21)    	 # Delay slot
3368		 lw    $15,m68k_ICount
3369		 addiu $15,$15,-22
3370		 bgez  $15,3f
3371		 lhu   $24,0x00($23)    	 # Delay slot
3372		 j     MainExit
3373	3:
3374		 sll   $7,$24,2         	 # Delay slot
3375		 addu  $7,$7,$30
3376		 lw    $7,0x00($7)
3377		 jr    $7
3378		 nop                    	 # Delay slot
3379
3380OP0_11b0:				#:
3381		 addiu $23,$23,2
3382
3383		 and   $8,$24,0x07
3384		 sll   $8,$8,2
3385		 addu  $8,$8,$21
3386		 lw    $14,0x20($8)
3387		 lhu   $7,0x00($23)
3388		 addiu $23,$23,2
3389		 seb   $6,$7
3390		 or    $25,$0,$7
3391		 srl   $7,$7,12
3392		 andi  $25,$25,0x0800
3393		 sll   $7,$7,2
3394		 addu  $7,$7,$21
3395		 bne   $25,$0,0f
3396		 lw    $25,0x00($7)      	 # Delay slot
3397		 seh   $25,$25
3398	0:
3399		 addu  $25,$14,$25
3400		 addu  $14,$25,$6
3401		 lw    $25,0x7C($21)
3402		 sw    $15,m68k_ICount
3403		 sw    $24,0x44($29)
3404		 or    $4,$0,$14
3405		 jalr  $25
3406		 sw    $23,0x4C($21)    	 # Delay slot
3407		 lw    $24,0x44($29)
3408		 lw    $15,m68k_ICount
3409		 and   $16,$0,$0        	 # Clear Carry
3410		 and   $17,$0,$0        	 # Clear Overflow
3411		 srl   $19,$2,7         	 # Set Sign
3412		 sltiu $18,$2,1         	 # Set Zero
3413		 srl   $24,$24,7
3414		 andi  $24,$24,0x1C
3415		 addu  $24,$24,$21
3416		 lw    $14,0x20($24)
3417		 lhu   $7,0x00($23)
3418		 addiu $23,$23,2
3419		 seb   $6,$7
3420		 or    $25,$0,$7
3421		 srl   $7,$7,12
3422		 andi  $25,$25,0x0800
3423		 sll   $7,$7,2
3424		 addu  $7,$7,$21
3425		 bne   $25,$0,0f
3426		 lw    $25,0x00($7)      	 # Delay slot
3427		 seh   $25,$25
3428	0:
3429		 addu  $25,$14,$25
3430		 addu  $14,$25,$6
3431		 lw    $25,0x88($21)
3432		 sw    $15,m68k_ICount
3433		 or    $5,$0,$2
3434		 or    $4,$0,$14
3435		 jalr  $25
3436		 sw    $23,0x4C($21)    	 # Delay slot
3437		 lw    $15,m68k_ICount
3438		 addiu $15,$15,-24
3439		 bgez  $15,3f
3440		 lhu   $24,0x00($23)    	 # Delay slot
3441		 j     MainExit
3442	3:
3443		 sll   $7,$24,2         	 # Delay slot
3444		 addu  $7,$7,$30
3445		 lw    $7,0x00($7)
3446		 jr    $7
3447		 nop                    	 # Delay slot
3448
3449OP0_11b8:				#:
3450		 addiu $23,$23,2
3451
3452		 lh    $14,0x00($23)
3453		 addiu $23,$23,2
3454		 lw    $25,0x7C($21)
3455		 sw    $15,m68k_ICount
3456		 sw    $24,0x44($29)
3457		 or    $4,$0,$14
3458		 jalr  $25
3459		 sw    $23,0x4C($21)    	 # Delay slot
3460		 lw    $24,0x44($29)
3461		 lw    $15,m68k_ICount
3462		 and   $16,$0,$0        	 # Clear Carry
3463		 and   $17,$0,$0        	 # Clear Overflow
3464		 srl   $19,$2,7         	 # Set Sign
3465		 sltiu $18,$2,1         	 # Set Zero
3466		 srl   $24,$24,7
3467		 andi  $24,$24,0x1C
3468		 addu  $24,$24,$21
3469		 lw    $14,0x20($24)
3470		 lhu   $7,0x00($23)
3471		 addiu $23,$23,2
3472		 seb   $6,$7
3473		 or    $25,$0,$7
3474		 srl   $7,$7,12
3475		 andi  $25,$25,0x0800
3476		 sll   $7,$7,2
3477		 addu  $7,$7,$21
3478		 bne   $25,$0,0f
3479		 lw    $25,0x00($7)      	 # Delay slot
3480		 seh   $25,$25
3481	0:
3482		 addu  $25,$14,$25
3483		 addu  $14,$25,$6
3484		 lw    $25,0x88($21)
3485		 sw    $15,m68k_ICount
3486		 or    $5,$0,$2
3487		 or    $4,$0,$14
3488		 jalr  $25
3489		 sw    $23,0x4C($21)    	 # Delay slot
3490		 lw    $15,m68k_ICount
3491		 addiu $15,$15,-22
3492		 bgez  $15,3f
3493		 lhu   $24,0x00($23)    	 # Delay slot
3494		 j     MainExit
3495	3:
3496		 sll   $7,$24,2         	 # Delay slot
3497		 addu  $7,$7,$30
3498		 lw    $7,0x00($7)
3499		 jr    $7
3500		 nop                    	 # Delay slot
3501
3502OP0_11b9:				#:
3503		 addiu $23,$23,2
3504
3505		 lhu   $14,0x00($23)
3506		 lhu   $25,0x02($23)
3507		 sll   $14,$14,16
3508		 or    $14,$14,$25
3509		 addiu $23,$23,4
3510		 lw    $25,0x7C($21)
3511		 sw    $15,m68k_ICount
3512		 sw    $24,0x44($29)
3513		 or    $4,$0,$14
3514		 jalr  $25
3515		 sw    $23,0x4C($21)    	 # Delay slot
3516		 lw    $24,0x44($29)
3517		 lw    $15,m68k_ICount
3518		 and   $16,$0,$0        	 # Clear Carry
3519		 and   $17,$0,$0        	 # Clear Overflow
3520		 srl   $19,$2,7         	 # Set Sign
3521		 sltiu $18,$2,1         	 # Set Zero
3522		 srl   $24,$24,7
3523		 andi  $24,$24,0x1C
3524		 addu  $24,$24,$21
3525		 lw    $14,0x20($24)
3526		 lhu   $7,0x00($23)
3527		 addiu $23,$23,2
3528		 seb   $6,$7
3529		 or    $25,$0,$7
3530		 srl   $7,$7,12
3531		 andi  $25,$25,0x0800
3532		 sll   $7,$7,2
3533		 addu  $7,$7,$21
3534		 bne   $25,$0,0f
3535		 lw    $25,0x00($7)      	 # Delay slot
3536		 seh   $25,$25
3537	0:
3538		 addu  $25,$14,$25
3539		 addu  $14,$25,$6
3540		 lw    $25,0x88($21)
3541		 sw    $15,m68k_ICount
3542		 or    $5,$0,$2
3543		 or    $4,$0,$14
3544		 jalr  $25
3545		 sw    $23,0x4C($21)    	 # Delay slot
3546		 lw    $15,m68k_ICount
3547		 addiu $15,$15,-26
3548		 bgez  $15,3f
3549		 lhu   $24,0x00($23)    	 # Delay slot
3550		 j     MainExit
3551	3:
3552		 sll   $7,$24,2         	 # Delay slot
3553		 addu  $7,$7,$30
3554		 lw    $7,0x00($7)
3555		 jr    $7
3556		 nop                    	 # Delay slot
3557
3558OP0_11ba:				#:
3559		 addiu $23,$23,2
3560
3561		 lh    $7,0x00($23)
3562		 subu  $25,$23,$22
3563		 addu  $14,$25,$7       	 # Add Offset to PC
3564		 addiu $23,$23,2
3565		 lw    $25,0x98($21)
3566		 sw    $15,m68k_ICount
3567		 sw    $24,0x44($29)
3568		 or    $4,$0,$14
3569		 jalr  $25
3570		 sw    $23,0x4C($21)    	 # Delay slot
3571		 lw    $24,0x44($29)
3572		 lw    $15,m68k_ICount
3573		 and   $16,$0,$0        	 # Clear Carry
3574		 and   $17,$0,$0        	 # Clear Overflow
3575		 srl   $19,$2,7         	 # Set Sign
3576		 sltiu $18,$2,1         	 # Set Zero
3577		 srl   $24,$24,7
3578		 andi  $24,$24,0x1C
3579		 addu  $24,$24,$21
3580		 lw    $14,0x20($24)
3581		 lhu   $7,0x00($23)
3582		 addiu $23,$23,2
3583		 seb   $6,$7
3584		 or    $25,$0,$7
3585		 srl   $7,$7,12
3586		 andi  $25,$25,0x0800
3587		 sll   $7,$7,2
3588		 addu  $7,$7,$21
3589		 bne   $25,$0,0f
3590		 lw    $25,0x00($7)      	 # Delay slot
3591		 seh   $25,$25
3592	0:
3593		 addu  $25,$14,$25
3594		 addu  $14,$25,$6
3595		 lw    $25,0x88($21)
3596		 sw    $15,m68k_ICount
3597		 or    $5,$0,$2
3598		 or    $4,$0,$14
3599		 jalr  $25
3600		 sw    $23,0x4C($21)    	 # Delay slot
3601		 lw    $15,m68k_ICount
3602		 addiu $15,$15,-22
3603		 bgez  $15,3f
3604		 lhu   $24,0x00($23)    	 # Delay slot
3605		 j     MainExit
3606	3:
3607		 sll   $7,$24,2         	 # Delay slot
3608		 addu  $7,$7,$30
3609		 lw    $7,0x00($7)
3610		 jr    $7
3611		 nop                    	 # Delay slot
3612
3613OP0_11bb:				#:
3614		 addiu $23,$23,2
3615
3616		 subu  $14,$23,$22       	 # Get PC
3617		 lhu   $7,0x00($23)
3618		 addiu $23,$23,2
3619		 seb   $6,$7
3620		 or    $25,$0,$7
3621		 srl   $7,$7,12
3622		 andi  $25,$25,0x0800
3623		 sll   $7,$7,2
3624		 addu  $7,$7,$21
3625		 bne   $25,$0,0f
3626		 lw    $25,0x00($7)      	 # Delay slot
3627		 seh   $25,$25
3628	0:
3629		 addu  $25,$14,$25
3630		 addu  $14,$25,$6
3631		 lw    $25,0x98($21)
3632		 sw    $15,m68k_ICount
3633		 sw    $24,0x44($29)
3634		 or    $4,$0,$14
3635		 jalr  $25
3636		 sw    $23,0x4C($21)    	 # Delay slot
3637		 lw    $24,0x44($29)
3638		 lw    $15,m68k_ICount
3639		 and   $16,$0,$0        	 # Clear Carry
3640		 and   $17,$0,$0        	 # Clear Overflow
3641		 srl   $19,$2,7         	 # Set Sign
3642		 sltiu $18,$2,1         	 # Set Zero
3643		 srl   $24,$24,7
3644		 andi  $24,$24,0x1C
3645		 addu  $24,$24,$21
3646		 lw    $14,0x20($24)
3647		 lhu   $7,0x00($23)
3648		 addiu $23,$23,2
3649		 seb   $6,$7
3650		 or    $25,$0,$7
3651		 srl   $7,$7,12
3652		 andi  $25,$25,0x0800
3653		 sll   $7,$7,2
3654		 addu  $7,$7,$21
3655		 bne   $25,$0,0f
3656		 lw    $25,0x00($7)      	 # Delay slot
3657		 seh   $25,$25
3658	0:
3659		 addu  $25,$14,$25
3660		 addu  $14,$25,$6
3661		 lw    $25,0x88($21)
3662		 sw    $15,m68k_ICount
3663		 or    $5,$0,$2
3664		 or    $4,$0,$14
3665		 jalr  $25
3666		 sw    $23,0x4C($21)    	 # Delay slot
3667		 lw    $15,m68k_ICount
3668		 addiu $15,$15,-24
3669		 bgez  $15,3f
3670		 lhu   $24,0x00($23)    	 # Delay slot
3671		 j     MainExit
3672	3:
3673		 sll   $7,$24,2         	 # Delay slot
3674		 addu  $7,$7,$30
3675		 lw    $7,0x00($7)
3676		 jr    $7
3677		 nop                    	 # Delay slot
3678
3679OP0_11bc:				#:
3680		 addiu $23,$23,2
3681
3682		 lbu   $2,0x00($23)
3683		 addiu $23,$23,2
3684		 and   $16,$0,$0        	 # Clear Carry
3685		 and   $17,$0,$0        	 # Clear Overflow
3686		 srl   $19,$2,7         	 # Set Sign
3687		 sltiu $18,$2,1         	 # Set Zero
3688		 srl   $24,$24,7
3689		 andi  $24,$24,0x1C
3690		 addu  $24,$24,$21
3691		 lw    $14,0x20($24)
3692		 lhu   $7,0x00($23)
3693		 addiu $23,$23,2
3694		 seb   $6,$7
3695		 or    $25,$0,$7
3696		 srl   $7,$7,12
3697		 andi  $25,$25,0x0800
3698		 sll   $7,$7,2
3699		 addu  $7,$7,$21
3700		 bne   $25,$0,0f
3701		 lw    $25,0x00($7)      	 # Delay slot
3702		 seh   $25,$25
3703	0:
3704		 addu  $25,$14,$25
3705		 addu  $14,$25,$6
3706		 lw    $25,0x88($21)
3707		 sw    $15,m68k_ICount
3708		 or    $5,$0,$2
3709		 or    $4,$0,$14
3710		 jalr  $25
3711		 sw    $23,0x4C($21)    	 # Delay slot
3712		 lw    $15,m68k_ICount
3713		 addiu $15,$15,-14
3714		 bgez  $15,3f
3715		 lhu   $24,0x00($23)    	 # Delay slot
3716		 j     MainExit
3717	3:
3718		 sll   $7,$24,2         	 # Delay slot
3719		 addu  $7,$7,$30
3720		 lw    $7,0x00($7)
3721		 jr    $7
3722		 nop                    	 # Delay slot
3723
3724OP0_11c0:				#:
3725		 addiu $23,$23,2
3726
3727		 and   $8,$24,0x0f
3728		 sll   $8,$8,2
3729		 addu  $8,$8,$21
3730		 lbu   $2,0x00($8)
3731		 and   $16,$0,$0        	 # Clear Carry
3732		 and   $17,$0,$0        	 # Clear Overflow
3733		 srl   $19,$2,7         	 # Set Sign
3734		 sltiu $18,$2,1         	 # Set Zero
3735		 lh    $14,0x00($23)
3736		 addiu $23,$23,2
3737		 lw    $25,0x88($21)
3738		 sw    $15,m68k_ICount
3739		 or    $5,$0,$2
3740		 or    $4,$0,$14
3741		 jalr  $25
3742		 sw    $23,0x4C($21)    	 # Delay slot
3743		 lw    $15,m68k_ICount
3744		 addiu $15,$15,-12
3745		 bgez  $15,3f
3746		 lhu   $24,0x00($23)    	 # Delay slot
3747		 j     MainExit
3748	3:
3749		 sll   $7,$24,2         	 # Delay slot
3750		 addu  $7,$7,$30
3751		 lw    $7,0x00($7)
3752		 jr    $7
3753		 nop                    	 # Delay slot
3754
3755OP0_11d0:				#:
3756		 addiu $23,$23,2
3757
3758		 and   $8,$24,0x07
3759		 sll   $8,$8,2
3760		 addu  $8,$8,$21
3761		 lw    $14,0x20($8)
3762		 lw    $25,0x7C($21)
3763		 sw    $15,m68k_ICount
3764		 or    $4,$0,$14
3765		 jalr  $25
3766		 sw    $23,0x4C($21)    	 # Delay slot
3767		 lw    $15,m68k_ICount
3768		 and   $16,$0,$0        	 # Clear Carry
3769		 and   $17,$0,$0        	 # Clear Overflow
3770		 srl   $19,$2,7         	 # Set Sign
3771		 sltiu $18,$2,1         	 # Set Zero
3772		 lh    $14,0x00($23)
3773		 addiu $23,$23,2
3774		 lw    $25,0x88($21)
3775		 sw    $15,m68k_ICount
3776		 or    $5,$0,$2
3777		 or    $4,$0,$14
3778		 jalr  $25
3779		 sw    $23,0x4C($21)    	 # Delay slot
3780		 lw    $15,m68k_ICount
3781		 addiu $15,$15,-16
3782		 bgez  $15,3f
3783		 lhu   $24,0x00($23)    	 # Delay slot
3784		 j     MainExit
3785	3:
3786		 sll   $7,$24,2         	 # Delay slot
3787		 addu  $7,$7,$30
3788		 lw    $7,0x00($7)
3789		 jr    $7
3790		 nop                    	 # Delay slot
3791
3792OP0_11d8:				#:
3793		 addiu $23,$23,2
3794
3795		 and   $8,$24,0x07
3796		 sll   $8,$8,2
3797		 addu  $8,$8,$21
3798		 lw    $14,0x20($8)
3799		 addiu $25,$14,1
3800		 sw    $25,0x20($8)
3801		 lw    $25,0x7C($21)
3802		 sw    $15,m68k_ICount
3803		 or    $4,$0,$14
3804		 jalr  $25
3805		 sw    $23,0x4C($21)    	 # Delay slot
3806		 lw    $15,m68k_ICount
3807		 and   $16,$0,$0        	 # Clear Carry
3808		 and   $17,$0,$0        	 # Clear Overflow
3809		 srl   $19,$2,7         	 # Set Sign
3810		 sltiu $18,$2,1         	 # Set Zero
3811		 lh    $14,0x00($23)
3812		 addiu $23,$23,2
3813		 lw    $25,0x88($21)
3814		 sw    $15,m68k_ICount
3815		 or    $5,$0,$2
3816		 or    $4,$0,$14
3817		 jalr  $25
3818		 sw    $23,0x4C($21)    	 # Delay slot
3819		 lw    $15,m68k_ICount
3820		 addiu $15,$15,-16
3821		 bgez  $15,3f
3822		 lhu   $24,0x00($23)    	 # Delay slot
3823		 j     MainExit
3824	3:
3825		 sll   $7,$24,2         	 # Delay slot
3826		 addu  $7,$7,$30
3827		 lw    $7,0x00($7)
3828		 jr    $7
3829		 nop                    	 # Delay slot
3830
3831OP0_11df:				#:
3832		 addiu $23,$23,2
3833
3834		 lw    $14,0x3C($21)    	 # Get A7
3835		 addiu $25,$14,2
3836		 sw    $25,0x3C($21)
3837		 lw    $25,0x7C($21)
3838		 sw    $15,m68k_ICount
3839		 or    $4,$0,$14
3840		 jalr  $25
3841		 sw    $23,0x4C($21)    	 # Delay slot
3842		 lw    $15,m68k_ICount
3843		 and   $16,$0,$0        	 # Clear Carry
3844		 and   $17,$0,$0        	 # Clear Overflow
3845		 srl   $19,$2,7         	 # Set Sign
3846		 sltiu $18,$2,1         	 # Set Zero
3847		 lh    $14,0x00($23)
3848		 addiu $23,$23,2
3849		 lw    $25,0x88($21)
3850		 sw    $15,m68k_ICount
3851		 or    $5,$0,$2
3852		 or    $4,$0,$14
3853		 jalr  $25
3854		 sw    $23,0x4C($21)    	 # Delay slot
3855		 lw    $15,m68k_ICount
3856		 addiu $15,$15,-16
3857		 bgez  $15,3f
3858		 lhu   $24,0x00($23)    	 # Delay slot
3859		 j     MainExit
3860	3:
3861		 sll   $7,$24,2         	 # Delay slot
3862		 addu  $7,$7,$30
3863		 lw    $7,0x00($7)
3864		 jr    $7
3865		 nop                    	 # Delay slot
3866
3867OP0_11e0:				#:
3868		 addiu $23,$23,2
3869
3870		 and   $8,$24,0x07
3871		 sll   $8,$8,2
3872		 addu  $8,$8,$21
3873		 lw    $14,0x20($8)
3874		 addiu $14,$14,-1
3875		 sw    $14,0x20($8)
3876		 lw    $25,0x7C($21)
3877		 sw    $15,m68k_ICount
3878		 or    $4,$0,$14
3879		 jalr  $25
3880		 sw    $23,0x4C($21)    	 # Delay slot
3881		 lw    $15,m68k_ICount
3882		 and   $16,$0,$0        	 # Clear Carry
3883		 and   $17,$0,$0        	 # Clear Overflow
3884		 srl   $19,$2,7         	 # Set Sign
3885		 sltiu $18,$2,1         	 # Set Zero
3886		 lh    $14,0x00($23)
3887		 addiu $23,$23,2
3888		 lw    $25,0x88($21)
3889		 sw    $15,m68k_ICount
3890		 or    $5,$0,$2
3891		 or    $4,$0,$14
3892		 jalr  $25
3893		 sw    $23,0x4C($21)    	 # Delay slot
3894		 lw    $15,m68k_ICount
3895		 addiu $15,$15,-18
3896		 bgez  $15,3f
3897		 lhu   $24,0x00($23)    	 # Delay slot
3898		 j     MainExit
3899	3:
3900		 sll   $7,$24,2         	 # Delay slot
3901		 addu  $7,$7,$30
3902		 lw    $7,0x00($7)
3903		 jr    $7
3904		 nop                    	 # Delay slot
3905
3906OP0_11e7:				#:
3907		 addiu $23,$23,2
3908
3909		 lw    $14,0x3C($21)    	 # Get A7
3910		 addiu $14,$14,-2
3911		 sw    $14,0x3C($21)
3912		 lw    $25,0x7C($21)
3913		 sw    $15,m68k_ICount
3914		 or    $4,$0,$14
3915		 jalr  $25
3916		 sw    $23,0x4C($21)    	 # Delay slot
3917		 lw    $15,m68k_ICount
3918		 and   $16,$0,$0        	 # Clear Carry
3919		 and   $17,$0,$0        	 # Clear Overflow
3920		 srl   $19,$2,7         	 # Set Sign
3921		 sltiu $18,$2,1         	 # Set Zero
3922		 lh    $14,0x00($23)
3923		 addiu $23,$23,2
3924		 lw    $25,0x88($21)
3925		 sw    $15,m68k_ICount
3926		 or    $5,$0,$2
3927		 or    $4,$0,$14
3928		 jalr  $25
3929		 sw    $23,0x4C($21)    	 # Delay slot
3930		 lw    $15,m68k_ICount
3931		 addiu $15,$15,-18
3932		 bgez  $15,3f
3933		 lhu   $24,0x00($23)    	 # Delay slot
3934		 j     MainExit
3935	3:
3936		 sll   $7,$24,2         	 # Delay slot
3937		 addu  $7,$7,$30
3938		 lw    $7,0x00($7)
3939		 jr    $7
3940		 nop                    	 # Delay slot
3941
3942OP0_11e8:				#:
3943		 addiu $23,$23,2
3944
3945		 and   $8,$24,0x07
3946		 lh    $7,0x00($23)
3947		 sll   $8,$8,2
3948		 addu  $8,$8,$21
3949		 lw    $14,0x20($8)
3950		 addiu $23,$23,2
3951		 addu  $14,$14,$7
3952		 lw    $25,0x7C($21)
3953		 sw    $15,m68k_ICount
3954		 or    $4,$0,$14
3955		 jalr  $25
3956		 sw    $23,0x4C($21)    	 # Delay slot
3957		 lw    $15,m68k_ICount
3958		 and   $16,$0,$0        	 # Clear Carry
3959		 and   $17,$0,$0        	 # Clear Overflow
3960		 srl   $19,$2,7         	 # Set Sign
3961		 sltiu $18,$2,1         	 # Set Zero
3962		 lh    $14,0x00($23)
3963		 addiu $23,$23,2
3964		 lw    $25,0x88($21)
3965		 sw    $15,m68k_ICount
3966		 or    $5,$0,$2
3967		 or    $4,$0,$14
3968		 jalr  $25
3969		 sw    $23,0x4C($21)    	 # Delay slot
3970		 lw    $15,m68k_ICount
3971		 addiu $15,$15,-20
3972		 bgez  $15,3f
3973		 lhu   $24,0x00($23)    	 # Delay slot
3974		 j     MainExit
3975	3:
3976		 sll   $7,$24,2         	 # Delay slot
3977		 addu  $7,$7,$30
3978		 lw    $7,0x00($7)
3979		 jr    $7
3980		 nop                    	 # Delay slot
3981
3982OP0_11f0:				#:
3983		 addiu $23,$23,2
3984
3985		 and   $8,$24,0x07
3986		 sll   $8,$8,2
3987		 addu  $8,$8,$21
3988		 lw    $14,0x20($8)
3989		 lhu   $7,0x00($23)
3990		 addiu $23,$23,2
3991		 seb   $6,$7
3992		 or    $25,$0,$7
3993		 srl   $7,$7,12
3994		 andi  $25,$25,0x0800
3995		 sll   $7,$7,2
3996		 addu  $7,$7,$21
3997		 bne   $25,$0,0f
3998		 lw    $25,0x00($7)      	 # Delay slot
3999		 seh   $25,$25
4000	0:
4001		 addu  $25,$14,$25
4002		 addu  $14,$25,$6
4003		 lw    $25,0x7C($21)
4004		 sw    $15,m68k_ICount
4005		 or    $4,$0,$14
4006		 jalr  $25
4007		 sw    $23,0x4C($21)    	 # Delay slot
4008		 lw    $15,m68k_ICount
4009		 and   $16,$0,$0        	 # Clear Carry
4010		 and   $17,$0,$0        	 # Clear Overflow
4011		 srl   $19,$2,7         	 # Set Sign
4012		 sltiu $18,$2,1         	 # Set Zero
4013		 lh    $14,0x00($23)
4014		 addiu $23,$23,2
4015		 lw    $25,0x88($21)
4016		 sw    $15,m68k_ICount
4017		 or    $5,$0,$2
4018		 or    $4,$0,$14
4019		 jalr  $25
4020		 sw    $23,0x4C($21)    	 # Delay slot
4021		 lw    $15,m68k_ICount
4022		 addiu $15,$15,-22
4023		 bgez  $15,3f
4024		 lhu   $24,0x00($23)    	 # Delay slot
4025		 j     MainExit
4026	3:
4027		 sll   $7,$24,2         	 # Delay slot
4028		 addu  $7,$7,$30
4029		 lw    $7,0x00($7)
4030		 jr    $7
4031		 nop                    	 # Delay slot
4032
4033OP0_11f8:				#:
4034		 addiu $23,$23,2
4035
4036		 lh    $14,0x00($23)
4037		 addiu $23,$23,2
4038		 lw    $25,0x7C($21)
4039		 sw    $15,m68k_ICount
4040		 or    $4,$0,$14
4041		 jalr  $25
4042		 sw    $23,0x4C($21)    	 # Delay slot
4043		 lw    $15,m68k_ICount
4044		 and   $16,$0,$0        	 # Clear Carry
4045		 and   $17,$0,$0        	 # Clear Overflow
4046		 srl   $19,$2,7         	 # Set Sign
4047		 sltiu $18,$2,1         	 # Set Zero
4048		 lh    $14,0x00($23)
4049		 addiu $23,$23,2
4050		 lw    $25,0x88($21)
4051		 sw    $15,m68k_ICount
4052		 or    $5,$0,$2
4053		 or    $4,$0,$14
4054		 jalr  $25
4055		 sw    $23,0x4C($21)    	 # Delay slot
4056		 lw    $15,m68k_ICount
4057		 addiu $15,$15,-20
4058		 bgez  $15,3f
4059		 lhu   $24,0x00($23)    	 # Delay slot
4060		 j     MainExit
4061	3:
4062		 sll   $7,$24,2         	 # Delay slot
4063		 addu  $7,$7,$30
4064		 lw    $7,0x00($7)
4065		 jr    $7
4066		 nop                    	 # Delay slot
4067
4068OP0_11f9:				#:
4069		 addiu $23,$23,2
4070
4071		 lhu   $14,0x00($23)
4072		 lhu   $25,0x02($23)
4073		 sll   $14,$14,16
4074		 or    $14,$14,$25
4075		 addiu $23,$23,4
4076		 lw    $25,0x7C($21)
4077		 sw    $15,m68k_ICount
4078		 or    $4,$0,$14
4079		 jalr  $25
4080		 sw    $23,0x4C($21)    	 # Delay slot
4081		 lw    $15,m68k_ICount
4082		 and   $16,$0,$0        	 # Clear Carry
4083		 and   $17,$0,$0        	 # Clear Overflow
4084		 srl   $19,$2,7         	 # Set Sign
4085		 sltiu $18,$2,1         	 # Set Zero
4086		 lh    $14,0x00($23)
4087		 addiu $23,$23,2
4088		 lw    $25,0x88($21)
4089		 sw    $15,m68k_ICount
4090		 or    $5,$0,$2
4091		 or    $4,$0,$14
4092		 jalr  $25
4093		 sw    $23,0x4C($21)    	 # Delay slot
4094		 lw    $15,m68k_ICount
4095		 addiu $15,$15,-24
4096		 bgez  $15,3f
4097		 lhu   $24,0x00($23)    	 # Delay slot
4098		 j     MainExit
4099	3:
4100		 sll   $7,$24,2         	 # Delay slot
4101		 addu  $7,$7,$30
4102		 lw    $7,0x00($7)
4103		 jr    $7
4104		 nop                    	 # Delay slot
4105
4106OP0_11fa:				#:
4107		 addiu $23,$23,2
4108
4109		 lh    $7,0x00($23)
4110		 subu  $25,$23,$22
4111		 addu  $14,$25,$7       	 # Add Offset to PC
4112		 addiu $23,$23,2
4113		 lw    $25,0x98($21)
4114		 sw    $15,m68k_ICount
4115		 or    $4,$0,$14
4116		 jalr  $25
4117		 sw    $23,0x4C($21)    	 # Delay slot
4118		 lw    $15,m68k_ICount
4119		 and   $16,$0,$0        	 # Clear Carry
4120		 and   $17,$0,$0        	 # Clear Overflow
4121		 srl   $19,$2,7         	 # Set Sign
4122		 sltiu $18,$2,1         	 # Set Zero
4123		 lh    $14,0x00($23)
4124		 addiu $23,$23,2
4125		 lw    $25,0x88($21)
4126		 sw    $15,m68k_ICount
4127		 or    $5,$0,$2
4128		 or    $4,$0,$14
4129		 jalr  $25
4130		 sw    $23,0x4C($21)    	 # Delay slot
4131		 lw    $15,m68k_ICount
4132		 addiu $15,$15,-20
4133		 bgez  $15,3f
4134		 lhu   $24,0x00($23)    	 # Delay slot
4135		 j     MainExit
4136	3:
4137		 sll   $7,$24,2         	 # Delay slot
4138		 addu  $7,$7,$30
4139		 lw    $7,0x00($7)
4140		 jr    $7
4141		 nop                    	 # Delay slot
4142
4143OP0_11fb:				#:
4144		 addiu $23,$23,2
4145
4146		 subu  $14,$23,$22       	 # Get PC
4147		 lhu   $7,0x00($23)
4148		 addiu $23,$23,2
4149		 seb   $6,$7
4150		 or    $25,$0,$7
4151		 srl   $7,$7,12
4152		 andi  $25,$25,0x0800
4153		 sll   $7,$7,2
4154		 addu  $7,$7,$21
4155		 bne   $25,$0,0f
4156		 lw    $25,0x00($7)      	 # Delay slot
4157		 seh   $25,$25
4158	0:
4159		 addu  $25,$14,$25
4160		 addu  $14,$25,$6
4161		 lw    $25,0x98($21)
4162		 sw    $15,m68k_ICount
4163		 or    $4,$0,$14
4164		 jalr  $25
4165		 sw    $23,0x4C($21)    	 # Delay slot
4166		 lw    $15,m68k_ICount
4167		 and   $16,$0,$0        	 # Clear Carry
4168		 and   $17,$0,$0        	 # Clear Overflow
4169		 srl   $19,$2,7         	 # Set Sign
4170		 sltiu $18,$2,1         	 # Set Zero
4171		 lh    $14,0x00($23)
4172		 addiu $23,$23,2
4173		 lw    $25,0x88($21)
4174		 sw    $15,m68k_ICount
4175		 or    $5,$0,$2
4176		 or    $4,$0,$14
4177		 jalr  $25
4178		 sw    $23,0x4C($21)    	 # Delay slot
4179		 lw    $15,m68k_ICount
4180		 addiu $15,$15,-22
4181		 bgez  $15,3f
4182		 lhu   $24,0x00($23)    	 # Delay slot
4183		 j     MainExit
4184	3:
4185		 sll   $7,$24,2         	 # Delay slot
4186		 addu  $7,$7,$30
4187		 lw    $7,0x00($7)
4188		 jr    $7
4189		 nop                    	 # Delay slot
4190
4191OP0_11fc:				#:
4192		 addiu $23,$23,2
4193
4194		 lbu   $2,0x00($23)
4195		 addiu $23,$23,2
4196		 and   $16,$0,$0        	 # Clear Carry
4197		 and   $17,$0,$0        	 # Clear Overflow
4198		 srl   $19,$2,7         	 # Set Sign
4199		 sltiu $18,$2,1         	 # Set Zero
4200		 lh    $14,0x00($23)
4201		 addiu $23,$23,2
4202		 lw    $25,0x88($21)
4203		 sw    $15,m68k_ICount
4204		 or    $5,$0,$2
4205		 or    $4,$0,$14
4206		 jalr  $25
4207		 sw    $23,0x4C($21)    	 # Delay slot
4208		 lw    $15,m68k_ICount
4209		 addiu $15,$15,-12
4210		 bgez  $15,3f
4211		 lhu   $24,0x00($23)    	 # Delay slot
4212		 j     MainExit
4213	3:
4214		 sll   $7,$24,2         	 # Delay slot
4215		 addu  $7,$7,$30
4216		 lw    $7,0x00($7)
4217		 jr    $7
4218		 nop                    	 # Delay slot
4219
4220OP0_13c0:				#:
4221		 addiu $23,$23,2
4222
4223		 and   $8,$24,0x0f
4224		 sll   $8,$8,2
4225		 addu  $8,$8,$21
4226		 lbu   $2,0x00($8)
4227		 and   $16,$0,$0        	 # Clear Carry
4228		 and   $17,$0,$0        	 # Clear Overflow
4229		 srl   $19,$2,7         	 # Set Sign
4230		 sltiu $18,$2,1         	 # Set Zero
4231		 lhu   $14,0x00($23)
4232		 lhu   $25,0x02($23)
4233		 sll   $14,$14,16
4234		 or    $14,$14,$25
4235		 addiu $23,$23,4
4236		 lw    $25,0x88($21)
4237		 sw    $15,m68k_ICount
4238		 or    $5,$0,$2
4239		 or    $4,$0,$14
4240		 jalr  $25
4241		 sw    $23,0x4C($21)    	 # Delay slot
4242		 lw    $15,m68k_ICount
4243		 addiu $15,$15,-16
4244		 bgez  $15,3f
4245		 lhu   $24,0x00($23)    	 # Delay slot
4246		 j     MainExit
4247	3:
4248		 sll   $7,$24,2         	 # Delay slot
4249		 addu  $7,$7,$30
4250		 lw    $7,0x00($7)
4251		 jr    $7
4252		 nop                    	 # Delay slot
4253
4254OP0_13d0:				#:
4255		 addiu $23,$23,2
4256
4257		 and   $8,$24,0x07
4258		 sll   $8,$8,2
4259		 addu  $8,$8,$21
4260		 lw    $14,0x20($8)
4261		 lw    $25,0x7C($21)
4262		 sw    $15,m68k_ICount
4263		 or    $4,$0,$14
4264		 jalr  $25
4265		 sw    $23,0x4C($21)    	 # Delay slot
4266		 lw    $15,m68k_ICount
4267		 and   $16,$0,$0        	 # Clear Carry
4268		 and   $17,$0,$0        	 # Clear Overflow
4269		 srl   $19,$2,7         	 # Set Sign
4270		 sltiu $18,$2,1         	 # Set Zero
4271		 lhu   $14,0x00($23)
4272		 lhu   $25,0x02($23)
4273		 sll   $14,$14,16
4274		 or    $14,$14,$25
4275		 addiu $23,$23,4
4276		 lw    $25,0x88($21)
4277		 sw    $15,m68k_ICount
4278		 or    $5,$0,$2
4279		 or    $4,$0,$14
4280		 jalr  $25
4281		 sw    $23,0x4C($21)    	 # Delay slot
4282		 lw    $15,m68k_ICount
4283		 addiu $15,$15,-20
4284		 bgez  $15,3f
4285		 lhu   $24,0x00($23)    	 # Delay slot
4286		 j     MainExit
4287	3:
4288		 sll   $7,$24,2         	 # Delay slot
4289		 addu  $7,$7,$30
4290		 lw    $7,0x00($7)
4291		 jr    $7
4292		 nop                    	 # Delay slot
4293
4294OP0_13d8:				#:
4295		 addiu $23,$23,2
4296
4297		 and   $8,$24,0x07
4298		 sll   $8,$8,2
4299		 addu  $8,$8,$21
4300		 lw    $14,0x20($8)
4301		 addiu $25,$14,1
4302		 sw    $25,0x20($8)
4303		 lw    $25,0x7C($21)
4304		 sw    $15,m68k_ICount
4305		 or    $4,$0,$14
4306		 jalr  $25
4307		 sw    $23,0x4C($21)    	 # Delay slot
4308		 lw    $15,m68k_ICount
4309		 and   $16,$0,$0        	 # Clear Carry
4310		 and   $17,$0,$0        	 # Clear Overflow
4311		 srl   $19,$2,7         	 # Set Sign
4312		 sltiu $18,$2,1         	 # Set Zero
4313		 lhu   $14,0x00($23)
4314		 lhu   $25,0x02($23)
4315		 sll   $14,$14,16
4316		 or    $14,$14,$25
4317		 addiu $23,$23,4
4318		 lw    $25,0x88($21)
4319		 sw    $15,m68k_ICount
4320		 or    $5,$0,$2
4321		 or    $4,$0,$14
4322		 jalr  $25
4323		 sw    $23,0x4C($21)    	 # Delay slot
4324		 lw    $15,m68k_ICount
4325		 addiu $15,$15,-20
4326		 bgez  $15,3f
4327		 lhu   $24,0x00($23)    	 # Delay slot
4328		 j     MainExit
4329	3:
4330		 sll   $7,$24,2         	 # Delay slot
4331		 addu  $7,$7,$30
4332		 lw    $7,0x00($7)
4333		 jr    $7
4334		 nop                    	 # Delay slot
4335
4336OP0_13df:				#:
4337		 addiu $23,$23,2
4338
4339		 lw    $14,0x3C($21)    	 # Get A7
4340		 addiu $25,$14,2
4341		 sw    $25,0x3C($21)
4342		 lw    $25,0x7C($21)
4343		 sw    $15,m68k_ICount
4344		 or    $4,$0,$14
4345		 jalr  $25
4346		 sw    $23,0x4C($21)    	 # Delay slot
4347		 lw    $15,m68k_ICount
4348		 and   $16,$0,$0        	 # Clear Carry
4349		 and   $17,$0,$0        	 # Clear Overflow
4350		 srl   $19,$2,7         	 # Set Sign
4351		 sltiu $18,$2,1         	 # Set Zero
4352		 lhu   $14,0x00($23)
4353		 lhu   $25,0x02($23)
4354		 sll   $14,$14,16
4355		 or    $14,$14,$25
4356		 addiu $23,$23,4
4357		 lw    $25,0x88($21)
4358		 sw    $15,m68k_ICount
4359		 or    $5,$0,$2
4360		 or    $4,$0,$14
4361		 jalr  $25
4362		 sw    $23,0x4C($21)    	 # Delay slot
4363		 lw    $15,m68k_ICount
4364		 addiu $15,$15,-20
4365		 bgez  $15,3f
4366		 lhu   $24,0x00($23)    	 # Delay slot
4367		 j     MainExit
4368	3:
4369		 sll   $7,$24,2         	 # Delay slot
4370		 addu  $7,$7,$30
4371		 lw    $7,0x00($7)
4372		 jr    $7
4373		 nop                    	 # Delay slot
4374
4375OP0_13e0:				#:
4376		 addiu $23,$23,2
4377
4378		 and   $8,$24,0x07
4379		 sll   $8,$8,2
4380		 addu  $8,$8,$21
4381		 lw    $14,0x20($8)
4382		 addiu $14,$14,-1
4383		 sw    $14,0x20($8)
4384		 lw    $25,0x7C($21)
4385		 sw    $15,m68k_ICount
4386		 or    $4,$0,$14
4387		 jalr  $25
4388		 sw    $23,0x4C($21)    	 # Delay slot
4389		 lw    $15,m68k_ICount
4390		 and   $16,$0,$0        	 # Clear Carry
4391		 and   $17,$0,$0        	 # Clear Overflow
4392		 srl   $19,$2,7         	 # Set Sign
4393		 sltiu $18,$2,1         	 # Set Zero
4394		 lhu   $14,0x00($23)
4395		 lhu   $25,0x02($23)
4396		 sll   $14,$14,16
4397		 or    $14,$14,$25
4398		 addiu $23,$23,4
4399		 lw    $25,0x88($21)
4400		 sw    $15,m68k_ICount
4401		 or    $5,$0,$2
4402		 or    $4,$0,$14
4403		 jalr  $25
4404		 sw    $23,0x4C($21)    	 # Delay slot
4405		 lw    $15,m68k_ICount
4406		 addiu $15,$15,-22
4407		 bgez  $15,3f
4408		 lhu   $24,0x00($23)    	 # Delay slot
4409		 j     MainExit
4410	3:
4411		 sll   $7,$24,2         	 # Delay slot
4412		 addu  $7,$7,$30
4413		 lw    $7,0x00($7)
4414		 jr    $7
4415		 nop                    	 # Delay slot
4416
4417OP0_13e7:				#:
4418		 addiu $23,$23,2
4419
4420		 lw    $14,0x3C($21)    	 # Get A7
4421		 addiu $14,$14,-2
4422		 sw    $14,0x3C($21)
4423		 lw    $25,0x7C($21)
4424		 sw    $15,m68k_ICount
4425		 or    $4,$0,$14
4426		 jalr  $25
4427		 sw    $23,0x4C($21)    	 # Delay slot
4428		 lw    $15,m68k_ICount
4429		 and   $16,$0,$0        	 # Clear Carry
4430		 and   $17,$0,$0        	 # Clear Overflow
4431		 srl   $19,$2,7         	 # Set Sign
4432		 sltiu $18,$2,1         	 # Set Zero
4433		 lhu   $14,0x00($23)
4434		 lhu   $25,0x02($23)
4435		 sll   $14,$14,16
4436		 or    $14,$14,$25
4437		 addiu $23,$23,4
4438		 lw    $25,0x88($21)
4439		 sw    $15,m68k_ICount
4440		 or    $5,$0,$2
4441		 or    $4,$0,$14
4442		 jalr  $25
4443		 sw    $23,0x4C($21)    	 # Delay slot
4444		 lw    $15,m68k_ICount
4445		 addiu $15,$15,-22
4446		 bgez  $15,3f
4447		 lhu   $24,0x00($23)    	 # Delay slot
4448		 j     MainExit
4449	3:
4450		 sll   $7,$24,2         	 # Delay slot
4451		 addu  $7,$7,$30
4452		 lw    $7,0x00($7)
4453		 jr    $7
4454		 nop                    	 # Delay slot
4455
4456OP0_13e8:				#:
4457		 addiu $23,$23,2
4458
4459		 and   $8,$24,0x07
4460		 lh    $7,0x00($23)
4461		 sll   $8,$8,2
4462		 addu  $8,$8,$21
4463		 lw    $14,0x20($8)
4464		 addiu $23,$23,2
4465		 addu  $14,$14,$7
4466		 lw    $25,0x7C($21)
4467		 sw    $15,m68k_ICount
4468		 or    $4,$0,$14
4469		 jalr  $25
4470		 sw    $23,0x4C($21)    	 # Delay slot
4471		 lw    $15,m68k_ICount
4472		 and   $16,$0,$0        	 # Clear Carry
4473		 and   $17,$0,$0        	 # Clear Overflow
4474		 srl   $19,$2,7         	 # Set Sign
4475		 sltiu $18,$2,1         	 # Set Zero
4476		 lhu   $14,0x00($23)
4477		 lhu   $25,0x02($23)
4478		 sll   $14,$14,16
4479		 or    $14,$14,$25
4480		 addiu $23,$23,4
4481		 lw    $25,0x88($21)
4482		 sw    $15,m68k_ICount
4483		 or    $5,$0,$2
4484		 or    $4,$0,$14
4485		 jalr  $25
4486		 sw    $23,0x4C($21)    	 # Delay slot
4487		 lw    $15,m68k_ICount
4488		 addiu $15,$15,-24
4489		 bgez  $15,3f
4490		 lhu   $24,0x00($23)    	 # Delay slot
4491		 j     MainExit
4492	3:
4493		 sll   $7,$24,2         	 # Delay slot
4494		 addu  $7,$7,$30
4495		 lw    $7,0x00($7)
4496		 jr    $7
4497		 nop                    	 # Delay slot
4498
4499OP0_13f0:				#:
4500		 addiu $23,$23,2
4501
4502		 and   $8,$24,0x07
4503		 sll   $8,$8,2
4504		 addu  $8,$8,$21
4505		 lw    $14,0x20($8)
4506		 lhu   $7,0x00($23)
4507		 addiu $23,$23,2
4508		 seb   $6,$7
4509		 or    $25,$0,$7
4510		 srl   $7,$7,12
4511		 andi  $25,$25,0x0800
4512		 sll   $7,$7,2
4513		 addu  $7,$7,$21
4514		 bne   $25,$0,0f
4515		 lw    $25,0x00($7)      	 # Delay slot
4516		 seh   $25,$25
4517	0:
4518		 addu  $25,$14,$25
4519		 addu  $14,$25,$6
4520		 lw    $25,0x7C($21)
4521		 sw    $15,m68k_ICount
4522		 or    $4,$0,$14
4523		 jalr  $25
4524		 sw    $23,0x4C($21)    	 # Delay slot
4525		 lw    $15,m68k_ICount
4526		 and   $16,$0,$0        	 # Clear Carry
4527		 and   $17,$0,$0        	 # Clear Overflow
4528		 srl   $19,$2,7         	 # Set Sign
4529		 sltiu $18,$2,1         	 # Set Zero
4530		 lhu   $14,0x00($23)
4531		 lhu   $25,0x02($23)
4532		 sll   $14,$14,16
4533		 or    $14,$14,$25
4534		 addiu $23,$23,4
4535		 lw    $25,0x88($21)
4536		 sw    $15,m68k_ICount
4537		 or    $5,$0,$2
4538		 or    $4,$0,$14
4539		 jalr  $25
4540		 sw    $23,0x4C($21)    	 # Delay slot
4541		 lw    $15,m68k_ICount
4542		 addiu $15,$15,-26
4543		 bgez  $15,3f
4544		 lhu   $24,0x00($23)    	 # Delay slot
4545		 j     MainExit
4546	3:
4547		 sll   $7,$24,2         	 # Delay slot
4548		 addu  $7,$7,$30
4549		 lw    $7,0x00($7)
4550		 jr    $7
4551		 nop                    	 # Delay slot
4552
4553OP0_13f8:				#:
4554		 addiu $23,$23,2
4555
4556		 lh    $14,0x00($23)
4557		 addiu $23,$23,2
4558		 lw    $25,0x7C($21)
4559		 sw    $15,m68k_ICount
4560		 or    $4,$0,$14
4561		 jalr  $25
4562		 sw    $23,0x4C($21)    	 # Delay slot
4563		 lw    $15,m68k_ICount
4564		 and   $16,$0,$0        	 # Clear Carry
4565		 and   $17,$0,$0        	 # Clear Overflow
4566		 srl   $19,$2,7         	 # Set Sign
4567		 sltiu $18,$2,1         	 # Set Zero
4568		 lhu   $14,0x00($23)
4569		 lhu   $25,0x02($23)
4570		 sll   $14,$14,16
4571		 or    $14,$14,$25
4572		 addiu $23,$23,4
4573		 lw    $25,0x88($21)
4574		 sw    $15,m68k_ICount
4575		 or    $5,$0,$2
4576		 or    $4,$0,$14
4577		 jalr  $25
4578		 sw    $23,0x4C($21)    	 # Delay slot
4579		 lw    $15,m68k_ICount
4580		 addiu $15,$15,-24
4581		 bgez  $15,3f
4582		 lhu   $24,0x00($23)    	 # Delay slot
4583		 j     MainExit
4584	3:
4585		 sll   $7,$24,2         	 # Delay slot
4586		 addu  $7,$7,$30
4587		 lw    $7,0x00($7)
4588		 jr    $7
4589		 nop                    	 # Delay slot
4590
4591OP0_13f9:				#:
4592		 addiu $23,$23,2
4593
4594		 lhu   $14,0x00($23)
4595		 lhu   $25,0x02($23)
4596		 sll   $14,$14,16
4597		 or    $14,$14,$25
4598		 addiu $23,$23,4
4599		 lw    $25,0x7C($21)
4600		 sw    $15,m68k_ICount
4601		 or    $4,$0,$14
4602		 jalr  $25
4603		 sw    $23,0x4C($21)    	 # Delay slot
4604		 lw    $15,m68k_ICount
4605		 and   $16,$0,$0        	 # Clear Carry
4606		 and   $17,$0,$0        	 # Clear Overflow
4607		 srl   $19,$2,7         	 # Set Sign
4608		 sltiu $18,$2,1         	 # Set Zero
4609		 lhu   $14,0x00($23)
4610		 lhu   $25,0x02($23)
4611		 sll   $14,$14,16
4612		 or    $14,$14,$25
4613		 addiu $23,$23,4
4614		 lw    $25,0x88($21)
4615		 sw    $15,m68k_ICount
4616		 or    $5,$0,$2
4617		 or    $4,$0,$14
4618		 jalr  $25
4619		 sw    $23,0x4C($21)    	 # Delay slot
4620		 lw    $15,m68k_ICount
4621		 addiu $15,$15,-28
4622		 bgez  $15,3f
4623		 lhu   $24,0x00($23)    	 # Delay slot
4624		 j     MainExit
4625	3:
4626		 sll   $7,$24,2         	 # Delay slot
4627		 addu  $7,$7,$30
4628		 lw    $7,0x00($7)
4629		 jr    $7
4630		 nop                    	 # Delay slot
4631
4632OP0_13fa:				#:
4633		 addiu $23,$23,2
4634
4635		 lh    $7,0x00($23)
4636		 subu  $25,$23,$22
4637		 addu  $14,$25,$7       	 # Add Offset to PC
4638		 addiu $23,$23,2
4639		 lw    $25,0x98($21)
4640		 sw    $15,m68k_ICount
4641		 or    $4,$0,$14
4642		 jalr  $25
4643		 sw    $23,0x4C($21)    	 # Delay slot
4644		 lw    $15,m68k_ICount
4645		 and   $16,$0,$0        	 # Clear Carry
4646		 and   $17,$0,$0        	 # Clear Overflow
4647		 srl   $19,$2,7         	 # Set Sign
4648		 sltiu $18,$2,1         	 # Set Zero
4649		 lhu   $14,0x00($23)
4650		 lhu   $25,0x02($23)
4651		 sll   $14,$14,16
4652		 or    $14,$14,$25
4653		 addiu $23,$23,4
4654		 lw    $25,0x88($21)
4655		 sw    $15,m68k_ICount
4656		 or    $5,$0,$2
4657		 or    $4,$0,$14
4658		 jalr  $25
4659		 sw    $23,0x4C($21)    	 # Delay slot
4660		 lw    $15,m68k_ICount
4661		 addiu $15,$15,-24
4662		 bgez  $15,3f
4663		 lhu   $24,0x00($23)    	 # Delay slot
4664		 j     MainExit
4665	3:
4666		 sll   $7,$24,2         	 # Delay slot
4667		 addu  $7,$7,$30
4668		 lw    $7,0x00($7)
4669		 jr    $7
4670		 nop                    	 # Delay slot
4671
4672OP0_13fb:				#:
4673		 addiu $23,$23,2
4674
4675		 subu  $14,$23,$22       	 # Get PC
4676		 lhu   $7,0x00($23)
4677		 addiu $23,$23,2
4678		 seb   $6,$7
4679		 or    $25,$0,$7
4680		 srl   $7,$7,12
4681		 andi  $25,$25,0x0800
4682		 sll   $7,$7,2
4683		 addu  $7,$7,$21
4684		 bne   $25,$0,0f
4685		 lw    $25,0x00($7)      	 # Delay slot
4686		 seh   $25,$25
4687	0:
4688		 addu  $25,$14,$25
4689		 addu  $14,$25,$6
4690		 lw    $25,0x98($21)
4691		 sw    $15,m68k_ICount
4692		 or    $4,$0,$14
4693		 jalr  $25
4694		 sw    $23,0x4C($21)    	 # Delay slot
4695		 lw    $15,m68k_ICount
4696		 and   $16,$0,$0        	 # Clear Carry
4697		 and   $17,$0,$0        	 # Clear Overflow
4698		 srl   $19,$2,7         	 # Set Sign
4699		 sltiu $18,$2,1         	 # Set Zero
4700		 lhu   $14,0x00($23)
4701		 lhu   $25,0x02($23)
4702		 sll   $14,$14,16
4703		 or    $14,$14,$25
4704		 addiu $23,$23,4
4705		 lw    $25,0x88($21)
4706		 sw    $15,m68k_ICount
4707		 or    $5,$0,$2
4708		 or    $4,$0,$14
4709		 jalr  $25
4710		 sw    $23,0x4C($21)    	 # Delay slot
4711		 lw    $15,m68k_ICount
4712		 addiu $15,$15,-26
4713		 bgez  $15,3f
4714		 lhu   $24,0x00($23)    	 # Delay slot
4715		 j     MainExit
4716	3:
4717		 sll   $7,$24,2         	 # Delay slot
4718		 addu  $7,$7,$30
4719		 lw    $7,0x00($7)
4720		 jr    $7
4721		 nop                    	 # Delay slot
4722
4723OP0_13fc:				#:
4724		 addiu $23,$23,2
4725
4726		 lbu   $2,0x00($23)
4727		 addiu $23,$23,2
4728		 and   $16,$0,$0        	 # Clear Carry
4729		 and   $17,$0,$0        	 # Clear Overflow
4730		 srl   $19,$2,7         	 # Set Sign
4731		 sltiu $18,$2,1         	 # Set Zero
4732		 lhu   $14,0x00($23)
4733		 lhu   $25,0x02($23)
4734		 sll   $14,$14,16
4735		 or    $14,$14,$25
4736		 addiu $23,$23,4
4737		 lw    $25,0x88($21)
4738		 sw    $15,m68k_ICount
4739		 or    $5,$0,$2
4740		 or    $4,$0,$14
4741		 jalr  $25
4742		 sw    $23,0x4C($21)    	 # Delay slot
4743		 lw    $15,m68k_ICount
4744		 addiu $15,$15,-16
4745		 bgez  $15,3f
4746		 lhu   $24,0x00($23)    	 # Delay slot
4747		 j     MainExit
4748	3:
4749		 sll   $7,$24,2         	 # Delay slot
4750		 addu  $7,$7,$30
4751		 lw    $7,0x00($7)
4752		 jr    $7
4753		 nop                    	 # Delay slot
4754
4755OP0_1ec0:				#:
4756		 addiu $23,$23,2
4757
4758		 and   $8,$24,0x0f
4759		 sll   $8,$8,2
4760		 addu  $8,$8,$21
4761		 lbu   $2,0x00($8)
4762		 and   $16,$0,$0        	 # Clear Carry
4763		 and   $17,$0,$0        	 # Clear Overflow
4764		 srl   $19,$2,7         	 # Set Sign
4765		 sltiu $18,$2,1         	 # Set Zero
4766		 lw    $14,0x3C($21)    	 # Get A7
4767		 addiu $25,$14,2
4768		 sw    $25,0x3C($21)
4769		 lw    $25,0x88($21)
4770		 sw    $15,m68k_ICount
4771		 or    $5,$0,$2
4772		 or    $4,$0,$14
4773		 jalr  $25
4774		 sw    $23,0x4C($21)    	 # Delay slot
4775		 lw    $15,m68k_ICount
4776		 addiu $15,$15,-8
4777		 bgez  $15,3f
4778		 lhu   $24,0x00($23)    	 # Delay slot
4779		 j     MainExit
4780	3:
4781		 sll   $7,$24,2         	 # Delay slot
4782		 addu  $7,$7,$30
4783		 lw    $7,0x00($7)
4784		 jr    $7
4785		 nop                    	 # Delay slot
4786
4787OP0_1ed0:				#:
4788		 addiu $23,$23,2
4789
4790		 and   $8,$24,0x07
4791		 sll   $8,$8,2
4792		 addu  $8,$8,$21
4793		 lw    $14,0x20($8)
4794		 lw    $25,0x7C($21)
4795		 sw    $15,m68k_ICount
4796		 or    $4,$0,$14
4797		 jalr  $25
4798		 sw    $23,0x4C($21)    	 # Delay slot
4799		 lw    $15,m68k_ICount
4800		 and   $16,$0,$0        	 # Clear Carry
4801		 and   $17,$0,$0        	 # Clear Overflow
4802		 srl   $19,$2,7         	 # Set Sign
4803		 sltiu $18,$2,1         	 # Set Zero
4804		 lw    $14,0x3C($21)    	 # Get A7
4805		 addiu $25,$14,2
4806		 sw    $25,0x3C($21)
4807		 lw    $25,0x88($21)
4808		 sw    $15,m68k_ICount
4809		 or    $5,$0,$2
4810		 or    $4,$0,$14
4811		 jalr  $25
4812		 sw    $23,0x4C($21)    	 # Delay slot
4813		 lw    $15,m68k_ICount
4814		 addiu $15,$15,-12
4815		 bgez  $15,3f
4816		 lhu   $24,0x00($23)    	 # Delay slot
4817		 j     MainExit
4818	3:
4819		 sll   $7,$24,2         	 # Delay slot
4820		 addu  $7,$7,$30
4821		 lw    $7,0x00($7)
4822		 jr    $7
4823		 nop                    	 # Delay slot
4824
4825OP0_1ed8:				#:
4826		 addiu $23,$23,2
4827
4828		 and   $8,$24,0x07
4829		 sll   $8,$8,2
4830		 addu  $8,$8,$21
4831		 lw    $14,0x20($8)
4832		 addiu $25,$14,1
4833		 sw    $25,0x20($8)
4834		 lw    $25,0x7C($21)
4835		 sw    $15,m68k_ICount
4836		 or    $4,$0,$14
4837		 jalr  $25
4838		 sw    $23,0x4C($21)    	 # Delay slot
4839		 lw    $15,m68k_ICount
4840		 and   $16,$0,$0        	 # Clear Carry
4841		 and   $17,$0,$0        	 # Clear Overflow
4842		 srl   $19,$2,7         	 # Set Sign
4843		 sltiu $18,$2,1         	 # Set Zero
4844		 lw    $14,0x3C($21)    	 # Get A7
4845		 addiu $25,$14,2
4846		 sw    $25,0x3C($21)
4847		 lw    $25,0x88($21)
4848		 sw    $15,m68k_ICount
4849		 or    $5,$0,$2
4850		 or    $4,$0,$14
4851		 jalr  $25
4852		 sw    $23,0x4C($21)    	 # Delay slot
4853		 lw    $15,m68k_ICount
4854		 addiu $15,$15,-12
4855		 bgez  $15,3f
4856		 lhu   $24,0x00($23)    	 # Delay slot
4857		 j     MainExit
4858	3:
4859		 sll   $7,$24,2         	 # Delay slot
4860		 addu  $7,$7,$30
4861		 lw    $7,0x00($7)
4862		 jr    $7
4863		 nop                    	 # Delay slot
4864
4865OP0_1edf:				#:
4866		 addiu $23,$23,2
4867
4868		 lw    $14,0x3C($21)    	 # Get A7
4869		 addiu $25,$14,2
4870		 sw    $25,0x3C($21)
4871		 lw    $25,0x7C($21)
4872		 sw    $15,m68k_ICount
4873		 or    $4,$0,$14
4874		 jalr  $25
4875		 sw    $23,0x4C($21)    	 # Delay slot
4876		 lw    $15,m68k_ICount
4877		 and   $16,$0,$0        	 # Clear Carry
4878		 and   $17,$0,$0        	 # Clear Overflow
4879		 srl   $19,$2,7         	 # Set Sign
4880		 sltiu $18,$2,1         	 # Set Zero
4881		 lw    $14,0x3C($21)    	 # Get A7
4882		 addiu $25,$14,2
4883		 sw    $25,0x3C($21)
4884		 lw    $25,0x88($21)
4885		 sw    $15,m68k_ICount
4886		 or    $5,$0,$2
4887		 or    $4,$0,$14
4888		 jalr  $25
4889		 sw    $23,0x4C($21)    	 # Delay slot
4890		 lw    $15,m68k_ICount
4891		 addiu $15,$15,-12
4892		 bgez  $15,3f
4893		 lhu   $24,0x00($23)    	 # Delay slot
4894		 j     MainExit
4895	3:
4896		 sll   $7,$24,2         	 # Delay slot
4897		 addu  $7,$7,$30
4898		 lw    $7,0x00($7)
4899		 jr    $7
4900		 nop                    	 # Delay slot
4901
4902OP0_1ee0:				#:
4903		 addiu $23,$23,2
4904
4905		 and   $8,$24,0x07
4906		 sll   $8,$8,2
4907		 addu  $8,$8,$21
4908		 lw    $14,0x20($8)
4909		 addiu $14,$14,-1
4910		 sw    $14,0x20($8)
4911		 lw    $25,0x7C($21)
4912		 sw    $15,m68k_ICount
4913		 or    $4,$0,$14
4914		 jalr  $25
4915		 sw    $23,0x4C($21)    	 # Delay slot
4916		 lw    $15,m68k_ICount
4917		 and   $16,$0,$0        	 # Clear Carry
4918		 and   $17,$0,$0        	 # Clear Overflow
4919		 srl   $19,$2,7         	 # Set Sign
4920		 sltiu $18,$2,1         	 # Set Zero
4921		 lw    $14,0x3C($21)    	 # Get A7
4922		 addiu $25,$14,2
4923		 sw    $25,0x3C($21)
4924		 lw    $25,0x88($21)
4925		 sw    $15,m68k_ICount
4926		 or    $5,$0,$2
4927		 or    $4,$0,$14
4928		 jalr  $25
4929		 sw    $23,0x4C($21)    	 # Delay slot
4930		 lw    $15,m68k_ICount
4931		 addiu $15,$15,-14
4932		 bgez  $15,3f
4933		 lhu   $24,0x00($23)    	 # Delay slot
4934		 j     MainExit
4935	3:
4936		 sll   $7,$24,2         	 # Delay slot
4937		 addu  $7,$7,$30
4938		 lw    $7,0x00($7)
4939		 jr    $7
4940		 nop                    	 # Delay slot
4941
4942OP0_1ee7:				#:
4943		 addiu $23,$23,2
4944
4945		 lw    $14,0x3C($21)    	 # Get A7
4946		 addiu $14,$14,-2
4947		 sw    $14,0x3C($21)
4948		 lw    $25,0x7C($21)
4949		 sw    $15,m68k_ICount
4950		 or    $4,$0,$14
4951		 jalr  $25
4952		 sw    $23,0x4C($21)    	 # Delay slot
4953		 lw    $15,m68k_ICount
4954		 and   $16,$0,$0        	 # Clear Carry
4955		 and   $17,$0,$0        	 # Clear Overflow
4956		 srl   $19,$2,7         	 # Set Sign
4957		 sltiu $18,$2,1         	 # Set Zero
4958		 lw    $14,0x3C($21)    	 # Get A7
4959		 addiu $25,$14,2
4960		 sw    $25,0x3C($21)
4961		 lw    $25,0x88($21)
4962		 sw    $15,m68k_ICount
4963		 or    $5,$0,$2
4964		 or    $4,$0,$14
4965		 jalr  $25
4966		 sw    $23,0x4C($21)    	 # Delay slot
4967		 lw    $15,m68k_ICount
4968		 addiu $15,$15,-14
4969		 bgez  $15,3f
4970		 lhu   $24,0x00($23)    	 # Delay slot
4971		 j     MainExit
4972	3:
4973		 sll   $7,$24,2         	 # Delay slot
4974		 addu  $7,$7,$30
4975		 lw    $7,0x00($7)
4976		 jr    $7
4977		 nop                    	 # Delay slot
4978
4979OP0_1ee8:				#:
4980		 addiu $23,$23,2
4981
4982		 and   $8,$24,0x07
4983		 lh    $7,0x00($23)
4984		 sll   $8,$8,2
4985		 addu  $8,$8,$21
4986		 lw    $14,0x20($8)
4987		 addiu $23,$23,2
4988		 addu  $14,$14,$7
4989		 lw    $25,0x7C($21)
4990		 sw    $15,m68k_ICount
4991		 or    $4,$0,$14
4992		 jalr  $25
4993		 sw    $23,0x4C($21)    	 # Delay slot
4994		 lw    $15,m68k_ICount
4995		 and   $16,$0,$0        	 # Clear Carry
4996		 and   $17,$0,$0        	 # Clear Overflow
4997		 srl   $19,$2,7         	 # Set Sign
4998		 sltiu $18,$2,1         	 # Set Zero
4999		 lw    $14,0x3C($21)    	 # Get A7
5000		 addiu $25,$14,2
5001		 sw    $25,0x3C($21)
5002		 lw    $25,0x88($21)
5003		 sw    $15,m68k_ICount
5004		 or    $5,$0,$2
5005		 or    $4,$0,$14
5006		 jalr  $25
5007		 sw    $23,0x4C($21)    	 # Delay slot
5008		 lw    $15,m68k_ICount
5009		 addiu $15,$15,-16
5010		 bgez  $15,3f
5011		 lhu   $24,0x00($23)    	 # Delay slot
5012		 j     MainExit
5013	3:
5014		 sll   $7,$24,2         	 # Delay slot
5015		 addu  $7,$7,$30
5016		 lw    $7,0x00($7)
5017		 jr    $7
5018		 nop                    	 # Delay slot
5019
5020OP0_1ef0:				#:
5021		 addiu $23,$23,2
5022
5023		 and   $8,$24,0x07
5024		 sll   $8,$8,2
5025		 addu  $8,$8,$21
5026		 lw    $14,0x20($8)
5027		 lhu   $7,0x00($23)
5028		 addiu $23,$23,2
5029		 seb   $6,$7
5030		 or    $25,$0,$7
5031		 srl   $7,$7,12
5032		 andi  $25,$25,0x0800
5033		 sll   $7,$7,2
5034		 addu  $7,$7,$21
5035		 bne   $25,$0,0f
5036		 lw    $25,0x00($7)      	 # Delay slot
5037		 seh   $25,$25
5038	0:
5039		 addu  $25,$14,$25
5040		 addu  $14,$25,$6
5041		 lw    $25,0x7C($21)
5042		 sw    $15,m68k_ICount
5043		 or    $4,$0,$14
5044		 jalr  $25
5045		 sw    $23,0x4C($21)    	 # Delay slot
5046		 lw    $15,m68k_ICount
5047		 and   $16,$0,$0        	 # Clear Carry
5048		 and   $17,$0,$0        	 # Clear Overflow
5049		 srl   $19,$2,7         	 # Set Sign
5050		 sltiu $18,$2,1         	 # Set Zero
5051		 lw    $14,0x3C($21)    	 # Get A7
5052		 addiu $25,$14,2
5053		 sw    $25,0x3C($21)
5054		 lw    $25,0x88($21)
5055		 sw    $15,m68k_ICount
5056		 or    $5,$0,$2
5057		 or    $4,$0,$14
5058		 jalr  $25
5059		 sw    $23,0x4C($21)    	 # Delay slot
5060		 lw    $15,m68k_ICount
5061		 addiu $15,$15,-18
5062		 bgez  $15,3f
5063		 lhu   $24,0x00($23)    	 # Delay slot
5064		 j     MainExit
5065	3:
5066		 sll   $7,$24,2         	 # Delay slot
5067		 addu  $7,$7,$30
5068		 lw    $7,0x00($7)
5069		 jr    $7
5070		 nop                    	 # Delay slot
5071
5072OP0_1ef8:				#:
5073		 addiu $23,$23,2
5074
5075		 lh    $14,0x00($23)
5076		 addiu $23,$23,2
5077		 lw    $25,0x7C($21)
5078		 sw    $15,m68k_ICount
5079		 or    $4,$0,$14
5080		 jalr  $25
5081		 sw    $23,0x4C($21)    	 # Delay slot
5082		 lw    $15,m68k_ICount
5083		 and   $16,$0,$0        	 # Clear Carry
5084		 and   $17,$0,$0        	 # Clear Overflow
5085		 srl   $19,$2,7         	 # Set Sign
5086		 sltiu $18,$2,1         	 # Set Zero
5087		 lw    $14,0x3C($21)    	 # Get A7
5088		 addiu $25,$14,2
5089		 sw    $25,0x3C($21)
5090		 lw    $25,0x88($21)
5091		 sw    $15,m68k_ICount
5092		 or    $5,$0,$2
5093		 or    $4,$0,$14
5094		 jalr  $25
5095		 sw    $23,0x4C($21)    	 # Delay slot
5096		 lw    $15,m68k_ICount
5097		 addiu $15,$15,-16
5098		 bgez  $15,3f
5099		 lhu   $24,0x00($23)    	 # Delay slot
5100		 j     MainExit
5101	3:
5102		 sll   $7,$24,2         	 # Delay slot
5103		 addu  $7,$7,$30
5104		 lw    $7,0x00($7)
5105		 jr    $7
5106		 nop                    	 # Delay slot
5107
5108OP0_1ef9:				#:
5109		 addiu $23,$23,2
5110
5111		 lhu   $14,0x00($23)
5112		 lhu   $25,0x02($23)
5113		 sll   $14,$14,16
5114		 or    $14,$14,$25
5115		 addiu $23,$23,4
5116		 lw    $25,0x7C($21)
5117		 sw    $15,m68k_ICount
5118		 or    $4,$0,$14
5119		 jalr  $25
5120		 sw    $23,0x4C($21)    	 # Delay slot
5121		 lw    $15,m68k_ICount
5122		 and   $16,$0,$0        	 # Clear Carry
5123		 and   $17,$0,$0        	 # Clear Overflow
5124		 srl   $19,$2,7         	 # Set Sign
5125		 sltiu $18,$2,1         	 # Set Zero
5126		 lw    $14,0x3C($21)    	 # Get A7
5127		 addiu $25,$14,2
5128		 sw    $25,0x3C($21)
5129		 lw    $25,0x88($21)
5130		 sw    $15,m68k_ICount
5131		 or    $5,$0,$2
5132		 or    $4,$0,$14
5133		 jalr  $25
5134		 sw    $23,0x4C($21)    	 # Delay slot
5135		 lw    $15,m68k_ICount
5136		 addiu $15,$15,-20
5137		 bgez  $15,3f
5138		 lhu   $24,0x00($23)    	 # Delay slot
5139		 j     MainExit
5140	3:
5141		 sll   $7,$24,2         	 # Delay slot
5142		 addu  $7,$7,$30
5143		 lw    $7,0x00($7)
5144		 jr    $7
5145		 nop                    	 # Delay slot
5146
5147OP0_1efa:				#:
5148		 addiu $23,$23,2
5149
5150		 lh    $7,0x00($23)
5151		 subu  $25,$23,$22
5152		 addu  $14,$25,$7       	 # Add Offset to PC
5153		 addiu $23,$23,2
5154		 lw    $25,0x98($21)
5155		 sw    $15,m68k_ICount
5156		 or    $4,$0,$14
5157		 jalr  $25
5158		 sw    $23,0x4C($21)    	 # Delay slot
5159		 lw    $15,m68k_ICount
5160		 and   $16,$0,$0        	 # Clear Carry
5161		 and   $17,$0,$0        	 # Clear Overflow
5162		 srl   $19,$2,7         	 # Set Sign
5163		 sltiu $18,$2,1         	 # Set Zero
5164		 lw    $14,0x3C($21)    	 # Get A7
5165		 addiu $25,$14,2
5166		 sw    $25,0x3C($21)
5167		 lw    $25,0x88($21)
5168		 sw    $15,m68k_ICount
5169		 or    $5,$0,$2
5170		 or    $4,$0,$14
5171		 jalr  $25
5172		 sw    $23,0x4C($21)    	 # Delay slot
5173		 lw    $15,m68k_ICount
5174		 addiu $15,$15,-16
5175		 bgez  $15,3f
5176		 lhu   $24,0x00($23)    	 # Delay slot
5177		 j     MainExit
5178	3:
5179		 sll   $7,$24,2         	 # Delay slot
5180		 addu  $7,$7,$30
5181		 lw    $7,0x00($7)
5182		 jr    $7
5183		 nop                    	 # Delay slot
5184
5185OP0_1efb:				#:
5186		 addiu $23,$23,2
5187
5188		 subu  $14,$23,$22       	 # Get PC
5189		 lhu   $7,0x00($23)
5190		 addiu $23,$23,2
5191		 seb   $6,$7
5192		 or    $25,$0,$7
5193		 srl   $7,$7,12
5194		 andi  $25,$25,0x0800
5195		 sll   $7,$7,2
5196		 addu  $7,$7,$21
5197		 bne   $25,$0,0f
5198		 lw    $25,0x00($7)      	 # Delay slot
5199		 seh   $25,$25
5200	0:
5201		 addu  $25,$14,$25
5202		 addu  $14,$25,$6
5203		 lw    $25,0x98($21)
5204		 sw    $15,m68k_ICount
5205		 or    $4,$0,$14
5206		 jalr  $25
5207		 sw    $23,0x4C($21)    	 # Delay slot
5208		 lw    $15,m68k_ICount
5209		 and   $16,$0,$0        	 # Clear Carry
5210		 and   $17,$0,$0        	 # Clear Overflow
5211		 srl   $19,$2,7         	 # Set Sign
5212		 sltiu $18,$2,1         	 # Set Zero
5213		 lw    $14,0x3C($21)    	 # Get A7
5214		 addiu $25,$14,2
5215		 sw    $25,0x3C($21)
5216		 lw    $25,0x88($21)
5217		 sw    $15,m68k_ICount
5218		 or    $5,$0,$2
5219		 or    $4,$0,$14
5220		 jalr  $25
5221		 sw    $23,0x4C($21)    	 # Delay slot
5222		 lw    $15,m68k_ICount
5223		 addiu $15,$15,-18
5224		 bgez  $15,3f
5225		 lhu   $24,0x00($23)    	 # Delay slot
5226		 j     MainExit
5227	3:
5228		 sll   $7,$24,2         	 # Delay slot
5229		 addu  $7,$7,$30
5230		 lw    $7,0x00($7)
5231		 jr    $7
5232		 nop                    	 # Delay slot
5233
5234OP0_1efc:				#:
5235		 addiu $23,$23,2
5236
5237		 lbu   $2,0x00($23)
5238		 addiu $23,$23,2
5239		 and   $16,$0,$0        	 # Clear Carry
5240		 and   $17,$0,$0        	 # Clear Overflow
5241		 srl   $19,$2,7         	 # Set Sign
5242		 sltiu $18,$2,1         	 # Set Zero
5243		 lw    $14,0x3C($21)    	 # Get A7
5244		 addiu $25,$14,2
5245		 sw    $25,0x3C($21)
5246		 lw    $25,0x88($21)
5247		 sw    $15,m68k_ICount
5248		 or    $5,$0,$2
5249		 or    $4,$0,$14
5250		 jalr  $25
5251		 sw    $23,0x4C($21)    	 # Delay slot
5252		 lw    $15,m68k_ICount
5253		 addiu $15,$15,-8
5254		 bgez  $15,3f
5255		 lhu   $24,0x00($23)    	 # Delay slot
5256		 j     MainExit
5257	3:
5258		 sll   $7,$24,2         	 # Delay slot
5259		 addu  $7,$7,$30
5260		 lw    $7,0x00($7)
5261		 jr    $7
5262		 nop                    	 # Delay slot
5263
5264OP0_1f00:				#:
5265		 addiu $23,$23,2
5266
5267		 and   $8,$24,0x0f
5268		 sll   $8,$8,2
5269		 addu  $8,$8,$21
5270		 lbu   $2,0x00($8)
5271		 and   $16,$0,$0        	 # Clear Carry
5272		 and   $17,$0,$0        	 # Clear Overflow
5273		 srl   $19,$2,7         	 # Set Sign
5274		 sltiu $18,$2,1         	 # Set Zero
5275		 lw    $14,0x3C($21)    	 # Get A7
5276		 addiu $14,$14,-2
5277		 sw    $14,0x3C($21)
5278		 lw    $25,0x88($21)
5279		 sw    $15,m68k_ICount
5280		 or    $5,$0,$2
5281		 or    $4,$0,$14
5282		 jalr  $25
5283		 sw    $23,0x4C($21)    	 # Delay slot
5284		 lw    $15,m68k_ICount
5285		 addiu $15,$15,-10
5286		 bgez  $15,3f
5287		 lhu   $24,0x00($23)    	 # Delay slot
5288		 j     MainExit
5289	3:
5290		 sll   $7,$24,2         	 # Delay slot
5291		 addu  $7,$7,$30
5292		 lw    $7,0x00($7)
5293		 jr    $7
5294		 nop                    	 # Delay slot
5295
5296OP0_1f10:				#:
5297		 addiu $23,$23,2
5298
5299		 and   $8,$24,0x07
5300		 sll   $8,$8,2
5301		 addu  $8,$8,$21
5302		 lw    $14,0x20($8)
5303		 lw    $25,0x7C($21)
5304		 sw    $15,m68k_ICount
5305		 or    $4,$0,$14
5306		 jalr  $25
5307		 sw    $23,0x4C($21)    	 # Delay slot
5308		 lw    $15,m68k_ICount
5309		 and   $16,$0,$0        	 # Clear Carry
5310		 and   $17,$0,$0        	 # Clear Overflow
5311		 srl   $19,$2,7         	 # Set Sign
5312		 sltiu $18,$2,1         	 # Set Zero
5313		 lw    $14,0x3C($21)    	 # Get A7
5314		 addiu $14,$14,-2
5315		 sw    $14,0x3C($21)
5316		 lw    $25,0x88($21)
5317		 sw    $15,m68k_ICount
5318		 or    $5,$0,$2
5319		 or    $4,$0,$14
5320		 jalr  $25
5321		 sw    $23,0x4C($21)    	 # Delay slot
5322		 lw    $15,m68k_ICount
5323		 addiu $15,$15,-14
5324		 bgez  $15,3f
5325		 lhu   $24,0x00($23)    	 # Delay slot
5326		 j     MainExit
5327	3:
5328		 sll   $7,$24,2         	 # Delay slot
5329		 addu  $7,$7,$30
5330		 lw    $7,0x00($7)
5331		 jr    $7
5332		 nop                    	 # Delay slot
5333
5334OP0_1f18:				#:
5335		 addiu $23,$23,2
5336
5337		 and   $8,$24,0x07
5338		 sll   $8,$8,2
5339		 addu  $8,$8,$21
5340		 lw    $14,0x20($8)
5341		 addiu $25,$14,1
5342		 sw    $25,0x20($8)
5343		 lw    $25,0x7C($21)
5344		 sw    $15,m68k_ICount
5345		 or    $4,$0,$14
5346		 jalr  $25
5347		 sw    $23,0x4C($21)    	 # Delay slot
5348		 lw    $15,m68k_ICount
5349		 and   $16,$0,$0        	 # Clear Carry
5350		 and   $17,$0,$0        	 # Clear Overflow
5351		 srl   $19,$2,7         	 # Set Sign
5352		 sltiu $18,$2,1         	 # Set Zero
5353		 lw    $14,0x3C($21)    	 # Get A7
5354		 addiu $14,$14,-2
5355		 sw    $14,0x3C($21)
5356		 lw    $25,0x88($21)
5357		 sw    $15,m68k_ICount
5358		 or    $5,$0,$2
5359		 or    $4,$0,$14
5360		 jalr  $25
5361		 sw    $23,0x4C($21)    	 # Delay slot
5362		 lw    $15,m68k_ICount
5363		 addiu $15,$15,-14
5364		 bgez  $15,3f
5365		 lhu   $24,0x00($23)    	 # Delay slot
5366		 j     MainExit
5367	3:
5368		 sll   $7,$24,2         	 # Delay slot
5369		 addu  $7,$7,$30
5370		 lw    $7,0x00($7)
5371		 jr    $7
5372		 nop                    	 # Delay slot
5373
5374OP0_1f1f:				#:
5375		 addiu $23,$23,2
5376
5377		 lw    $14,0x3C($21)    	 # Get A7
5378		 addiu $25,$14,2
5379		 sw    $25,0x3C($21)
5380		 lw    $25,0x7C($21)
5381		 sw    $15,m68k_ICount
5382		 or    $4,$0,$14
5383		 jalr  $25
5384		 sw    $23,0x4C($21)    	 # Delay slot
5385		 lw    $15,m68k_ICount
5386		 and   $16,$0,$0        	 # Clear Carry
5387		 and   $17,$0,$0        	 # Clear Overflow
5388		 srl   $19,$2,7         	 # Set Sign
5389		 sltiu $18,$2,1         	 # Set Zero
5390		 lw    $14,0x3C($21)    	 # Get A7
5391		 addiu $14,$14,-2
5392		 sw    $14,0x3C($21)
5393		 lw    $25,0x88($21)
5394		 sw    $15,m68k_ICount
5395		 or    $5,$0,$2
5396		 or    $4,$0,$14
5397		 jalr  $25
5398		 sw    $23,0x4C($21)    	 # Delay slot
5399		 lw    $15,m68k_ICount
5400		 addiu $15,$15,-14
5401		 bgez  $15,3f
5402		 lhu   $24,0x00($23)    	 # Delay slot
5403		 j     MainExit
5404	3:
5405		 sll   $7,$24,2         	 # Delay slot
5406		 addu  $7,$7,$30
5407		 lw    $7,0x00($7)
5408		 jr    $7
5409		 nop                    	 # Delay slot
5410
5411OP0_1f20:				#:
5412		 addiu $23,$23,2
5413
5414		 and   $8,$24,0x07
5415		 sll   $8,$8,2
5416		 addu  $8,$8,$21
5417		 lw    $14,0x20($8)
5418		 addiu $14,$14,-1
5419		 sw    $14,0x20($8)
5420		 lw    $25,0x7C($21)
5421		 sw    $15,m68k_ICount
5422		 or    $4,$0,$14
5423		 jalr  $25
5424		 sw    $23,0x4C($21)    	 # Delay slot
5425		 lw    $15,m68k_ICount
5426		 and   $16,$0,$0        	 # Clear Carry
5427		 and   $17,$0,$0        	 # Clear Overflow
5428		 srl   $19,$2,7         	 # Set Sign
5429		 sltiu $18,$2,1         	 # Set Zero
5430		 lw    $14,0x3C($21)    	 # Get A7
5431		 addiu $14,$14,-2
5432		 sw    $14,0x3C($21)
5433		 lw    $25,0x88($21)
5434		 sw    $15,m68k_ICount
5435		 or    $5,$0,$2
5436		 or    $4,$0,$14
5437		 jalr  $25
5438		 sw    $23,0x4C($21)    	 # Delay slot
5439		 lw    $15,m68k_ICount
5440		 addiu $15,$15,-16
5441		 bgez  $15,3f
5442		 lhu   $24,0x00($23)    	 # Delay slot
5443		 j     MainExit
5444	3:
5445		 sll   $7,$24,2         	 # Delay slot
5446		 addu  $7,$7,$30
5447		 lw    $7,0x00($7)
5448		 jr    $7
5449		 nop                    	 # Delay slot
5450
5451OP0_1f27:				#:
5452		 addiu $23,$23,2
5453
5454		 lw    $14,0x3C($21)    	 # Get A7
5455		 addiu $14,$14,-2
5456		 sw    $14,0x3C($21)
5457		 lw    $25,0x7C($21)
5458		 sw    $15,m68k_ICount
5459		 or    $4,$0,$14
5460		 jalr  $25
5461		 sw    $23,0x4C($21)    	 # Delay slot
5462		 lw    $15,m68k_ICount
5463		 and   $16,$0,$0        	 # Clear Carry
5464		 and   $17,$0,$0        	 # Clear Overflow
5465		 srl   $19,$2,7         	 # Set Sign
5466		 sltiu $18,$2,1         	 # Set Zero
5467		 lw    $14,0x3C($21)    	 # Get A7
5468		 addiu $14,$14,-2
5469		 sw    $14,0x3C($21)
5470		 lw    $25,0x88($21)
5471		 sw    $15,m68k_ICount
5472		 or    $5,$0,$2
5473		 or    $4,$0,$14
5474		 jalr  $25
5475		 sw    $23,0x4C($21)    	 # Delay slot
5476		 lw    $15,m68k_ICount
5477		 addiu $15,$15,-16
5478		 bgez  $15,3f
5479		 lhu   $24,0x00($23)    	 # Delay slot
5480		 j     MainExit
5481	3:
5482		 sll   $7,$24,2         	 # Delay slot
5483		 addu  $7,$7,$30
5484		 lw    $7,0x00($7)
5485		 jr    $7
5486		 nop                    	 # Delay slot
5487
5488OP0_1f28:				#:
5489		 addiu $23,$23,2
5490
5491		 and   $8,$24,0x07
5492		 lh    $7,0x00($23)
5493		 sll   $8,$8,2
5494		 addu  $8,$8,$21
5495		 lw    $14,0x20($8)
5496		 addiu $23,$23,2
5497		 addu  $14,$14,$7
5498		 lw    $25,0x7C($21)
5499		 sw    $15,m68k_ICount
5500		 or    $4,$0,$14
5501		 jalr  $25
5502		 sw    $23,0x4C($21)    	 # Delay slot
5503		 lw    $15,m68k_ICount
5504		 and   $16,$0,$0        	 # Clear Carry
5505		 and   $17,$0,$0        	 # Clear Overflow
5506		 srl   $19,$2,7         	 # Set Sign
5507		 sltiu $18,$2,1         	 # Set Zero
5508		 lw    $14,0x3C($21)    	 # Get A7
5509		 addiu $14,$14,-2
5510		 sw    $14,0x3C($21)
5511		 lw    $25,0x88($21)
5512		 sw    $15,m68k_ICount
5513		 or    $5,$0,$2
5514		 or    $4,$0,$14
5515		 jalr  $25
5516		 sw    $23,0x4C($21)    	 # Delay slot
5517		 lw    $15,m68k_ICount
5518		 addiu $15,$15,-18
5519		 bgez  $15,3f
5520		 lhu   $24,0x00($23)    	 # Delay slot
5521		 j     MainExit
5522	3:
5523		 sll   $7,$24,2         	 # Delay slot
5524		 addu  $7,$7,$30
5525		 lw    $7,0x00($7)
5526		 jr    $7
5527		 nop                    	 # Delay slot
5528
5529OP0_1f30:				#:
5530		 addiu $23,$23,2
5531
5532		 and   $8,$24,0x07
5533		 sll   $8,$8,2
5534		 addu  $8,$8,$21
5535		 lw    $14,0x20($8)
5536		 lhu   $7,0x00($23)
5537		 addiu $23,$23,2
5538		 seb   $6,$7
5539		 or    $25,$0,$7
5540		 srl   $7,$7,12
5541		 andi  $25,$25,0x0800
5542		 sll   $7,$7,2
5543		 addu  $7,$7,$21
5544		 bne   $25,$0,0f
5545		 lw    $25,0x00($7)      	 # Delay slot
5546		 seh   $25,$25
5547	0:
5548		 addu  $25,$14,$25
5549		 addu  $14,$25,$6
5550		 lw    $25,0x7C($21)
5551		 sw    $15,m68k_ICount
5552		 or    $4,$0,$14
5553		 jalr  $25
5554		 sw    $23,0x4C($21)    	 # Delay slot
5555		 lw    $15,m68k_ICount
5556		 and   $16,$0,$0        	 # Clear Carry
5557		 and   $17,$0,$0        	 # Clear Overflow
5558		 srl   $19,$2,7         	 # Set Sign
5559		 sltiu $18,$2,1         	 # Set Zero
5560		 lw    $14,0x3C($21)    	 # Get A7
5561		 addiu $14,$14,-2
5562		 sw    $14,0x3C($21)
5563		 lw    $25,0x88($21)
5564		 sw    $15,m68k_ICount
5565		 or    $5,$0,$2
5566		 or    $4,$0,$14
5567		 jalr  $25
5568		 sw    $23,0x4C($21)    	 # Delay slot
5569		 lw    $15,m68k_ICount
5570		 addiu $15,$15,-20
5571		 bgez  $15,3f
5572		 lhu   $24,0x00($23)    	 # Delay slot
5573		 j     MainExit
5574	3:
5575		 sll   $7,$24,2         	 # Delay slot
5576		 addu  $7,$7,$30
5577		 lw    $7,0x00($7)
5578		 jr    $7
5579		 nop                    	 # Delay slot
5580
5581OP0_1f38:				#:
5582		 addiu $23,$23,2
5583
5584		 lh    $14,0x00($23)
5585		 addiu $23,$23,2
5586		 lw    $25,0x7C($21)
5587		 sw    $15,m68k_ICount
5588		 or    $4,$0,$14
5589		 jalr  $25
5590		 sw    $23,0x4C($21)    	 # Delay slot
5591		 lw    $15,m68k_ICount
5592		 and   $16,$0,$0        	 # Clear Carry
5593		 and   $17,$0,$0        	 # Clear Overflow
5594		 srl   $19,$2,7         	 # Set Sign
5595		 sltiu $18,$2,1         	 # Set Zero
5596		 lw    $14,0x3C($21)    	 # Get A7
5597		 addiu $14,$14,-2
5598		 sw    $14,0x3C($21)
5599		 lw    $25,0x88($21)
5600		 sw    $15,m68k_ICount
5601		 or    $5,$0,$2
5602		 or    $4,$0,$14
5603		 jalr  $25
5604		 sw    $23,0x4C($21)    	 # Delay slot
5605		 lw    $15,m68k_ICount
5606		 addiu $15,$15,-18
5607		 bgez  $15,3f
5608		 lhu   $24,0x00($23)    	 # Delay slot
5609		 j     MainExit
5610	3:
5611		 sll   $7,$24,2         	 # Delay slot
5612		 addu  $7,$7,$30
5613		 lw    $7,0x00($7)
5614		 jr    $7
5615		 nop                    	 # Delay slot
5616
5617OP0_1f39:				#:
5618		 addiu $23,$23,2
5619
5620		 lhu   $14,0x00($23)
5621		 lhu   $25,0x02($23)
5622		 sll   $14,$14,16
5623		 or    $14,$14,$25
5624		 addiu $23,$23,4
5625		 lw    $25,0x7C($21)
5626		 sw    $15,m68k_ICount
5627		 or    $4,$0,$14
5628		 jalr  $25
5629		 sw    $23,0x4C($21)    	 # Delay slot
5630		 lw    $15,m68k_ICount
5631		 and   $16,$0,$0        	 # Clear Carry
5632		 and   $17,$0,$0        	 # Clear Overflow
5633		 srl   $19,$2,7         	 # Set Sign
5634		 sltiu $18,$2,1         	 # Set Zero
5635		 lw    $14,0x3C($21)    	 # Get A7
5636		 addiu $14,$14,-2
5637		 sw    $14,0x3C($21)
5638		 lw    $25,0x88($21)
5639		 sw    $15,m68k_ICount
5640		 or    $5,$0,$2
5641		 or    $4,$0,$14
5642		 jalr  $25
5643		 sw    $23,0x4C($21)    	 # Delay slot
5644		 lw    $15,m68k_ICount
5645		 addiu $15,$15,-22
5646		 bgez  $15,3f
5647		 lhu   $24,0x00($23)    	 # Delay slot
5648		 j     MainExit
5649	3:
5650		 sll   $7,$24,2         	 # Delay slot
5651		 addu  $7,$7,$30
5652		 lw    $7,0x00($7)
5653		 jr    $7
5654		 nop                    	 # Delay slot
5655
5656OP0_1f3a:				#:
5657		 addiu $23,$23,2
5658
5659		 lh    $7,0x00($23)
5660		 subu  $25,$23,$22
5661		 addu  $14,$25,$7       	 # Add Offset to PC
5662		 addiu $23,$23,2
5663		 lw    $25,0x98($21)
5664		 sw    $15,m68k_ICount
5665		 or    $4,$0,$14
5666		 jalr  $25
5667		 sw    $23,0x4C($21)    	 # Delay slot
5668		 lw    $15,m68k_ICount
5669		 and   $16,$0,$0        	 # Clear Carry
5670		 and   $17,$0,$0        	 # Clear Overflow
5671		 srl   $19,$2,7         	 # Set Sign
5672		 sltiu $18,$2,1         	 # Set Zero
5673		 lw    $14,0x3C($21)    	 # Get A7
5674		 addiu $14,$14,-2
5675		 sw    $14,0x3C($21)
5676		 lw    $25,0x88($21)
5677		 sw    $15,m68k_ICount
5678		 or    $5,$0,$2
5679		 or    $4,$0,$14
5680		 jalr  $25
5681		 sw    $23,0x4C($21)    	 # Delay slot
5682		 lw    $15,m68k_ICount
5683		 addiu $15,$15,-18
5684		 bgez  $15,3f
5685		 lhu   $24,0x00($23)    	 # Delay slot
5686		 j     MainExit
5687	3:
5688		 sll   $7,$24,2         	 # Delay slot
5689		 addu  $7,$7,$30
5690		 lw    $7,0x00($7)
5691		 jr    $7
5692		 nop                    	 # Delay slot
5693
5694OP0_1f3b:				#:
5695		 addiu $23,$23,2
5696
5697		 subu  $14,$23,$22       	 # Get PC
5698		 lhu   $7,0x00($23)
5699		 addiu $23,$23,2
5700		 seb   $6,$7
5701		 or    $25,$0,$7
5702		 srl   $7,$7,12
5703		 andi  $25,$25,0x0800
5704		 sll   $7,$7,2
5705		 addu  $7,$7,$21
5706		 bne   $25,$0,0f
5707		 lw    $25,0x00($7)      	 # Delay slot
5708		 seh   $25,$25
5709	0:
5710		 addu  $25,$14,$25
5711		 addu  $14,$25,$6
5712		 lw    $25,0x98($21)
5713		 sw    $15,m68k_ICount
5714		 or    $4,$0,$14
5715		 jalr  $25
5716		 sw    $23,0x4C($21)    	 # Delay slot
5717		 lw    $15,m68k_ICount
5718		 and   $16,$0,$0        	 # Clear Carry
5719		 and   $17,$0,$0        	 # Clear Overflow
5720		 srl   $19,$2,7         	 # Set Sign
5721		 sltiu $18,$2,1         	 # Set Zero
5722		 lw    $14,0x3C($21)    	 # Get A7
5723		 addiu $14,$14,-2
5724		 sw    $14,0x3C($21)
5725		 lw    $25,0x88($21)
5726		 sw    $15,m68k_ICount
5727		 or    $5,$0,$2
5728		 or    $4,$0,$14
5729		 jalr  $25
5730		 sw    $23,0x4C($21)    	 # Delay slot
5731		 lw    $15,m68k_ICount
5732		 addiu $15,$15,-20
5733		 bgez  $15,3f
5734		 lhu   $24,0x00($23)    	 # Delay slot
5735		 j     MainExit
5736	3:
5737		 sll   $7,$24,2         	 # Delay slot
5738		 addu  $7,$7,$30
5739		 lw    $7,0x00($7)
5740		 jr    $7
5741		 nop                    	 # Delay slot
5742
5743OP0_1f3c:				#:
5744		 addiu $23,$23,2
5745
5746		 lbu   $2,0x00($23)
5747		 addiu $23,$23,2
5748		 and   $16,$0,$0        	 # Clear Carry
5749		 and   $17,$0,$0        	 # Clear Overflow
5750		 srl   $19,$2,7         	 # Set Sign
5751		 sltiu $18,$2,1         	 # Set Zero
5752		 lw    $14,0x3C($21)    	 # Get A7
5753		 addiu $14,$14,-2
5754		 sw    $14,0x3C($21)
5755		 lw    $25,0x88($21)
5756		 sw    $15,m68k_ICount
5757		 or    $5,$0,$2
5758		 or    $4,$0,$14
5759		 jalr  $25
5760		 sw    $23,0x4C($21)    	 # Delay slot
5761		 lw    $15,m68k_ICount
5762		 addiu $15,$15,-10
5763		 bgez  $15,3f
5764		 lhu   $24,0x00($23)    	 # Delay slot
5765		 j     MainExit
5766	3:
5767		 sll   $7,$24,2         	 # Delay slot
5768		 addu  $7,$7,$30
5769		 lw    $7,0x00($7)
5770		 jr    $7
5771		 nop                    	 # Delay slot
5772
5773OP0_2000:				#:
5774		 addiu $23,$23,2
5775
5776		 and   $8,$24,0x0f
5777		 sll   $8,$8,2
5778		 addu  $8,$8,$21
5779		 lw    $2,0x00($8)
5780		 and   $16,$0,$0        	 # Clear Carry
5781		 and   $17,$0,$0        	 # Clear Overflow
5782		 srl   $19,$2,31         	 # Set Sign
5783		 sltiu $18,$2,1         	 # Set Zero
5784		 srl   $24,$24,7
5785		 andi  $24,$24,0x1C
5786		 addu  $24,$24,$21
5787		 sw    $2,0x00($24)
5788		 addiu $15,$15,-4
5789		 bgez  $15,3f
5790		 lhu   $24,0x00($23)    	 # Delay slot
5791		 j     MainExit
5792	3:
5793		 sll   $7,$24,2         	 # Delay slot
5794		 addu  $7,$7,$30
5795		 lw    $7,0x00($7)
5796		 jr    $7
5797		 nop                    	 # Delay slot
5798
5799OP0_2010:				#:
5800		 addiu $23,$23,2
5801
5802		 and   $8,$24,0x07
5803		 sll   $8,$8,2
5804		 addu  $8,$8,$21
5805		 lw    $14,0x20($8)
5806		 lw    $25,0x84($21)
5807		 sw    $15,m68k_ICount
5808		 sw    $24,0x44($29)
5809		 or    $4,$0,$14
5810		 jalr  $25
5811		 sw    $23,0x4C($21)    	 # Delay slot
5812		 lw    $24,0x44($29)
5813		 lw    $15,m68k_ICount
5814		 and   $16,$0,$0        	 # Clear Carry
5815		 and   $17,$0,$0        	 # Clear Overflow
5816		 srl   $19,$2,31         	 # Set Sign
5817		 sltiu $18,$2,1         	 # Set Zero
5818		 srl   $24,$24,7
5819		 andi  $24,$24,0x1C
5820		 addu  $24,$24,$21
5821		 sw    $2,0x00($24)
5822		 addiu $15,$15,-12
5823		 bgez  $15,3f
5824		 lhu   $24,0x00($23)    	 # Delay slot
5825		 j     MainExit
5826	3:
5827		 sll   $7,$24,2         	 # Delay slot
5828		 addu  $7,$7,$30
5829		 lw    $7,0x00($7)
5830		 jr    $7
5831		 nop                    	 # Delay slot
5832
5833OP0_2018:				#:
5834		 addiu $23,$23,2
5835
5836		 and   $8,$24,0x07
5837		 sll   $8,$8,2
5838		 addu  $8,$8,$21
5839		 lw    $14,0x20($8)
5840		 addiu $25,$14,4
5841		 sw    $25,0x20($8)
5842		 lw    $25,0x84($21)
5843		 sw    $15,m68k_ICount
5844		 sw    $24,0x44($29)
5845		 or    $4,$0,$14
5846		 jalr  $25
5847		 sw    $23,0x4C($21)    	 # Delay slot
5848		 lw    $24,0x44($29)
5849		 lw    $15,m68k_ICount
5850		 and   $16,$0,$0        	 # Clear Carry
5851		 and   $17,$0,$0        	 # Clear Overflow
5852		 srl   $19,$2,31         	 # Set Sign
5853		 sltiu $18,$2,1         	 # Set Zero
5854		 srl   $24,$24,7
5855		 andi  $24,$24,0x1C
5856		 addu  $24,$24,$21
5857		 sw    $2,0x00($24)
5858		 addiu $15,$15,-12
5859		 bgez  $15,3f
5860		 lhu   $24,0x00($23)    	 # Delay slot
5861		 j     MainExit
5862	3:
5863		 sll   $7,$24,2         	 # Delay slot
5864		 addu  $7,$7,$30
5865		 lw    $7,0x00($7)
5866		 jr    $7
5867		 nop                    	 # Delay slot
5868
5869OP0_2020:				#:
5870		 addiu $23,$23,2
5871
5872		 and   $8,$24,0x07
5873		 sll   $8,$8,2
5874		 addu  $8,$8,$21
5875		 lw    $14,0x20($8)
5876		 addiu $14,$14,-4
5877		 sw    $14,0x20($8)
5878		 lw    $25,0x84($21)
5879		 sw    $15,m68k_ICount
5880		 sw    $24,0x44($29)
5881		 or    $4,$0,$14
5882		 jalr  $25
5883		 sw    $23,0x4C($21)    	 # Delay slot
5884		 lw    $24,0x44($29)
5885		 lw    $15,m68k_ICount
5886		 and   $16,$0,$0        	 # Clear Carry
5887		 and   $17,$0,$0        	 # Clear Overflow
5888		 srl   $19,$2,31         	 # Set Sign
5889		 sltiu $18,$2,1         	 # Set Zero
5890		 srl   $24,$24,7
5891		 andi  $24,$24,0x1C
5892		 addu  $24,$24,$21
5893		 sw    $2,0x00($24)
5894		 addiu $15,$15,-14
5895		 bgez  $15,3f
5896		 lhu   $24,0x00($23)    	 # Delay slot
5897		 j     MainExit
5898	3:
5899		 sll   $7,$24,2         	 # Delay slot
5900		 addu  $7,$7,$30
5901		 lw    $7,0x00($7)
5902		 jr    $7
5903		 nop                    	 # Delay slot
5904
5905OP0_2028:				#:
5906		 addiu $23,$23,2
5907
5908		 and   $8,$24,0x07
5909		 lh    $7,0x00($23)
5910		 sll   $8,$8,2
5911		 addu  $8,$8,$21
5912		 lw    $14,0x20($8)
5913		 addiu $23,$23,2
5914		 addu  $14,$14,$7
5915		 lw    $25,0x84($21)
5916		 sw    $15,m68k_ICount
5917		 sw    $24,0x44($29)
5918		 or    $4,$0,$14
5919		 jalr  $25
5920		 sw    $23,0x4C($21)    	 # Delay slot
5921		 lw    $24,0x44($29)
5922		 lw    $15,m68k_ICount
5923		 and   $16,$0,$0        	 # Clear Carry
5924		 and   $17,$0,$0        	 # Clear Overflow
5925		 srl   $19,$2,31         	 # Set Sign
5926		 sltiu $18,$2,1         	 # Set Zero
5927		 srl   $24,$24,7
5928		 andi  $24,$24,0x1C
5929		 addu  $24,$24,$21
5930		 sw    $2,0x00($24)
5931		 addiu $15,$15,-16
5932		 bgez  $15,3f
5933		 lhu   $24,0x00($23)    	 # Delay slot
5934		 j     MainExit
5935	3:
5936		 sll   $7,$24,2         	 # Delay slot
5937		 addu  $7,$7,$30
5938		 lw    $7,0x00($7)
5939		 jr    $7
5940		 nop                    	 # Delay slot
5941
5942OP0_2030:				#:
5943		 addiu $23,$23,2
5944
5945		 and   $8,$24,0x07
5946		 sll   $8,$8,2
5947		 addu  $8,$8,$21
5948		 lw    $14,0x20($8)
5949		 lhu   $7,0x00($23)
5950		 addiu $23,$23,2
5951		 seb   $6,$7
5952		 or    $25,$0,$7
5953		 srl   $7,$7,12
5954		 andi  $25,$25,0x0800
5955		 sll   $7,$7,2
5956		 addu  $7,$7,$21
5957		 bne   $25,$0,0f
5958		 lw    $25,0x00($7)      	 # Delay slot
5959		 seh   $25,$25
5960	0:
5961		 addu  $25,$14,$25
5962		 addu  $14,$25,$6
5963		 lw    $25,0x84($21)
5964		 sw    $15,m68k_ICount
5965		 sw    $24,0x44($29)
5966		 or    $4,$0,$14
5967		 jalr  $25
5968		 sw    $23,0x4C($21)    	 # Delay slot
5969		 lw    $24,0x44($29)
5970		 lw    $15,m68k_ICount
5971		 and   $16,$0,$0        	 # Clear Carry
5972		 and   $17,$0,$0        	 # Clear Overflow
5973		 srl   $19,$2,31         	 # Set Sign
5974		 sltiu $18,$2,1         	 # Set Zero
5975		 srl   $24,$24,7
5976		 andi  $24,$24,0x1C
5977		 addu  $24,$24,$21
5978		 sw    $2,0x00($24)
5979		 addiu $15,$15,-18
5980		 bgez  $15,3f
5981		 lhu   $24,0x00($23)    	 # Delay slot
5982		 j     MainExit
5983	3:
5984		 sll   $7,$24,2         	 # Delay slot
5985		 addu  $7,$7,$30
5986		 lw    $7,0x00($7)
5987		 jr    $7
5988		 nop                    	 # Delay slot
5989
5990OP0_2038:				#:
5991		 addiu $23,$23,2
5992
5993		 lh    $14,0x00($23)
5994		 addiu $23,$23,2
5995		 lw    $25,0x84($21)
5996		 sw    $15,m68k_ICount
5997		 sw    $24,0x44($29)
5998		 or    $4,$0,$14
5999		 jalr  $25
6000		 sw    $23,0x4C($21)    	 # Delay slot
6001		 lw    $24,0x44($29)
6002		 lw    $15,m68k_ICount
6003		 and   $16,$0,$0        	 # Clear Carry
6004		 and   $17,$0,$0        	 # Clear Overflow
6005		 srl   $19,$2,31         	 # Set Sign
6006		 sltiu $18,$2,1         	 # Set Zero
6007		 srl   $24,$24,7
6008		 andi  $24,$24,0x1C
6009		 addu  $24,$24,$21
6010		 sw    $2,0x00($24)
6011		 addiu $15,$15,-16
6012		 bgez  $15,3f
6013		 lhu   $24,0x00($23)    	 # Delay slot
6014		 j     MainExit
6015	3:
6016		 sll   $7,$24,2         	 # Delay slot
6017		 addu  $7,$7,$30
6018		 lw    $7,0x00($7)
6019		 jr    $7
6020		 nop                    	 # Delay slot
6021
6022OP0_2039:				#:
6023		 addiu $23,$23,2
6024
6025		 lhu   $14,0x00($23)
6026		 lhu   $25,0x02($23)
6027		 sll   $14,$14,16
6028		 or    $14,$14,$25
6029		 addiu $23,$23,4
6030		 lw    $25,0x84($21)
6031		 sw    $15,m68k_ICount
6032		 sw    $24,0x44($29)
6033		 or    $4,$0,$14
6034		 jalr  $25
6035		 sw    $23,0x4C($21)    	 # Delay slot
6036		 lw    $24,0x44($29)
6037		 lw    $15,m68k_ICount
6038		 and   $16,$0,$0        	 # Clear Carry
6039		 and   $17,$0,$0        	 # Clear Overflow
6040		 srl   $19,$2,31         	 # Set Sign
6041		 sltiu $18,$2,1         	 # Set Zero
6042		 srl   $24,$24,7
6043		 andi  $24,$24,0x1C
6044		 addu  $24,$24,$21
6045		 sw    $2,0x00($24)
6046		 addiu $15,$15,-20
6047		 bgez  $15,3f
6048		 lhu   $24,0x00($23)    	 # Delay slot
6049		 j     MainExit
6050	3:
6051		 sll   $7,$24,2         	 # Delay slot
6052		 addu  $7,$7,$30
6053		 lw    $7,0x00($7)
6054		 jr    $7
6055		 nop                    	 # Delay slot
6056
6057OP0_203a:				#:
6058		 addiu $23,$23,2
6059
6060		 lh    $7,0x00($23)
6061		 subu  $25,$23,$22
6062		 addu  $14,$25,$7       	 # Add Offset to PC
6063		 addiu $23,$23,2
6064		 lw    $25,0xA0($21)
6065		 sw    $15,m68k_ICount
6066		 sw    $24,0x44($29)
6067		 or    $4,$0,$14
6068		 jalr  $25
6069		 sw    $23,0x4C($21)    	 # Delay slot
6070		 lw    $24,0x44($29)
6071		 lw    $15,m68k_ICount
6072		 and   $16,$0,$0        	 # Clear Carry
6073		 and   $17,$0,$0        	 # Clear Overflow
6074		 srl   $19,$2,31         	 # Set Sign
6075		 sltiu $18,$2,1         	 # Set Zero
6076		 srl   $24,$24,7
6077		 andi  $24,$24,0x1C
6078		 addu  $24,$24,$21
6079		 sw    $2,0x00($24)
6080		 addiu $15,$15,-16
6081		 bgez  $15,3f
6082		 lhu   $24,0x00($23)    	 # Delay slot
6083		 j     MainExit
6084	3:
6085		 sll   $7,$24,2         	 # Delay slot
6086		 addu  $7,$7,$30
6087		 lw    $7,0x00($7)
6088		 jr    $7
6089		 nop                    	 # Delay slot
6090
6091OP0_203b:				#:
6092		 addiu $23,$23,2
6093
6094		 subu  $14,$23,$22       	 # Get PC
6095		 lhu   $7,0x00($23)
6096		 addiu $23,$23,2
6097		 seb   $6,$7
6098		 or    $25,$0,$7
6099		 srl   $7,$7,12
6100		 andi  $25,$25,0x0800
6101		 sll   $7,$7,2
6102		 addu  $7,$7,$21
6103		 bne   $25,$0,0f
6104		 lw    $25,0x00($7)      	 # Delay slot
6105		 seh   $25,$25
6106	0:
6107		 addu  $25,$14,$25
6108		 addu  $14,$25,$6
6109		 lw    $25,0xA0($21)
6110		 sw    $15,m68k_ICount
6111		 sw    $24,0x44($29)
6112		 or    $4,$0,$14
6113		 jalr  $25
6114		 sw    $23,0x4C($21)    	 # Delay slot
6115		 lw    $24,0x44($29)
6116		 lw    $15,m68k_ICount
6117		 and   $16,$0,$0        	 # Clear Carry
6118		 and   $17,$0,$0        	 # Clear Overflow
6119		 srl   $19,$2,31         	 # Set Sign
6120		 sltiu $18,$2,1         	 # Set Zero
6121		 srl   $24,$24,7
6122		 andi  $24,$24,0x1C
6123		 addu  $24,$24,$21
6124		 sw    $2,0x00($24)
6125		 addiu $15,$15,-18
6126		 bgez  $15,3f
6127		 lhu   $24,0x00($23)    	 # Delay slot
6128		 j     MainExit
6129	3:
6130		 sll   $7,$24,2         	 # Delay slot
6131		 addu  $7,$7,$30
6132		 lw    $7,0x00($7)
6133		 jr    $7
6134		 nop                    	 # Delay slot
6135
6136OP0_203c:				#:
6137		 addiu $23,$23,2
6138
6139		 lhu   $2,0x00($23)
6140		 lhu   $25,0x02($23)
6141		 sll   $2,$2,16
6142		 or    $2,$2,$25
6143		 addiu $23,$23,4
6144		 and   $16,$0,$0        	 # Clear Carry
6145		 and   $17,$0,$0        	 # Clear Overflow
6146		 srl   $19,$2,31         	 # Set Sign
6147		 sltiu $18,$2,1         	 # Set Zero
6148		 srl   $24,$24,7
6149		 andi  $24,$24,0x1C
6150		 addu  $24,$24,$21
6151		 sw    $2,0x00($24)
6152		 addiu $15,$15,-4
6153		 bgez  $15,3f
6154		 lhu   $24,0x00($23)    	 # Delay slot
6155		 j     MainExit
6156	3:
6157		 sll   $7,$24,2         	 # Delay slot
6158		 addu  $7,$7,$30
6159		 lw    $7,0x00($7)
6160		 jr    $7
6161		 nop                    	 # Delay slot
6162
6163OP0_2040:				#:
6164		 addiu $23,$23,2
6165
6166		 and   $8,$24,0x0f
6167		 sll   $8,$8,2
6168		 addu  $8,$8,$21
6169		 lw    $2,0x00($8)
6170		 srl   $24,$24,7
6171		 andi  $24,$24,0x1C
6172		 addu  $24,$24,$21
6173		 sw    $2,0x20($24)
6174		 addiu $15,$15,-4
6175		 bgez  $15,3f
6176		 lhu   $24,0x00($23)    	 # Delay slot
6177		 j     MainExit
6178	3:
6179		 sll   $7,$24,2         	 # Delay slot
6180		 addu  $7,$7,$30
6181		 lw    $7,0x00($7)
6182		 jr    $7
6183		 nop                    	 # Delay slot
6184
6185OP0_2050:				#:
6186		 addiu $23,$23,2
6187
6188		 and   $8,$24,0x07
6189		 sll   $8,$8,2
6190		 addu  $8,$8,$21
6191		 lw    $14,0x20($8)
6192		 lw    $25,0x84($21)
6193		 sw    $15,m68k_ICount
6194		 sw    $24,0x44($29)
6195		 or    $4,$0,$14
6196		 jalr  $25
6197		 sw    $23,0x4C($21)    	 # Delay slot
6198		 lw    $24,0x44($29)
6199		 lw    $15,m68k_ICount
6200		 srl   $24,$24,7
6201		 andi  $24,$24,0x1C
6202		 addu  $24,$24,$21
6203		 sw    $2,0x20($24)
6204		 addiu $15,$15,-12
6205		 bgez  $15,3f
6206		 lhu   $24,0x00($23)    	 # Delay slot
6207		 j     MainExit
6208	3:
6209		 sll   $7,$24,2         	 # Delay slot
6210		 addu  $7,$7,$30
6211		 lw    $7,0x00($7)
6212		 jr    $7
6213		 nop                    	 # Delay slot
6214
6215OP0_2058:				#:
6216		 addiu $23,$23,2
6217
6218		 and   $8,$24,0x07
6219		 sll   $8,$8,2
6220		 addu  $8,$8,$21
6221		 lw    $14,0x20($8)
6222		 addiu $25,$14,4
6223		 sw    $25,0x20($8)
6224		 lw    $25,0x84($21)
6225		 sw    $15,m68k_ICount
6226		 sw    $24,0x44($29)
6227		 or    $4,$0,$14
6228		 jalr  $25
6229		 sw    $23,0x4C($21)    	 # Delay slot
6230		 lw    $24,0x44($29)
6231		 lw    $15,m68k_ICount
6232		 srl   $24,$24,7
6233		 andi  $24,$24,0x1C
6234		 addu  $24,$24,$21
6235		 sw    $2,0x20($24)
6236		 addiu $15,$15,-12
6237		 bgez  $15,3f
6238		 lhu   $24,0x00($23)    	 # Delay slot
6239		 j     MainExit
6240	3:
6241		 sll   $7,$24,2         	 # Delay slot
6242		 addu  $7,$7,$30
6243		 lw    $7,0x00($7)
6244		 jr    $7
6245		 nop                    	 # Delay slot
6246
6247OP0_2060:				#:
6248		 addiu $23,$23,2
6249
6250		 and   $8,$24,0x07
6251		 sll   $8,$8,2
6252		 addu  $8,$8,$21
6253		 lw    $14,0x20($8)
6254		 addiu $14,$14,-4
6255		 sw    $14,0x20($8)
6256		 lw    $25,0x84($21)
6257		 sw    $15,m68k_ICount
6258		 sw    $24,0x44($29)
6259		 or    $4,$0,$14
6260		 jalr  $25
6261		 sw    $23,0x4C($21)    	 # Delay slot
6262		 lw    $24,0x44($29)
6263		 lw    $15,m68k_ICount
6264		 srl   $24,$24,7
6265		 andi  $24,$24,0x1C
6266		 addu  $24,$24,$21
6267		 sw    $2,0x20($24)
6268		 addiu $15,$15,-14
6269		 bgez  $15,3f
6270		 lhu   $24,0x00($23)    	 # Delay slot
6271		 j     MainExit
6272	3:
6273		 sll   $7,$24,2         	 # Delay slot
6274		 addu  $7,$7,$30
6275		 lw    $7,0x00($7)
6276		 jr    $7
6277		 nop                    	 # Delay slot
6278
6279OP0_2068:				#:
6280		 addiu $23,$23,2
6281
6282		 and   $8,$24,0x07
6283		 lh    $7,0x00($23)
6284		 sll   $8,$8,2
6285		 addu  $8,$8,$21
6286		 lw    $14,0x20($8)
6287		 addiu $23,$23,2
6288		 addu  $14,$14,$7
6289		 lw    $25,0x84($21)
6290		 sw    $15,m68k_ICount
6291		 sw    $24,0x44($29)
6292		 or    $4,$0,$14
6293		 jalr  $25
6294		 sw    $23,0x4C($21)    	 # Delay slot
6295		 lw    $24,0x44($29)
6296		 lw    $15,m68k_ICount
6297		 srl   $24,$24,7
6298		 andi  $24,$24,0x1C
6299		 addu  $24,$24,$21
6300		 sw    $2,0x20($24)
6301		 addiu $15,$15,-16
6302		 bgez  $15,3f
6303		 lhu   $24,0x00($23)    	 # Delay slot
6304		 j     MainExit
6305	3:
6306		 sll   $7,$24,2         	 # Delay slot
6307		 addu  $7,$7,$30
6308		 lw    $7,0x00($7)
6309		 jr    $7
6310		 nop                    	 # Delay slot
6311
6312OP0_2070:				#:
6313		 addiu $23,$23,2
6314
6315		 and   $8,$24,0x07
6316		 sll   $8,$8,2
6317		 addu  $8,$8,$21
6318		 lw    $14,0x20($8)
6319		 lhu   $7,0x00($23)
6320		 addiu $23,$23,2
6321		 seb   $6,$7
6322		 or    $25,$0,$7
6323		 srl   $7,$7,12
6324		 andi  $25,$25,0x0800
6325		 sll   $7,$7,2
6326		 addu  $7,$7,$21
6327		 bne   $25,$0,0f
6328		 lw    $25,0x00($7)      	 # Delay slot
6329		 seh   $25,$25
6330	0:
6331		 addu  $25,$14,$25
6332		 addu  $14,$25,$6
6333		 lw    $25,0x84($21)
6334		 sw    $15,m68k_ICount
6335		 sw    $24,0x44($29)
6336		 or    $4,$0,$14
6337		 jalr  $25
6338		 sw    $23,0x4C($21)    	 # Delay slot
6339		 lw    $24,0x44($29)
6340		 lw    $15,m68k_ICount
6341		 srl   $24,$24,7
6342		 andi  $24,$24,0x1C
6343		 addu  $24,$24,$21
6344		 sw    $2,0x20($24)
6345		 addiu $15,$15,-18
6346		 bgez  $15,3f
6347		 lhu   $24,0x00($23)    	 # Delay slot
6348		 j     MainExit
6349	3:
6350		 sll   $7,$24,2         	 # Delay slot
6351		 addu  $7,$7,$30
6352		 lw    $7,0x00($7)
6353		 jr    $7
6354		 nop                    	 # Delay slot
6355
6356OP0_2078:				#:
6357		 addiu $23,$23,2
6358
6359		 lh    $14,0x00($23)
6360		 addiu $23,$23,2
6361		 lw    $25,0x84($21)
6362		 sw    $15,m68k_ICount
6363		 sw    $24,0x44($29)
6364		 or    $4,$0,$14
6365		 jalr  $25
6366		 sw    $23,0x4C($21)    	 # Delay slot
6367		 lw    $24,0x44($29)
6368		 lw    $15,m68k_ICount
6369		 srl   $24,$24,7
6370		 andi  $24,$24,0x1C
6371		 addu  $24,$24,$21
6372		 sw    $2,0x20($24)
6373		 addiu $15,$15,-16
6374		 bgez  $15,3f
6375		 lhu   $24,0x00($23)    	 # Delay slot
6376		 j     MainExit
6377	3:
6378		 sll   $7,$24,2         	 # Delay slot
6379		 addu  $7,$7,$30
6380		 lw    $7,0x00($7)
6381		 jr    $7
6382		 nop                    	 # Delay slot
6383
6384OP0_2079:				#:
6385		 addiu $23,$23,2
6386
6387		 lhu   $14,0x00($23)
6388		 lhu   $25,0x02($23)
6389		 sll   $14,$14,16
6390		 or    $14,$14,$25
6391		 addiu $23,$23,4
6392		 lw    $25,0x84($21)
6393		 sw    $15,m68k_ICount
6394		 sw    $24,0x44($29)
6395		 or    $4,$0,$14
6396		 jalr  $25
6397		 sw    $23,0x4C($21)    	 # Delay slot
6398		 lw    $24,0x44($29)
6399		 lw    $15,m68k_ICount
6400		 srl   $24,$24,7
6401		 andi  $24,$24,0x1C
6402		 addu  $24,$24,$21
6403		 sw    $2,0x20($24)
6404		 addiu $15,$15,-20
6405		 bgez  $15,3f
6406		 lhu   $24,0x00($23)    	 # Delay slot
6407		 j     MainExit
6408	3:
6409		 sll   $7,$24,2         	 # Delay slot
6410		 addu  $7,$7,$30
6411		 lw    $7,0x00($7)
6412		 jr    $7
6413		 nop                    	 # Delay slot
6414
6415OP0_207a:				#:
6416		 addiu $23,$23,2
6417
6418		 lh    $7,0x00($23)
6419		 subu  $25,$23,$22
6420		 addu  $14,$25,$7       	 # Add Offset to PC
6421		 addiu $23,$23,2
6422		 lw    $25,0xA0($21)
6423		 sw    $15,m68k_ICount
6424		 sw    $24,0x44($29)
6425		 or    $4,$0,$14
6426		 jalr  $25
6427		 sw    $23,0x4C($21)    	 # Delay slot
6428		 lw    $24,0x44($29)
6429		 lw    $15,m68k_ICount
6430		 srl   $24,$24,7
6431		 andi  $24,$24,0x1C
6432		 addu  $24,$24,$21
6433		 sw    $2,0x20($24)
6434		 addiu $15,$15,-16
6435		 bgez  $15,3f
6436		 lhu   $24,0x00($23)    	 # Delay slot
6437		 j     MainExit
6438	3:
6439		 sll   $7,$24,2         	 # Delay slot
6440		 addu  $7,$7,$30
6441		 lw    $7,0x00($7)
6442		 jr    $7
6443		 nop                    	 # Delay slot
6444
6445OP0_207b:				#:
6446		 addiu $23,$23,2
6447
6448		 subu  $14,$23,$22       	 # Get PC
6449		 lhu   $7,0x00($23)
6450		 addiu $23,$23,2
6451		 seb   $6,$7
6452		 or    $25,$0,$7
6453		 srl   $7,$7,12
6454		 andi  $25,$25,0x0800
6455		 sll   $7,$7,2
6456		 addu  $7,$7,$21
6457		 bne   $25,$0,0f
6458		 lw    $25,0x00($7)      	 # Delay slot
6459		 seh   $25,$25
6460	0:
6461		 addu  $25,$14,$25
6462		 addu  $14,$25,$6
6463		 lw    $25,0xA0($21)
6464		 sw    $15,m68k_ICount
6465		 sw    $24,0x44($29)
6466		 or    $4,$0,$14
6467		 jalr  $25
6468		 sw    $23,0x4C($21)    	 # Delay slot
6469		 lw    $24,0x44($29)
6470		 lw    $15,m68k_ICount
6471		 srl   $24,$24,7
6472		 andi  $24,$24,0x1C
6473		 addu  $24,$24,$21
6474		 sw    $2,0x20($24)
6475		 addiu $15,$15,-18
6476		 bgez  $15,3f
6477		 lhu   $24,0x00($23)    	 # Delay slot
6478		 j     MainExit
6479	3:
6480		 sll   $7,$24,2         	 # Delay slot
6481		 addu  $7,$7,$30
6482		 lw    $7,0x00($7)
6483		 jr    $7
6484		 nop                    	 # Delay slot
6485
6486OP0_207c:				#:
6487		 addiu $23,$23,2
6488
6489		 lhu   $2,0x00($23)
6490		 lhu   $25,0x02($23)
6491		 sll   $2,$2,16
6492		 or    $2,$2,$25
6493		 addiu $23,$23,4
6494		 srl   $24,$24,7
6495		 andi  $24,$24,0x1C
6496		 addu  $24,$24,$21
6497		 sw    $2,0x20($24)
6498		 addiu $15,$15,-4
6499		 bgez  $15,3f
6500		 lhu   $24,0x00($23)    	 # Delay slot
6501		 j     MainExit
6502	3:
6503		 sll   $7,$24,2         	 # Delay slot
6504		 addu  $7,$7,$30
6505		 lw    $7,0x00($7)
6506		 jr    $7
6507		 nop                    	 # Delay slot
6508
6509OP0_2080:				#:
6510		 addiu $23,$23,2
6511
6512		 and   $8,$24,0x0f
6513		 sll   $8,$8,2
6514		 addu  $8,$8,$21
6515		 lw    $2,0x00($8)
6516		 and   $16,$0,$0        	 # Clear Carry
6517		 and   $17,$0,$0        	 # Clear Overflow
6518		 srl   $19,$2,31         	 # Set Sign
6519		 sltiu $18,$2,1         	 # Set Zero
6520		 srl   $24,$24,7
6521		 andi  $24,$24,0x1C
6522		 addu  $24,$24,$21
6523		 lw    $14,0x20($24)
6524		 lw    $25,0x90($21)
6525		 sw    $15,m68k_ICount
6526		 or    $5,$0,$2
6527		 or    $4,$0,$14
6528		 jalr  $25
6529		 sw    $23,0x4C($21)    	 # Delay slot
6530		 lw    $15,m68k_ICount
6531		 addiu $15,$15,-12
6532		 bgez  $15,3f
6533		 lhu   $24,0x00($23)    	 # Delay slot
6534		 j     MainExit
6535	3:
6536		 sll   $7,$24,2         	 # Delay slot
6537		 addu  $7,$7,$30
6538		 lw    $7,0x00($7)
6539		 jr    $7
6540		 nop                    	 # Delay slot
6541
6542OP0_2090:				#:
6543		 addiu $23,$23,2
6544
6545		 and   $8,$24,0x07
6546		 sll   $8,$8,2
6547		 addu  $8,$8,$21
6548		 lw    $14,0x20($8)
6549		 lw    $25,0x84($21)
6550		 sw    $15,m68k_ICount
6551		 sw    $24,0x44($29)
6552		 or    $4,$0,$14
6553		 jalr  $25
6554		 sw    $23,0x4C($21)    	 # Delay slot
6555		 lw    $24,0x44($29)
6556		 lw    $15,m68k_ICount
6557		 and   $16,$0,$0        	 # Clear Carry
6558		 and   $17,$0,$0        	 # Clear Overflow
6559		 srl   $19,$2,31         	 # Set Sign
6560		 sltiu $18,$2,1         	 # Set Zero
6561		 srl   $24,$24,7
6562		 andi  $24,$24,0x1C
6563		 addu  $24,$24,$21
6564		 lw    $14,0x20($24)
6565		 lw    $25,0x90($21)
6566		 sw    $15,m68k_ICount
6567		 or    $5,$0,$2
6568		 or    $4,$0,$14
6569		 jalr  $25
6570		 sw    $23,0x4C($21)    	 # Delay slot
6571		 lw    $15,m68k_ICount
6572		 addiu $15,$15,-20
6573		 bgez  $15,3f
6574		 lhu   $24,0x00($23)    	 # Delay slot
6575		 j     MainExit
6576	3:
6577		 sll   $7,$24,2         	 # Delay slot
6578		 addu  $7,$7,$30
6579		 lw    $7,0x00($7)
6580		 jr    $7
6581		 nop                    	 # Delay slot
6582
6583OP0_2098:				#:
6584		 addiu $23,$23,2
6585
6586		 and   $8,$24,0x07
6587		 sll   $8,$8,2
6588		 addu  $8,$8,$21
6589		 lw    $14,0x20($8)
6590		 addiu $25,$14,4
6591		 sw    $25,0x20($8)
6592		 lw    $25,0x84($21)
6593		 sw    $15,m68k_ICount
6594		 sw    $24,0x44($29)
6595		 or    $4,$0,$14
6596		 jalr  $25
6597		 sw    $23,0x4C($21)    	 # Delay slot
6598		 lw    $24,0x44($29)
6599		 lw    $15,m68k_ICount
6600		 and   $16,$0,$0        	 # Clear Carry
6601		 and   $17,$0,$0        	 # Clear Overflow
6602		 srl   $19,$2,31         	 # Set Sign
6603		 sltiu $18,$2,1         	 # Set Zero
6604		 srl   $24,$24,7
6605		 andi  $24,$24,0x1C
6606		 addu  $24,$24,$21
6607		 lw    $14,0x20($24)
6608		 lw    $25,0x90($21)
6609		 sw    $15,m68k_ICount
6610		 or    $5,$0,$2
6611		 or    $4,$0,$14
6612		 jalr  $25
6613		 sw    $23,0x4C($21)    	 # Delay slot
6614		 lw    $15,m68k_ICount
6615		 addiu $15,$15,-20
6616		 bgez  $15,3f
6617		 lhu   $24,0x00($23)    	 # Delay slot
6618		 j     MainExit
6619	3:
6620		 sll   $7,$24,2         	 # Delay slot
6621		 addu  $7,$7,$30
6622		 lw    $7,0x00($7)
6623		 jr    $7
6624		 nop                    	 # Delay slot
6625
6626OP0_20a0:				#:
6627		 addiu $23,$23,2
6628
6629		 and   $8,$24,0x07
6630		 sll   $8,$8,2
6631		 addu  $8,$8,$21
6632		 lw    $14,0x20($8)
6633		 addiu $14,$14,-4
6634		 sw    $14,0x20($8)
6635		 lw    $25,0x84($21)
6636		 sw    $15,m68k_ICount
6637		 sw    $24,0x44($29)
6638		 or    $4,$0,$14
6639		 jalr  $25
6640		 sw    $23,0x4C($21)    	 # Delay slot
6641		 lw    $24,0x44($29)
6642		 lw    $15,m68k_ICount
6643		 and   $16,$0,$0        	 # Clear Carry
6644		 and   $17,$0,$0        	 # Clear Overflow
6645		 srl   $19,$2,31         	 # Set Sign
6646		 sltiu $18,$2,1         	 # Set Zero
6647		 srl   $24,$24,7
6648		 andi  $24,$24,0x1C
6649		 addu  $24,$24,$21
6650		 lw    $14,0x20($24)
6651		 lw    $25,0x90($21)
6652		 sw    $15,m68k_ICount
6653		 or    $5,$0,$2
6654		 or    $4,$0,$14
6655		 jalr  $25
6656		 sw    $23,0x4C($21)    	 # Delay slot
6657		 lw    $15,m68k_ICount
6658		 addiu $15,$15,-22
6659		 bgez  $15,3f
6660		 lhu   $24,0x00($23)    	 # Delay slot
6661		 j     MainExit
6662	3:
6663		 sll   $7,$24,2         	 # Delay slot
6664		 addu  $7,$7,$30
6665		 lw    $7,0x00($7)
6666		 jr    $7
6667		 nop                    	 # Delay slot
6668
6669OP0_20a8:				#:
6670		 addiu $23,$23,2
6671
6672		 and   $8,$24,0x07
6673		 lh    $7,0x00($23)
6674		 sll   $8,$8,2
6675		 addu  $8,$8,$21
6676		 lw    $14,0x20($8)
6677		 addiu $23,$23,2
6678		 addu  $14,$14,$7
6679		 lw    $25,0x84($21)
6680		 sw    $15,m68k_ICount
6681		 sw    $24,0x44($29)
6682		 or    $4,$0,$14
6683		 jalr  $25
6684		 sw    $23,0x4C($21)    	 # Delay slot
6685		 lw    $24,0x44($29)
6686		 lw    $15,m68k_ICount
6687		 and   $16,$0,$0        	 # Clear Carry
6688		 and   $17,$0,$0        	 # Clear Overflow
6689		 srl   $19,$2,31         	 # Set Sign
6690		 sltiu $18,$2,1         	 # Set Zero
6691		 srl   $24,$24,7
6692		 andi  $24,$24,0x1C
6693		 addu  $24,$24,$21
6694		 lw    $14,0x20($24)
6695		 lw    $25,0x90($21)
6696		 sw    $15,m68k_ICount
6697		 or    $5,$0,$2
6698		 or    $4,$0,$14
6699		 jalr  $25
6700		 sw    $23,0x4C($21)    	 # Delay slot
6701		 lw    $15,m68k_ICount
6702		 addiu $15,$15,-24
6703		 bgez  $15,3f
6704		 lhu   $24,0x00($23)    	 # Delay slot
6705		 j     MainExit
6706	3:
6707		 sll   $7,$24,2         	 # Delay slot
6708		 addu  $7,$7,$30
6709		 lw    $7,0x00($7)
6710		 jr    $7
6711		 nop                    	 # Delay slot
6712
6713OP0_20b0:				#:
6714		 addiu $23,$23,2
6715
6716		 and   $8,$24,0x07
6717		 sll   $8,$8,2
6718		 addu  $8,$8,$21
6719		 lw    $14,0x20($8)
6720		 lhu   $7,0x00($23)
6721		 addiu $23,$23,2
6722		 seb   $6,$7
6723		 or    $25,$0,$7
6724		 srl   $7,$7,12
6725		 andi  $25,$25,0x0800
6726		 sll   $7,$7,2
6727		 addu  $7,$7,$21
6728		 bne   $25,$0,0f
6729		 lw    $25,0x00($7)      	 # Delay slot
6730		 seh   $25,$25
6731	0:
6732		 addu  $25,$14,$25
6733		 addu  $14,$25,$6
6734		 lw    $25,0x84($21)
6735		 sw    $15,m68k_ICount
6736		 sw    $24,0x44($29)
6737		 or    $4,$0,$14
6738		 jalr  $25
6739		 sw    $23,0x4C($21)    	 # Delay slot
6740		 lw    $24,0x44($29)
6741		 lw    $15,m68k_ICount
6742		 and   $16,$0,$0        	 # Clear Carry
6743		 and   $17,$0,$0        	 # Clear Overflow
6744		 srl   $19,$2,31         	 # Set Sign
6745		 sltiu $18,$2,1         	 # Set Zero
6746		 srl   $24,$24,7
6747		 andi  $24,$24,0x1C
6748		 addu  $24,$24,$21
6749		 lw    $14,0x20($24)
6750		 lw    $25,0x90($21)
6751		 sw    $15,m68k_ICount
6752		 or    $5,$0,$2
6753		 or    $4,$0,$14
6754		 jalr  $25
6755		 sw    $23,0x4C($21)    	 # Delay slot
6756		 lw    $15,m68k_ICount
6757		 addiu $15,$15,-26
6758		 bgez  $15,3f
6759		 lhu   $24,0x00($23)    	 # Delay slot
6760		 j     MainExit
6761	3:
6762		 sll   $7,$24,2         	 # Delay slot
6763		 addu  $7,$7,$30
6764		 lw    $7,0x00($7)
6765		 jr    $7
6766		 nop                    	 # Delay slot
6767
6768OP0_20b8:				#:
6769		 addiu $23,$23,2
6770
6771		 lh    $14,0x00($23)
6772		 addiu $23,$23,2
6773		 lw    $25,0x84($21)
6774		 sw    $15,m68k_ICount
6775		 sw    $24,0x44($29)
6776		 or    $4,$0,$14
6777		 jalr  $25
6778		 sw    $23,0x4C($21)    	 # Delay slot
6779		 lw    $24,0x44($29)
6780		 lw    $15,m68k_ICount
6781		 and   $16,$0,$0        	 # Clear Carry
6782		 and   $17,$0,$0        	 # Clear Overflow
6783		 srl   $19,$2,31         	 # Set Sign
6784		 sltiu $18,$2,1         	 # Set Zero
6785		 srl   $24,$24,7
6786		 andi  $24,$24,0x1C
6787		 addu  $24,$24,$21
6788		 lw    $14,0x20($24)
6789		 lw    $25,0x90($21)
6790		 sw    $15,m68k_ICount
6791		 or    $5,$0,$2
6792		 or    $4,$0,$14
6793		 jalr  $25
6794		 sw    $23,0x4C($21)    	 # Delay slot
6795		 lw    $15,m68k_ICount
6796		 addiu $15,$15,-24
6797		 bgez  $15,3f
6798		 lhu   $24,0x00($23)    	 # Delay slot
6799		 j     MainExit
6800	3:
6801		 sll   $7,$24,2         	 # Delay slot
6802		 addu  $7,$7,$30
6803		 lw    $7,0x00($7)
6804		 jr    $7
6805		 nop                    	 # Delay slot
6806
6807OP0_20b9:				#:
6808		 addiu $23,$23,2
6809
6810		 lhu   $14,0x00($23)
6811		 lhu   $25,0x02($23)
6812		 sll   $14,$14,16
6813		 or    $14,$14,$25
6814		 addiu $23,$23,4
6815		 lw    $25,0x84($21)
6816		 sw    $15,m68k_ICount
6817		 sw    $24,0x44($29)
6818		 or    $4,$0,$14
6819		 jalr  $25
6820		 sw    $23,0x4C($21)    	 # Delay slot
6821		 lw    $24,0x44($29)
6822		 lw    $15,m68k_ICount
6823		 and   $16,$0,$0        	 # Clear Carry
6824		 and   $17,$0,$0        	 # Clear Overflow
6825		 srl   $19,$2,31         	 # Set Sign
6826		 sltiu $18,$2,1         	 # Set Zero
6827		 srl   $24,$24,7
6828		 andi  $24,$24,0x1C
6829		 addu  $24,$24,$21
6830		 lw    $14,0x20($24)
6831		 lw    $25,0x90($21)
6832		 sw    $15,m68k_ICount
6833		 or    $5,$0,$2
6834		 or    $4,$0,$14
6835		 jalr  $25
6836		 sw    $23,0x4C($21)    	 # Delay slot
6837		 lw    $15,m68k_ICount
6838		 addiu $15,$15,-28
6839		 bgez  $15,3f
6840		 lhu   $24,0x00($23)    	 # Delay slot
6841		 j     MainExit
6842	3:
6843		 sll   $7,$24,2         	 # Delay slot
6844		 addu  $7,$7,$30
6845		 lw    $7,0x00($7)
6846		 jr    $7
6847		 nop                    	 # Delay slot
6848
6849OP0_20ba:				#:
6850		 addiu $23,$23,2
6851
6852		 lh    $7,0x00($23)
6853		 subu  $25,$23,$22
6854		 addu  $14,$25,$7       	 # Add Offset to PC
6855		 addiu $23,$23,2
6856		 lw    $25,0xA0($21)
6857		 sw    $15,m68k_ICount
6858		 sw    $24,0x44($29)
6859		 or    $4,$0,$14
6860		 jalr  $25
6861		 sw    $23,0x4C($21)    	 # Delay slot
6862		 lw    $24,0x44($29)
6863		 lw    $15,m68k_ICount
6864		 and   $16,$0,$0        	 # Clear Carry
6865		 and   $17,$0,$0        	 # Clear Overflow
6866		 srl   $19,$2,31         	 # Set Sign
6867		 sltiu $18,$2,1         	 # Set Zero
6868		 srl   $24,$24,7
6869		 andi  $24,$24,0x1C
6870		 addu  $24,$24,$21
6871		 lw    $14,0x20($24)
6872		 lw    $25,0x90($21)
6873		 sw    $15,m68k_ICount
6874		 or    $5,$0,$2
6875		 or    $4,$0,$14
6876		 jalr  $25
6877		 sw    $23,0x4C($21)    	 # Delay slot
6878		 lw    $15,m68k_ICount
6879		 addiu $15,$15,-24
6880		 bgez  $15,3f
6881		 lhu   $24,0x00($23)    	 # Delay slot
6882		 j     MainExit
6883	3:
6884		 sll   $7,$24,2         	 # Delay slot
6885		 addu  $7,$7,$30
6886		 lw    $7,0x00($7)
6887		 jr    $7
6888		 nop                    	 # Delay slot
6889
6890OP0_20bb:				#:
6891		 addiu $23,$23,2
6892
6893		 subu  $14,$23,$22       	 # Get PC
6894		 lhu   $7,0x00($23)
6895		 addiu $23,$23,2
6896		 seb   $6,$7
6897		 or    $25,$0,$7
6898		 srl   $7,$7,12
6899		 andi  $25,$25,0x0800
6900		 sll   $7,$7,2
6901		 addu  $7,$7,$21
6902		 bne   $25,$0,0f
6903		 lw    $25,0x00($7)      	 # Delay slot
6904		 seh   $25,$25
6905	0:
6906		 addu  $25,$14,$25
6907		 addu  $14,$25,$6
6908		 lw    $25,0xA0($21)
6909		 sw    $15,m68k_ICount
6910		 sw    $24,0x44($29)
6911		 or    $4,$0,$14
6912		 jalr  $25
6913		 sw    $23,0x4C($21)    	 # Delay slot
6914		 lw    $24,0x44($29)
6915		 lw    $15,m68k_ICount
6916		 and   $16,$0,$0        	 # Clear Carry
6917		 and   $17,$0,$0        	 # Clear Overflow
6918		 srl   $19,$2,31         	 # Set Sign
6919		 sltiu $18,$2,1         	 # Set Zero
6920		 srl   $24,$24,7
6921		 andi  $24,$24,0x1C
6922		 addu  $24,$24,$21
6923		 lw    $14,0x20($24)
6924		 lw    $25,0x90($21)
6925		 sw    $15,m68k_ICount
6926		 or    $5,$0,$2
6927		 or    $4,$0,$14
6928		 jalr  $25
6929		 sw    $23,0x4C($21)    	 # Delay slot
6930		 lw    $15,m68k_ICount
6931		 addiu $15,$15,-26
6932		 bgez  $15,3f
6933		 lhu   $24,0x00($23)    	 # Delay slot
6934		 j     MainExit
6935	3:
6936		 sll   $7,$24,2         	 # Delay slot
6937		 addu  $7,$7,$30
6938		 lw    $7,0x00($7)
6939		 jr    $7
6940		 nop                    	 # Delay slot
6941
6942OP0_20bc:				#:
6943		 addiu $23,$23,2
6944
6945		 lhu   $2,0x00($23)
6946		 lhu   $25,0x02($23)
6947		 sll   $2,$2,16
6948		 or    $2,$2,$25
6949		 addiu $23,$23,4
6950		 and   $16,$0,$0        	 # Clear Carry
6951		 and   $17,$0,$0        	 # Clear Overflow
6952		 srl   $19,$2,31         	 # Set Sign
6953		 sltiu $18,$2,1         	 # Set Zero
6954		 srl   $24,$24,7
6955		 andi  $24,$24,0x1C
6956		 addu  $24,$24,$21
6957		 lw    $14,0x20($24)
6958		 lw    $25,0x90($21)
6959		 sw    $15,m68k_ICount
6960		 or    $5,$0,$2
6961		 or    $4,$0,$14
6962		 jalr  $25
6963		 sw    $23,0x4C($21)    	 # Delay slot
6964		 lw    $15,m68k_ICount
6965		 addiu $15,$15,-12
6966		 bgez  $15,3f
6967		 lhu   $24,0x00($23)    	 # Delay slot
6968		 j     MainExit
6969	3:
6970		 sll   $7,$24,2         	 # Delay slot
6971		 addu  $7,$7,$30
6972		 lw    $7,0x00($7)
6973		 jr    $7
6974		 nop                    	 # Delay slot
6975
6976OP0_20c0:				#:
6977		 addiu $23,$23,2
6978
6979		 and   $8,$24,0x0f
6980		 sll   $8,$8,2
6981		 addu  $8,$8,$21
6982		 lw    $2,0x00($8)
6983		 and   $16,$0,$0        	 # Clear Carry
6984		 and   $17,$0,$0        	 # Clear Overflow
6985		 srl   $19,$2,31         	 # Set Sign
6986		 sltiu $18,$2,1         	 # Set Zero
6987		 srl   $24,$24,7
6988		 andi  $24,$24,0x1C
6989		 addu  $24,$24,$21
6990		 lw    $14,0x20($24)
6991		 addiu $25,$14,4
6992		 sw    $25,0x20($24)
6993		 lw    $25,0x90($21)
6994		 sw    $15,m68k_ICount
6995		 or    $5,$0,$2
6996		 or    $4,$0,$14
6997		 jalr  $25
6998		 sw    $23,0x4C($21)    	 # Delay slot
6999		 lw    $15,m68k_ICount
7000		 addiu $15,$15,-12
7001		 bgez  $15,3f
7002		 lhu   $24,0x00($23)    	 # Delay slot
7003		 j     MainExit
7004	3:
7005		 sll   $7,$24,2         	 # Delay slot
7006		 addu  $7,$7,$30
7007		 lw    $7,0x00($7)
7008		 jr    $7
7009		 nop                    	 # Delay slot
7010
7011OP0_20d0:				#:
7012		 addiu $23,$23,2
7013
7014		 and   $8,$24,0x07
7015		 sll   $8,$8,2
7016		 addu  $8,$8,$21
7017		 lw    $14,0x20($8)
7018		 lw    $25,0x84($21)
7019		 sw    $15,m68k_ICount
7020		 sw    $24,0x44($29)
7021		 or    $4,$0,$14
7022		 jalr  $25
7023		 sw    $23,0x4C($21)    	 # Delay slot
7024		 lw    $24,0x44($29)
7025		 lw    $15,m68k_ICount
7026		 and   $16,$0,$0        	 # Clear Carry
7027		 and   $17,$0,$0        	 # Clear Overflow
7028		 srl   $19,$2,31         	 # Set Sign
7029		 sltiu $18,$2,1         	 # Set Zero
7030		 srl   $24,$24,7
7031		 andi  $24,$24,0x1C
7032		 addu  $24,$24,$21
7033		 lw    $14,0x20($24)
7034		 addiu $25,$14,4
7035		 sw    $25,0x20($24)
7036		 lw    $25,0x90($21)
7037		 sw    $15,m68k_ICount
7038		 or    $5,$0,$2
7039		 or    $4,$0,$14
7040		 jalr  $25
7041		 sw    $23,0x4C($21)    	 # Delay slot
7042		 lw    $15,m68k_ICount
7043		 addiu $15,$15,-20
7044		 bgez  $15,3f
7045		 lhu   $24,0x00($23)    	 # Delay slot
7046		 j     MainExit
7047	3:
7048		 sll   $7,$24,2         	 # Delay slot
7049		 addu  $7,$7,$30
7050		 lw    $7,0x00($7)
7051		 jr    $7
7052		 nop                    	 # Delay slot
7053
7054OP0_20d8:				#:
7055		 addiu $23,$23,2
7056
7057		 and   $8,$24,0x07
7058		 sll   $8,$8,2
7059		 addu  $8,$8,$21
7060		 lw    $14,0x20($8)
7061		 addiu $25,$14,4
7062		 sw    $25,0x20($8)
7063		 lw    $25,0x84($21)
7064		 sw    $15,m68k_ICount
7065		 sw    $24,0x44($29)
7066		 or    $4,$0,$14
7067		 jalr  $25
7068		 sw    $23,0x4C($21)    	 # Delay slot
7069		 lw    $24,0x44($29)
7070		 lw    $15,m68k_ICount
7071		 and   $16,$0,$0        	 # Clear Carry
7072		 and   $17,$0,$0        	 # Clear Overflow
7073		 srl   $19,$2,31         	 # Set Sign
7074		 sltiu $18,$2,1         	 # Set Zero
7075		 srl   $24,$24,7
7076		 andi  $24,$24,0x1C
7077		 addu  $24,$24,$21
7078		 lw    $14,0x20($24)
7079		 addiu $25,$14,4
7080		 sw    $25,0x20($24)
7081		 lw    $25,0x90($21)
7082		 sw    $15,m68k_ICount
7083		 or    $5,$0,$2
7084		 or    $4,$0,$14
7085		 jalr  $25
7086		 sw    $23,0x4C($21)    	 # Delay slot
7087		 lw    $15,m68k_ICount
7088		 addiu $15,$15,-20
7089		 bgez  $15,3f
7090		 lhu   $24,0x00($23)    	 # Delay slot
7091		 j     MainExit
7092	3:
7093		 sll   $7,$24,2         	 # Delay slot
7094		 addu  $7,$7,$30
7095		 lw    $7,0x00($7)
7096		 jr    $7
7097		 nop                    	 # Delay slot
7098
7099OP0_20e0:				#:
7100		 addiu $23,$23,2
7101
7102		 and   $8,$24,0x07
7103		 sll   $8,$8,2
7104		 addu  $8,$8,$21
7105		 lw    $14,0x20($8)
7106		 addiu $14,$14,-4
7107		 sw    $14,0x20($8)
7108		 lw    $25,0x84($21)
7109		 sw    $15,m68k_ICount
7110		 sw    $24,0x44($29)
7111		 or    $4,$0,$14
7112		 jalr  $25
7113		 sw    $23,0x4C($21)    	 # Delay slot
7114		 lw    $24,0x44($29)
7115		 lw    $15,m68k_ICount
7116		 and   $16,$0,$0        	 # Clear Carry
7117		 and   $17,$0,$0        	 # Clear Overflow
7118		 srl   $19,$2,31         	 # Set Sign
7119		 sltiu $18,$2,1         	 # Set Zero
7120		 srl   $24,$24,7
7121		 andi  $24,$24,0x1C
7122		 addu  $24,$24,$21
7123		 lw    $14,0x20($24)
7124		 addiu $25,$14,4
7125		 sw    $25,0x20($24)
7126		 lw    $25,0x90($21)
7127		 sw    $15,m68k_ICount
7128		 or    $5,$0,$2
7129		 or    $4,$0,$14
7130		 jalr  $25
7131		 sw    $23,0x4C($21)    	 # Delay slot
7132		 lw    $15,m68k_ICount
7133		 addiu $15,$15,-22
7134		 bgez  $15,3f
7135		 lhu   $24,0x00($23)    	 # Delay slot
7136		 j     MainExit
7137	3:
7138		 sll   $7,$24,2         	 # Delay slot
7139		 addu  $7,$7,$30
7140		 lw    $7,0x00($7)
7141		 jr    $7
7142		 nop                    	 # Delay slot
7143
7144OP0_20e8:				#:
7145		 addiu $23,$23,2
7146
7147		 and   $8,$24,0x07
7148		 lh    $7,0x00($23)
7149		 sll   $8,$8,2
7150		 addu  $8,$8,$21
7151		 lw    $14,0x20($8)
7152		 addiu $23,$23,2
7153		 addu  $14,$14,$7
7154		 lw    $25,0x84($21)
7155		 sw    $15,m68k_ICount
7156		 sw    $24,0x44($29)
7157		 or    $4,$0,$14
7158		 jalr  $25
7159		 sw    $23,0x4C($21)    	 # Delay slot
7160		 lw    $24,0x44($29)
7161		 lw    $15,m68k_ICount
7162		 and   $16,$0,$0        	 # Clear Carry
7163		 and   $17,$0,$0        	 # Clear Overflow
7164		 srl   $19,$2,31         	 # Set Sign
7165		 sltiu $18,$2,1         	 # Set Zero
7166		 srl   $24,$24,7
7167		 andi  $24,$24,0x1C
7168		 addu  $24,$24,$21
7169		 lw    $14,0x20($24)
7170		 addiu $25,$14,4
7171		 sw    $25,0x20($24)
7172		 lw    $25,0x90($21)
7173		 sw    $15,m68k_ICount
7174		 or    $5,$0,$2
7175		 or    $4,$0,$14
7176		 jalr  $25
7177		 sw    $23,0x4C($21)    	 # Delay slot
7178		 lw    $15,m68k_ICount
7179		 addiu $15,$15,-24
7180		 bgez  $15,3f
7181		 lhu   $24,0x00($23)    	 # Delay slot
7182		 j     MainExit
7183	3:
7184		 sll   $7,$24,2         	 # Delay slot
7185		 addu  $7,$7,$30
7186		 lw    $7,0x00($7)
7187		 jr    $7
7188		 nop                    	 # Delay slot
7189
7190OP0_20f0:				#:
7191		 addiu $23,$23,2
7192
7193		 and   $8,$24,0x07
7194		 sll   $8,$8,2
7195		 addu  $8,$8,$21
7196		 lw    $14,0x20($8)
7197		 lhu   $7,0x00($23)
7198		 addiu $23,$23,2
7199		 seb   $6,$7
7200		 or    $25,$0,$7
7201		 srl   $7,$7,12
7202		 andi  $25,$25,0x0800
7203		 sll   $7,$7,2
7204		 addu  $7,$7,$21
7205		 bne   $25,$0,0f
7206		 lw    $25,0x00($7)      	 # Delay slot
7207		 seh   $25,$25
7208	0:
7209		 addu  $25,$14,$25
7210		 addu  $14,$25,$6
7211		 lw    $25,0x84($21)
7212		 sw    $15,m68k_ICount
7213		 sw    $24,0x44($29)
7214		 or    $4,$0,$14
7215		 jalr  $25
7216		 sw    $23,0x4C($21)    	 # Delay slot
7217		 lw    $24,0x44($29)
7218		 lw    $15,m68k_ICount
7219		 and   $16,$0,$0        	 # Clear Carry
7220		 and   $17,$0,$0        	 # Clear Overflow
7221		 srl   $19,$2,31         	 # Set Sign
7222		 sltiu $18,$2,1         	 # Set Zero
7223		 srl   $24,$24,7
7224		 andi  $24,$24,0x1C
7225		 addu  $24,$24,$21
7226		 lw    $14,0x20($24)
7227		 addiu $25,$14,4
7228		 sw    $25,0x20($24)
7229		 lw    $25,0x90($21)
7230		 sw    $15,m68k_ICount
7231		 or    $5,$0,$2
7232		 or    $4,$0,$14
7233		 jalr  $25
7234		 sw    $23,0x4C($21)    	 # Delay slot
7235		 lw    $15,m68k_ICount
7236		 addiu $15,$15,-26
7237		 bgez  $15,3f
7238		 lhu   $24,0x00($23)    	 # Delay slot
7239		 j     MainExit
7240	3:
7241		 sll   $7,$24,2         	 # Delay slot
7242		 addu  $7,$7,$30
7243		 lw    $7,0x00($7)
7244		 jr    $7
7245		 nop                    	 # Delay slot
7246
7247OP0_20f8:				#:
7248		 addiu $23,$23,2
7249
7250		 lh    $14,0x00($23)
7251		 addiu $23,$23,2
7252		 lw    $25,0x84($21)
7253		 sw    $15,m68k_ICount
7254		 sw    $24,0x44($29)
7255		 or    $4,$0,$14
7256		 jalr  $25
7257		 sw    $23,0x4C($21)    	 # Delay slot
7258		 lw    $24,0x44($29)
7259		 lw    $15,m68k_ICount
7260		 and   $16,$0,$0        	 # Clear Carry
7261		 and   $17,$0,$0        	 # Clear Overflow
7262		 srl   $19,$2,31         	 # Set Sign
7263		 sltiu $18,$2,1         	 # Set Zero
7264		 srl   $24,$24,7
7265		 andi  $24,$24,0x1C
7266		 addu  $24,$24,$21
7267		 lw    $14,0x20($24)
7268		 addiu $25,$14,4
7269		 sw    $25,0x20($24)
7270		 lw    $25,0x90($21)
7271		 sw    $15,m68k_ICount
7272		 or    $5,$0,$2
7273		 or    $4,$0,$14
7274		 jalr  $25
7275		 sw    $23,0x4C($21)    	 # Delay slot
7276		 lw    $15,m68k_ICount
7277		 addiu $15,$15,-24
7278		 bgez  $15,3f
7279		 lhu   $24,0x00($23)    	 # Delay slot
7280		 j     MainExit
7281	3:
7282		 sll   $7,$24,2         	 # Delay slot
7283		 addu  $7,$7,$30
7284		 lw    $7,0x00($7)
7285		 jr    $7
7286		 nop                    	 # Delay slot
7287
7288OP0_20f9:				#:
7289		 addiu $23,$23,2
7290
7291		 lhu   $14,0x00($23)
7292		 lhu   $25,0x02($23)
7293		 sll   $14,$14,16
7294		 or    $14,$14,$25
7295		 addiu $23,$23,4
7296		 lw    $25,0x84($21)
7297		 sw    $15,m68k_ICount
7298		 sw    $24,0x44($29)
7299		 or    $4,$0,$14
7300		 jalr  $25
7301		 sw    $23,0x4C($21)    	 # Delay slot
7302		 lw    $24,0x44($29)
7303		 lw    $15,m68k_ICount
7304		 and   $16,$0,$0        	 # Clear Carry
7305		 and   $17,$0,$0        	 # Clear Overflow
7306		 srl   $19,$2,31         	 # Set Sign
7307		 sltiu $18,$2,1         	 # Set Zero
7308		 srl   $24,$24,7
7309		 andi  $24,$24,0x1C
7310		 addu  $24,$24,$21
7311		 lw    $14,0x20($24)
7312		 addiu $25,$14,4
7313		 sw    $25,0x20($24)
7314		 lw    $25,0x90($21)
7315		 sw    $15,m68k_ICount
7316		 or    $5,$0,$2
7317		 or    $4,$0,$14
7318		 jalr  $25
7319		 sw    $23,0x4C($21)    	 # Delay slot
7320		 lw    $15,m68k_ICount
7321		 addiu $15,$15,-28
7322		 bgez  $15,3f
7323		 lhu   $24,0x00($23)    	 # Delay slot
7324		 j     MainExit
7325	3:
7326		 sll   $7,$24,2         	 # Delay slot
7327		 addu  $7,$7,$30
7328		 lw    $7,0x00($7)
7329		 jr    $7
7330		 nop                    	 # Delay slot
7331
7332OP0_20fa:				#:
7333		 addiu $23,$23,2
7334
7335		 lh    $7,0x00($23)
7336		 subu  $25,$23,$22
7337		 addu  $14,$25,$7       	 # Add Offset to PC
7338		 addiu $23,$23,2
7339		 lw    $25,0xA0($21)
7340		 sw    $15,m68k_ICount
7341		 sw    $24,0x44($29)
7342		 or    $4,$0,$14
7343		 jalr  $25
7344		 sw    $23,0x4C($21)    	 # Delay slot
7345		 lw    $24,0x44($29)
7346		 lw    $15,m68k_ICount
7347		 and   $16,$0,$0        	 # Clear Carry
7348		 and   $17,$0,$0        	 # Clear Overflow
7349		 srl   $19,$2,31         	 # Set Sign
7350		 sltiu $18,$2,1         	 # Set Zero
7351		 srl   $24,$24,7
7352		 andi  $24,$24,0x1C
7353		 addu  $24,$24,$21
7354		 lw    $14,0x20($24)
7355		 addiu $25,$14,4
7356		 sw    $25,0x20($24)
7357		 lw    $25,0x90($21)
7358		 sw    $15,m68k_ICount
7359		 or    $5,$0,$2
7360		 or    $4,$0,$14
7361		 jalr  $25
7362		 sw    $23,0x4C($21)    	 # Delay slot
7363		 lw    $15,m68k_ICount
7364		 addiu $15,$15,-24
7365		 bgez  $15,3f
7366		 lhu   $24,0x00($23)    	 # Delay slot
7367		 j     MainExit
7368	3:
7369		 sll   $7,$24,2         	 # Delay slot
7370		 addu  $7,$7,$30
7371		 lw    $7,0x00($7)
7372		 jr    $7
7373		 nop                    	 # Delay slot
7374
7375OP0_20fb:				#:
7376		 addiu $23,$23,2
7377
7378		 subu  $14,$23,$22       	 # Get PC
7379		 lhu   $7,0x00($23)
7380		 addiu $23,$23,2
7381		 seb   $6,$7
7382		 or    $25,$0,$7
7383		 srl   $7,$7,12
7384		 andi  $25,$25,0x0800
7385		 sll   $7,$7,2
7386		 addu  $7,$7,$21
7387		 bne   $25,$0,0f
7388		 lw    $25,0x00($7)      	 # Delay slot
7389		 seh   $25,$25
7390	0:
7391		 addu  $25,$14,$25
7392		 addu  $14,$25,$6
7393		 lw    $25,0xA0($21)
7394		 sw    $15,m68k_ICount
7395		 sw    $24,0x44($29)
7396		 or    $4,$0,$14
7397		 jalr  $25
7398		 sw    $23,0x4C($21)    	 # Delay slot
7399		 lw    $24,0x44($29)
7400		 lw    $15,m68k_ICount
7401		 and   $16,$0,$0        	 # Clear Carry
7402		 and   $17,$0,$0        	 # Clear Overflow
7403		 srl   $19,$2,31         	 # Set Sign
7404		 sltiu $18,$2,1         	 # Set Zero
7405		 srl   $24,$24,7
7406		 andi  $24,$24,0x1C
7407		 addu  $24,$24,$21
7408		 lw    $14,0x20($24)
7409		 addiu $25,$14,4
7410		 sw    $25,0x20($24)
7411		 lw    $25,0x90($21)
7412		 sw    $15,m68k_ICount
7413		 or    $5,$0,$2
7414		 or    $4,$0,$14
7415		 jalr  $25
7416		 sw    $23,0x4C($21)    	 # Delay slot
7417		 lw    $15,m68k_ICount
7418		 addiu $15,$15,-26
7419		 bgez  $15,3f
7420		 lhu   $24,0x00($23)    	 # Delay slot
7421		 j     MainExit
7422	3:
7423		 sll   $7,$24,2         	 # Delay slot
7424		 addu  $7,$7,$30
7425		 lw    $7,0x00($7)
7426		 jr    $7
7427		 nop                    	 # Delay slot
7428
7429OP0_20fc:				#:
7430		 addiu $23,$23,2
7431
7432		 lhu   $2,0x00($23)
7433		 lhu   $25,0x02($23)
7434		 sll   $2,$2,16
7435		 or    $2,$2,$25
7436		 addiu $23,$23,4
7437		 and   $16,$0,$0        	 # Clear Carry
7438		 and   $17,$0,$0        	 # Clear Overflow
7439		 srl   $19,$2,31         	 # Set Sign
7440		 sltiu $18,$2,1         	 # Set Zero
7441		 srl   $24,$24,7
7442		 andi  $24,$24,0x1C
7443		 addu  $24,$24,$21
7444		 lw    $14,0x20($24)
7445		 addiu $25,$14,4
7446		 sw    $25,0x20($24)
7447		 lw    $25,0x90($21)
7448		 sw    $15,m68k_ICount
7449		 or    $5,$0,$2
7450		 or    $4,$0,$14
7451		 jalr  $25
7452		 sw    $23,0x4C($21)    	 # Delay slot
7453		 lw    $15,m68k_ICount
7454		 addiu $15,$15,-12
7455		 bgez  $15,3f
7456		 lhu   $24,0x00($23)    	 # Delay slot
7457		 j     MainExit
7458	3:
7459		 sll   $7,$24,2         	 # Delay slot
7460		 addu  $7,$7,$30
7461		 lw    $7,0x00($7)
7462		 jr    $7
7463		 nop                    	 # Delay slot
7464
7465OP0_2100:				#:
7466		 addiu $23,$23,2
7467
7468		 and   $8,$24,0x0f
7469		 sll   $8,$8,2
7470		 addu  $8,$8,$21
7471		 lw    $2,0x00($8)
7472		 and   $16,$0,$0        	 # Clear Carry
7473		 and   $17,$0,$0        	 # Clear Overflow
7474		 srl   $19,$2,31         	 # Set Sign
7475		 sltiu $18,$2,1         	 # Set Zero
7476		 srl   $24,$24,7
7477		 andi  $24,$24,0x1C
7478		 addu  $24,$24,$21
7479		 lw    $14,0x20($24)
7480		 addiu $14,$14,-4
7481		 sw    $14,0x20($24)
7482		 lw    $25,0x8C($21)
7483		 sw    $15,m68k_ICount
7484		 sw    $2,0x44($29)
7485		 sw    $14,0x40($29)
7486		 addiu $14,$14,2
7487		 or    $5,$0,$2
7488		 or    $4,$0,$14
7489		 jalr  $25
7490		 sw    $23,0x4C($21)    	 # Delay slot
7491		 lw    $25,0x8C($21)
7492		 lw    $4,0x40($29)
7493		 lw    $5,0x44($29)
7494		 jalr  $25
7495		 srl   $5,$5,16         	 # Delay slot
7496		 lw    $15,m68k_ICount
7497		 addiu $15,$15,-14
7498		 bgez  $15,3f
7499		 lhu   $24,0x00($23)    	 # Delay slot
7500		 j     MainExit
7501	3:
7502		 sll   $7,$24,2         	 # Delay slot
7503		 addu  $7,$7,$30
7504		 lw    $7,0x00($7)
7505		 jr    $7
7506		 nop                    	 # Delay slot
7507
7508OP0_2110:				#:
7509		 addiu $23,$23,2
7510
7511		 and   $8,$24,0x07
7512		 sll   $8,$8,2
7513		 addu  $8,$8,$21
7514		 lw    $14,0x20($8)
7515		 lw    $25,0x84($21)
7516		 sw    $15,m68k_ICount
7517		 sw    $24,0x44($29)
7518		 or    $4,$0,$14
7519		 jalr  $25
7520		 sw    $23,0x4C($21)    	 # Delay slot
7521		 lw    $24,0x44($29)
7522		 lw    $15,m68k_ICount
7523		 and   $16,$0,$0        	 # Clear Carry
7524		 and   $17,$0,$0        	 # Clear Overflow
7525		 srl   $19,$2,31         	 # Set Sign
7526		 sltiu $18,$2,1         	 # Set Zero
7527		 srl   $24,$24,7
7528		 andi  $24,$24,0x1C
7529		 addu  $24,$24,$21
7530		 lw    $14,0x20($24)
7531		 addiu $14,$14,-4
7532		 sw    $14,0x20($24)
7533		 lw    $25,0x8C($21)
7534		 sw    $15,m68k_ICount
7535		 sw    $2,0x44($29)
7536		 sw    $14,0x40($29)
7537		 addiu $14,$14,2
7538		 or    $5,$0,$2
7539		 or    $4,$0,$14
7540		 jalr  $25
7541		 sw    $23,0x4C($21)    	 # Delay slot
7542		 lw    $25,0x8C($21)
7543		 lw    $4,0x40($29)
7544		 lw    $5,0x44($29)
7545		 jalr  $25
7546		 srl   $5,$5,16         	 # Delay slot
7547		 lw    $15,m68k_ICount
7548		 addiu $15,$15,-22
7549		 bgez  $15,3f
7550		 lhu   $24,0x00($23)    	 # Delay slot
7551		 j     MainExit
7552	3:
7553		 sll   $7,$24,2         	 # Delay slot
7554		 addu  $7,$7,$30
7555		 lw    $7,0x00($7)
7556		 jr    $7
7557		 nop                    	 # Delay slot
7558
7559OP0_2118:				#:
7560		 addiu $23,$23,2
7561
7562		 and   $8,$24,0x07
7563		 sll   $8,$8,2
7564		 addu  $8,$8,$21
7565		 lw    $14,0x20($8)
7566		 addiu $25,$14,4
7567		 sw    $25,0x20($8)
7568		 lw    $25,0x84($21)
7569		 sw    $15,m68k_ICount
7570		 sw    $24,0x44($29)
7571		 or    $4,$0,$14
7572		 jalr  $25
7573		 sw    $23,0x4C($21)    	 # Delay slot
7574		 lw    $24,0x44($29)
7575		 lw    $15,m68k_ICount
7576		 and   $16,$0,$0        	 # Clear Carry
7577		 and   $17,$0,$0        	 # Clear Overflow
7578		 srl   $19,$2,31         	 # Set Sign
7579		 sltiu $18,$2,1         	 # Set Zero
7580		 srl   $24,$24,7
7581		 andi  $24,$24,0x1C
7582		 addu  $24,$24,$21
7583		 lw    $14,0x20($24)
7584		 addiu $14,$14,-4
7585		 sw    $14,0x20($24)
7586		 lw    $25,0x8C($21)
7587		 sw    $15,m68k_ICount
7588		 sw    $2,0x44($29)
7589		 sw    $14,0x40($29)
7590		 addiu $14,$14,2
7591		 or    $5,$0,$2
7592		 or    $4,$0,$14
7593		 jalr  $25
7594		 sw    $23,0x4C($21)    	 # Delay slot
7595		 lw    $25,0x8C($21)
7596		 lw    $4,0x40($29)
7597		 lw    $5,0x44($29)
7598		 jalr  $25
7599		 srl   $5,$5,16         	 # Delay slot
7600		 lw    $15,m68k_ICount
7601		 addiu $15,$15,-22
7602		 bgez  $15,3f
7603		 lhu   $24,0x00($23)    	 # Delay slot
7604		 j     MainExit
7605	3:
7606		 sll   $7,$24,2         	 # Delay slot
7607		 addu  $7,$7,$30
7608		 lw    $7,0x00($7)
7609		 jr    $7
7610		 nop                    	 # Delay slot
7611
7612OP0_2120:				#:
7613		 addiu $23,$23,2
7614
7615		 and   $8,$24,0x07
7616		 sll   $8,$8,2
7617		 addu  $8,$8,$21
7618		 lw    $14,0x20($8)
7619		 addiu $14,$14,-4
7620		 sw    $14,0x20($8)
7621		 lw    $25,0x84($21)
7622		 sw    $15,m68k_ICount
7623		 sw    $24,0x44($29)
7624		 or    $4,$0,$14
7625		 jalr  $25
7626		 sw    $23,0x4C($21)    	 # Delay slot
7627		 lw    $24,0x44($29)
7628		 lw    $15,m68k_ICount
7629		 and   $16,$0,$0        	 # Clear Carry
7630		 and   $17,$0,$0        	 # Clear Overflow
7631		 srl   $19,$2,31         	 # Set Sign
7632		 sltiu $18,$2,1         	 # Set Zero
7633		 srl   $24,$24,7
7634		 andi  $24,$24,0x1C
7635		 addu  $24,$24,$21
7636		 lw    $14,0x20($24)
7637		 addiu $14,$14,-4
7638		 sw    $14,0x20($24)
7639		 lw    $25,0x8C($21)
7640		 sw    $15,m68k_ICount
7641		 sw    $2,0x44($29)
7642		 sw    $14,0x40($29)
7643		 addiu $14,$14,2
7644		 or    $5,$0,$2
7645		 or    $4,$0,$14
7646		 jalr  $25
7647		 sw    $23,0x4C($21)    	 # Delay slot
7648		 lw    $25,0x8C($21)
7649		 lw    $4,0x40($29)
7650		 lw    $5,0x44($29)
7651		 jalr  $25
7652		 srl   $5,$5,16         	 # Delay slot
7653		 lw    $15,m68k_ICount
7654		 addiu $15,$15,-24
7655		 bgez  $15,3f
7656		 lhu   $24,0x00($23)    	 # Delay slot
7657		 j     MainExit
7658	3:
7659		 sll   $7,$24,2         	 # Delay slot
7660		 addu  $7,$7,$30
7661		 lw    $7,0x00($7)
7662		 jr    $7
7663		 nop                    	 # Delay slot
7664
7665OP0_2128:				#:
7666		 addiu $23,$23,2
7667
7668		 and   $8,$24,0x07
7669		 lh    $7,0x00($23)
7670		 sll   $8,$8,2
7671		 addu  $8,$8,$21
7672		 lw    $14,0x20($8)
7673		 addiu $23,$23,2
7674		 addu  $14,$14,$7
7675		 lw    $25,0x84($21)
7676		 sw    $15,m68k_ICount
7677		 sw    $24,0x44($29)
7678		 or    $4,$0,$14
7679		 jalr  $25
7680		 sw    $23,0x4C($21)    	 # Delay slot
7681		 lw    $24,0x44($29)
7682		 lw    $15,m68k_ICount
7683		 and   $16,$0,$0        	 # Clear Carry
7684		 and   $17,$0,$0        	 # Clear Overflow
7685		 srl   $19,$2,31         	 # Set Sign
7686		 sltiu $18,$2,1         	 # Set Zero
7687		 srl   $24,$24,7
7688		 andi  $24,$24,0x1C
7689		 addu  $24,$24,$21
7690		 lw    $14,0x20($24)
7691		 addiu $14,$14,-4
7692		 sw    $14,0x20($24)
7693		 lw    $25,0x8C($21)
7694		 sw    $15,m68k_ICount
7695		 sw    $2,0x44($29)
7696		 sw    $14,0x40($29)
7697		 addiu $14,$14,2
7698		 or    $5,$0,$2
7699		 or    $4,$0,$14
7700		 jalr  $25
7701		 sw    $23,0x4C($21)    	 # Delay slot
7702		 lw    $25,0x8C($21)
7703		 lw    $4,0x40($29)
7704		 lw    $5,0x44($29)
7705		 jalr  $25
7706		 srl   $5,$5,16         	 # Delay slot
7707		 lw    $15,m68k_ICount
7708		 addiu $15,$15,-26
7709		 bgez  $15,3f
7710		 lhu   $24,0x00($23)    	 # Delay slot
7711		 j     MainExit
7712	3:
7713		 sll   $7,$24,2         	 # Delay slot
7714		 addu  $7,$7,$30
7715		 lw    $7,0x00($7)
7716		 jr    $7
7717		 nop                    	 # Delay slot
7718
7719OP0_2130:				#:
7720		 addiu $23,$23,2
7721
7722		 and   $8,$24,0x07
7723		 sll   $8,$8,2
7724		 addu  $8,$8,$21
7725		 lw    $14,0x20($8)
7726		 lhu   $7,0x00($23)
7727		 addiu $23,$23,2
7728		 seb   $6,$7
7729		 or    $25,$0,$7
7730		 srl   $7,$7,12
7731		 andi  $25,$25,0x0800
7732		 sll   $7,$7,2
7733		 addu  $7,$7,$21
7734		 bne   $25,$0,0f
7735		 lw    $25,0x00($7)      	 # Delay slot
7736		 seh   $25,$25
7737	0:
7738		 addu  $25,$14,$25
7739		 addu  $14,$25,$6
7740		 lw    $25,0x84($21)
7741		 sw    $15,m68k_ICount
7742		 sw    $24,0x44($29)
7743		 or    $4,$0,$14
7744		 jalr  $25
7745		 sw    $23,0x4C($21)    	 # Delay slot
7746		 lw    $24,0x44($29)
7747		 lw    $15,m68k_ICount
7748		 and   $16,$0,$0        	 # Clear Carry
7749		 and   $17,$0,$0        	 # Clear Overflow
7750		 srl   $19,$2,31         	 # Set Sign
7751		 sltiu $18,$2,1         	 # Set Zero
7752		 srl   $24,$24,7
7753		 andi  $24,$24,0x1C
7754		 addu  $24,$24,$21
7755		 lw    $14,0x20($24)
7756		 addiu $14,$14,-4
7757		 sw    $14,0x20($24)
7758		 lw    $25,0x8C($21)
7759		 sw    $15,m68k_ICount
7760		 sw    $2,0x44($29)
7761		 sw    $14,0x40($29)
7762		 addiu $14,$14,2
7763		 or    $5,$0,$2
7764		 or    $4,$0,$14
7765		 jalr  $25
7766		 sw    $23,0x4C($21)    	 # Delay slot
7767		 lw    $25,0x8C($21)
7768		 lw    $4,0x40($29)
7769		 lw    $5,0x44($29)
7770		 jalr  $25
7771		 srl   $5,$5,16         	 # Delay slot
7772		 lw    $15,m68k_ICount
7773		 addiu $15,$15,-28
7774		 bgez  $15,3f
7775		 lhu   $24,0x00($23)    	 # Delay slot
7776		 j     MainExit
7777	3:
7778		 sll   $7,$24,2         	 # Delay slot
7779		 addu  $7,$7,$30
7780		 lw    $7,0x00($7)
7781		 jr    $7
7782		 nop                    	 # Delay slot
7783
7784OP0_2138:				#:
7785		 addiu $23,$23,2
7786
7787		 lh    $14,0x00($23)
7788		 addiu $23,$23,2
7789		 lw    $25,0x84($21)
7790		 sw    $15,m68k_ICount
7791		 sw    $24,0x44($29)
7792		 or    $4,$0,$14
7793		 jalr  $25
7794		 sw    $23,0x4C($21)    	 # Delay slot
7795		 lw    $24,0x44($29)
7796		 lw    $15,m68k_ICount
7797		 and   $16,$0,$0        	 # Clear Carry
7798		 and   $17,$0,$0        	 # Clear Overflow
7799		 srl   $19,$2,31         	 # Set Sign
7800		 sltiu $18,$2,1         	 # Set Zero
7801		 srl   $24,$24,7
7802		 andi  $24,$24,0x1C
7803		 addu  $24,$24,$21
7804		 lw    $14,0x20($24)
7805		 addiu $14,$14,-4
7806		 sw    $14,0x20($24)
7807		 lw    $25,0x8C($21)
7808		 sw    $15,m68k_ICount
7809		 sw    $2,0x44($29)
7810		 sw    $14,0x40($29)
7811		 addiu $14,$14,2
7812		 or    $5,$0,$2
7813		 or    $4,$0,$14
7814		 jalr  $25
7815		 sw    $23,0x4C($21)    	 # Delay slot
7816		 lw    $25,0x8C($21)
7817		 lw    $4,0x40($29)
7818		 lw    $5,0x44($29)
7819		 jalr  $25
7820		 srl   $5,$5,16         	 # Delay slot
7821		 lw    $15,m68k_ICount
7822		 addiu $15,$15,-26
7823		 bgez  $15,3f
7824		 lhu   $24,0x00($23)    	 # Delay slot
7825		 j     MainExit
7826	3:
7827		 sll   $7,$24,2         	 # Delay slot
7828		 addu  $7,$7,$30
7829		 lw    $7,0x00($7)
7830		 jr    $7
7831		 nop                    	 # Delay slot
7832
7833OP0_2139:				#:
7834		 addiu $23,$23,2
7835
7836		 lhu   $14,0x00($23)
7837		 lhu   $25,0x02($23)
7838		 sll   $14,$14,16
7839		 or    $14,$14,$25
7840		 addiu $23,$23,4
7841		 lw    $25,0x84($21)
7842		 sw    $15,m68k_ICount
7843		 sw    $24,0x44($29)
7844		 or    $4,$0,$14
7845		 jalr  $25
7846		 sw    $23,0x4C($21)    	 # Delay slot
7847		 lw    $24,0x44($29)
7848		 lw    $15,m68k_ICount
7849		 and   $16,$0,$0        	 # Clear Carry
7850		 and   $17,$0,$0        	 # Clear Overflow
7851		 srl   $19,$2,31         	 # Set Sign
7852		 sltiu $18,$2,1         	 # Set Zero
7853		 srl   $24,$24,7
7854		 andi  $24,$24,0x1C
7855		 addu  $24,$24,$21
7856		 lw    $14,0x20($24)
7857		 addiu $14,$14,-4
7858		 sw    $14,0x20($24)
7859		 lw    $25,0x8C($21)
7860		 sw    $15,m68k_ICount
7861		 sw    $2,0x44($29)
7862		 sw    $14,0x40($29)
7863		 addiu $14,$14,2
7864		 or    $5,$0,$2
7865		 or    $4,$0,$14
7866		 jalr  $25
7867		 sw    $23,0x4C($21)    	 # Delay slot
7868		 lw    $25,0x8C($21)
7869		 lw    $4,0x40($29)
7870		 lw    $5,0x44($29)
7871		 jalr  $25
7872		 srl   $5,$5,16         	 # Delay slot
7873		 lw    $15,m68k_ICount
7874		 addiu $15,$15,-30
7875		 bgez  $15,3f
7876		 lhu   $24,0x00($23)    	 # Delay slot
7877		 j     MainExit
7878	3:
7879		 sll   $7,$24,2         	 # Delay slot
7880		 addu  $7,$7,$30
7881		 lw    $7,0x00($7)
7882		 jr    $7
7883		 nop                    	 # Delay slot
7884
7885OP0_213a:				#:
7886		 addiu $23,$23,2
7887
7888		 lh    $7,0x00($23)
7889		 subu  $25,$23,$22
7890		 addu  $14,$25,$7       	 # Add Offset to PC
7891		 addiu $23,$23,2
7892		 lw    $25,0xA0($21)
7893		 sw    $15,m68k_ICount
7894		 sw    $24,0x44($29)
7895		 or    $4,$0,$14
7896		 jalr  $25
7897		 sw    $23,0x4C($21)    	 # Delay slot
7898		 lw    $24,0x44($29)
7899		 lw    $15,m68k_ICount
7900		 and   $16,$0,$0        	 # Clear Carry
7901		 and   $17,$0,$0        	 # Clear Overflow
7902		 srl   $19,$2,31         	 # Set Sign
7903		 sltiu $18,$2,1         	 # Set Zero
7904		 srl   $24,$24,7
7905		 andi  $24,$24,0x1C
7906		 addu  $24,$24,$21
7907		 lw    $14,0x20($24)
7908		 addiu $14,$14,-4
7909		 sw    $14,0x20($24)
7910		 lw    $25,0x8C($21)
7911		 sw    $15,m68k_ICount
7912		 sw    $2,0x44($29)
7913		 sw    $14,0x40($29)
7914		 addiu $14,$14,2
7915		 or    $5,$0,$2
7916		 or    $4,$0,$14
7917		 jalr  $25
7918		 sw    $23,0x4C($21)    	 # Delay slot
7919		 lw    $25,0x8C($21)
7920		 lw    $4,0x40($29)
7921		 lw    $5,0x44($29)
7922		 jalr  $25
7923		 srl   $5,$5,16         	 # Delay slot
7924		 lw    $15,m68k_ICount
7925		 addiu $15,$15,-26
7926		 bgez  $15,3f
7927		 lhu   $24,0x00($23)    	 # Delay slot
7928		 j     MainExit
7929	3:
7930		 sll   $7,$24,2         	 # Delay slot
7931		 addu  $7,$7,$30
7932		 lw    $7,0x00($7)
7933		 jr    $7
7934		 nop                    	 # Delay slot
7935
7936OP0_213b:				#:
7937		 addiu $23,$23,2
7938
7939		 subu  $14,$23,$22       	 # Get PC
7940		 lhu   $7,0x00($23)
7941		 addiu $23,$23,2
7942		 seb   $6,$7
7943		 or    $25,$0,$7
7944		 srl   $7,$7,12
7945		 andi  $25,$25,0x0800
7946		 sll   $7,$7,2
7947		 addu  $7,$7,$21
7948		 bne   $25,$0,0f
7949		 lw    $25,0x00($7)      	 # Delay slot
7950		 seh   $25,$25
7951	0:
7952		 addu  $25,$14,$25
7953		 addu  $14,$25,$6
7954		 lw    $25,0xA0($21)
7955		 sw    $15,m68k_ICount
7956		 sw    $24,0x44($29)
7957		 or    $4,$0,$14
7958		 jalr  $25
7959		 sw    $23,0x4C($21)    	 # Delay slot
7960		 lw    $24,0x44($29)
7961		 lw    $15,m68k_ICount
7962		 and   $16,$0,$0        	 # Clear Carry
7963		 and   $17,$0,$0        	 # Clear Overflow
7964		 srl   $19,$2,31         	 # Set Sign
7965		 sltiu $18,$2,1         	 # Set Zero
7966		 srl   $24,$24,7
7967		 andi  $24,$24,0x1C
7968		 addu  $24,$24,$21
7969		 lw    $14,0x20($24)
7970		 addiu $14,$14,-4
7971		 sw    $14,0x20($24)
7972		 lw    $25,0x8C($21)
7973		 sw    $15,m68k_ICount
7974		 sw    $2,0x44($29)
7975		 sw    $14,0x40($29)
7976		 addiu $14,$14,2
7977		 or    $5,$0,$2
7978		 or    $4,$0,$14
7979		 jalr  $25
7980		 sw    $23,0x4C($21)    	 # Delay slot
7981		 lw    $25,0x8C($21)
7982		 lw    $4,0x40($29)
7983		 lw    $5,0x44($29)
7984		 jalr  $25
7985		 srl   $5,$5,16         	 # Delay slot
7986		 lw    $15,m68k_ICount
7987		 addiu $15,$15,-28
7988		 bgez  $15,3f
7989		 lhu   $24,0x00($23)    	 # Delay slot
7990		 j     MainExit
7991	3:
7992		 sll   $7,$24,2         	 # Delay slot
7993		 addu  $7,$7,$30
7994		 lw    $7,0x00($7)
7995		 jr    $7
7996		 nop                    	 # Delay slot
7997
7998OP0_213c:				#:
7999		 addiu $23,$23,2
8000
8001		 lhu   $2,0x00($23)
8002		 lhu   $25,0x02($23)
8003		 sll   $2,$2,16
8004		 or    $2,$2,$25
8005		 addiu $23,$23,4
8006		 and   $16,$0,$0        	 # Clear Carry
8007		 and   $17,$0,$0        	 # Clear Overflow
8008		 srl   $19,$2,31         	 # Set Sign
8009		 sltiu $18,$2,1         	 # Set Zero
8010		 srl   $24,$24,7
8011		 andi  $24,$24,0x1C
8012		 addu  $24,$24,$21
8013		 lw    $14,0x20($24)
8014		 addiu $14,$14,-4
8015		 sw    $14,0x20($24)
8016		 lw    $25,0x8C($21)
8017		 sw    $15,m68k_ICount
8018		 sw    $2,0x44($29)
8019		 sw    $14,0x40($29)
8020		 addiu $14,$14,2
8021		 or    $5,$0,$2
8022		 or    $4,$0,$14
8023		 jalr  $25
8024		 sw    $23,0x4C($21)    	 # Delay slot
8025		 lw    $25,0x8C($21)
8026		 lw    $4,0x40($29)
8027		 lw    $5,0x44($29)
8028		 jalr  $25
8029		 srl   $5,$5,16         	 # Delay slot
8030		 lw    $15,m68k_ICount
8031		 addiu $15,$15,-14
8032		 bgez  $15,3f
8033		 lhu   $24,0x00($23)    	 # Delay slot
8034		 j     MainExit
8035	3:
8036		 sll   $7,$24,2         	 # Delay slot
8037		 addu  $7,$7,$30
8038		 lw    $7,0x00($7)
8039		 jr    $7
8040		 nop                    	 # Delay slot
8041
8042OP0_2140:				#:
8043		 addiu $23,$23,2
8044
8045		 and   $8,$24,0x0f
8046		 sll   $8,$8,2
8047		 addu  $8,$8,$21
8048		 lw    $2,0x00($8)
8049		 and   $16,$0,$0        	 # Clear Carry
8050		 and   $17,$0,$0        	 # Clear Overflow
8051		 srl   $19,$2,31         	 # Set Sign
8052		 sltiu $18,$2,1         	 # Set Zero
8053		 srl   $24,$24,7
8054		 andi  $24,$24,0x1C
8055		 lh    $7,0x00($23)
8056		 addu  $24,$24,$21
8057		 lw    $14,0x20($24)
8058		 addiu $23,$23,2
8059		 addu  $14,$14,$7
8060		 lw    $25,0x90($21)
8061		 sw    $15,m68k_ICount
8062		 or    $5,$0,$2
8063		 or    $4,$0,$14
8064		 jalr  $25
8065		 sw    $23,0x4C($21)    	 # Delay slot
8066		 lw    $15,m68k_ICount
8067		 addiu $15,$15,-16
8068		 bgez  $15,3f
8069		 lhu   $24,0x00($23)    	 # Delay slot
8070		 j     MainExit
8071	3:
8072		 sll   $7,$24,2         	 # Delay slot
8073		 addu  $7,$7,$30
8074		 lw    $7,0x00($7)
8075		 jr    $7
8076		 nop                    	 # Delay slot
8077
8078OP0_2150:				#:
8079		 addiu $23,$23,2
8080
8081		 and   $8,$24,0x07
8082		 sll   $8,$8,2
8083		 addu  $8,$8,$21
8084		 lw    $14,0x20($8)
8085		 lw    $25,0x84($21)
8086		 sw    $15,m68k_ICount
8087		 sw    $24,0x44($29)
8088		 or    $4,$0,$14
8089		 jalr  $25
8090		 sw    $23,0x4C($21)    	 # Delay slot
8091		 lw    $24,0x44($29)
8092		 lw    $15,m68k_ICount
8093		 and   $16,$0,$0        	 # Clear Carry
8094		 and   $17,$0,$0        	 # Clear Overflow
8095		 srl   $19,$2,31         	 # Set Sign
8096		 sltiu $18,$2,1         	 # Set Zero
8097		 srl   $24,$24,7
8098		 andi  $24,$24,0x1C
8099		 lh    $7,0x00($23)
8100		 addu  $24,$24,$21
8101		 lw    $14,0x20($24)
8102		 addiu $23,$23,2
8103		 addu  $14,$14,$7
8104		 lw    $25,0x90($21)
8105		 sw    $15,m68k_ICount
8106		 or    $5,$0,$2
8107		 or    $4,$0,$14
8108		 jalr  $25
8109		 sw    $23,0x4C($21)    	 # Delay slot
8110		 lw    $15,m68k_ICount
8111		 addiu $15,$15,-24
8112		 bgez  $15,3f
8113		 lhu   $24,0x00($23)    	 # Delay slot
8114		 j     MainExit
8115	3:
8116		 sll   $7,$24,2         	 # Delay slot
8117		 addu  $7,$7,$30
8118		 lw    $7,0x00($7)
8119		 jr    $7
8120		 nop                    	 # Delay slot
8121
8122OP0_2158:				#:
8123		 addiu $23,$23,2
8124
8125		 and   $8,$24,0x07
8126		 sll   $8,$8,2
8127		 addu  $8,$8,$21
8128		 lw    $14,0x20($8)
8129		 addiu $25,$14,4
8130		 sw    $25,0x20($8)
8131		 lw    $25,0x84($21)
8132		 sw    $15,m68k_ICount
8133		 sw    $24,0x44($29)
8134		 or    $4,$0,$14
8135		 jalr  $25
8136		 sw    $23,0x4C($21)    	 # Delay slot
8137		 lw    $24,0x44($29)
8138		 lw    $15,m68k_ICount
8139		 and   $16,$0,$0        	 # Clear Carry
8140		 and   $17,$0,$0        	 # Clear Overflow
8141		 srl   $19,$2,31         	 # Set Sign
8142		 sltiu $18,$2,1         	 # Set Zero
8143		 srl   $24,$24,7
8144		 andi  $24,$24,0x1C
8145		 lh    $7,0x00($23)
8146		 addu  $24,$24,$21
8147		 lw    $14,0x20($24)
8148		 addiu $23,$23,2
8149		 addu  $14,$14,$7
8150		 lw    $25,0x90($21)
8151		 sw    $15,m68k_ICount
8152		 or    $5,$0,$2
8153		 or    $4,$0,$14
8154		 jalr  $25
8155		 sw    $23,0x4C($21)    	 # Delay slot
8156		 lw    $15,m68k_ICount
8157		 addiu $15,$15,-24
8158		 bgez  $15,3f
8159		 lhu   $24,0x00($23)    	 # Delay slot
8160		 j     MainExit
8161	3:
8162		 sll   $7,$24,2         	 # Delay slot
8163		 addu  $7,$7,$30
8164		 lw    $7,0x00($7)
8165		 jr    $7
8166		 nop                    	 # Delay slot
8167
8168OP0_2160:				#:
8169		 addiu $23,$23,2
8170
8171		 and   $8,$24,0x07
8172		 sll   $8,$8,2
8173		 addu  $8,$8,$21
8174		 lw    $14,0x20($8)
8175		 addiu $14,$14,-4
8176		 sw    $14,0x20($8)
8177		 lw    $25,0x84($21)
8178		 sw    $15,m68k_ICount
8179		 sw    $24,0x44($29)
8180		 or    $4,$0,$14
8181		 jalr  $25
8182		 sw    $23,0x4C($21)    	 # Delay slot
8183		 lw    $24,0x44($29)
8184		 lw    $15,m68k_ICount
8185		 and   $16,$0,$0        	 # Clear Carry
8186		 and   $17,$0,$0        	 # Clear Overflow
8187		 srl   $19,$2,31         	 # Set Sign
8188		 sltiu $18,$2,1         	 # Set Zero
8189		 srl   $24,$24,7
8190		 andi  $24,$24,0x1C
8191		 lh    $7,0x00($23)
8192		 addu  $24,$24,$21
8193		 lw    $14,0x20($24)
8194		 addiu $23,$23,2
8195		 addu  $14,$14,$7
8196		 lw    $25,0x90($21)
8197		 sw    $15,m68k_ICount
8198		 or    $5,$0,$2
8199		 or    $4,$0,$14
8200		 jalr  $25
8201		 sw    $23,0x4C($21)    	 # Delay slot
8202		 lw    $15,m68k_ICount
8203		 addiu $15,$15,-26
8204		 bgez  $15,3f
8205		 lhu   $24,0x00($23)    	 # Delay slot
8206		 j     MainExit
8207	3:
8208		 sll   $7,$24,2         	 # Delay slot
8209		 addu  $7,$7,$30
8210		 lw    $7,0x00($7)
8211		 jr    $7
8212		 nop                    	 # Delay slot
8213
8214OP0_2168:				#:
8215		 addiu $23,$23,2
8216
8217		 and   $8,$24,0x07
8218		 lh    $7,0x00($23)
8219		 sll   $8,$8,2
8220		 addu  $8,$8,$21
8221		 lw    $14,0x20($8)
8222		 addiu $23,$23,2
8223		 addu  $14,$14,$7
8224		 lw    $25,0x84($21)
8225		 sw    $15,m68k_ICount
8226		 sw    $24,0x44($29)
8227		 or    $4,$0,$14
8228		 jalr  $25
8229		 sw    $23,0x4C($21)    	 # Delay slot
8230		 lw    $24,0x44($29)
8231		 lw    $15,m68k_ICount
8232		 and   $16,$0,$0        	 # Clear Carry
8233		 and   $17,$0,$0        	 # Clear Overflow
8234		 srl   $19,$2,31         	 # Set Sign
8235		 sltiu $18,$2,1         	 # Set Zero
8236		 srl   $24,$24,7
8237		 andi  $24,$24,0x1C
8238		 lh    $7,0x00($23)
8239		 addu  $24,$24,$21
8240		 lw    $14,0x20($24)
8241		 addiu $23,$23,2
8242		 addu  $14,$14,$7
8243		 lw    $25,0x90($21)
8244		 sw    $15,m68k_ICount
8245		 or    $5,$0,$2
8246		 or    $4,$0,$14
8247		 jalr  $25
8248		 sw    $23,0x4C($21)    	 # Delay slot
8249		 lw    $15,m68k_ICount
8250		 addiu $15,$15,-28
8251		 bgez  $15,3f
8252		 lhu   $24,0x00($23)    	 # Delay slot
8253		 j     MainExit
8254	3:
8255		 sll   $7,$24,2         	 # Delay slot
8256		 addu  $7,$7,$30
8257		 lw    $7,0x00($7)
8258		 jr    $7
8259		 nop                    	 # Delay slot
8260
8261OP0_2170:				#:
8262		 addiu $23,$23,2
8263
8264		 and   $8,$24,0x07
8265		 sll   $8,$8,2
8266		 addu  $8,$8,$21
8267		 lw    $14,0x20($8)
8268		 lhu   $7,0x00($23)
8269		 addiu $23,$23,2
8270		 seb   $6,$7
8271		 or    $25,$0,$7
8272		 srl   $7,$7,12
8273		 andi  $25,$25,0x0800
8274		 sll   $7,$7,2
8275		 addu  $7,$7,$21
8276		 bne   $25,$0,0f
8277		 lw    $25,0x00($7)      	 # Delay slot
8278		 seh   $25,$25
8279	0:
8280		 addu  $25,$14,$25
8281		 addu  $14,$25,$6
8282		 lw    $25,0x84($21)
8283		 sw    $15,m68k_ICount
8284		 sw    $24,0x44($29)
8285		 or    $4,$0,$14
8286		 jalr  $25
8287		 sw    $23,0x4C($21)    	 # Delay slot
8288		 lw    $24,0x44($29)
8289		 lw    $15,m68k_ICount
8290		 and   $16,$0,$0        	 # Clear Carry
8291		 and   $17,$0,$0        	 # Clear Overflow
8292		 srl   $19,$2,31         	 # Set Sign
8293		 sltiu $18,$2,1         	 # Set Zero
8294		 srl   $24,$24,7
8295		 andi  $24,$24,0x1C
8296		 lh    $7,0x00($23)
8297		 addu  $24,$24,$21
8298		 lw    $14,0x20($24)
8299		 addiu $23,$23,2
8300		 addu  $14,$14,$7
8301		 lw    $25,0x90($21)
8302		 sw    $15,m68k_ICount
8303		 or    $5,$0,$2
8304		 or    $4,$0,$14
8305		 jalr  $25
8306		 sw    $23,0x4C($21)    	 # Delay slot
8307		 lw    $15,m68k_ICount
8308		 addiu $15,$15,-30
8309		 bgez  $15,3f
8310		 lhu   $24,0x00($23)    	 # Delay slot
8311		 j     MainExit
8312	3:
8313		 sll   $7,$24,2         	 # Delay slot
8314		 addu  $7,$7,$30
8315		 lw    $7,0x00($7)
8316		 jr    $7
8317		 nop                    	 # Delay slot
8318
8319OP0_2178:				#:
8320		 addiu $23,$23,2
8321
8322		 lh    $14,0x00($23)
8323		 addiu $23,$23,2
8324		 lw    $25,0x84($21)
8325		 sw    $15,m68k_ICount
8326		 sw    $24,0x44($29)
8327		 or    $4,$0,$14
8328		 jalr  $25
8329		 sw    $23,0x4C($21)    	 # Delay slot
8330		 lw    $24,0x44($29)
8331		 lw    $15,m68k_ICount
8332		 and   $16,$0,$0        	 # Clear Carry
8333		 and   $17,$0,$0        	 # Clear Overflow
8334		 srl   $19,$2,31         	 # Set Sign
8335		 sltiu $18,$2,1         	 # Set Zero
8336		 srl   $24,$24,7
8337		 andi  $24,$24,0x1C
8338		 lh    $7,0x00($23)
8339		 addu  $24,$24,$21
8340		 lw    $14,0x20($24)
8341		 addiu $23,$23,2
8342		 addu  $14,$14,$7
8343		 lw    $25,0x90($21)
8344		 sw    $15,m68k_ICount
8345		 or    $5,$0,$2
8346		 or    $4,$0,$14
8347		 jalr  $25
8348		 sw    $23,0x4C($21)    	 # Delay slot
8349		 lw    $15,m68k_ICount
8350		 addiu $15,$15,-28
8351		 bgez  $15,3f
8352		 lhu   $24,0x00($23)    	 # Delay slot
8353		 j     MainExit
8354	3:
8355		 sll   $7,$24,2         	 # Delay slot
8356		 addu  $7,$7,$30
8357		 lw    $7,0x00($7)
8358		 jr    $7
8359		 nop                    	 # Delay slot
8360
8361OP0_2179:				#:
8362		 addiu $23,$23,2
8363
8364		 lhu   $14,0x00($23)
8365		 lhu   $25,0x02($23)
8366		 sll   $14,$14,16
8367		 or    $14,$14,$25
8368		 addiu $23,$23,4
8369		 lw    $25,0x84($21)
8370		 sw    $15,m68k_ICount
8371		 sw    $24,0x44($29)
8372		 or    $4,$0,$14
8373		 jalr  $25
8374		 sw    $23,0x4C($21)    	 # Delay slot
8375		 lw    $24,0x44($29)
8376		 lw    $15,m68k_ICount
8377		 and   $16,$0,$0        	 # Clear Carry
8378		 and   $17,$0,$0        	 # Clear Overflow
8379		 srl   $19,$2,31         	 # Set Sign
8380		 sltiu $18,$2,1         	 # Set Zero
8381		 srl   $24,$24,7
8382		 andi  $24,$24,0x1C
8383		 lh    $7,0x00($23)
8384		 addu  $24,$24,$21
8385		 lw    $14,0x20($24)
8386		 addiu $23,$23,2
8387		 addu  $14,$14,$7
8388		 lw    $25,0x90($21)
8389		 sw    $15,m68k_ICount
8390		 or    $5,$0,$2
8391		 or    $4,$0,$14
8392		 jalr  $25
8393		 sw    $23,0x4C($21)    	 # Delay slot
8394		 lw    $15,m68k_ICount
8395		 addiu $15,$15,-32
8396		 bgez  $15,3f
8397		 lhu   $24,0x00($23)    	 # Delay slot
8398		 j     MainExit
8399	3:
8400		 sll   $7,$24,2         	 # Delay slot
8401		 addu  $7,$7,$30
8402		 lw    $7,0x00($7)
8403		 jr    $7
8404		 nop                    	 # Delay slot
8405
8406OP0_217a:				#:
8407		 addiu $23,$23,2
8408
8409		 lh    $7,0x00($23)
8410		 subu  $25,$23,$22
8411		 addu  $14,$25,$7       	 # Add Offset to PC
8412		 addiu $23,$23,2
8413		 lw    $25,0xA0($21)
8414		 sw    $15,m68k_ICount
8415		 sw    $24,0x44($29)
8416		 or    $4,$0,$14
8417		 jalr  $25
8418		 sw    $23,0x4C($21)    	 # Delay slot
8419		 lw    $24,0x44($29)
8420		 lw    $15,m68k_ICount
8421		 and   $16,$0,$0        	 # Clear Carry
8422		 and   $17,$0,$0        	 # Clear Overflow
8423		 srl   $19,$2,31         	 # Set Sign
8424		 sltiu $18,$2,1         	 # Set Zero
8425		 srl   $24,$24,7
8426		 andi  $24,$24,0x1C
8427		 lh    $7,0x00($23)
8428		 addu  $24,$24,$21
8429		 lw    $14,0x20($24)
8430		 addiu $23,$23,2
8431		 addu  $14,$14,$7
8432		 lw    $25,0x90($21)
8433		 sw    $15,m68k_ICount
8434		 or    $5,$0,$2
8435		 or    $4,$0,$14
8436		 jalr  $25
8437		 sw    $23,0x4C($21)    	 # Delay slot
8438		 lw    $15,m68k_ICount
8439		 addiu $15,$15,-28
8440		 bgez  $15,3f
8441		 lhu   $24,0x00($23)    	 # Delay slot
8442		 j     MainExit
8443	3:
8444		 sll   $7,$24,2         	 # Delay slot
8445		 addu  $7,$7,$30
8446		 lw    $7,0x00($7)
8447		 jr    $7
8448		 nop                    	 # Delay slot
8449
8450OP0_217b:				#:
8451		 addiu $23,$23,2
8452
8453		 subu  $14,$23,$22       	 # Get PC
8454		 lhu   $7,0x00($23)
8455		 addiu $23,$23,2
8456		 seb   $6,$7
8457		 or    $25,$0,$7
8458		 srl   $7,$7,12
8459		 andi  $25,$25,0x0800
8460		 sll   $7,$7,2
8461		 addu  $7,$7,$21
8462		 bne   $25,$0,0f
8463		 lw    $25,0x00($7)      	 # Delay slot
8464		 seh   $25,$25
8465	0:
8466		 addu  $25,$14,$25
8467		 addu  $14,$25,$6
8468		 lw    $25,0xA0($21)
8469		 sw    $15,m68k_ICount
8470		 sw    $24,0x44($29)
8471		 or    $4,$0,$14
8472		 jalr  $25
8473		 sw    $23,0x4C($21)    	 # Delay slot
8474		 lw    $24,0x44($29)
8475		 lw    $15,m68k_ICount
8476		 and   $16,$0,$0        	 # Clear Carry
8477		 and   $17,$0,$0        	 # Clear Overflow
8478		 srl   $19,$2,31         	 # Set Sign
8479		 sltiu $18,$2,1         	 # Set Zero
8480		 srl   $24,$24,7
8481		 andi  $24,$24,0x1C
8482		 lh    $7,0x00($23)
8483		 addu  $24,$24,$21
8484		 lw    $14,0x20($24)
8485		 addiu $23,$23,2
8486		 addu  $14,$14,$7
8487		 lw    $25,0x90($21)
8488		 sw    $15,m68k_ICount
8489		 or    $5,$0,$2
8490		 or    $4,$0,$14
8491		 jalr  $25
8492		 sw    $23,0x4C($21)    	 # Delay slot
8493		 lw    $15,m68k_ICount
8494		 addiu $15,$15,-30
8495		 bgez  $15,3f
8496		 lhu   $24,0x00($23)    	 # Delay slot
8497		 j     MainExit
8498	3:
8499		 sll   $7,$24,2         	 # Delay slot
8500		 addu  $7,$7,$30
8501		 lw    $7,0x00($7)
8502		 jr    $7
8503		 nop                    	 # Delay slot
8504
8505OP0_217c:				#:
8506		 addiu $23,$23,2
8507
8508		 lhu   $2,0x00($23)
8509		 lhu   $25,0x02($23)
8510		 sll   $2,$2,16
8511		 or    $2,$2,$25
8512		 addiu $23,$23,4
8513		 and   $16,$0,$0        	 # Clear Carry
8514		 and   $17,$0,$0        	 # Clear Overflow
8515		 srl   $19,$2,31         	 # Set Sign
8516		 sltiu $18,$2,1         	 # Set Zero
8517		 srl   $24,$24,7
8518		 andi  $24,$24,0x1C
8519		 lh    $7,0x00($23)
8520		 addu  $24,$24,$21
8521		 lw    $14,0x20($24)
8522		 addiu $23,$23,2
8523		 addu  $14,$14,$7
8524		 lw    $25,0x90($21)
8525		 sw    $15,m68k_ICount
8526		 or    $5,$0,$2
8527		 or    $4,$0,$14
8528		 jalr  $25
8529		 sw    $23,0x4C($21)    	 # Delay slot
8530		 lw    $15,m68k_ICount
8531		 addiu $15,$15,-16
8532		 bgez  $15,3f
8533		 lhu   $24,0x00($23)    	 # Delay slot
8534		 j     MainExit
8535	3:
8536		 sll   $7,$24,2         	 # Delay slot
8537		 addu  $7,$7,$30
8538		 lw    $7,0x00($7)
8539		 jr    $7
8540		 nop                    	 # Delay slot
8541
8542OP0_2180:				#:
8543		 addiu $23,$23,2
8544
8545		 and   $8,$24,0x0f
8546		 sll   $8,$8,2
8547		 addu  $8,$8,$21
8548		 lw    $2,0x00($8)
8549		 and   $16,$0,$0        	 # Clear Carry
8550		 and   $17,$0,$0        	 # Clear Overflow
8551		 srl   $19,$2,31         	 # Set Sign
8552		 sltiu $18,$2,1         	 # Set Zero
8553		 srl   $24,$24,7
8554		 andi  $24,$24,0x1C
8555		 addu  $24,$24,$21
8556		 lw    $14,0x20($24)
8557		 lhu   $7,0x00($23)
8558		 addiu $23,$23,2
8559		 seb   $6,$7
8560		 or    $25,$0,$7
8561		 srl   $7,$7,12
8562		 andi  $25,$25,0x0800
8563		 sll   $7,$7,2
8564		 addu  $7,$7,$21
8565		 bne   $25,$0,0f
8566		 lw    $25,0x00($7)      	 # Delay slot
8567		 seh   $25,$25
8568	0:
8569		 addu  $25,$14,$25
8570		 addu  $14,$25,$6
8571		 lw    $25,0x90($21)
8572		 sw    $15,m68k_ICount
8573		 or    $5,$0,$2
8574		 or    $4,$0,$14
8575		 jalr  $25
8576		 sw    $23,0x4C($21)    	 # Delay slot
8577		 lw    $15,m68k_ICount
8578		 addiu $15,$15,-18
8579		 bgez  $15,3f
8580		 lhu   $24,0x00($23)    	 # Delay slot
8581		 j     MainExit
8582	3:
8583		 sll   $7,$24,2         	 # Delay slot
8584		 addu  $7,$7,$30
8585		 lw    $7,0x00($7)
8586		 jr    $7
8587		 nop                    	 # Delay slot
8588
8589OP0_2190:				#:
8590		 addiu $23,$23,2
8591
8592		 and   $8,$24,0x07
8593		 sll   $8,$8,2
8594		 addu  $8,$8,$21
8595		 lw    $14,0x20($8)
8596		 lw    $25,0x84($21)
8597		 sw    $15,m68k_ICount
8598		 sw    $24,0x44($29)
8599		 or    $4,$0,$14
8600		 jalr  $25
8601		 sw    $23,0x4C($21)    	 # Delay slot
8602		 lw    $24,0x44($29)
8603		 lw    $15,m68k_ICount
8604		 and   $16,$0,$0        	 # Clear Carry
8605		 and   $17,$0,$0        	 # Clear Overflow
8606		 srl   $19,$2,31         	 # Set Sign
8607		 sltiu $18,$2,1         	 # Set Zero
8608		 srl   $24,$24,7
8609		 andi  $24,$24,0x1C
8610		 addu  $24,$24,$21
8611		 lw    $14,0x20($24)
8612		 lhu   $7,0x00($23)
8613		 addiu $23,$23,2
8614		 seb   $6,$7
8615		 or    $25,$0,$7
8616		 srl   $7,$7,12
8617		 andi  $25,$25,0x0800
8618		 sll   $7,$7,2
8619		 addu  $7,$7,$21
8620		 bne   $25,$0,0f
8621		 lw    $25,0x00($7)      	 # Delay slot
8622		 seh   $25,$25
8623	0:
8624		 addu  $25,$14,$25
8625		 addu  $14,$25,$6
8626		 lw    $25,0x90($21)
8627		 sw    $15,m68k_ICount
8628		 or    $5,$0,$2
8629		 or    $4,$0,$14
8630		 jalr  $25
8631		 sw    $23,0x4C($21)    	 # Delay slot
8632		 lw    $15,m68k_ICount
8633		 addiu $15,$15,-26
8634		 bgez  $15,3f
8635		 lhu   $24,0x00($23)    	 # Delay slot
8636		 j     MainExit
8637	3:
8638		 sll   $7,$24,2         	 # Delay slot
8639		 addu  $7,$7,$30
8640		 lw    $7,0x00($7)
8641		 jr    $7
8642		 nop                    	 # Delay slot
8643
8644OP0_2198:				#:
8645		 addiu $23,$23,2
8646
8647		 and   $8,$24,0x07
8648		 sll   $8,$8,2
8649		 addu  $8,$8,$21
8650		 lw    $14,0x20($8)
8651		 addiu $25,$14,4
8652		 sw    $25,0x20($8)
8653		 lw    $25,0x84($21)
8654		 sw    $15,m68k_ICount
8655		 sw    $24,0x44($29)
8656		 or    $4,$0,$14
8657		 jalr  $25
8658		 sw    $23,0x4C($21)    	 # Delay slot
8659		 lw    $24,0x44($29)
8660		 lw    $15,m68k_ICount
8661		 and   $16,$0,$0        	 # Clear Carry
8662		 and   $17,$0,$0        	 # Clear Overflow
8663		 srl   $19,$2,31         	 # Set Sign
8664		 sltiu $18,$2,1         	 # Set Zero
8665		 srl   $24,$24,7
8666		 andi  $24,$24,0x1C
8667		 addu  $24,$24,$21
8668		 lw    $14,0x20($24)
8669		 lhu   $7,0x00($23)
8670		 addiu $23,$23,2
8671		 seb   $6,$7
8672		 or    $25,$0,$7
8673		 srl   $7,$7,12
8674		 andi  $25,$25,0x0800
8675		 sll   $7,$7,2
8676		 addu  $7,$7,$21
8677		 bne   $25,$0,0f
8678		 lw    $25,0x00($7)      	 # Delay slot
8679		 seh   $25,$25
8680	0:
8681		 addu  $25,$14,$25
8682		 addu  $14,$25,$6
8683		 lw    $25,0x90($21)
8684		 sw    $15,m68k_ICount
8685		 or    $5,$0,$2
8686		 or    $4,$0,$14
8687		 jalr  $25
8688		 sw    $23,0x4C($21)    	 # Delay slot
8689		 lw    $15,m68k_ICount
8690		 addiu $15,$15,-26
8691		 bgez  $15,3f
8692		 lhu   $24,0x00($23)    	 # Delay slot
8693		 j     MainExit
8694	3:
8695		 sll   $7,$24,2         	 # Delay slot
8696		 addu  $7,$7,$30
8697		 lw    $7,0x00($7)
8698		 jr    $7
8699		 nop                    	 # Delay slot
8700
8701OP0_21a0:				#:
8702		 addiu $23,$23,2
8703
8704		 and   $8,$24,0x07
8705		 sll   $8,$8,2
8706		 addu  $8,$8,$21
8707		 lw    $14,0x20($8)
8708		 addiu $14,$14,-4
8709		 sw    $14,0x20($8)
8710		 lw    $25,0x84($21)
8711		 sw    $15,m68k_ICount
8712		 sw    $24,0x44($29)
8713		 or    $4,$0,$14
8714		 jalr  $25
8715		 sw    $23,0x4C($21)    	 # Delay slot
8716		 lw    $24,0x44($29)
8717		 lw    $15,m68k_ICount
8718		 and   $16,$0,$0        	 # Clear Carry
8719		 and   $17,$0,$0        	 # Clear Overflow
8720		 srl   $19,$2,31         	 # Set Sign
8721		 sltiu $18,$2,1         	 # Set Zero
8722		 srl   $24,$24,7
8723		 andi  $24,$24,0x1C
8724		 addu  $24,$24,$21
8725		 lw    $14,0x20($24)
8726		 lhu   $7,0x00($23)
8727		 addiu $23,$23,2
8728		 seb   $6,$7
8729		 or    $25,$0,$7
8730		 srl   $7,$7,12
8731		 andi  $25,$25,0x0800
8732		 sll   $7,$7,2
8733		 addu  $7,$7,$21
8734		 bne   $25,$0,0f
8735		 lw    $25,0x00($7)      	 # Delay slot
8736		 seh   $25,$25
8737	0:
8738		 addu  $25,$14,$25
8739		 addu  $14,$25,$6
8740		 lw    $25,0x90($21)
8741		 sw    $15,m68k_ICount
8742		 or    $5,$0,$2
8743		 or    $4,$0,$14
8744		 jalr  $25
8745		 sw    $23,0x4C($21)    	 # Delay slot
8746		 lw    $15,m68k_ICount
8747		 addiu $15,$15,-28
8748		 bgez  $15,3f
8749		 lhu   $24,0x00($23)    	 # Delay slot
8750		 j     MainExit
8751	3:
8752		 sll   $7,$24,2         	 # Delay slot
8753		 addu  $7,$7,$30
8754		 lw    $7,0x00($7)
8755		 jr    $7
8756		 nop                    	 # Delay slot
8757
8758OP0_21a8:				#:
8759		 addiu $23,$23,2
8760
8761		 and   $8,$24,0x07
8762		 lh    $7,0x00($23)
8763		 sll   $8,$8,2
8764		 addu  $8,$8,$21
8765		 lw    $14,0x20($8)
8766		 addiu $23,$23,2
8767		 addu  $14,$14,$7
8768		 lw    $25,0x84($21)
8769		 sw    $15,m68k_ICount
8770		 sw    $24,0x44($29)
8771		 or    $4,$0,$14
8772		 jalr  $25
8773		 sw    $23,0x4C($21)    	 # Delay slot
8774		 lw    $24,0x44($29)
8775		 lw    $15,m68k_ICount
8776		 and   $16,$0,$0        	 # Clear Carry
8777		 and   $17,$0,$0        	 # Clear Overflow
8778		 srl   $19,$2,31         	 # Set Sign
8779		 sltiu $18,$2,1         	 # Set Zero
8780		 srl   $24,$24,7
8781		 andi  $24,$24,0x1C
8782		 addu  $24,$24,$21
8783		 lw    $14,0x20($24)
8784		 lhu   $7,0x00($23)
8785		 addiu $23,$23,2
8786		 seb   $6,$7
8787		 or    $25,$0,$7
8788		 srl   $7,$7,12
8789		 andi  $25,$25,0x0800
8790		 sll   $7,$7,2
8791		 addu  $7,$7,$21
8792		 bne   $25,$0,0f
8793		 lw    $25,0x00($7)      	 # Delay slot
8794		 seh   $25,$25
8795	0:
8796		 addu  $25,$14,$25
8797		 addu  $14,$25,$6
8798		 lw    $25,0x90($21)
8799		 sw    $15,m68k_ICount
8800		 or    $5,$0,$2
8801		 or    $4,$0,$14
8802		 jalr  $25
8803		 sw    $23,0x4C($21)    	 # Delay slot
8804		 lw    $15,m68k_ICount
8805		 addiu $15,$15,-30
8806		 bgez  $15,3f
8807		 lhu   $24,0x00($23)    	 # Delay slot
8808		 j     MainExit
8809	3:
8810		 sll   $7,$24,2         	 # Delay slot
8811		 addu  $7,$7,$30
8812		 lw    $7,0x00($7)
8813		 jr    $7
8814		 nop                    	 # Delay slot
8815
8816OP0_21b0:				#:
8817		 addiu $23,$23,2
8818
8819		 and   $8,$24,0x07
8820		 sll   $8,$8,2
8821		 addu  $8,$8,$21
8822		 lw    $14,0x20($8)
8823		 lhu   $7,0x00($23)
8824		 addiu $23,$23,2
8825		 seb   $6,$7
8826		 or    $25,$0,$7
8827		 srl   $7,$7,12
8828		 andi  $25,$25,0x0800
8829		 sll   $7,$7,2
8830		 addu  $7,$7,$21
8831		 bne   $25,$0,0f
8832		 lw    $25,0x00($7)      	 # Delay slot
8833		 seh   $25,$25
8834	0:
8835		 addu  $25,$14,$25
8836		 addu  $14,$25,$6
8837		 lw    $25,0x84($21)
8838		 sw    $15,m68k_ICount
8839		 sw    $24,0x44($29)
8840		 or    $4,$0,$14
8841		 jalr  $25
8842		 sw    $23,0x4C($21)    	 # Delay slot
8843		 lw    $24,0x44($29)
8844		 lw    $15,m68k_ICount
8845		 and   $16,$0,$0        	 # Clear Carry
8846		 and   $17,$0,$0        	 # Clear Overflow
8847		 srl   $19,$2,31         	 # Set Sign
8848		 sltiu $18,$2,1         	 # Set Zero
8849		 srl   $24,$24,7
8850		 andi  $24,$24,0x1C
8851		 addu  $24,$24,$21
8852		 lw    $14,0x20($24)
8853		 lhu   $7,0x00($23)
8854		 addiu $23,$23,2
8855		 seb   $6,$7
8856		 or    $25,$0,$7
8857		 srl   $7,$7,12
8858		 andi  $25,$25,0x0800
8859		 sll   $7,$7,2
8860		 addu  $7,$7,$21
8861		 bne   $25,$0,0f
8862		 lw    $25,0x00($7)      	 # Delay slot
8863		 seh   $25,$25
8864	0:
8865		 addu  $25,$14,$25
8866		 addu  $14,$25,$6
8867		 lw    $25,0x90($21)
8868		 sw    $15,m68k_ICount
8869		 or    $5,$0,$2
8870		 or    $4,$0,$14
8871		 jalr  $25
8872		 sw    $23,0x4C($21)    	 # Delay slot
8873		 lw    $15,m68k_ICount
8874		 addiu $15,$15,-32
8875		 bgez  $15,3f
8876		 lhu   $24,0x00($23)    	 # Delay slot
8877		 j     MainExit
8878	3:
8879		 sll   $7,$24,2         	 # Delay slot
8880		 addu  $7,$7,$30
8881		 lw    $7,0x00($7)
8882		 jr    $7
8883		 nop                    	 # Delay slot
8884
8885OP0_21b8:				#:
8886		 addiu $23,$23,2
8887
8888		 lh    $14,0x00($23)
8889		 addiu $23,$23,2
8890		 lw    $25,0x84($21)
8891		 sw    $15,m68k_ICount
8892		 sw    $24,0x44($29)
8893		 or    $4,$0,$14
8894		 jalr  $25
8895		 sw    $23,0x4C($21)    	 # Delay slot
8896		 lw    $24,0x44($29)
8897		 lw    $15,m68k_ICount
8898		 and   $16,$0,$0        	 # Clear Carry
8899		 and   $17,$0,$0        	 # Clear Overflow
8900		 srl   $19,$2,31         	 # Set Sign
8901		 sltiu $18,$2,1         	 # Set Zero
8902		 srl   $24,$24,7
8903		 andi  $24,$24,0x1C
8904		 addu  $24,$24,$21
8905		 lw    $14,0x20($24)
8906		 lhu   $7,0x00($23)
8907		 addiu $23,$23,2
8908		 seb   $6,$7
8909		 or    $25,$0,$7
8910		 srl   $7,$7,12
8911		 andi  $25,$25,0x0800
8912		 sll   $7,$7,2
8913		 addu  $7,$7,$21
8914		 bne   $25,$0,0f
8915		 lw    $25,0x00($7)      	 # Delay slot
8916		 seh   $25,$25
8917	0:
8918		 addu  $25,$14,$25
8919		 addu  $14,$25,$6
8920		 lw    $25,0x90($21)
8921		 sw    $15,m68k_ICount
8922		 or    $5,$0,$2
8923		 or    $4,$0,$14
8924		 jalr  $25
8925		 sw    $23,0x4C($21)    	 # Delay slot
8926		 lw    $15,m68k_ICount
8927		 addiu $15,$15,-30
8928		 bgez  $15,3f
8929		 lhu   $24,0x00($23)    	 # Delay slot
8930		 j     MainExit
8931	3:
8932		 sll   $7,$24,2         	 # Delay slot
8933		 addu  $7,$7,$30
8934		 lw    $7,0x00($7)
8935		 jr    $7
8936		 nop                    	 # Delay slot
8937
8938OP0_21b9:				#:
8939		 addiu $23,$23,2
8940
8941		 lhu   $14,0x00($23)
8942		 lhu   $25,0x02($23)
8943		 sll   $14,$14,16
8944		 or    $14,$14,$25
8945		 addiu $23,$23,4
8946		 lw    $25,0x84($21)
8947		 sw    $15,m68k_ICount
8948		 sw    $24,0x44($29)
8949		 or    $4,$0,$14
8950		 jalr  $25
8951		 sw    $23,0x4C($21)    	 # Delay slot
8952		 lw    $24,0x44($29)
8953		 lw    $15,m68k_ICount
8954		 and   $16,$0,$0        	 # Clear Carry
8955		 and   $17,$0,$0        	 # Clear Overflow
8956		 srl   $19,$2,31         	 # Set Sign
8957		 sltiu $18,$2,1         	 # Set Zero
8958		 srl   $24,$24,7
8959		 andi  $24,$24,0x1C
8960		 addu  $24,$24,$21
8961		 lw    $14,0x20($24)
8962		 lhu   $7,0x00($23)
8963		 addiu $23,$23,2
8964		 seb   $6,$7
8965		 or    $25,$0,$7
8966		 srl   $7,$7,12
8967		 andi  $25,$25,0x0800
8968		 sll   $7,$7,2
8969		 addu  $7,$7,$21
8970		 bne   $25,$0,0f
8971		 lw    $25,0x00($7)      	 # Delay slot
8972		 seh   $25,$25
8973	0:
8974		 addu  $25,$14,$25
8975		 addu  $14,$25,$6
8976		 lw    $25,0x90($21)
8977		 sw    $15,m68k_ICount
8978		 or    $5,$0,$2
8979		 or    $4,$0,$14
8980		 jalr  $25
8981		 sw    $23,0x4C($21)    	 # Delay slot
8982		 lw    $15,m68k_ICount
8983		 addiu $15,$15,-34
8984		 bgez  $15,3f
8985		 lhu   $24,0x00($23)    	 # Delay slot
8986		 j     MainExit
8987	3:
8988		 sll   $7,$24,2         	 # Delay slot
8989		 addu  $7,$7,$30
8990		 lw    $7,0x00($7)
8991		 jr    $7
8992		 nop                    	 # Delay slot
8993
8994OP0_21ba:				#:
8995		 addiu $23,$23,2
8996
8997		 lh    $7,0x00($23)
8998		 subu  $25,$23,$22
8999		 addu  $14,$25,$7       	 # Add Offset to PC
9000		 addiu $23,$23,2
9001		 lw    $25,0xA0($21)
9002		 sw    $15,m68k_ICount
9003		 sw    $24,0x44($29)
9004		 or    $4,$0,$14
9005		 jalr  $25
9006		 sw    $23,0x4C($21)    	 # Delay slot
9007		 lw    $24,0x44($29)
9008		 lw    $15,m68k_ICount
9009		 and   $16,$0,$0        	 # Clear Carry
9010		 and   $17,$0,$0        	 # Clear Overflow
9011		 srl   $19,$2,31         	 # Set Sign
9012		 sltiu $18,$2,1         	 # Set Zero
9013		 srl   $24,$24,7
9014		 andi  $24,$24,0x1C
9015		 addu  $24,$24,$21
9016		 lw    $14,0x20($24)
9017		 lhu   $7,0x00($23)
9018		 addiu $23,$23,2
9019		 seb   $6,$7
9020		 or    $25,$0,$7
9021		 srl   $7,$7,12
9022		 andi  $25,$25,0x0800
9023		 sll   $7,$7,2
9024		 addu  $7,$7,$21
9025		 bne   $25,$0,0f
9026		 lw    $25,0x00($7)      	 # Delay slot
9027		 seh   $25,$25
9028	0:
9029		 addu  $25,$14,$25
9030		 addu  $14,$25,$6
9031		 lw    $25,0x90($21)
9032		 sw    $15,m68k_ICount
9033		 or    $5,$0,$2
9034		 or    $4,$0,$14
9035		 jalr  $25
9036		 sw    $23,0x4C($21)    	 # Delay slot
9037		 lw    $15,m68k_ICount
9038		 addiu $15,$15,-30
9039		 bgez  $15,3f
9040		 lhu   $24,0x00($23)    	 # Delay slot
9041		 j     MainExit
9042	3:
9043		 sll   $7,$24,2         	 # Delay slot
9044		 addu  $7,$7,$30
9045		 lw    $7,0x00($7)
9046		 jr    $7
9047		 nop                    	 # Delay slot
9048
9049OP0_21bb:				#:
9050		 addiu $23,$23,2
9051
9052		 subu  $14,$23,$22       	 # Get PC
9053		 lhu   $7,0x00($23)
9054		 addiu $23,$23,2
9055		 seb   $6,$7
9056		 or    $25,$0,$7
9057		 srl   $7,$7,12
9058		 andi  $25,$25,0x0800
9059		 sll   $7,$7,2
9060		 addu  $7,$7,$21
9061		 bne   $25,$0,0f
9062		 lw    $25,0x00($7)      	 # Delay slot
9063		 seh   $25,$25
9064	0:
9065		 addu  $25,$14,$25
9066		 addu  $14,$25,$6
9067		 lw    $25,0xA0($21)
9068		 sw    $15,m68k_ICount
9069		 sw    $24,0x44($29)
9070		 or    $4,$0,$14
9071		 jalr  $25
9072		 sw    $23,0x4C($21)    	 # Delay slot
9073		 lw    $24,0x44($29)
9074		 lw    $15,m68k_ICount
9075		 and   $16,$0,$0        	 # Clear Carry
9076		 and   $17,$0,$0        	 # Clear Overflow
9077		 srl   $19,$2,31         	 # Set Sign
9078		 sltiu $18,$2,1         	 # Set Zero
9079		 srl   $24,$24,7
9080		 andi  $24,$24,0x1C
9081		 addu  $24,$24,$21
9082		 lw    $14,0x20($24)
9083		 lhu   $7,0x00($23)
9084		 addiu $23,$23,2
9085		 seb   $6,$7
9086		 or    $25,$0,$7
9087		 srl   $7,$7,12
9088		 andi  $25,$25,0x0800
9089		 sll   $7,$7,2
9090		 addu  $7,$7,$21
9091		 bne   $25,$0,0f
9092		 lw    $25,0x00($7)      	 # Delay slot
9093		 seh   $25,$25
9094	0:
9095		 addu  $25,$14,$25
9096		 addu  $14,$25,$6
9097		 lw    $25,0x90($21)
9098		 sw    $15,m68k_ICount
9099		 or    $5,$0,$2
9100		 or    $4,$0,$14
9101		 jalr  $25
9102		 sw    $23,0x4C($21)    	 # Delay slot
9103		 lw    $15,m68k_ICount
9104		 addiu $15,$15,-32
9105		 bgez  $15,3f
9106		 lhu   $24,0x00($23)    	 # Delay slot
9107		 j     MainExit
9108	3:
9109		 sll   $7,$24,2         	 # Delay slot
9110		 addu  $7,$7,$30
9111		 lw    $7,0x00($7)
9112		 jr    $7
9113		 nop                    	 # Delay slot
9114
9115OP0_21bc:				#:
9116		 addiu $23,$23,2
9117
9118		 lhu   $2,0x00($23)
9119		 lhu   $25,0x02($23)
9120		 sll   $2,$2,16
9121		 or    $2,$2,$25
9122		 addiu $23,$23,4
9123		 and   $16,$0,$0        	 # Clear Carry
9124		 and   $17,$0,$0        	 # Clear Overflow
9125		 srl   $19,$2,31         	 # Set Sign
9126		 sltiu $18,$2,1         	 # Set Zero
9127		 srl   $24,$24,7
9128		 andi  $24,$24,0x1C
9129		 addu  $24,$24,$21
9130		 lw    $14,0x20($24)
9131		 lhu   $7,0x00($23)
9132		 addiu $23,$23,2
9133		 seb   $6,$7
9134		 or    $25,$0,$7
9135		 srl   $7,$7,12
9136		 andi  $25,$25,0x0800
9137		 sll   $7,$7,2
9138		 addu  $7,$7,$21
9139		 bne   $25,$0,0f
9140		 lw    $25,0x00($7)      	 # Delay slot
9141		 seh   $25,$25
9142	0:
9143		 addu  $25,$14,$25
9144		 addu  $14,$25,$6
9145		 lw    $25,0x90($21)
9146		 sw    $15,m68k_ICount
9147		 or    $5,$0,$2
9148		 or    $4,$0,$14
9149		 jalr  $25
9150		 sw    $23,0x4C($21)    	 # Delay slot
9151		 lw    $15,m68k_ICount
9152		 addiu $15,$15,-18
9153		 bgez  $15,3f
9154		 lhu   $24,0x00($23)    	 # Delay slot
9155		 j     MainExit
9156	3:
9157		 sll   $7,$24,2         	 # Delay slot
9158		 addu  $7,$7,$30
9159		 lw    $7,0x00($7)
9160		 jr    $7
9161		 nop                    	 # Delay slot
9162
9163OP0_21c0:				#:
9164		 addiu $23,$23,2
9165
9166		 and   $8,$24,0x0f
9167		 sll   $8,$8,2
9168		 addu  $8,$8,$21
9169		 lw    $2,0x00($8)
9170		 and   $16,$0,$0        	 # Clear Carry
9171		 and   $17,$0,$0        	 # Clear Overflow
9172		 srl   $19,$2,31         	 # Set Sign
9173		 sltiu $18,$2,1         	 # Set Zero
9174		 lh    $14,0x00($23)
9175		 addiu $23,$23,2
9176		 lw    $25,0x90($21)
9177		 sw    $15,m68k_ICount
9178		 or    $5,$0,$2
9179		 or    $4,$0,$14
9180		 jalr  $25
9181		 sw    $23,0x4C($21)    	 # Delay slot
9182		 lw    $15,m68k_ICount
9183		 addiu $15,$15,-16
9184		 bgez  $15,3f
9185		 lhu   $24,0x00($23)    	 # Delay slot
9186		 j     MainExit
9187	3:
9188		 sll   $7,$24,2         	 # Delay slot
9189		 addu  $7,$7,$30
9190		 lw    $7,0x00($7)
9191		 jr    $7
9192		 nop                    	 # Delay slot
9193
9194OP0_21d0:				#:
9195		 addiu $23,$23,2
9196
9197		 and   $8,$24,0x07
9198		 sll   $8,$8,2
9199		 addu  $8,$8,$21
9200		 lw    $14,0x20($8)
9201		 lw    $25,0x84($21)
9202		 sw    $15,m68k_ICount
9203		 or    $4,$0,$14
9204		 jalr  $25
9205		 sw    $23,0x4C($21)    	 # Delay slot
9206		 lw    $15,m68k_ICount
9207		 and   $16,$0,$0        	 # Clear Carry
9208		 and   $17,$0,$0        	 # Clear Overflow
9209		 srl   $19,$2,31         	 # Set Sign
9210		 sltiu $18,$2,1         	 # Set Zero
9211		 lh    $14,0x00($23)
9212		 addiu $23,$23,2
9213		 lw    $25,0x90($21)
9214		 sw    $15,m68k_ICount
9215		 or    $5,$0,$2
9216		 or    $4,$0,$14
9217		 jalr  $25
9218		 sw    $23,0x4C($21)    	 # Delay slot
9219		 lw    $15,m68k_ICount
9220		 addiu $15,$15,-24
9221		 bgez  $15,3f
9222		 lhu   $24,0x00($23)    	 # Delay slot
9223		 j     MainExit
9224	3:
9225		 sll   $7,$24,2         	 # Delay slot
9226		 addu  $7,$7,$30
9227		 lw    $7,0x00($7)
9228		 jr    $7
9229		 nop                    	 # Delay slot
9230
9231OP0_21d8:				#:
9232		 addiu $23,$23,2
9233
9234		 and   $8,$24,0x07
9235		 sll   $8,$8,2
9236		 addu  $8,$8,$21
9237		 lw    $14,0x20($8)
9238		 addiu $25,$14,4
9239		 sw    $25,0x20($8)
9240		 lw    $25,0x84($21)
9241		 sw    $15,m68k_ICount
9242		 or    $4,$0,$14
9243		 jalr  $25
9244		 sw    $23,0x4C($21)    	 # Delay slot
9245		 lw    $15,m68k_ICount
9246		 and   $16,$0,$0        	 # Clear Carry
9247		 and   $17,$0,$0        	 # Clear Overflow
9248		 srl   $19,$2,31         	 # Set Sign
9249		 sltiu $18,$2,1         	 # Set Zero
9250		 lh    $14,0x00($23)
9251		 addiu $23,$23,2
9252		 lw    $25,0x90($21)
9253		 sw    $15,m68k_ICount
9254		 or    $5,$0,$2
9255		 or    $4,$0,$14
9256		 jalr  $25
9257		 sw    $23,0x4C($21)    	 # Delay slot
9258		 lw    $15,m68k_ICount
9259		 addiu $15,$15,-24
9260		 bgez  $15,3f
9261		 lhu   $24,0x00($23)    	 # Delay slot
9262		 j     MainExit
9263	3:
9264		 sll   $7,$24,2         	 # Delay slot
9265		 addu  $7,$7,$30
9266		 lw    $7,0x00($7)
9267		 jr    $7
9268		 nop                    	 # Delay slot
9269
9270OP0_21e0:				#:
9271		 addiu $23,$23,2
9272
9273		 and   $8,$24,0x07
9274		 sll   $8,$8,2
9275		 addu  $8,$8,$21
9276		 lw    $14,0x20($8)
9277		 addiu $14,$14,-4
9278		 sw    $14,0x20($8)
9279		 lw    $25,0x84($21)
9280		 sw    $15,m68k_ICount
9281		 or    $4,$0,$14
9282		 jalr  $25
9283		 sw    $23,0x4C($21)    	 # Delay slot
9284		 lw    $15,m68k_ICount
9285		 and   $16,$0,$0        	 # Clear Carry
9286		 and   $17,$0,$0        	 # Clear Overflow
9287		 srl   $19,$2,31         	 # Set Sign
9288		 sltiu $18,$2,1         	 # Set Zero
9289		 lh    $14,0x00($23)
9290		 addiu $23,$23,2
9291		 lw    $25,0x90($21)
9292		 sw    $15,m68k_ICount
9293		 or    $5,$0,$2
9294		 or    $4,$0,$14
9295		 jalr  $25
9296		 sw    $23,0x4C($21)    	 # Delay slot
9297		 lw    $15,m68k_ICount
9298		 addiu $15,$15,-26
9299		 bgez  $15,3f
9300		 lhu   $24,0x00($23)    	 # Delay slot
9301		 j     MainExit
9302	3:
9303		 sll   $7,$24,2         	 # Delay slot
9304		 addu  $7,$7,$30
9305		 lw    $7,0x00($7)
9306		 jr    $7
9307		 nop                    	 # Delay slot
9308
9309OP0_21e8:				#:
9310		 addiu $23,$23,2
9311
9312		 and   $8,$24,0x07
9313		 lh    $7,0x00($23)
9314		 sll   $8,$8,2
9315		 addu  $8,$8,$21
9316		 lw    $14,0x20($8)
9317		 addiu $23,$23,2
9318		 addu  $14,$14,$7
9319		 lw    $25,0x84($21)
9320		 sw    $15,m68k_ICount
9321		 or    $4,$0,$14
9322		 jalr  $25
9323		 sw    $23,0x4C($21)    	 # Delay slot
9324		 lw    $15,m68k_ICount
9325		 and   $16,$0,$0        	 # Clear Carry
9326		 and   $17,$0,$0        	 # Clear Overflow
9327		 srl   $19,$2,31         	 # Set Sign
9328		 sltiu $18,$2,1         	 # Set Zero
9329		 lh    $14,0x00($23)
9330		 addiu $23,$23,2
9331		 lw    $25,0x90($21)
9332		 sw    $15,m68k_ICount
9333		 or    $5,$0,$2
9334		 or    $4,$0,$14
9335		 jalr  $25
9336		 sw    $23,0x4C($21)    	 # Delay slot
9337		 lw    $15,m68k_ICount
9338		 addiu $15,$15,-28
9339		 bgez  $15,3f
9340		 lhu   $24,0x00($23)    	 # Delay slot
9341		 j     MainExit
9342	3:
9343		 sll   $7,$24,2         	 # Delay slot
9344		 addu  $7,$7,$30
9345		 lw    $7,0x00($7)
9346		 jr    $7
9347		 nop                    	 # Delay slot
9348
9349OP0_21f0:				#:
9350		 addiu $23,$23,2
9351
9352		 and   $8,$24,0x07
9353		 sll   $8,$8,2
9354		 addu  $8,$8,$21
9355		 lw    $14,0x20($8)
9356		 lhu   $7,0x00($23)
9357		 addiu $23,$23,2
9358		 seb   $6,$7
9359		 or    $25,$0,$7
9360		 srl   $7,$7,12
9361		 andi  $25,$25,0x0800
9362		 sll   $7,$7,2
9363		 addu  $7,$7,$21
9364		 bne   $25,$0,0f
9365		 lw    $25,0x00($7)      	 # Delay slot
9366		 seh   $25,$25
9367	0:
9368		 addu  $25,$14,$25
9369		 addu  $14,$25,$6
9370		 lw    $25,0x84($21)
9371		 sw    $15,m68k_ICount
9372		 or    $4,$0,$14
9373		 jalr  $25
9374		 sw    $23,0x4C($21)    	 # Delay slot
9375		 lw    $15,m68k_ICount
9376		 and   $16,$0,$0        	 # Clear Carry
9377		 and   $17,$0,$0        	 # Clear Overflow
9378		 srl   $19,$2,31         	 # Set Sign
9379		 sltiu $18,$2,1         	 # Set Zero
9380		 lh    $14,0x00($23)
9381		 addiu $23,$23,2
9382		 lw    $25,0x90($21)
9383		 sw    $15,m68k_ICount
9384		 or    $5,$0,$2
9385		 or    $4,$0,$14
9386		 jalr  $25
9387		 sw    $23,0x4C($21)    	 # Delay slot
9388		 lw    $15,m68k_ICount
9389		 addiu $15,$15,-30
9390		 bgez  $15,3f
9391		 lhu   $24,0x00($23)    	 # Delay slot
9392		 j     MainExit
9393	3:
9394		 sll   $7,$24,2         	 # Delay slot
9395		 addu  $7,$7,$30
9396		 lw    $7,0x00($7)
9397		 jr    $7
9398		 nop                    	 # Delay slot
9399
9400OP0_21f8:				#:
9401		 addiu $23,$23,2
9402
9403		 lh    $14,0x00($23)
9404		 addiu $23,$23,2
9405		 lw    $25,0x84($21)
9406		 sw    $15,m68k_ICount
9407		 or    $4,$0,$14
9408		 jalr  $25
9409		 sw    $23,0x4C($21)    	 # Delay slot
9410		 lw    $15,m68k_ICount
9411		 and   $16,$0,$0        	 # Clear Carry
9412		 and   $17,$0,$0        	 # Clear Overflow
9413		 srl   $19,$2,31         	 # Set Sign
9414		 sltiu $18,$2,1         	 # Set Zero
9415		 lh    $14,0x00($23)
9416		 addiu $23,$23,2
9417		 lw    $25,0x90($21)
9418		 sw    $15,m68k_ICount
9419		 or    $5,$0,$2
9420		 or    $4,$0,$14
9421		 jalr  $25
9422		 sw    $23,0x4C($21)    	 # Delay slot
9423		 lw    $15,m68k_ICount
9424		 addiu $15,$15,-28
9425		 bgez  $15,3f
9426		 lhu   $24,0x00($23)    	 # Delay slot
9427		 j     MainExit
9428	3:
9429		 sll   $7,$24,2         	 # Delay slot
9430		 addu  $7,$7,$30
9431		 lw    $7,0x00($7)
9432		 jr    $7
9433		 nop                    	 # Delay slot
9434
9435OP0_21f9:				#:
9436		 addiu $23,$23,2
9437
9438		 lhu   $14,0x00($23)
9439		 lhu   $25,0x02($23)
9440		 sll   $14,$14,16
9441		 or    $14,$14,$25
9442		 addiu $23,$23,4
9443		 lw    $25,0x84($21)
9444		 sw    $15,m68k_ICount
9445		 or    $4,$0,$14
9446		 jalr  $25
9447		 sw    $23,0x4C($21)    	 # Delay slot
9448		 lw    $15,m68k_ICount
9449		 and   $16,$0,$0        	 # Clear Carry
9450		 and   $17,$0,$0        	 # Clear Overflow
9451		 srl   $19,$2,31         	 # Set Sign
9452		 sltiu $18,$2,1         	 # Set Zero
9453		 lh    $14,0x00($23)
9454		 addiu $23,$23,2
9455		 lw    $25,0x90($21)
9456		 sw    $15,m68k_ICount
9457		 or    $5,$0,$2
9458		 or    $4,$0,$14
9459		 jalr  $25
9460		 sw    $23,0x4C($21)    	 # Delay slot
9461		 lw    $15,m68k_ICount
9462		 addiu $15,$15,-32
9463		 bgez  $15,3f
9464		 lhu   $24,0x00($23)    	 # Delay slot
9465		 j     MainExit
9466	3:
9467		 sll   $7,$24,2         	 # Delay slot
9468		 addu  $7,$7,$30
9469		 lw    $7,0x00($7)
9470		 jr    $7
9471		 nop                    	 # Delay slot
9472
9473OP0_21fa:				#:
9474		 addiu $23,$23,2
9475
9476		 lh    $7,0x00($23)
9477		 subu  $25,$23,$22
9478		 addu  $14,$25,$7       	 # Add Offset to PC
9479		 addiu $23,$23,2
9480		 lw    $25,0xA0($21)
9481		 sw    $15,m68k_ICount
9482		 or    $4,$0,$14
9483		 jalr  $25
9484		 sw    $23,0x4C($21)    	 # Delay slot
9485		 lw    $15,m68k_ICount
9486		 and   $16,$0,$0        	 # Clear Carry
9487		 and   $17,$0,$0        	 # Clear Overflow
9488		 srl   $19,$2,31         	 # Set Sign
9489		 sltiu $18,$2,1         	 # Set Zero
9490		 lh    $14,0x00($23)
9491		 addiu $23,$23,2
9492		 lw    $25,0x90($21)
9493		 sw    $15,m68k_ICount
9494		 or    $5,$0,$2
9495		 or    $4,$0,$14
9496		 jalr  $25
9497		 sw    $23,0x4C($21)    	 # Delay slot
9498		 lw    $15,m68k_ICount
9499		 addiu $15,$15,-28
9500		 bgez  $15,3f
9501		 lhu   $24,0x00($23)    	 # Delay slot
9502		 j     MainExit
9503	3:
9504		 sll   $7,$24,2         	 # Delay slot
9505		 addu  $7,$7,$30
9506		 lw    $7,0x00($7)
9507		 jr    $7
9508		 nop                    	 # Delay slot
9509
9510OP0_21fb:				#:
9511		 addiu $23,$23,2
9512
9513		 subu  $14,$23,$22       	 # Get PC
9514		 lhu   $7,0x00($23)
9515		 addiu $23,$23,2
9516		 seb   $6,$7
9517		 or    $25,$0,$7
9518		 srl   $7,$7,12
9519		 andi  $25,$25,0x0800
9520		 sll   $7,$7,2
9521		 addu  $7,$7,$21
9522		 bne   $25,$0,0f
9523		 lw    $25,0x00($7)      	 # Delay slot
9524		 seh   $25,$25
9525	0:
9526		 addu  $25,$14,$25
9527		 addu  $14,$25,$6
9528		 lw    $25,0xA0($21)
9529		 sw    $15,m68k_ICount
9530		 or    $4,$0,$14
9531		 jalr  $25
9532		 sw    $23,0x4C($21)    	 # Delay slot
9533		 lw    $15,m68k_ICount
9534		 and   $16,$0,$0        	 # Clear Carry
9535		 and   $17,$0,$0        	 # Clear Overflow
9536		 srl   $19,$2,31         	 # Set Sign
9537		 sltiu $18,$2,1         	 # Set Zero
9538		 lh    $14,0x00($23)
9539		 addiu $23,$23,2
9540		 lw    $25,0x90($21)
9541		 sw    $15,m68k_ICount
9542		 or    $5,$0,$2
9543		 or    $4,$0,$14
9544		 jalr  $25
9545		 sw    $23,0x4C($21)    	 # Delay slot
9546		 lw    $15,m68k_ICount
9547		 addiu $15,$15,-30
9548		 bgez  $15,3f
9549		 lhu   $24,0x00($23)    	 # Delay slot
9550		 j     MainExit
9551	3:
9552		 sll   $7,$24,2         	 # Delay slot
9553		 addu  $7,$7,$30
9554		 lw    $7,0x00($7)
9555		 jr    $7
9556		 nop                    	 # Delay slot
9557
9558OP0_21fc:				#:
9559		 addiu $23,$23,2
9560
9561		 lhu   $2,0x00($23)
9562		 lhu   $25,0x02($23)
9563		 sll   $2,$2,16
9564		 or    $2,$2,$25
9565		 addiu $23,$23,4
9566		 and   $16,$0,$0        	 # Clear Carry
9567		 and   $17,$0,$0        	 # Clear Overflow
9568		 srl   $19,$2,31         	 # Set Sign
9569		 sltiu $18,$2,1         	 # Set Zero
9570		 lh    $14,0x00($23)
9571		 addiu $23,$23,2
9572		 lw    $25,0x90($21)
9573		 sw    $15,m68k_ICount
9574		 or    $5,$0,$2
9575		 or    $4,$0,$14
9576		 jalr  $25
9577		 sw    $23,0x4C($21)    	 # Delay slot
9578		 lw    $15,m68k_ICount
9579		 addiu $15,$15,-16
9580		 bgez  $15,3f
9581		 lhu   $24,0x00($23)    	 # Delay slot
9582		 j     MainExit
9583	3:
9584		 sll   $7,$24,2         	 # Delay slot
9585		 addu  $7,$7,$30
9586		 lw    $7,0x00($7)
9587		 jr    $7
9588		 nop                    	 # Delay slot
9589
9590OP0_23c0:				#:
9591		 addiu $23,$23,2
9592
9593		 and   $8,$24,0x0f
9594		 sll   $8,$8,2
9595		 addu  $8,$8,$21
9596		 lw    $2,0x00($8)
9597		 and   $16,$0,$0        	 # Clear Carry
9598		 and   $17,$0,$0        	 # Clear Overflow
9599		 srl   $19,$2,31         	 # Set Sign
9600		 sltiu $18,$2,1         	 # Set Zero
9601		 lhu   $14,0x00($23)
9602		 lhu   $25,0x02($23)
9603		 sll   $14,$14,16
9604		 or    $14,$14,$25
9605		 addiu $23,$23,4
9606		 lw    $25,0x90($21)
9607		 sw    $15,m68k_ICount
9608		 or    $5,$0,$2
9609		 or    $4,$0,$14
9610		 jalr  $25
9611		 sw    $23,0x4C($21)    	 # Delay slot
9612		 lw    $15,m68k_ICount
9613		 addiu $15,$15,-20
9614		 bgez  $15,3f
9615		 lhu   $24,0x00($23)    	 # Delay slot
9616		 j     MainExit
9617	3:
9618		 sll   $7,$24,2         	 # Delay slot
9619		 addu  $7,$7,$30
9620		 lw    $7,0x00($7)
9621		 jr    $7
9622		 nop                    	 # Delay slot
9623
9624OP0_23d0:				#:
9625		 addiu $23,$23,2
9626
9627		 and   $8,$24,0x07
9628		 sll   $8,$8,2
9629		 addu  $8,$8,$21
9630		 lw    $14,0x20($8)
9631		 lw    $25,0x84($21)
9632		 sw    $15,m68k_ICount
9633		 or    $4,$0,$14
9634		 jalr  $25
9635		 sw    $23,0x4C($21)    	 # Delay slot
9636		 lw    $15,m68k_ICount
9637		 and   $16,$0,$0        	 # Clear Carry
9638		 and   $17,$0,$0        	 # Clear Overflow
9639		 srl   $19,$2,31         	 # Set Sign
9640		 sltiu $18,$2,1         	 # Set Zero
9641		 lhu   $14,0x00($23)
9642		 lhu   $25,0x02($23)
9643		 sll   $14,$14,16
9644		 or    $14,$14,$25
9645		 addiu $23,$23,4
9646		 lw    $25,0x90($21)
9647		 sw    $15,m68k_ICount
9648		 or    $5,$0,$2
9649		 or    $4,$0,$14
9650		 jalr  $25
9651		 sw    $23,0x4C($21)    	 # Delay slot
9652		 lw    $15,m68k_ICount
9653		 addiu $15,$15,-28
9654		 bgez  $15,3f
9655		 lhu   $24,0x00($23)    	 # Delay slot
9656		 j     MainExit
9657	3:
9658		 sll   $7,$24,2         	 # Delay slot
9659		 addu  $7,$7,$30
9660		 lw    $7,0x00($7)
9661		 jr    $7
9662		 nop                    	 # Delay slot
9663
9664OP0_23d8:				#:
9665		 addiu $23,$23,2
9666
9667		 and   $8,$24,0x07
9668		 sll   $8,$8,2
9669		 addu  $8,$8,$21
9670		 lw    $14,0x20($8)
9671		 addiu $25,$14,4
9672		 sw    $25,0x20($8)
9673		 lw    $25,0x84($21)
9674		 sw    $15,m68k_ICount
9675		 or    $4,$0,$14
9676		 jalr  $25
9677		 sw    $23,0x4C($21)    	 # Delay slot
9678		 lw    $15,m68k_ICount
9679		 and   $16,$0,$0        	 # Clear Carry
9680		 and   $17,$0,$0        	 # Clear Overflow
9681		 srl   $19,$2,31         	 # Set Sign
9682		 sltiu $18,$2,1         	 # Set Zero
9683		 lhu   $14,0x00($23)
9684		 lhu   $25,0x02($23)
9685		 sll   $14,$14,16
9686		 or    $14,$14,$25
9687		 addiu $23,$23,4
9688		 lw    $25,0x90($21)
9689		 sw    $15,m68k_ICount
9690		 or    $5,$0,$2
9691		 or    $4,$0,$14
9692		 jalr  $25
9693		 sw    $23,0x4C($21)    	 # Delay slot
9694		 lw    $15,m68k_ICount
9695		 addiu $15,$15,-28
9696		 bgez  $15,3f
9697		 lhu   $24,0x00($23)    	 # Delay slot
9698		 j     MainExit
9699	3:
9700		 sll   $7,$24,2         	 # Delay slot
9701		 addu  $7,$7,$30
9702		 lw    $7,0x00($7)
9703		 jr    $7
9704		 nop                    	 # Delay slot
9705
9706OP0_23e0:				#:
9707		 addiu $23,$23,2
9708
9709		 and   $8,$24,0x07
9710		 sll   $8,$8,2
9711		 addu  $8,$8,$21
9712		 lw    $14,0x20($8)
9713		 addiu $14,$14,-4
9714		 sw    $14,0x20($8)
9715		 lw    $25,0x84($21)
9716		 sw    $15,m68k_ICount
9717		 or    $4,$0,$14
9718		 jalr  $25
9719		 sw    $23,0x4C($21)    	 # Delay slot
9720		 lw    $15,m68k_ICount
9721		 and   $16,$0,$0        	 # Clear Carry
9722		 and   $17,$0,$0        	 # Clear Overflow
9723		 srl   $19,$2,31         	 # Set Sign
9724		 sltiu $18,$2,1         	 # Set Zero
9725		 lhu   $14,0x00($23)
9726		 lhu   $25,0x02($23)
9727		 sll   $14,$14,16
9728		 or    $14,$14,$25
9729		 addiu $23,$23,4
9730		 lw    $25,0x90($21)
9731		 sw    $15,m68k_ICount
9732		 or    $5,$0,$2
9733		 or    $4,$0,$14
9734		 jalr  $25
9735		 sw    $23,0x4C($21)    	 # Delay slot
9736		 lw    $15,m68k_ICount
9737		 addiu $15,$15,-30
9738		 bgez  $15,3f
9739		 lhu   $24,0x00($23)    	 # Delay slot
9740		 j     MainExit
9741	3:
9742		 sll   $7,$24,2         	 # Delay slot
9743		 addu  $7,$7,$30
9744		 lw    $7,0x00($7)
9745		 jr    $7
9746		 nop                    	 # Delay slot
9747
9748OP0_23e8:				#:
9749		 addiu $23,$23,2
9750
9751		 and   $8,$24,0x07
9752		 lh    $7,0x00($23)
9753		 sll   $8,$8,2
9754		 addu  $8,$8,$21
9755		 lw    $14,0x20($8)
9756		 addiu $23,$23,2
9757		 addu  $14,$14,$7
9758		 lw    $25,0x84($21)
9759		 sw    $15,m68k_ICount
9760		 or    $4,$0,$14
9761		 jalr  $25
9762		 sw    $23,0x4C($21)    	 # Delay slot
9763		 lw    $15,m68k_ICount
9764		 and   $16,$0,$0        	 # Clear Carry
9765		 and   $17,$0,$0        	 # Clear Overflow
9766		 srl   $19,$2,31         	 # Set Sign
9767		 sltiu $18,$2,1         	 # Set Zero
9768		 lhu   $14,0x00($23)
9769		 lhu   $25,0x02($23)
9770		 sll   $14,$14,16
9771		 or    $14,$14,$25
9772		 addiu $23,$23,4
9773		 lw    $25,0x90($21)
9774		 sw    $15,m68k_ICount
9775		 or    $5,$0,$2
9776		 or    $4,$0,$14
9777		 jalr  $25
9778		 sw    $23,0x4C($21)    	 # Delay slot
9779		 lw    $15,m68k_ICount
9780		 addiu $15,$15,-32
9781		 bgez  $15,3f
9782		 lhu   $24,0x00($23)    	 # Delay slot
9783		 j     MainExit
9784	3:
9785		 sll   $7,$24,2         	 # Delay slot
9786		 addu  $7,$7,$30
9787		 lw    $7,0x00($7)
9788		 jr    $7
9789		 nop                    	 # Delay slot
9790
9791OP0_23f0:				#:
9792		 addiu $23,$23,2
9793
9794		 and   $8,$24,0x07
9795		 sll   $8,$8,2
9796		 addu  $8,$8,$21
9797		 lw    $14,0x20($8)
9798		 lhu   $7,0x00($23)
9799		 addiu $23,$23,2
9800		 seb   $6,$7
9801		 or    $25,$0,$7
9802		 srl   $7,$7,12
9803		 andi  $25,$25,0x0800
9804		 sll   $7,$7,2
9805		 addu  $7,$7,$21
9806		 bne   $25,$0,0f
9807		 lw    $25,0x00($7)      	 # Delay slot
9808		 seh   $25,$25
9809	0:
9810		 addu  $25,$14,$25
9811		 addu  $14,$25,$6
9812		 lw    $25,0x84($21)
9813		 sw    $15,m68k_ICount
9814		 or    $4,$0,$14
9815		 jalr  $25
9816		 sw    $23,0x4C($21)    	 # Delay slot
9817		 lw    $15,m68k_ICount
9818		 and   $16,$0,$0        	 # Clear Carry
9819		 and   $17,$0,$0        	 # Clear Overflow
9820		 srl   $19,$2,31         	 # Set Sign
9821		 sltiu $18,$2,1         	 # Set Zero
9822		 lhu   $14,0x00($23)
9823		 lhu   $25,0x02($23)
9824		 sll   $14,$14,16
9825		 or    $14,$14,$25
9826		 addiu $23,$23,4
9827		 lw    $25,0x90($21)
9828		 sw    $15,m68k_ICount
9829		 or    $5,$0,$2
9830		 or    $4,$0,$14
9831		 jalr  $25
9832		 sw    $23,0x4C($21)    	 # Delay slot
9833		 lw    $15,m68k_ICount
9834		 addiu $15,$15,-34
9835		 bgez  $15,3f
9836		 lhu   $24,0x00($23)    	 # Delay slot
9837		 j     MainExit
9838	3:
9839		 sll   $7,$24,2         	 # Delay slot
9840		 addu  $7,$7,$30
9841		 lw    $7,0x00($7)
9842		 jr    $7
9843		 nop                    	 # Delay slot
9844
9845OP0_23f8:				#:
9846		 addiu $23,$23,2
9847
9848		 lh    $14,0x00($23)
9849		 addiu $23,$23,2
9850		 lw    $25,0x84($21)
9851		 sw    $15,m68k_ICount
9852		 or    $4,$0,$14
9853		 jalr  $25
9854		 sw    $23,0x4C($21)    	 # Delay slot
9855		 lw    $15,m68k_ICount
9856		 and   $16,$0,$0        	 # Clear Carry
9857		 and   $17,$0,$0        	 # Clear Overflow
9858		 srl   $19,$2,31         	 # Set Sign
9859		 sltiu $18,$2,1         	 # Set Zero
9860		 lhu   $14,0x00($23)
9861		 lhu   $25,0x02($23)
9862		 sll   $14,$14,16
9863		 or    $14,$14,$25
9864		 addiu $23,$23,4
9865		 lw    $25,0x90($21)
9866		 sw    $15,m68k_ICount
9867		 or    $5,$0,$2
9868		 or    $4,$0,$14
9869		 jalr  $25
9870		 sw    $23,0x4C($21)    	 # Delay slot
9871		 lw    $15,m68k_ICount
9872		 addiu $15,$15,-32
9873		 bgez  $15,3f
9874		 lhu   $24,0x00($23)    	 # Delay slot
9875		 j     MainExit
9876	3:
9877		 sll   $7,$24,2         	 # Delay slot
9878		 addu  $7,$7,$30
9879		 lw    $7,0x00($7)
9880		 jr    $7
9881		 nop                    	 # Delay slot
9882
9883OP0_23f9:				#:
9884		 addiu $23,$23,2
9885
9886		 lhu   $14,0x00($23)
9887		 lhu   $25,0x02($23)
9888		 sll   $14,$14,16
9889		 or    $14,$14,$25
9890		 addiu $23,$23,4
9891		 lw    $25,0x84($21)
9892		 sw    $15,m68k_ICount
9893		 or    $4,$0,$14
9894		 jalr  $25
9895		 sw    $23,0x4C($21)    	 # Delay slot
9896		 lw    $15,m68k_ICount
9897		 and   $16,$0,$0        	 # Clear Carry
9898		 and   $17,$0,$0        	 # Clear Overflow
9899		 srl   $19,$2,31         	 # Set Sign
9900		 sltiu $18,$2,1         	 # Set Zero
9901		 lhu   $14,0x00($23)
9902		 lhu   $25,0x02($23)
9903		 sll   $14,$14,16
9904		 or    $14,$14,$25
9905		 addiu $23,$23,4
9906		 lw    $25,0x90($21)
9907		 sw    $15,m68k_ICount
9908		 or    $5,$0,$2
9909		 or    $4,$0,$14
9910		 jalr  $25
9911		 sw    $23,0x4C($21)    	 # Delay slot
9912		 lw    $15,m68k_ICount
9913		 addiu $15,$15,-36
9914		 bgez  $15,3f
9915		 lhu   $24,0x00($23)    	 # Delay slot
9916		 j     MainExit
9917	3:
9918		 sll   $7,$24,2         	 # Delay slot
9919		 addu  $7,$7,$30
9920		 lw    $7,0x00($7)
9921		 jr    $7
9922		 nop                    	 # Delay slot
9923
9924OP0_23fa:				#:
9925		 addiu $23,$23,2
9926
9927		 lh    $7,0x00($23)
9928		 subu  $25,$23,$22
9929		 addu  $14,$25,$7       	 # Add Offset to PC
9930		 addiu $23,$23,2
9931		 lw    $25,0xA0($21)
9932		 sw    $15,m68k_ICount
9933		 or    $4,$0,$14
9934		 jalr  $25
9935		 sw    $23,0x4C($21)    	 # Delay slot
9936		 lw    $15,m68k_ICount
9937		 and   $16,$0,$0        	 # Clear Carry
9938		 and   $17,$0,$0        	 # Clear Overflow
9939		 srl   $19,$2,31         	 # Set Sign
9940		 sltiu $18,$2,1         	 # Set Zero
9941		 lhu   $14,0x00($23)
9942		 lhu   $25,0x02($23)
9943		 sll   $14,$14,16
9944		 or    $14,$14,$25
9945		 addiu $23,$23,4
9946		 lw    $25,0x90($21)
9947		 sw    $15,m68k_ICount
9948		 or    $5,$0,$2
9949		 or    $4,$0,$14
9950		 jalr  $25
9951		 sw    $23,0x4C($21)    	 # Delay slot
9952		 lw    $15,m68k_ICount
9953		 addiu $15,$15,-32
9954		 bgez  $15,3f
9955		 lhu   $24,0x00($23)    	 # Delay slot
9956		 j     MainExit
9957	3:
9958		 sll   $7,$24,2         	 # Delay slot
9959		 addu  $7,$7,$30
9960		 lw    $7,0x00($7)
9961		 jr    $7
9962		 nop                    	 # Delay slot
9963
9964OP0_23fb:				#:
9965		 addiu $23,$23,2
9966
9967		 subu  $14,$23,$22       	 # Get PC
9968		 lhu   $7,0x00($23)
9969		 addiu $23,$23,2
9970		 seb   $6,$7
9971		 or    $25,$0,$7
9972		 srl   $7,$7,12
9973		 andi  $25,$25,0x0800
9974		 sll   $7,$7,2
9975		 addu  $7,$7,$21
9976		 bne   $25,$0,0f
9977		 lw    $25,0x00($7)      	 # Delay slot
9978		 seh   $25,$25
9979	0:
9980		 addu  $25,$14,$25
9981		 addu  $14,$25,$6
9982		 lw    $25,0xA0($21)
9983		 sw    $15,m68k_ICount
9984		 or    $4,$0,$14
9985		 jalr  $25
9986		 sw    $23,0x4C($21)    	 # Delay slot
9987		 lw    $15,m68k_ICount
9988		 and   $16,$0,$0        	 # Clear Carry
9989		 and   $17,$0,$0        	 # Clear Overflow
9990		 srl   $19,$2,31         	 # Set Sign
9991		 sltiu $18,$2,1         	 # Set Zero
9992		 lhu   $14,0x00($23)
9993		 lhu   $25,0x02($23)
9994		 sll   $14,$14,16
9995		 or    $14,$14,$25
9996		 addiu $23,$23,4
9997		 lw    $25,0x90($21)
9998		 sw    $15,m68k_ICount
9999		 or    $5,$0,$2
10000		 or    $4,$0,$14
10001		 jalr  $25
10002		 sw    $23,0x4C($21)    	 # Delay slot
10003		 lw    $15,m68k_ICount
10004		 addiu $15,$15,-34
10005		 bgez  $15,3f
10006		 lhu   $24,0x00($23)    	 # Delay slot
10007		 j     MainExit
10008	3:
10009		 sll   $7,$24,2         	 # Delay slot
10010		 addu  $7,$7,$30
10011		 lw    $7,0x00($7)
10012		 jr    $7
10013		 nop                    	 # Delay slot
10014
10015OP0_23fc:				#:
10016		 addiu $23,$23,2
10017
10018		 lhu   $2,0x00($23)
10019		 lhu   $25,0x02($23)
10020		 sll   $2,$2,16
10021		 or    $2,$2,$25
10022		 addiu $23,$23,4
10023		 and   $16,$0,$0        	 # Clear Carry
10024		 and   $17,$0,$0        	 # Clear Overflow
10025		 srl   $19,$2,31         	 # Set Sign
10026		 sltiu $18,$2,1         	 # Set Zero
10027		 lhu   $14,0x00($23)
10028		 lhu   $25,0x02($23)
10029		 sll   $14,$14,16
10030		 or    $14,$14,$25
10031		 addiu $23,$23,4
10032		 lw    $25,0x90($21)
10033		 sw    $15,m68k_ICount
10034		 or    $5,$0,$2
10035		 or    $4,$0,$14
10036		 jalr  $25
10037		 sw    $23,0x4C($21)    	 # Delay slot
10038		 lw    $15,m68k_ICount
10039		 addiu $15,$15,-20
10040		 bgez  $15,3f
10041		 lhu   $24,0x00($23)    	 # Delay slot
10042		 j     MainExit
10043	3:
10044		 sll   $7,$24,2         	 # Delay slot
10045		 addu  $7,$7,$30
10046		 lw    $7,0x00($7)
10047		 jr    $7
10048		 nop                    	 # Delay slot
10049
10050OP0_3000:				#:
10051		 addiu $23,$23,2
10052
10053		 and   $8,$24,0x0f
10054		 sll   $8,$8,2
10055		 addu  $8,$8,$21
10056		 lhu   $2,0x00($8)
10057		 and   $16,$0,$0        	 # Clear Carry
10058		 and   $17,$0,$0        	 # Clear Overflow
10059		 srl   $19,$2,15         	 # Set Sign
10060		 sltiu $18,$2,1         	 # Set Zero
10061		 srl   $24,$24,7
10062		 andi  $24,$24,0x1C
10063		 addu  $24,$24,$21
10064		 sh    $2,0x00($24)
10065		 addiu $15,$15,-4
10066		 bgez  $15,3f
10067		 lhu   $24,0x00($23)    	 # Delay slot
10068		 j     MainExit
10069	3:
10070		 sll   $7,$24,2         	 # Delay slot
10071		 addu  $7,$7,$30
10072		 lw    $7,0x00($7)
10073		 jr    $7
10074		 nop                    	 # Delay slot
10075
10076OP0_3010:				#:
10077		 addiu $23,$23,2
10078
10079		 and   $8,$24,0x07
10080		 sll   $8,$8,2
10081		 addu  $8,$8,$21
10082		 lw    $14,0x20($8)
10083		 lw    $25,0x80($21)
10084		 sw    $15,m68k_ICount
10085		 sw    $24,0x44($29)
10086		 or    $4,$0,$14
10087		 jalr  $25
10088		 sw    $23,0x4C($21)    	 # Delay slot
10089		 lw    $24,0x44($29)
10090		 lw    $15,m68k_ICount
10091		 and   $16,$0,$0        	 # Clear Carry
10092		 and   $17,$0,$0        	 # Clear Overflow
10093		 srl   $19,$2,15         	 # Set Sign
10094		 sltiu $18,$2,1         	 # Set Zero
10095		 srl   $24,$24,7
10096		 andi  $24,$24,0x1C
10097		 addu  $24,$24,$21
10098		 sh    $2,0x00($24)
10099		 addiu $15,$15,-8
10100		 bgez  $15,3f
10101		 lhu   $24,0x00($23)    	 # Delay slot
10102		 j     MainExit
10103	3:
10104		 sll   $7,$24,2         	 # Delay slot
10105		 addu  $7,$7,$30
10106		 lw    $7,0x00($7)
10107		 jr    $7
10108		 nop                    	 # Delay slot
10109
10110OP0_3018:				#:
10111		 addiu $23,$23,2
10112
10113		 and   $8,$24,0x07
10114		 sll   $8,$8,2
10115		 addu  $8,$8,$21
10116		 lw    $14,0x20($8)
10117		 addiu $25,$14,2
10118		 sw    $25,0x20($8)
10119		 lw    $25,0x80($21)
10120		 sw    $15,m68k_ICount
10121		 sw    $24,0x44($29)
10122		 or    $4,$0,$14
10123		 jalr  $25
10124		 sw    $23,0x4C($21)    	 # Delay slot
10125		 lw    $24,0x44($29)
10126		 lw    $15,m68k_ICount
10127		 and   $16,$0,$0        	 # Clear Carry
10128		 and   $17,$0,$0        	 # Clear Overflow
10129		 srl   $19,$2,15         	 # Set Sign
10130		 sltiu $18,$2,1         	 # Set Zero
10131		 srl   $24,$24,7
10132		 andi  $24,$24,0x1C
10133		 addu  $24,$24,$21
10134		 sh    $2,0x00($24)
10135		 addiu $15,$15,-8
10136		 bgez  $15,3f
10137		 lhu   $24,0x00($23)    	 # Delay slot
10138		 j     MainExit
10139	3:
10140		 sll   $7,$24,2         	 # Delay slot
10141		 addu  $7,$7,$30
10142		 lw    $7,0x00($7)
10143		 jr    $7
10144		 nop                    	 # Delay slot
10145
10146OP0_3020:				#:
10147		 addiu $23,$23,2
10148
10149		 and   $8,$24,0x07
10150		 sll   $8,$8,2
10151		 addu  $8,$8,$21
10152		 lw    $14,0x20($8)
10153		 addiu $14,$14,-2
10154		 sw    $14,0x20($8)
10155		 lw    $25,0x80($21)
10156		 sw    $15,m68k_ICount
10157		 sw    $24,0x44($29)
10158		 or    $4,$0,$14
10159		 jalr  $25
10160		 sw    $23,0x4C($21)    	 # Delay slot
10161		 lw    $24,0x44($29)
10162		 lw    $15,m68k_ICount
10163		 and   $16,$0,$0        	 # Clear Carry
10164		 and   $17,$0,$0        	 # Clear Overflow
10165		 srl   $19,$2,15         	 # Set Sign
10166		 sltiu $18,$2,1         	 # Set Zero
10167		 srl   $24,$24,7
10168		 andi  $24,$24,0x1C
10169		 addu  $24,$24,$21
10170		 sh    $2,0x00($24)
10171		 addiu $15,$15,-10
10172		 bgez  $15,3f
10173		 lhu   $24,0x00($23)    	 # Delay slot
10174		 j     MainExit
10175	3:
10176		 sll   $7,$24,2         	 # Delay slot
10177		 addu  $7,$7,$30
10178		 lw    $7,0x00($7)
10179		 jr    $7
10180		 nop                    	 # Delay slot
10181
10182OP0_3028:				#:
10183		 addiu $23,$23,2
10184
10185		 and   $8,$24,0x07
10186		 lh    $7,0x00($23)
10187		 sll   $8,$8,2
10188		 addu  $8,$8,$21
10189		 lw    $14,0x20($8)
10190		 addiu $23,$23,2
10191		 addu  $14,$14,$7
10192		 lw    $25,0x80($21)
10193		 sw    $15,m68k_ICount
10194		 sw    $24,0x44($29)
10195		 or    $4,$0,$14
10196		 jalr  $25
10197		 sw    $23,0x4C($21)    	 # Delay slot
10198		 lw    $24,0x44($29)
10199		 lw    $15,m68k_ICount
10200		 and   $16,$0,$0        	 # Clear Carry
10201		 and   $17,$0,$0        	 # Clear Overflow
10202		 srl   $19,$2,15         	 # Set Sign
10203		 sltiu $18,$2,1         	 # Set Zero
10204		 srl   $24,$24,7
10205		 andi  $24,$24,0x1C
10206		 addu  $24,$24,$21
10207		 sh    $2,0x00($24)
10208		 addiu $15,$15,-12
10209		 bgez  $15,3f
10210		 lhu   $24,0x00($23)    	 # Delay slot
10211		 j     MainExit
10212	3:
10213		 sll   $7,$24,2         	 # Delay slot
10214		 addu  $7,$7,$30
10215		 lw    $7,0x00($7)
10216		 jr    $7
10217		 nop                    	 # Delay slot
10218
10219OP0_3030:				#:
10220		 addiu $23,$23,2
10221
10222		 and   $8,$24,0x07
10223		 sll   $8,$8,2
10224		 addu  $8,$8,$21
10225		 lw    $14,0x20($8)
10226		 lhu   $7,0x00($23)
10227		 addiu $23,$23,2
10228		 seb   $6,$7
10229		 or    $25,$0,$7
10230		 srl   $7,$7,12
10231		 andi  $25,$25,0x0800
10232		 sll   $7,$7,2
10233		 addu  $7,$7,$21
10234		 bne   $25,$0,0f
10235		 lw    $25,0x00($7)      	 # Delay slot
10236		 seh   $25,$25
10237	0:
10238		 addu  $25,$14,$25
10239		 addu  $14,$25,$6
10240		 lw    $25,0x80($21)
10241		 sw    $15,m68k_ICount
10242		 sw    $24,0x44($29)
10243		 or    $4,$0,$14
10244		 jalr  $25
10245		 sw    $23,0x4C($21)    	 # Delay slot
10246		 lw    $24,0x44($29)
10247		 lw    $15,m68k_ICount
10248		 and   $16,$0,$0        	 # Clear Carry
10249		 and   $17,$0,$0        	 # Clear Overflow
10250		 srl   $19,$2,15         	 # Set Sign
10251		 sltiu $18,$2,1         	 # Set Zero
10252		 srl   $24,$24,7
10253		 andi  $24,$24,0x1C
10254		 addu  $24,$24,$21
10255		 sh    $2,0x00($24)
10256		 addiu $15,$15,-14
10257		 bgez  $15,3f
10258		 lhu   $24,0x00($23)    	 # Delay slot
10259		 j     MainExit
10260	3:
10261		 sll   $7,$24,2         	 # Delay slot
10262		 addu  $7,$7,$30
10263		 lw    $7,0x00($7)
10264		 jr    $7
10265		 nop                    	 # Delay slot
10266
10267OP0_3038:				#:
10268		 addiu $23,$23,2
10269
10270		 lh    $14,0x00($23)
10271		 addiu $23,$23,2
10272		 lw    $25,0x80($21)
10273		 sw    $15,m68k_ICount
10274		 sw    $24,0x44($29)
10275		 or    $4,$0,$14
10276		 jalr  $25
10277		 sw    $23,0x4C($21)    	 # Delay slot
10278		 lw    $24,0x44($29)
10279		 lw    $15,m68k_ICount
10280		 and   $16,$0,$0        	 # Clear Carry
10281		 and   $17,$0,$0        	 # Clear Overflow
10282		 srl   $19,$2,15         	 # Set Sign
10283		 sltiu $18,$2,1         	 # Set Zero
10284		 srl   $24,$24,7
10285		 andi  $24,$24,0x1C
10286		 addu  $24,$24,$21
10287		 sh    $2,0x00($24)
10288		 addiu $15,$15,-12
10289		 bgez  $15,3f
10290		 lhu   $24,0x00($23)    	 # Delay slot
10291		 j     MainExit
10292	3:
10293		 sll   $7,$24,2         	 # Delay slot
10294		 addu  $7,$7,$30
10295		 lw    $7,0x00($7)
10296		 jr    $7
10297		 nop                    	 # Delay slot
10298
10299OP0_3039:				#:
10300		 addiu $23,$23,2
10301
10302		 lhu   $14,0x00($23)
10303		 lhu   $25,0x02($23)
10304		 sll   $14,$14,16
10305		 or    $14,$14,$25
10306		 addiu $23,$23,4
10307		 lw    $25,0x80($21)
10308		 sw    $15,m68k_ICount
10309		 sw    $24,0x44($29)
10310		 or    $4,$0,$14
10311		 jalr  $25
10312		 sw    $23,0x4C($21)    	 # Delay slot
10313		 lw    $24,0x44($29)
10314		 lw    $15,m68k_ICount
10315		 and   $16,$0,$0        	 # Clear Carry
10316		 and   $17,$0,$0        	 # Clear Overflow
10317		 srl   $19,$2,15         	 # Set Sign
10318		 sltiu $18,$2,1         	 # Set Zero
10319		 srl   $24,$24,7
10320		 andi  $24,$24,0x1C
10321		 addu  $24,$24,$21
10322		 sh    $2,0x00($24)
10323		 addiu $15,$15,-16
10324		 bgez  $15,3f
10325		 lhu   $24,0x00($23)    	 # Delay slot
10326		 j     MainExit
10327	3:
10328		 sll   $7,$24,2         	 # Delay slot
10329		 addu  $7,$7,$30
10330		 lw    $7,0x00($7)
10331		 jr    $7
10332		 nop                    	 # Delay slot
10333
10334OP0_303a:				#:
10335		 addiu $23,$23,2
10336
10337		 lh    $7,0x00($23)
10338		 subu  $25,$23,$22
10339		 addu  $14,$25,$7       	 # Add Offset to PC
10340		 addiu $23,$23,2
10341		 lw    $25,0x9C($21)
10342		 sw    $15,m68k_ICount
10343		 sw    $24,0x44($29)
10344		 or    $4,$0,$14
10345		 jalr  $25
10346		 sw    $23,0x4C($21)    	 # Delay slot
10347		 lw    $24,0x44($29)
10348		 lw    $15,m68k_ICount
10349		 and   $16,$0,$0        	 # Clear Carry
10350		 and   $17,$0,$0        	 # Clear Overflow
10351		 srl   $19,$2,15         	 # Set Sign
10352		 sltiu $18,$2,1         	 # Set Zero
10353		 srl   $24,$24,7
10354		 andi  $24,$24,0x1C
10355		 addu  $24,$24,$21
10356		 sh    $2,0x00($24)
10357		 addiu $15,$15,-12
10358		 bgez  $15,3f
10359		 lhu   $24,0x00($23)    	 # Delay slot
10360		 j     MainExit
10361	3:
10362		 sll   $7,$24,2         	 # Delay slot
10363		 addu  $7,$7,$30
10364		 lw    $7,0x00($7)
10365		 jr    $7
10366		 nop                    	 # Delay slot
10367
10368OP0_303b:				#:
10369		 addiu $23,$23,2
10370
10371		 subu  $14,$23,$22       	 # Get PC
10372		 lhu   $7,0x00($23)
10373		 addiu $23,$23,2
10374		 seb   $6,$7
10375		 or    $25,$0,$7
10376		 srl   $7,$7,12
10377		 andi  $25,$25,0x0800
10378		 sll   $7,$7,2
10379		 addu  $7,$7,$21
10380		 bne   $25,$0,0f
10381		 lw    $25,0x00($7)      	 # Delay slot
10382		 seh   $25,$25
10383	0:
10384		 addu  $25,$14,$25
10385		 addu  $14,$25,$6
10386		 lw    $25,0x9C($21)
10387		 sw    $15,m68k_ICount
10388		 sw    $24,0x44($29)
10389		 or    $4,$0,$14
10390		 jalr  $25
10391		 sw    $23,0x4C($21)    	 # Delay slot
10392		 lw    $24,0x44($29)
10393		 lw    $15,m68k_ICount
10394		 and   $16,$0,$0        	 # Clear Carry
10395		 and   $17,$0,$0        	 # Clear Overflow
10396		 srl   $19,$2,15         	 # Set Sign
10397		 sltiu $18,$2,1         	 # Set Zero
10398		 srl   $24,$24,7
10399		 andi  $24,$24,0x1C
10400		 addu  $24,$24,$21
10401		 sh    $2,0x00($24)
10402		 addiu $15,$15,-14
10403		 bgez  $15,3f
10404		 lhu   $24,0x00($23)    	 # Delay slot
10405		 j     MainExit
10406	3:
10407		 sll   $7,$24,2         	 # Delay slot
10408		 addu  $7,$7,$30
10409		 lw    $7,0x00($7)
10410		 jr    $7
10411		 nop                    	 # Delay slot
10412
10413OP0_303c:				#:
10414		 addiu $23,$23,2
10415
10416		 lhu   $2,0x00($23)
10417		 addiu $23,$23,2
10418		 and   $16,$0,$0        	 # Clear Carry
10419		 and   $17,$0,$0        	 # Clear Overflow
10420		 srl   $19,$2,15         	 # Set Sign
10421		 sltiu $18,$2,1         	 # Set Zero
10422		 srl   $24,$24,7
10423		 andi  $24,$24,0x1C
10424		 addu  $24,$24,$21
10425		 sh    $2,0x00($24)
10426		 addiu $15,$15,-4
10427		 bgez  $15,3f
10428		 lhu   $24,0x00($23)    	 # Delay slot
10429		 j     MainExit
10430	3:
10431		 sll   $7,$24,2         	 # Delay slot
10432		 addu  $7,$7,$30
10433		 lw    $7,0x00($7)
10434		 jr    $7
10435		 nop                    	 # Delay slot
10436
10437OP0_3040:				#:
10438		 addiu $23,$23,2
10439
10440		 and   $8,$24,0x0f
10441		 sll   $8,$8,2
10442		 addu  $8,$8,$21
10443		 lhu   $2,0x00($8)
10444		 srl   $24,$24,7
10445		 andi  $24,$24,0x1C
10446		 seh   $2,$2
10447		 addu  $24,$24,$21
10448		 sw    $2,0x20($24)
10449		 addiu $15,$15,-4
10450		 bgez  $15,3f
10451		 lhu   $24,0x00($23)    	 # Delay slot
10452		 j     MainExit
10453	3:
10454		 sll   $7,$24,2         	 # Delay slot
10455		 addu  $7,$7,$30
10456		 lw    $7,0x00($7)
10457		 jr    $7
10458		 nop                    	 # Delay slot
10459
10460OP0_3050:				#:
10461		 addiu $23,$23,2
10462
10463		 and   $8,$24,0x07
10464		 sll   $8,$8,2
10465		 addu  $8,$8,$21
10466		 lw    $14,0x20($8)
10467		 lw    $25,0x80($21)
10468		 sw    $15,m68k_ICount
10469		 sw    $24,0x44($29)
10470		 or    $4,$0,$14
10471		 jalr  $25
10472		 sw    $23,0x4C($21)    	 # Delay slot
10473		 lw    $24,0x44($29)
10474		 lw    $15,m68k_ICount
10475		 srl   $24,$24,7
10476		 andi  $24,$24,0x1C
10477		 seh   $2,$2
10478		 addu  $24,$24,$21
10479		 sw    $2,0x20($24)
10480		 addiu $15,$15,-8
10481		 bgez  $15,3f
10482		 lhu   $24,0x00($23)    	 # Delay slot
10483		 j     MainExit
10484	3:
10485		 sll   $7,$24,2         	 # Delay slot
10486		 addu  $7,$7,$30
10487		 lw    $7,0x00($7)
10488		 jr    $7
10489		 nop                    	 # Delay slot
10490
10491OP0_3058:				#:
10492		 addiu $23,$23,2
10493
10494		 and   $8,$24,0x07
10495		 sll   $8,$8,2
10496		 addu  $8,$8,$21
10497		 lw    $14,0x20($8)
10498		 addiu $25,$14,2
10499		 sw    $25,0x20($8)
10500		 lw    $25,0x80($21)
10501		 sw    $15,m68k_ICount
10502		 sw    $24,0x44($29)
10503		 or    $4,$0,$14
10504		 jalr  $25
10505		 sw    $23,0x4C($21)    	 # Delay slot
10506		 lw    $24,0x44($29)
10507		 lw    $15,m68k_ICount
10508		 srl   $24,$24,7
10509		 andi  $24,$24,0x1C
10510		 seh   $2,$2
10511		 addu  $24,$24,$21
10512		 sw    $2,0x20($24)
10513		 addiu $15,$15,-8
10514		 bgez  $15,3f
10515		 lhu   $24,0x00($23)    	 # Delay slot
10516		 j     MainExit
10517	3:
10518		 sll   $7,$24,2         	 # Delay slot
10519		 addu  $7,$7,$30
10520		 lw    $7,0x00($7)
10521		 jr    $7
10522		 nop                    	 # Delay slot
10523
10524OP0_3060:				#:
10525		 addiu $23,$23,2
10526
10527		 and   $8,$24,0x07
10528		 sll   $8,$8,2
10529		 addu  $8,$8,$21
10530		 lw    $14,0x20($8)
10531		 addiu $14,$14,-2
10532		 sw    $14,0x20($8)
10533		 lw    $25,0x80($21)
10534		 sw    $15,m68k_ICount
10535		 sw    $24,0x44($29)
10536		 or    $4,$0,$14
10537		 jalr  $25
10538		 sw    $23,0x4C($21)    	 # Delay slot
10539		 lw    $24,0x44($29)
10540		 lw    $15,m68k_ICount
10541		 srl   $24,$24,7
10542		 andi  $24,$24,0x1C
10543		 seh   $2,$2
10544		 addu  $24,$24,$21
10545		 sw    $2,0x20($24)
10546		 addiu $15,$15,-10
10547		 bgez  $15,3f
10548		 lhu   $24,0x00($23)    	 # Delay slot
10549		 j     MainExit
10550	3:
10551		 sll   $7,$24,2         	 # Delay slot
10552		 addu  $7,$7,$30
10553		 lw    $7,0x00($7)
10554		 jr    $7
10555		 nop                    	 # Delay slot
10556
10557OP0_3068:				#:
10558		 addiu $23,$23,2
10559
10560		 and   $8,$24,0x07
10561		 lh    $7,0x00($23)
10562		 sll   $8,$8,2
10563		 addu  $8,$8,$21
10564		 lw    $14,0x20($8)
10565		 addiu $23,$23,2
10566		 addu  $14,$14,$7
10567		 lw    $25,0x80($21)
10568		 sw    $15,m68k_ICount
10569		 sw    $24,0x44($29)
10570		 or    $4,$0,$14
10571		 jalr  $25
10572		 sw    $23,0x4C($21)    	 # Delay slot
10573		 lw    $24,0x44($29)
10574		 lw    $15,m68k_ICount
10575		 srl   $24,$24,7
10576		 andi  $24,$24,0x1C
10577		 seh   $2,$2
10578		 addu  $24,$24,$21
10579		 sw    $2,0x20($24)
10580		 addiu $15,$15,-12
10581		 bgez  $15,3f
10582		 lhu   $24,0x00($23)    	 # Delay slot
10583		 j     MainExit
10584	3:
10585		 sll   $7,$24,2         	 # Delay slot
10586		 addu  $7,$7,$30
10587		 lw    $7,0x00($7)
10588		 jr    $7
10589		 nop                    	 # Delay slot
10590
10591OP0_3070:				#:
10592		 addiu $23,$23,2
10593
10594		 and   $8,$24,0x07
10595		 sll   $8,$8,2
10596		 addu  $8,$8,$21
10597		 lw    $14,0x20($8)
10598		 lhu   $7,0x00($23)
10599		 addiu $23,$23,2
10600		 seb   $6,$7
10601		 or    $25,$0,$7
10602		 srl   $7,$7,12
10603		 andi  $25,$25,0x0800
10604		 sll   $7,$7,2
10605		 addu  $7,$7,$21
10606		 bne   $25,$0,0f
10607		 lw    $25,0x00($7)      	 # Delay slot
10608		 seh   $25,$25
10609	0:
10610		 addu  $25,$14,$25
10611		 addu  $14,$25,$6
10612		 lw    $25,0x80($21)
10613		 sw    $15,m68k_ICount
10614		 sw    $24,0x44($29)
10615		 or    $4,$0,$14
10616		 jalr  $25
10617		 sw    $23,0x4C($21)    	 # Delay slot
10618		 lw    $24,0x44($29)
10619		 lw    $15,m68k_ICount
10620		 srl   $24,$24,7
10621		 andi  $24,$24,0x1C
10622		 seh   $2,$2
10623		 addu  $24,$24,$21
10624		 sw    $2,0x20($24)
10625		 addiu $15,$15,-14
10626		 bgez  $15,3f
10627		 lhu   $24,0x00($23)    	 # Delay slot
10628		 j     MainExit
10629	3:
10630		 sll   $7,$24,2         	 # Delay slot
10631		 addu  $7,$7,$30
10632		 lw    $7,0x00($7)
10633		 jr    $7
10634		 nop                    	 # Delay slot
10635
10636OP0_3078:				#:
10637		 addiu $23,$23,2
10638
10639		 lh    $14,0x00($23)
10640		 addiu $23,$23,2
10641		 lw    $25,0x80($21)
10642		 sw    $15,m68k_ICount
10643		 sw    $24,0x44($29)
10644		 or    $4,$0,$14
10645		 jalr  $25
10646		 sw    $23,0x4C($21)    	 # Delay slot
10647		 lw    $24,0x44($29)
10648		 lw    $15,m68k_ICount
10649		 srl   $24,$24,7
10650		 andi  $24,$24,0x1C
10651		 seh   $2,$2
10652		 addu  $24,$24,$21
10653		 sw    $2,0x20($24)
10654		 addiu $15,$15,-12
10655		 bgez  $15,3f
10656		 lhu   $24,0x00($23)    	 # Delay slot
10657		 j     MainExit
10658	3:
10659		 sll   $7,$24,2         	 # Delay slot
10660		 addu  $7,$7,$30
10661		 lw    $7,0x00($7)
10662		 jr    $7
10663		 nop                    	 # Delay slot
10664
10665OP0_3079:				#:
10666		 addiu $23,$23,2
10667
10668		 lhu   $14,0x00($23)
10669		 lhu   $25,0x02($23)
10670		 sll   $14,$14,16
10671		 or    $14,$14,$25
10672		 addiu $23,$23,4
10673		 lw    $25,0x80($21)
10674		 sw    $15,m68k_ICount
10675		 sw    $24,0x44($29)
10676		 or    $4,$0,$14
10677		 jalr  $25
10678		 sw    $23,0x4C($21)    	 # Delay slot
10679		 lw    $24,0x44($29)
10680		 lw    $15,m68k_ICount
10681		 srl   $24,$24,7
10682		 andi  $24,$24,0x1C
10683		 seh   $2,$2
10684		 addu  $24,$24,$21
10685		 sw    $2,0x20($24)
10686		 addiu $15,$15,-16
10687		 bgez  $15,3f
10688		 lhu   $24,0x00($23)    	 # Delay slot
10689		 j     MainExit
10690	3:
10691		 sll   $7,$24,2         	 # Delay slot
10692		 addu  $7,$7,$30
10693		 lw    $7,0x00($7)
10694		 jr    $7
10695		 nop                    	 # Delay slot
10696
10697OP0_307a:				#:
10698		 addiu $23,$23,2
10699
10700		 lh    $7,0x00($23)
10701		 subu  $25,$23,$22
10702		 addu  $14,$25,$7       	 # Add Offset to PC
10703		 addiu $23,$23,2
10704		 lw    $25,0x9C($21)
10705		 sw    $15,m68k_ICount
10706		 sw    $24,0x44($29)
10707		 or    $4,$0,$14
10708		 jalr  $25
10709		 sw    $23,0x4C($21)    	 # Delay slot
10710		 lw    $24,0x44($29)
10711		 lw    $15,m68k_ICount
10712		 srl   $24,$24,7
10713		 andi  $24,$24,0x1C
10714		 seh   $2,$2
10715		 addu  $24,$24,$21
10716		 sw    $2,0x20($24)
10717		 addiu $15,$15,-12
10718		 bgez  $15,3f
10719		 lhu   $24,0x00($23)    	 # Delay slot
10720		 j     MainExit
10721	3:
10722		 sll   $7,$24,2         	 # Delay slot
10723		 addu  $7,$7,$30
10724		 lw    $7,0x00($7)
10725		 jr    $7
10726		 nop                    	 # Delay slot
10727
10728OP0_307b:				#:
10729		 addiu $23,$23,2
10730
10731		 subu  $14,$23,$22       	 # Get PC
10732		 lhu   $7,0x00($23)
10733		 addiu $23,$23,2
10734		 seb   $6,$7
10735		 or    $25,$0,$7
10736		 srl   $7,$7,12
10737		 andi  $25,$25,0x0800
10738		 sll   $7,$7,2
10739		 addu  $7,$7,$21
10740		 bne   $25,$0,0f
10741		 lw    $25,0x00($7)      	 # Delay slot
10742		 seh   $25,$25
10743	0:
10744		 addu  $25,$14,$25
10745		 addu  $14,$25,$6
10746		 lw    $25,0x9C($21)
10747		 sw    $15,m68k_ICount
10748		 sw    $24,0x44($29)
10749		 or    $4,$0,$14
10750		 jalr  $25
10751		 sw    $23,0x4C($21)    	 # Delay slot
10752		 lw    $24,0x44($29)
10753		 lw    $15,m68k_ICount
10754		 srl   $24,$24,7
10755		 andi  $24,$24,0x1C
10756		 seh   $2,$2
10757		 addu  $24,$24,$21
10758		 sw    $2,0x20($24)
10759		 addiu $15,$15,-14
10760		 bgez  $15,3f
10761		 lhu   $24,0x00($23)    	 # Delay slot
10762		 j     MainExit
10763	3:
10764		 sll   $7,$24,2         	 # Delay slot
10765		 addu  $7,$7,$30
10766		 lw    $7,0x00($7)
10767		 jr    $7
10768		 nop                    	 # Delay slot
10769
10770OP0_307c:				#:
10771		 addiu $23,$23,2
10772
10773		 lhu   $2,0x00($23)
10774		 addiu $23,$23,2
10775		 srl   $24,$24,7
10776		 andi  $24,$24,0x1C
10777		 seh   $2,$2
10778		 addu  $24,$24,$21
10779		 sw    $2,0x20($24)
10780		 addiu $15,$15,-4
10781		 bgez  $15,3f
10782		 lhu   $24,0x00($23)    	 # Delay slot
10783		 j     MainExit
10784	3:
10785		 sll   $7,$24,2         	 # Delay slot
10786		 addu  $7,$7,$30
10787		 lw    $7,0x00($7)
10788		 jr    $7
10789		 nop                    	 # Delay slot
10790
10791OP0_3080:				#:
10792		 addiu $23,$23,2
10793
10794		 and   $8,$24,0x0f
10795		 sll   $8,$8,2
10796		 addu  $8,$8,$21
10797		 lhu   $2,0x00($8)
10798		 and   $16,$0,$0        	 # Clear Carry
10799		 and   $17,$0,$0        	 # Clear Overflow
10800		 srl   $19,$2,15         	 # Set Sign
10801		 sltiu $18,$2,1         	 # Set Zero
10802		 srl   $24,$24,7
10803		 andi  $24,$24,0x1C
10804		 addu  $24,$24,$21
10805		 lw    $14,0x20($24)
10806		 lw    $25,0x8C($21)
10807		 sw    $15,m68k_ICount
10808		 or    $5,$0,$2
10809		 or    $4,$0,$14
10810		 jalr  $25
10811		 sw    $23,0x4C($21)    	 # Delay slot
10812		 lw    $15,m68k_ICount
10813		 addiu $15,$15,-8
10814		 bgez  $15,3f
10815		 lhu   $24,0x00($23)    	 # Delay slot
10816		 j     MainExit
10817	3:
10818		 sll   $7,$24,2         	 # Delay slot
10819		 addu  $7,$7,$30
10820		 lw    $7,0x00($7)
10821		 jr    $7
10822		 nop                    	 # Delay slot
10823
10824OP0_3090:				#:
10825		 addiu $23,$23,2
10826
10827		 and   $8,$24,0x07
10828		 sll   $8,$8,2
10829		 addu  $8,$8,$21
10830		 lw    $14,0x20($8)
10831		 lw    $25,0x80($21)
10832		 sw    $15,m68k_ICount
10833		 sw    $24,0x44($29)
10834		 or    $4,$0,$14
10835		 jalr  $25
10836		 sw    $23,0x4C($21)    	 # Delay slot
10837		 lw    $24,0x44($29)
10838		 lw    $15,m68k_ICount
10839		 and   $16,$0,$0        	 # Clear Carry
10840		 and   $17,$0,$0        	 # Clear Overflow
10841		 srl   $19,$2,15         	 # Set Sign
10842		 sltiu $18,$2,1         	 # Set Zero
10843		 srl   $24,$24,7
10844		 andi  $24,$24,0x1C
10845		 addu  $24,$24,$21
10846		 lw    $14,0x20($24)
10847		 lw    $25,0x8C($21)
10848		 sw    $15,m68k_ICount
10849		 or    $5,$0,$2
10850		 or    $4,$0,$14
10851		 jalr  $25
10852		 sw    $23,0x4C($21)    	 # Delay slot
10853		 lw    $15,m68k_ICount
10854		 addiu $15,$15,-12
10855		 bgez  $15,3f
10856		 lhu   $24,0x00($23)    	 # Delay slot
10857		 j     MainExit
10858	3:
10859		 sll   $7,$24,2         	 # Delay slot
10860		 addu  $7,$7,$30
10861		 lw    $7,0x00($7)
10862		 jr    $7
10863		 nop                    	 # Delay slot
10864
10865OP0_3098:				#:
10866		 addiu $23,$23,2
10867
10868		 and   $8,$24,0x07
10869		 sll   $8,$8,2
10870		 addu  $8,$8,$21
10871		 lw    $14,0x20($8)
10872		 addiu $25,$14,2
10873		 sw    $25,0x20($8)
10874		 lw    $25,0x80($21)
10875		 sw    $15,m68k_ICount
10876		 sw    $24,0x44($29)
10877		 or    $4,$0,$14
10878		 jalr  $25
10879		 sw    $23,0x4C($21)    	 # Delay slot
10880		 lw    $24,0x44($29)
10881		 lw    $15,m68k_ICount
10882		 and   $16,$0,$0        	 # Clear Carry
10883		 and   $17,$0,$0        	 # Clear Overflow
10884		 srl   $19,$2,15         	 # Set Sign
10885		 sltiu $18,$2,1         	 # Set Zero
10886		 srl   $24,$24,7
10887		 andi  $24,$24,0x1C
10888		 addu  $24,$24,$21
10889		 lw    $14,0x20($24)
10890		 lw    $25,0x8C($21)
10891		 sw    $15,m68k_ICount
10892		 or    $5,$0,$2
10893		 or    $4,$0,$14
10894		 jalr  $25
10895		 sw    $23,0x4C($21)    	 # Delay slot
10896		 lw    $15,m68k_ICount
10897		 addiu $15,$15,-12
10898		 bgez  $15,3f
10899		 lhu   $24,0x00($23)    	 # Delay slot
10900		 j     MainExit
10901	3:
10902		 sll   $7,$24,2         	 # Delay slot
10903		 addu  $7,$7,$30
10904		 lw    $7,0x00($7)
10905		 jr    $7
10906		 nop                    	 # Delay slot
10907
10908OP0_30a0:				#:
10909		 addiu $23,$23,2
10910
10911		 and   $8,$24,0x07
10912		 sll   $8,$8,2
10913		 addu  $8,$8,$21
10914		 lw    $14,0x20($8)
10915		 addiu $14,$14,-2
10916		 sw    $14,0x20($8)
10917		 lw    $25,0x80($21)
10918		 sw    $15,m68k_ICount
10919		 sw    $24,0x44($29)
10920		 or    $4,$0,$14
10921		 jalr  $25
10922		 sw    $23,0x4C($21)    	 # Delay slot
10923		 lw    $24,0x44($29)
10924		 lw    $15,m68k_ICount
10925		 and   $16,$0,$0        	 # Clear Carry
10926		 and   $17,$0,$0        	 # Clear Overflow
10927		 srl   $19,$2,15         	 # Set Sign
10928		 sltiu $18,$2,1         	 # Set Zero
10929		 srl   $24,$24,7
10930		 andi  $24,$24,0x1C
10931		 addu  $24,$24,$21
10932		 lw    $14,0x20($24)
10933		 lw    $25,0x8C($21)
10934		 sw    $15,m68k_ICount
10935		 or    $5,$0,$2
10936		 or    $4,$0,$14
10937		 jalr  $25
10938		 sw    $23,0x4C($21)    	 # Delay slot
10939		 lw    $15,m68k_ICount
10940		 addiu $15,$15,-14
10941		 bgez  $15,3f
10942		 lhu   $24,0x00($23)    	 # Delay slot
10943		 j     MainExit
10944	3:
10945		 sll   $7,$24,2         	 # Delay slot
10946		 addu  $7,$7,$30
10947		 lw    $7,0x00($7)
10948		 jr    $7
10949		 nop                    	 # Delay slot
10950
10951OP0_30a8:				#:
10952		 addiu $23,$23,2
10953
10954		 and   $8,$24,0x07
10955		 lh    $7,0x00($23)
10956		 sll   $8,$8,2
10957		 addu  $8,$8,$21
10958		 lw    $14,0x20($8)
10959		 addiu $23,$23,2
10960		 addu  $14,$14,$7
10961		 lw    $25,0x80($21)
10962		 sw    $15,m68k_ICount
10963		 sw    $24,0x44($29)
10964		 or    $4,$0,$14
10965		 jalr  $25
10966		 sw    $23,0x4C($21)    	 # Delay slot
10967		 lw    $24,0x44($29)
10968		 lw    $15,m68k_ICount
10969		 and   $16,$0,$0        	 # Clear Carry
10970		 and   $17,$0,$0        	 # Clear Overflow
10971		 srl   $19,$2,15         	 # Set Sign
10972		 sltiu $18,$2,1         	 # Set Zero
10973		 srl   $24,$24,7
10974		 andi  $24,$24,0x1C
10975		 addu  $24,$24,$21
10976		 lw    $14,0x20($24)
10977		 lw    $25,0x8C($21)
10978		 sw    $15,m68k_ICount
10979		 or    $5,$0,$2
10980		 or    $4,$0,$14
10981		 jalr  $25
10982		 sw    $23,0x4C($21)    	 # Delay slot
10983		 lw    $15,m68k_ICount
10984		 addiu $15,$15,-16
10985		 bgez  $15,3f
10986		 lhu   $24,0x00($23)    	 # Delay slot
10987		 j     MainExit
10988	3:
10989		 sll   $7,$24,2         	 # Delay slot
10990		 addu  $7,$7,$30
10991		 lw    $7,0x00($7)
10992		 jr    $7
10993		 nop                    	 # Delay slot
10994
10995OP0_30b0:				#:
10996		 addiu $23,$23,2
10997
10998		 and   $8,$24,0x07
10999		 sll   $8,$8,2
11000		 addu  $8,$8,$21
11001		 lw    $14,0x20($8)
11002		 lhu   $7,0x00($23)
11003		 addiu $23,$23,2
11004		 seb   $6,$7
11005		 or    $25,$0,$7
11006		 srl   $7,$7,12
11007		 andi  $25,$25,0x0800
11008		 sll   $7,$7,2
11009		 addu  $7,$7,$21
11010		 bne   $25,$0,0f
11011		 lw    $25,0x00($7)      	 # Delay slot
11012		 seh   $25,$25
11013	0:
11014		 addu  $25,$14,$25
11015		 addu  $14,$25,$6
11016		 lw    $25,0x80($21)
11017		 sw    $15,m68k_ICount
11018		 sw    $24,0x44($29)
11019		 or    $4,$0,$14
11020		 jalr  $25
11021		 sw    $23,0x4C($21)    	 # Delay slot
11022		 lw    $24,0x44($29)
11023		 lw    $15,m68k_ICount
11024		 and   $16,$0,$0        	 # Clear Carry
11025		 and   $17,$0,$0        	 # Clear Overflow
11026		 srl   $19,$2,15         	 # Set Sign
11027		 sltiu $18,$2,1         	 # Set Zero
11028		 srl   $24,$24,7
11029		 andi  $24,$24,0x1C
11030		 addu  $24,$24,$21
11031		 lw    $14,0x20($24)
11032		 lw    $25,0x8C($21)
11033		 sw    $15,m68k_ICount
11034		 or    $5,$0,$2
11035		 or    $4,$0,$14
11036		 jalr  $25
11037		 sw    $23,0x4C($21)    	 # Delay slot
11038		 lw    $15,m68k_ICount
11039		 addiu $15,$15,-18
11040		 bgez  $15,3f
11041		 lhu   $24,0x00($23)    	 # Delay slot
11042		 j     MainExit
11043	3:
11044		 sll   $7,$24,2         	 # Delay slot
11045		 addu  $7,$7,$30
11046		 lw    $7,0x00($7)
11047		 jr    $7
11048		 nop                    	 # Delay slot
11049
11050OP0_30b8:				#:
11051		 addiu $23,$23,2
11052
11053		 lh    $14,0x00($23)
11054		 addiu $23,$23,2
11055		 lw    $25,0x80($21)
11056		 sw    $15,m68k_ICount
11057		 sw    $24,0x44($29)
11058		 or    $4,$0,$14
11059		 jalr  $25
11060		 sw    $23,0x4C($21)    	 # Delay slot
11061		 lw    $24,0x44($29)
11062		 lw    $15,m68k_ICount
11063		 and   $16,$0,$0        	 # Clear Carry
11064		 and   $17,$0,$0        	 # Clear Overflow
11065		 srl   $19,$2,15         	 # Set Sign
11066		 sltiu $18,$2,1         	 # Set Zero
11067		 srl   $24,$24,7
11068		 andi  $24,$24,0x1C
11069		 addu  $24,$24,$21
11070		 lw    $14,0x20($24)
11071		 lw    $25,0x8C($21)
11072		 sw    $15,m68k_ICount
11073		 or    $5,$0,$2
11074		 or    $4,$0,$14
11075		 jalr  $25
11076		 sw    $23,0x4C($21)    	 # Delay slot
11077		 lw    $15,m68k_ICount
11078		 addiu $15,$15,-16
11079		 bgez  $15,3f
11080		 lhu   $24,0x00($23)    	 # Delay slot
11081		 j     MainExit
11082	3:
11083		 sll   $7,$24,2         	 # Delay slot
11084		 addu  $7,$7,$30
11085		 lw    $7,0x00($7)
11086		 jr    $7
11087		 nop                    	 # Delay slot
11088
11089OP0_30b9:				#:
11090		 addiu $23,$23,2
11091
11092		 lhu   $14,0x00($23)
11093		 lhu   $25,0x02($23)
11094		 sll   $14,$14,16
11095		 or    $14,$14,$25
11096		 addiu $23,$23,4
11097		 lw    $25,0x80($21)
11098		 sw    $15,m68k_ICount
11099		 sw    $24,0x44($29)
11100		 or    $4,$0,$14
11101		 jalr  $25
11102		 sw    $23,0x4C($21)    	 # Delay slot
11103		 lw    $24,0x44($29)
11104		 lw    $15,m68k_ICount
11105		 and   $16,$0,$0        	 # Clear Carry
11106		 and   $17,$0,$0        	 # Clear Overflow
11107		 srl   $19,$2,15         	 # Set Sign
11108		 sltiu $18,$2,1         	 # Set Zero
11109		 srl   $24,$24,7
11110		 andi  $24,$24,0x1C
11111		 addu  $24,$24,$21
11112		 lw    $14,0x20($24)
11113		 lw    $25,0x8C($21)
11114		 sw    $15,m68k_ICount
11115		 or    $5,$0,$2
11116		 or    $4,$0,$14
11117		 jalr  $25
11118		 sw    $23,0x4C($21)    	 # Delay slot
11119		 lw    $15,m68k_ICount
11120		 addiu $15,$15,-20
11121		 bgez  $15,3f
11122		 lhu   $24,0x00($23)    	 # Delay slot
11123		 j     MainExit
11124	3:
11125		 sll   $7,$24,2         	 # Delay slot
11126		 addu  $7,$7,$30
11127		 lw    $7,0x00($7)
11128		 jr    $7
11129		 nop                    	 # Delay slot
11130
11131OP0_30ba:				#:
11132		 addiu $23,$23,2
11133
11134		 lh    $7,0x00($23)
11135		 subu  $25,$23,$22
11136		 addu  $14,$25,$7       	 # Add Offset to PC
11137		 addiu $23,$23,2
11138		 lw    $25,0x9C($21)
11139		 sw    $15,m68k_ICount
11140		 sw    $24,0x44($29)
11141		 or    $4,$0,$14
11142		 jalr  $25
11143		 sw    $23,0x4C($21)    	 # Delay slot
11144		 lw    $24,0x44($29)
11145		 lw    $15,m68k_ICount
11146		 and   $16,$0,$0        	 # Clear Carry
11147		 and   $17,$0,$0        	 # Clear Overflow
11148		 srl   $19,$2,15         	 # Set Sign
11149		 sltiu $18,$2,1         	 # Set Zero
11150		 srl   $24,$24,7
11151		 andi  $24,$24,0x1C
11152		 addu  $24,$24,$21
11153		 lw    $14,0x20($24)
11154		 lw    $25,0x8C($21)
11155		 sw    $15,m68k_ICount
11156		 or    $5,$0,$2
11157		 or    $4,$0,$14
11158		 jalr  $25
11159		 sw    $23,0x4C($21)    	 # Delay slot
11160		 lw    $15,m68k_ICount
11161		 addiu $15,$15,-16
11162		 bgez  $15,3f
11163		 lhu   $24,0x00($23)    	 # Delay slot
11164		 j     MainExit
11165	3:
11166		 sll   $7,$24,2         	 # Delay slot
11167		 addu  $7,$7,$30
11168		 lw    $7,0x00($7)
11169		 jr    $7
11170		 nop                    	 # Delay slot
11171
11172OP0_30bb:				#:
11173		 addiu $23,$23,2
11174
11175		 subu  $14,$23,$22       	 # Get PC
11176		 lhu   $7,0x00($23)
11177		 addiu $23,$23,2
11178		 seb   $6,$7
11179		 or    $25,$0,$7
11180		 srl   $7,$7,12
11181		 andi  $25,$25,0x0800
11182		 sll   $7,$7,2
11183		 addu  $7,$7,$21
11184		 bne   $25,$0,0f
11185		 lw    $25,0x00($7)      	 # Delay slot
11186		 seh   $25,$25
11187	0:
11188		 addu  $25,$14,$25
11189		 addu  $14,$25,$6
11190		 lw    $25,0x9C($21)
11191		 sw    $15,m68k_ICount
11192		 sw    $24,0x44($29)
11193		 or    $4,$0,$14
11194		 jalr  $25
11195		 sw    $23,0x4C($21)    	 # Delay slot
11196		 lw    $24,0x44($29)
11197		 lw    $15,m68k_ICount
11198		 and   $16,$0,$0        	 # Clear Carry
11199		 and   $17,$0,$0        	 # Clear Overflow
11200		 srl   $19,$2,15         	 # Set Sign
11201		 sltiu $18,$2,1         	 # Set Zero
11202		 srl   $24,$24,7
11203		 andi  $24,$24,0x1C
11204		 addu  $24,$24,$21
11205		 lw    $14,0x20($24)
11206		 lw    $25,0x8C($21)
11207		 sw    $15,m68k_ICount
11208		 or    $5,$0,$2
11209		 or    $4,$0,$14
11210		 jalr  $25
11211		 sw    $23,0x4C($21)    	 # Delay slot
11212		 lw    $15,m68k_ICount
11213		 addiu $15,$15,-18
11214		 bgez  $15,3f
11215		 lhu   $24,0x00($23)    	 # Delay slot
11216		 j     MainExit
11217	3:
11218		 sll   $7,$24,2         	 # Delay slot
11219		 addu  $7,$7,$30
11220		 lw    $7,0x00($7)
11221		 jr    $7
11222		 nop                    	 # Delay slot
11223
11224OP0_30bc:				#:
11225		 addiu $23,$23,2
11226
11227		 lhu   $2,0x00($23)
11228		 addiu $23,$23,2
11229		 and   $16,$0,$0        	 # Clear Carry
11230		 and   $17,$0,$0        	 # Clear Overflow
11231		 srl   $19,$2,15         	 # Set Sign
11232		 sltiu $18,$2,1         	 # Set Zero
11233		 srl   $24,$24,7
11234		 andi  $24,$24,0x1C
11235		 addu  $24,$24,$21
11236		 lw    $14,0x20($24)
11237		 lw    $25,0x8C($21)
11238		 sw    $15,m68k_ICount
11239		 or    $5,$0,$2
11240		 or    $4,$0,$14
11241		 jalr  $25
11242		 sw    $23,0x4C($21)    	 # Delay slot
11243		 lw    $15,m68k_ICount
11244		 addiu $15,$15,-8
11245		 bgez  $15,3f
11246		 lhu   $24,0x00($23)    	 # Delay slot
11247		 j     MainExit
11248	3:
11249		 sll   $7,$24,2         	 # Delay slot
11250		 addu  $7,$7,$30
11251		 lw    $7,0x00($7)
11252		 jr    $7
11253		 nop                    	 # Delay slot
11254
11255OP0_30c0:				#:
11256		 addiu $23,$23,2
11257
11258		 and   $8,$24,0x0f
11259		 sll   $8,$8,2
11260		 addu  $8,$8,$21
11261		 lhu   $2,0x00($8)
11262		 and   $16,$0,$0        	 # Clear Carry
11263		 and   $17,$0,$0        	 # Clear Overflow
11264		 srl   $19,$2,15         	 # Set Sign
11265		 sltiu $18,$2,1         	 # Set Zero
11266		 srl   $24,$24,7
11267		 andi  $24,$24,0x1C
11268		 addu  $24,$24,$21
11269		 lw    $14,0x20($24)
11270		 addiu $25,$14,2
11271		 sw    $25,0x20($24)
11272		 lw    $25,0x8C($21)
11273		 sw    $15,m68k_ICount
11274		 or    $5,$0,$2
11275		 or    $4,$0,$14
11276		 jalr  $25
11277		 sw    $23,0x4C($21)    	 # Delay slot
11278		 lw    $15,m68k_ICount
11279		 addiu $15,$15,-8
11280		 bgez  $15,3f
11281		 lhu   $24,0x00($23)    	 # Delay slot
11282		 j     MainExit
11283	3:
11284		 sll   $7,$24,2         	 # Delay slot
11285		 addu  $7,$7,$30
11286		 lw    $7,0x00($7)
11287		 jr    $7
11288		 nop                    	 # Delay slot
11289
11290OP0_30d0:				#:
11291		 addiu $23,$23,2
11292
11293		 and   $8,$24,0x07
11294		 sll   $8,$8,2
11295		 addu  $8,$8,$21
11296		 lw    $14,0x20($8)
11297		 lw    $25,0x80($21)
11298		 sw    $15,m68k_ICount
11299		 sw    $24,0x44($29)
11300		 or    $4,$0,$14
11301		 jalr  $25
11302		 sw    $23,0x4C($21)    	 # Delay slot
11303		 lw    $24,0x44($29)
11304		 lw    $15,m68k_ICount
11305		 and   $16,$0,$0        	 # Clear Carry
11306		 and   $17,$0,$0        	 # Clear Overflow
11307		 srl   $19,$2,15         	 # Set Sign
11308		 sltiu $18,$2,1         	 # Set Zero
11309		 srl   $24,$24,7
11310		 andi  $24,$24,0x1C
11311		 addu  $24,$24,$21
11312		 lw    $14,0x20($24)
11313		 addiu $25,$14,2
11314		 sw    $25,0x20($24)
11315		 lw    $25,0x8C($21)
11316		 sw    $15,m68k_ICount
11317		 or    $5,$0,$2
11318		 or    $4,$0,$14
11319		 jalr  $25
11320		 sw    $23,0x4C($21)    	 # Delay slot
11321		 lw    $15,m68k_ICount
11322		 addiu $15,$15,-12
11323		 bgez  $15,3f
11324		 lhu   $24,0x00($23)    	 # Delay slot
11325		 j     MainExit
11326	3:
11327		 sll   $7,$24,2         	 # Delay slot
11328		 addu  $7,$7,$30
11329		 lw    $7,0x00($7)
11330		 jr    $7
11331		 nop                    	 # Delay slot
11332
11333OP0_30d8:				#:
11334		 addiu $23,$23,2
11335
11336		 and   $8,$24,0x07
11337		 sll   $8,$8,2
11338		 addu  $8,$8,$21
11339		 lw    $14,0x20($8)
11340		 addiu $25,$14,2
11341		 sw    $25,0x20($8)
11342		 lw    $25,0x80($21)
11343		 sw    $15,m68k_ICount
11344		 sw    $24,0x44($29)
11345		 or    $4,$0,$14
11346		 jalr  $25
11347		 sw    $23,0x4C($21)    	 # Delay slot
11348		 lw    $24,0x44($29)
11349		 lw    $15,m68k_ICount
11350		 and   $16,$0,$0        	 # Clear Carry
11351		 and   $17,$0,$0        	 # Clear Overflow
11352		 srl   $19,$2,15         	 # Set Sign
11353		 sltiu $18,$2,1         	 # Set Zero
11354		 srl   $24,$24,7
11355		 andi  $24,$24,0x1C
11356		 addu  $24,$24,$21
11357		 lw    $14,0x20($24)
11358		 addiu $25,$14,2
11359		 sw    $25,0x20($24)
11360		 lw    $25,0x8C($21)
11361		 sw    $15,m68k_ICount
11362		 or    $5,$0,$2
11363		 or    $4,$0,$14
11364		 jalr  $25
11365		 sw    $23,0x4C($21)    	 # Delay slot
11366		 lw    $15,m68k_ICount
11367		 addiu $15,$15,-12
11368		 bgez  $15,3f
11369		 lhu   $24,0x00($23)    	 # Delay slot
11370		 j     MainExit
11371	3:
11372		 sll   $7,$24,2         	 # Delay slot
11373		 addu  $7,$7,$30
11374		 lw    $7,0x00($7)
11375		 jr    $7
11376		 nop                    	 # Delay slot
11377
11378OP0_30e0:				#:
11379		 addiu $23,$23,2
11380
11381		 and   $8,$24,0x07
11382		 sll   $8,$8,2
11383		 addu  $8,$8,$21
11384		 lw    $14,0x20($8)
11385		 addiu $14,$14,-2
11386		 sw    $14,0x20($8)
11387		 lw    $25,0x80($21)
11388		 sw    $15,m68k_ICount
11389		 sw    $24,0x44($29)
11390		 or    $4,$0,$14
11391		 jalr  $25
11392		 sw    $23,0x4C($21)    	 # Delay slot
11393		 lw    $24,0x44($29)
11394		 lw    $15,m68k_ICount
11395		 and   $16,$0,$0        	 # Clear Carry
11396		 and   $17,$0,$0        	 # Clear Overflow
11397		 srl   $19,$2,15         	 # Set Sign
11398		 sltiu $18,$2,1         	 # Set Zero
11399		 srl   $24,$24,7
11400		 andi  $24,$24,0x1C
11401		 addu  $24,$24,$21
11402		 lw    $14,0x20($24)
11403		 addiu $25,$14,2
11404		 sw    $25,0x20($24)
11405		 lw    $25,0x8C($21)
11406		 sw    $15,m68k_ICount
11407		 or    $5,$0,$2
11408		 or    $4,$0,$14
11409		 jalr  $25
11410		 sw    $23,0x4C($21)    	 # Delay slot
11411		 lw    $15,m68k_ICount
11412		 addiu $15,$15,-14
11413		 bgez  $15,3f
11414		 lhu   $24,0x00($23)    	 # Delay slot
11415		 j     MainExit
11416	3:
11417		 sll   $7,$24,2         	 # Delay slot
11418		 addu  $7,$7,$30
11419		 lw    $7,0x00($7)
11420		 jr    $7
11421		 nop                    	 # Delay slot
11422
11423OP0_30e8:				#:
11424		 addiu $23,$23,2
11425
11426		 and   $8,$24,0x07
11427		 lh    $7,0x00($23)
11428		 sll   $8,$8,2
11429		 addu  $8,$8,$21
11430		 lw    $14,0x20($8)
11431		 addiu $23,$23,2
11432		 addu  $14,$14,$7
11433		 lw    $25,0x80($21)
11434		 sw    $15,m68k_ICount
11435		 sw    $24,0x44($29)
11436		 or    $4,$0,$14
11437		 jalr  $25
11438		 sw    $23,0x4C($21)    	 # Delay slot
11439		 lw    $24,0x44($29)
11440		 lw    $15,m68k_ICount
11441		 and   $16,$0,$0        	 # Clear Carry
11442		 and   $17,$0,$0        	 # Clear Overflow
11443		 srl   $19,$2,15         	 # Set Sign
11444		 sltiu $18,$2,1         	 # Set Zero
11445		 srl   $24,$24,7
11446		 andi  $24,$24,0x1C
11447		 addu  $24,$24,$21
11448		 lw    $14,0x20($24)
11449		 addiu $25,$14,2
11450		 sw    $25,0x20($24)
11451		 lw    $25,0x8C($21)
11452		 sw    $15,m68k_ICount
11453		 or    $5,$0,$2
11454		 or    $4,$0,$14
11455		 jalr  $25
11456		 sw    $23,0x4C($21)    	 # Delay slot
11457		 lw    $15,m68k_ICount
11458		 addiu $15,$15,-16
11459		 bgez  $15,3f
11460		 lhu   $24,0x00($23)    	 # Delay slot
11461		 j     MainExit
11462	3:
11463		 sll   $7,$24,2         	 # Delay slot
11464		 addu  $7,$7,$30
11465		 lw    $7,0x00($7)
11466		 jr    $7
11467		 nop                    	 # Delay slot
11468
11469OP0_30f0:				#:
11470		 addiu $23,$23,2
11471
11472		 and   $8,$24,0x07
11473		 sll   $8,$8,2
11474		 addu  $8,$8,$21
11475		 lw    $14,0x20($8)
11476		 lhu   $7,0x00($23)
11477		 addiu $23,$23,2
11478		 seb   $6,$7
11479		 or    $25,$0,$7
11480		 srl   $7,$7,12
11481		 andi  $25,$25,0x0800
11482		 sll   $7,$7,2
11483		 addu  $7,$7,$21
11484		 bne   $25,$0,0f
11485		 lw    $25,0x00($7)      	 # Delay slot
11486		 seh   $25,$25
11487	0:
11488		 addu  $25,$14,$25
11489		 addu  $14,$25,$6
11490		 lw    $25,0x80($21)
11491		 sw    $15,m68k_ICount
11492		 sw    $24,0x44($29)
11493		 or    $4,$0,$14
11494		 jalr  $25
11495		 sw    $23,0x4C($21)    	 # Delay slot
11496		 lw    $24,0x44($29)
11497		 lw    $15,m68k_ICount
11498		 and   $16,$0,$0        	 # Clear Carry
11499		 and   $17,$0,$0        	 # Clear Overflow
11500		 srl   $19,$2,15         	 # Set Sign
11501		 sltiu $18,$2,1         	 # Set Zero
11502		 srl   $24,$24,7
11503		 andi  $24,$24,0x1C
11504		 addu  $24,$24,$21
11505		 lw    $14,0x20($24)
11506		 addiu $25,$14,2
11507		 sw    $25,0x20($24)
11508		 lw    $25,0x8C($21)
11509		 sw    $15,m68k_ICount
11510		 or    $5,$0,$2
11511		 or    $4,$0,$14
11512		 jalr  $25
11513		 sw    $23,0x4C($21)    	 # Delay slot
11514		 lw    $15,m68k_ICount
11515		 addiu $15,$15,-18
11516		 bgez  $15,3f
11517		 lhu   $24,0x00($23)    	 # Delay slot
11518		 j     MainExit
11519	3:
11520		 sll   $7,$24,2         	 # Delay slot
11521		 addu  $7,$7,$30
11522		 lw    $7,0x00($7)
11523		 jr    $7
11524		 nop                    	 # Delay slot
11525
11526OP0_30f8:				#:
11527		 addiu $23,$23,2
11528
11529		 lh    $14,0x00($23)
11530		 addiu $23,$23,2
11531		 lw    $25,0x80($21)
11532		 sw    $15,m68k_ICount
11533		 sw    $24,0x44($29)
11534		 or    $4,$0,$14
11535		 jalr  $25
11536		 sw    $23,0x4C($21)    	 # Delay slot
11537		 lw    $24,0x44($29)
11538		 lw    $15,m68k_ICount
11539		 and   $16,$0,$0        	 # Clear Carry
11540		 and   $17,$0,$0        	 # Clear Overflow
11541		 srl   $19,$2,15         	 # Set Sign
11542		 sltiu $18,$2,1         	 # Set Zero
11543		 srl   $24,$24,7
11544		 andi  $24,$24,0x1C
11545		 addu  $24,$24,$21
11546		 lw    $14,0x20($24)
11547		 addiu $25,$14,2
11548		 sw    $25,0x20($24)
11549		 lw    $25,0x8C($21)
11550		 sw    $15,m68k_ICount
11551		 or    $5,$0,$2
11552		 or    $4,$0,$14
11553		 jalr  $25
11554		 sw    $23,0x4C($21)    	 # Delay slot
11555		 lw    $15,m68k_ICount
11556		 addiu $15,$15,-16
11557		 bgez  $15,3f
11558		 lhu   $24,0x00($23)    	 # Delay slot
11559		 j     MainExit
11560	3:
11561		 sll   $7,$24,2         	 # Delay slot
11562		 addu  $7,$7,$30
11563		 lw    $7,0x00($7)
11564		 jr    $7
11565		 nop                    	 # Delay slot
11566
11567OP0_30f9:				#:
11568		 addiu $23,$23,2
11569
11570		 lhu   $14,0x00($23)
11571		 lhu   $25,0x02($23)
11572		 sll   $14,$14,16
11573		 or    $14,$14,$25
11574		 addiu $23,$23,4
11575		 lw    $25,0x80($21)
11576		 sw    $15,m68k_ICount
11577		 sw    $24,0x44($29)
11578		 or    $4,$0,$14
11579		 jalr  $25
11580		 sw    $23,0x4C($21)    	 # Delay slot
11581		 lw    $24,0x44($29)
11582		 lw    $15,m68k_ICount
11583		 and   $16,$0,$0        	 # Clear Carry
11584		 and   $17,$0,$0        	 # Clear Overflow
11585		 srl   $19,$2,15         	 # Set Sign
11586		 sltiu $18,$2,1         	 # Set Zero
11587		 srl   $24,$24,7
11588		 andi  $24,$24,0x1C
11589		 addu  $24,$24,$21
11590		 lw    $14,0x20($24)
11591		 addiu $25,$14,2
11592		 sw    $25,0x20($24)
11593		 lw    $25,0x8C($21)
11594		 sw    $15,m68k_ICount
11595		 or    $5,$0,$2
11596		 or    $4,$0,$14
11597		 jalr  $25
11598		 sw    $23,0x4C($21)    	 # Delay slot
11599		 lw    $15,m68k_ICount
11600		 addiu $15,$15,-20
11601		 bgez  $15,3f
11602		 lhu   $24,0x00($23)    	 # Delay slot
11603		 j     MainExit
11604	3:
11605		 sll   $7,$24,2         	 # Delay slot
11606		 addu  $7,$7,$30
11607		 lw    $7,0x00($7)
11608		 jr    $7
11609		 nop                    	 # Delay slot
11610
11611OP0_30fa:				#:
11612		 addiu $23,$23,2
11613
11614		 lh    $7,0x00($23)
11615		 subu  $25,$23,$22
11616		 addu  $14,$25,$7       	 # Add Offset to PC
11617		 addiu $23,$23,2
11618		 lw    $25,0x9C($21)
11619		 sw    $15,m68k_ICount
11620		 sw    $24,0x44($29)
11621		 or    $4,$0,$14
11622		 jalr  $25
11623		 sw    $23,0x4C($21)    	 # Delay slot
11624		 lw    $24,0x44($29)
11625		 lw    $15,m68k_ICount
11626		 and   $16,$0,$0        	 # Clear Carry
11627		 and   $17,$0,$0        	 # Clear Overflow
11628		 srl   $19,$2,15         	 # Set Sign
11629		 sltiu $18,$2,1         	 # Set Zero
11630		 srl   $24,$24,7
11631		 andi  $24,$24,0x1C
11632		 addu  $24,$24,$21
11633		 lw    $14,0x20($24)
11634		 addiu $25,$14,2
11635		 sw    $25,0x20($24)
11636		 lw    $25,0x8C($21)
11637		 sw    $15,m68k_ICount
11638		 or    $5,$0,$2
11639		 or    $4,$0,$14
11640		 jalr  $25
11641		 sw    $23,0x4C($21)    	 # Delay slot
11642		 lw    $15,m68k_ICount
11643		 addiu $15,$15,-16
11644		 bgez  $15,3f
11645		 lhu   $24,0x00($23)    	 # Delay slot
11646		 j     MainExit
11647	3:
11648		 sll   $7,$24,2         	 # Delay slot
11649		 addu  $7,$7,$30
11650		 lw    $7,0x00($7)
11651		 jr    $7
11652		 nop                    	 # Delay slot
11653
11654OP0_30fb:				#:
11655		 addiu $23,$23,2
11656
11657		 subu  $14,$23,$22       	 # Get PC
11658		 lhu   $7,0x00($23)
11659		 addiu $23,$23,2
11660		 seb   $6,$7
11661		 or    $25,$0,$7
11662		 srl   $7,$7,12
11663		 andi  $25,$25,0x0800
11664		 sll   $7,$7,2
11665		 addu  $7,$7,$21
11666		 bne   $25,$0,0f
11667		 lw    $25,0x00($7)      	 # Delay slot
11668		 seh   $25,$25
11669	0:
11670		 addu  $25,$14,$25
11671		 addu  $14,$25,$6
11672		 lw    $25,0x9C($21)
11673		 sw    $15,m68k_ICount
11674		 sw    $24,0x44($29)
11675		 or    $4,$0,$14
11676		 jalr  $25
11677		 sw    $23,0x4C($21)    	 # Delay slot
11678		 lw    $24,0x44($29)
11679		 lw    $15,m68k_ICount
11680		 and   $16,$0,$0        	 # Clear Carry
11681		 and   $17,$0,$0        	 # Clear Overflow
11682		 srl   $19,$2,15         	 # Set Sign
11683		 sltiu $18,$2,1         	 # Set Zero
11684		 srl   $24,$24,7
11685		 andi  $24,$24,0x1C
11686		 addu  $24,$24,$21
11687		 lw    $14,0x20($24)
11688		 addiu $25,$14,2
11689		 sw    $25,0x20($24)
11690		 lw    $25,0x8C($21)
11691		 sw    $15,m68k_ICount
11692		 or    $5,$0,$2
11693		 or    $4,$0,$14
11694		 jalr  $25
11695		 sw    $23,0x4C($21)    	 # Delay slot
11696		 lw    $15,m68k_ICount
11697		 addiu $15,$15,-18
11698		 bgez  $15,3f
11699		 lhu   $24,0x00($23)    	 # Delay slot
11700		 j     MainExit
11701	3:
11702		 sll   $7,$24,2         	 # Delay slot
11703		 addu  $7,$7,$30
11704		 lw    $7,0x00($7)
11705		 jr    $7
11706		 nop                    	 # Delay slot
11707
11708OP0_30fc:				#:
11709		 addiu $23,$23,2
11710
11711		 lhu   $2,0x00($23)
11712		 addiu $23,$23,2
11713		 and   $16,$0,$0        	 # Clear Carry
11714		 and   $17,$0,$0        	 # Clear Overflow
11715		 srl   $19,$2,15         	 # Set Sign
11716		 sltiu $18,$2,1         	 # Set Zero
11717		 srl   $24,$24,7
11718		 andi  $24,$24,0x1C
11719		 addu  $24,$24,$21
11720		 lw    $14,0x20($24)
11721		 addiu $25,$14,2
11722		 sw    $25,0x20($24)
11723		 lw    $25,0x8C($21)
11724		 sw    $15,m68k_ICount
11725		 or    $5,$0,$2
11726		 or    $4,$0,$14
11727		 jalr  $25
11728		 sw    $23,0x4C($21)    	 # Delay slot
11729		 lw    $15,m68k_ICount
11730		 addiu $15,$15,-8
11731		 bgez  $15,3f
11732		 lhu   $24,0x00($23)    	 # Delay slot
11733		 j     MainExit
11734	3:
11735		 sll   $7,$24,2         	 # Delay slot
11736		 addu  $7,$7,$30
11737		 lw    $7,0x00($7)
11738		 jr    $7
11739		 nop                    	 # Delay slot
11740
11741OP0_3100:				#:
11742		 addiu $23,$23,2
11743
11744		 and   $8,$24,0x0f
11745		 sll   $8,$8,2
11746		 addu  $8,$8,$21
11747		 lhu   $2,0x00($8)
11748		 and   $16,$0,$0        	 # Clear Carry
11749		 and   $17,$0,$0        	 # Clear Overflow
11750		 srl   $19,$2,15         	 # Set Sign
11751		 sltiu $18,$2,1         	 # Set Zero
11752		 srl   $24,$24,7
11753		 andi  $24,$24,0x1C
11754		 addu  $24,$24,$21
11755		 lw    $14,0x20($24)
11756		 addiu $14,$14,-2
11757		 sw    $14,0x20($24)
11758		 lw    $25,0x8C($21)
11759		 sw    $15,m68k_ICount
11760		 or    $5,$0,$2
11761		 or    $4,$0,$14
11762		 jalr  $25
11763		 sw    $23,0x4C($21)    	 # Delay slot
11764		 lw    $15,m68k_ICount
11765		 addiu $15,$15,-10
11766		 bgez  $15,3f
11767		 lhu   $24,0x00($23)    	 # Delay slot
11768		 j     MainExit
11769	3:
11770		 sll   $7,$24,2         	 # Delay slot
11771		 addu  $7,$7,$30
11772		 lw    $7,0x00($7)
11773		 jr    $7
11774		 nop                    	 # Delay slot
11775
11776OP0_3110:				#:
11777		 addiu $23,$23,2
11778
11779		 and   $8,$24,0x07
11780		 sll   $8,$8,2
11781		 addu  $8,$8,$21
11782		 lw    $14,0x20($8)
11783		 lw    $25,0x80($21)
11784		 sw    $15,m68k_ICount
11785		 sw    $24,0x44($29)
11786		 or    $4,$0,$14
11787		 jalr  $25
11788		 sw    $23,0x4C($21)    	 # Delay slot
11789		 lw    $24,0x44($29)
11790		 lw    $15,m68k_ICount
11791		 and   $16,$0,$0        	 # Clear Carry
11792		 and   $17,$0,$0        	 # Clear Overflow
11793		 srl   $19,$2,15         	 # Set Sign
11794		 sltiu $18,$2,1         	 # Set Zero
11795		 srl   $24,$24,7
11796		 andi  $24,$24,0x1C
11797		 addu  $24,$24,$21
11798		 lw    $14,0x20($24)
11799		 addiu $14,$14,-2
11800		 sw    $14,0x20($24)
11801		 lw    $25,0x8C($21)
11802		 sw    $15,m68k_ICount
11803		 or    $5,$0,$2
11804		 or    $4,$0,$14
11805		 jalr  $25
11806		 sw    $23,0x4C($21)    	 # Delay slot
11807		 lw    $15,m68k_ICount
11808		 addiu $15,$15,-14
11809		 bgez  $15,3f
11810		 lhu   $24,0x00($23)    	 # Delay slot
11811		 j     MainExit
11812	3:
11813		 sll   $7,$24,2         	 # Delay slot
11814		 addu  $7,$7,$30
11815		 lw    $7,0x00($7)
11816		 jr    $7
11817		 nop                    	 # Delay slot
11818
11819OP0_3118:				#:
11820		 addiu $23,$23,2
11821
11822		 and   $8,$24,0x07
11823		 sll   $8,$8,2
11824		 addu  $8,$8,$21
11825		 lw    $14,0x20($8)
11826		 addiu $25,$14,2
11827		 sw    $25,0x20($8)
11828		 lw    $25,0x80($21)
11829		 sw    $15,m68k_ICount
11830		 sw    $24,0x44($29)
11831		 or    $4,$0,$14
11832		 jalr  $25
11833		 sw    $23,0x4C($21)    	 # Delay slot
11834		 lw    $24,0x44($29)
11835		 lw    $15,m68k_ICount
11836		 and   $16,$0,$0        	 # Clear Carry
11837		 and   $17,$0,$0        	 # Clear Overflow
11838		 srl   $19,$2,15         	 # Set Sign
11839		 sltiu $18,$2,1         	 # Set Zero
11840		 srl   $24,$24,7
11841		 andi  $24,$24,0x1C
11842		 addu  $24,$24,$21
11843		 lw    $14,0x20($24)
11844		 addiu $14,$14,-2
11845		 sw    $14,0x20($24)
11846		 lw    $25,0x8C($21)
11847		 sw    $15,m68k_ICount
11848		 or    $5,$0,$2
11849		 or    $4,$0,$14
11850		 jalr  $25
11851		 sw    $23,0x4C($21)    	 # Delay slot
11852		 lw    $15,m68k_ICount
11853		 addiu $15,$15,-14
11854		 bgez  $15,3f
11855		 lhu   $24,0x00($23)    	 # Delay slot
11856		 j     MainExit
11857	3:
11858		 sll   $7,$24,2         	 # Delay slot
11859		 addu  $7,$7,$30
11860		 lw    $7,0x00($7)
11861		 jr    $7
11862		 nop                    	 # Delay slot
11863
11864OP0_3120:				#:
11865		 addiu $23,$23,2
11866
11867		 and   $8,$24,0x07
11868		 sll   $8,$8,2
11869		 addu  $8,$8,$21
11870		 lw    $14,0x20($8)
11871		 addiu $14,$14,-2
11872		 sw    $14,0x20($8)
11873		 lw    $25,0x80($21)
11874		 sw    $15,m68k_ICount
11875		 sw    $24,0x44($29)
11876		 or    $4,$0,$14
11877		 jalr  $25
11878		 sw    $23,0x4C($21)    	 # Delay slot
11879		 lw    $24,0x44($29)
11880		 lw    $15,m68k_ICount
11881		 and   $16,$0,$0        	 # Clear Carry
11882		 and   $17,$0,$0        	 # Clear Overflow
11883		 srl   $19,$2,15         	 # Set Sign
11884		 sltiu $18,$2,1         	 # Set Zero
11885		 srl   $24,$24,7
11886		 andi  $24,$24,0x1C
11887		 addu  $24,$24,$21
11888		 lw    $14,0x20($24)
11889		 addiu $14,$14,-2
11890		 sw    $14,0x20($24)
11891		 lw    $25,0x8C($21)
11892		 sw    $15,m68k_ICount
11893		 or    $5,$0,$2
11894		 or    $4,$0,$14
11895		 jalr  $25
11896		 sw    $23,0x4C($21)    	 # Delay slot
11897		 lw    $15,m68k_ICount
11898		 addiu $15,$15,-16
11899		 bgez  $15,3f
11900		 lhu   $24,0x00($23)    	 # Delay slot
11901		 j     MainExit
11902	3:
11903		 sll   $7,$24,2         	 # Delay slot
11904		 addu  $7,$7,$30
11905		 lw    $7,0x00($7)
11906		 jr    $7
11907		 nop                    	 # Delay slot
11908
11909OP0_3128:				#:
11910		 addiu $23,$23,2
11911
11912		 and   $8,$24,0x07
11913		 lh    $7,0x00($23)
11914		 sll   $8,$8,2
11915		 addu  $8,$8,$21
11916		 lw    $14,0x20($8)
11917		 addiu $23,$23,2
11918		 addu  $14,$14,$7
11919		 lw    $25,0x80($21)
11920		 sw    $15,m68k_ICount
11921		 sw    $24,0x44($29)
11922		 or    $4,$0,$14
11923		 jalr  $25
11924		 sw    $23,0x4C($21)    	 # Delay slot
11925		 lw    $24,0x44($29)
11926		 lw    $15,m68k_ICount
11927		 and   $16,$0,$0        	 # Clear Carry
11928		 and   $17,$0,$0        	 # Clear Overflow
11929		 srl   $19,$2,15         	 # Set Sign
11930		 sltiu $18,$2,1         	 # Set Zero
11931		 srl   $24,$24,7
11932		 andi  $24,$24,0x1C
11933		 addu  $24,$24,$21
11934		 lw    $14,0x20($24)
11935		 addiu $14,$14,-2
11936		 sw    $14,0x20($24)
11937		 lw    $25,0x8C($21)
11938		 sw    $15,m68k_ICount
11939		 or    $5,$0,$2
11940		 or    $4,$0,$14
11941		 jalr  $25
11942		 sw    $23,0x4C($21)    	 # Delay slot
11943		 lw    $15,m68k_ICount
11944		 addiu $15,$15,-18
11945		 bgez  $15,3f
11946		 lhu   $24,0x00($23)    	 # Delay slot
11947		 j     MainExit
11948	3:
11949		 sll   $7,$24,2         	 # Delay slot
11950		 addu  $7,$7,$30
11951		 lw    $7,0x00($7)
11952		 jr    $7
11953		 nop                    	 # Delay slot
11954
11955OP0_3130:				#:
11956		 addiu $23,$23,2
11957
11958		 and   $8,$24,0x07
11959		 sll   $8,$8,2
11960		 addu  $8,$8,$21
11961		 lw    $14,0x20($8)
11962		 lhu   $7,0x00($23)
11963		 addiu $23,$23,2
11964		 seb   $6,$7
11965		 or    $25,$0,$7
11966		 srl   $7,$7,12
11967		 andi  $25,$25,0x0800
11968		 sll   $7,$7,2
11969		 addu  $7,$7,$21
11970		 bne   $25,$0,0f
11971		 lw    $25,0x00($7)      	 # Delay slot
11972		 seh   $25,$25
11973	0:
11974		 addu  $25,$14,$25
11975		 addu  $14,$25,$6
11976		 lw    $25,0x80($21)
11977		 sw    $15,m68k_ICount
11978		 sw    $24,0x44($29)
11979		 or    $4,$0,$14
11980		 jalr  $25
11981		 sw    $23,0x4C($21)    	 # Delay slot
11982		 lw    $24,0x44($29)
11983		 lw    $15,m68k_ICount
11984		 and   $16,$0,$0        	 # Clear Carry
11985		 and   $17,$0,$0        	 # Clear Overflow
11986		 srl   $19,$2,15         	 # Set Sign
11987		 sltiu $18,$2,1         	 # Set Zero
11988		 srl   $24,$24,7
11989		 andi  $24,$24,0x1C
11990		 addu  $24,$24,$21
11991		 lw    $14,0x20($24)
11992		 addiu $14,$14,-2
11993		 sw    $14,0x20($24)
11994		 lw    $25,0x8C($21)
11995		 sw    $15,m68k_ICount
11996		 or    $5,$0,$2
11997		 or    $4,$0,$14
11998		 jalr  $25
11999		 sw    $23,0x4C($21)    	 # Delay slot
12000		 lw    $15,m68k_ICount
12001		 addiu $15,$15,-20
12002		 bgez  $15,3f
12003		 lhu   $24,0x00($23)    	 # Delay slot
12004		 j     MainExit
12005	3:
12006		 sll   $7,$24,2         	 # Delay slot
12007		 addu  $7,$7,$30
12008		 lw    $7,0x00($7)
12009		 jr    $7
12010		 nop                    	 # Delay slot
12011
12012OP0_3138:				#:
12013		 addiu $23,$23,2
12014
12015		 lh    $14,0x00($23)
12016		 addiu $23,$23,2
12017		 lw    $25,0x80($21)
12018		 sw    $15,m68k_ICount
12019		 sw    $24,0x44($29)
12020		 or    $4,$0,$14
12021		 jalr  $25
12022		 sw    $23,0x4C($21)    	 # Delay slot
12023		 lw    $24,0x44($29)
12024		 lw    $15,m68k_ICount
12025		 and   $16,$0,$0        	 # Clear Carry
12026		 and   $17,$0,$0        	 # Clear Overflow
12027		 srl   $19,$2,15         	 # Set Sign
12028		 sltiu $18,$2,1         	 # Set Zero
12029		 srl   $24,$24,7
12030		 andi  $24,$24,0x1C
12031		 addu  $24,$24,$21
12032		 lw    $14,0x20($24)
12033		 addiu $14,$14,-2
12034		 sw    $14,0x20($24)
12035		 lw    $25,0x8C($21)
12036		 sw    $15,m68k_ICount
12037		 or    $5,$0,$2
12038		 or    $4,$0,$14
12039		 jalr  $25
12040		 sw    $23,0x4C($21)    	 # Delay slot
12041		 lw    $15,m68k_ICount
12042		 addiu $15,$15,-18
12043		 bgez  $15,3f
12044		 lhu   $24,0x00($23)    	 # Delay slot
12045		 j     MainExit
12046	3:
12047		 sll   $7,$24,2         	 # Delay slot
12048		 addu  $7,$7,$30
12049		 lw    $7,0x00($7)
12050		 jr    $7
12051		 nop                    	 # Delay slot
12052
12053OP0_3139:				#:
12054		 addiu $23,$23,2
12055
12056		 lhu   $14,0x00($23)
12057		 lhu   $25,0x02($23)
12058		 sll   $14,$14,16
12059		 or    $14,$14,$25
12060		 addiu $23,$23,4
12061		 lw    $25,0x80($21)
12062		 sw    $15,m68k_ICount
12063		 sw    $24,0x44($29)
12064		 or    $4,$0,$14
12065		 jalr  $25
12066		 sw    $23,0x4C($21)    	 # Delay slot
12067		 lw    $24,0x44($29)
12068		 lw    $15,m68k_ICount
12069		 and   $16,$0,$0        	 # Clear Carry
12070		 and   $17,$0,$0        	 # Clear Overflow
12071		 srl   $19,$2,15         	 # Set Sign
12072		 sltiu $18,$2,1         	 # Set Zero
12073		 srl   $24,$24,7
12074		 andi  $24,$24,0x1C
12075		 addu  $24,$24,$21
12076		 lw    $14,0x20($24)
12077		 addiu $14,$14,-2
12078		 sw    $14,0x20($24)
12079		 lw    $25,0x8C($21)
12080		 sw    $15,m68k_ICount
12081		 or    $5,$0,$2
12082		 or    $4,$0,$14
12083		 jalr  $25
12084		 sw    $23,0x4C($21)    	 # Delay slot
12085		 lw    $15,m68k_ICount
12086		 addiu $15,$15,-22
12087		 bgez  $15,3f
12088		 lhu   $24,0x00($23)    	 # Delay slot
12089		 j     MainExit
12090	3:
12091		 sll   $7,$24,2         	 # Delay slot
12092		 addu  $7,$7,$30
12093		 lw    $7,0x00($7)
12094		 jr    $7
12095		 nop                    	 # Delay slot
12096
12097OP0_313a:				#:
12098		 addiu $23,$23,2
12099
12100		 lh    $7,0x00($23)
12101		 subu  $25,$23,$22
12102		 addu  $14,$25,$7       	 # Add Offset to PC
12103		 addiu $23,$23,2
12104		 lw    $25,0x9C($21)
12105		 sw    $15,m68k_ICount
12106		 sw    $24,0x44($29)
12107		 or    $4,$0,$14
12108		 jalr  $25
12109		 sw    $23,0x4C($21)    	 # Delay slot
12110		 lw    $24,0x44($29)
12111		 lw    $15,m68k_ICount
12112		 and   $16,$0,$0        	 # Clear Carry
12113		 and   $17,$0,$0        	 # Clear Overflow
12114		 srl   $19,$2,15         	 # Set Sign
12115		 sltiu $18,$2,1         	 # Set Zero
12116		 srl   $24,$24,7
12117		 andi  $24,$24,0x1C
12118		 addu  $24,$24,$21
12119		 lw    $14,0x20($24)
12120		 addiu $14,$14,-2
12121		 sw    $14,0x20($24)
12122		 lw    $25,0x8C($21)
12123		 sw    $15,m68k_ICount
12124		 or    $5,$0,$2
12125		 or    $4,$0,$14
12126		 jalr  $25
12127		 sw    $23,0x4C($21)    	 # Delay slot
12128		 lw    $15,m68k_ICount
12129		 addiu $15,$15,-18
12130		 bgez  $15,3f
12131		 lhu   $24,0x00($23)    	 # Delay slot
12132		 j     MainExit
12133	3:
12134		 sll   $7,$24,2         	 # Delay slot
12135		 addu  $7,$7,$30
12136		 lw    $7,0x00($7)
12137		 jr    $7
12138		 nop                    	 # Delay slot
12139
12140OP0_313b:				#:
12141		 addiu $23,$23,2
12142
12143		 subu  $14,$23,$22       	 # Get PC
12144		 lhu   $7,0x00($23)
12145		 addiu $23,$23,2
12146		 seb   $6,$7
12147		 or    $25,$0,$7
12148		 srl   $7,$7,12
12149		 andi  $25,$25,0x0800
12150		 sll   $7,$7,2
12151		 addu  $7,$7,$21
12152		 bne   $25,$0,0f
12153		 lw    $25,0x00($7)      	 # Delay slot
12154		 seh   $25,$25
12155	0:
12156		 addu  $25,$14,$25
12157		 addu  $14,$25,$6
12158		 lw    $25,0x9C($21)
12159		 sw    $15,m68k_ICount
12160		 sw    $24,0x44($29)
12161		 or    $4,$0,$14
12162		 jalr  $25
12163		 sw    $23,0x4C($21)    	 # Delay slot
12164		 lw    $24,0x44($29)
12165		 lw    $15,m68k_ICount
12166		 and   $16,$0,$0        	 # Clear Carry
12167		 and   $17,$0,$0        	 # Clear Overflow
12168		 srl   $19,$2,15         	 # Set Sign
12169		 sltiu $18,$2,1         	 # Set Zero
12170		 srl   $24,$24,7
12171		 andi  $24,$24,0x1C
12172		 addu  $24,$24,$21
12173		 lw    $14,0x20($24)
12174		 addiu $14,$14,-2
12175		 sw    $14,0x20($24)
12176		 lw    $25,0x8C($21)
12177		 sw    $15,m68k_ICount
12178		 or    $5,$0,$2
12179		 or    $4,$0,$14
12180		 jalr  $25
12181		 sw    $23,0x4C($21)    	 # Delay slot
12182		 lw    $15,m68k_ICount
12183		 addiu $15,$15,-20
12184		 bgez  $15,3f
12185		 lhu   $24,0x00($23)    	 # Delay slot
12186		 j     MainExit
12187	3:
12188		 sll   $7,$24,2         	 # Delay slot
12189		 addu  $7,$7,$30
12190		 lw    $7,0x00($7)
12191		 jr    $7
12192		 nop                    	 # Delay slot
12193
12194OP0_313c:				#:
12195		 addiu $23,$23,2
12196
12197		 lhu   $2,0x00($23)
12198		 addiu $23,$23,2
12199		 and   $16,$0,$0        	 # Clear Carry
12200		 and   $17,$0,$0        	 # Clear Overflow
12201		 srl   $19,$2,15         	 # Set Sign
12202		 sltiu $18,$2,1         	 # Set Zero
12203		 srl   $24,$24,7
12204		 andi  $24,$24,0x1C
12205		 addu  $24,$24,$21
12206		 lw    $14,0x20($24)
12207		 addiu $14,$14,-2
12208		 sw    $14,0x20($24)
12209		 lw    $25,0x8C($21)
12210		 sw    $15,m68k_ICount
12211		 or    $5,$0,$2
12212		 or    $4,$0,$14
12213		 jalr  $25
12214		 sw    $23,0x4C($21)    	 # Delay slot
12215		 lw    $15,m68k_ICount
12216		 addiu $15,$15,-10
12217		 bgez  $15,3f
12218		 lhu   $24,0x00($23)    	 # Delay slot
12219		 j     MainExit
12220	3:
12221		 sll   $7,$24,2         	 # Delay slot
12222		 addu  $7,$7,$30
12223		 lw    $7,0x00($7)
12224		 jr    $7
12225		 nop                    	 # Delay slot
12226
12227OP0_3140:				#:
12228		 addiu $23,$23,2
12229
12230		 and   $8,$24,0x0f
12231		 sll   $8,$8,2
12232		 addu  $8,$8,$21
12233		 lhu   $2,0x00($8)
12234		 and   $16,$0,$0        	 # Clear Carry
12235		 and   $17,$0,$0        	 # Clear Overflow
12236		 srl   $19,$2,15         	 # Set Sign
12237		 sltiu $18,$2,1         	 # Set Zero
12238		 srl   $24,$24,7
12239		 andi  $24,$24,0x1C
12240		 lh    $7,0x00($23)
12241		 addu  $24,$24,$21
12242		 lw    $14,0x20($24)
12243		 addiu $23,$23,2
12244		 addu  $14,$14,$7
12245		 lw    $25,0x8C($21)
12246		 sw    $15,m68k_ICount
12247		 or    $5,$0,$2
12248		 or    $4,$0,$14
12249		 jalr  $25
12250		 sw    $23,0x4C($21)    	 # Delay slot
12251		 lw    $15,m68k_ICount
12252		 addiu $15,$15,-12
12253		 bgez  $15,3f
12254		 lhu   $24,0x00($23)    	 # Delay slot
12255		 j     MainExit
12256	3:
12257		 sll   $7,$24,2         	 # Delay slot
12258		 addu  $7,$7,$30
12259		 lw    $7,0x00($7)
12260		 jr    $7
12261		 nop                    	 # Delay slot
12262
12263OP0_3150:				#:
12264		 addiu $23,$23,2
12265
12266		 and   $8,$24,0x07
12267		 sll   $8,$8,2
12268		 addu  $8,$8,$21
12269		 lw    $14,0x20($8)
12270		 lw    $25,0x80($21)
12271		 sw    $15,m68k_ICount
12272		 sw    $24,0x44($29)
12273		 or    $4,$0,$14
12274		 jalr  $25
12275		 sw    $23,0x4C($21)    	 # Delay slot
12276		 lw    $24,0x44($29)
12277		 lw    $15,m68k_ICount
12278		 and   $16,$0,$0        	 # Clear Carry
12279		 and   $17,$0,$0        	 # Clear Overflow
12280		 srl   $19,$2,15         	 # Set Sign
12281		 sltiu $18,$2,1         	 # Set Zero
12282		 srl   $24,$24,7
12283		 andi  $24,$24,0x1C
12284		 lh    $7,0x00($23)
12285		 addu  $24,$24,$21
12286		 lw    $14,0x20($24)
12287		 addiu $23,$23,2
12288		 addu  $14,$14,$7
12289		 lw    $25,0x8C($21)
12290		 sw    $15,m68k_ICount
12291		 or    $5,$0,$2
12292		 or    $4,$0,$14
12293		 jalr  $25
12294		 sw    $23,0x4C($21)    	 # Delay slot
12295		 lw    $15,m68k_ICount
12296		 addiu $15,$15,-16
12297		 bgez  $15,3f
12298		 lhu   $24,0x00($23)    	 # Delay slot
12299		 j     MainExit
12300	3:
12301		 sll   $7,$24,2         	 # Delay slot
12302		 addu  $7,$7,$30
12303		 lw    $7,0x00($7)
12304		 jr    $7
12305		 nop                    	 # Delay slot
12306
12307OP0_3158:				#:
12308		 addiu $23,$23,2
12309
12310		 and   $8,$24,0x07
12311		 sll   $8,$8,2
12312		 addu  $8,$8,$21
12313		 lw    $14,0x20($8)
12314		 addiu $25,$14,2
12315		 sw    $25,0x20($8)
12316		 lw    $25,0x80($21)
12317		 sw    $15,m68k_ICount
12318		 sw    $24,0x44($29)
12319		 or    $4,$0,$14
12320		 jalr  $25
12321		 sw    $23,0x4C($21)    	 # Delay slot
12322		 lw    $24,0x44($29)
12323		 lw    $15,m68k_ICount
12324		 and   $16,$0,$0        	 # Clear Carry
12325		 and   $17,$0,$0        	 # Clear Overflow
12326		 srl   $19,$2,15         	 # Set Sign
12327		 sltiu $18,$2,1         	 # Set Zero
12328		 srl   $24,$24,7
12329		 andi  $24,$24,0x1C
12330		 lh    $7,0x00($23)
12331		 addu  $24,$24,$21
12332		 lw    $14,0x20($24)
12333		 addiu $23,$23,2
12334		 addu  $14,$14,$7
12335		 lw    $25,0x8C($21)
12336		 sw    $15,m68k_ICount
12337		 or    $5,$0,$2
12338		 or    $4,$0,$14
12339		 jalr  $25
12340		 sw    $23,0x4C($21)    	 # Delay slot
12341		 lw    $15,m68k_ICount
12342		 addiu $15,$15,-16
12343		 bgez  $15,3f
12344		 lhu   $24,0x00($23)    	 # Delay slot
12345		 j     MainExit
12346	3:
12347		 sll   $7,$24,2         	 # Delay slot
12348		 addu  $7,$7,$30
12349		 lw    $7,0x00($7)
12350		 jr    $7
12351		 nop                    	 # Delay slot
12352
12353OP0_3160:				#:
12354		 addiu $23,$23,2
12355
12356		 and   $8,$24,0x07
12357		 sll   $8,$8,2
12358		 addu  $8,$8,$21
12359		 lw    $14,0x20($8)
12360		 addiu $14,$14,-2
12361		 sw    $14,0x20($8)
12362		 lw    $25,0x80($21)
12363		 sw    $15,m68k_ICount
12364		 sw    $24,0x44($29)
12365		 or    $4,$0,$14
12366		 jalr  $25
12367		 sw    $23,0x4C($21)    	 # Delay slot
12368		 lw    $24,0x44($29)
12369		 lw    $15,m68k_ICount
12370		 and   $16,$0,$0        	 # Clear Carry
12371		 and   $17,$0,$0        	 # Clear Overflow
12372		 srl   $19,$2,15         	 # Set Sign
12373		 sltiu $18,$2,1         	 # Set Zero
12374		 srl   $24,$24,7
12375		 andi  $24,$24,0x1C
12376		 lh    $7,0x00($23)
12377		 addu  $24,$24,$21
12378		 lw    $14,0x20($24)
12379		 addiu $23,$23,2
12380		 addu  $14,$14,$7
12381		 lw    $25,0x8C($21)
12382		 sw    $15,m68k_ICount
12383		 or    $5,$0,$2
12384		 or    $4,$0,$14
12385		 jalr  $25
12386		 sw    $23,0x4C($21)    	 # Delay slot
12387		 lw    $15,m68k_ICount
12388		 addiu $15,$15,-18
12389		 bgez  $15,3f
12390		 lhu   $24,0x00($23)    	 # Delay slot
12391		 j     MainExit
12392	3:
12393		 sll   $7,$24,2         	 # Delay slot
12394		 addu  $7,$7,$30
12395		 lw    $7,0x00($7)
12396		 jr    $7
12397		 nop                    	 # Delay slot
12398
12399OP0_3168:				#:
12400		 addiu $23,$23,2
12401
12402		 and   $8,$24,0x07
12403		 lh    $7,0x00($23)
12404		 sll   $8,$8,2
12405		 addu  $8,$8,$21
12406		 lw    $14,0x20($8)
12407		 addiu $23,$23,2
12408		 addu  $14,$14,$7
12409		 lw    $25,0x80($21)
12410		 sw    $15,m68k_ICount
12411		 sw    $24,0x44($29)
12412		 or    $4,$0,$14
12413		 jalr  $25
12414		 sw    $23,0x4C($21)    	 # Delay slot
12415		 lw    $24,0x44($29)
12416		 lw    $15,m68k_ICount
12417		 and   $16,$0,$0        	 # Clear Carry
12418		 and   $17,$0,$0        	 # Clear Overflow
12419		 srl   $19,$2,15         	 # Set Sign
12420		 sltiu $18,$2,1         	 # Set Zero
12421		 srl   $24,$24,7
12422		 andi  $24,$24,0x1C
12423		 lh    $7,0x00($23)
12424		 addu  $24,$24,$21
12425		 lw    $14,0x20($24)
12426		 addiu $23,$23,2
12427		 addu  $14,$14,$7
12428		 lw    $25,0x8C($21)
12429		 sw    $15,m68k_ICount
12430		 or    $5,$0,$2
12431		 or    $4,$0,$14
12432		 jalr  $25
12433		 sw    $23,0x4C($21)    	 # Delay slot
12434		 lw    $15,m68k_ICount
12435		 addiu $15,$15,-20
12436		 bgez  $15,3f
12437		 lhu   $24,0x00($23)    	 # Delay slot
12438		 j     MainExit
12439	3:
12440		 sll   $7,$24,2         	 # Delay slot
12441		 addu  $7,$7,$30
12442		 lw    $7,0x00($7)
12443		 jr    $7
12444		 nop                    	 # Delay slot
12445
12446OP0_3170:				#:
12447		 addiu $23,$23,2
12448
12449		 and   $8,$24,0x07
12450		 sll   $8,$8,2
12451		 addu  $8,$8,$21
12452		 lw    $14,0x20($8)
12453		 lhu   $7,0x00($23)
12454		 addiu $23,$23,2
12455		 seb   $6,$7
12456		 or    $25,$0,$7
12457		 srl   $7,$7,12
12458		 andi  $25,$25,0x0800
12459		 sll   $7,$7,2
12460		 addu  $7,$7,$21
12461		 bne   $25,$0,0f
12462		 lw    $25,0x00($7)      	 # Delay slot
12463		 seh   $25,$25
12464	0:
12465		 addu  $25,$14,$25
12466		 addu  $14,$25,$6
12467		 lw    $25,0x80($21)
12468		 sw    $15,m68k_ICount
12469		 sw    $24,0x44($29)
12470		 or    $4,$0,$14
12471		 jalr  $25
12472		 sw    $23,0x4C($21)    	 # Delay slot
12473		 lw    $24,0x44($29)
12474		 lw    $15,m68k_ICount
12475		 and   $16,$0,$0        	 # Clear Carry
12476		 and   $17,$0,$0        	 # Clear Overflow
12477		 srl   $19,$2,15         	 # Set Sign
12478		 sltiu $18,$2,1         	 # Set Zero
12479		 srl   $24,$24,7
12480		 andi  $24,$24,0x1C
12481		 lh    $7,0x00($23)
12482		 addu  $24,$24,$21
12483		 lw    $14,0x20($24)
12484		 addiu $23,$23,2
12485		 addu  $14,$14,$7
12486		 lw    $25,0x8C($21)
12487		 sw    $15,m68k_ICount
12488		 or    $5,$0,$2
12489		 or    $4,$0,$14
12490		 jalr  $25
12491		 sw    $23,0x4C($21)    	 # Delay slot
12492		 lw    $15,m68k_ICount
12493		 addiu $15,$15,-22
12494		 bgez  $15,3f
12495		 lhu   $24,0x00($23)    	 # Delay slot
12496		 j     MainExit
12497	3:
12498		 sll   $7,$24,2         	 # Delay slot
12499		 addu  $7,$7,$30
12500		 lw    $7,0x00($7)
12501		 jr    $7
12502		 nop                    	 # Delay slot
12503
12504OP0_3178:				#:
12505		 addiu $23,$23,2
12506
12507		 lh    $14,0x00($23)
12508		 addiu $23,$23,2
12509		 lw    $25,0x80($21)
12510		 sw    $15,m68k_ICount
12511		 sw    $24,0x44($29)
12512		 or    $4,$0,$14
12513		 jalr  $25
12514		 sw    $23,0x4C($21)    	 # Delay slot
12515		 lw    $24,0x44($29)
12516		 lw    $15,m68k_ICount
12517		 and   $16,$0,$0        	 # Clear Carry
12518		 and   $17,$0,$0        	 # Clear Overflow
12519		 srl   $19,$2,15         	 # Set Sign
12520		 sltiu $18,$2,1         	 # Set Zero
12521		 srl   $24,$24,7
12522		 andi  $24,$24,0x1C
12523		 lh    $7,0x00($23)
12524		 addu  $24,$24,$21
12525		 lw    $14,0x20($24)
12526		 addiu $23,$23,2
12527		 addu  $14,$14,$7
12528		 lw    $25,0x8C($21)
12529		 sw    $15,m68k_ICount
12530		 or    $5,$0,$2
12531		 or    $4,$0,$14
12532		 jalr  $25
12533		 sw    $23,0x4C($21)    	 # Delay slot
12534		 lw    $15,m68k_ICount
12535		 addiu $15,$15,-20
12536		 bgez  $15,3f
12537		 lhu   $24,0x00($23)    	 # Delay slot
12538		 j     MainExit
12539	3:
12540		 sll   $7,$24,2         	 # Delay slot
12541		 addu  $7,$7,$30
12542		 lw    $7,0x00($7)
12543		 jr    $7
12544		 nop                    	 # Delay slot
12545
12546OP0_3179:				#:
12547		 addiu $23,$23,2
12548
12549		 lhu   $14,0x00($23)
12550		 lhu   $25,0x02($23)
12551		 sll   $14,$14,16
12552		 or    $14,$14,$25
12553		 addiu $23,$23,4
12554		 lw    $25,0x80($21)
12555		 sw    $15,m68k_ICount
12556		 sw    $24,0x44($29)
12557		 or    $4,$0,$14
12558		 jalr  $25
12559		 sw    $23,0x4C($21)    	 # Delay slot
12560		 lw    $24,0x44($29)
12561		 lw    $15,m68k_ICount
12562		 and   $16,$0,$0        	 # Clear Carry
12563		 and   $17,$0,$0        	 # Clear Overflow
12564		 srl   $19,$2,15         	 # Set Sign
12565		 sltiu $18,$2,1         	 # Set Zero
12566		 srl   $24,$24,7
12567		 andi  $24,$24,0x1C
12568		 lh    $7,0x00($23)
12569		 addu  $24,$24,$21
12570		 lw    $14,0x20($24)
12571		 addiu $23,$23,2
12572		 addu  $14,$14,$7
12573		 lw    $25,0x8C($21)
12574		 sw    $15,m68k_ICount
12575		 or    $5,$0,$2
12576		 or    $4,$0,$14
12577		 jalr  $25
12578		 sw    $23,0x4C($21)    	 # Delay slot
12579		 lw    $15,m68k_ICount
12580		 addiu $15,$15,-24
12581		 bgez  $15,3f
12582		 lhu   $24,0x00($23)    	 # Delay slot
12583		 j     MainExit
12584	3:
12585		 sll   $7,$24,2         	 # Delay slot
12586		 addu  $7,$7,$30
12587		 lw    $7,0x00($7)
12588		 jr    $7
12589		 nop                    	 # Delay slot
12590
12591OP0_317a:				#:
12592		 addiu $23,$23,2
12593
12594		 lh    $7,0x00($23)
12595		 subu  $25,$23,$22
12596		 addu  $14,$25,$7       	 # Add Offset to PC
12597		 addiu $23,$23,2
12598		 lw    $25,0x9C($21)
12599		 sw    $15,m68k_ICount
12600		 sw    $24,0x44($29)
12601		 or    $4,$0,$14
12602		 jalr  $25
12603		 sw    $23,0x4C($21)    	 # Delay slot
12604		 lw    $24,0x44($29)
12605		 lw    $15,m68k_ICount
12606		 and   $16,$0,$0        	 # Clear Carry
12607		 and   $17,$0,$0        	 # Clear Overflow
12608		 srl   $19,$2,15         	 # Set Sign
12609		 sltiu $18,$2,1         	 # Set Zero
12610		 srl   $24,$24,7
12611		 andi  $24,$24,0x1C
12612		 lh    $7,0x00($23)
12613		 addu  $24,$24,$21
12614		 lw    $14,0x20($24)
12615		 addiu $23,$23,2
12616		 addu  $14,$14,$7
12617		 lw    $25,0x8C($21)
12618		 sw    $15,m68k_ICount
12619		 or    $5,$0,$2
12620		 or    $4,$0,$14
12621		 jalr  $25
12622		 sw    $23,0x4C($21)    	 # Delay slot
12623		 lw    $15,m68k_ICount
12624		 addiu $15,$15,-20
12625		 bgez  $15,3f
12626		 lhu   $24,0x00($23)    	 # Delay slot
12627		 j     MainExit
12628	3:
12629		 sll   $7,$24,2         	 # Delay slot
12630		 addu  $7,$7,$30
12631		 lw    $7,0x00($7)
12632		 jr    $7
12633		 nop                    	 # Delay slot
12634
12635OP0_317b:				#:
12636		 addiu $23,$23,2
12637
12638		 subu  $14,$23,$22       	 # Get PC
12639		 lhu   $7,0x00($23)
12640		 addiu $23,$23,2
12641		 seb   $6,$7
12642		 or    $25,$0,$7
12643		 srl   $7,$7,12
12644		 andi  $25,$25,0x0800
12645		 sll   $7,$7,2
12646		 addu  $7,$7,$21
12647		 bne   $25,$0,0f
12648		 lw    $25,0x00($7)      	 # Delay slot
12649		 seh   $25,$25
12650	0:
12651		 addu  $25,$14,$25
12652		 addu  $14,$25,$6
12653		 lw    $25,0x9C($21)
12654		 sw    $15,m68k_ICount
12655		 sw    $24,0x44($29)
12656		 or    $4,$0,$14
12657		 jalr  $25
12658		 sw    $23,0x4C($21)    	 # Delay slot
12659		 lw    $24,0x44($29)
12660		 lw    $15,m68k_ICount
12661		 and   $16,$0,$0        	 # Clear Carry
12662		 and   $17,$0,$0        	 # Clear Overflow
12663		 srl   $19,$2,15         	 # Set Sign
12664		 sltiu $18,$2,1         	 # Set Zero
12665		 srl   $24,$24,7
12666		 andi  $24,$24,0x1C
12667		 lh    $7,0x00($23)
12668		 addu  $24,$24,$21
12669		 lw    $14,0x20($24)
12670		 addiu $23,$23,2
12671		 addu  $14,$14,$7
12672		 lw    $25,0x8C($21)
12673		 sw    $15,m68k_ICount
12674		 or    $5,$0,$2
12675		 or    $4,$0,$14
12676		 jalr  $25
12677		 sw    $23,0x4C($21)    	 # Delay slot
12678		 lw    $15,m68k_ICount
12679		 addiu $15,$15,-22
12680		 bgez  $15,3f
12681		 lhu   $24,0x00($23)    	 # Delay slot
12682		 j     MainExit
12683	3:
12684		 sll   $7,$24,2         	 # Delay slot
12685		 addu  $7,$7,$30
12686		 lw    $7,0x00($7)
12687		 jr    $7
12688		 nop                    	 # Delay slot
12689
12690OP0_317c:				#:
12691		 addiu $23,$23,2
12692
12693		 lhu   $2,0x00($23)
12694		 addiu $23,$23,2
12695		 and   $16,$0,$0        	 # Clear Carry
12696		 and   $17,$0,$0        	 # Clear Overflow
12697		 srl   $19,$2,15         	 # Set Sign
12698		 sltiu $18,$2,1         	 # Set Zero
12699		 srl   $24,$24,7
12700		 andi  $24,$24,0x1C
12701		 lh    $7,0x00($23)
12702		 addu  $24,$24,$21
12703		 lw    $14,0x20($24)
12704		 addiu $23,$23,2
12705		 addu  $14,$14,$7
12706		 lw    $25,0x8C($21)
12707		 sw    $15,m68k_ICount
12708		 or    $5,$0,$2
12709		 or    $4,$0,$14
12710		 jalr  $25
12711		 sw    $23,0x4C($21)    	 # Delay slot
12712		 lw    $15,m68k_ICount
12713		 addiu $15,$15,-12
12714		 bgez  $15,3f
12715		 lhu   $24,0x00($23)    	 # Delay slot
12716		 j     MainExit
12717	3:
12718		 sll   $7,$24,2         	 # Delay slot
12719		 addu  $7,$7,$30
12720		 lw    $7,0x00($7)
12721		 jr    $7
12722		 nop                    	 # Delay slot
12723
12724OP0_3180:				#:
12725		 addiu $23,$23,2
12726
12727		 and   $8,$24,0x0f
12728		 sll   $8,$8,2
12729		 addu  $8,$8,$21
12730		 lhu   $2,0x00($8)
12731		 and   $16,$0,$0        	 # Clear Carry
12732		 and   $17,$0,$0        	 # Clear Overflow
12733		 srl   $19,$2,15         	 # Set Sign
12734		 sltiu $18,$2,1         	 # Set Zero
12735		 srl   $24,$24,7
12736		 andi  $24,$24,0x1C
12737		 addu  $24,$24,$21
12738		 lw    $14,0x20($24)
12739		 lhu   $7,0x00($23)
12740		 addiu $23,$23,2
12741		 seb   $6,$7
12742		 or    $25,$0,$7
12743		 srl   $7,$7,12
12744		 andi  $25,$25,0x0800
12745		 sll   $7,$7,2
12746		 addu  $7,$7,$21
12747		 bne   $25,$0,0f
12748		 lw    $25,0x00($7)      	 # Delay slot
12749		 seh   $25,$25
12750	0:
12751		 addu  $25,$14,$25
12752		 addu  $14,$25,$6
12753		 lw    $25,0x8C($21)
12754		 sw    $15,m68k_ICount
12755		 or    $5,$0,$2
12756		 or    $4,$0,$14
12757		 jalr  $25
12758		 sw    $23,0x4C($21)    	 # Delay slot
12759		 lw    $15,m68k_ICount
12760		 addiu $15,$15,-14
12761		 bgez  $15,3f
12762		 lhu   $24,0x00($23)    	 # Delay slot
12763		 j     MainExit
12764	3:
12765		 sll   $7,$24,2         	 # Delay slot
12766		 addu  $7,$7,$30
12767		 lw    $7,0x00($7)
12768		 jr    $7
12769		 nop                    	 # Delay slot
12770
12771OP0_3190:				#:
12772		 addiu $23,$23,2
12773
12774		 and   $8,$24,0x07
12775		 sll   $8,$8,2
12776		 addu  $8,$8,$21
12777		 lw    $14,0x20($8)
12778		 lw    $25,0x80($21)
12779		 sw    $15,m68k_ICount
12780		 sw    $24,0x44($29)
12781		 or    $4,$0,$14
12782		 jalr  $25
12783		 sw    $23,0x4C($21)    	 # Delay slot
12784		 lw    $24,0x44($29)
12785		 lw    $15,m68k_ICount
12786		 and   $16,$0,$0        	 # Clear Carry
12787		 and   $17,$0,$0        	 # Clear Overflow
12788		 srl   $19,$2,15         	 # Set Sign
12789		 sltiu $18,$2,1         	 # Set Zero
12790		 srl   $24,$24,7
12791		 andi  $24,$24,0x1C
12792		 addu  $24,$24,$21
12793		 lw    $14,0x20($24)
12794		 lhu   $7,0x00($23)
12795		 addiu $23,$23,2
12796		 seb   $6,$7
12797		 or    $25,$0,$7
12798		 srl   $7,$7,12
12799		 andi  $25,$25,0x0800
12800		 sll   $7,$7,2
12801		 addu  $7,$7,$21
12802		 bne   $25,$0,0f
12803		 lw    $25,0x00($7)      	 # Delay slot
12804		 seh   $25,$25
12805	0:
12806		 addu  $25,$14,$25
12807		 addu  $14,$25,$6
12808		 lw    $25,0x8C($21)
12809		 sw    $15,m68k_ICount
12810		 or    $5,$0,$2
12811		 or    $4,$0,$14
12812		 jalr  $25
12813		 sw    $23,0x4C($21)    	 # Delay slot
12814		 lw    $15,m68k_ICount
12815		 addiu $15,$15,-18
12816		 bgez  $15,3f
12817		 lhu   $24,0x00($23)    	 # Delay slot
12818		 j     MainExit
12819	3:
12820		 sll   $7,$24,2         	 # Delay slot
12821		 addu  $7,$7,$30
12822		 lw    $7,0x00($7)
12823		 jr    $7
12824		 nop                    	 # Delay slot
12825
12826OP0_3198:				#:
12827		 addiu $23,$23,2
12828
12829		 and   $8,$24,0x07
12830		 sll   $8,$8,2
12831		 addu  $8,$8,$21
12832		 lw    $14,0x20($8)
12833		 addiu $25,$14,2
12834		 sw    $25,0x20($8)
12835		 lw    $25,0x80($21)
12836		 sw    $15,m68k_ICount
12837		 sw    $24,0x44($29)
12838		 or    $4,$0,$14
12839		 jalr  $25
12840		 sw    $23,0x4C($21)    	 # Delay slot
12841		 lw    $24,0x44($29)
12842		 lw    $15,m68k_ICount
12843		 and   $16,$0,$0        	 # Clear Carry
12844		 and   $17,$0,$0        	 # Clear Overflow
12845		 srl   $19,$2,15         	 # Set Sign
12846		 sltiu $18,$2,1         	 # Set Zero
12847		 srl   $24,$24,7
12848		 andi  $24,$24,0x1C
12849		 addu  $24,$24,$21
12850		 lw    $14,0x20($24)
12851		 lhu   $7,0x00($23)
12852		 addiu $23,$23,2
12853		 seb   $6,$7
12854		 or    $25,$0,$7
12855		 srl   $7,$7,12
12856		 andi  $25,$25,0x0800
12857		 sll   $7,$7,2
12858		 addu  $7,$7,$21
12859		 bne   $25,$0,0f
12860		 lw    $25,0x00($7)      	 # Delay slot
12861		 seh   $25,$25
12862	0:
12863		 addu  $25,$14,$25
12864		 addu  $14,$25,$6
12865		 lw    $25,0x8C($21)
12866		 sw    $15,m68k_ICount
12867		 or    $5,$0,$2
12868		 or    $4,$0,$14
12869		 jalr  $25
12870		 sw    $23,0x4C($21)    	 # Delay slot
12871		 lw    $15,m68k_ICount
12872		 addiu $15,$15,-18
12873		 bgez  $15,3f
12874		 lhu   $24,0x00($23)    	 # Delay slot
12875		 j     MainExit
12876	3:
12877		 sll   $7,$24,2         	 # Delay slot
12878		 addu  $7,$7,$30
12879		 lw    $7,0x00($7)
12880		 jr    $7
12881		 nop                    	 # Delay slot
12882
12883OP0_31a0:				#:
12884		 addiu $23,$23,2
12885
12886		 and   $8,$24,0x07
12887		 sll   $8,$8,2
12888		 addu  $8,$8,$21
12889		 lw    $14,0x20($8)
12890		 addiu $14,$14,-2
12891		 sw    $14,0x20($8)
12892		 lw    $25,0x80($21)
12893		 sw    $15,m68k_ICount
12894		 sw    $24,0x44($29)
12895		 or    $4,$0,$14
12896		 jalr  $25
12897		 sw    $23,0x4C($21)    	 # Delay slot
12898		 lw    $24,0x44($29)
12899		 lw    $15,m68k_ICount
12900		 and   $16,$0,$0        	 # Clear Carry
12901		 and   $17,$0,$0        	 # Clear Overflow
12902		 srl   $19,$2,15         	 # Set Sign
12903		 sltiu $18,$2,1         	 # Set Zero
12904		 srl   $24,$24,7
12905		 andi  $24,$24,0x1C
12906		 addu  $24,$24,$21
12907		 lw    $14,0x20($24)
12908		 lhu   $7,0x00($23)
12909		 addiu $23,$23,2
12910		 seb   $6,$7
12911		 or    $25,$0,$7
12912		 srl   $7,$7,12
12913		 andi  $25,$25,0x0800
12914		 sll   $7,$7,2
12915		 addu  $7,$7,$21
12916		 bne   $25,$0,0f
12917		 lw    $25,0x00($7)      	 # Delay slot
12918		 seh   $25,$25
12919	0:
12920		 addu  $25,$14,$25
12921		 addu  $14,$25,$6
12922		 lw    $25,0x8C($21)
12923		 sw    $15,m68k_ICount
12924		 or    $5,$0,$2
12925		 or    $4,$0,$14
12926		 jalr  $25
12927		 sw    $23,0x4C($21)    	 # Delay slot
12928		 lw    $15,m68k_ICount
12929		 addiu $15,$15,-20
12930		 bgez  $15,3f
12931		 lhu   $24,0x00($23)    	 # Delay slot
12932		 j     MainExit
12933	3:
12934		 sll   $7,$24,2         	 # Delay slot
12935		 addu  $7,$7,$30
12936		 lw    $7,0x00($7)
12937		 jr    $7
12938		 nop                    	 # Delay slot
12939
12940OP0_31a8:				#:
12941		 addiu $23,$23,2
12942
12943		 and   $8,$24,0x07
12944		 lh    $7,0x00($23)
12945		 sll   $8,$8,2
12946		 addu  $8,$8,$21
12947		 lw    $14,0x20($8)
12948		 addiu $23,$23,2
12949		 addu  $14,$14,$7
12950		 lw    $25,0x80($21)
12951		 sw    $15,m68k_ICount
12952		 sw    $24,0x44($29)
12953		 or    $4,$0,$14
12954		 jalr  $25
12955		 sw    $23,0x4C($21)    	 # Delay slot
12956		 lw    $24,0x44($29)
12957		 lw    $15,m68k_ICount
12958		 and   $16,$0,$0        	 # Clear Carry
12959		 and   $17,$0,$0        	 # Clear Overflow
12960		 srl   $19,$2,15         	 # Set Sign
12961		 sltiu $18,$2,1         	 # Set Zero
12962		 srl   $24,$24,7
12963		 andi  $24,$24,0x1C
12964		 addu  $24,$24,$21
12965		 lw    $14,0x20($24)
12966		 lhu   $7,0x00($23)
12967		 addiu $23,$23,2
12968		 seb   $6,$7
12969		 or    $25,$0,$7
12970		 srl   $7,$7,12
12971		 andi  $25,$25,0x0800
12972		 sll   $7,$7,2
12973		 addu  $7,$7,$21
12974		 bne   $25,$0,0f
12975		 lw    $25,0x00($7)      	 # Delay slot
12976		 seh   $25,$25
12977	0:
12978		 addu  $25,$14,$25
12979		 addu  $14,$25,$6
12980		 lw    $25,0x8C($21)
12981		 sw    $15,m68k_ICount
12982		 or    $5,$0,$2
12983		 or    $4,$0,$14
12984		 jalr  $25
12985		 sw    $23,0x4C($21)    	 # Delay slot
12986		 lw    $15,m68k_ICount
12987		 addiu $15,$15,-22
12988		 bgez  $15,3f
12989		 lhu   $24,0x00($23)    	 # Delay slot
12990		 j     MainExit
12991	3:
12992		 sll   $7,$24,2         	 # Delay slot
12993		 addu  $7,$7,$30
12994		 lw    $7,0x00($7)
12995		 jr    $7
12996		 nop                    	 # Delay slot
12997
12998OP0_31b0:				#:
12999		 addiu $23,$23,2
13000
13001		 and   $8,$24,0x07
13002		 sll   $8,$8,2
13003		 addu  $8,$8,$21
13004		 lw    $14,0x20($8)
13005		 lhu   $7,0x00($23)
13006		 addiu $23,$23,2
13007		 seb   $6,$7
13008		 or    $25,$0,$7
13009		 srl   $7,$7,12
13010		 andi  $25,$25,0x0800
13011		 sll   $7,$7,2
13012		 addu  $7,$7,$21
13013		 bne   $25,$0,0f
13014		 lw    $25,0x00($7)      	 # Delay slot
13015		 seh   $25,$25
13016	0:
13017		 addu  $25,$14,$25
13018		 addu  $14,$25,$6
13019		 lw    $25,0x80($21)
13020		 sw    $15,m68k_ICount
13021		 sw    $24,0x44($29)
13022		 or    $4,$0,$14
13023		 jalr  $25
13024		 sw    $23,0x4C($21)    	 # Delay slot
13025		 lw    $24,0x44($29)
13026		 lw    $15,m68k_ICount
13027		 and   $16,$0,$0        	 # Clear Carry
13028		 and   $17,$0,$0        	 # Clear Overflow
13029		 srl   $19,$2,15         	 # Set Sign
13030		 sltiu $18,$2,1         	 # Set Zero
13031		 srl   $24,$24,7
13032		 andi  $24,$24,0x1C
13033		 addu  $24,$24,$21
13034		 lw    $14,0x20($24)
13035		 lhu   $7,0x00($23)
13036		 addiu $23,$23,2
13037		 seb   $6,$7
13038		 or    $25,$0,$7
13039		 srl   $7,$7,12
13040		 andi  $25,$25,0x0800
13041		 sll   $7,$7,2
13042		 addu  $7,$7,$21
13043		 bne   $25,$0,0f
13044		 lw    $25,0x00($7)      	 # Delay slot
13045		 seh   $25,$25
13046	0:
13047		 addu  $25,$14,$25
13048		 addu  $14,$25,$6
13049		 lw    $25,0x8C($21)
13050		 sw    $15,m68k_ICount
13051		 or    $5,$0,$2
13052		 or    $4,$0,$14
13053		 jalr  $25
13054		 sw    $23,0x4C($21)    	 # Delay slot
13055		 lw    $15,m68k_ICount
13056		 addiu $15,$15,-24
13057		 bgez  $15,3f
13058		 lhu   $24,0x00($23)    	 # Delay slot
13059		 j     MainExit
13060	3:
13061		 sll   $7,$24,2         	 # Delay slot
13062		 addu  $7,$7,$30
13063		 lw    $7,0x00($7)
13064		 jr    $7
13065		 nop                    	 # Delay slot
13066
13067OP0_31b8:				#:
13068		 addiu $23,$23,2
13069
13070		 lh    $14,0x00($23)
13071		 addiu $23,$23,2
13072		 lw    $25,0x80($21)
13073		 sw    $15,m68k_ICount
13074		 sw    $24,0x44($29)
13075		 or    $4,$0,$14
13076		 jalr  $25
13077		 sw    $23,0x4C($21)    	 # Delay slot
13078		 lw    $24,0x44($29)
13079		 lw    $15,m68k_ICount
13080		 and   $16,$0,$0        	 # Clear Carry
13081		 and   $17,$0,$0        	 # Clear Overflow
13082		 srl   $19,$2,15         	 # Set Sign
13083		 sltiu $18,$2,1         	 # Set Zero
13084		 srl   $24,$24,7
13085		 andi  $24,$24,0x1C
13086		 addu  $24,$24,$21
13087		 lw    $14,0x20($24)
13088		 lhu   $7,0x00($23)
13089		 addiu $23,$23,2
13090		 seb   $6,$7
13091		 or    $25,$0,$7
13092		 srl   $7,$7,12
13093		 andi  $25,$25,0x0800
13094		 sll   $7,$7,2
13095		 addu  $7,$7,$21
13096		 bne   $25,$0,0f
13097		 lw    $25,0x00($7)      	 # Delay slot
13098		 seh   $25,$25
13099	0:
13100		 addu  $25,$14,$25
13101		 addu  $14,$25,$6
13102		 lw    $25,0x8C($21)
13103		 sw    $15,m68k_ICount
13104		 or    $5,$0,$2
13105		 or    $4,$0,$14
13106		 jalr  $25
13107		 sw    $23,0x4C($21)    	 # Delay slot
13108		 lw    $15,m68k_ICount
13109		 addiu $15,$15,-22
13110		 bgez  $15,3f
13111		 lhu   $24,0x00($23)    	 # Delay slot
13112		 j     MainExit
13113	3:
13114		 sll   $7,$24,2         	 # Delay slot
13115		 addu  $7,$7,$30
13116		 lw    $7,0x00($7)
13117		 jr    $7
13118		 nop                    	 # Delay slot
13119
13120OP0_31b9:				#:
13121		 addiu $23,$23,2
13122
13123		 lhu   $14,0x00($23)
13124		 lhu   $25,0x02($23)
13125		 sll   $14,$14,16
13126		 or    $14,$14,$25
13127		 addiu $23,$23,4
13128		 lw    $25,0x80($21)
13129		 sw    $15,m68k_ICount
13130		 sw    $24,0x44($29)
13131		 or    $4,$0,$14
13132		 jalr  $25
13133		 sw    $23,0x4C($21)    	 # Delay slot
13134		 lw    $24,0x44($29)
13135		 lw    $15,m68k_ICount
13136		 and   $16,$0,$0        	 # Clear Carry
13137		 and   $17,$0,$0        	 # Clear Overflow
13138		 srl   $19,$2,15         	 # Set Sign
13139		 sltiu $18,$2,1         	 # Set Zero
13140		 srl   $24,$24,7
13141		 andi  $24,$24,0x1C
13142		 addu  $24,$24,$21
13143		 lw    $14,0x20($24)
13144		 lhu   $7,0x00($23)
13145		 addiu $23,$23,2
13146		 seb   $6,$7
13147		 or    $25,$0,$7
13148		 srl   $7,$7,12
13149		 andi  $25,$25,0x0800
13150		 sll   $7,$7,2
13151		 addu  $7,$7,$21
13152		 bne   $25,$0,0f
13153		 lw    $25,0x00($7)      	 # Delay slot
13154		 seh   $25,$25
13155	0:
13156		 addu  $25,$14,$25
13157		 addu  $14,$25,$6
13158		 lw    $25,0x8C($21)
13159		 sw    $15,m68k_ICount
13160		 or    $5,$0,$2
13161		 or    $4,$0,$14
13162		 jalr  $25
13163		 sw    $23,0x4C($21)    	 # Delay slot
13164		 lw    $15,m68k_ICount
13165		 addiu $15,$15,-26
13166		 bgez  $15,3f
13167		 lhu   $24,0x00($23)    	 # Delay slot
13168		 j     MainExit
13169	3:
13170		 sll   $7,$24,2         	 # Delay slot
13171		 addu  $7,$7,$30
13172		 lw    $7,0x00($7)
13173		 jr    $7
13174		 nop                    	 # Delay slot
13175
13176OP0_31ba:				#:
13177		 addiu $23,$23,2
13178
13179		 lh    $7,0x00($23)
13180		 subu  $25,$23,$22
13181		 addu  $14,$25,$7       	 # Add Offset to PC
13182		 addiu $23,$23,2
13183		 lw    $25,0x9C($21)
13184		 sw    $15,m68k_ICount
13185		 sw    $24,0x44($29)
13186		 or    $4,$0,$14
13187		 jalr  $25
13188		 sw    $23,0x4C($21)    	 # Delay slot
13189		 lw    $24,0x44($29)
13190		 lw    $15,m68k_ICount
13191		 and   $16,$0,$0        	 # Clear Carry
13192		 and   $17,$0,$0        	 # Clear Overflow
13193		 srl   $19,$2,15         	 # Set Sign
13194		 sltiu $18,$2,1         	 # Set Zero
13195		 srl   $24,$24,7
13196		 andi  $24,$24,0x1C
13197		 addu  $24,$24,$21
13198		 lw    $14,0x20($24)
13199		 lhu   $7,0x00($23)
13200		 addiu $23,$23,2
13201		 seb   $6,$7
13202		 or    $25,$0,$7
13203		 srl   $7,$7,12
13204		 andi  $25,$25,0x0800
13205		 sll   $7,$7,2
13206		 addu  $7,$7,$21
13207		 bne   $25,$0,0f
13208		 lw    $25,0x00($7)      	 # Delay slot
13209		 seh   $25,$25
13210	0:
13211		 addu  $25,$14,$25
13212		 addu  $14,$25,$6
13213		 lw    $25,0x8C($21)
13214		 sw    $15,m68k_ICount
13215		 or    $5,$0,$2
13216		 or    $4,$0,$14
13217		 jalr  $25
13218		 sw    $23,0x4C($21)    	 # Delay slot
13219		 lw    $15,m68k_ICount
13220		 addiu $15,$15,-22
13221		 bgez  $15,3f
13222		 lhu   $24,0x00($23)    	 # Delay slot
13223		 j     MainExit
13224	3:
13225		 sll   $7,$24,2         	 # Delay slot
13226		 addu  $7,$7,$30
13227		 lw    $7,0x00($7)
13228		 jr    $7
13229		 nop                    	 # Delay slot
13230
13231OP0_31bb:				#:
13232		 addiu $23,$23,2
13233
13234		 subu  $14,$23,$22       	 # Get PC
13235		 lhu   $7,0x00($23)
13236		 addiu $23,$23,2
13237		 seb   $6,$7
13238		 or    $25,$0,$7
13239		 srl   $7,$7,12
13240		 andi  $25,$25,0x0800
13241		 sll   $7,$7,2
13242		 addu  $7,$7,$21
13243		 bne   $25,$0,0f
13244		 lw    $25,0x00($7)      	 # Delay slot
13245		 seh   $25,$25
13246	0:
13247		 addu  $25,$14,$25
13248		 addu  $14,$25,$6
13249		 lw    $25,0x9C($21)
13250		 sw    $15,m68k_ICount
13251		 sw    $24,0x44($29)
13252		 or    $4,$0,$14
13253		 jalr  $25
13254		 sw    $23,0x4C($21)    	 # Delay slot
13255		 lw    $24,0x44($29)
13256		 lw    $15,m68k_ICount
13257		 and   $16,$0,$0        	 # Clear Carry
13258		 and   $17,$0,$0        	 # Clear Overflow
13259		 srl   $19,$2,15         	 # Set Sign
13260		 sltiu $18,$2,1         	 # Set Zero
13261		 srl   $24,$24,7
13262		 andi  $24,$24,0x1C
13263		 addu  $24,$24,$21
13264		 lw    $14,0x20($24)
13265		 lhu   $7,0x00($23)
13266		 addiu $23,$23,2
13267		 seb   $6,$7
13268		 or    $25,$0,$7
13269		 srl   $7,$7,12
13270		 andi  $25,$25,0x0800
13271		 sll   $7,$7,2
13272		 addu  $7,$7,$21
13273		 bne   $25,$0,0f
13274		 lw    $25,0x00($7)      	 # Delay slot
13275		 seh   $25,$25
13276	0:
13277		 addu  $25,$14,$25
13278		 addu  $14,$25,$6
13279		 lw    $25,0x8C($21)
13280		 sw    $15,m68k_ICount
13281		 or    $5,$0,$2
13282		 or    $4,$0,$14
13283		 jalr  $25
13284		 sw    $23,0x4C($21)    	 # Delay slot
13285		 lw    $15,m68k_ICount
13286		 addiu $15,$15,-24
13287		 bgez  $15,3f
13288		 lhu   $24,0x00($23)    	 # Delay slot
13289		 j     MainExit
13290	3:
13291		 sll   $7,$24,2         	 # Delay slot
13292		 addu  $7,$7,$30
13293		 lw    $7,0x00($7)
13294		 jr    $7
13295		 nop                    	 # Delay slot
13296
13297OP0_31bc:				#:
13298		 addiu $23,$23,2
13299
13300		 lhu   $2,0x00($23)
13301		 addiu $23,$23,2
13302		 and   $16,$0,$0        	 # Clear Carry
13303		 and   $17,$0,$0        	 # Clear Overflow
13304		 srl   $19,$2,15         	 # Set Sign
13305		 sltiu $18,$2,1         	 # Set Zero
13306		 srl   $24,$24,7
13307		 andi  $24,$24,0x1C
13308		 addu  $24,$24,$21
13309		 lw    $14,0x20($24)
13310		 lhu   $7,0x00($23)
13311		 addiu $23,$23,2
13312		 seb   $6,$7
13313		 or    $25,$0,$7
13314		 srl   $7,$7,12
13315		 andi  $25,$25,0x0800
13316		 sll   $7,$7,2
13317		 addu  $7,$7,$21
13318		 bne   $25,$0,0f
13319		 lw    $25,0x00($7)      	 # Delay slot
13320		 seh   $25,$25
13321	0:
13322		 addu  $25,$14,$25
13323		 addu  $14,$25,$6
13324		 lw    $25,0x8C($21)
13325		 sw    $15,m68k_ICount
13326		 or    $5,$0,$2
13327		 or    $4,$0,$14
13328		 jalr  $25
13329		 sw    $23,0x4C($21)    	 # Delay slot
13330		 lw    $15,m68k_ICount
13331		 addiu $15,$15,-14
13332		 bgez  $15,3f
13333		 lhu   $24,0x00($23)    	 # Delay slot
13334		 j     MainExit
13335	3:
13336		 sll   $7,$24,2         	 # Delay slot
13337		 addu  $7,$7,$30
13338		 lw    $7,0x00($7)
13339		 jr    $7
13340		 nop                    	 # Delay slot
13341
13342OP0_31c0:				#:
13343		 addiu $23,$23,2
13344
13345		 and   $8,$24,0x0f
13346		 sll   $8,$8,2
13347		 addu  $8,$8,$21
13348		 lhu   $2,0x00($8)
13349		 and   $16,$0,$0        	 # Clear Carry
13350		 and   $17,$0,$0        	 # Clear Overflow
13351		 srl   $19,$2,15         	 # Set Sign
13352		 sltiu $18,$2,1         	 # Set Zero
13353		 lh    $14,0x00($23)
13354		 addiu $23,$23,2
13355		 lw    $25,0x8C($21)
13356		 sw    $15,m68k_ICount
13357		 or    $5,$0,$2
13358		 or    $4,$0,$14
13359		 jalr  $25
13360		 sw    $23,0x4C($21)    	 # Delay slot
13361		 lw    $15,m68k_ICount
13362		 addiu $15,$15,-12
13363		 bgez  $15,3f
13364		 lhu   $24,0x00($23)    	 # Delay slot
13365		 j     MainExit
13366	3:
13367		 sll   $7,$24,2         	 # Delay slot
13368		 addu  $7,$7,$30
13369		 lw    $7,0x00($7)
13370		 jr    $7
13371		 nop                    	 # Delay slot
13372
13373OP0_31d0:				#:
13374		 addiu $23,$23,2
13375
13376		 and   $8,$24,0x07
13377		 sll   $8,$8,2
13378		 addu  $8,$8,$21
13379		 lw    $14,0x20($8)
13380		 lw    $25,0x80($21)
13381		 sw    $15,m68k_ICount
13382		 or    $4,$0,$14
13383		 jalr  $25
13384		 sw    $23,0x4C($21)    	 # Delay slot
13385		 lw    $15,m68k_ICount
13386		 and   $16,$0,$0        	 # Clear Carry
13387		 and   $17,$0,$0        	 # Clear Overflow
13388		 srl   $19,$2,15         	 # Set Sign
13389		 sltiu $18,$2,1         	 # Set Zero
13390		 lh    $14,0x00($23)
13391		 addiu $23,$23,2
13392		 lw    $25,0x8C($21)
13393		 sw    $15,m68k_ICount
13394		 or    $5,$0,$2
13395		 or    $4,$0,$14
13396		 jalr  $25
13397		 sw    $23,0x4C($21)    	 # Delay slot
13398		 lw    $15,m68k_ICount
13399		 addiu $15,$15,-16
13400		 bgez  $15,3f
13401		 lhu   $24,0x00($23)    	 # Delay slot
13402		 j     MainExit
13403	3:
13404		 sll   $7,$24,2         	 # Delay slot
13405		 addu  $7,$7,$30
13406		 lw    $7,0x00($7)
13407		 jr    $7
13408		 nop                    	 # Delay slot
13409
13410OP0_31d8:				#:
13411		 addiu $23,$23,2
13412
13413		 and   $8,$24,0x07
13414		 sll   $8,$8,2
13415		 addu  $8,$8,$21
13416		 lw    $14,0x20($8)
13417		 addiu $25,$14,2
13418		 sw    $25,0x20($8)
13419		 lw    $25,0x80($21)
13420		 sw    $15,m68k_ICount
13421		 or    $4,$0,$14
13422		 jalr  $25
13423		 sw    $23,0x4C($21)    	 # Delay slot
13424		 lw    $15,m68k_ICount
13425		 and   $16,$0,$0        	 # Clear Carry
13426		 and   $17,$0,$0        	 # Clear Overflow
13427		 srl   $19,$2,15         	 # Set Sign
13428		 sltiu $18,$2,1         	 # Set Zero
13429		 lh    $14,0x00($23)
13430		 addiu $23,$23,2
13431		 lw    $25,0x8C($21)
13432		 sw    $15,m68k_ICount
13433		 or    $5,$0,$2
13434		 or    $4,$0,$14
13435		 jalr  $25
13436		 sw    $23,0x4C($21)    	 # Delay slot
13437		 lw    $15,m68k_ICount
13438		 addiu $15,$15,-16
13439		 bgez  $15,3f
13440		 lhu   $24,0x00($23)    	 # Delay slot
13441		 j     MainExit
13442	3:
13443		 sll   $7,$24,2         	 # Delay slot
13444		 addu  $7,$7,$30
13445		 lw    $7,0x00($7)
13446		 jr    $7
13447		 nop                    	 # Delay slot
13448
13449OP0_31e0:				#:
13450		 addiu $23,$23,2
13451
13452		 and   $8,$24,0x07
13453		 sll   $8,$8,2
13454		 addu  $8,$8,$21
13455		 lw    $14,0x20($8)
13456		 addiu $14,$14,-2
13457		 sw    $14,0x20($8)
13458		 lw    $25,0x80($21)
13459		 sw    $15,m68k_ICount
13460		 or    $4,$0,$14
13461		 jalr  $25
13462		 sw    $23,0x4C($21)    	 # Delay slot
13463		 lw    $15,m68k_ICount
13464		 and   $16,$0,$0        	 # Clear Carry
13465		 and   $17,$0,$0        	 # Clear Overflow
13466		 srl   $19,$2,15         	 # Set Sign
13467		 sltiu $18,$2,1         	 # Set Zero
13468		 lh    $14,0x00($23)
13469		 addiu $23,$23,2
13470		 lw    $25,0x8C($21)
13471		 sw    $15,m68k_ICount
13472		 or    $5,$0,$2
13473		 or    $4,$0,$14
13474		 jalr  $25
13475		 sw    $23,0x4C($21)    	 # Delay slot
13476		 lw    $15,m68k_ICount
13477		 addiu $15,$15,-18
13478		 bgez  $15,3f
13479		 lhu   $24,0x00($23)    	 # Delay slot
13480		 j     MainExit
13481	3:
13482		 sll   $7,$24,2         	 # Delay slot
13483		 addu  $7,$7,$30
13484		 lw    $7,0x00($7)
13485		 jr    $7
13486		 nop                    	 # Delay slot
13487
13488OP0_31e8:				#:
13489		 addiu $23,$23,2
13490
13491		 and   $8,$24,0x07
13492		 lh    $7,0x00($23)
13493		 sll   $8,$8,2
13494		 addu  $8,$8,$21
13495		 lw    $14,0x20($8)
13496		 addiu $23,$23,2
13497		 addu  $14,$14,$7
13498		 lw    $25,0x80($21)
13499		 sw    $15,m68k_ICount
13500		 or    $4,$0,$14
13501		 jalr  $25
13502		 sw    $23,0x4C($21)    	 # Delay slot
13503		 lw    $15,m68k_ICount
13504		 and   $16,$0,$0        	 # Clear Carry
13505		 and   $17,$0,$0        	 # Clear Overflow
13506		 srl   $19,$2,15         	 # Set Sign
13507		 sltiu $18,$2,1         	 # Set Zero
13508		 lh    $14,0x00($23)
13509		 addiu $23,$23,2
13510		 lw    $25,0x8C($21)
13511		 sw    $15,m68k_ICount
13512		 or    $5,$0,$2
13513		 or    $4,$0,$14
13514		 jalr  $25
13515		 sw    $23,0x4C($21)    	 # Delay slot
13516		 lw    $15,m68k_ICount
13517		 addiu $15,$15,-20
13518		 bgez  $15,3f
13519		 lhu   $24,0x00($23)    	 # Delay slot
13520		 j     MainExit
13521	3:
13522		 sll   $7,$24,2         	 # Delay slot
13523		 addu  $7,$7,$30
13524		 lw    $7,0x00($7)
13525		 jr    $7
13526		 nop                    	 # Delay slot
13527
13528OP0_31f0:				#:
13529		 addiu $23,$23,2
13530
13531		 and   $8,$24,0x07
13532		 sll   $8,$8,2
13533		 addu  $8,$8,$21
13534		 lw    $14,0x20($8)
13535		 lhu   $7,0x00($23)
13536		 addiu $23,$23,2
13537		 seb   $6,$7
13538		 or    $25,$0,$7
13539		 srl   $7,$7,12
13540		 andi  $25,$25,0x0800
13541		 sll   $7,$7,2
13542		 addu  $7,$7,$21
13543		 bne   $25,$0,0f
13544		 lw    $25,0x00($7)      	 # Delay slot
13545		 seh   $25,$25
13546	0:
13547		 addu  $25,$14,$25
13548		 addu  $14,$25,$6
13549		 lw    $25,0x80($21)
13550		 sw    $15,m68k_ICount
13551		 or    $4,$0,$14
13552		 jalr  $25
13553		 sw    $23,0x4C($21)    	 # Delay slot
13554		 lw    $15,m68k_ICount
13555		 and   $16,$0,$0        	 # Clear Carry
13556		 and   $17,$0,$0        	 # Clear Overflow
13557		 srl   $19,$2,15         	 # Set Sign
13558		 sltiu $18,$2,1         	 # Set Zero
13559		 lh    $14,0x00($23)
13560		 addiu $23,$23,2
13561		 lw    $25,0x8C($21)
13562		 sw    $15,m68k_ICount
13563		 or    $5,$0,$2
13564		 or    $4,$0,$14
13565		 jalr  $25
13566		 sw    $23,0x4C($21)    	 # Delay slot
13567		 lw    $15,m68k_ICount
13568		 addiu $15,$15,-22
13569		 bgez  $15,3f
13570		 lhu   $24,0x00($23)    	 # Delay slot
13571		 j     MainExit
13572	3:
13573		 sll   $7,$24,2         	 # Delay slot
13574		 addu  $7,$7,$30
13575		 lw    $7,0x00($7)
13576		 jr    $7
13577		 nop                    	 # Delay slot
13578
13579OP0_31f8:				#:
13580		 addiu $23,$23,2
13581
13582		 lh    $14,0x00($23)
13583		 addiu $23,$23,2
13584		 lw    $25,0x80($21)
13585		 sw    $15,m68k_ICount
13586		 or    $4,$0,$14
13587		 jalr  $25
13588		 sw    $23,0x4C($21)    	 # Delay slot
13589		 lw    $15,m68k_ICount
13590		 and   $16,$0,$0        	 # Clear Carry
13591		 and   $17,$0,$0        	 # Clear Overflow
13592		 srl   $19,$2,15         	 # Set Sign
13593		 sltiu $18,$2,1         	 # Set Zero
13594		 lh    $14,0x00($23)
13595		 addiu $23,$23,2
13596		 lw    $25,0x8C($21)
13597		 sw    $15,m68k_ICount
13598		 or    $5,$0,$2
13599		 or    $4,$0,$14
13600		 jalr  $25
13601		 sw    $23,0x4C($21)    	 # Delay slot
13602		 lw    $15,m68k_ICount
13603		 addiu $15,$15,-20
13604		 bgez  $15,3f
13605		 lhu   $24,0x00($23)    	 # Delay slot
13606		 j     MainExit
13607	3:
13608		 sll   $7,$24,2         	 # Delay slot
13609		 addu  $7,$7,$30
13610		 lw    $7,0x00($7)
13611		 jr    $7
13612		 nop                    	 # Delay slot
13613
13614OP0_31f9:				#:
13615		 addiu $23,$23,2
13616
13617		 lhu   $14,0x00($23)
13618		 lhu   $25,0x02($23)
13619		 sll   $14,$14,16
13620		 or    $14,$14,$25
13621		 addiu $23,$23,4
13622		 lw    $25,0x80($21)
13623		 sw    $15,m68k_ICount
13624		 or    $4,$0,$14
13625		 jalr  $25
13626		 sw    $23,0x4C($21)    	 # Delay slot
13627		 lw    $15,m68k_ICount
13628		 and   $16,$0,$0        	 # Clear Carry
13629		 and   $17,$0,$0        	 # Clear Overflow
13630		 srl   $19,$2,15         	 # Set Sign
13631		 sltiu $18,$2,1         	 # Set Zero
13632		 lh    $14,0x00($23)
13633		 addiu $23,$23,2
13634		 lw    $25,0x8C($21)
13635		 sw    $15,m68k_ICount
13636		 or    $5,$0,$2
13637		 or    $4,$0,$14
13638		 jalr  $25
13639		 sw    $23,0x4C($21)    	 # Delay slot
13640		 lw    $15,m68k_ICount
13641		 addiu $15,$15,-24
13642		 bgez  $15,3f
13643		 lhu   $24,0x00($23)    	 # Delay slot
13644		 j     MainExit
13645	3:
13646		 sll   $7,$24,2         	 # Delay slot
13647		 addu  $7,$7,$30
13648		 lw    $7,0x00($7)
13649		 jr    $7
13650		 nop                    	 # Delay slot
13651
13652OP0_31fa:				#:
13653		 addiu $23,$23,2
13654
13655		 lh    $7,0x00($23)
13656		 subu  $25,$23,$22
13657		 addu  $14,$25,$7       	 # Add Offset to PC
13658		 addiu $23,$23,2
13659		 lw    $25,0x9C($21)
13660		 sw    $15,m68k_ICount
13661		 or    $4,$0,$14
13662		 jalr  $25
13663		 sw    $23,0x4C($21)    	 # Delay slot
13664		 lw    $15,m68k_ICount
13665		 and   $16,$0,$0        	 # Clear Carry
13666		 and   $17,$0,$0        	 # Clear Overflow
13667		 srl   $19,$2,15         	 # Set Sign
13668		 sltiu $18,$2,1         	 # Set Zero
13669		 lh    $14,0x00($23)
13670		 addiu $23,$23,2
13671		 lw    $25,0x8C($21)
13672		 sw    $15,m68k_ICount
13673		 or    $5,$0,$2
13674		 or    $4,$0,$14
13675		 jalr  $25
13676		 sw    $23,0x4C($21)    	 # Delay slot
13677		 lw    $15,m68k_ICount
13678		 addiu $15,$15,-20
13679		 bgez  $15,3f
13680		 lhu   $24,0x00($23)    	 # Delay slot
13681		 j     MainExit
13682	3:
13683		 sll   $7,$24,2         	 # Delay slot
13684		 addu  $7,$7,$30
13685		 lw    $7,0x00($7)
13686		 jr    $7
13687		 nop                    	 # Delay slot
13688
13689OP0_31fb:				#:
13690		 addiu $23,$23,2
13691
13692		 subu  $14,$23,$22       	 # Get PC
13693		 lhu   $7,0x00($23)
13694		 addiu $23,$23,2
13695		 seb   $6,$7
13696		 or    $25,$0,$7
13697		 srl   $7,$7,12
13698		 andi  $25,$25,0x0800
13699		 sll   $7,$7,2
13700		 addu  $7,$7,$21
13701		 bne   $25,$0,0f
13702		 lw    $25,0x00($7)      	 # Delay slot
13703		 seh   $25,$25
13704	0:
13705		 addu  $25,$14,$25
13706		 addu  $14,$25,$6
13707		 lw    $25,0x9C($21)
13708		 sw    $15,m68k_ICount
13709		 or    $4,$0,$14
13710		 jalr  $25
13711		 sw    $23,0x4C($21)    	 # Delay slot
13712		 lw    $15,m68k_ICount
13713		 and   $16,$0,$0        	 # Clear Carry
13714		 and   $17,$0,$0        	 # Clear Overflow
13715		 srl   $19,$2,15         	 # Set Sign
13716		 sltiu $18,$2,1         	 # Set Zero
13717		 lh    $14,0x00($23)
13718		 addiu $23,$23,2
13719		 lw    $25,0x8C($21)
13720		 sw    $15,m68k_ICount
13721		 or    $5,$0,$2
13722		 or    $4,$0,$14
13723		 jalr  $25
13724		 sw    $23,0x4C($21)    	 # Delay slot
13725		 lw    $15,m68k_ICount
13726		 addiu $15,$15,-22
13727		 bgez  $15,3f
13728		 lhu   $24,0x00($23)    	 # Delay slot
13729		 j     MainExit
13730	3:
13731		 sll   $7,$24,2         	 # Delay slot
13732		 addu  $7,$7,$30
13733		 lw    $7,0x00($7)
13734		 jr    $7
13735		 nop                    	 # Delay slot
13736
13737OP0_31fc:				#:
13738		 addiu $23,$23,2
13739
13740		 lhu   $2,0x00($23)
13741		 addiu $23,$23,2
13742		 and   $16,$0,$0        	 # Clear Carry
13743		 and   $17,$0,$0        	 # Clear Overflow
13744		 srl   $19,$2,15         	 # Set Sign
13745		 sltiu $18,$2,1         	 # Set Zero
13746		 lh    $14,0x00($23)
13747		 addiu $23,$23,2
13748		 lw    $25,0x8C($21)
13749		 sw    $15,m68k_ICount
13750		 or    $5,$0,$2
13751		 or    $4,$0,$14
13752		 jalr  $25
13753		 sw    $23,0x4C($21)    	 # Delay slot
13754		 lw    $15,m68k_ICount
13755		 addiu $15,$15,-12
13756		 bgez  $15,3f
13757		 lhu   $24,0x00($23)    	 # Delay slot
13758		 j     MainExit
13759	3:
13760		 sll   $7,$24,2         	 # Delay slot
13761		 addu  $7,$7,$30
13762		 lw    $7,0x00($7)
13763		 jr    $7
13764		 nop                    	 # Delay slot
13765
13766OP0_33c0:				#:
13767		 addiu $23,$23,2
13768
13769		 and   $8,$24,0x0f
13770		 sll   $8,$8,2
13771		 addu  $8,$8,$21
13772		 lhu   $2,0x00($8)
13773		 and   $16,$0,$0        	 # Clear Carry
13774		 and   $17,$0,$0        	 # Clear Overflow
13775		 srl   $19,$2,15         	 # Set Sign
13776		 sltiu $18,$2,1         	 # Set Zero
13777		 lhu   $14,0x00($23)
13778		 lhu   $25,0x02($23)
13779		 sll   $14,$14,16
13780		 or    $14,$14,$25
13781		 addiu $23,$23,4
13782		 lw    $25,0x8C($21)
13783		 sw    $15,m68k_ICount
13784		 or    $5,$0,$2
13785		 or    $4,$0,$14
13786		 jalr  $25
13787		 sw    $23,0x4C($21)    	 # Delay slot
13788		 lw    $15,m68k_ICount
13789		 addiu $15,$15,-16
13790		 bgez  $15,3f
13791		 lhu   $24,0x00($23)    	 # Delay slot
13792		 j     MainExit
13793	3:
13794		 sll   $7,$24,2         	 # Delay slot
13795		 addu  $7,$7,$30
13796		 lw    $7,0x00($7)
13797		 jr    $7
13798		 nop                    	 # Delay slot
13799
13800OP0_33d0:				#:
13801		 addiu $23,$23,2
13802
13803		 and   $8,$24,0x07
13804		 sll   $8,$8,2
13805		 addu  $8,$8,$21
13806		 lw    $14,0x20($8)
13807		 lw    $25,0x80($21)
13808		 sw    $15,m68k_ICount
13809		 or    $4,$0,$14
13810		 jalr  $25
13811		 sw    $23,0x4C($21)    	 # Delay slot
13812		 lw    $15,m68k_ICount
13813		 and   $16,$0,$0        	 # Clear Carry
13814		 and   $17,$0,$0        	 # Clear Overflow
13815		 srl   $19,$2,15         	 # Set Sign
13816		 sltiu $18,$2,1         	 # Set Zero
13817		 lhu   $14,0x00($23)
13818		 lhu   $25,0x02($23)
13819		 sll   $14,$14,16
13820		 or    $14,$14,$25
13821		 addiu $23,$23,4
13822		 lw    $25,0x8C($21)
13823		 sw    $15,m68k_ICount
13824		 or    $5,$0,$2
13825		 or    $4,$0,$14
13826		 jalr  $25
13827		 sw    $23,0x4C($21)    	 # Delay slot
13828		 lw    $15,m68k_ICount
13829		 addiu $15,$15,-20
13830		 bgez  $15,3f
13831		 lhu   $24,0x00($23)    	 # Delay slot
13832		 j     MainExit
13833	3:
13834		 sll   $7,$24,2         	 # Delay slot
13835		 addu  $7,$7,$30
13836		 lw    $7,0x00($7)
13837		 jr    $7
13838		 nop                    	 # Delay slot
13839
13840OP0_33d8:				#:
13841		 addiu $23,$23,2
13842
13843		 and   $8,$24,0x07
13844		 sll   $8,$8,2
13845		 addu  $8,$8,$21
13846		 lw    $14,0x20($8)
13847		 addiu $25,$14,2
13848		 sw    $25,0x20($8)
13849		 lw    $25,0x80($21)
13850		 sw    $15,m68k_ICount
13851		 or    $4,$0,$14
13852		 jalr  $25
13853		 sw    $23,0x4C($21)    	 # Delay slot
13854		 lw    $15,m68k_ICount
13855		 and   $16,$0,$0        	 # Clear Carry
13856		 and   $17,$0,$0        	 # Clear Overflow
13857		 srl   $19,$2,15         	 # Set Sign
13858		 sltiu $18,$2,1         	 # Set Zero
13859		 lhu   $14,0x00($23)
13860		 lhu   $25,0x02($23)
13861		 sll   $14,$14,16
13862		 or    $14,$14,$25
13863		 addiu $23,$23,4
13864		 lw    $25,0x8C($21)
13865		 sw    $15,m68k_ICount
13866		 or    $5,$0,$2
13867		 or    $4,$0,$14
13868		 jalr  $25
13869		 sw    $23,0x4C($21)    	 # Delay slot
13870		 lw    $15,m68k_ICount
13871		 addiu $15,$15,-20
13872		 bgez  $15,3f
13873		 lhu   $24,0x00($23)    	 # Delay slot
13874		 j     MainExit
13875	3:
13876		 sll   $7,$24,2         	 # Delay slot
13877		 addu  $7,$7,$30
13878		 lw    $7,0x00($7)
13879		 jr    $7
13880		 nop                    	 # Delay slot
13881
13882OP0_33e0:				#:
13883		 addiu $23,$23,2
13884
13885		 and   $8,$24,0x07
13886		 sll   $8,$8,2
13887		 addu  $8,$8,$21
13888		 lw    $14,0x20($8)
13889		 addiu $14,$14,-2
13890		 sw    $14,0x20($8)
13891		 lw    $25,0x80($21)
13892		 sw    $15,m68k_ICount
13893		 or    $4,$0,$14
13894		 jalr  $25
13895		 sw    $23,0x4C($21)    	 # Delay slot
13896		 lw    $15,m68k_ICount
13897		 and   $16,$0,$0        	 # Clear Carry
13898		 and   $17,$0,$0        	 # Clear Overflow
13899		 srl   $19,$2,15         	 # Set Sign
13900		 sltiu $18,$2,1         	 # Set Zero
13901		 lhu   $14,0x00($23)
13902		 lhu   $25,0x02($23)
13903		 sll   $14,$14,16
13904		 or    $14,$14,$25
13905		 addiu $23,$23,4
13906		 lw    $25,0x8C($21)
13907		 sw    $15,m68k_ICount
13908		 or    $5,$0,$2
13909		 or    $4,$0,$14
13910		 jalr  $25
13911		 sw    $23,0x4C($21)    	 # Delay slot
13912		 lw    $15,m68k_ICount
13913		 addiu $15,$15,-22
13914		 bgez  $15,3f
13915		 lhu   $24,0x00($23)    	 # Delay slot
13916		 j     MainExit
13917	3:
13918		 sll   $7,$24,2         	 # Delay slot
13919		 addu  $7,$7,$30
13920		 lw    $7,0x00($7)
13921		 jr    $7
13922		 nop                    	 # Delay slot
13923
13924OP0_33e8:				#:
13925		 addiu $23,$23,2
13926
13927		 and   $8,$24,0x07
13928		 lh    $7,0x00($23)
13929		 sll   $8,$8,2
13930		 addu  $8,$8,$21
13931		 lw    $14,0x20($8)
13932		 addiu $23,$23,2
13933		 addu  $14,$14,$7
13934		 lw    $25,0x80($21)
13935		 sw    $15,m68k_ICount
13936		 or    $4,$0,$14
13937		 jalr  $25
13938		 sw    $23,0x4C($21)    	 # Delay slot
13939		 lw    $15,m68k_ICount
13940		 and   $16,$0,$0        	 # Clear Carry
13941		 and   $17,$0,$0        	 # Clear Overflow
13942		 srl   $19,$2,15         	 # Set Sign
13943		 sltiu $18,$2,1         	 # Set Zero
13944		 lhu   $14,0x00($23)
13945		 lhu   $25,0x02($23)
13946		 sll   $14,$14,16
13947		 or    $14,$14,$25
13948		 addiu $23,$23,4
13949		 lw    $25,0x8C($21)
13950		 sw    $15,m68k_ICount
13951		 or    $5,$0,$2
13952		 or    $4,$0,$14
13953		 jalr  $25
13954		 sw    $23,0x4C($21)    	 # Delay slot
13955		 lw    $15,m68k_ICount
13956		 addiu $15,$15,-24
13957		 bgez  $15,3f
13958		 lhu   $24,0x00($23)    	 # Delay slot
13959		 j     MainExit
13960	3:
13961		 sll   $7,$24,2         	 # Delay slot
13962		 addu  $7,$7,$30
13963		 lw    $7,0x00($7)
13964		 jr    $7
13965		 nop                    	 # Delay slot
13966
13967OP0_33f0:				#:
13968		 addiu $23,$23,2
13969
13970		 and   $8,$24,0x07
13971		 sll   $8,$8,2
13972		 addu  $8,$8,$21
13973		 lw    $14,0x20($8)
13974		 lhu   $7,0x00($23)
13975		 addiu $23,$23,2
13976		 seb   $6,$7
13977		 or    $25,$0,$7
13978		 srl   $7,$7,12
13979		 andi  $25,$25,0x0800
13980		 sll   $7,$7,2
13981		 addu  $7,$7,$21
13982		 bne   $25,$0,0f
13983		 lw    $25,0x00($7)      	 # Delay slot
13984		 seh   $25,$25
13985	0:
13986		 addu  $25,$14,$25
13987		 addu  $14,$25,$6
13988		 lw    $25,0x80($21)
13989		 sw    $15,m68k_ICount
13990		 or    $4,$0,$14
13991		 jalr  $25
13992		 sw    $23,0x4C($21)    	 # Delay slot
13993		 lw    $15,m68k_ICount
13994		 and   $16,$0,$0        	 # Clear Carry
13995		 and   $17,$0,$0        	 # Clear Overflow
13996		 srl   $19,$2,15         	 # Set Sign
13997		 sltiu $18,$2,1         	 # Set Zero
13998		 lhu   $14,0x00($23)
13999		 lhu   $25,0x02($23)
14000		 sll   $14,$14,16
14001		 or    $14,$14,$25
14002		 addiu $23,$23,4
14003		 lw    $25,0x8C($21)
14004		 sw    $15,m68k_ICount
14005		 or    $5,$0,$2
14006		 or    $4,$0,$14
14007		 jalr  $25
14008		 sw    $23,0x4C($21)    	 # Delay slot
14009		 lw    $15,m68k_ICount
14010		 addiu $15,$15,-26
14011		 bgez  $15,3f
14012		 lhu   $24,0x00($23)    	 # Delay slot
14013		 j     MainExit
14014	3:
14015		 sll   $7,$24,2         	 # Delay slot
14016		 addu  $7,$7,$30
14017		 lw    $7,0x00($7)
14018		 jr    $7
14019		 nop                    	 # Delay slot
14020
14021OP0_33f8:				#:
14022		 addiu $23,$23,2
14023
14024		 lh    $14,0x00($23)
14025		 addiu $23,$23,2
14026		 lw    $25,0x80($21)
14027		 sw    $15,m68k_ICount
14028		 or    $4,$0,$14
14029		 jalr  $25
14030		 sw    $23,0x4C($21)    	 # Delay slot
14031		 lw    $15,m68k_ICount
14032		 and   $16,$0,$0        	 # Clear Carry
14033		 and   $17,$0,$0        	 # Clear Overflow
14034		 srl   $19,$2,15         	 # Set Sign
14035		 sltiu $18,$2,1         	 # Set Zero
14036		 lhu   $14,0x00($23)
14037		 lhu   $25,0x02($23)
14038		 sll   $14,$14,16
14039		 or    $14,$14,$25
14040		 addiu $23,$23,4
14041		 lw    $25,0x8C($21)
14042		 sw    $15,m68k_ICount
14043		 or    $5,$0,$2
14044		 or    $4,$0,$14
14045		 jalr  $25
14046		 sw    $23,0x4C($21)    	 # Delay slot
14047		 lw    $15,m68k_ICount
14048		 addiu $15,$15,-24
14049		 bgez  $15,3f
14050		 lhu   $24,0x00($23)    	 # Delay slot
14051		 j     MainExit
14052	3:
14053		 sll   $7,$24,2         	 # Delay slot
14054		 addu  $7,$7,$30
14055		 lw    $7,0x00($7)
14056		 jr    $7
14057		 nop                    	 # Delay slot
14058
14059OP0_33f9:				#:
14060		 addiu $23,$23,2
14061
14062		 lhu   $14,0x00($23)
14063		 lhu   $25,0x02($23)
14064		 sll   $14,$14,16
14065		 or    $14,$14,$25
14066		 addiu $23,$23,4
14067		 lw    $25,0x80($21)
14068		 sw    $15,m68k_ICount
14069		 or    $4,$0,$14
14070		 jalr  $25
14071		 sw    $23,0x4C($21)    	 # Delay slot
14072		 lw    $15,m68k_ICount
14073		 and   $16,$0,$0        	 # Clear Carry
14074		 and   $17,$0,$0        	 # Clear Overflow
14075		 srl   $19,$2,15         	 # Set Sign
14076		 sltiu $18,$2,1         	 # Set Zero
14077		 lhu   $14,0x00($23)
14078		 lhu   $25,0x02($23)
14079		 sll   $14,$14,16
14080		 or    $14,$14,$25
14081		 addiu $23,$23,4
14082		 lw    $25,0x8C($21)
14083		 sw    $15,m68k_ICount
14084		 or    $5,$0,$2
14085		 or    $4,$0,$14
14086		 jalr  $25
14087		 sw    $23,0x4C($21)    	 # Delay slot
14088		 lw    $15,m68k_ICount
14089		 addiu $15,$15,-28
14090		 bgez  $15,3f
14091		 lhu   $24,0x00($23)    	 # Delay slot
14092		 j     MainExit
14093	3:
14094		 sll   $7,$24,2         	 # Delay slot
14095		 addu  $7,$7,$30
14096		 lw    $7,0x00($7)
14097		 jr    $7
14098		 nop                    	 # Delay slot
14099
14100OP0_33fa:				#:
14101		 addiu $23,$23,2
14102
14103		 lh    $7,0x00($23)
14104		 subu  $25,$23,$22
14105		 addu  $14,$25,$7       	 # Add Offset to PC
14106		 addiu $23,$23,2
14107		 lw    $25,0x9C($21)
14108		 sw    $15,m68k_ICount
14109		 or    $4,$0,$14
14110		 jalr  $25
14111		 sw    $23,0x4C($21)    	 # Delay slot
14112		 lw    $15,m68k_ICount
14113		 and   $16,$0,$0        	 # Clear Carry
14114		 and   $17,$0,$0        	 # Clear Overflow
14115		 srl   $19,$2,15         	 # Set Sign
14116		 sltiu $18,$2,1         	 # Set Zero
14117		 lhu   $14,0x00($23)
14118		 lhu   $25,0x02($23)
14119		 sll   $14,$14,16
14120		 or    $14,$14,$25
14121		 addiu $23,$23,4
14122		 lw    $25,0x8C($21)
14123		 sw    $15,m68k_ICount
14124		 or    $5,$0,$2
14125		 or    $4,$0,$14
14126		 jalr  $25
14127		 sw    $23,0x4C($21)    	 # Delay slot
14128		 lw    $15,m68k_ICount
14129		 addiu $15,$15,-24
14130		 bgez  $15,3f
14131		 lhu   $24,0x00($23)    	 # Delay slot
14132		 j     MainExit
14133	3:
14134		 sll   $7,$24,2         	 # Delay slot
14135		 addu  $7,$7,$30
14136		 lw    $7,0x00($7)
14137		 jr    $7
14138		 nop                    	 # Delay slot
14139
14140OP0_33fb:				#:
14141		 addiu $23,$23,2
14142
14143		 subu  $14,$23,$22       	 # Get PC
14144		 lhu   $7,0x00($23)
14145		 addiu $23,$23,2
14146		 seb   $6,$7
14147		 or    $25,$0,$7
14148		 srl   $7,$7,12
14149		 andi  $25,$25,0x0800
14150		 sll   $7,$7,2
14151		 addu  $7,$7,$21
14152		 bne   $25,$0,0f
14153		 lw    $25,0x00($7)      	 # Delay slot
14154		 seh   $25,$25
14155	0:
14156		 addu  $25,$14,$25
14157		 addu  $14,$25,$6
14158		 lw    $25,0x9C($21)
14159		 sw    $15,m68k_ICount
14160		 or    $4,$0,$14
14161		 jalr  $25
14162		 sw    $23,0x4C($21)    	 # Delay slot
14163		 lw    $15,m68k_ICount
14164		 and   $16,$0,$0        	 # Clear Carry
14165		 and   $17,$0,$0        	 # Clear Overflow
14166		 srl   $19,$2,15         	 # Set Sign
14167		 sltiu $18,$2,1         	 # Set Zero
14168		 lhu   $14,0x00($23)
14169		 lhu   $25,0x02($23)
14170		 sll   $14,$14,16
14171		 or    $14,$14,$25
14172		 addiu $23,$23,4
14173		 lw    $25,0x8C($21)
14174		 sw    $15,m68k_ICount
14175		 or    $5,$0,$2
14176		 or    $4,$0,$14
14177		 jalr  $25
14178		 sw    $23,0x4C($21)    	 # Delay slot
14179		 lw    $15,m68k_ICount
14180		 addiu $15,$15,-26
14181		 bgez  $15,3f
14182		 lhu   $24,0x00($23)    	 # Delay slot
14183		 j     MainExit
14184	3:
14185		 sll   $7,$24,2         	 # Delay slot
14186		 addu  $7,$7,$30
14187		 lw    $7,0x00($7)
14188		 jr    $7
14189		 nop                    	 # Delay slot
14190
14191OP0_33fc:				#:
14192		 addiu $23,$23,2
14193
14194		 lhu   $2,0x00($23)
14195		 addiu $23,$23,2
14196		 and   $16,$0,$0        	 # Clear Carry
14197		 and   $17,$0,$0        	 # Clear Overflow
14198		 srl   $19,$2,15         	 # Set Sign
14199		 sltiu $18,$2,1         	 # Set Zero
14200		 lhu   $14,0x00($23)
14201		 lhu   $25,0x02($23)
14202		 sll   $14,$14,16
14203		 or    $14,$14,$25
14204		 addiu $23,$23,4
14205		 lw    $25,0x8C($21)
14206		 sw    $15,m68k_ICount
14207		 or    $5,$0,$2
14208		 or    $4,$0,$14
14209		 jalr  $25
14210		 sw    $23,0x4C($21)    	 # Delay slot
14211		 lw    $15,m68k_ICount
14212		 addiu $15,$15,-16
14213		 bgez  $15,3f
14214		 lhu   $24,0x00($23)    	 # Delay slot
14215		 j     MainExit
14216	3:
14217		 sll   $7,$24,2         	 # Delay slot
14218		 addu  $7,$7,$30
14219		 lw    $7,0x00($7)
14220		 jr    $7
14221		 nop                    	 # Delay slot
14222
14223OP0_0000:				#:
14224		 addiu $23,$23,2
14225
14226		 andi  $24,$24,0x07
14227		 lb    $8,0x00($23)
14228		 addiu $23,$23,2
14229		 sll   $24,$24,2
14230		 addu  $24,$24,$21
14231		 lb    $2,0x00($24)
14232		 or    $2,$2,$8
14233		 and   $16,$0,$0        	 # Clear Carry
14234		 and   $17,$0,$0        	 # Clear Overflow
14235		 slt   $19,$2,$0        	 # Set Sign
14236		 sltiu $18,$2,1         	 # Set Zero
14237		 sb    $2,0x00($24)
14238		 addiu $15,$15,-8
14239		 bgez  $15,3f
14240		 lhu   $24,0x00($23)    	 # Delay slot
14241		 j     MainExit
14242	3:
14243		 sll   $7,$24,2         	 # Delay slot
14244		 addu  $7,$7,$30
14245		 lw    $7,0x00($7)
14246		 jr    $7
14247		 nop                    	 # Delay slot
14248
14249OP0_0010:				#:
14250		 addiu $23,$23,2
14251
14252		 andi  $24,$24,0x07
14253		 lb    $8,0x00($23)
14254		 addiu $23,$23,2
14255		 sll   $24,$24,2
14256		 addu  $24,$24,$21
14257		 lw    $14,0x20($24)
14258		 lw    $25,0x7C($21)
14259		 sw    $15,m68k_ICount
14260		 sw    $8,0x44($29)
14261		 sw    $14,0x40($29)
14262		 or    $4,$0,$14
14263		 jalr  $25
14264		 sw    $23,0x4C($21)    	 # Delay slot
14265		 lw    $14,0x40($29)
14266		 lw    $8,0x44($29)
14267		 lw    $15,m68k_ICount
14268		 seb   $2,$2
14269		 or    $2,$2,$8
14270		 and   $16,$0,$0        	 # Clear Carry
14271		 and   $17,$0,$0        	 # Clear Overflow
14272		 slt   $19,$2,$0        	 # Set Sign
14273		 sltiu $18,$2,1         	 # Set Zero
14274		 lw    $25,0x88($21)
14275		 sw    $15,m68k_ICount
14276		 or    $5,$0,$2
14277		 or    $4,$0,$14
14278		 jalr  $25
14279		 sw    $23,0x4C($21)    	 # Delay slot
14280		 lw    $15,m68k_ICount
14281		 addiu $15,$15,-16
14282		 bgez  $15,3f
14283		 lhu   $24,0x00($23)    	 # Delay slot
14284		 j     MainExit
14285	3:
14286		 sll   $7,$24,2         	 # Delay slot
14287		 addu  $7,$7,$30
14288		 lw    $7,0x00($7)
14289		 jr    $7
14290		 nop                    	 # Delay slot
14291
14292OP0_0018:				#:
14293		 addiu $23,$23,2
14294
14295		 andi  $24,$24,0x07
14296		 lb    $8,0x00($23)
14297		 addiu $23,$23,2
14298		 sll   $24,$24,2
14299		 addu  $24,$24,$21
14300		 lw    $14,0x20($24)
14301		 addiu $25,$14,1
14302		 sw    $25,0x20($24)
14303		 lw    $25,0x7C($21)
14304		 sw    $15,m68k_ICount
14305		 sw    $8,0x44($29)
14306		 sw    $14,0x40($29)
14307		 or    $4,$0,$14
14308		 jalr  $25
14309		 sw    $23,0x4C($21)    	 # Delay slot
14310		 lw    $14,0x40($29)
14311		 lw    $8,0x44($29)
14312		 lw    $15,m68k_ICount
14313		 seb   $2,$2
14314		 or    $2,$2,$8
14315		 and   $16,$0,$0        	 # Clear Carry
14316		 and   $17,$0,$0        	 # Clear Overflow
14317		 slt   $19,$2,$0        	 # Set Sign
14318		 sltiu $18,$2,1         	 # Set Zero
14319		 lw    $25,0x88($21)
14320		 sw    $15,m68k_ICount
14321		 or    $5,$0,$2
14322		 or    $4,$0,$14
14323		 jalr  $25
14324		 sw    $23,0x4C($21)    	 # Delay slot
14325		 lw    $15,m68k_ICount
14326		 addiu $15,$15,-16
14327		 bgez  $15,3f
14328		 lhu   $24,0x00($23)    	 # Delay slot
14329		 j     MainExit
14330	3:
14331		 sll   $7,$24,2         	 # Delay slot
14332		 addu  $7,$7,$30
14333		 lw    $7,0x00($7)
14334		 jr    $7
14335		 nop                    	 # Delay slot
14336
14337OP0_001f:				#:
14338		 addiu $23,$23,2
14339
14340		 lb    $8,0x00($23)
14341		 addiu $23,$23,2
14342		 lw    $14,0x3C($21)    	 # Get A7
14343		 addiu $25,$14,2
14344		 sw    $25,0x3C($21)
14345		 lw    $25,0x7C($21)
14346		 sw    $15,m68k_ICount
14347		 sw    $8,0x44($29)
14348		 sw    $14,0x40($29)
14349		 or    $4,$0,$14
14350		 jalr  $25
14351		 sw    $23,0x4C($21)    	 # Delay slot
14352		 lw    $14,0x40($29)
14353		 lw    $8,0x44($29)
14354		 lw    $15,m68k_ICount
14355		 seb   $2,$2
14356		 or    $2,$2,$8
14357		 and   $16,$0,$0        	 # Clear Carry
14358		 and   $17,$0,$0        	 # Clear Overflow
14359		 slt   $19,$2,$0        	 # Set Sign
14360		 sltiu $18,$2,1         	 # Set Zero
14361		 lw    $25,0x88($21)
14362		 sw    $15,m68k_ICount
14363		 or    $5,$0,$2
14364		 or    $4,$0,$14
14365		 jalr  $25
14366		 sw    $23,0x4C($21)    	 # Delay slot
14367		 lw    $15,m68k_ICount
14368		 addiu $15,$15,-16
14369		 bgez  $15,3f
14370		 lhu   $24,0x00($23)    	 # Delay slot
14371		 j     MainExit
14372	3:
14373		 sll   $7,$24,2         	 # Delay slot
14374		 addu  $7,$7,$30
14375		 lw    $7,0x00($7)
14376		 jr    $7
14377		 nop                    	 # Delay slot
14378
14379OP0_0020:				#:
14380		 addiu $23,$23,2
14381
14382		 andi  $24,$24,0x07
14383		 lb    $8,0x00($23)
14384		 addiu $23,$23,2
14385		 sll   $24,$24,2
14386		 addu  $24,$24,$21
14387		 lw    $14,0x20($24)
14388		 addiu $14,$14,-1
14389		 sw    $14,0x20($24)
14390		 lw    $25,0x7C($21)
14391		 sw    $15,m68k_ICount
14392		 sw    $8,0x44($29)
14393		 sw    $14,0x40($29)
14394		 or    $4,$0,$14
14395		 jalr  $25
14396		 sw    $23,0x4C($21)    	 # Delay slot
14397		 lw    $14,0x40($29)
14398		 lw    $8,0x44($29)
14399		 lw    $15,m68k_ICount
14400		 seb   $2,$2
14401		 or    $2,$2,$8
14402		 and   $16,$0,$0        	 # Clear Carry
14403		 and   $17,$0,$0        	 # Clear Overflow
14404		 slt   $19,$2,$0        	 # Set Sign
14405		 sltiu $18,$2,1         	 # Set Zero
14406		 lw    $25,0x88($21)
14407		 sw    $15,m68k_ICount
14408		 or    $5,$0,$2
14409		 or    $4,$0,$14
14410		 jalr  $25
14411		 sw    $23,0x4C($21)    	 # Delay slot
14412		 lw    $15,m68k_ICount
14413		 addiu $15,$15,-18
14414		 bgez  $15,3f
14415		 lhu   $24,0x00($23)    	 # Delay slot
14416		 j     MainExit
14417	3:
14418		 sll   $7,$24,2         	 # Delay slot
14419		 addu  $7,$7,$30
14420		 lw    $7,0x00($7)
14421		 jr    $7
14422		 nop                    	 # Delay slot
14423
14424OP0_0027:				#:
14425		 addiu $23,$23,2
14426
14427		 lb    $8,0x00($23)
14428		 addiu $23,$23,2
14429		 lw    $14,0x3C($21)    	 # Get A7
14430		 addiu $14,$14,-2
14431		 sw    $14,0x3C($21)
14432		 lw    $25,0x7C($21)
14433		 sw    $15,m68k_ICount
14434		 sw    $8,0x44($29)
14435		 sw    $14,0x40($29)
14436		 or    $4,$0,$14
14437		 jalr  $25
14438		 sw    $23,0x4C($21)    	 # Delay slot
14439		 lw    $14,0x40($29)
14440		 lw    $8,0x44($29)
14441		 lw    $15,m68k_ICount
14442		 seb   $2,$2
14443		 or    $2,$2,$8
14444		 and   $16,$0,$0        	 # Clear Carry
14445		 and   $17,$0,$0        	 # Clear Overflow
14446		 slt   $19,$2,$0        	 # Set Sign
14447		 sltiu $18,$2,1         	 # Set Zero
14448		 lw    $25,0x88($21)
14449		 sw    $15,m68k_ICount
14450		 or    $5,$0,$2
14451		 or    $4,$0,$14
14452		 jalr  $25
14453		 sw    $23,0x4C($21)    	 # Delay slot
14454		 lw    $15,m68k_ICount
14455		 addiu $15,$15,-18
14456		 bgez  $15,3f
14457		 lhu   $24,0x00($23)    	 # Delay slot
14458		 j     MainExit
14459	3:
14460		 sll   $7,$24,2         	 # Delay slot
14461		 addu  $7,$7,$30
14462		 lw    $7,0x00($7)
14463		 jr    $7
14464		 nop                    	 # Delay slot
14465
14466OP0_0028:				#:
14467		 addiu $23,$23,2
14468
14469		 andi  $24,$24,0x07
14470		 lb    $8,0x00($23)
14471		 addiu $23,$23,2
14472		 lh    $7,0x00($23)
14473		 sll   $24,$24,2
14474		 addu  $24,$24,$21
14475		 lw    $14,0x20($24)
14476		 addiu $23,$23,2
14477		 addu  $14,$14,$7
14478		 lw    $25,0x7C($21)
14479		 sw    $15,m68k_ICount
14480		 sw    $8,0x44($29)
14481		 sw    $14,0x40($29)
14482		 or    $4,$0,$14
14483		 jalr  $25
14484		 sw    $23,0x4C($21)    	 # Delay slot
14485		 lw    $14,0x40($29)
14486		 lw    $8,0x44($29)
14487		 lw    $15,m68k_ICount
14488		 seb   $2,$2
14489		 or    $2,$2,$8
14490		 and   $16,$0,$0        	 # Clear Carry
14491		 and   $17,$0,$0        	 # Clear Overflow
14492		 slt   $19,$2,$0        	 # Set Sign
14493		 sltiu $18,$2,1         	 # Set Zero
14494		 lw    $25,0x88($21)
14495		 sw    $15,m68k_ICount
14496		 or    $5,$0,$2
14497		 or    $4,$0,$14
14498		 jalr  $25
14499		 sw    $23,0x4C($21)    	 # Delay slot
14500		 lw    $15,m68k_ICount
14501		 addiu $15,$15,-20
14502		 bgez  $15,3f
14503		 lhu   $24,0x00($23)    	 # Delay slot
14504		 j     MainExit
14505	3:
14506		 sll   $7,$24,2         	 # Delay slot
14507		 addu  $7,$7,$30
14508		 lw    $7,0x00($7)
14509		 jr    $7
14510		 nop                    	 # Delay slot
14511
14512OP0_0030:				#:
14513		 addiu $23,$23,2
14514
14515		 andi  $24,$24,0x07
14516		 lb    $8,0x00($23)
14517		 addiu $23,$23,2
14518		 sll   $24,$24,2
14519		 addu  $24,$24,$21
14520		 lw    $14,0x20($24)
14521		 lhu   $7,0x00($23)
14522		 addiu $23,$23,2
14523		 seb   $6,$7
14524		 or    $25,$0,$7
14525		 srl   $7,$7,12
14526		 andi  $25,$25,0x0800
14527		 sll   $7,$7,2
14528		 addu  $7,$7,$21
14529		 bne   $25,$0,0f
14530		 lw    $25,0x00($7)      	 # Delay slot
14531		 seh   $25,$25
14532	0:
14533		 addu  $25,$14,$25
14534		 addu  $14,$25,$6
14535		 lw    $25,0x7C($21)
14536		 sw    $15,m68k_ICount
14537		 sw    $8,0x44($29)
14538		 sw    $14,0x40($29)
14539		 or    $4,$0,$14
14540		 jalr  $25
14541		 sw    $23,0x4C($21)    	 # Delay slot
14542		 lw    $14,0x40($29)
14543		 lw    $8,0x44($29)
14544		 lw    $15,m68k_ICount
14545		 seb   $2,$2
14546		 or    $2,$2,$8
14547		 and   $16,$0,$0        	 # Clear Carry
14548		 and   $17,$0,$0        	 # Clear Overflow
14549		 slt   $19,$2,$0        	 # Set Sign
14550		 sltiu $18,$2,1         	 # Set Zero
14551		 lw    $25,0x88($21)
14552		 sw    $15,m68k_ICount
14553		 or    $5,$0,$2
14554		 or    $4,$0,$14
14555		 jalr  $25
14556		 sw    $23,0x4C($21)    	 # Delay slot
14557		 lw    $15,m68k_ICount
14558		 addiu $15,$15,-22
14559		 bgez  $15,3f
14560		 lhu   $24,0x00($23)    	 # Delay slot
14561		 j     MainExit
14562	3:
14563		 sll   $7,$24,2         	 # Delay slot
14564		 addu  $7,$7,$30
14565		 lw    $7,0x00($7)
14566		 jr    $7
14567		 nop                    	 # Delay slot
14568
14569OP0_0038:				#:
14570		 addiu $23,$23,2
14571
14572		 lb    $8,0x00($23)
14573		 addiu $23,$23,2
14574		 lh    $14,0x00($23)
14575		 addiu $23,$23,2
14576		 lw    $25,0x7C($21)
14577		 sw    $15,m68k_ICount
14578		 sw    $8,0x44($29)
14579		 sw    $14,0x40($29)
14580		 or    $4,$0,$14
14581		 jalr  $25
14582		 sw    $23,0x4C($21)    	 # Delay slot
14583		 lw    $14,0x40($29)
14584		 lw    $8,0x44($29)
14585		 lw    $15,m68k_ICount
14586		 seb   $2,$2
14587		 or    $2,$2,$8
14588		 and   $16,$0,$0        	 # Clear Carry
14589		 and   $17,$0,$0        	 # Clear Overflow
14590		 slt   $19,$2,$0        	 # Set Sign
14591		 sltiu $18,$2,1         	 # Set Zero
14592		 lw    $25,0x88($21)
14593		 sw    $15,m68k_ICount
14594		 or    $5,$0,$2
14595		 or    $4,$0,$14
14596		 jalr  $25
14597		 sw    $23,0x4C($21)    	 # Delay slot
14598		 lw    $15,m68k_ICount
14599		 addiu $15,$15,-20
14600		 bgez  $15,3f
14601		 lhu   $24,0x00($23)    	 # Delay slot
14602		 j     MainExit
14603	3:
14604		 sll   $7,$24,2         	 # Delay slot
14605		 addu  $7,$7,$30
14606		 lw    $7,0x00($7)
14607		 jr    $7
14608		 nop                    	 # Delay slot
14609
14610OP0_0039:				#:
14611		 addiu $23,$23,2
14612
14613		 lb    $8,0x00($23)
14614		 addiu $23,$23,2
14615		 lhu   $14,0x00($23)
14616		 lhu   $25,0x02($23)
14617		 sll   $14,$14,16
14618		 or    $14,$14,$25
14619		 addiu $23,$23,4
14620		 lw    $25,0x7C($21)
14621		 sw    $15,m68k_ICount
14622		 sw    $8,0x44($29)
14623		 sw    $14,0x40($29)
14624		 or    $4,$0,$14
14625		 jalr  $25
14626		 sw    $23,0x4C($21)    	 # Delay slot
14627		 lw    $14,0x40($29)
14628		 lw    $8,0x44($29)
14629		 lw    $15,m68k_ICount
14630		 seb   $2,$2
14631		 or    $2,$2,$8
14632		 and   $16,$0,$0        	 # Clear Carry
14633		 and   $17,$0,$0        	 # Clear Overflow
14634		 slt   $19,$2,$0        	 # Set Sign
14635		 sltiu $18,$2,1         	 # Set Zero
14636		 lw    $25,0x88($21)
14637		 sw    $15,m68k_ICount
14638		 or    $5,$0,$2
14639		 or    $4,$0,$14
14640		 jalr  $25
14641		 sw    $23,0x4C($21)    	 # Delay slot
14642		 lw    $15,m68k_ICount
14643		 addiu $15,$15,-24
14644		 bgez  $15,3f
14645		 lhu   $24,0x00($23)    	 # Delay slot
14646		 j     MainExit
14647	3:
14648		 sll   $7,$24,2         	 # Delay slot
14649		 addu  $7,$7,$30
14650		 lw    $7,0x00($7)
14651		 jr    $7
14652		 nop                    	 # Delay slot
14653
14654OP0_003c:				#:
14655		 addiu $23,$23,2
14656
14657		 lbu   $8,0x00($23)
14658		 addiu $23,$23,2
14659		 or    $2,$0,$20
14660		 sll   $2,$2,1
14661		 or    $2,$2,$19
14662		 sll   $2,$2,1
14663		 or    $2,$2,$18
14664		 sll   $2,$2,1
14665		 or    $2,$2,$17
14666		 sll   $2,$2,1
14667		 or    $2,$2,$16
14668		 or    $2,$2,$8
14669		 or    $20,$0,$2
14670		 or    $19,$0,$2
14671		 or    $18,$0,$2
14672		 or    $17,$0,$2
14673		 or    $16,$0,$2
14674		 andi  $20,$20,0x10
14675		 andi  $19,$19,0x08
14676		 andi  $18,$18,0x04
14677		 andi  $17,$17,0x02
14678		 andi  $16,$16,0x01
14679		 srl   $20,$20,4
14680		 srl   $19,$19,3
14681		 srl   $18,$18,2
14682		 srl   $17,$17,1
14683		 addiu $15,$15,-20
14684		 bgez  $15,3f
14685		 lhu   $24,0x00($23)    	 # Delay slot
14686		 j     MainExit
14687	3:
14688		 sll   $7,$24,2         	 # Delay slot
14689		 addu  $7,$7,$30
14690		 lw    $7,0x00($7)
14691		 jr    $7
14692		 nop                    	 # Delay slot
14693
14694OP0_0040:				#:
14695		 addiu $23,$23,2
14696
14697		 andi  $24,$24,0x07
14698		 lh    $8,0x00($23)
14699		 addiu $23,$23,2
14700		 sll   $24,$24,2
14701		 addu  $24,$24,$21
14702		 lh    $2,0x00($24)
14703		 or    $2,$2,$8
14704		 and   $16,$0,$0        	 # Clear Carry
14705		 and   $17,$0,$0        	 # Clear Overflow
14706		 slt   $19,$2,$0        	 # Set Sign
14707		 sltiu $18,$2,1         	 # Set Zero
14708		 sh    $2,0x00($24)
14709		 addiu $15,$15,-8
14710		 bgez  $15,3f
14711		 lhu   $24,0x00($23)    	 # Delay slot
14712		 j     MainExit
14713	3:
14714		 sll   $7,$24,2         	 # Delay slot
14715		 addu  $7,$7,$30
14716		 lw    $7,0x00($7)
14717		 jr    $7
14718		 nop                    	 # Delay slot
14719
14720OP0_0050:				#:
14721		 addiu $23,$23,2
14722
14723		 andi  $24,$24,0x07
14724		 lh    $8,0x00($23)
14725		 addiu $23,$23,2
14726		 sll   $24,$24,2
14727		 addu  $24,$24,$21
14728		 lw    $14,0x20($24)
14729		 lw    $25,0x80($21)
14730		 sw    $15,m68k_ICount
14731		 sw    $8,0x44($29)
14732		 sw    $14,0x40($29)
14733		 or    $4,$0,$14
14734		 jalr  $25
14735		 sw    $23,0x4C($21)    	 # Delay slot
14736		 lw    $14,0x40($29)
14737		 lw    $8,0x44($29)
14738		 lw    $15,m68k_ICount
14739		 seh   $2,$2
14740		 or    $2,$2,$8
14741		 and   $16,$0,$0        	 # Clear Carry
14742		 and   $17,$0,$0        	 # Clear Overflow
14743		 slt   $19,$2,$0        	 # Set Sign
14744		 sltiu $18,$2,1         	 # Set Zero
14745		 lw    $25,0x8C($21)
14746		 sw    $15,m68k_ICount
14747		 or    $5,$0,$2
14748		 or    $4,$0,$14
14749		 jalr  $25
14750		 sw    $23,0x4C($21)    	 # Delay slot
14751		 lw    $15,m68k_ICount
14752		 addiu $15,$15,-16
14753		 bgez  $15,3f
14754		 lhu   $24,0x00($23)    	 # Delay slot
14755		 j     MainExit
14756	3:
14757		 sll   $7,$24,2         	 # Delay slot
14758		 addu  $7,$7,$30
14759		 lw    $7,0x00($7)
14760		 jr    $7
14761		 nop                    	 # Delay slot
14762
14763OP0_0058:				#:
14764		 addiu $23,$23,2
14765
14766		 andi  $24,$24,0x07
14767		 lh    $8,0x00($23)
14768		 addiu $23,$23,2
14769		 sll   $24,$24,2
14770		 addu  $24,$24,$21
14771		 lw    $14,0x20($24)
14772		 addiu $25,$14,2
14773		 sw    $25,0x20($24)
14774		 lw    $25,0x80($21)
14775		 sw    $15,m68k_ICount
14776		 sw    $8,0x44($29)
14777		 sw    $14,0x40($29)
14778		 or    $4,$0,$14
14779		 jalr  $25
14780		 sw    $23,0x4C($21)    	 # Delay slot
14781		 lw    $14,0x40($29)
14782		 lw    $8,0x44($29)
14783		 lw    $15,m68k_ICount
14784		 seh   $2,$2
14785		 or    $2,$2,$8
14786		 and   $16,$0,$0        	 # Clear Carry
14787		 and   $17,$0,$0        	 # Clear Overflow
14788		 slt   $19,$2,$0        	 # Set Sign
14789		 sltiu $18,$2,1         	 # Set Zero
14790		 lw    $25,0x8C($21)
14791		 sw    $15,m68k_ICount
14792		 or    $5,$0,$2
14793		 or    $4,$0,$14
14794		 jalr  $25
14795		 sw    $23,0x4C($21)    	 # Delay slot
14796		 lw    $15,m68k_ICount
14797		 addiu $15,$15,-16
14798		 bgez  $15,3f
14799		 lhu   $24,0x00($23)    	 # Delay slot
14800		 j     MainExit
14801	3:
14802		 sll   $7,$24,2         	 # Delay slot
14803		 addu  $7,$7,$30
14804		 lw    $7,0x00($7)
14805		 jr    $7
14806		 nop                    	 # Delay slot
14807
14808OP0_0060:				#:
14809		 addiu $23,$23,2
14810
14811		 andi  $24,$24,0x07
14812		 lh    $8,0x00($23)
14813		 addiu $23,$23,2
14814		 sll   $24,$24,2
14815		 addu  $24,$24,$21
14816		 lw    $14,0x20($24)
14817		 addiu $14,$14,-2
14818		 sw    $14,0x20($24)
14819		 lw    $25,0x80($21)
14820		 sw    $15,m68k_ICount
14821		 sw    $8,0x44($29)
14822		 sw    $14,0x40($29)
14823		 or    $4,$0,$14
14824		 jalr  $25
14825		 sw    $23,0x4C($21)    	 # Delay slot
14826		 lw    $14,0x40($29)
14827		 lw    $8,0x44($29)
14828		 lw    $15,m68k_ICount
14829		 seh   $2,$2
14830		 or    $2,$2,$8
14831		 and   $16,$0,$0        	 # Clear Carry
14832		 and   $17,$0,$0        	 # Clear Overflow
14833		 slt   $19,$2,$0        	 # Set Sign
14834		 sltiu $18,$2,1         	 # Set Zero
14835		 lw    $25,0x8C($21)
14836		 sw    $15,m68k_ICount
14837		 or    $5,$0,$2
14838		 or    $4,$0,$14
14839		 jalr  $25
14840		 sw    $23,0x4C($21)    	 # Delay slot
14841		 lw    $15,m68k_ICount
14842		 addiu $15,$15,-18
14843		 bgez  $15,3f
14844		 lhu   $24,0x00($23)    	 # Delay slot
14845		 j     MainExit
14846	3:
14847		 sll   $7,$24,2         	 # Delay slot
14848		 addu  $7,$7,$30
14849		 lw    $7,0x00($7)
14850		 jr    $7
14851		 nop                    	 # Delay slot
14852
14853OP0_0068:				#:
14854		 addiu $23,$23,2
14855
14856		 andi  $24,$24,0x07
14857		 lh    $8,0x00($23)
14858		 addiu $23,$23,2
14859		 lh    $7,0x00($23)
14860		 sll   $24,$24,2
14861		 addu  $24,$24,$21
14862		 lw    $14,0x20($24)
14863		 addiu $23,$23,2
14864		 addu  $14,$14,$7
14865		 lw    $25,0x80($21)
14866		 sw    $15,m68k_ICount
14867		 sw    $8,0x44($29)
14868		 sw    $14,0x40($29)
14869		 or    $4,$0,$14
14870		 jalr  $25
14871		 sw    $23,0x4C($21)    	 # Delay slot
14872		 lw    $14,0x40($29)
14873		 lw    $8,0x44($29)
14874		 lw    $15,m68k_ICount
14875		 seh   $2,$2
14876		 or    $2,$2,$8
14877		 and   $16,$0,$0        	 # Clear Carry
14878		 and   $17,$0,$0        	 # Clear Overflow
14879		 slt   $19,$2,$0        	 # Set Sign
14880		 sltiu $18,$2,1         	 # Set Zero
14881		 lw    $25,0x8C($21)
14882		 sw    $15,m68k_ICount
14883		 or    $5,$0,$2
14884		 or    $4,$0,$14
14885		 jalr  $25
14886		 sw    $23,0x4C($21)    	 # Delay slot
14887		 lw    $15,m68k_ICount
14888		 addiu $15,$15,-20
14889		 bgez  $15,3f
14890		 lhu   $24,0x00($23)    	 # Delay slot
14891		 j     MainExit
14892	3:
14893		 sll   $7,$24,2         	 # Delay slot
14894		 addu  $7,$7,$30
14895		 lw    $7,0x00($7)
14896		 jr    $7
14897		 nop                    	 # Delay slot
14898
14899OP0_0070:				#:
14900		 addiu $23,$23,2
14901
14902		 andi  $24,$24,0x07
14903		 lh    $8,0x00($23)
14904		 addiu $23,$23,2
14905		 sll   $24,$24,2
14906		 addu  $24,$24,$21
14907		 lw    $14,0x20($24)
14908		 lhu   $7,0x00($23)
14909		 addiu $23,$23,2
14910		 seb   $6,$7
14911		 or    $25,$0,$7
14912		 srl   $7,$7,12
14913		 andi  $25,$25,0x0800
14914		 sll   $7,$7,2
14915		 addu  $7,$7,$21
14916		 bne   $25,$0,0f
14917		 lw    $25,0x00($7)      	 # Delay slot
14918		 seh   $25,$25
14919	0:
14920		 addu  $25,$14,$25
14921		 addu  $14,$25,$6
14922		 lw    $25,0x80($21)
14923		 sw    $15,m68k_ICount
14924		 sw    $8,0x44($29)
14925		 sw    $14,0x40($29)
14926		 or    $4,$0,$14
14927		 jalr  $25
14928		 sw    $23,0x4C($21)    	 # Delay slot
14929		 lw    $14,0x40($29)
14930		 lw    $8,0x44($29)
14931		 lw    $15,m68k_ICount
14932		 seh   $2,$2
14933		 or    $2,$2,$8
14934		 and   $16,$0,$0        	 # Clear Carry
14935		 and   $17,$0,$0        	 # Clear Overflow
14936		 slt   $19,$2,$0        	 # Set Sign
14937		 sltiu $18,$2,1         	 # Set Zero
14938		 lw    $25,0x8C($21)
14939		 sw    $15,m68k_ICount
14940		 or    $5,$0,$2
14941		 or    $4,$0,$14
14942		 jalr  $25
14943		 sw    $23,0x4C($21)    	 # Delay slot
14944		 lw    $15,m68k_ICount
14945		 addiu $15,$15,-22
14946		 bgez  $15,3f
14947		 lhu   $24,0x00($23)    	 # Delay slot
14948		 j     MainExit
14949	3:
14950		 sll   $7,$24,2         	 # Delay slot
14951		 addu  $7,$7,$30
14952		 lw    $7,0x00($7)
14953		 jr    $7
14954		 nop                    	 # Delay slot
14955
14956OP0_0078:				#:
14957		 addiu $23,$23,2
14958
14959		 lh    $8,0x00($23)
14960		 addiu $23,$23,2
14961		 lh    $14,0x00($23)
14962		 addiu $23,$23,2
14963		 lw    $25,0x80($21)
14964		 sw    $15,m68k_ICount
14965		 sw    $8,0x44($29)
14966		 sw    $14,0x40($29)
14967		 or    $4,$0,$14
14968		 jalr  $25
14969		 sw    $23,0x4C($21)    	 # Delay slot
14970		 lw    $14,0x40($29)
14971		 lw    $8,0x44($29)
14972		 lw    $15,m68k_ICount
14973		 seh   $2,$2
14974		 or    $2,$2,$8
14975		 and   $16,$0,$0        	 # Clear Carry
14976		 and   $17,$0,$0        	 # Clear Overflow
14977		 slt   $19,$2,$0        	 # Set Sign
14978		 sltiu $18,$2,1         	 # Set Zero
14979		 lw    $25,0x8C($21)
14980		 sw    $15,m68k_ICount
14981		 or    $5,$0,$2
14982		 or    $4,$0,$14
14983		 jalr  $25
14984		 sw    $23,0x4C($21)    	 # Delay slot
14985		 lw    $15,m68k_ICount
14986		 addiu $15,$15,-20
14987		 bgez  $15,3f
14988		 lhu   $24,0x00($23)    	 # Delay slot
14989		 j     MainExit
14990	3:
14991		 sll   $7,$24,2         	 # Delay slot
14992		 addu  $7,$7,$30
14993		 lw    $7,0x00($7)
14994		 jr    $7
14995		 nop                    	 # Delay slot
14996
14997OP0_0079:				#:
14998		 addiu $23,$23,2
14999
15000		 lh    $8,0x00($23)
15001		 addiu $23,$23,2
15002		 lhu   $14,0x00($23)
15003		 lhu   $25,0x02($23)
15004		 sll   $14,$14,16
15005		 or    $14,$14,$25
15006		 addiu $23,$23,4
15007		 lw    $25,0x80($21)
15008		 sw    $15,m68k_ICount
15009		 sw    $8,0x44($29)
15010		 sw    $14,0x40($29)
15011		 or    $4,$0,$14
15012		 jalr  $25
15013		 sw    $23,0x4C($21)    	 # Delay slot
15014		 lw    $14,0x40($29)
15015		 lw    $8,0x44($29)
15016		 lw    $15,m68k_ICount
15017		 seh   $2,$2
15018		 or    $2,$2,$8
15019		 and   $16,$0,$0        	 # Clear Carry
15020		 and   $17,$0,$0        	 # Clear Overflow
15021		 slt   $19,$2,$0        	 # Set Sign
15022		 sltiu $18,$2,1         	 # Set Zero
15023		 lw    $25,0x8C($21)
15024		 sw    $15,m68k_ICount
15025		 or    $5,$0,$2
15026		 or    $4,$0,$14
15027		 jalr  $25
15028		 sw    $23,0x4C($21)    	 # Delay slot
15029		 lw    $15,m68k_ICount
15030		 addiu $15,$15,-24
15031		 bgez  $15,3f
15032		 lhu   $24,0x00($23)    	 # Delay slot
15033		 j     MainExit
15034	3:
15035		 sll   $7,$24,2         	 # Delay slot
15036		 addu  $7,$7,$30
15037		 lw    $7,0x00($7)
15038		 jr    $7
15039		 nop                    	 # Delay slot
15040
15041OP0_007c:				#:
15042		 lbu   $8,0x44($21)
15043		 andi  $8,$8,0x20       	 # Supervisor Mode ?
15044		 bne   $8,$0,9f
15045		 addiu $23,$23,2        	 # Delay slot
15046
15047		 addiu $23,$23,-2
15048		 jal   Exception
15049		 ori   $2,$0,8
15050
15051		 addiu $15,$15,-20
15052		 bgez  $15,3f
15053		 lhu   $24,0x00($23)    	 # Delay slot
15054		 j     MainExit
15055	3:
15056		 sll   $7,$24,2         	 # Delay slot
15057		 addu  $7,$7,$30
15058		 lw    $7,0x00($7)
15059		 jr    $7
15060		 nop                    	 # Delay slot
15061
15062	9:
15063		 lhu   $8,0x00($23)
15064		 addiu $23,$23,2
15065		 lbu   $2,0x44($21)
15066		 sll   $2,$2,4
15067		 or    $2,$2,$20
15068		 sll   $2,$2,1
15069		 or    $2,$2,$19
15070		 sll   $2,$2,1
15071		 or    $2,$2,$18
15072		 sll   $2,$2,1
15073		 or    $2,$2,$17
15074		 sll   $2,$2,1
15075		 or    $2,$2,$16
15076		 or    $2,$2,$8
15077		 andi  $25,$2,0x2000    	 # User Mode ?
15078		 bne   $25,$0,0f
15079		 or    $18,$0,$2       	 # Delay slot
15080		 lw    $16,0x3C($21)
15081		 lw    $17,0x68($21)
15082		 sw    $16,0x40($21)
15083		 sw    $17,0x3C($21)
15084	0:
15085		 srl   $18,$18,8
15086		 sb    $18,0x44($21)    	 # T, S & I
15087		 or    $20,$0,$2
15088		 or    $19,$0,$2
15089		 or    $18,$0,$2
15090		 or    $17,$0,$2
15091		 or    $16,$0,$2
15092		 andi  $20,$20,0x10
15093		 andi  $19,$19,0x08
15094		 andi  $18,$18,0x04
15095		 andi  $17,$17,0x02
15096		 andi  $16,$16,0x01
15097		 srl   $20,$20,4
15098		 srl   $19,$19,3
15099		 srl   $18,$18,2
15100		 srl   $17,$17,1
15101		 addiu $15,$15,-20
15102		 bgez  $15,3f
15103		 lbu   $7,0x50($21)     	 # Delay slot
15104		 j     MainExit
15105	3:
15106 # Check for Interrupt waiting
15107
15108		 andi  $7,$7,0x07       	 # Delay slot
15109		 beq   $7,$0,3f
15110		 nop                    	 # Delay slot
15111		 j     interrupt
15112	3:
15113		 lhu   $24,0x00($23)    	 # Delay slot
15114		 sll   $7,$24,2
15115		 addu  $7,$7,$30
15116		 lw    $7,0x00($7)
15117		 jr    $7
15118		 nop                    	 # Delay slot
15119
15120OP0_0080:				#:
15121		 addiu $23,$23,2
15122
15123		 andi  $24,$24,0x07
15124		 lhu   $8,0x00($23)
15125		 lhu   $25,0x02($23)
15126		 sll   $8,$8,16
15127		 or    $8,$8,$25
15128		 addiu $23,$23,4
15129		 sll   $24,$24,2
15130		 addu  $24,$24,$21
15131		 lw    $2,0x00($24)
15132		 or    $2,$2,$8
15133		 and   $16,$0,$0        	 # Clear Carry
15134		 and   $17,$0,$0        	 # Clear Overflow
15135		 slt   $19,$2,$0        	 # Set Sign
15136		 sltiu $18,$2,1         	 # Set Zero
15137		 sw    $2,0x00($24)
15138		 addiu $15,$15,-16
15139		 bgez  $15,3f
15140		 lhu   $24,0x00($23)    	 # Delay slot
15141		 j     MainExit
15142	3:
15143		 sll   $7,$24,2         	 # Delay slot
15144		 addu  $7,$7,$30
15145		 lw    $7,0x00($7)
15146		 jr    $7
15147		 nop                    	 # Delay slot
15148
15149OP0_0090:				#:
15150		 addiu $23,$23,2
15151
15152		 andi  $24,$24,0x07
15153		 lhu   $8,0x00($23)
15154		 lhu   $25,0x02($23)
15155		 sll   $8,$8,16
15156		 or    $8,$8,$25
15157		 addiu $23,$23,4
15158		 sll   $24,$24,2
15159		 addu  $24,$24,$21
15160		 lw    $14,0x20($24)
15161		 lw    $25,0x84($21)
15162		 sw    $15,m68k_ICount
15163		 sw    $8,0x44($29)
15164		 sw    $14,0x40($29)
15165		 or    $4,$0,$14
15166		 jalr  $25
15167		 sw    $23,0x4C($21)    	 # Delay slot
15168		 lw    $14,0x40($29)
15169		 lw    $8,0x44($29)
15170		 lw    $15,m68k_ICount
15171		 or    $2,$2,$8
15172		 and   $16,$0,$0        	 # Clear Carry
15173		 and   $17,$0,$0        	 # Clear Overflow
15174		 slt   $19,$2,$0        	 # Set Sign
15175		 sltiu $18,$2,1         	 # Set Zero
15176		 lw    $25,0x90($21)
15177		 sw    $15,m68k_ICount
15178		 or    $5,$0,$2
15179		 or    $4,$0,$14
15180		 jalr  $25
15181		 sw    $23,0x4C($21)    	 # Delay slot
15182		 lw    $15,m68k_ICount
15183		 addiu $15,$15,-28
15184		 bgez  $15,3f
15185		 lhu   $24,0x00($23)    	 # Delay slot
15186		 j     MainExit
15187	3:
15188		 sll   $7,$24,2         	 # Delay slot
15189		 addu  $7,$7,$30
15190		 lw    $7,0x00($7)
15191		 jr    $7
15192		 nop                    	 # Delay slot
15193
15194OP0_0098:				#:
15195		 addiu $23,$23,2
15196
15197		 andi  $24,$24,0x07
15198		 lhu   $8,0x00($23)
15199		 lhu   $25,0x02($23)
15200		 sll   $8,$8,16
15201		 or    $8,$8,$25
15202		 addiu $23,$23,4
15203		 sll   $24,$24,2
15204		 addu  $24,$24,$21
15205		 lw    $14,0x20($24)
15206		 addiu $25,$14,4
15207		 sw    $25,0x20($24)
15208		 lw    $25,0x84($21)
15209		 sw    $15,m68k_ICount
15210		 sw    $8,0x44($29)
15211		 sw    $14,0x40($29)
15212		 or    $4,$0,$14
15213		 jalr  $25
15214		 sw    $23,0x4C($21)    	 # Delay slot
15215		 lw    $14,0x40($29)
15216		 lw    $8,0x44($29)
15217		 lw    $15,m68k_ICount
15218		 or    $2,$2,$8
15219		 and   $16,$0,$0        	 # Clear Carry
15220		 and   $17,$0,$0        	 # Clear Overflow
15221		 slt   $19,$2,$0        	 # Set Sign
15222		 sltiu $18,$2,1         	 # Set Zero
15223		 lw    $25,0x90($21)
15224		 sw    $15,m68k_ICount
15225		 or    $5,$0,$2
15226		 or    $4,$0,$14
15227		 jalr  $25
15228		 sw    $23,0x4C($21)    	 # Delay slot
15229		 lw    $15,m68k_ICount
15230		 addiu $15,$15,-28
15231		 bgez  $15,3f
15232		 lhu   $24,0x00($23)    	 # Delay slot
15233		 j     MainExit
15234	3:
15235		 sll   $7,$24,2         	 # Delay slot
15236		 addu  $7,$7,$30
15237		 lw    $7,0x00($7)
15238		 jr    $7
15239		 nop                    	 # Delay slot
15240
15241OP0_00a0:				#:
15242		 addiu $23,$23,2
15243
15244		 andi  $24,$24,0x07
15245		 lhu   $8,0x00($23)
15246		 lhu   $25,0x02($23)
15247		 sll   $8,$8,16
15248		 or    $8,$8,$25
15249		 addiu $23,$23,4
15250		 sll   $24,$24,2
15251		 addu  $24,$24,$21
15252		 lw    $14,0x20($24)
15253		 addiu $14,$14,-4
15254		 sw    $14,0x20($24)
15255		 lw    $25,0x84($21)
15256		 sw    $15,m68k_ICount
15257		 sw    $8,0x44($29)
15258		 sw    $14,0x40($29)
15259		 or    $4,$0,$14
15260		 jalr  $25
15261		 sw    $23,0x4C($21)    	 # Delay slot
15262		 lw    $14,0x40($29)
15263		 lw    $8,0x44($29)
15264		 lw    $15,m68k_ICount
15265		 or    $2,$2,$8
15266		 and   $16,$0,$0        	 # Clear Carry
15267		 and   $17,$0,$0        	 # Clear Overflow
15268		 slt   $19,$2,$0        	 # Set Sign
15269		 sltiu $18,$2,1         	 # Set Zero
15270		 lw    $25,0x90($21)
15271		 sw    $15,m68k_ICount
15272		 or    $5,$0,$2
15273		 or    $4,$0,$14
15274		 jalr  $25
15275		 sw    $23,0x4C($21)    	 # Delay slot
15276		 lw    $15,m68k_ICount
15277		 addiu $15,$15,-30
15278		 bgez  $15,3f
15279		 lhu   $24,0x00($23)    	 # Delay slot
15280		 j     MainExit
15281	3:
15282		 sll   $7,$24,2         	 # Delay slot
15283		 addu  $7,$7,$30
15284		 lw    $7,0x00($7)
15285		 jr    $7
15286		 nop                    	 # Delay slot
15287
15288OP0_00a8:				#:
15289		 addiu $23,$23,2
15290
15291		 andi  $24,$24,0x07
15292		 lhu   $8,0x00($23)
15293		 lhu   $25,0x02($23)
15294		 sll   $8,$8,16
15295		 or    $8,$8,$25
15296		 addiu $23,$23,4
15297		 lh    $7,0x00($23)
15298		 sll   $24,$24,2
15299		 addu  $24,$24,$21
15300		 lw    $14,0x20($24)
15301		 addiu $23,$23,2
15302		 addu  $14,$14,$7
15303		 lw    $25,0x84($21)
15304		 sw    $15,m68k_ICount
15305		 sw    $8,0x44($29)
15306		 sw    $14,0x40($29)
15307		 or    $4,$0,$14
15308		 jalr  $25
15309		 sw    $23,0x4C($21)    	 # Delay slot
15310		 lw    $14,0x40($29)
15311		 lw    $8,0x44($29)
15312		 lw    $15,m68k_ICount
15313		 or    $2,$2,$8
15314		 and   $16,$0,$0        	 # Clear Carry
15315		 and   $17,$0,$0        	 # Clear Overflow
15316		 slt   $19,$2,$0        	 # Set Sign
15317		 sltiu $18,$2,1         	 # Set Zero
15318		 lw    $25,0x90($21)
15319		 sw    $15,m68k_ICount
15320		 or    $5,$0,$2
15321		 or    $4,$0,$14
15322		 jalr  $25
15323		 sw    $23,0x4C($21)    	 # Delay slot
15324		 lw    $15,m68k_ICount
15325		 addiu $15,$15,-32
15326		 bgez  $15,3f
15327		 lhu   $24,0x00($23)    	 # Delay slot
15328		 j     MainExit
15329	3:
15330		 sll   $7,$24,2         	 # Delay slot
15331		 addu  $7,$7,$30
15332		 lw    $7,0x00($7)
15333		 jr    $7
15334		 nop                    	 # Delay slot
15335
15336OP0_00b0:				#:
15337		 addiu $23,$23,2
15338
15339		 andi  $24,$24,0x07
15340		 lhu   $8,0x00($23)
15341		 lhu   $25,0x02($23)
15342		 sll   $8,$8,16
15343		 or    $8,$8,$25
15344		 addiu $23,$23,4
15345		 sll   $24,$24,2
15346		 addu  $24,$24,$21
15347		 lw    $14,0x20($24)
15348		 lhu   $7,0x00($23)
15349		 addiu $23,$23,2
15350		 seb   $6,$7
15351		 or    $25,$0,$7
15352		 srl   $7,$7,12
15353		 andi  $25,$25,0x0800
15354		 sll   $7,$7,2
15355		 addu  $7,$7,$21
15356		 bne   $25,$0,0f
15357		 lw    $25,0x00($7)      	 # Delay slot
15358		 seh   $25,$25
15359	0:
15360		 addu  $25,$14,$25
15361		 addu  $14,$25,$6
15362		 lw    $25,0x84($21)
15363		 sw    $15,m68k_ICount
15364		 sw    $8,0x44($29)
15365		 sw    $14,0x40($29)
15366		 or    $4,$0,$14
15367		 jalr  $25
15368		 sw    $23,0x4C($21)    	 # Delay slot
15369		 lw    $14,0x40($29)
15370		 lw    $8,0x44($29)
15371		 lw    $15,m68k_ICount
15372		 or    $2,$2,$8
15373		 and   $16,$0,$0        	 # Clear Carry
15374		 and   $17,$0,$0        	 # Clear Overflow
15375		 slt   $19,$2,$0        	 # Set Sign
15376		 sltiu $18,$2,1         	 # Set Zero
15377		 lw    $25,0x90($21)
15378		 sw    $15,m68k_ICount
15379		 or    $5,$0,$2
15380		 or    $4,$0,$14
15381		 jalr  $25
15382		 sw    $23,0x4C($21)    	 # Delay slot
15383		 lw    $15,m68k_ICount
15384		 addiu $15,$15,-34
15385		 bgez  $15,3f
15386		 lhu   $24,0x00($23)    	 # Delay slot
15387		 j     MainExit
15388	3:
15389		 sll   $7,$24,2         	 # Delay slot
15390		 addu  $7,$7,$30
15391		 lw    $7,0x00($7)
15392		 jr    $7
15393		 nop                    	 # Delay slot
15394
15395OP0_00b8:				#:
15396		 addiu $23,$23,2
15397
15398		 lhu   $8,0x00($23)
15399		 lhu   $25,0x02($23)
15400		 sll   $8,$8,16
15401		 or    $8,$8,$25
15402		 addiu $23,$23,4
15403		 lh    $14,0x00($23)
15404		 addiu $23,$23,2
15405		 lw    $25,0x84($21)
15406		 sw    $15,m68k_ICount
15407		 sw    $8,0x44($29)
15408		 sw    $14,0x40($29)
15409		 or    $4,$0,$14
15410		 jalr  $25
15411		 sw    $23,0x4C($21)    	 # Delay slot
15412		 lw    $14,0x40($29)
15413		 lw    $8,0x44($29)
15414		 lw    $15,m68k_ICount
15415		 or    $2,$2,$8
15416		 and   $16,$0,$0        	 # Clear Carry
15417		 and   $17,$0,$0        	 # Clear Overflow
15418		 slt   $19,$2,$0        	 # Set Sign
15419		 sltiu $18,$2,1         	 # Set Zero
15420		 lw    $25,0x90($21)
15421		 sw    $15,m68k_ICount
15422		 or    $5,$0,$2
15423		 or    $4,$0,$14
15424		 jalr  $25
15425		 sw    $23,0x4C($21)    	 # Delay slot
15426		 lw    $15,m68k_ICount
15427		 addiu $15,$15,-32
15428		 bgez  $15,3f
15429		 lhu   $24,0x00($23)    	 # Delay slot
15430		 j     MainExit
15431	3:
15432		 sll   $7,$24,2         	 # Delay slot
15433		 addu  $7,$7,$30
15434		 lw    $7,0x00($7)
15435		 jr    $7
15436		 nop                    	 # Delay slot
15437
15438OP0_00b9:				#:
15439		 addiu $23,$23,2
15440
15441		 lhu   $8,0x00($23)
15442		 lhu   $25,0x02($23)
15443		 sll   $8,$8,16
15444		 or    $8,$8,$25
15445		 addiu $23,$23,4
15446		 lhu   $14,0x00($23)
15447		 lhu   $25,0x02($23)
15448		 sll   $14,$14,16
15449		 or    $14,$14,$25
15450		 addiu $23,$23,4
15451		 lw    $25,0x84($21)
15452		 sw    $15,m68k_ICount
15453		 sw    $8,0x44($29)
15454		 sw    $14,0x40($29)
15455		 or    $4,$0,$14
15456		 jalr  $25
15457		 sw    $23,0x4C($21)    	 # Delay slot
15458		 lw    $14,0x40($29)
15459		 lw    $8,0x44($29)
15460		 lw    $15,m68k_ICount
15461		 or    $2,$2,$8
15462		 and   $16,$0,$0        	 # Clear Carry
15463		 and   $17,$0,$0        	 # Clear Overflow
15464		 slt   $19,$2,$0        	 # Set Sign
15465		 sltiu $18,$2,1         	 # Set Zero
15466		 lw    $25,0x90($21)
15467		 sw    $15,m68k_ICount
15468		 or    $5,$0,$2
15469		 or    $4,$0,$14
15470		 jalr  $25
15471		 sw    $23,0x4C($21)    	 # Delay slot
15472		 lw    $15,m68k_ICount
15473		 addiu $15,$15,-36
15474		 bgez  $15,3f
15475		 lhu   $24,0x00($23)    	 # Delay slot
15476		 j     MainExit
15477	3:
15478		 sll   $7,$24,2         	 # Delay slot
15479		 addu  $7,$7,$30
15480		 lw    $7,0x00($7)
15481		 jr    $7
15482		 nop                    	 # Delay slot
15483
15484OP0_0200:				#:
15485		 addiu $23,$23,2
15486
15487		 andi  $24,$24,0x07
15488		 lb    $8,0x00($23)
15489		 addiu $23,$23,2
15490		 sll   $24,$24,2
15491		 addu  $24,$24,$21
15492		 lb    $2,0x00($24)
15493		 and   $2,$2,$8
15494		 and   $16,$0,$0        	 # Clear Carry
15495		 and   $17,$0,$0        	 # Clear Overflow
15496		 slt   $19,$2,$0        	 # Set Sign
15497		 sltiu $18,$2,1         	 # Set Zero
15498		 sb    $2,0x00($24)
15499		 addiu $15,$15,-8
15500		 bgez  $15,3f
15501		 lhu   $24,0x00($23)    	 # Delay slot
15502		 j     MainExit
15503	3:
15504		 sll   $7,$24,2         	 # Delay slot
15505		 addu  $7,$7,$30
15506		 lw    $7,0x00($7)
15507		 jr    $7
15508		 nop                    	 # Delay slot
15509
15510OP0_0210:				#:
15511		 addiu $23,$23,2
15512
15513		 andi  $24,$24,0x07
15514		 lb    $8,0x00($23)
15515		 addiu $23,$23,2
15516		 sll   $24,$24,2
15517		 addu  $24,$24,$21
15518		 lw    $14,0x20($24)
15519		 lw    $25,0x7C($21)
15520		 sw    $15,m68k_ICount
15521		 sw    $8,0x44($29)
15522		 sw    $14,0x40($29)
15523		 or    $4,$0,$14
15524		 jalr  $25
15525		 sw    $23,0x4C($21)    	 # Delay slot
15526		 lw    $14,0x40($29)
15527		 lw    $8,0x44($29)
15528		 lw    $15,m68k_ICount
15529		 seb   $2,$2
15530		 and   $2,$2,$8
15531		 and   $16,$0,$0        	 # Clear Carry
15532		 and   $17,$0,$0        	 # Clear Overflow
15533		 slt   $19,$2,$0        	 # Set Sign
15534		 sltiu $18,$2,1         	 # Set Zero
15535		 lw    $25,0x88($21)
15536		 sw    $15,m68k_ICount
15537		 or    $5,$0,$2
15538		 or    $4,$0,$14
15539		 jalr  $25
15540		 sw    $23,0x4C($21)    	 # Delay slot
15541		 lw    $15,m68k_ICount
15542		 addiu $15,$15,-16
15543		 bgez  $15,3f
15544		 lhu   $24,0x00($23)    	 # Delay slot
15545		 j     MainExit
15546	3:
15547		 sll   $7,$24,2         	 # Delay slot
15548		 addu  $7,$7,$30
15549		 lw    $7,0x00($7)
15550		 jr    $7
15551		 nop                    	 # Delay slot
15552
15553OP0_0218:				#:
15554		 addiu $23,$23,2
15555
15556		 andi  $24,$24,0x07
15557		 lb    $8,0x00($23)
15558		 addiu $23,$23,2
15559		 sll   $24,$24,2
15560		 addu  $24,$24,$21
15561		 lw    $14,0x20($24)
15562		 addiu $25,$14,1
15563		 sw    $25,0x20($24)
15564		 lw    $25,0x7C($21)
15565		 sw    $15,m68k_ICount
15566		 sw    $8,0x44($29)
15567		 sw    $14,0x40($29)
15568		 or    $4,$0,$14
15569		 jalr  $25
15570		 sw    $23,0x4C($21)    	 # Delay slot
15571		 lw    $14,0x40($29)
15572		 lw    $8,0x44($29)
15573		 lw    $15,m68k_ICount
15574		 seb   $2,$2
15575		 and   $2,$2,$8
15576		 and   $16,$0,$0        	 # Clear Carry
15577		 and   $17,$0,$0        	 # Clear Overflow
15578		 slt   $19,$2,$0        	 # Set Sign
15579		 sltiu $18,$2,1         	 # Set Zero
15580		 lw    $25,0x88($21)
15581		 sw    $15,m68k_ICount
15582		 or    $5,$0,$2
15583		 or    $4,$0,$14
15584		 jalr  $25
15585		 sw    $23,0x4C($21)    	 # Delay slot
15586		 lw    $15,m68k_ICount
15587		 addiu $15,$15,-16
15588		 bgez  $15,3f
15589		 lhu   $24,0x00($23)    	 # Delay slot
15590		 j     MainExit
15591	3:
15592		 sll   $7,$24,2         	 # Delay slot
15593		 addu  $7,$7,$30
15594		 lw    $7,0x00($7)
15595		 jr    $7
15596		 nop                    	 # Delay slot
15597
15598OP0_021f:				#:
15599		 addiu $23,$23,2
15600
15601		 lb    $8,0x00($23)
15602		 addiu $23,$23,2
15603		 lw    $14,0x3C($21)    	 # Get A7
15604		 addiu $25,$14,2
15605		 sw    $25,0x3C($21)
15606		 lw    $25,0x7C($21)
15607		 sw    $15,m68k_ICount
15608		 sw    $8,0x44($29)
15609		 sw    $14,0x40($29)
15610		 or    $4,$0,$14
15611		 jalr  $25
15612		 sw    $23,0x4C($21)    	 # Delay slot
15613		 lw    $14,0x40($29)
15614		 lw    $8,0x44($29)
15615		 lw    $15,m68k_ICount
15616		 seb   $2,$2
15617		 and   $2,$2,$8
15618		 and   $16,$0,$0        	 # Clear Carry
15619		 and   $17,$0,$0        	 # Clear Overflow
15620		 slt   $19,$2,$0        	 # Set Sign
15621		 sltiu $18,$2,1         	 # Set Zero
15622		 lw    $25,0x88($21)
15623		 sw    $15,m68k_ICount
15624		 or    $5,$0,$2
15625		 or    $4,$0,$14
15626		 jalr  $25
15627		 sw    $23,0x4C($21)    	 # Delay slot
15628		 lw    $15,m68k_ICount
15629		 addiu $15,$15,-16
15630		 bgez  $15,3f
15631		 lhu   $24,0x00($23)    	 # Delay slot
15632		 j     MainExit
15633	3:
15634		 sll   $7,$24,2         	 # Delay slot
15635		 addu  $7,$7,$30
15636		 lw    $7,0x00($7)
15637		 jr    $7
15638		 nop                    	 # Delay slot
15639
15640OP0_0220:				#:
15641		 addiu $23,$23,2
15642
15643		 andi  $24,$24,0x07
15644		 lb    $8,0x00($23)
15645		 addiu $23,$23,2
15646		 sll   $24,$24,2
15647		 addu  $24,$24,$21
15648		 lw    $14,0x20($24)
15649		 addiu $14,$14,-1
15650		 sw    $14,0x20($24)
15651		 lw    $25,0x7C($21)
15652		 sw    $15,m68k_ICount
15653		 sw    $8,0x44($29)
15654		 sw    $14,0x40($29)
15655		 or    $4,$0,$14
15656		 jalr  $25
15657		 sw    $23,0x4C($21)    	 # Delay slot
15658		 lw    $14,0x40($29)
15659		 lw    $8,0x44($29)
15660		 lw    $15,m68k_ICount
15661		 seb   $2,$2
15662		 and   $2,$2,$8
15663		 and   $16,$0,$0        	 # Clear Carry
15664		 and   $17,$0,$0        	 # Clear Overflow
15665		 slt   $19,$2,$0        	 # Set Sign
15666		 sltiu $18,$2,1         	 # Set Zero
15667		 lw    $25,0x88($21)
15668		 sw    $15,m68k_ICount
15669		 or    $5,$0,$2
15670		 or    $4,$0,$14
15671		 jalr  $25
15672		 sw    $23,0x4C($21)    	 # Delay slot
15673		 lw    $15,m68k_ICount
15674		 addiu $15,$15,-18
15675		 bgez  $15,3f
15676		 lhu   $24,0x00($23)    	 # Delay slot
15677		 j     MainExit
15678	3:
15679		 sll   $7,$24,2         	 # Delay slot
15680		 addu  $7,$7,$30
15681		 lw    $7,0x00($7)
15682		 jr    $7
15683		 nop                    	 # Delay slot
15684
15685OP0_0227:				#:
15686		 addiu $23,$23,2
15687
15688		 lb    $8,0x00($23)
15689		 addiu $23,$23,2
15690		 lw    $14,0x3C($21)    	 # Get A7
15691		 addiu $14,$14,-2
15692		 sw    $14,0x3C($21)
15693		 lw    $25,0x7C($21)
15694		 sw    $15,m68k_ICount
15695		 sw    $8,0x44($29)
15696		 sw    $14,0x40($29)
15697		 or    $4,$0,$14
15698		 jalr  $25
15699		 sw    $23,0x4C($21)    	 # Delay slot
15700		 lw    $14,0x40($29)
15701		 lw    $8,0x44($29)
15702		 lw    $15,m68k_ICount
15703		 seb   $2,$2
15704		 and   $2,$2,$8
15705		 and   $16,$0,$0        	 # Clear Carry
15706		 and   $17,$0,$0        	 # Clear Overflow
15707		 slt   $19,$2,$0        	 # Set Sign
15708		 sltiu $18,$2,1         	 # Set Zero
15709		 lw    $25,0x88($21)
15710		 sw    $15,m68k_ICount
15711		 or    $5,$0,$2
15712		 or    $4,$0,$14
15713		 jalr  $25
15714		 sw    $23,0x4C($21)    	 # Delay slot
15715		 lw    $15,m68k_ICount
15716		 addiu $15,$15,-18
15717		 bgez  $15,3f
15718		 lhu   $24,0x00($23)    	 # Delay slot
15719		 j     MainExit
15720	3:
15721		 sll   $7,$24,2         	 # Delay slot
15722		 addu  $7,$7,$30
15723		 lw    $7,0x00($7)
15724		 jr    $7
15725		 nop                    	 # Delay slot
15726
15727OP0_0228:				#:
15728		 addiu $23,$23,2
15729
15730		 andi  $24,$24,0x07
15731		 lb    $8,0x00($23)
15732		 addiu $23,$23,2
15733		 lh    $7,0x00($23)
15734		 sll   $24,$24,2
15735		 addu  $24,$24,$21
15736		 lw    $14,0x20($24)
15737		 addiu $23,$23,2
15738		 addu  $14,$14,$7
15739		 lw    $25,0x7C($21)
15740		 sw    $15,m68k_ICount
15741		 sw    $8,0x44($29)
15742		 sw    $14,0x40($29)
15743		 or    $4,$0,$14
15744		 jalr  $25
15745		 sw    $23,0x4C($21)    	 # Delay slot
15746		 lw    $14,0x40($29)
15747		 lw    $8,0x44($29)
15748		 lw    $15,m68k_ICount
15749		 seb   $2,$2
15750		 and   $2,$2,$8
15751		 and   $16,$0,$0        	 # Clear Carry
15752		 and   $17,$0,$0        	 # Clear Overflow
15753		 slt   $19,$2,$0        	 # Set Sign
15754		 sltiu $18,$2,1         	 # Set Zero
15755		 lw    $25,0x88($21)
15756		 sw    $15,m68k_ICount
15757		 or    $5,$0,$2
15758		 or    $4,$0,$14
15759		 jalr  $25
15760		 sw    $23,0x4C($21)    	 # Delay slot
15761		 lw    $15,m68k_ICount
15762		 addiu $15,$15,-20
15763		 bgez  $15,3f
15764		 lhu   $24,0x00($23)    	 # Delay slot
15765		 j     MainExit
15766	3:
15767		 sll   $7,$24,2         	 # Delay slot
15768		 addu  $7,$7,$30
15769		 lw    $7,0x00($7)
15770		 jr    $7
15771		 nop                    	 # Delay slot
15772
15773OP0_0230:				#:
15774		 addiu $23,$23,2
15775
15776		 andi  $24,$24,0x07
15777		 lb    $8,0x00($23)
15778		 addiu $23,$23,2
15779		 sll   $24,$24,2
15780		 addu  $24,$24,$21
15781		 lw    $14,0x20($24)
15782		 lhu   $7,0x00($23)
15783		 addiu $23,$23,2
15784		 seb   $6,$7
15785		 or    $25,$0,$7
15786		 srl   $7,$7,12
15787		 andi  $25,$25,0x0800
15788		 sll   $7,$7,2
15789		 addu  $7,$7,$21
15790		 bne   $25,$0,0f
15791		 lw    $25,0x00($7)      	 # Delay slot
15792		 seh   $25,$25
15793	0:
15794		 addu  $25,$14,$25
15795		 addu  $14,$25,$6
15796		 lw    $25,0x7C($21)
15797		 sw    $15,m68k_ICount
15798		 sw    $8,0x44($29)
15799		 sw    $14,0x40($29)
15800		 or    $4,$0,$14
15801		 jalr  $25
15802		 sw    $23,0x4C($21)    	 # Delay slot
15803		 lw    $14,0x40($29)
15804		 lw    $8,0x44($29)
15805		 lw    $15,m68k_ICount
15806		 seb   $2,$2
15807		 and   $2,$2,$8
15808		 and   $16,$0,$0        	 # Clear Carry
15809		 and   $17,$0,$0        	 # Clear Overflow
15810		 slt   $19,$2,$0        	 # Set Sign
15811		 sltiu $18,$2,1         	 # Set Zero
15812		 lw    $25,0x88($21)
15813		 sw    $15,m68k_ICount
15814		 or    $5,$0,$2
15815		 or    $4,$0,$14
15816		 jalr  $25
15817		 sw    $23,0x4C($21)    	 # Delay slot
15818		 lw    $15,m68k_ICount
15819		 addiu $15,$15,-22
15820		 bgez  $15,3f
15821		 lhu   $24,0x00($23)    	 # Delay slot
15822		 j     MainExit
15823	3:
15824		 sll   $7,$24,2         	 # Delay slot
15825		 addu  $7,$7,$30
15826		 lw    $7,0x00($7)
15827		 jr    $7
15828		 nop                    	 # Delay slot
15829
15830OP0_0238:				#:
15831		 addiu $23,$23,2
15832
15833		 lb    $8,0x00($23)
15834		 addiu $23,$23,2
15835		 lh    $14,0x00($23)
15836		 addiu $23,$23,2
15837		 lw    $25,0x7C($21)
15838		 sw    $15,m68k_ICount
15839		 sw    $8,0x44($29)
15840		 sw    $14,0x40($29)
15841		 or    $4,$0,$14
15842		 jalr  $25
15843		 sw    $23,0x4C($21)    	 # Delay slot
15844		 lw    $14,0x40($29)
15845		 lw    $8,0x44($29)
15846		 lw    $15,m68k_ICount
15847		 seb   $2,$2
15848		 and   $2,$2,$8
15849		 and   $16,$0,$0        	 # Clear Carry
15850		 and   $17,$0,$0        	 # Clear Overflow
15851		 slt   $19,$2,$0        	 # Set Sign
15852		 sltiu $18,$2,1         	 # Set Zero
15853		 lw    $25,0x88($21)
15854		 sw    $15,m68k_ICount
15855		 or    $5,$0,$2
15856		 or    $4,$0,$14
15857		 jalr  $25
15858		 sw    $23,0x4C($21)    	 # Delay slot
15859		 lw    $15,m68k_ICount
15860		 addiu $15,$15,-20
15861		 bgez  $15,3f
15862		 lhu   $24,0x00($23)    	 # Delay slot
15863		 j     MainExit
15864	3:
15865		 sll   $7,$24,2         	 # Delay slot
15866		 addu  $7,$7,$30
15867		 lw    $7,0x00($7)
15868		 jr    $7
15869		 nop                    	 # Delay slot
15870
15871OP0_0239:				#:
15872		 addiu $23,$23,2
15873
15874		 lb    $8,0x00($23)
15875		 addiu $23,$23,2
15876		 lhu   $14,0x00($23)
15877		 lhu   $25,0x02($23)
15878		 sll   $14,$14,16
15879		 or    $14,$14,$25
15880		 addiu $23,$23,4
15881		 lw    $25,0x7C($21)
15882		 sw    $15,m68k_ICount
15883		 sw    $8,0x44($29)
15884		 sw    $14,0x40($29)
15885		 or    $4,$0,$14
15886		 jalr  $25
15887		 sw    $23,0x4C($21)    	 # Delay slot
15888		 lw    $14,0x40($29)
15889		 lw    $8,0x44($29)
15890		 lw    $15,m68k_ICount
15891		 seb   $2,$2
15892		 and   $2,$2,$8
15893		 and   $16,$0,$0        	 # Clear Carry
15894		 and   $17,$0,$0        	 # Clear Overflow
15895		 slt   $19,$2,$0        	 # Set Sign
15896		 sltiu $18,$2,1         	 # Set Zero
15897		 lw    $25,0x88($21)
15898		 sw    $15,m68k_ICount
15899		 or    $5,$0,$2
15900		 or    $4,$0,$14
15901		 jalr  $25
15902		 sw    $23,0x4C($21)    	 # Delay slot
15903		 lw    $15,m68k_ICount
15904		 addiu $15,$15,-24
15905		 bgez  $15,3f
15906		 lhu   $24,0x00($23)    	 # Delay slot
15907		 j     MainExit
15908	3:
15909		 sll   $7,$24,2         	 # Delay slot
15910		 addu  $7,$7,$30
15911		 lw    $7,0x00($7)
15912		 jr    $7
15913		 nop                    	 # Delay slot
15914
15915OP0_023c:				#:
15916		 addiu $23,$23,2
15917
15918		 lbu   $8,0x00($23)
15919		 addiu $23,$23,2
15920		 or    $2,$0,$20
15921		 sll   $2,$2,1
15922		 or    $2,$2,$19
15923		 sll   $2,$2,1
15924		 or    $2,$2,$18
15925		 sll   $2,$2,1
15926		 or    $2,$2,$17
15927		 sll   $2,$2,1
15928		 or    $2,$2,$16
15929		 and   $2,$2,$8
15930		 or    $20,$0,$2
15931		 or    $19,$0,$2
15932		 or    $18,$0,$2
15933		 or    $17,$0,$2
15934		 or    $16,$0,$2
15935		 andi  $20,$20,0x10
15936		 andi  $19,$19,0x08
15937		 andi  $18,$18,0x04
15938		 andi  $17,$17,0x02
15939		 andi  $16,$16,0x01
15940		 srl   $20,$20,4
15941		 srl   $19,$19,3
15942		 srl   $18,$18,2
15943		 srl   $17,$17,1
15944		 addiu $15,$15,-20
15945		 bgez  $15,3f
15946		 lhu   $24,0x00($23)    	 # Delay slot
15947		 j     MainExit
15948	3:
15949		 sll   $7,$24,2         	 # Delay slot
15950		 addu  $7,$7,$30
15951		 lw    $7,0x00($7)
15952		 jr    $7
15953		 nop                    	 # Delay slot
15954
15955OP0_0240:				#:
15956		 addiu $23,$23,2
15957
15958		 andi  $24,$24,0x07
15959		 lh    $8,0x00($23)
15960		 addiu $23,$23,2
15961		 sll   $24,$24,2
15962		 addu  $24,$24,$21
15963		 lh    $2,0x00($24)
15964		 and   $2,$2,$8
15965		 and   $16,$0,$0        	 # Clear Carry
15966		 and   $17,$0,$0        	 # Clear Overflow
15967		 slt   $19,$2,$0        	 # Set Sign
15968		 sltiu $18,$2,1         	 # Set Zero
15969		 sh    $2,0x00($24)
15970		 addiu $15,$15,-8
15971		 bgez  $15,3f
15972		 lhu   $24,0x00($23)    	 # Delay slot
15973		 j     MainExit
15974	3:
15975		 sll   $7,$24,2         	 # Delay slot
15976		 addu  $7,$7,$30
15977		 lw    $7,0x00($7)
15978		 jr    $7
15979		 nop                    	 # Delay slot
15980
15981OP0_0250:				#:
15982		 addiu $23,$23,2
15983
15984		 andi  $24,$24,0x07
15985		 lh    $8,0x00($23)
15986		 addiu $23,$23,2
15987		 sll   $24,$24,2
15988		 addu  $24,$24,$21
15989		 lw    $14,0x20($24)
15990		 lw    $25,0x80($21)
15991		 sw    $15,m68k_ICount
15992		 sw    $8,0x44($29)
15993		 sw    $14,0x40($29)
15994		 or    $4,$0,$14
15995		 jalr  $25
15996		 sw    $23,0x4C($21)    	 # Delay slot
15997		 lw    $14,0x40($29)
15998		 lw    $8,0x44($29)
15999		 lw    $15,m68k_ICount
16000		 seh   $2,$2
16001		 and   $2,$2,$8
16002		 and   $16,$0,$0        	 # Clear Carry
16003		 and   $17,$0,$0        	 # Clear Overflow
16004		 slt   $19,$2,$0        	 # Set Sign
16005		 sltiu $18,$2,1         	 # Set Zero
16006		 lw    $25,0x8C($21)
16007		 sw    $15,m68k_ICount
16008		 or    $5,$0,$2
16009		 or    $4,$0,$14
16010		 jalr  $25
16011		 sw    $23,0x4C($21)    	 # Delay slot
16012		 lw    $15,m68k_ICount
16013		 addiu $15,$15,-16
16014		 bgez  $15,3f
16015		 lhu   $24,0x00($23)    	 # Delay slot
16016		 j     MainExit
16017	3:
16018		 sll   $7,$24,2         	 # Delay slot
16019		 addu  $7,$7,$30
16020		 lw    $7,0x00($7)
16021		 jr    $7
16022		 nop                    	 # Delay slot
16023
16024OP0_0258:				#:
16025		 addiu $23,$23,2
16026
16027		 andi  $24,$24,0x07
16028		 lh    $8,0x00($23)
16029		 addiu $23,$23,2
16030		 sll   $24,$24,2
16031		 addu  $24,$24,$21
16032		 lw    $14,0x20($24)
16033		 addiu $25,$14,2
16034		 sw    $25,0x20($24)
16035		 lw    $25,0x80($21)
16036		 sw    $15,m68k_ICount
16037		 sw    $8,0x44($29)
16038		 sw    $14,0x40($29)
16039		 or    $4,$0,$14
16040		 jalr  $25
16041		 sw    $23,0x4C($21)    	 # Delay slot
16042		 lw    $14,0x40($29)
16043		 lw    $8,0x44($29)
16044		 lw    $15,m68k_ICount
16045		 seh   $2,$2
16046		 and   $2,$2,$8
16047		 and   $16,$0,$0        	 # Clear Carry
16048		 and   $17,$0,$0        	 # Clear Overflow
16049		 slt   $19,$2,$0        	 # Set Sign
16050		 sltiu $18,$2,1         	 # Set Zero
16051		 lw    $25,0x8C($21)
16052		 sw    $15,m68k_ICount
16053		 or    $5,$0,$2
16054		 or    $4,$0,$14
16055		 jalr  $25
16056		 sw    $23,0x4C($21)    	 # Delay slot
16057		 lw    $15,m68k_ICount
16058		 addiu $15,$15,-16
16059		 bgez  $15,3f
16060		 lhu   $24,0x00($23)    	 # Delay slot
16061		 j     MainExit
16062	3:
16063		 sll   $7,$24,2         	 # Delay slot
16064		 addu  $7,$7,$30
16065		 lw    $7,0x00($7)
16066		 jr    $7
16067		 nop                    	 # Delay slot
16068
16069OP0_0260:				#:
16070		 addiu $23,$23,2
16071
16072		 andi  $24,$24,0x07
16073		 lh    $8,0x00($23)
16074		 addiu $23,$23,2
16075		 sll   $24,$24,2
16076		 addu  $24,$24,$21
16077		 lw    $14,0x20($24)
16078		 addiu $14,$14,-2
16079		 sw    $14,0x20($24)
16080		 lw    $25,0x80($21)
16081		 sw    $15,m68k_ICount
16082		 sw    $8,0x44($29)
16083		 sw    $14,0x40($29)
16084		 or    $4,$0,$14
16085		 jalr  $25
16086		 sw    $23,0x4C($21)    	 # Delay slot
16087		 lw    $14,0x40($29)
16088		 lw    $8,0x44($29)
16089		 lw    $15,m68k_ICount
16090		 seh   $2,$2
16091		 and   $2,$2,$8
16092		 and   $16,$0,$0        	 # Clear Carry
16093		 and   $17,$0,$0        	 # Clear Overflow
16094		 slt   $19,$2,$0        	 # Set Sign
16095		 sltiu $18,$2,1         	 # Set Zero
16096		 lw    $25,0x8C($21)
16097		 sw    $15,m68k_ICount
16098		 or    $5,$0,$2
16099		 or    $4,$0,$14
16100		 jalr  $25
16101		 sw    $23,0x4C($21)    	 # Delay slot
16102		 lw    $15,m68k_ICount
16103		 addiu $15,$15,-18
16104		 bgez  $15,3f
16105		 lhu   $24,0x00($23)    	 # Delay slot
16106		 j     MainExit
16107	3:
16108		 sll   $7,$24,2         	 # Delay slot
16109		 addu  $7,$7,$30
16110		 lw    $7,0x00($7)
16111		 jr    $7
16112		 nop                    	 # Delay slot
16113
16114OP0_0268:				#:
16115		 addiu $23,$23,2
16116
16117		 andi  $24,$24,0x07
16118		 lh    $8,0x00($23)
16119		 addiu $23,$23,2
16120		 lh    $7,0x00($23)
16121		 sll   $24,$24,2
16122		 addu  $24,$24,$21
16123		 lw    $14,0x20($24)
16124		 addiu $23,$23,2
16125		 addu  $14,$14,$7
16126		 lw    $25,0x80($21)
16127		 sw    $15,m68k_ICount
16128		 sw    $8,0x44($29)
16129		 sw    $14,0x40($29)
16130		 or    $4,$0,$14
16131		 jalr  $25
16132		 sw    $23,0x4C($21)    	 # Delay slot
16133		 lw    $14,0x40($29)
16134		 lw    $8,0x44($29)
16135		 lw    $15,m68k_ICount
16136		 seh   $2,$2
16137		 and   $2,$2,$8
16138		 and   $16,$0,$0        	 # Clear Carry
16139		 and   $17,$0,$0        	 # Clear Overflow
16140		 slt   $19,$2,$0        	 # Set Sign
16141		 sltiu $18,$2,1         	 # Set Zero
16142		 lw    $25,0x8C($21)
16143		 sw    $15,m68k_ICount
16144		 or    $5,$0,$2
16145		 or    $4,$0,$14
16146		 jalr  $25
16147		 sw    $23,0x4C($21)    	 # Delay slot
16148		 lw    $15,m68k_ICount
16149		 addiu $15,$15,-20
16150		 bgez  $15,3f
16151		 lhu   $24,0x00($23)    	 # Delay slot
16152		 j     MainExit
16153	3:
16154		 sll   $7,$24,2         	 # Delay slot
16155		 addu  $7,$7,$30
16156		 lw    $7,0x00($7)
16157		 jr    $7
16158		 nop                    	 # Delay slot
16159
16160OP0_0270:				#:
16161		 addiu $23,$23,2
16162
16163		 andi  $24,$24,0x07
16164		 lh    $8,0x00($23)
16165		 addiu $23,$23,2
16166		 sll   $24,$24,2
16167		 addu  $24,$24,$21
16168		 lw    $14,0x20($24)
16169		 lhu   $7,0x00($23)
16170		 addiu $23,$23,2
16171		 seb   $6,$7
16172		 or    $25,$0,$7
16173		 srl   $7,$7,12
16174		 andi  $25,$25,0x0800
16175		 sll   $7,$7,2
16176		 addu  $7,$7,$21
16177		 bne   $25,$0,0f
16178		 lw    $25,0x00($7)      	 # Delay slot
16179		 seh   $25,$25
16180	0:
16181		 addu  $25,$14,$25
16182		 addu  $14,$25,$6
16183		 lw    $25,0x80($21)
16184		 sw    $15,m68k_ICount
16185		 sw    $8,0x44($29)
16186		 sw    $14,0x40($29)
16187		 or    $4,$0,$14
16188		 jalr  $25
16189		 sw    $23,0x4C($21)    	 # Delay slot
16190		 lw    $14,0x40($29)
16191		 lw    $8,0x44($29)
16192		 lw    $15,m68k_ICount
16193		 seh   $2,$2
16194		 and   $2,$2,$8
16195		 and   $16,$0,$0        	 # Clear Carry
16196		 and   $17,$0,$0        	 # Clear Overflow
16197		 slt   $19,$2,$0        	 # Set Sign
16198		 sltiu $18,$2,1         	 # Set Zero
16199		 lw    $25,0x8C($21)
16200		 sw    $15,m68k_ICount
16201		 or    $5,$0,$2
16202		 or    $4,$0,$14
16203		 jalr  $25
16204		 sw    $23,0x4C($21)    	 # Delay slot
16205		 lw    $15,m68k_ICount
16206		 addiu $15,$15,-22
16207		 bgez  $15,3f
16208		 lhu   $24,0x00($23)    	 # Delay slot
16209		 j     MainExit
16210	3:
16211		 sll   $7,$24,2         	 # Delay slot
16212		 addu  $7,$7,$30
16213		 lw    $7,0x00($7)
16214		 jr    $7
16215		 nop                    	 # Delay slot
16216
16217OP0_0278:				#:
16218		 addiu $23,$23,2
16219
16220		 lh    $8,0x00($23)
16221		 addiu $23,$23,2
16222		 lh    $14,0x00($23)
16223		 addiu $23,$23,2
16224		 lw    $25,0x80($21)
16225		 sw    $15,m68k_ICount
16226		 sw    $8,0x44($29)
16227		 sw    $14,0x40($29)
16228		 or    $4,$0,$14
16229		 jalr  $25
16230		 sw    $23,0x4C($21)    	 # Delay slot
16231		 lw    $14,0x40($29)
16232		 lw    $8,0x44($29)
16233		 lw    $15,m68k_ICount
16234		 seh   $2,$2
16235		 and   $2,$2,$8
16236		 and   $16,$0,$0        	 # Clear Carry
16237		 and   $17,$0,$0        	 # Clear Overflow
16238		 slt   $19,$2,$0        	 # Set Sign
16239		 sltiu $18,$2,1         	 # Set Zero
16240		 lw    $25,0x8C($21)
16241		 sw    $15,m68k_ICount
16242		 or    $5,$0,$2
16243		 or    $4,$0,$14
16244		 jalr  $25
16245		 sw    $23,0x4C($21)    	 # Delay slot
16246		 lw    $15,m68k_ICount
16247		 addiu $15,$15,-20
16248		 bgez  $15,3f
16249		 lhu   $24,0x00($23)    	 # Delay slot
16250		 j     MainExit
16251	3:
16252		 sll   $7,$24,2         	 # Delay slot
16253		 addu  $7,$7,$30
16254		 lw    $7,0x00($7)
16255		 jr    $7
16256		 nop                    	 # Delay slot
16257
16258OP0_0279:				#:
16259		 addiu $23,$23,2
16260
16261		 lh    $8,0x00($23)
16262		 addiu $23,$23,2
16263		 lhu   $14,0x00($23)
16264		 lhu   $25,0x02($23)
16265		 sll   $14,$14,16
16266		 or    $14,$14,$25
16267		 addiu $23,$23,4
16268		 lw    $25,0x80($21)
16269		 sw    $15,m68k_ICount
16270		 sw    $8,0x44($29)
16271		 sw    $14,0x40($29)
16272		 or    $4,$0,$14
16273		 jalr  $25
16274		 sw    $23,0x4C($21)    	 # Delay slot
16275		 lw    $14,0x40($29)
16276		 lw    $8,0x44($29)
16277		 lw    $15,m68k_ICount
16278		 seh   $2,$2
16279		 and   $2,$2,$8
16280		 and   $16,$0,$0        	 # Clear Carry
16281		 and   $17,$0,$0        	 # Clear Overflow
16282		 slt   $19,$2,$0        	 # Set Sign
16283		 sltiu $18,$2,1         	 # Set Zero
16284		 lw    $25,0x8C($21)
16285		 sw    $15,m68k_ICount
16286		 or    $5,$0,$2
16287		 or    $4,$0,$14
16288		 jalr  $25
16289		 sw    $23,0x4C($21)    	 # Delay slot
16290		 lw    $15,m68k_ICount
16291		 addiu $15,$15,-24
16292		 bgez  $15,3f
16293		 lhu   $24,0x00($23)    	 # Delay slot
16294		 j     MainExit
16295	3:
16296		 sll   $7,$24,2         	 # Delay slot
16297		 addu  $7,$7,$30
16298		 lw    $7,0x00($7)
16299		 jr    $7
16300		 nop                    	 # Delay slot
16301
16302OP0_027c:				#:
16303		 lbu   $8,0x44($21)
16304		 andi  $8,$8,0x20       	 # Supervisor Mode ?
16305		 bne   $8,$0,9f
16306		 addiu $23,$23,2        	 # Delay slot
16307
16308		 addiu $23,$23,-2
16309		 jal   Exception
16310		 ori   $2,$0,8
16311
16312		 addiu $15,$15,-20
16313		 bgez  $15,3f
16314		 lhu   $24,0x00($23)    	 # Delay slot
16315		 j     MainExit
16316	3:
16317		 sll   $7,$24,2         	 # Delay slot
16318		 addu  $7,$7,$30
16319		 lw    $7,0x00($7)
16320		 jr    $7
16321		 nop                    	 # Delay slot
16322
16323	9:
16324		 lhu   $8,0x00($23)
16325		 addiu $23,$23,2
16326		 lbu   $2,0x44($21)
16327		 sll   $2,$2,4
16328		 or    $2,$2,$20
16329		 sll   $2,$2,1
16330		 or    $2,$2,$19
16331		 sll   $2,$2,1
16332		 or    $2,$2,$18
16333		 sll   $2,$2,1
16334		 or    $2,$2,$17
16335		 sll   $2,$2,1
16336		 or    $2,$2,$16
16337		 and   $2,$2,$8
16338		 andi  $25,$2,0x2000    	 # User Mode ?
16339		 bne   $25,$0,0f
16340		 or    $18,$0,$2       	 # Delay slot
16341		 lw    $16,0x3C($21)
16342		 lw    $17,0x68($21)
16343		 sw    $16,0x40($21)
16344		 sw    $17,0x3C($21)
16345	0:
16346		 srl   $18,$18,8
16347		 sb    $18,0x44($21)    	 # T, S & I
16348		 or    $20,$0,$2
16349		 or    $19,$0,$2
16350		 or    $18,$0,$2
16351		 or    $17,$0,$2
16352		 or    $16,$0,$2
16353		 andi  $20,$20,0x10
16354		 andi  $19,$19,0x08
16355		 andi  $18,$18,0x04
16356		 andi  $17,$17,0x02
16357		 andi  $16,$16,0x01
16358		 srl   $20,$20,4
16359		 srl   $19,$19,3
16360		 srl   $18,$18,2
16361		 srl   $17,$17,1
16362		 addiu $15,$15,-20
16363		 bgez  $15,3f
16364		 lbu   $7,0x50($21)     	 # Delay slot
16365		 j     MainExit
16366	3:
16367 # Check for Interrupt waiting
16368
16369		 andi  $7,$7,0x07       	 # Delay slot
16370		 beq   $7,$0,3f
16371		 nop                    	 # Delay slot
16372		 j     interrupt
16373	3:
16374		 lhu   $24,0x00($23)    	 # Delay slot
16375		 sll   $7,$24,2
16376		 addu  $7,$7,$30
16377		 lw    $7,0x00($7)
16378		 jr    $7
16379		 nop                    	 # Delay slot
16380
16381OP0_0280:				#:
16382		 addiu $23,$23,2
16383
16384		 andi  $24,$24,0x07
16385		 lhu   $8,0x00($23)
16386		 lhu   $25,0x02($23)
16387		 sll   $8,$8,16
16388		 or    $8,$8,$25
16389		 addiu $23,$23,4
16390		 sll   $24,$24,2
16391		 addu  $24,$24,$21
16392		 lw    $2,0x00($24)
16393		 and   $2,$2,$8
16394		 and   $16,$0,$0        	 # Clear Carry
16395		 and   $17,$0,$0        	 # Clear Overflow
16396		 slt   $19,$2,$0        	 # Set Sign
16397		 sltiu $18,$2,1         	 # Set Zero
16398		 sw    $2,0x00($24)
16399		 addiu $15,$15,-14
16400		 bgez  $15,3f
16401		 lhu   $24,0x00($23)    	 # Delay slot
16402		 j     MainExit
16403	3:
16404		 sll   $7,$24,2         	 # Delay slot
16405		 addu  $7,$7,$30
16406		 lw    $7,0x00($7)
16407		 jr    $7
16408		 nop                    	 # Delay slot
16409
16410OP0_0290:				#:
16411		 addiu $23,$23,2
16412
16413		 andi  $24,$24,0x07
16414		 lhu   $8,0x00($23)
16415		 lhu   $25,0x02($23)
16416		 sll   $8,$8,16
16417		 or    $8,$8,$25
16418		 addiu $23,$23,4
16419		 sll   $24,$24,2
16420		 addu  $24,$24,$21
16421		 lw    $14,0x20($24)
16422		 lw    $25,0x84($21)
16423		 sw    $15,m68k_ICount
16424		 sw    $8,0x44($29)
16425		 sw    $14,0x40($29)
16426		 or    $4,$0,$14
16427		 jalr  $25
16428		 sw    $23,0x4C($21)    	 # Delay slot
16429		 lw    $14,0x40($29)
16430		 lw    $8,0x44($29)
16431		 lw    $15,m68k_ICount
16432		 and   $2,$2,$8
16433		 and   $16,$0,$0        	 # Clear Carry
16434		 and   $17,$0,$0        	 # Clear Overflow
16435		 slt   $19,$2,$0        	 # Set Sign
16436		 sltiu $18,$2,1         	 # Set Zero
16437		 lw    $25,0x90($21)
16438		 sw    $15,m68k_ICount
16439		 or    $5,$0,$2
16440		 or    $4,$0,$14
16441		 jalr  $25
16442		 sw    $23,0x4C($21)    	 # Delay slot
16443		 lw    $15,m68k_ICount
16444		 addiu $15,$15,-28
16445		 bgez  $15,3f
16446		 lhu   $24,0x00($23)    	 # Delay slot
16447		 j     MainExit
16448	3:
16449		 sll   $7,$24,2         	 # Delay slot
16450		 addu  $7,$7,$30
16451		 lw    $7,0x00($7)
16452		 jr    $7
16453		 nop                    	 # Delay slot
16454
16455OP0_0298:				#:
16456		 addiu $23,$23,2
16457
16458		 andi  $24,$24,0x07
16459		 lhu   $8,0x00($23)
16460		 lhu   $25,0x02($23)
16461		 sll   $8,$8,16
16462		 or    $8,$8,$25
16463		 addiu $23,$23,4
16464		 sll   $24,$24,2
16465		 addu  $24,$24,$21
16466		 lw    $14,0x20($24)
16467		 addiu $25,$14,4
16468		 sw    $25,0x20($24)
16469		 lw    $25,0x84($21)
16470		 sw    $15,m68k_ICount
16471		 sw    $8,0x44($29)
16472		 sw    $14,0x40($29)
16473		 or    $4,$0,$14
16474		 jalr  $25
16475		 sw    $23,0x4C($21)    	 # Delay slot
16476		 lw    $14,0x40($29)
16477		 lw    $8,0x44($29)
16478		 lw    $15,m68k_ICount
16479		 and   $2,$2,$8
16480		 and   $16,$0,$0        	 # Clear Carry
16481		 and   $17,$0,$0        	 # Clear Overflow
16482		 slt   $19,$2,$0        	 # Set Sign
16483		 sltiu $18,$2,1         	 # Set Zero
16484		 lw    $25,0x90($21)
16485		 sw    $15,m68k_ICount
16486		 or    $5,$0,$2
16487		 or    $4,$0,$14
16488		 jalr  $25
16489		 sw    $23,0x4C($21)    	 # Delay slot
16490		 lw    $15,m68k_ICount
16491		 addiu $15,$15,-28
16492		 bgez  $15,3f
16493		 lhu   $24,0x00($23)    	 # Delay slot
16494		 j     MainExit
16495	3:
16496		 sll   $7,$24,2         	 # Delay slot
16497		 addu  $7,$7,$30
16498		 lw    $7,0x00($7)
16499		 jr    $7
16500		 nop                    	 # Delay slot
16501
16502OP0_02a0:				#:
16503		 addiu $23,$23,2
16504
16505		 andi  $24,$24,0x07
16506		 lhu   $8,0x00($23)
16507		 lhu   $25,0x02($23)
16508		 sll   $8,$8,16
16509		 or    $8,$8,$25
16510		 addiu $23,$23,4
16511		 sll   $24,$24,2
16512		 addu  $24,$24,$21
16513		 lw    $14,0x20($24)
16514		 addiu $14,$14,-4
16515		 sw    $14,0x20($24)
16516		 lw    $25,0x84($21)
16517		 sw    $15,m68k_ICount
16518		 sw    $8,0x44($29)
16519		 sw    $14,0x40($29)
16520		 or    $4,$0,$14
16521		 jalr  $25
16522		 sw    $23,0x4C($21)    	 # Delay slot
16523		 lw    $14,0x40($29)
16524		 lw    $8,0x44($29)
16525		 lw    $15,m68k_ICount
16526		 and   $2,$2,$8
16527		 and   $16,$0,$0        	 # Clear Carry
16528		 and   $17,$0,$0        	 # Clear Overflow
16529		 slt   $19,$2,$0        	 # Set Sign
16530		 sltiu $18,$2,1         	 # Set Zero
16531		 lw    $25,0x90($21)
16532		 sw    $15,m68k_ICount
16533		 or    $5,$0,$2
16534		 or    $4,$0,$14
16535		 jalr  $25
16536		 sw    $23,0x4C($21)    	 # Delay slot
16537		 lw    $15,m68k_ICount
16538		 addiu $15,$15,-30
16539		 bgez  $15,3f
16540		 lhu   $24,0x00($23)    	 # Delay slot
16541		 j     MainExit
16542	3:
16543		 sll   $7,$24,2         	 # Delay slot
16544		 addu  $7,$7,$30
16545		 lw    $7,0x00($7)
16546		 jr    $7
16547		 nop                    	 # Delay slot
16548
16549OP0_02a8:				#:
16550		 addiu $23,$23,2
16551
16552		 andi  $24,$24,0x07
16553		 lhu   $8,0x00($23)
16554		 lhu   $25,0x02($23)
16555		 sll   $8,$8,16
16556		 or    $8,$8,$25
16557		 addiu $23,$23,4
16558		 lh    $7,0x00($23)
16559		 sll   $24,$24,2
16560		 addu  $24,$24,$21
16561		 lw    $14,0x20($24)
16562		 addiu $23,$23,2
16563		 addu  $14,$14,$7
16564		 lw    $25,0x84($21)
16565		 sw    $15,m68k_ICount
16566		 sw    $8,0x44($29)
16567		 sw    $14,0x40($29)
16568		 or    $4,$0,$14
16569		 jalr  $25
16570		 sw    $23,0x4C($21)    	 # Delay slot
16571		 lw    $14,0x40($29)
16572		 lw    $8,0x44($29)
16573		 lw    $15,m68k_ICount
16574		 and   $2,$2,$8
16575		 and   $16,$0,$0        	 # Clear Carry
16576		 and   $17,$0,$0        	 # Clear Overflow
16577		 slt   $19,$2,$0        	 # Set Sign
16578		 sltiu $18,$2,1         	 # Set Zero
16579		 lw    $25,0x90($21)
16580		 sw    $15,m68k_ICount
16581		 or    $5,$0,$2
16582		 or    $4,$0,$14
16583		 jalr  $25
16584		 sw    $23,0x4C($21)    	 # Delay slot
16585		 lw    $15,m68k_ICount
16586		 addiu $15,$15,-32
16587		 bgez  $15,3f
16588		 lhu   $24,0x00($23)    	 # Delay slot
16589		 j     MainExit
16590	3:
16591		 sll   $7,$24,2         	 # Delay slot
16592		 addu  $7,$7,$30
16593		 lw    $7,0x00($7)
16594		 jr    $7
16595		 nop                    	 # Delay slot
16596
16597OP0_02b0:				#:
16598		 addiu $23,$23,2
16599
16600		 andi  $24,$24,0x07
16601		 lhu   $8,0x00($23)
16602		 lhu   $25,0x02($23)
16603		 sll   $8,$8,16
16604		 or    $8,$8,$25
16605		 addiu $23,$23,4
16606		 sll   $24,$24,2
16607		 addu  $24,$24,$21
16608		 lw    $14,0x20($24)
16609		 lhu   $7,0x00($23)
16610		 addiu $23,$23,2
16611		 seb   $6,$7
16612		 or    $25,$0,$7
16613		 srl   $7,$7,12
16614		 andi  $25,$25,0x0800
16615		 sll   $7,$7,2
16616		 addu  $7,$7,$21
16617		 bne   $25,$0,0f
16618		 lw    $25,0x00($7)      	 # Delay slot
16619		 seh   $25,$25
16620	0:
16621		 addu  $25,$14,$25
16622		 addu  $14,$25,$6
16623		 lw    $25,0x84($21)
16624		 sw    $15,m68k_ICount
16625		 sw    $8,0x44($29)
16626		 sw    $14,0x40($29)
16627		 or    $4,$0,$14
16628		 jalr  $25
16629		 sw    $23,0x4C($21)    	 # Delay slot
16630		 lw    $14,0x40($29)
16631		 lw    $8,0x44($29)
16632		 lw    $15,m68k_ICount
16633		 and   $2,$2,$8
16634		 and   $16,$0,$0        	 # Clear Carry
16635		 and   $17,$0,$0        	 # Clear Overflow
16636		 slt   $19,$2,$0        	 # Set Sign
16637		 sltiu $18,$2,1         	 # Set Zero
16638		 lw    $25,0x90($21)
16639		 sw    $15,m68k_ICount
16640		 or    $5,$0,$2
16641		 or    $4,$0,$14
16642		 jalr  $25
16643		 sw    $23,0x4C($21)    	 # Delay slot
16644		 lw    $15,m68k_ICount
16645		 addiu $15,$15,-34
16646		 bgez  $15,3f
16647		 lhu   $24,0x00($23)    	 # Delay slot
16648		 j     MainExit
16649	3:
16650		 sll   $7,$24,2         	 # Delay slot
16651		 addu  $7,$7,$30
16652		 lw    $7,0x00($7)
16653		 jr    $7
16654		 nop                    	 # Delay slot
16655
16656OP0_02b8:				#:
16657		 addiu $23,$23,2
16658
16659		 lhu   $8,0x00($23)
16660		 lhu   $25,0x02($23)
16661		 sll   $8,$8,16
16662		 or    $8,$8,$25
16663		 addiu $23,$23,4
16664		 lh    $14,0x00($23)
16665		 addiu $23,$23,2
16666		 lw    $25,0x84($21)
16667		 sw    $15,m68k_ICount
16668		 sw    $8,0x44($29)
16669		 sw    $14,0x40($29)
16670		 or    $4,$0,$14
16671		 jalr  $25
16672		 sw    $23,0x4C($21)    	 # Delay slot
16673		 lw    $14,0x40($29)
16674		 lw    $8,0x44($29)
16675		 lw    $15,m68k_ICount
16676		 and   $2,$2,$8
16677		 and   $16,$0,$0        	 # Clear Carry
16678		 and   $17,$0,$0        	 # Clear Overflow
16679		 slt   $19,$2,$0        	 # Set Sign
16680		 sltiu $18,$2,1         	 # Set Zero
16681		 lw    $25,0x90($21)
16682		 sw    $15,m68k_ICount
16683		 or    $5,$0,$2
16684		 or    $4,$0,$14
16685		 jalr  $25
16686		 sw    $23,0x4C($21)    	 # Delay slot
16687		 lw    $15,m68k_ICount
16688		 addiu $15,$15,-32
16689		 bgez  $15,3f
16690		 lhu   $24,0x00($23)    	 # Delay slot
16691		 j     MainExit
16692	3:
16693		 sll   $7,$24,2         	 # Delay slot
16694		 addu  $7,$7,$30
16695		 lw    $7,0x00($7)
16696		 jr    $7
16697		 nop                    	 # Delay slot
16698
16699OP0_02b9:				#:
16700		 addiu $23,$23,2
16701
16702		 lhu   $8,0x00($23)
16703		 lhu   $25,0x02($23)
16704		 sll   $8,$8,16
16705		 or    $8,$8,$25
16706		 addiu $23,$23,4
16707		 lhu   $14,0x00($23)
16708		 lhu   $25,0x02($23)
16709		 sll   $14,$14,16
16710		 or    $14,$14,$25
16711		 addiu $23,$23,4
16712		 lw    $25,0x84($21)
16713		 sw    $15,m68k_ICount
16714		 sw    $8,0x44($29)
16715		 sw    $14,0x40($29)
16716		 or    $4,$0,$14
16717		 jalr  $25
16718		 sw    $23,0x4C($21)    	 # Delay slot
16719		 lw    $14,0x40($29)
16720		 lw    $8,0x44($29)
16721		 lw    $15,m68k_ICount
16722		 and   $2,$2,$8
16723		 and   $16,$0,$0        	 # Clear Carry
16724		 and   $17,$0,$0        	 # Clear Overflow
16725		 slt   $19,$2,$0        	 # Set Sign
16726		 sltiu $18,$2,1         	 # Set Zero
16727		 lw    $25,0x90($21)
16728		 sw    $15,m68k_ICount
16729		 or    $5,$0,$2
16730		 or    $4,$0,$14
16731		 jalr  $25
16732		 sw    $23,0x4C($21)    	 # Delay slot
16733		 lw    $15,m68k_ICount
16734		 addiu $15,$15,-36
16735		 bgez  $15,3f
16736		 lhu   $24,0x00($23)    	 # Delay slot
16737		 j     MainExit
16738	3:
16739		 sll   $7,$24,2         	 # Delay slot
16740		 addu  $7,$7,$30
16741		 lw    $7,0x00($7)
16742		 jr    $7
16743		 nop                    	 # Delay slot
16744
16745OP0_0400:				#:
16746		 addiu $23,$23,2
16747
16748		 andi  $24,$24,0x07
16749		 lb    $8,0x00($23)
16750		 addiu $23,$23,2
16751		 sll   $24,$24,2
16752		 addu  $24,$24,$21
16753		 lb    $9,0x00($24)
16754		 subu  $2,$9,$8
16755		 sltu  $16,$9,$8       	 # Set Carry
16756		 xor   $17,$9,$8
16757		 xor   $25,$2,$9
16758		 and   $17,$17,$25
16759		 srl   $17,$17,7
16760		 andi  $17,$17,0x01     	 # Set Overflow
16761		 seb  $25,$2
16762		 slt   $19,$25,$0        	 # Set Sign
16763		 sltiu $18,$25,1         	 # Set Zero
16764		 or    $20,$0,$16      	 # Copy Carry to X
16765		 sb    $2,0x00($24)
16766		 addiu $15,$15,-8
16767		 bgez  $15,3f
16768		 lhu   $24,0x00($23)    	 # Delay slot
16769		 j     MainExit
16770	3:
16771		 sll   $7,$24,2         	 # Delay slot
16772		 addu  $7,$7,$30
16773		 lw    $7,0x00($7)
16774		 jr    $7
16775		 nop                    	 # Delay slot
16776
16777OP0_0410:				#:
16778		 addiu $23,$23,2
16779
16780		 andi  $24,$24,0x07
16781		 lb    $8,0x00($23)
16782		 addiu $23,$23,2
16783		 sll   $24,$24,2
16784		 addu  $24,$24,$21
16785		 lw    $14,0x20($24)
16786		 lw    $25,0x7C($21)
16787		 sw    $15,m68k_ICount
16788		 sw    $8,0x44($29)
16789		 sw    $14,0x40($29)
16790		 or    $4,$0,$14
16791		 jalr  $25
16792		 sw    $23,0x4C($21)    	 # Delay slot
16793		 lw    $14,0x40($29)
16794		 lw    $8,0x44($29)
16795		 lw    $15,m68k_ICount
16796		 seb   $9,$2
16797		 subu  $2,$9,$8
16798		 sltu  $16,$9,$8       	 # Set Carry
16799		 xor   $17,$9,$8
16800		 xor   $25,$2,$9
16801		 and   $17,$17,$25
16802		 srl   $17,$17,7
16803		 andi  $17,$17,0x01     	 # Set Overflow
16804		 seb  $25,$2
16805		 slt   $19,$25,$0        	 # Set Sign
16806		 sltiu $18,$25,1         	 # Set Zero
16807		 or    $20,$0,$16      	 # Copy Carry to X
16808		 lw    $25,0x88($21)
16809		 sw    $15,m68k_ICount
16810		 or    $5,$0,$2
16811		 or    $4,$0,$14
16812		 jalr  $25
16813		 sw    $23,0x4C($21)    	 # Delay slot
16814		 lw    $15,m68k_ICount
16815		 addiu $15,$15,-16
16816		 bgez  $15,3f
16817		 lhu   $24,0x00($23)    	 # Delay slot
16818		 j     MainExit
16819	3:
16820		 sll   $7,$24,2         	 # Delay slot
16821		 addu  $7,$7,$30
16822		 lw    $7,0x00($7)
16823		 jr    $7
16824		 nop                    	 # Delay slot
16825
16826OP0_0418:				#:
16827		 addiu $23,$23,2
16828
16829		 andi  $24,$24,0x07
16830		 lb    $8,0x00($23)
16831		 addiu $23,$23,2
16832		 sll   $24,$24,2
16833		 addu  $24,$24,$21
16834		 lw    $14,0x20($24)
16835		 addiu $25,$14,1
16836		 sw    $25,0x20($24)
16837		 lw    $25,0x7C($21)
16838		 sw    $15,m68k_ICount
16839		 sw    $8,0x44($29)
16840		 sw    $14,0x40($29)
16841		 or    $4,$0,$14
16842		 jalr  $25
16843		 sw    $23,0x4C($21)    	 # Delay slot
16844		 lw    $14,0x40($29)
16845		 lw    $8,0x44($29)
16846		 lw    $15,m68k_ICount
16847		 seb   $9,$2
16848		 subu  $2,$9,$8
16849		 sltu  $16,$9,$8       	 # Set Carry
16850		 xor   $17,$9,$8
16851		 xor   $25,$2,$9
16852		 and   $17,$17,$25
16853		 srl   $17,$17,7
16854		 andi  $17,$17,0x01     	 # Set Overflow
16855		 seb  $25,$2
16856		 slt   $19,$25,$0        	 # Set Sign
16857		 sltiu $18,$25,1         	 # Set Zero
16858		 or    $20,$0,$16      	 # Copy Carry to X
16859		 lw    $25,0x88($21)
16860		 sw    $15,m68k_ICount
16861		 or    $5,$0,$2
16862		 or    $4,$0,$14
16863		 jalr  $25
16864		 sw    $23,0x4C($21)    	 # Delay slot
16865		 lw    $15,m68k_ICount
16866		 addiu $15,$15,-16
16867		 bgez  $15,3f
16868		 lhu   $24,0x00($23)    	 # Delay slot
16869		 j     MainExit
16870	3:
16871		 sll   $7,$24,2         	 # Delay slot
16872		 addu  $7,$7,$30
16873		 lw    $7,0x00($7)
16874		 jr    $7
16875		 nop                    	 # Delay slot
16876
16877OP0_041f:				#:
16878		 addiu $23,$23,2
16879
16880		 lb    $8,0x00($23)
16881		 addiu $23,$23,2
16882		 lw    $14,0x3C($21)    	 # Get A7
16883		 addiu $25,$14,2
16884		 sw    $25,0x3C($21)
16885		 lw    $25,0x7C($21)
16886		 sw    $15,m68k_ICount
16887		 sw    $8,0x44($29)
16888		 sw    $14,0x40($29)
16889		 or    $4,$0,$14
16890		 jalr  $25
16891		 sw    $23,0x4C($21)    	 # Delay slot
16892		 lw    $14,0x40($29)
16893		 lw    $8,0x44($29)
16894		 lw    $15,m68k_ICount
16895		 seb   $9,$2
16896		 subu  $2,$9,$8
16897		 sltu  $16,$9,$8       	 # Set Carry
16898		 xor   $17,$9,$8
16899		 xor   $25,$2,$9
16900		 and   $17,$17,$25
16901		 srl   $17,$17,7
16902		 andi  $17,$17,0x01     	 # Set Overflow
16903		 seb  $25,$2
16904		 slt   $19,$25,$0        	 # Set Sign
16905		 sltiu $18,$25,1         	 # Set Zero
16906		 or    $20,$0,$16      	 # Copy Carry to X
16907		 lw    $25,0x88($21)
16908		 sw    $15,m68k_ICount
16909		 or    $5,$0,$2
16910		 or    $4,$0,$14
16911		 jalr  $25
16912		 sw    $23,0x4C($21)    	 # Delay slot
16913		 lw    $15,m68k_ICount
16914		 addiu $15,$15,-16
16915		 bgez  $15,3f
16916		 lhu   $24,0x00($23)    	 # Delay slot
16917		 j     MainExit
16918	3:
16919		 sll   $7,$24,2         	 # Delay slot
16920		 addu  $7,$7,$30
16921		 lw    $7,0x00($7)
16922		 jr    $7
16923		 nop                    	 # Delay slot
16924
16925OP0_0420:				#:
16926		 addiu $23,$23,2
16927
16928		 andi  $24,$24,0x07
16929		 lb    $8,0x00($23)
16930		 addiu $23,$23,2
16931		 sll   $24,$24,2
16932		 addu  $24,$24,$21
16933		 lw    $14,0x20($24)
16934		 addiu $14,$14,-1
16935		 sw    $14,0x20($24)
16936		 lw    $25,0x7C($21)
16937		 sw    $15,m68k_ICount
16938		 sw    $8,0x44($29)
16939		 sw    $14,0x40($29)
16940		 or    $4,$0,$14
16941		 jalr  $25
16942		 sw    $23,0x4C($21)    	 # Delay slot
16943		 lw    $14,0x40($29)
16944		 lw    $8,0x44($29)
16945		 lw    $15,m68k_ICount
16946		 seb   $9,$2
16947		 subu  $2,$9,$8
16948		 sltu  $16,$9,$8       	 # Set Carry
16949		 xor   $17,$9,$8
16950		 xor   $25,$2,$9
16951		 and   $17,$17,$25
16952		 srl   $17,$17,7
16953		 andi  $17,$17,0x01     	 # Set Overflow
16954		 seb  $25,$2
16955		 slt   $19,$25,$0        	 # Set Sign
16956		 sltiu $18,$25,1         	 # Set Zero
16957		 or    $20,$0,$16      	 # Copy Carry to X
16958		 lw    $25,0x88($21)
16959		 sw    $15,m68k_ICount
16960		 or    $5,$0,$2
16961		 or    $4,$0,$14
16962		 jalr  $25
16963		 sw    $23,0x4C($21)    	 # Delay slot
16964		 lw    $15,m68k_ICount
16965		 addiu $15,$15,-18
16966		 bgez  $15,3f
16967		 lhu   $24,0x00($23)    	 # Delay slot
16968		 j     MainExit
16969	3:
16970		 sll   $7,$24,2         	 # Delay slot
16971		 addu  $7,$7,$30
16972		 lw    $7,0x00($7)
16973		 jr    $7
16974		 nop                    	 # Delay slot
16975
16976OP0_0427:				#:
16977		 addiu $23,$23,2
16978
16979		 lb    $8,0x00($23)
16980		 addiu $23,$23,2
16981		 lw    $14,0x3C($21)    	 # Get A7
16982		 addiu $14,$14,-2
16983		 sw    $14,0x3C($21)
16984		 lw    $25,0x7C($21)
16985		 sw    $15,m68k_ICount
16986		 sw    $8,0x44($29)
16987		 sw    $14,0x40($29)
16988		 or    $4,$0,$14
16989		 jalr  $25
16990		 sw    $23,0x4C($21)    	 # Delay slot
16991		 lw    $14,0x40($29)
16992		 lw    $8,0x44($29)
16993		 lw    $15,m68k_ICount
16994		 seb   $9,$2
16995		 subu  $2,$9,$8
16996		 sltu  $16,$9,$8       	 # Set Carry
16997		 xor   $17,$9,$8
16998		 xor   $25,$2,$9
16999		 and   $17,$17,$25
17000		 srl   $17,$17,7
17001		 andi  $17,$17,0x01     	 # Set Overflow
17002		 seb  $25,$2
17003		 slt   $19,$25,$0        	 # Set Sign
17004		 sltiu $18,$25,1         	 # Set Zero
17005		 or    $20,$0,$16      	 # Copy Carry to X
17006		 lw    $25,0x88($21)
17007		 sw    $15,m68k_ICount
17008		 or    $5,$0,$2
17009		 or    $4,$0,$14
17010		 jalr  $25
17011		 sw    $23,0x4C($21)    	 # Delay slot
17012		 lw    $15,m68k_ICount
17013		 addiu $15,$15,-18
17014		 bgez  $15,3f
17015		 lhu   $24,0x00($23)    	 # Delay slot
17016		 j     MainExit
17017	3:
17018		 sll   $7,$24,2         	 # Delay slot
17019		 addu  $7,$7,$30
17020		 lw    $7,0x00($7)
17021		 jr    $7
17022		 nop                    	 # Delay slot
17023
17024OP0_0428:				#:
17025		 addiu $23,$23,2
17026
17027		 andi  $24,$24,0x07
17028		 lb    $8,0x00($23)
17029		 addiu $23,$23,2
17030		 lh    $7,0x00($23)
17031		 sll   $24,$24,2
17032		 addu  $24,$24,$21
17033		 lw    $14,0x20($24)
17034		 addiu $23,$23,2
17035		 addu  $14,$14,$7
17036		 lw    $25,0x7C($21)
17037		 sw    $15,m68k_ICount
17038		 sw    $8,0x44($29)
17039		 sw    $14,0x40($29)
17040		 or    $4,$0,$14
17041		 jalr  $25
17042		 sw    $23,0x4C($21)    	 # Delay slot
17043		 lw    $14,0x40($29)
17044		 lw    $8,0x44($29)
17045		 lw    $15,m68k_ICount
17046		 seb   $9,$2
17047		 subu  $2,$9,$8
17048		 sltu  $16,$9,$8       	 # Set Carry
17049		 xor   $17,$9,$8
17050		 xor   $25,$2,$9
17051		 and   $17,$17,$25
17052		 srl   $17,$17,7
17053		 andi  $17,$17,0x01     	 # Set Overflow
17054		 seb  $25,$2
17055		 slt   $19,$25,$0        	 # Set Sign
17056		 sltiu $18,$25,1         	 # Set Zero
17057		 or    $20,$0,$16      	 # Copy Carry to X
17058		 lw    $25,0x88($21)
17059		 sw    $15,m68k_ICount
17060		 or    $5,$0,$2
17061		 or    $4,$0,$14
17062		 jalr  $25
17063		 sw    $23,0x4C($21)    	 # Delay slot
17064		 lw    $15,m68k_ICount
17065		 addiu $15,$15,-20
17066		 bgez  $15,3f
17067		 lhu   $24,0x00($23)    	 # Delay slot
17068		 j     MainExit
17069	3:
17070		 sll   $7,$24,2         	 # Delay slot
17071		 addu  $7,$7,$30
17072		 lw    $7,0x00($7)
17073		 jr    $7
17074		 nop                    	 # Delay slot
17075
17076OP0_0430:				#:
17077		 addiu $23,$23,2
17078
17079		 andi  $24,$24,0x07
17080		 lb    $8,0x00($23)
17081		 addiu $23,$23,2
17082		 sll   $24,$24,2
17083		 addu  $24,$24,$21
17084		 lw    $14,0x20($24)
17085		 lhu   $7,0x00($23)
17086		 addiu $23,$23,2
17087		 seb   $6,$7
17088		 or    $25,$0,$7
17089		 srl   $7,$7,12
17090		 andi  $25,$25,0x0800
17091		 sll   $7,$7,2
17092		 addu  $7,$7,$21
17093		 bne   $25,$0,0f
17094		 lw    $25,0x00($7)      	 # Delay slot
17095		 seh   $25,$25
17096	0:
17097		 addu  $25,$14,$25
17098		 addu  $14,$25,$6
17099		 lw    $25,0x7C($21)
17100		 sw    $15,m68k_ICount
17101		 sw    $8,0x44($29)
17102		 sw    $14,0x40($29)
17103		 or    $4,$0,$14
17104		 jalr  $25
17105		 sw    $23,0x4C($21)    	 # Delay slot
17106		 lw    $14,0x40($29)
17107		 lw    $8,0x44($29)
17108		 lw    $15,m68k_ICount
17109		 seb   $9,$2
17110		 subu  $2,$9,$8
17111		 sltu  $16,$9,$8       	 # Set Carry
17112		 xor   $17,$9,$8
17113		 xor   $25,$2,$9
17114		 and   $17,$17,$25
17115		 srl   $17,$17,7
17116		 andi  $17,$17,0x01     	 # Set Overflow
17117		 seb  $25,$2
17118		 slt   $19,$25,$0        	 # Set Sign
17119		 sltiu $18,$25,1         	 # Set Zero
17120		 or    $20,$0,$16      	 # Copy Carry to X
17121		 lw    $25,0x88($21)
17122		 sw    $15,m68k_ICount
17123		 or    $5,$0,$2
17124		 or    $4,$0,$14
17125		 jalr  $25
17126		 sw    $23,0x4C($21)    	 # Delay slot
17127		 lw    $15,m68k_ICount
17128		 addiu $15,$15,-22
17129		 bgez  $15,3f
17130		 lhu   $24,0x00($23)    	 # Delay slot
17131		 j     MainExit
17132	3:
17133		 sll   $7,$24,2         	 # Delay slot
17134		 addu  $7,$7,$30
17135		 lw    $7,0x00($7)
17136		 jr    $7
17137		 nop                    	 # Delay slot
17138
17139OP0_0438:				#:
17140		 addiu $23,$23,2
17141
17142		 lb    $8,0x00($23)
17143		 addiu $23,$23,2
17144		 lh    $14,0x00($23)
17145		 addiu $23,$23,2
17146		 lw    $25,0x7C($21)
17147		 sw    $15,m68k_ICount
17148		 sw    $8,0x44($29)
17149		 sw    $14,0x40($29)
17150		 or    $4,$0,$14
17151		 jalr  $25
17152		 sw    $23,0x4C($21)    	 # Delay slot
17153		 lw    $14,0x40($29)
17154		 lw    $8,0x44($29)
17155		 lw    $15,m68k_ICount
17156		 seb   $9,$2
17157		 subu  $2,$9,$8
17158		 sltu  $16,$9,$8       	 # Set Carry
17159		 xor   $17,$9,$8
17160		 xor   $25,$2,$9
17161		 and   $17,$17,$25
17162		 srl   $17,$17,7
17163		 andi  $17,$17,0x01     	 # Set Overflow
17164		 seb  $25,$2
17165		 slt   $19,$25,$0        	 # Set Sign
17166		 sltiu $18,$25,1         	 # Set Zero
17167		 or    $20,$0,$16      	 # Copy Carry to X
17168		 lw    $25,0x88($21)
17169		 sw    $15,m68k_ICount
17170		 or    $5,$0,$2
17171		 or    $4,$0,$14
17172		 jalr  $25
17173		 sw    $23,0x4C($21)    	 # Delay slot
17174		 lw    $15,m68k_ICount
17175		 addiu $15,$15,-20
17176		 bgez  $15,3f
17177		 lhu   $24,0x00($23)    	 # Delay slot
17178		 j     MainExit
17179	3:
17180		 sll   $7,$24,2         	 # Delay slot
17181		 addu  $7,$7,$30
17182		 lw    $7,0x00($7)
17183		 jr    $7
17184		 nop                    	 # Delay slot
17185
17186OP0_0439:				#:
17187		 addiu $23,$23,2
17188
17189		 lb    $8,0x00($23)
17190		 addiu $23,$23,2
17191		 lhu   $14,0x00($23)
17192		 lhu   $25,0x02($23)
17193		 sll   $14,$14,16
17194		 or    $14,$14,$25
17195		 addiu $23,$23,4
17196		 lw    $25,0x7C($21)
17197		 sw    $15,m68k_ICount
17198		 sw    $8,0x44($29)
17199		 sw    $14,0x40($29)
17200		 or    $4,$0,$14
17201		 jalr  $25
17202		 sw    $23,0x4C($21)    	 # Delay slot
17203		 lw    $14,0x40($29)
17204		 lw    $8,0x44($29)
17205		 lw    $15,m68k_ICount
17206		 seb   $9,$2
17207		 subu  $2,$9,$8
17208		 sltu  $16,$9,$8       	 # Set Carry
17209		 xor   $17,$9,$8
17210		 xor   $25,$2,$9
17211		 and   $17,$17,$25
17212		 srl   $17,$17,7
17213		 andi  $17,$17,0x01     	 # Set Overflow
17214		 seb  $25,$2
17215		 slt   $19,$25,$0        	 # Set Sign
17216		 sltiu $18,$25,1         	 # Set Zero
17217		 or    $20,$0,$16      	 # Copy Carry to X
17218		 lw    $25,0x88($21)
17219		 sw    $15,m68k_ICount
17220		 or    $5,$0,$2
17221		 or    $4,$0,$14
17222		 jalr  $25
17223		 sw    $23,0x4C($21)    	 # Delay slot
17224		 lw    $15,m68k_ICount
17225		 addiu $15,$15,-24
17226		 bgez  $15,3f
17227		 lhu   $24,0x00($23)    	 # Delay slot
17228		 j     MainExit
17229	3:
17230		 sll   $7,$24,2         	 # Delay slot
17231		 addu  $7,$7,$30
17232		 lw    $7,0x00($7)
17233		 jr    $7
17234		 nop                    	 # Delay slot
17235
17236OP0_0440:				#:
17237		 addiu $23,$23,2
17238
17239		 andi  $24,$24,0x07
17240		 lh    $8,0x00($23)
17241		 addiu $23,$23,2
17242		 sll   $24,$24,2
17243		 addu  $24,$24,$21
17244		 lh    $9,0x00($24)
17245		 subu  $2,$9,$8
17246		 sltu  $16,$9,$8       	 # Set Carry
17247		 xor   $17,$9,$8
17248		 xor   $25,$2,$9
17249		 and   $17,$17,$25
17250		 srl   $17,$17,15
17251		 andi  $17,$17,0x01     	 # Set Overflow
17252		 seh  $25,$2
17253		 slt   $19,$25,$0        	 # Set Sign
17254		 sltiu $18,$25,1         	 # Set Zero
17255		 or    $20,$0,$16      	 # Copy Carry to X
17256		 sh    $2,0x00($24)
17257		 addiu $15,$15,-8
17258		 bgez  $15,3f
17259		 lhu   $24,0x00($23)    	 # Delay slot
17260		 j     MainExit
17261	3:
17262		 sll   $7,$24,2         	 # Delay slot
17263		 addu  $7,$7,$30
17264		 lw    $7,0x00($7)
17265		 jr    $7
17266		 nop                    	 # Delay slot
17267
17268OP0_0450:				#:
17269		 addiu $23,$23,2
17270
17271		 andi  $24,$24,0x07
17272		 lh    $8,0x00($23)
17273		 addiu $23,$23,2
17274		 sll   $24,$24,2
17275		 addu  $24,$24,$21
17276		 lw    $14,0x20($24)
17277		 lw    $25,0x80($21)
17278		 sw    $15,m68k_ICount
17279		 sw    $8,0x44($29)
17280		 sw    $14,0x40($29)
17281		 or    $4,$0,$14
17282		 jalr  $25
17283		 sw    $23,0x4C($21)    	 # Delay slot
17284		 lw    $14,0x40($29)
17285		 lw    $8,0x44($29)
17286		 lw    $15,m68k_ICount
17287		 seh   $9,$2
17288		 subu  $2,$9,$8
17289		 sltu  $16,$9,$8       	 # Set Carry
17290		 xor   $17,$9,$8
17291		 xor   $25,$2,$9
17292		 and   $17,$17,$25
17293		 srl   $17,$17,15
17294		 andi  $17,$17,0x01     	 # Set Overflow
17295		 seh  $25,$2
17296		 slt   $19,$25,$0        	 # Set Sign
17297		 sltiu $18,$25,1         	 # Set Zero
17298		 or    $20,$0,$16      	 # Copy Carry to X
17299		 lw    $25,0x8C($21)
17300		 sw    $15,m68k_ICount
17301		 or    $5,$0,$2
17302		 or    $4,$0,$14
17303		 jalr  $25
17304		 sw    $23,0x4C($21)    	 # Delay slot
17305		 lw    $15,m68k_ICount
17306		 addiu $15,$15,-16
17307		 bgez  $15,3f
17308		 lhu   $24,0x00($23)    	 # Delay slot
17309		 j     MainExit
17310	3:
17311		 sll   $7,$24,2         	 # Delay slot
17312		 addu  $7,$7,$30
17313		 lw    $7,0x00($7)
17314		 jr    $7
17315		 nop                    	 # Delay slot
17316
17317OP0_0458:				#:
17318		 addiu $23,$23,2
17319
17320		 andi  $24,$24,0x07
17321		 lh    $8,0x00($23)
17322		 addiu $23,$23,2
17323		 sll   $24,$24,2
17324		 addu  $24,$24,$21
17325		 lw    $14,0x20($24)
17326		 addiu $25,$14,2
17327		 sw    $25,0x20($24)
17328		 lw    $25,0x80($21)
17329		 sw    $15,m68k_ICount
17330		 sw    $8,0x44($29)
17331		 sw    $14,0x40($29)
17332		 or    $4,$0,$14
17333		 jalr  $25
17334		 sw    $23,0x4C($21)    	 # Delay slot
17335		 lw    $14,0x40($29)
17336		 lw    $8,0x44($29)
17337		 lw    $15,m68k_ICount
17338		 seh   $9,$2
17339		 subu  $2,$9,$8
17340		 sltu  $16,$9,$8       	 # Set Carry
17341		 xor   $17,$9,$8
17342		 xor   $25,$2,$9
17343		 and   $17,$17,$25
17344		 srl   $17,$17,15
17345		 andi  $17,$17,0x01     	 # Set Overflow
17346		 seh  $25,$2
17347		 slt   $19,$25,$0        	 # Set Sign
17348		 sltiu $18,$25,1         	 # Set Zero
17349		 or    $20,$0,$16      	 # Copy Carry to X
17350		 lw    $25,0x8C($21)
17351		 sw    $15,m68k_ICount
17352		 or    $5,$0,$2
17353		 or    $4,$0,$14
17354		 jalr  $25
17355		 sw    $23,0x4C($21)    	 # Delay slot
17356		 lw    $15,m68k_ICount
17357		 addiu $15,$15,-16
17358		 bgez  $15,3f
17359		 lhu   $24,0x00($23)    	 # Delay slot
17360		 j     MainExit
17361	3:
17362		 sll   $7,$24,2         	 # Delay slot
17363		 addu  $7,$7,$30
17364		 lw    $7,0x00($7)
17365		 jr    $7
17366		 nop                    	 # Delay slot
17367
17368OP0_0460:				#:
17369		 addiu $23,$23,2
17370
17371		 andi  $24,$24,0x07
17372		 lh    $8,0x00($23)
17373		 addiu $23,$23,2
17374		 sll   $24,$24,2
17375		 addu  $24,$24,$21
17376		 lw    $14,0x20($24)
17377		 addiu $14,$14,-2
17378		 sw    $14,0x20($24)
17379		 lw    $25,0x80($21)
17380		 sw    $15,m68k_ICount
17381		 sw    $8,0x44($29)
17382		 sw    $14,0x40($29)
17383		 or    $4,$0,$14
17384		 jalr  $25
17385		 sw    $23,0x4C($21)    	 # Delay slot
17386		 lw    $14,0x40($29)
17387		 lw    $8,0x44($29)
17388		 lw    $15,m68k_ICount
17389		 seh   $9,$2
17390		 subu  $2,$9,$8
17391		 sltu  $16,$9,$8       	 # Set Carry
17392		 xor   $17,$9,$8
17393		 xor   $25,$2,$9
17394		 and   $17,$17,$25
17395		 srl   $17,$17,15
17396		 andi  $17,$17,0x01     	 # Set Overflow
17397		 seh  $25,$2
17398		 slt   $19,$25,$0        	 # Set Sign
17399		 sltiu $18,$25,1         	 # Set Zero
17400		 or    $20,$0,$16      	 # Copy Carry to X
17401		 lw    $25,0x8C($21)
17402		 sw    $15,m68k_ICount
17403		 or    $5,$0,$2
17404		 or    $4,$0,$14
17405		 jalr  $25
17406		 sw    $23,0x4C($21)    	 # Delay slot
17407		 lw    $15,m68k_ICount
17408		 addiu $15,$15,-18
17409		 bgez  $15,3f
17410		 lhu   $24,0x00($23)    	 # Delay slot
17411		 j     MainExit
17412	3:
17413		 sll   $7,$24,2         	 # Delay slot
17414		 addu  $7,$7,$30
17415		 lw    $7,0x00($7)
17416		 jr    $7
17417		 nop                    	 # Delay slot
17418
17419OP0_0468:				#:
17420		 addiu $23,$23,2
17421
17422		 andi  $24,$24,0x07
17423		 lh    $8,0x00($23)
17424		 addiu $23,$23,2
17425		 lh    $7,0x00($23)
17426		 sll   $24,$24,2
17427		 addu  $24,$24,$21
17428		 lw    $14,0x20($24)
17429		 addiu $23,$23,2
17430		 addu  $14,$14,$7
17431		 lw    $25,0x80($21)
17432		 sw    $15,m68k_ICount
17433		 sw    $8,0x44($29)
17434		 sw    $14,0x40($29)
17435		 or    $4,$0,$14
17436		 jalr  $25
17437		 sw    $23,0x4C($21)    	 # Delay slot
17438		 lw    $14,0x40($29)
17439		 lw    $8,0x44($29)
17440		 lw    $15,m68k_ICount
17441		 seh   $9,$2
17442		 subu  $2,$9,$8
17443		 sltu  $16,$9,$8       	 # Set Carry
17444		 xor   $17,$9,$8
17445		 xor   $25,$2,$9
17446		 and   $17,$17,$25
17447		 srl   $17,$17,15
17448		 andi  $17,$17,0x01     	 # Set Overflow
17449		 seh  $25,$2
17450		 slt   $19,$25,$0        	 # Set Sign
17451		 sltiu $18,$25,1         	 # Set Zero
17452		 or    $20,$0,$16      	 # Copy Carry to X
17453		 lw    $25,0x8C($21)
17454		 sw    $15,m68k_ICount
17455		 or    $5,$0,$2
17456		 or    $4,$0,$14
17457		 jalr  $25
17458		 sw    $23,0x4C($21)    	 # Delay slot
17459		 lw    $15,m68k_ICount
17460		 addiu $15,$15,-20
17461		 bgez  $15,3f
17462		 lhu   $24,0x00($23)    	 # Delay slot
17463		 j     MainExit
17464	3:
17465		 sll   $7,$24,2         	 # Delay slot
17466		 addu  $7,$7,$30
17467		 lw    $7,0x00($7)
17468		 jr    $7
17469		 nop                    	 # Delay slot
17470
17471OP0_0470:				#:
17472		 addiu $23,$23,2
17473
17474		 andi  $24,$24,0x07
17475		 lh    $8,0x00($23)
17476		 addiu $23,$23,2
17477		 sll   $24,$24,2
17478		 addu  $24,$24,$21
17479		 lw    $14,0x20($24)
17480		 lhu   $7,0x00($23)
17481		 addiu $23,$23,2
17482		 seb   $6,$7
17483		 or    $25,$0,$7
17484		 srl   $7,$7,12
17485		 andi  $25,$25,0x0800
17486		 sll   $7,$7,2
17487		 addu  $7,$7,$21
17488		 bne   $25,$0,0f
17489		 lw    $25,0x00($7)      	 # Delay slot
17490		 seh   $25,$25
17491	0:
17492		 addu  $25,$14,$25
17493		 addu  $14,$25,$6
17494		 lw    $25,0x80($21)
17495		 sw    $15,m68k_ICount
17496		 sw    $8,0x44($29)
17497		 sw    $14,0x40($29)
17498		 or    $4,$0,$14
17499		 jalr  $25
17500		 sw    $23,0x4C($21)    	 # Delay slot
17501		 lw    $14,0x40($29)
17502		 lw    $8,0x44($29)
17503		 lw    $15,m68k_ICount
17504		 seh   $9,$2
17505		 subu  $2,$9,$8
17506		 sltu  $16,$9,$8       	 # Set Carry
17507		 xor   $17,$9,$8
17508		 xor   $25,$2,$9
17509		 and   $17,$17,$25
17510		 srl   $17,$17,15
17511		 andi  $17,$17,0x01     	 # Set Overflow
17512		 seh  $25,$2
17513		 slt   $19,$25,$0        	 # Set Sign
17514		 sltiu $18,$25,1         	 # Set Zero
17515		 or    $20,$0,$16      	 # Copy Carry to X
17516		 lw    $25,0x8C($21)
17517		 sw    $15,m68k_ICount
17518		 or    $5,$0,$2
17519		 or    $4,$0,$14
17520		 jalr  $25
17521		 sw    $23,0x4C($21)    	 # Delay slot
17522		 lw    $15,m68k_ICount
17523		 addiu $15,$15,-22
17524		 bgez  $15,3f
17525		 lhu   $24,0x00($23)    	 # Delay slot
17526		 j     MainExit
17527	3:
17528		 sll   $7,$24,2         	 # Delay slot
17529		 addu  $7,$7,$30
17530		 lw    $7,0x00($7)
17531		 jr    $7
17532		 nop                    	 # Delay slot
17533
17534OP0_0478:				#:
17535		 addiu $23,$23,2
17536
17537		 lh    $8,0x00($23)
17538		 addiu $23,$23,2
17539		 lh    $14,0x00($23)
17540		 addiu $23,$23,2
17541		 lw    $25,0x80($21)
17542		 sw    $15,m68k_ICount
17543		 sw    $8,0x44($29)
17544		 sw    $14,0x40($29)
17545		 or    $4,$0,$14
17546		 jalr  $25
17547		 sw    $23,0x4C($21)    	 # Delay slot
17548		 lw    $14,0x40($29)
17549		 lw    $8,0x44($29)
17550		 lw    $15,m68k_ICount
17551		 seh   $9,$2
17552		 subu  $2,$9,$8
17553		 sltu  $16,$9,$8       	 # Set Carry
17554		 xor   $17,$9,$8
17555		 xor   $25,$2,$9
17556		 and   $17,$17,$25
17557		 srl   $17,$17,15
17558		 andi  $17,$17,0x01     	 # Set Overflow
17559		 seh  $25,$2
17560		 slt   $19,$25,$0        	 # Set Sign
17561		 sltiu $18,$25,1         	 # Set Zero
17562		 or    $20,$0,$16      	 # Copy Carry to X
17563		 lw    $25,0x8C($21)
17564		 sw    $15,m68k_ICount
17565		 or    $5,$0,$2
17566		 or    $4,$0,$14
17567		 jalr  $25
17568		 sw    $23,0x4C($21)    	 # Delay slot
17569		 lw    $15,m68k_ICount
17570		 addiu $15,$15,-20
17571		 bgez  $15,3f
17572		 lhu   $24,0x00($23)    	 # Delay slot
17573		 j     MainExit
17574	3:
17575		 sll   $7,$24,2         	 # Delay slot
17576		 addu  $7,$7,$30
17577		 lw    $7,0x00($7)
17578		 jr    $7
17579		 nop                    	 # Delay slot
17580
17581OP0_0479:				#:
17582		 addiu $23,$23,2
17583
17584		 lh    $8,0x00($23)
17585		 addiu $23,$23,2
17586		 lhu   $14,0x00($23)
17587		 lhu   $25,0x02($23)
17588		 sll   $14,$14,16
17589		 or    $14,$14,$25
17590		 addiu $23,$23,4
17591		 lw    $25,0x80($21)
17592		 sw    $15,m68k_ICount
17593		 sw    $8,0x44($29)
17594		 sw    $14,0x40($29)
17595		 or    $4,$0,$14
17596		 jalr  $25
17597		 sw    $23,0x4C($21)    	 # Delay slot
17598		 lw    $14,0x40($29)
17599		 lw    $8,0x44($29)
17600		 lw    $15,m68k_ICount
17601		 seh   $9,$2
17602		 subu  $2,$9,$8
17603		 sltu  $16,$9,$8       	 # Set Carry
17604		 xor   $17,$9,$8
17605		 xor   $25,$2,$9
17606		 and   $17,$17,$25
17607		 srl   $17,$17,15
17608		 andi  $17,$17,0x01     	 # Set Overflow
17609		 seh  $25,$2
17610		 slt   $19,$25,$0        	 # Set Sign
17611		 sltiu $18,$25,1         	 # Set Zero
17612		 or    $20,$0,$16      	 # Copy Carry to X
17613		 lw    $25,0x8C($21)
17614		 sw    $15,m68k_ICount
17615		 or    $5,$0,$2
17616		 or    $4,$0,$14
17617		 jalr  $25
17618		 sw    $23,0x4C($21)    	 # Delay slot
17619		 lw    $15,m68k_ICount
17620		 addiu $15,$15,-24
17621		 bgez  $15,3f
17622		 lhu   $24,0x00($23)    	 # Delay slot
17623		 j     MainExit
17624	3:
17625		 sll   $7,$24,2         	 # Delay slot
17626		 addu  $7,$7,$30
17627		 lw    $7,0x00($7)
17628		 jr    $7
17629		 nop                    	 # Delay slot
17630
17631OP0_0480:				#:
17632		 addiu $23,$23,2
17633
17634		 andi  $24,$24,0x07
17635		 lhu   $8,0x00($23)
17636		 lhu   $25,0x02($23)
17637		 sll   $8,$8,16
17638		 or    $8,$8,$25
17639		 addiu $23,$23,4
17640		 sll   $24,$24,2
17641		 addu  $24,$24,$21
17642		 lw    $9,0x00($24)
17643		 subu  $2,$9,$8
17644		 sltu  $16,$9,$8       	 # Set Carry
17645		 xor   $17,$9,$8
17646		 xor   $25,$2,$9
17647		 and   $17,$17,$25
17648		 srl   $17,$17,31        	 # Set Overflow
17649		 slt   $19,$2,$0        	 # Set Sign
17650		 sltiu $18,$2,1         	 # Set Zero
17651		 or    $20,$0,$16      	 # Copy Carry to X
17652		 sw    $2,0x00($24)
17653		 addiu $15,$15,-16
17654		 bgez  $15,3f
17655		 lhu   $24,0x00($23)    	 # Delay slot
17656		 j     MainExit
17657	3:
17658		 sll   $7,$24,2         	 # Delay slot
17659		 addu  $7,$7,$30
17660		 lw    $7,0x00($7)
17661		 jr    $7
17662		 nop                    	 # Delay slot
17663
17664OP0_0490:				#:
17665		 addiu $23,$23,2
17666
17667		 andi  $24,$24,0x07
17668		 lhu   $8,0x00($23)
17669		 lhu   $25,0x02($23)
17670		 sll   $8,$8,16
17671		 or    $8,$8,$25
17672		 addiu $23,$23,4
17673		 sll   $24,$24,2
17674		 addu  $24,$24,$21
17675		 lw    $14,0x20($24)
17676		 lw    $25,0x84($21)
17677		 sw    $15,m68k_ICount
17678		 sw    $8,0x44($29)
17679		 sw    $14,0x40($29)
17680		 or    $4,$0,$14
17681		 jalr  $25
17682		 sw    $23,0x4C($21)    	 # Delay slot
17683		 lw    $14,0x40($29)
17684		 lw    $8,0x44($29)
17685		 lw    $15,m68k_ICount
17686		 or    $9,$0,$2
17687		 subu  $2,$9,$8
17688		 sltu  $16,$9,$8       	 # Set Carry
17689		 xor   $17,$9,$8
17690		 xor   $25,$2,$9
17691		 and   $17,$17,$25
17692		 srl   $17,$17,31        	 # Set Overflow
17693		 slt   $19,$2,$0        	 # Set Sign
17694		 sltiu $18,$2,1         	 # Set Zero
17695		 or    $20,$0,$16      	 # Copy Carry to X
17696		 lw    $25,0x90($21)
17697		 sw    $15,m68k_ICount
17698		 or    $5,$0,$2
17699		 or    $4,$0,$14
17700		 jalr  $25
17701		 sw    $23,0x4C($21)    	 # Delay slot
17702		 lw    $15,m68k_ICount
17703		 addiu $15,$15,-28
17704		 bgez  $15,3f
17705		 lhu   $24,0x00($23)    	 # Delay slot
17706		 j     MainExit
17707	3:
17708		 sll   $7,$24,2         	 # Delay slot
17709		 addu  $7,$7,$30
17710		 lw    $7,0x00($7)
17711		 jr    $7
17712		 nop                    	 # Delay slot
17713
17714OP0_0498:				#:
17715		 addiu $23,$23,2
17716
17717		 andi  $24,$24,0x07
17718		 lhu   $8,0x00($23)
17719		 lhu   $25,0x02($23)
17720		 sll   $8,$8,16
17721		 or    $8,$8,$25
17722		 addiu $23,$23,4
17723		 sll   $24,$24,2
17724		 addu  $24,$24,$21
17725		 lw    $14,0x20($24)
17726		 addiu $25,$14,4
17727		 sw    $25,0x20($24)
17728		 lw    $25,0x84($21)
17729		 sw    $15,m68k_ICount
17730		 sw    $8,0x44($29)
17731		 sw    $14,0x40($29)
17732		 or    $4,$0,$14
17733		 jalr  $25
17734		 sw    $23,0x4C($21)    	 # Delay slot
17735		 lw    $14,0x40($29)
17736		 lw    $8,0x44($29)
17737		 lw    $15,m68k_ICount
17738		 or    $9,$0,$2
17739		 subu  $2,$9,$8
17740		 sltu  $16,$9,$8       	 # Set Carry
17741		 xor   $17,$9,$8
17742		 xor   $25,$2,$9
17743		 and   $17,$17,$25
17744		 srl   $17,$17,31        	 # Set Overflow
17745		 slt   $19,$2,$0        	 # Set Sign
17746		 sltiu $18,$2,1         	 # Set Zero
17747		 or    $20,$0,$16      	 # Copy Carry to X
17748		 lw    $25,0x90($21)
17749		 sw    $15,m68k_ICount
17750		 or    $5,$0,$2
17751		 or    $4,$0,$14
17752		 jalr  $25
17753		 sw    $23,0x4C($21)    	 # Delay slot
17754		 lw    $15,m68k_ICount
17755		 addiu $15,$15,-28
17756		 bgez  $15,3f
17757		 lhu   $24,0x00($23)    	 # Delay slot
17758		 j     MainExit
17759	3:
17760		 sll   $7,$24,2         	 # Delay slot
17761		 addu  $7,$7,$30
17762		 lw    $7,0x00($7)
17763		 jr    $7
17764		 nop                    	 # Delay slot
17765
17766OP0_04a0:				#:
17767		 addiu $23,$23,2
17768
17769		 andi  $24,$24,0x07
17770		 lhu   $8,0x00($23)
17771		 lhu   $25,0x02($23)
17772		 sll   $8,$8,16
17773		 or    $8,$8,$25
17774		 addiu $23,$23,4
17775		 sll   $24,$24,2
17776		 addu  $24,$24,$21
17777		 lw    $14,0x20($24)
17778		 addiu $14,$14,-4
17779		 sw    $14,0x20($24)
17780		 lw    $25,0x84($21)
17781		 sw    $15,m68k_ICount
17782		 sw    $8,0x44($29)
17783		 sw    $14,0x40($29)
17784		 or    $4,$0,$14
17785		 jalr  $25
17786		 sw    $23,0x4C($21)    	 # Delay slot
17787		 lw    $14,0x40($29)
17788		 lw    $8,0x44($29)
17789		 lw    $15,m68k_ICount
17790		 or    $9,$0,$2
17791		 subu  $2,$9,$8
17792		 sltu  $16,$9,$8       	 # Set Carry
17793		 xor   $17,$9,$8
17794		 xor   $25,$2,$9
17795		 and   $17,$17,$25
17796		 srl   $17,$17,31        	 # Set Overflow
17797		 slt   $19,$2,$0        	 # Set Sign
17798		 sltiu $18,$2,1         	 # Set Zero
17799		 or    $20,$0,$16      	 # Copy Carry to X
17800		 lw    $25,0x90($21)
17801		 sw    $15,m68k_ICount
17802		 or    $5,$0,$2
17803		 or    $4,$0,$14
17804		 jalr  $25
17805		 sw    $23,0x4C($21)    	 # Delay slot
17806		 lw    $15,m68k_ICount
17807		 addiu $15,$15,-30
17808		 bgez  $15,3f
17809		 lhu   $24,0x00($23)    	 # Delay slot
17810		 j     MainExit
17811	3:
17812		 sll   $7,$24,2         	 # Delay slot
17813		 addu  $7,$7,$30
17814		 lw    $7,0x00($7)
17815		 jr    $7
17816		 nop                    	 # Delay slot
17817
17818OP0_04a8:				#:
17819		 addiu $23,$23,2
17820
17821		 andi  $24,$24,0x07
17822		 lhu   $8,0x00($23)
17823		 lhu   $25,0x02($23)
17824		 sll   $8,$8,16
17825		 or    $8,$8,$25
17826		 addiu $23,$23,4
17827		 lh    $7,0x00($23)
17828		 sll   $24,$24,2
17829		 addu  $24,$24,$21
17830		 lw    $14,0x20($24)
17831		 addiu $23,$23,2
17832		 addu  $14,$14,$7
17833		 lw    $25,0x84($21)
17834		 sw    $15,m68k_ICount
17835		 sw    $8,0x44($29)
17836		 sw    $14,0x40($29)
17837		 or    $4,$0,$14
17838		 jalr  $25
17839		 sw    $23,0x4C($21)    	 # Delay slot
17840		 lw    $14,0x40($29)
17841		 lw    $8,0x44($29)
17842		 lw    $15,m68k_ICount
17843		 or    $9,$0,$2
17844		 subu  $2,$9,$8
17845		 sltu  $16,$9,$8       	 # Set Carry
17846		 xor   $17,$9,$8
17847		 xor   $25,$2,$9
17848		 and   $17,$17,$25
17849		 srl   $17,$17,31        	 # Set Overflow
17850		 slt   $19,$2,$0        	 # Set Sign
17851		 sltiu $18,$2,1         	 # Set Zero
17852		 or    $20,$0,$16      	 # Copy Carry to X
17853		 lw    $25,0x90($21)
17854		 sw    $15,m68k_ICount
17855		 or    $5,$0,$2
17856		 or    $4,$0,$14
17857		 jalr  $25
17858		 sw    $23,0x4C($21)    	 # Delay slot
17859		 lw    $15,m68k_ICount
17860		 addiu $15,$15,-32
17861		 bgez  $15,3f
17862		 lhu   $24,0x00($23)    	 # Delay slot
17863		 j     MainExit
17864	3:
17865		 sll   $7,$24,2         	 # Delay slot
17866		 addu  $7,$7,$30
17867		 lw    $7,0x00($7)
17868		 jr    $7
17869		 nop                    	 # Delay slot
17870
17871OP0_04b0:				#:
17872		 addiu $23,$23,2
17873
17874		 andi  $24,$24,0x07
17875		 lhu   $8,0x00($23)
17876		 lhu   $25,0x02($23)
17877		 sll   $8,$8,16
17878		 or    $8,$8,$25
17879		 addiu $23,$23,4
17880		 sll   $24,$24,2
17881		 addu  $24,$24,$21
17882		 lw    $14,0x20($24)
17883		 lhu   $7,0x00($23)
17884		 addiu $23,$23,2
17885		 seb   $6,$7
17886		 or    $25,$0,$7
17887		 srl   $7,$7,12
17888		 andi  $25,$25,0x0800
17889		 sll   $7,$7,2
17890		 addu  $7,$7,$21
17891		 bne   $25,$0,0f
17892		 lw    $25,0x00($7)      	 # Delay slot
17893		 seh   $25,$25
17894	0:
17895		 addu  $25,$14,$25
17896		 addu  $14,$25,$6
17897		 lw    $25,0x84($21)
17898		 sw    $15,m68k_ICount
17899		 sw    $8,0x44($29)
17900		 sw    $14,0x40($29)
17901		 or    $4,$0,$14
17902		 jalr  $25
17903		 sw    $23,0x4C($21)    	 # Delay slot
17904		 lw    $14,0x40($29)
17905		 lw    $8,0x44($29)
17906		 lw    $15,m68k_ICount
17907		 or    $9,$0,$2
17908		 subu  $2,$9,$8
17909		 sltu  $16,$9,$8       	 # Set Carry
17910		 xor   $17,$9,$8
17911		 xor   $25,$2,$9
17912		 and   $17,$17,$25
17913		 srl   $17,$17,31        	 # Set Overflow
17914		 slt   $19,$2,$0        	 # Set Sign
17915		 sltiu $18,$2,1         	 # Set Zero
17916		 or    $20,$0,$16      	 # Copy Carry to X
17917		 lw    $25,0x90($21)
17918		 sw    $15,m68k_ICount
17919		 or    $5,$0,$2
17920		 or    $4,$0,$14
17921		 jalr  $25
17922		 sw    $23,0x4C($21)    	 # Delay slot
17923		 lw    $15,m68k_ICount
17924		 addiu $15,$15,-34
17925		 bgez  $15,3f
17926		 lhu   $24,0x00($23)    	 # Delay slot
17927		 j     MainExit
17928	3:
17929		 sll   $7,$24,2         	 # Delay slot
17930		 addu  $7,$7,$30
17931		 lw    $7,0x00($7)
17932		 jr    $7
17933		 nop                    	 # Delay slot
17934
17935OP0_04b8:				#:
17936		 addiu $23,$23,2
17937
17938		 lhu   $8,0x00($23)
17939		 lhu   $25,0x02($23)
17940		 sll   $8,$8,16
17941		 or    $8,$8,$25
17942		 addiu $23,$23,4
17943		 lh    $14,0x00($23)
17944		 addiu $23,$23,2
17945		 lw    $25,0x84($21)
17946		 sw    $15,m68k_ICount
17947		 sw    $8,0x44($29)
17948		 sw    $14,0x40($29)
17949		 or    $4,$0,$14
17950		 jalr  $25
17951		 sw    $23,0x4C($21)    	 # Delay slot
17952		 lw    $14,0x40($29)
17953		 lw    $8,0x44($29)
17954		 lw    $15,m68k_ICount
17955		 or    $9,$0,$2
17956		 subu  $2,$9,$8
17957		 sltu  $16,$9,$8       	 # Set Carry
17958		 xor   $17,$9,$8
17959		 xor   $25,$2,$9
17960		 and   $17,$17,$25
17961		 srl   $17,$17,31        	 # Set Overflow
17962		 slt   $19,$2,$0        	 # Set Sign
17963		 sltiu $18,$2,1         	 # Set Zero
17964		 or    $20,$0,$16      	 # Copy Carry to X
17965		 lw    $25,0x90($21)
17966		 sw    $15,m68k_ICount
17967		 or    $5,$0,$2
17968		 or    $4,$0,$14
17969		 jalr  $25
17970		 sw    $23,0x4C($21)    	 # Delay slot
17971		 lw    $15,m68k_ICount
17972		 addiu $15,$15,-32
17973		 bgez  $15,3f
17974		 lhu   $24,0x00($23)    	 # Delay slot
17975		 j     MainExit
17976	3:
17977		 sll   $7,$24,2         	 # Delay slot
17978		 addu  $7,$7,$30
17979		 lw    $7,0x00($7)
17980		 jr    $7
17981		 nop                    	 # Delay slot
17982
17983OP0_04b9:				#:
17984		 addiu $23,$23,2
17985
17986		 lhu   $8,0x00($23)
17987		 lhu   $25,0x02($23)
17988		 sll   $8,$8,16
17989		 or    $8,$8,$25
17990		 addiu $23,$23,4
17991		 lhu   $14,0x00($23)
17992		 lhu   $25,0x02($23)
17993		 sll   $14,$14,16
17994		 or    $14,$14,$25
17995		 addiu $23,$23,4
17996		 lw    $25,0x84($21)
17997		 sw    $15,m68k_ICount
17998		 sw    $8,0x44($29)
17999		 sw    $14,0x40($29)
18000		 or    $4,$0,$14
18001		 jalr  $25
18002		 sw    $23,0x4C($21)    	 # Delay slot
18003		 lw    $14,0x40($29)
18004		 lw    $8,0x44($29)
18005		 lw    $15,m68k_ICount
18006		 or    $9,$0,$2
18007		 subu  $2,$9,$8
18008		 sltu  $16,$9,$8       	 # Set Carry
18009		 xor   $17,$9,$8
18010		 xor   $25,$2,$9
18011		 and   $17,$17,$25
18012		 srl   $17,$17,31        	 # Set Overflow
18013		 slt   $19,$2,$0        	 # Set Sign
18014		 sltiu $18,$2,1         	 # Set Zero
18015		 or    $20,$0,$16      	 # Copy Carry to X
18016		 lw    $25,0x90($21)
18017		 sw    $15,m68k_ICount
18018		 or    $5,$0,$2
18019		 or    $4,$0,$14
18020		 jalr  $25
18021		 sw    $23,0x4C($21)    	 # Delay slot
18022		 lw    $15,m68k_ICount
18023		 addiu $15,$15,-36
18024		 bgez  $15,3f
18025		 lhu   $24,0x00($23)    	 # Delay slot
18026		 j     MainExit
18027	3:
18028		 sll   $7,$24,2         	 # Delay slot
18029		 addu  $7,$7,$30
18030		 lw    $7,0x00($7)
18031		 jr    $7
18032		 nop                    	 # Delay slot
18033
18034OP0_0600:				#:
18035		 addiu $23,$23,2
18036
18037		 andi  $24,$24,0x07
18038		 lb    $8,0x00($23)
18039		 addiu $23,$23,2
18040		 sll   $24,$24,2
18041		 addu  $24,$24,$21
18042		 lb    $9,0x00($24)
18043		 addu  $2,$9,$8
18044		 sltu  $16,$2,$8       	 # Set Carry
18045		 xor   $17,$9,$8
18046		 nor   $17,$0,$17
18047		 xor   $25,$2,$9
18048		 and   $17,$17,$25
18049		 srl   $17,$17,7
18050		 andi  $17,$17,0x01     	 # Set Overflow
18051		 seb  $25,$2
18052		 slt   $19,$25,$0        	 # Set Sign
18053		 sltiu $18,$25,1         	 # Set Zero
18054		 or    $20,$0,$16      	 # Copy Carry to X
18055		 sb    $2,0x00($24)
18056		 addiu $15,$15,-8
18057		 bgez  $15,3f
18058		 lhu   $24,0x00($23)    	 # Delay slot
18059		 j     MainExit
18060	3:
18061		 sll   $7,$24,2         	 # Delay slot
18062		 addu  $7,$7,$30
18063		 lw    $7,0x00($7)
18064		 jr    $7
18065		 nop                    	 # Delay slot
18066
18067OP0_0610:				#:
18068		 addiu $23,$23,2
18069
18070		 andi  $24,$24,0x07
18071		 lb    $8,0x00($23)
18072		 addiu $23,$23,2
18073		 sll   $24,$24,2
18074		 addu  $24,$24,$21
18075		 lw    $14,0x20($24)
18076		 lw    $25,0x7C($21)
18077		 sw    $15,m68k_ICount
18078		 sw    $8,0x44($29)
18079		 sw    $14,0x40($29)
18080		 or    $4,$0,$14
18081		 jalr  $25
18082		 sw    $23,0x4C($21)    	 # Delay slot
18083		 lw    $14,0x40($29)
18084		 lw    $8,0x44($29)
18085		 lw    $15,m68k_ICount
18086		 seb   $9,$2
18087		 addu  $2,$9,$8
18088		 sltu  $16,$2,$8       	 # Set Carry
18089		 xor   $17,$9,$8
18090		 nor   $17,$0,$17
18091		 xor   $25,$2,$9
18092		 and   $17,$17,$25
18093		 srl   $17,$17,7
18094		 andi  $17,$17,0x01     	 # Set Overflow
18095		 seb  $25,$2
18096		 slt   $19,$25,$0        	 # Set Sign
18097		 sltiu $18,$25,1         	 # Set Zero
18098		 or    $20,$0,$16      	 # Copy Carry to X
18099		 lw    $25,0x88($21)
18100		 sw    $15,m68k_ICount
18101		 or    $5,$0,$2
18102		 or    $4,$0,$14
18103		 jalr  $25
18104		 sw    $23,0x4C($21)    	 # Delay slot
18105		 lw    $15,m68k_ICount
18106		 addiu $15,$15,-16
18107		 bgez  $15,3f
18108		 lhu   $24,0x00($23)    	 # Delay slot
18109		 j     MainExit
18110	3:
18111		 sll   $7,$24,2         	 # Delay slot
18112		 addu  $7,$7,$30
18113		 lw    $7,0x00($7)
18114		 jr    $7
18115		 nop                    	 # Delay slot
18116
18117OP0_0618:				#:
18118		 addiu $23,$23,2
18119
18120		 andi  $24,$24,0x07
18121		 lb    $8,0x00($23)
18122		 addiu $23,$23,2
18123		 sll   $24,$24,2
18124		 addu  $24,$24,$21
18125		 lw    $14,0x20($24)
18126		 addiu $25,$14,1
18127		 sw    $25,0x20($24)
18128		 lw    $25,0x7C($21)
18129		 sw    $15,m68k_ICount
18130		 sw    $8,0x44($29)
18131		 sw    $14,0x40($29)
18132		 or    $4,$0,$14
18133		 jalr  $25
18134		 sw    $23,0x4C($21)    	 # Delay slot
18135		 lw    $14,0x40($29)
18136		 lw    $8,0x44($29)
18137		 lw    $15,m68k_ICount
18138		 seb   $9,$2
18139		 addu  $2,$9,$8
18140		 sltu  $16,$2,$8       	 # Set Carry
18141		 xor   $17,$9,$8
18142		 nor   $17,$0,$17
18143		 xor   $25,$2,$9
18144		 and   $17,$17,$25
18145		 srl   $17,$17,7
18146		 andi  $17,$17,0x01     	 # Set Overflow
18147		 seb  $25,$2
18148		 slt   $19,$25,$0        	 # Set Sign
18149		 sltiu $18,$25,1         	 # Set Zero
18150		 or    $20,$0,$16      	 # Copy Carry to X
18151		 lw    $25,0x88($21)
18152		 sw    $15,m68k_ICount
18153		 or    $5,$0,$2
18154		 or    $4,$0,$14
18155		 jalr  $25
18156		 sw    $23,0x4C($21)    	 # Delay slot
18157		 lw    $15,m68k_ICount
18158		 addiu $15,$15,-16
18159		 bgez  $15,3f
18160		 lhu   $24,0x00($23)    	 # Delay slot
18161		 j     MainExit
18162	3:
18163		 sll   $7,$24,2         	 # Delay slot
18164		 addu  $7,$7,$30
18165		 lw    $7,0x00($7)
18166		 jr    $7
18167		 nop                    	 # Delay slot
18168
18169OP0_061f:				#:
18170		 addiu $23,$23,2
18171
18172		 lb    $8,0x00($23)
18173		 addiu $23,$23,2
18174		 lw    $14,0x3C($21)    	 # Get A7
18175		 addiu $25,$14,2
18176		 sw    $25,0x3C($21)
18177		 lw    $25,0x7C($21)
18178		 sw    $15,m68k_ICount
18179		 sw    $8,0x44($29)
18180		 sw    $14,0x40($29)
18181		 or    $4,$0,$14
18182		 jalr  $25
18183		 sw    $23,0x4C($21)    	 # Delay slot
18184		 lw    $14,0x40($29)
18185		 lw    $8,0x44($29)
18186		 lw    $15,m68k_ICount
18187		 seb   $9,$2
18188		 addu  $2,$9,$8
18189		 sltu  $16,$2,$8       	 # Set Carry
18190		 xor   $17,$9,$8
18191		 nor   $17,$0,$17
18192		 xor   $25,$2,$9
18193		 and   $17,$17,$25
18194		 srl   $17,$17,7
18195		 andi  $17,$17,0x01     	 # Set Overflow
18196		 seb  $25,$2
18197		 slt   $19,$25,$0        	 # Set Sign
18198		 sltiu $18,$25,1         	 # Set Zero
18199		 or    $20,$0,$16      	 # Copy Carry to X
18200		 lw    $25,0x88($21)
18201		 sw    $15,m68k_ICount
18202		 or    $5,$0,$2
18203		 or    $4,$0,$14
18204		 jalr  $25
18205		 sw    $23,0x4C($21)    	 # Delay slot
18206		 lw    $15,m68k_ICount
18207		 addiu $15,$15,-16
18208		 bgez  $15,3f
18209		 lhu   $24,0x00($23)    	 # Delay slot
18210		 j     MainExit
18211	3:
18212		 sll   $7,$24,2         	 # Delay slot
18213		 addu  $7,$7,$30
18214		 lw    $7,0x00($7)
18215		 jr    $7
18216		 nop                    	 # Delay slot
18217
18218OP0_0620:				#:
18219		 addiu $23,$23,2
18220
18221		 andi  $24,$24,0x07
18222		 lb    $8,0x00($23)
18223		 addiu $23,$23,2
18224		 sll   $24,$24,2
18225		 addu  $24,$24,$21
18226		 lw    $14,0x20($24)
18227		 addiu $14,$14,-1
18228		 sw    $14,0x20($24)
18229		 lw    $25,0x7C($21)
18230		 sw    $15,m68k_ICount
18231		 sw    $8,0x44($29)
18232		 sw    $14,0x40($29)
18233		 or    $4,$0,$14
18234		 jalr  $25
18235		 sw    $23,0x4C($21)    	 # Delay slot
18236		 lw    $14,0x40($29)
18237		 lw    $8,0x44($29)
18238		 lw    $15,m68k_ICount
18239		 seb   $9,$2
18240		 addu  $2,$9,$8
18241		 sltu  $16,$2,$8       	 # Set Carry
18242		 xor   $17,$9,$8
18243		 nor   $17,$0,$17
18244		 xor   $25,$2,$9
18245		 and   $17,$17,$25
18246		 srl   $17,$17,7
18247		 andi  $17,$17,0x01     	 # Set Overflow
18248		 seb  $25,$2
18249		 slt   $19,$25,$0        	 # Set Sign
18250		 sltiu $18,$25,1         	 # Set Zero
18251		 or    $20,$0,$16      	 # Copy Carry to X
18252		 lw    $25,0x88($21)
18253		 sw    $15,m68k_ICount
18254		 or    $5,$0,$2
18255		 or    $4,$0,$14
18256		 jalr  $25
18257		 sw    $23,0x4C($21)    	 # Delay slot
18258		 lw    $15,m68k_ICount
18259		 addiu $15,$15,-18
18260		 bgez  $15,3f
18261		 lhu   $24,0x00($23)    	 # Delay slot
18262		 j     MainExit
18263	3:
18264		 sll   $7,$24,2         	 # Delay slot
18265		 addu  $7,$7,$30
18266		 lw    $7,0x00($7)
18267		 jr    $7
18268		 nop                    	 # Delay slot
18269
18270OP0_0627:				#:
18271		 addiu $23,$23,2
18272
18273		 lb    $8,0x00($23)
18274		 addiu $23,$23,2
18275		 lw    $14,0x3C($21)    	 # Get A7
18276		 addiu $14,$14,-2
18277		 sw    $14,0x3C($21)
18278		 lw    $25,0x7C($21)
18279		 sw    $15,m68k_ICount
18280		 sw    $8,0x44($29)
18281		 sw    $14,0x40($29)
18282		 or    $4,$0,$14
18283		 jalr  $25
18284		 sw    $23,0x4C($21)    	 # Delay slot
18285		 lw    $14,0x40($29)
18286		 lw    $8,0x44($29)
18287		 lw    $15,m68k_ICount
18288		 seb   $9,$2
18289		 addu  $2,$9,$8
18290		 sltu  $16,$2,$8       	 # Set Carry
18291		 xor   $17,$9,$8
18292		 nor   $17,$0,$17
18293		 xor   $25,$2,$9
18294		 and   $17,$17,$25
18295		 srl   $17,$17,7
18296		 andi  $17,$17,0x01     	 # Set Overflow
18297		 seb  $25,$2
18298		 slt   $19,$25,$0        	 # Set Sign
18299		 sltiu $18,$25,1         	 # Set Zero
18300		 or    $20,$0,$16      	 # Copy Carry to X
18301		 lw    $25,0x88($21)
18302		 sw    $15,m68k_ICount
18303		 or    $5,$0,$2
18304		 or    $4,$0,$14
18305		 jalr  $25
18306		 sw    $23,0x4C($21)    	 # Delay slot
18307		 lw    $15,m68k_ICount
18308		 addiu $15,$15,-18
18309		 bgez  $15,3f
18310		 lhu   $24,0x00($23)    	 # Delay slot
18311		 j     MainExit
18312	3:
18313		 sll   $7,$24,2         	 # Delay slot
18314		 addu  $7,$7,$30
18315		 lw    $7,0x00($7)
18316		 jr    $7
18317		 nop                    	 # Delay slot
18318
18319OP0_0628:				#:
18320		 addiu $23,$23,2
18321
18322		 andi  $24,$24,0x07
18323		 lb    $8,0x00($23)
18324		 addiu $23,$23,2
18325		 lh    $7,0x00($23)
18326		 sll   $24,$24,2
18327		 addu  $24,$24,$21
18328		 lw    $14,0x20($24)
18329		 addiu $23,$23,2
18330		 addu  $14,$14,$7
18331		 lw    $25,0x7C($21)
18332		 sw    $15,m68k_ICount
18333		 sw    $8,0x44($29)
18334		 sw    $14,0x40($29)
18335		 or    $4,$0,$14
18336		 jalr  $25
18337		 sw    $23,0x4C($21)    	 # Delay slot
18338		 lw    $14,0x40($29)
18339		 lw    $8,0x44($29)
18340		 lw    $15,m68k_ICount
18341		 seb   $9,$2
18342		 addu  $2,$9,$8
18343		 sltu  $16,$2,$8       	 # Set Carry
18344		 xor   $17,$9,$8
18345		 nor   $17,$0,$17
18346		 xor   $25,$2,$9
18347		 and   $17,$17,$25
18348		 srl   $17,$17,7
18349		 andi  $17,$17,0x01     	 # Set Overflow
18350		 seb  $25,$2
18351		 slt   $19,$25,$0        	 # Set Sign
18352		 sltiu $18,$25,1         	 # Set Zero
18353		 or    $20,$0,$16      	 # Copy Carry to X
18354		 lw    $25,0x88($21)
18355		 sw    $15,m68k_ICount
18356		 or    $5,$0,$2
18357		 or    $4,$0,$14
18358		 jalr  $25
18359		 sw    $23,0x4C($21)    	 # Delay slot
18360		 lw    $15,m68k_ICount
18361		 addiu $15,$15,-20
18362		 bgez  $15,3f
18363		 lhu   $24,0x00($23)    	 # Delay slot
18364		 j     MainExit
18365	3:
18366		 sll   $7,$24,2         	 # Delay slot
18367		 addu  $7,$7,$30
18368		 lw    $7,0x00($7)
18369		 jr    $7
18370		 nop                    	 # Delay slot
18371
18372OP0_0630:				#:
18373		 addiu $23,$23,2
18374
18375		 andi  $24,$24,0x07
18376		 lb    $8,0x00($23)
18377		 addiu $23,$23,2
18378		 sll   $24,$24,2
18379		 addu  $24,$24,$21
18380		 lw    $14,0x20($24)
18381		 lhu   $7,0x00($23)
18382		 addiu $23,$23,2
18383		 seb   $6,$7
18384		 or    $25,$0,$7
18385		 srl   $7,$7,12
18386		 andi  $25,$25,0x0800
18387		 sll   $7,$7,2
18388		 addu  $7,$7,$21
18389		 bne   $25,$0,0f
18390		 lw    $25,0x00($7)      	 # Delay slot
18391		 seh   $25,$25
18392	0:
18393		 addu  $25,$14,$25
18394		 addu  $14,$25,$6
18395		 lw    $25,0x7C($21)
18396		 sw    $15,m68k_ICount
18397		 sw    $8,0x44($29)
18398		 sw    $14,0x40($29)
18399		 or    $4,$0,$14
18400		 jalr  $25
18401		 sw    $23,0x4C($21)    	 # Delay slot
18402		 lw    $14,0x40($29)
18403		 lw    $8,0x44($29)
18404		 lw    $15,m68k_ICount
18405		 seb   $9,$2
18406		 addu  $2,$9,$8
18407		 sltu  $16,$2,$8       	 # Set Carry
18408		 xor   $17,$9,$8
18409		 nor   $17,$0,$17
18410		 xor   $25,$2,$9
18411		 and   $17,$17,$25
18412		 srl   $17,$17,7
18413		 andi  $17,$17,0x01     	 # Set Overflow
18414		 seb  $25,$2
18415		 slt   $19,$25,$0        	 # Set Sign
18416		 sltiu $18,$25,1         	 # Set Zero
18417		 or    $20,$0,$16      	 # Copy Carry to X
18418		 lw    $25,0x88($21)
18419		 sw    $15,m68k_ICount
18420		 or    $5,$0,$2
18421		 or    $4,$0,$14
18422		 jalr  $25
18423		 sw    $23,0x4C($21)    	 # Delay slot
18424		 lw    $15,m68k_ICount
18425		 addiu $15,$15,-22
18426		 bgez  $15,3f
18427		 lhu   $24,0x00($23)    	 # Delay slot
18428		 j     MainExit
18429	3:
18430		 sll   $7,$24,2         	 # Delay slot
18431		 addu  $7,$7,$30
18432		 lw    $7,0x00($7)
18433		 jr    $7
18434		 nop                    	 # Delay slot
18435
18436OP0_0638:				#:
18437		 addiu $23,$23,2
18438
18439		 lb    $8,0x00($23)
18440		 addiu $23,$23,2
18441		 lh    $14,0x00($23)
18442		 addiu $23,$23,2
18443		 lw    $25,0x7C($21)
18444		 sw    $15,m68k_ICount
18445		 sw    $8,0x44($29)
18446		 sw    $14,0x40($29)
18447		 or    $4,$0,$14
18448		 jalr  $25
18449		 sw    $23,0x4C($21)    	 # Delay slot
18450		 lw    $14,0x40($29)
18451		 lw    $8,0x44($29)
18452		 lw    $15,m68k_ICount
18453		 seb   $9,$2
18454		 addu  $2,$9,$8
18455		 sltu  $16,$2,$8       	 # Set Carry
18456		 xor   $17,$9,$8
18457		 nor   $17,$0,$17
18458		 xor   $25,$2,$9
18459		 and   $17,$17,$25
18460		 srl   $17,$17,7
18461		 andi  $17,$17,0x01     	 # Set Overflow
18462		 seb  $25,$2
18463		 slt   $19,$25,$0        	 # Set Sign
18464		 sltiu $18,$25,1         	 # Set Zero
18465		 or    $20,$0,$16      	 # Copy Carry to X
18466		 lw    $25,0x88($21)
18467		 sw    $15,m68k_ICount
18468		 or    $5,$0,$2
18469		 or    $4,$0,$14
18470		 jalr  $25
18471		 sw    $23,0x4C($21)    	 # Delay slot
18472		 lw    $15,m68k_ICount
18473		 addiu $15,$15,-20
18474		 bgez  $15,3f
18475		 lhu   $24,0x00($23)    	 # Delay slot
18476		 j     MainExit
18477	3:
18478		 sll   $7,$24,2         	 # Delay slot
18479		 addu  $7,$7,$30
18480		 lw    $7,0x00($7)
18481		 jr    $7
18482		 nop                    	 # Delay slot
18483
18484OP0_0639:				#:
18485		 addiu $23,$23,2
18486
18487		 lb    $8,0x00($23)
18488		 addiu $23,$23,2
18489		 lhu   $14,0x00($23)
18490		 lhu   $25,0x02($23)
18491		 sll   $14,$14,16
18492		 or    $14,$14,$25
18493		 addiu $23,$23,4
18494		 lw    $25,0x7C($21)
18495		 sw    $15,m68k_ICount
18496		 sw    $8,0x44($29)
18497		 sw    $14,0x40($29)
18498		 or    $4,$0,$14
18499		 jalr  $25
18500		 sw    $23,0x4C($21)    	 # Delay slot
18501		 lw    $14,0x40($29)
18502		 lw    $8,0x44($29)
18503		 lw    $15,m68k_ICount
18504		 seb   $9,$2
18505		 addu  $2,$9,$8
18506		 sltu  $16,$2,$8       	 # Set Carry
18507		 xor   $17,$9,$8
18508		 nor   $17,$0,$17
18509		 xor   $25,$2,$9
18510		 and   $17,$17,$25
18511		 srl   $17,$17,7
18512		 andi  $17,$17,0x01     	 # Set Overflow
18513		 seb  $25,$2
18514		 slt   $19,$25,$0        	 # Set Sign
18515		 sltiu $18,$25,1         	 # Set Zero
18516		 or    $20,$0,$16      	 # Copy Carry to X
18517		 lw    $25,0x88($21)
18518		 sw    $15,m68k_ICount
18519		 or    $5,$0,$2
18520		 or    $4,$0,$14
18521		 jalr  $25
18522		 sw    $23,0x4C($21)    	 # Delay slot
18523		 lw    $15,m68k_ICount
18524		 addiu $15,$15,-24
18525		 bgez  $15,3f
18526		 lhu   $24,0x00($23)    	 # Delay slot
18527		 j     MainExit
18528	3:
18529		 sll   $7,$24,2         	 # Delay slot
18530		 addu  $7,$7,$30
18531		 lw    $7,0x00($7)
18532		 jr    $7
18533		 nop                    	 # Delay slot
18534
18535OP0_0640:				#:
18536		 addiu $23,$23,2
18537
18538		 andi  $24,$24,0x07
18539		 lh    $8,0x00($23)
18540		 addiu $23,$23,2
18541		 sll   $24,$24,2
18542		 addu  $24,$24,$21
18543		 lh    $9,0x00($24)
18544		 addu  $2,$9,$8
18545		 sltu  $16,$2,$8       	 # Set Carry
18546		 xor   $17,$9,$8
18547		 nor   $17,$0,$17
18548		 xor   $25,$2,$9
18549		 and   $17,$17,$25
18550		 srl   $17,$17,15
18551		 andi  $17,$17,0x01     	 # Set Overflow
18552		 seh  $25,$2
18553		 slt   $19,$25,$0        	 # Set Sign
18554		 sltiu $18,$25,1         	 # Set Zero
18555		 or    $20,$0,$16      	 # Copy Carry to X
18556		 sh    $2,0x00($24)
18557		 addiu $15,$15,-8
18558		 bgez  $15,3f
18559		 lhu   $24,0x00($23)    	 # Delay slot
18560		 j     MainExit
18561	3:
18562		 sll   $7,$24,2         	 # Delay slot
18563		 addu  $7,$7,$30
18564		 lw    $7,0x00($7)
18565		 jr    $7
18566		 nop                    	 # Delay slot
18567
18568OP0_0650:				#:
18569		 addiu $23,$23,2
18570
18571		 andi  $24,$24,0x07
18572		 lh    $8,0x00($23)
18573		 addiu $23,$23,2
18574		 sll   $24,$24,2
18575		 addu  $24,$24,$21
18576		 lw    $14,0x20($24)
18577		 lw    $25,0x80($21)
18578		 sw    $15,m68k_ICount
18579		 sw    $8,0x44($29)
18580		 sw    $14,0x40($29)
18581		 or    $4,$0,$14
18582		 jalr  $25
18583		 sw    $23,0x4C($21)    	 # Delay slot
18584		 lw    $14,0x40($29)
18585		 lw    $8,0x44($29)
18586		 lw    $15,m68k_ICount
18587		 seh   $9,$2
18588		 addu  $2,$9,$8
18589		 sltu  $16,$2,$8       	 # Set Carry
18590		 xor   $17,$9,$8
18591		 nor   $17,$0,$17
18592		 xor   $25,$2,$9
18593		 and   $17,$17,$25
18594		 srl   $17,$17,15
18595		 andi  $17,$17,0x01     	 # Set Overflow
18596		 seh  $25,$2
18597		 slt   $19,$25,$0        	 # Set Sign
18598		 sltiu $18,$25,1         	 # Set Zero
18599		 or    $20,$0,$16      	 # Copy Carry to X
18600		 lw    $25,0x8C($21)
18601		 sw    $15,m68k_ICount
18602		 or    $5,$0,$2
18603		 or    $4,$0,$14
18604		 jalr  $25
18605		 sw    $23,0x4C($21)    	 # Delay slot
18606		 lw    $15,m68k_ICount
18607		 addiu $15,$15,-16
18608		 bgez  $15,3f
18609		 lhu   $24,0x00($23)    	 # Delay slot
18610		 j     MainExit
18611	3:
18612		 sll   $7,$24,2         	 # Delay slot
18613		 addu  $7,$7,$30
18614		 lw    $7,0x00($7)
18615		 jr    $7
18616		 nop                    	 # Delay slot
18617
18618OP0_0658:				#:
18619		 addiu $23,$23,2
18620
18621		 andi  $24,$24,0x07
18622		 lh    $8,0x00($23)
18623		 addiu $23,$23,2
18624		 sll   $24,$24,2
18625		 addu  $24,$24,$21
18626		 lw    $14,0x20($24)
18627		 addiu $25,$14,2
18628		 sw    $25,0x20($24)
18629		 lw    $25,0x80($21)
18630		 sw    $15,m68k_ICount
18631		 sw    $8,0x44($29)
18632		 sw    $14,0x40($29)
18633		 or    $4,$0,$14
18634		 jalr  $25
18635		 sw    $23,0x4C($21)    	 # Delay slot
18636		 lw    $14,0x40($29)
18637		 lw    $8,0x44($29)
18638		 lw    $15,m68k_ICount
18639		 seh   $9,$2
18640		 addu  $2,$9,$8
18641		 sltu  $16,$2,$8       	 # Set Carry
18642		 xor   $17,$9,$8
18643		 nor   $17,$0,$17
18644		 xor   $25,$2,$9
18645		 and   $17,$17,$25
18646		 srl   $17,$17,15
18647		 andi  $17,$17,0x01     	 # Set Overflow
18648		 seh  $25,$2
18649		 slt   $19,$25,$0        	 # Set Sign
18650		 sltiu $18,$25,1         	 # Set Zero
18651		 or    $20,$0,$16      	 # Copy Carry to X
18652		 lw    $25,0x8C($21)
18653		 sw    $15,m68k_ICount
18654		 or    $5,$0,$2
18655		 or    $4,$0,$14
18656		 jalr  $25
18657		 sw    $23,0x4C($21)    	 # Delay slot
18658		 lw    $15,m68k_ICount
18659		 addiu $15,$15,-16
18660		 bgez  $15,3f
18661		 lhu   $24,0x00($23)    	 # Delay slot
18662		 j     MainExit
18663	3:
18664		 sll   $7,$24,2         	 # Delay slot
18665		 addu  $7,$7,$30
18666		 lw    $7,0x00($7)
18667		 jr    $7
18668		 nop                    	 # Delay slot
18669
18670OP0_0660:				#:
18671		 addiu $23,$23,2
18672
18673		 andi  $24,$24,0x07
18674		 lh    $8,0x00($23)
18675		 addiu $23,$23,2
18676		 sll   $24,$24,2
18677		 addu  $24,$24,$21
18678		 lw    $14,0x20($24)
18679		 addiu $14,$14,-2
18680		 sw    $14,0x20($24)
18681		 lw    $25,0x80($21)
18682		 sw    $15,m68k_ICount
18683		 sw    $8,0x44($29)
18684		 sw    $14,0x40($29)
18685		 or    $4,$0,$14
18686		 jalr  $25
18687		 sw    $23,0x4C($21)    	 # Delay slot
18688		 lw    $14,0x40($29)
18689		 lw    $8,0x44($29)
18690		 lw    $15,m68k_ICount
18691		 seh   $9,$2
18692		 addu  $2,$9,$8
18693		 sltu  $16,$2,$8       	 # Set Carry
18694		 xor   $17,$9,$8
18695		 nor   $17,$0,$17
18696		 xor   $25,$2,$9
18697		 and   $17,$17,$25
18698		 srl   $17,$17,15
18699		 andi  $17,$17,0x01     	 # Set Overflow
18700		 seh  $25,$2
18701		 slt   $19,$25,$0        	 # Set Sign
18702		 sltiu $18,$25,1         	 # Set Zero
18703		 or    $20,$0,$16      	 # Copy Carry to X
18704		 lw    $25,0x8C($21)
18705		 sw    $15,m68k_ICount
18706		 or    $5,$0,$2
18707		 or    $4,$0,$14
18708		 jalr  $25
18709		 sw    $23,0x4C($21)    	 # Delay slot
18710		 lw    $15,m68k_ICount
18711		 addiu $15,$15,-18
18712		 bgez  $15,3f
18713		 lhu   $24,0x00($23)    	 # Delay slot
18714		 j     MainExit
18715	3:
18716		 sll   $7,$24,2         	 # Delay slot
18717		 addu  $7,$7,$30
18718		 lw    $7,0x00($7)
18719		 jr    $7
18720		 nop                    	 # Delay slot
18721
18722OP0_0668:				#:
18723		 addiu $23,$23,2
18724
18725		 andi  $24,$24,0x07
18726		 lh    $8,0x00($23)
18727		 addiu $23,$23,2
18728		 lh    $7,0x00($23)
18729		 sll   $24,$24,2
18730		 addu  $24,$24,$21
18731		 lw    $14,0x20($24)
18732		 addiu $23,$23,2
18733		 addu  $14,$14,$7
18734		 lw    $25,0x80($21)
18735		 sw    $15,m68k_ICount
18736		 sw    $8,0x44($29)
18737		 sw    $14,0x40($29)
18738		 or    $4,$0,$14
18739		 jalr  $25
18740		 sw    $23,0x4C($21)    	 # Delay slot
18741		 lw    $14,0x40($29)
18742		 lw    $8,0x44($29)
18743		 lw    $15,m68k_ICount
18744		 seh   $9,$2
18745		 addu  $2,$9,$8
18746		 sltu  $16,$2,$8       	 # Set Carry
18747		 xor   $17,$9,$8
18748		 nor   $17,$0,$17
18749		 xor   $25,$2,$9
18750		 and   $17,$17,$25
18751		 srl   $17,$17,15
18752		 andi  $17,$17,0x01     	 # Set Overflow
18753		 seh  $25,$2
18754		 slt   $19,$25,$0        	 # Set Sign
18755		 sltiu $18,$25,1         	 # Set Zero
18756		 or    $20,$0,$16      	 # Copy Carry to X
18757		 lw    $25,0x8C($21)
18758		 sw    $15,m68k_ICount
18759		 or    $5,$0,$2
18760		 or    $4,$0,$14
18761		 jalr  $25
18762		 sw    $23,0x4C($21)    	 # Delay slot
18763		 lw    $15,m68k_ICount
18764		 addiu $15,$15,-20
18765		 bgez  $15,3f
18766		 lhu   $24,0x00($23)    	 # Delay slot
18767		 j     MainExit
18768	3:
18769		 sll   $7,$24,2         	 # Delay slot
18770		 addu  $7,$7,$30
18771		 lw    $7,0x00($7)
18772		 jr    $7
18773		 nop                    	 # Delay slot
18774
18775OP0_0670:				#:
18776		 addiu $23,$23,2
18777
18778		 andi  $24,$24,0x07
18779		 lh    $8,0x00($23)
18780		 addiu $23,$23,2
18781		 sll   $24,$24,2
18782		 addu  $24,$24,$21
18783		 lw    $14,0x20($24)
18784		 lhu   $7,0x00($23)
18785		 addiu $23,$23,2
18786		 seb   $6,$7
18787		 or    $25,$0,$7
18788		 srl   $7,$7,12
18789		 andi  $25,$25,0x0800
18790		 sll   $7,$7,2
18791		 addu  $7,$7,$21
18792		 bne   $25,$0,0f
18793		 lw    $25,0x00($7)      	 # Delay slot
18794		 seh   $25,$25
18795	0:
18796		 addu  $25,$14,$25
18797		 addu  $14,$25,$6
18798		 lw    $25,0x80($21)
18799		 sw    $15,m68k_ICount
18800		 sw    $8,0x44($29)
18801		 sw    $14,0x40($29)
18802		 or    $4,$0,$14
18803		 jalr  $25
18804		 sw    $23,0x4C($21)    	 # Delay slot
18805		 lw    $14,0x40($29)
18806		 lw    $8,0x44($29)
18807		 lw    $15,m68k_ICount
18808		 seh   $9,$2
18809		 addu  $2,$9,$8
18810		 sltu  $16,$2,$8       	 # Set Carry
18811		 xor   $17,$9,$8
18812		 nor   $17,$0,$17
18813		 xor   $25,$2,$9
18814		 and   $17,$17,$25
18815		 srl   $17,$17,15
18816		 andi  $17,$17,0x01     	 # Set Overflow
18817		 seh  $25,$2
18818		 slt   $19,$25,$0        	 # Set Sign
18819		 sltiu $18,$25,1         	 # Set Zero
18820		 or    $20,$0,$16      	 # Copy Carry to X
18821		 lw    $25,0x8C($21)
18822		 sw    $15,m68k_ICount
18823		 or    $5,$0,$2
18824		 or    $4,$0,$14
18825		 jalr  $25
18826		 sw    $23,0x4C($21)    	 # Delay slot
18827		 lw    $15,m68k_ICount
18828		 addiu $15,$15,-22
18829		 bgez  $15,3f
18830		 lhu   $24,0x00($23)    	 # Delay slot
18831		 j     MainExit
18832	3:
18833		 sll   $7,$24,2         	 # Delay slot
18834		 addu  $7,$7,$30
18835		 lw    $7,0x00($7)
18836		 jr    $7
18837		 nop                    	 # Delay slot
18838
18839OP0_0678:				#:
18840		 addiu $23,$23,2
18841
18842		 lh    $8,0x00($23)
18843		 addiu $23,$23,2
18844		 lh    $14,0x00($23)
18845		 addiu $23,$23,2
18846		 lw    $25,0x80($21)
18847		 sw    $15,m68k_ICount
18848		 sw    $8,0x44($29)
18849		 sw    $14,0x40($29)
18850		 or    $4,$0,$14
18851		 jalr  $25
18852		 sw    $23,0x4C($21)    	 # Delay slot
18853		 lw    $14,0x40($29)
18854		 lw    $8,0x44($29)
18855		 lw    $15,m68k_ICount
18856		 seh   $9,$2
18857		 addu  $2,$9,$8
18858		 sltu  $16,$2,$8       	 # Set Carry
18859		 xor   $17,$9,$8
18860		 nor   $17,$0,$17
18861		 xor   $25,$2,$9
18862		 and   $17,$17,$25
18863		 srl   $17,$17,15
18864		 andi  $17,$17,0x01     	 # Set Overflow
18865		 seh  $25,$2
18866		 slt   $19,$25,$0        	 # Set Sign
18867		 sltiu $18,$25,1         	 # Set Zero
18868		 or    $20,$0,$16      	 # Copy Carry to X
18869		 lw    $25,0x8C($21)
18870		 sw    $15,m68k_ICount
18871		 or    $5,$0,$2
18872		 or    $4,$0,$14
18873		 jalr  $25
18874		 sw    $23,0x4C($21)    	 # Delay slot
18875		 lw    $15,m68k_ICount
18876		 addiu $15,$15,-20
18877		 bgez  $15,3f
18878		 lhu   $24,0x00($23)    	 # Delay slot
18879		 j     MainExit
18880	3:
18881		 sll   $7,$24,2         	 # Delay slot
18882		 addu  $7,$7,$30
18883		 lw    $7,0x00($7)
18884		 jr    $7
18885		 nop                    	 # Delay slot
18886
18887OP0_0679:				#:
18888		 addiu $23,$23,2
18889
18890		 lh    $8,0x00($23)
18891		 addiu $23,$23,2
18892		 lhu   $14,0x00($23)
18893		 lhu   $25,0x02($23)
18894		 sll   $14,$14,16
18895		 or    $14,$14,$25
18896		 addiu $23,$23,4
18897		 lw    $25,0x80($21)
18898		 sw    $15,m68k_ICount
18899		 sw    $8,0x44($29)
18900		 sw    $14,0x40($29)
18901		 or    $4,$0,$14
18902		 jalr  $25
18903		 sw    $23,0x4C($21)    	 # Delay slot
18904		 lw    $14,0x40($29)
18905		 lw    $8,0x44($29)
18906		 lw    $15,m68k_ICount
18907		 seh   $9,$2
18908		 addu  $2,$9,$8
18909		 sltu  $16,$2,$8       	 # Set Carry
18910		 xor   $17,$9,$8
18911		 nor   $17,$0,$17
18912		 xor   $25,$2,$9
18913		 and   $17,$17,$25
18914		 srl   $17,$17,15
18915		 andi  $17,$17,0x01     	 # Set Overflow
18916		 seh  $25,$2
18917		 slt   $19,$25,$0        	 # Set Sign
18918		 sltiu $18,$25,1         	 # Set Zero
18919		 or    $20,$0,$16      	 # Copy Carry to X
18920		 lw    $25,0x8C($21)
18921		 sw    $15,m68k_ICount
18922		 or    $5,$0,$2
18923		 or    $4,$0,$14
18924		 jalr  $25
18925		 sw    $23,0x4C($21)    	 # Delay slot
18926		 lw    $15,m68k_ICount
18927		 addiu $15,$15,-24
18928		 bgez  $15,3f
18929		 lhu   $24,0x00($23)    	 # Delay slot
18930		 j     MainExit
18931	3:
18932		 sll   $7,$24,2         	 # Delay slot
18933		 addu  $7,$7,$30
18934		 lw    $7,0x00($7)
18935		 jr    $7
18936		 nop                    	 # Delay slot
18937
18938OP0_0680:				#:
18939		 addiu $23,$23,2
18940
18941		 andi  $24,$24,0x07
18942		 lhu   $8,0x00($23)
18943		 lhu   $25,0x02($23)
18944		 sll   $8,$8,16
18945		 or    $8,$8,$25
18946		 addiu $23,$23,4
18947		 sll   $24,$24,2
18948		 addu  $24,$24,$21
18949		 lw    $9,0x00($24)
18950		 addu  $2,$9,$8
18951		 sltu  $16,$2,$8       	 # Set Carry
18952		 xor   $17,$9,$8
18953		 nor   $17,$0,$17
18954		 xor   $25,$2,$9
18955		 and   $17,$17,$25
18956		 srl   $17,$17,31        	 # Set Overflow
18957		 slt   $19,$2,$0        	 # Set Sign
18958		 sltiu $18,$2,1         	 # Set Zero
18959		 or    $20,$0,$16      	 # Copy Carry to X
18960		 sw    $2,0x00($24)
18961		 addiu $15,$15,-16
18962		 bgez  $15,3f
18963		 lhu   $24,0x00($23)    	 # Delay slot
18964		 j     MainExit
18965	3:
18966		 sll   $7,$24,2         	 # Delay slot
18967		 addu  $7,$7,$30
18968		 lw    $7,0x00($7)
18969		 jr    $7
18970		 nop                    	 # Delay slot
18971
18972OP0_0690:				#:
18973		 addiu $23,$23,2
18974
18975		 andi  $24,$24,0x07
18976		 lhu   $8,0x00($23)
18977		 lhu   $25,0x02($23)
18978		 sll   $8,$8,16
18979		 or    $8,$8,$25
18980		 addiu $23,$23,4
18981		 sll   $24,$24,2
18982		 addu  $24,$24,$21
18983		 lw    $14,0x20($24)
18984		 lw    $25,0x84($21)
18985		 sw    $15,m68k_ICount
18986		 sw    $8,0x44($29)
18987		 sw    $14,0x40($29)
18988		 or    $4,$0,$14
18989		 jalr  $25
18990		 sw    $23,0x4C($21)    	 # Delay slot
18991		 lw    $14,0x40($29)
18992		 lw    $8,0x44($29)
18993		 lw    $15,m68k_ICount
18994		 or    $9,$0,$2
18995		 addu  $2,$9,$8
18996		 sltu  $16,$2,$8       	 # Set Carry
18997		 xor   $17,$9,$8
18998		 nor   $17,$0,$17
18999		 xor   $25,$2,$9
19000		 and   $17,$17,$25
19001		 srl   $17,$17,31        	 # Set Overflow
19002		 slt   $19,$2,$0        	 # Set Sign
19003		 sltiu $18,$2,1         	 # Set Zero
19004		 or    $20,$0,$16      	 # Copy Carry to X
19005		 lw    $25,0x90($21)
19006		 sw    $15,m68k_ICount
19007		 or    $5,$0,$2
19008		 or    $4,$0,$14
19009		 jalr  $25
19010		 sw    $23,0x4C($21)    	 # Delay slot
19011		 lw    $15,m68k_ICount
19012		 addiu $15,$15,-28
19013		 bgez  $15,3f
19014		 lhu   $24,0x00($23)    	 # Delay slot
19015		 j     MainExit
19016	3:
19017		 sll   $7,$24,2         	 # Delay slot
19018		 addu  $7,$7,$30
19019		 lw    $7,0x00($7)
19020		 jr    $7
19021		 nop                    	 # Delay slot
19022
19023OP0_0698:				#:
19024		 addiu $23,$23,2
19025
19026		 andi  $24,$24,0x07
19027		 lhu   $8,0x00($23)
19028		 lhu   $25,0x02($23)
19029		 sll   $8,$8,16
19030		 or    $8,$8,$25
19031		 addiu $23,$23,4
19032		 sll   $24,$24,2
19033		 addu  $24,$24,$21
19034		 lw    $14,0x20($24)
19035		 addiu $25,$14,4
19036		 sw    $25,0x20($24)
19037		 lw    $25,0x84($21)
19038		 sw    $15,m68k_ICount
19039		 sw    $8,0x44($29)
19040		 sw    $14,0x40($29)
19041		 or    $4,$0,$14
19042		 jalr  $25
19043		 sw    $23,0x4C($21)    	 # Delay slot
19044		 lw    $14,0x40($29)
19045		 lw    $8,0x44($29)
19046		 lw    $15,m68k_ICount
19047		 or    $9,$0,$2
19048		 addu  $2,$9,$8
19049		 sltu  $16,$2,$8       	 # Set Carry
19050		 xor   $17,$9,$8
19051		 nor   $17,$0,$17
19052		 xor   $25,$2,$9
19053		 and   $17,$17,$25
19054		 srl   $17,$17,31        	 # Set Overflow
19055		 slt   $19,$2,$0        	 # Set Sign
19056		 sltiu $18,$2,1         	 # Set Zero
19057		 or    $20,$0,$16      	 # Copy Carry to X
19058		 lw    $25,0x90($21)
19059		 sw    $15,m68k_ICount
19060		 or    $5,$0,$2
19061		 or    $4,$0,$14
19062		 jalr  $25
19063		 sw    $23,0x4C($21)    	 # Delay slot
19064		 lw    $15,m68k_ICount
19065		 addiu $15,$15,-28
19066		 bgez  $15,3f
19067		 lhu   $24,0x00($23)    	 # Delay slot
19068		 j     MainExit
19069	3:
19070		 sll   $7,$24,2         	 # Delay slot
19071		 addu  $7,$7,$30
19072		 lw    $7,0x00($7)
19073		 jr    $7
19074		 nop                    	 # Delay slot
19075
19076OP0_06a0:				#:
19077		 addiu $23,$23,2
19078
19079		 andi  $24,$24,0x07
19080		 lhu   $8,0x00($23)
19081		 lhu   $25,0x02($23)
19082		 sll   $8,$8,16
19083		 or    $8,$8,$25
19084		 addiu $23,$23,4
19085		 sll   $24,$24,2
19086		 addu  $24,$24,$21
19087		 lw    $14,0x20($24)
19088		 addiu $14,$14,-4
19089		 sw    $14,0x20($24)
19090		 lw    $25,0x84($21)
19091		 sw    $15,m68k_ICount
19092		 sw    $8,0x44($29)
19093		 sw    $14,0x40($29)
19094		 or    $4,$0,$14
19095		 jalr  $25
19096		 sw    $23,0x4C($21)    	 # Delay slot
19097		 lw    $14,0x40($29)
19098		 lw    $8,0x44($29)
19099		 lw    $15,m68k_ICount
19100		 or    $9,$0,$2
19101		 addu  $2,$9,$8
19102		 sltu  $16,$2,$8       	 # Set Carry
19103		 xor   $17,$9,$8
19104		 nor   $17,$0,$17
19105		 xor   $25,$2,$9
19106		 and   $17,$17,$25
19107		 srl   $17,$17,31        	 # Set Overflow
19108		 slt   $19,$2,$0        	 # Set Sign
19109		 sltiu $18,$2,1         	 # Set Zero
19110		 or    $20,$0,$16      	 # Copy Carry to X
19111		 lw    $25,0x90($21)
19112		 sw    $15,m68k_ICount
19113		 or    $5,$0,$2
19114		 or    $4,$0,$14
19115		 jalr  $25
19116		 sw    $23,0x4C($21)    	 # Delay slot
19117		 lw    $15,m68k_ICount
19118		 addiu $15,$15,-30
19119		 bgez  $15,3f
19120		 lhu   $24,0x00($23)    	 # Delay slot
19121		 j     MainExit
19122	3:
19123		 sll   $7,$24,2         	 # Delay slot
19124		 addu  $7,$7,$30
19125		 lw    $7,0x00($7)
19126		 jr    $7
19127		 nop                    	 # Delay slot
19128
19129OP0_06a8:				#:
19130		 addiu $23,$23,2
19131
19132		 andi  $24,$24,0x07
19133		 lhu   $8,0x00($23)
19134		 lhu   $25,0x02($23)
19135		 sll   $8,$8,16
19136		 or    $8,$8,$25
19137		 addiu $23,$23,4
19138		 lh    $7,0x00($23)
19139		 sll   $24,$24,2
19140		 addu  $24,$24,$21
19141		 lw    $14,0x20($24)
19142		 addiu $23,$23,2
19143		 addu  $14,$14,$7
19144		 lw    $25,0x84($21)
19145		 sw    $15,m68k_ICount
19146		 sw    $8,0x44($29)
19147		 sw    $14,0x40($29)
19148		 or    $4,$0,$14
19149		 jalr  $25
19150		 sw    $23,0x4C($21)    	 # Delay slot
19151		 lw    $14,0x40($29)
19152		 lw    $8,0x44($29)
19153		 lw    $15,m68k_ICount
19154		 or    $9,$0,$2
19155		 addu  $2,$9,$8
19156		 sltu  $16,$2,$8       	 # Set Carry
19157		 xor   $17,$9,$8
19158		 nor   $17,$0,$17
19159		 xor   $25,$2,$9
19160		 and   $17,$17,$25
19161		 srl   $17,$17,31        	 # Set Overflow
19162		 slt   $19,$2,$0        	 # Set Sign
19163		 sltiu $18,$2,1         	 # Set Zero
19164		 or    $20,$0,$16      	 # Copy Carry to X
19165		 lw    $25,0x90($21)
19166		 sw    $15,m68k_ICount
19167		 or    $5,$0,$2
19168		 or    $4,$0,$14
19169		 jalr  $25
19170		 sw    $23,0x4C($21)    	 # Delay slot
19171		 lw    $15,m68k_ICount
19172		 addiu $15,$15,-32
19173		 bgez  $15,3f
19174		 lhu   $24,0x00($23)    	 # Delay slot
19175		 j     MainExit
19176	3:
19177		 sll   $7,$24,2         	 # Delay slot
19178		 addu  $7,$7,$30
19179		 lw    $7,0x00($7)
19180		 jr    $7
19181		 nop                    	 # Delay slot
19182
19183OP0_06b0:				#:
19184		 addiu $23,$23,2
19185
19186		 andi  $24,$24,0x07
19187		 lhu   $8,0x00($23)
19188		 lhu   $25,0x02($23)
19189		 sll   $8,$8,16
19190		 or    $8,$8,$25
19191		 addiu $23,$23,4
19192		 sll   $24,$24,2
19193		 addu  $24,$24,$21
19194		 lw    $14,0x20($24)
19195		 lhu   $7,0x00($23)
19196		 addiu $23,$23,2
19197		 seb   $6,$7
19198		 or    $25,$0,$7
19199		 srl   $7,$7,12
19200		 andi  $25,$25,0x0800
19201		 sll   $7,$7,2
19202		 addu  $7,$7,$21
19203		 bne   $25,$0,0f
19204		 lw    $25,0x00($7)      	 # Delay slot
19205		 seh   $25,$25
19206	0:
19207		 addu  $25,$14,$25
19208		 addu  $14,$25,$6
19209		 lw    $25,0x84($21)
19210		 sw    $15,m68k_ICount
19211		 sw    $8,0x44($29)
19212		 sw    $14,0x40($29)
19213		 or    $4,$0,$14
19214		 jalr  $25
19215		 sw    $23,0x4C($21)    	 # Delay slot
19216		 lw    $14,0x40($29)
19217		 lw    $8,0x44($29)
19218		 lw    $15,m68k_ICount
19219		 or    $9,$0,$2
19220		 addu  $2,$9,$8
19221		 sltu  $16,$2,$8       	 # Set Carry
19222		 xor   $17,$9,$8
19223		 nor   $17,$0,$17
19224		 xor   $25,$2,$9
19225		 and   $17,$17,$25
19226		 srl   $17,$17,31        	 # Set Overflow
19227		 slt   $19,$2,$0        	 # Set Sign
19228		 sltiu $18,$2,1         	 # Set Zero
19229		 or    $20,$0,$16      	 # Copy Carry to X
19230		 lw    $25,0x90($21)
19231		 sw    $15,m68k_ICount
19232		 or    $5,$0,$2
19233		 or    $4,$0,$14
19234		 jalr  $25
19235		 sw    $23,0x4C($21)    	 # Delay slot
19236		 lw    $15,m68k_ICount
19237		 addiu $15,$15,-34
19238		 bgez  $15,3f
19239		 lhu   $24,0x00($23)    	 # Delay slot
19240		 j     MainExit
19241	3:
19242		 sll   $7,$24,2         	 # Delay slot
19243		 addu  $7,$7,$30
19244		 lw    $7,0x00($7)
19245		 jr    $7
19246		 nop                    	 # Delay slot
19247
19248OP0_06b8:				#:
19249		 addiu $23,$23,2
19250
19251		 lhu   $8,0x00($23)
19252		 lhu   $25,0x02($23)
19253		 sll   $8,$8,16
19254		 or    $8,$8,$25
19255		 addiu $23,$23,4
19256		 lh    $14,0x00($23)
19257		 addiu $23,$23,2
19258		 lw    $25,0x84($21)
19259		 sw    $15,m68k_ICount
19260		 sw    $8,0x44($29)
19261		 sw    $14,0x40($29)
19262		 or    $4,$0,$14
19263		 jalr  $25
19264		 sw    $23,0x4C($21)    	 # Delay slot
19265		 lw    $14,0x40($29)
19266		 lw    $8,0x44($29)
19267		 lw    $15,m68k_ICount
19268		 or    $9,$0,$2
19269		 addu  $2,$9,$8
19270		 sltu  $16,$2,$8       	 # Set Carry
19271		 xor   $17,$9,$8
19272		 nor   $17,$0,$17
19273		 xor   $25,$2,$9
19274		 and   $17,$17,$25
19275		 srl   $17,$17,31        	 # Set Overflow
19276		 slt   $19,$2,$0        	 # Set Sign
19277		 sltiu $18,$2,1         	 # Set Zero
19278		 or    $20,$0,$16      	 # Copy Carry to X
19279		 lw    $25,0x90($21)
19280		 sw    $15,m68k_ICount
19281		 or    $5,$0,$2
19282		 or    $4,$0,$14
19283		 jalr  $25
19284		 sw    $23,0x4C($21)    	 # Delay slot
19285		 lw    $15,m68k_ICount
19286		 addiu $15,$15,-32
19287		 bgez  $15,3f
19288		 lhu   $24,0x00($23)    	 # Delay slot
19289		 j     MainExit
19290	3:
19291		 sll   $7,$24,2         	 # Delay slot
19292		 addu  $7,$7,$30
19293		 lw    $7,0x00($7)
19294		 jr    $7
19295		 nop                    	 # Delay slot
19296
19297OP0_06b9:				#:
19298		 addiu $23,$23,2
19299
19300		 lhu   $8,0x00($23)
19301		 lhu   $25,0x02($23)
19302		 sll   $8,$8,16
19303		 or    $8,$8,$25
19304		 addiu $23,$23,4
19305		 lhu   $14,0x00($23)
19306		 lhu   $25,0x02($23)
19307		 sll   $14,$14,16
19308		 or    $14,$14,$25
19309		 addiu $23,$23,4
19310		 lw    $25,0x84($21)
19311		 sw    $15,m68k_ICount
19312		 sw    $8,0x44($29)
19313		 sw    $14,0x40($29)
19314		 or    $4,$0,$14
19315		 jalr  $25
19316		 sw    $23,0x4C($21)    	 # Delay slot
19317		 lw    $14,0x40($29)
19318		 lw    $8,0x44($29)
19319		 lw    $15,m68k_ICount
19320		 or    $9,$0,$2
19321		 addu  $2,$9,$8
19322		 sltu  $16,$2,$8       	 # Set Carry
19323		 xor   $17,$9,$8
19324		 nor   $17,$0,$17
19325		 xor   $25,$2,$9
19326		 and   $17,$17,$25
19327		 srl   $17,$17,31        	 # Set Overflow
19328		 slt   $19,$2,$0        	 # Set Sign
19329		 sltiu $18,$2,1         	 # Set Zero
19330		 or    $20,$0,$16      	 # Copy Carry to X
19331		 lw    $25,0x90($21)
19332		 sw    $15,m68k_ICount
19333		 or    $5,$0,$2
19334		 or    $4,$0,$14
19335		 jalr  $25
19336		 sw    $23,0x4C($21)    	 # Delay slot
19337		 lw    $15,m68k_ICount
19338		 addiu $15,$15,-36
19339		 bgez  $15,3f
19340		 lhu   $24,0x00($23)    	 # Delay slot
19341		 j     MainExit
19342	3:
19343		 sll   $7,$24,2         	 # Delay slot
19344		 addu  $7,$7,$30
19345		 lw    $7,0x00($7)
19346		 jr    $7
19347		 nop                    	 # Delay slot
19348
19349OP0_0a00:				#:
19350		 addiu $23,$23,2
19351
19352		 andi  $24,$24,0x07
19353		 lb    $8,0x00($23)
19354		 addiu $23,$23,2
19355		 sll   $24,$24,2
19356		 addu  $24,$24,$21
19357		 lb    $2,0x00($24)
19358		 xor   $2,$2,$8
19359		 and   $16,$0,$0        	 # Clear Carry
19360		 and   $17,$0,$0        	 # Clear Overflow
19361		 slt   $19,$2,$0        	 # Set Sign
19362		 sltiu $18,$2,1         	 # Set Zero
19363		 sb    $2,0x00($24)
19364		 addiu $15,$15,-8
19365		 bgez  $15,3f
19366		 lhu   $24,0x00($23)    	 # Delay slot
19367		 j     MainExit
19368	3:
19369		 sll   $7,$24,2         	 # Delay slot
19370		 addu  $7,$7,$30
19371		 lw    $7,0x00($7)
19372		 jr    $7
19373		 nop                    	 # Delay slot
19374
19375OP0_0a10:				#:
19376		 addiu $23,$23,2
19377
19378		 andi  $24,$24,0x07
19379		 lb    $8,0x00($23)
19380		 addiu $23,$23,2
19381		 sll   $24,$24,2
19382		 addu  $24,$24,$21
19383		 lw    $14,0x20($24)
19384		 lw    $25,0x7C($21)
19385		 sw    $15,m68k_ICount
19386		 sw    $8,0x44($29)
19387		 sw    $14,0x40($29)
19388		 or    $4,$0,$14
19389		 jalr  $25
19390		 sw    $23,0x4C($21)    	 # Delay slot
19391		 lw    $14,0x40($29)
19392		 lw    $8,0x44($29)
19393		 lw    $15,m68k_ICount
19394		 seb   $2,$2
19395		 xor   $2,$2,$8
19396		 and   $16,$0,$0        	 # Clear Carry
19397		 and   $17,$0,$0        	 # Clear Overflow
19398		 slt   $19,$2,$0        	 # Set Sign
19399		 sltiu $18,$2,1         	 # Set Zero
19400		 lw    $25,0x88($21)
19401		 sw    $15,m68k_ICount
19402		 or    $5,$0,$2
19403		 or    $4,$0,$14
19404		 jalr  $25
19405		 sw    $23,0x4C($21)    	 # Delay slot
19406		 lw    $15,m68k_ICount
19407		 addiu $15,$15,-16
19408		 bgez  $15,3f
19409		 lhu   $24,0x00($23)    	 # Delay slot
19410		 j     MainExit
19411	3:
19412		 sll   $7,$24,2         	 # Delay slot
19413		 addu  $7,$7,$30
19414		 lw    $7,0x00($7)
19415		 jr    $7
19416		 nop                    	 # Delay slot
19417
19418OP0_0a18:				#:
19419		 addiu $23,$23,2
19420
19421		 andi  $24,$24,0x07
19422		 lb    $8,0x00($23)
19423		 addiu $23,$23,2
19424		 sll   $24,$24,2
19425		 addu  $24,$24,$21
19426		 lw    $14,0x20($24)
19427		 addiu $25,$14,1
19428		 sw    $25,0x20($24)
19429		 lw    $25,0x7C($21)
19430		 sw    $15,m68k_ICount
19431		 sw    $8,0x44($29)
19432		 sw    $14,0x40($29)
19433		 or    $4,$0,$14
19434		 jalr  $25
19435		 sw    $23,0x4C($21)    	 # Delay slot
19436		 lw    $14,0x40($29)
19437		 lw    $8,0x44($29)
19438		 lw    $15,m68k_ICount
19439		 seb   $2,$2
19440		 xor   $2,$2,$8
19441		 and   $16,$0,$0        	 # Clear Carry
19442		 and   $17,$0,$0        	 # Clear Overflow
19443		 slt   $19,$2,$0        	 # Set Sign
19444		 sltiu $18,$2,1         	 # Set Zero
19445		 lw    $25,0x88($21)
19446		 sw    $15,m68k_ICount
19447		 or    $5,$0,$2
19448		 or    $4,$0,$14
19449		 jalr  $25
19450		 sw    $23,0x4C($21)    	 # Delay slot
19451		 lw    $15,m68k_ICount
19452		 addiu $15,$15,-16
19453		 bgez  $15,3f
19454		 lhu   $24,0x00($23)    	 # Delay slot
19455		 j     MainExit
19456	3:
19457		 sll   $7,$24,2         	 # Delay slot
19458		 addu  $7,$7,$30
19459		 lw    $7,0x00($7)
19460		 jr    $7
19461		 nop                    	 # Delay slot
19462
19463OP0_0a1f:				#:
19464		 addiu $23,$23,2
19465
19466		 lb    $8,0x00($23)
19467		 addiu $23,$23,2
19468		 lw    $14,0x3C($21)    	 # Get A7
19469		 addiu $25,$14,2
19470		 sw    $25,0x3C($21)
19471		 lw    $25,0x7C($21)
19472		 sw    $15,m68k_ICount
19473		 sw    $8,0x44($29)
19474		 sw    $14,0x40($29)
19475		 or    $4,$0,$14
19476		 jalr  $25
19477		 sw    $23,0x4C($21)    	 # Delay slot
19478		 lw    $14,0x40($29)
19479		 lw    $8,0x44($29)
19480		 lw    $15,m68k_ICount
19481		 seb   $2,$2
19482		 xor   $2,$2,$8
19483		 and   $16,$0,$0        	 # Clear Carry
19484		 and   $17,$0,$0        	 # Clear Overflow
19485		 slt   $19,$2,$0        	 # Set Sign
19486		 sltiu $18,$2,1         	 # Set Zero
19487		 lw    $25,0x88($21)
19488		 sw    $15,m68k_ICount
19489		 or    $5,$0,$2
19490		 or    $4,$0,$14
19491		 jalr  $25
19492		 sw    $23,0x4C($21)    	 # Delay slot
19493		 lw    $15,m68k_ICount
19494		 addiu $15,$15,-16
19495		 bgez  $15,3f
19496		 lhu   $24,0x00($23)    	 # Delay slot
19497		 j     MainExit
19498	3:
19499		 sll   $7,$24,2         	 # Delay slot
19500		 addu  $7,$7,$30
19501		 lw    $7,0x00($7)
19502		 jr    $7
19503		 nop                    	 # Delay slot
19504
19505OP0_0a20:				#:
19506		 addiu $23,$23,2
19507
19508		 andi  $24,$24,0x07
19509		 lb    $8,0x00($23)
19510		 addiu $23,$23,2
19511		 sll   $24,$24,2
19512		 addu  $24,$24,$21
19513		 lw    $14,0x20($24)
19514		 addiu $14,$14,-1
19515		 sw    $14,0x20($24)
19516		 lw    $25,0x7C($21)
19517		 sw    $15,m68k_ICount
19518		 sw    $8,0x44($29)
19519		 sw    $14,0x40($29)
19520		 or    $4,$0,$14
19521		 jalr  $25
19522		 sw    $23,0x4C($21)    	 # Delay slot
19523		 lw    $14,0x40($29)
19524		 lw    $8,0x44($29)
19525		 lw    $15,m68k_ICount
19526		 seb   $2,$2
19527		 xor   $2,$2,$8
19528		 and   $16,$0,$0        	 # Clear Carry
19529		 and   $17,$0,$0        	 # Clear Overflow
19530		 slt   $19,$2,$0        	 # Set Sign
19531		 sltiu $18,$2,1         	 # Set Zero
19532		 lw    $25,0x88($21)
19533		 sw    $15,m68k_ICount
19534		 or    $5,$0,$2
19535		 or    $4,$0,$14
19536		 jalr  $25
19537		 sw    $23,0x4C($21)    	 # Delay slot
19538		 lw    $15,m68k_ICount
19539		 addiu $15,$15,-18
19540		 bgez  $15,3f
19541		 lhu   $24,0x00($23)    	 # Delay slot
19542		 j     MainExit
19543	3:
19544		 sll   $7,$24,2         	 # Delay slot
19545		 addu  $7,$7,$30
19546		 lw    $7,0x00($7)
19547		 jr    $7
19548		 nop                    	 # Delay slot
19549
19550OP0_0a27:				#:
19551		 addiu $23,$23,2
19552
19553		 lb    $8,0x00($23)
19554		 addiu $23,$23,2
19555		 lw    $14,0x3C($21)    	 # Get A7
19556		 addiu $14,$14,-2
19557		 sw    $14,0x3C($21)
19558		 lw    $25,0x7C($21)
19559		 sw    $15,m68k_ICount
19560		 sw    $8,0x44($29)
19561		 sw    $14,0x40($29)
19562		 or    $4,$0,$14
19563		 jalr  $25
19564		 sw    $23,0x4C($21)    	 # Delay slot
19565		 lw    $14,0x40($29)
19566		 lw    $8,0x44($29)
19567		 lw    $15,m68k_ICount
19568		 seb   $2,$2
19569		 xor   $2,$2,$8
19570		 and   $16,$0,$0        	 # Clear Carry
19571		 and   $17,$0,$0        	 # Clear Overflow
19572		 slt   $19,$2,$0        	 # Set Sign
19573		 sltiu $18,$2,1         	 # Set Zero
19574		 lw    $25,0x88($21)
19575		 sw    $15,m68k_ICount
19576		 or    $5,$0,$2
19577		 or    $4,$0,$14
19578		 jalr  $25
19579		 sw    $23,0x4C($21)    	 # Delay slot
19580		 lw    $15,m68k_ICount
19581		 addiu $15,$15,-18
19582		 bgez  $15,3f
19583		 lhu   $24,0x00($23)    	 # Delay slot
19584		 j     MainExit
19585	3:
19586		 sll   $7,$24,2         	 # Delay slot
19587		 addu  $7,$7,$30
19588		 lw    $7,0x00($7)
19589		 jr    $7
19590		 nop                    	 # Delay slot
19591
19592OP0_0a28:				#:
19593		 addiu $23,$23,2
19594
19595		 andi  $24,$24,0x07
19596		 lb    $8,0x00($23)
19597		 addiu $23,$23,2
19598		 lh    $7,0x00($23)
19599		 sll   $24,$24,2
19600		 addu  $24,$24,$21
19601		 lw    $14,0x20($24)
19602		 addiu $23,$23,2
19603		 addu  $14,$14,$7
19604		 lw    $25,0x7C($21)
19605		 sw    $15,m68k_ICount
19606		 sw    $8,0x44($29)
19607		 sw    $14,0x40($29)
19608		 or    $4,$0,$14
19609		 jalr  $25
19610		 sw    $23,0x4C($21)    	 # Delay slot
19611		 lw    $14,0x40($29)
19612		 lw    $8,0x44($29)
19613		 lw    $15,m68k_ICount
19614		 seb   $2,$2
19615		 xor   $2,$2,$8
19616		 and   $16,$0,$0        	 # Clear Carry
19617		 and   $17,$0,$0        	 # Clear Overflow
19618		 slt   $19,$2,$0        	 # Set Sign
19619		 sltiu $18,$2,1         	 # Set Zero
19620		 lw    $25,0x88($21)
19621		 sw    $15,m68k_ICount
19622		 or    $5,$0,$2
19623		 or    $4,$0,$14
19624		 jalr  $25
19625		 sw    $23,0x4C($21)    	 # Delay slot
19626		 lw    $15,m68k_ICount
19627		 addiu $15,$15,-20
19628		 bgez  $15,3f
19629		 lhu   $24,0x00($23)    	 # Delay slot
19630		 j     MainExit
19631	3:
19632		 sll   $7,$24,2         	 # Delay slot
19633		 addu  $7,$7,$30
19634		 lw    $7,0x00($7)
19635		 jr    $7
19636		 nop                    	 # Delay slot
19637
19638OP0_0a30:				#:
19639		 addiu $23,$23,2
19640
19641		 andi  $24,$24,0x07
19642		 lb    $8,0x00($23)
19643		 addiu $23,$23,2
19644		 sll   $24,$24,2
19645		 addu  $24,$24,$21
19646		 lw    $14,0x20($24)
19647		 lhu   $7,0x00($23)
19648		 addiu $23,$23,2
19649		 seb   $6,$7
19650		 or    $25,$0,$7
19651		 srl   $7,$7,12
19652		 andi  $25,$25,0x0800
19653		 sll   $7,$7,2
19654		 addu  $7,$7,$21
19655		 bne   $25,$0,0f
19656		 lw    $25,0x00($7)      	 # Delay slot
19657		 seh   $25,$25
19658	0:
19659		 addu  $25,$14,$25
19660		 addu  $14,$25,$6
19661		 lw    $25,0x7C($21)
19662		 sw    $15,m68k_ICount
19663		 sw    $8,0x44($29)
19664		 sw    $14,0x40($29)
19665		 or    $4,$0,$14
19666		 jalr  $25
19667		 sw    $23,0x4C($21)    	 # Delay slot
19668		 lw    $14,0x40($29)
19669		 lw    $8,0x44($29)
19670		 lw    $15,m68k_ICount
19671		 seb   $2,$2
19672		 xor   $2,$2,$8
19673		 and   $16,$0,$0        	 # Clear Carry
19674		 and   $17,$0,$0        	 # Clear Overflow
19675		 slt   $19,$2,$0        	 # Set Sign
19676		 sltiu $18,$2,1         	 # Set Zero
19677		 lw    $25,0x88($21)
19678		 sw    $15,m68k_ICount
19679		 or    $5,$0,$2
19680		 or    $4,$0,$14
19681		 jalr  $25
19682		 sw    $23,0x4C($21)    	 # Delay slot
19683		 lw    $15,m68k_ICount
19684		 addiu $15,$15,-22
19685		 bgez  $15,3f
19686		 lhu   $24,0x00($23)    	 # Delay slot
19687		 j     MainExit
19688	3:
19689		 sll   $7,$24,2         	 # Delay slot
19690		 addu  $7,$7,$30
19691		 lw    $7,0x00($7)
19692		 jr    $7
19693		 nop                    	 # Delay slot
19694
19695OP0_0a38:				#:
19696		 addiu $23,$23,2
19697
19698		 lb    $8,0x00($23)
19699		 addiu $23,$23,2
19700		 lh    $14,0x00($23)
19701		 addiu $23,$23,2
19702		 lw    $25,0x7C($21)
19703		 sw    $15,m68k_ICount
19704		 sw    $8,0x44($29)
19705		 sw    $14,0x40($29)
19706		 or    $4,$0,$14
19707		 jalr  $25
19708		 sw    $23,0x4C($21)    	 # Delay slot
19709		 lw    $14,0x40($29)
19710		 lw    $8,0x44($29)
19711		 lw    $15,m68k_ICount
19712		 seb   $2,$2
19713		 xor   $2,$2,$8
19714		 and   $16,$0,$0        	 # Clear Carry
19715		 and   $17,$0,$0        	 # Clear Overflow
19716		 slt   $19,$2,$0        	 # Set Sign
19717		 sltiu $18,$2,1         	 # Set Zero
19718		 lw    $25,0x88($21)
19719		 sw    $15,m68k_ICount
19720		 or    $5,$0,$2
19721		 or    $4,$0,$14
19722		 jalr  $25
19723		 sw    $23,0x4C($21)    	 # Delay slot
19724		 lw    $15,m68k_ICount
19725		 addiu $15,$15,-20
19726		 bgez  $15,3f
19727		 lhu   $24,0x00($23)    	 # Delay slot
19728		 j     MainExit
19729	3:
19730		 sll   $7,$24,2         	 # Delay slot
19731		 addu  $7,$7,$30
19732		 lw    $7,0x00($7)
19733		 jr    $7
19734		 nop                    	 # Delay slot
19735
19736OP0_0a39:				#:
19737		 addiu $23,$23,2
19738
19739		 lb    $8,0x00($23)
19740		 addiu $23,$23,2
19741		 lhu   $14,0x00($23)
19742		 lhu   $25,0x02($23)
19743		 sll   $14,$14,16
19744		 or    $14,$14,$25
19745		 addiu $23,$23,4
19746		 lw    $25,0x7C($21)
19747		 sw    $15,m68k_ICount
19748		 sw    $8,0x44($29)
19749		 sw    $14,0x40($29)
19750		 or    $4,$0,$14
19751		 jalr  $25
19752		 sw    $23,0x4C($21)    	 # Delay slot
19753		 lw    $14,0x40($29)
19754		 lw    $8,0x44($29)
19755		 lw    $15,m68k_ICount
19756		 seb   $2,$2
19757		 xor   $2,$2,$8
19758		 and   $16,$0,$0        	 # Clear Carry
19759		 and   $17,$0,$0        	 # Clear Overflow
19760		 slt   $19,$2,$0        	 # Set Sign
19761		 sltiu $18,$2,1         	 # Set Zero
19762		 lw    $25,0x88($21)
19763		 sw    $15,m68k_ICount
19764		 or    $5,$0,$2
19765		 or    $4,$0,$14
19766		 jalr  $25
19767		 sw    $23,0x4C($21)    	 # Delay slot
19768		 lw    $15,m68k_ICount
19769		 addiu $15,$15,-24
19770		 bgez  $15,3f
19771		 lhu   $24,0x00($23)    	 # Delay slot
19772		 j     MainExit
19773	3:
19774		 sll   $7,$24,2         	 # Delay slot
19775		 addu  $7,$7,$30
19776		 lw    $7,0x00($7)
19777		 jr    $7
19778		 nop                    	 # Delay slot
19779
19780OP0_0a3c:				#:
19781		 addiu $23,$23,2
19782
19783		 lbu   $8,0x00($23)
19784		 addiu $23,$23,2
19785		 or    $2,$0,$20
19786		 sll   $2,$2,1
19787		 or    $2,$2,$19
19788		 sll   $2,$2,1
19789		 or    $2,$2,$18
19790		 sll   $2,$2,1
19791		 or    $2,$2,$17
19792		 sll   $2,$2,1
19793		 or    $2,$2,$16
19794		 xor   $2,$2,$8
19795		 or    $20,$0,$2
19796		 or    $19,$0,$2
19797		 or    $18,$0,$2
19798		 or    $17,$0,$2
19799		 or    $16,$0,$2
19800		 andi  $20,$20,0x10
19801		 andi  $19,$19,0x08
19802		 andi  $18,$18,0x04
19803		 andi  $17,$17,0x02
19804		 andi  $16,$16,0x01
19805		 srl   $20,$20,4
19806		 srl   $19,$19,3
19807		 srl   $18,$18,2
19808		 srl   $17,$17,1
19809		 addiu $15,$15,-20
19810		 bgez  $15,3f
19811		 lhu   $24,0x00($23)    	 # Delay slot
19812		 j     MainExit
19813	3:
19814		 sll   $7,$24,2         	 # Delay slot
19815		 addu  $7,$7,$30
19816		 lw    $7,0x00($7)
19817		 jr    $7
19818		 nop                    	 # Delay slot
19819
19820OP0_0a40:				#:
19821		 addiu $23,$23,2
19822
19823		 andi  $24,$24,0x07
19824		 lh    $8,0x00($23)
19825		 addiu $23,$23,2
19826		 sll   $24,$24,2
19827		 addu  $24,$24,$21
19828		 lh    $2,0x00($24)
19829		 xor   $2,$2,$8
19830		 and   $16,$0,$0        	 # Clear Carry
19831		 and   $17,$0,$0        	 # Clear Overflow
19832		 slt   $19,$2,$0        	 # Set Sign
19833		 sltiu $18,$2,1         	 # Set Zero
19834		 sh    $2,0x00($24)
19835		 addiu $15,$15,-8
19836		 bgez  $15,3f
19837		 lhu   $24,0x00($23)    	 # Delay slot
19838		 j     MainExit
19839	3:
19840		 sll   $7,$24,2         	 # Delay slot
19841		 addu  $7,$7,$30
19842		 lw    $7,0x00($7)
19843		 jr    $7
19844		 nop                    	 # Delay slot
19845
19846OP0_0a50:				#:
19847		 addiu $23,$23,2
19848
19849		 andi  $24,$24,0x07
19850		 lh    $8,0x00($23)
19851		 addiu $23,$23,2
19852		 sll   $24,$24,2
19853		 addu  $24,$24,$21
19854		 lw    $14,0x20($24)
19855		 lw    $25,0x80($21)
19856		 sw    $15,m68k_ICount
19857		 sw    $8,0x44($29)
19858		 sw    $14,0x40($29)
19859		 or    $4,$0,$14
19860		 jalr  $25
19861		 sw    $23,0x4C($21)    	 # Delay slot
19862		 lw    $14,0x40($29)
19863		 lw    $8,0x44($29)
19864		 lw    $15,m68k_ICount
19865		 seh   $2,$2
19866		 xor   $2,$2,$8
19867		 and   $16,$0,$0        	 # Clear Carry
19868		 and   $17,$0,$0        	 # Clear Overflow
19869		 slt   $19,$2,$0        	 # Set Sign
19870		 sltiu $18,$2,1         	 # Set Zero
19871		 lw    $25,0x8C($21)
19872		 sw    $15,m68k_ICount
19873		 or    $5,$0,$2
19874		 or    $4,$0,$14
19875		 jalr  $25
19876		 sw    $23,0x4C($21)    	 # Delay slot
19877		 lw    $15,m68k_ICount
19878		 addiu $15,$15,-16
19879		 bgez  $15,3f
19880		 lhu   $24,0x00($23)    	 # Delay slot
19881		 j     MainExit
19882	3:
19883		 sll   $7,$24,2         	 # Delay slot
19884		 addu  $7,$7,$30
19885		 lw    $7,0x00($7)
19886		 jr    $7
19887		 nop                    	 # Delay slot
19888
19889OP0_0a58:				#:
19890		 addiu $23,$23,2
19891
19892		 andi  $24,$24,0x07
19893		 lh    $8,0x00($23)
19894		 addiu $23,$23,2
19895		 sll   $24,$24,2
19896		 addu  $24,$24,$21
19897		 lw    $14,0x20($24)
19898		 addiu $25,$14,2
19899		 sw    $25,0x20($24)
19900		 lw    $25,0x80($21)
19901		 sw    $15,m68k_ICount
19902		 sw    $8,0x44($29)
19903		 sw    $14,0x40($29)
19904		 or    $4,$0,$14
19905		 jalr  $25
19906		 sw    $23,0x4C($21)    	 # Delay slot
19907		 lw    $14,0x40($29)
19908		 lw    $8,0x44($29)
19909		 lw    $15,m68k_ICount
19910		 seh   $2,$2
19911		 xor   $2,$2,$8
19912		 and   $16,$0,$0        	 # Clear Carry
19913		 and   $17,$0,$0        	 # Clear Overflow
19914		 slt   $19,$2,$0        	 # Set Sign
19915		 sltiu $18,$2,1         	 # Set Zero
19916		 lw    $25,0x8C($21)
19917		 sw    $15,m68k_ICount
19918		 or    $5,$0,$2
19919		 or    $4,$0,$14
19920		 jalr  $25
19921		 sw    $23,0x4C($21)    	 # Delay slot
19922		 lw    $15,m68k_ICount
19923		 addiu $15,$15,-16
19924		 bgez  $15,3f
19925		 lhu   $24,0x00($23)    	 # Delay slot
19926		 j     MainExit
19927	3:
19928		 sll   $7,$24,2         	 # Delay slot
19929		 addu  $7,$7,$30
19930		 lw    $7,0x00($7)
19931		 jr    $7
19932		 nop                    	 # Delay slot
19933
19934OP0_0a60:				#:
19935		 addiu $23,$23,2
19936
19937		 andi  $24,$24,0x07
19938		 lh    $8,0x00($23)
19939		 addiu $23,$23,2
19940		 sll   $24,$24,2
19941		 addu  $24,$24,$21
19942		 lw    $14,0x20($24)
19943		 addiu $14,$14,-2
19944		 sw    $14,0x20($24)
19945		 lw    $25,0x80($21)
19946		 sw    $15,m68k_ICount
19947		 sw    $8,0x44($29)
19948		 sw    $14,0x40($29)
19949		 or    $4,$0,$14
19950		 jalr  $25
19951		 sw    $23,0x4C($21)    	 # Delay slot
19952		 lw    $14,0x40($29)
19953		 lw    $8,0x44($29)
19954		 lw    $15,m68k_ICount
19955		 seh   $2,$2
19956		 xor   $2,$2,$8
19957		 and   $16,$0,$0        	 # Clear Carry
19958		 and   $17,$0,$0        	 # Clear Overflow
19959		 slt   $19,$2,$0        	 # Set Sign
19960		 sltiu $18,$2,1         	 # Set Zero
19961		 lw    $25,0x8C($21)
19962		 sw    $15,m68k_ICount
19963		 or    $5,$0,$2
19964		 or    $4,$0,$14
19965		 jalr  $25
19966		 sw    $23,0x4C($21)    	 # Delay slot
19967		 lw    $15,m68k_ICount
19968		 addiu $15,$15,-18
19969		 bgez  $15,3f
19970		 lhu   $24,0x00($23)    	 # Delay slot
19971		 j     MainExit
19972	3:
19973		 sll   $7,$24,2         	 # Delay slot
19974		 addu  $7,$7,$30
19975		 lw    $7,0x00($7)
19976		 jr    $7
19977		 nop                    	 # Delay slot
19978
19979OP0_0a68:				#:
19980		 addiu $23,$23,2
19981
19982		 andi  $24,$24,0x07
19983		 lh    $8,0x00($23)
19984		 addiu $23,$23,2
19985		 lh    $7,0x00($23)
19986		 sll   $24,$24,2
19987		 addu  $24,$24,$21
19988		 lw    $14,0x20($24)
19989		 addiu $23,$23,2
19990		 addu  $14,$14,$7
19991		 lw    $25,0x80($21)
19992		 sw    $15,m68k_ICount
19993		 sw    $8,0x44($29)
19994		 sw    $14,0x40($29)
19995		 or    $4,$0,$14
19996		 jalr  $25
19997		 sw    $23,0x4C($21)    	 # Delay slot
19998		 lw    $14,0x40($29)
19999		 lw    $8,0x44($29)
20000		 lw    $15,m68k_ICount
20001		 seh   $2,$2
20002		 xor   $2,$2,$8
20003		 and   $16,$0,$0        	 # Clear Carry
20004		 and   $17,$0,$0        	 # Clear Overflow
20005		 slt   $19,$2,$0        	 # Set Sign
20006		 sltiu $18,$2,1         	 # Set Zero
20007		 lw    $25,0x8C($21)
20008		 sw    $15,m68k_ICount
20009		 or    $5,$0,$2
20010		 or    $4,$0,$14
20011		 jalr  $25
20012		 sw    $23,0x4C($21)    	 # Delay slot
20013		 lw    $15,m68k_ICount
20014		 addiu $15,$15,-20
20015		 bgez  $15,3f
20016		 lhu   $24,0x00($23)    	 # Delay slot
20017		 j     MainExit
20018	3:
20019		 sll   $7,$24,2         	 # Delay slot
20020		 addu  $7,$7,$30
20021		 lw    $7,0x00($7)
20022		 jr    $7
20023		 nop                    	 # Delay slot
20024
20025OP0_0a70:				#:
20026		 addiu $23,$23,2
20027
20028		 andi  $24,$24,0x07
20029		 lh    $8,0x00($23)
20030		 addiu $23,$23,2
20031		 sll   $24,$24,2
20032		 addu  $24,$24,$21
20033		 lw    $14,0x20($24)
20034		 lhu   $7,0x00($23)
20035		 addiu $23,$23,2
20036		 seb   $6,$7
20037		 or    $25,$0,$7
20038		 srl   $7,$7,12
20039		 andi  $25,$25,0x0800
20040		 sll   $7,$7,2
20041		 addu  $7,$7,$21
20042		 bne   $25,$0,0f
20043		 lw    $25,0x00($7)      	 # Delay slot
20044		 seh   $25,$25
20045	0:
20046		 addu  $25,$14,$25
20047		 addu  $14,$25,$6
20048		 lw    $25,0x80($21)
20049		 sw    $15,m68k_ICount
20050		 sw    $8,0x44($29)
20051		 sw    $14,0x40($29)
20052		 or    $4,$0,$14
20053		 jalr  $25
20054		 sw    $23,0x4C($21)    	 # Delay slot
20055		 lw    $14,0x40($29)
20056		 lw    $8,0x44($29)
20057		 lw    $15,m68k_ICount
20058		 seh   $2,$2
20059		 xor   $2,$2,$8
20060		 and   $16,$0,$0        	 # Clear Carry
20061		 and   $17,$0,$0        	 # Clear Overflow
20062		 slt   $19,$2,$0        	 # Set Sign
20063		 sltiu $18,$2,1         	 # Set Zero
20064		 lw    $25,0x8C($21)
20065		 sw    $15,m68k_ICount
20066		 or    $5,$0,$2
20067		 or    $4,$0,$14
20068		 jalr  $25
20069		 sw    $23,0x4C($21)    	 # Delay slot
20070		 lw    $15,m68k_ICount
20071		 addiu $15,$15,-22
20072		 bgez  $15,3f
20073		 lhu   $24,0x00($23)    	 # Delay slot
20074		 j     MainExit
20075	3:
20076		 sll   $7,$24,2         	 # Delay slot
20077		 addu  $7,$7,$30
20078		 lw    $7,0x00($7)
20079		 jr    $7
20080		 nop                    	 # Delay slot
20081
20082OP0_0a78:				#:
20083		 addiu $23,$23,2
20084
20085		 lh    $8,0x00($23)
20086		 addiu $23,$23,2
20087		 lh    $14,0x00($23)
20088		 addiu $23,$23,2
20089		 lw    $25,0x80($21)
20090		 sw    $15,m68k_ICount
20091		 sw    $8,0x44($29)
20092		 sw    $14,0x40($29)
20093		 or    $4,$0,$14
20094		 jalr  $25
20095		 sw    $23,0x4C($21)    	 # Delay slot
20096		 lw    $14,0x40($29)
20097		 lw    $8,0x44($29)
20098		 lw    $15,m68k_ICount
20099		 seh   $2,$2
20100		 xor   $2,$2,$8
20101		 and   $16,$0,$0        	 # Clear Carry
20102		 and   $17,$0,$0        	 # Clear Overflow
20103		 slt   $19,$2,$0        	 # Set Sign
20104		 sltiu $18,$2,1         	 # Set Zero
20105		 lw    $25,0x8C($21)
20106		 sw    $15,m68k_ICount
20107		 or    $5,$0,$2
20108		 or    $4,$0,$14
20109		 jalr  $25
20110		 sw    $23,0x4C($21)    	 # Delay slot
20111		 lw    $15,m68k_ICount
20112		 addiu $15,$15,-20
20113		 bgez  $15,3f
20114		 lhu   $24,0x00($23)    	 # Delay slot
20115		 j     MainExit
20116	3:
20117		 sll   $7,$24,2         	 # Delay slot
20118		 addu  $7,$7,$30
20119		 lw    $7,0x00($7)
20120		 jr    $7
20121		 nop                    	 # Delay slot
20122
20123OP0_0a79:				#:
20124		 addiu $23,$23,2
20125
20126		 lh    $8,0x00($23)
20127		 addiu $23,$23,2
20128		 lhu   $14,0x00($23)
20129		 lhu   $25,0x02($23)
20130		 sll   $14,$14,16
20131		 or    $14,$14,$25
20132		 addiu $23,$23,4
20133		 lw    $25,0x80($21)
20134		 sw    $15,m68k_ICount
20135		 sw    $8,0x44($29)
20136		 sw    $14,0x40($29)
20137		 or    $4,$0,$14
20138		 jalr  $25
20139		 sw    $23,0x4C($21)    	 # Delay slot
20140		 lw    $14,0x40($29)
20141		 lw    $8,0x44($29)
20142		 lw    $15,m68k_ICount
20143		 seh   $2,$2
20144		 xor   $2,$2,$8
20145		 and   $16,$0,$0        	 # Clear Carry
20146		 and   $17,$0,$0        	 # Clear Overflow
20147		 slt   $19,$2,$0        	 # Set Sign
20148		 sltiu $18,$2,1         	 # Set Zero
20149		 lw    $25,0x8C($21)
20150		 sw    $15,m68k_ICount
20151		 or    $5,$0,$2
20152		 or    $4,$0,$14
20153		 jalr  $25
20154		 sw    $23,0x4C($21)    	 # Delay slot
20155		 lw    $15,m68k_ICount
20156		 addiu $15,$15,-24
20157		 bgez  $15,3f
20158		 lhu   $24,0x00($23)    	 # Delay slot
20159		 j     MainExit
20160	3:
20161		 sll   $7,$24,2         	 # Delay slot
20162		 addu  $7,$7,$30
20163		 lw    $7,0x00($7)
20164		 jr    $7
20165		 nop                    	 # Delay slot
20166
20167OP0_0a7c:				#:
20168		 lbu   $8,0x44($21)
20169		 andi  $8,$8,0x20       	 # Supervisor Mode ?
20170		 bne   $8,$0,9f
20171		 addiu $23,$23,2        	 # Delay slot
20172
20173		 addiu $23,$23,-2
20174		 jal   Exception
20175		 ori   $2,$0,8
20176
20177		 addiu $15,$15,-20
20178		 bgez  $15,3f
20179		 lhu   $24,0x00($23)    	 # Delay slot
20180		 j     MainExit
20181	3:
20182		 sll   $7,$24,2         	 # Delay slot
20183		 addu  $7,$7,$30
20184		 lw    $7,0x00($7)
20185		 jr    $7
20186		 nop                    	 # Delay slot
20187
20188	9:
20189		 lhu   $8,0x00($23)
20190		 addiu $23,$23,2
20191		 lbu   $2,0x44($21)
20192		 sll   $2,$2,4
20193		 or    $2,$2,$20
20194		 sll   $2,$2,1
20195		 or    $2,$2,$19
20196		 sll   $2,$2,1
20197		 or    $2,$2,$18
20198		 sll   $2,$2,1
20199		 or    $2,$2,$17
20200		 sll   $2,$2,1
20201		 or    $2,$2,$16
20202		 xor   $2,$2,$8
20203		 andi  $25,$2,0x2000    	 # User Mode ?
20204		 bne   $25,$0,0f
20205		 or    $18,$0,$2       	 # Delay slot
20206		 lw    $16,0x3C($21)
20207		 lw    $17,0x68($21)
20208		 sw    $16,0x40($21)
20209		 sw    $17,0x3C($21)
20210	0:
20211		 srl   $18,$18,8
20212		 sb    $18,0x44($21)    	 # T, S & I
20213		 or    $20,$0,$2
20214		 or    $19,$0,$2
20215		 or    $18,$0,$2
20216		 or    $17,$0,$2
20217		 or    $16,$0,$2
20218		 andi  $20,$20,0x10
20219		 andi  $19,$19,0x08
20220		 andi  $18,$18,0x04
20221		 andi  $17,$17,0x02
20222		 andi  $16,$16,0x01
20223		 srl   $20,$20,4
20224		 srl   $19,$19,3
20225		 srl   $18,$18,2
20226		 srl   $17,$17,1
20227		 addiu $15,$15,-20
20228		 bgez  $15,3f
20229		 lbu   $7,0x50($21)     	 # Delay slot
20230		 j     MainExit
20231	3:
20232 # Check for Interrupt waiting
20233
20234		 andi  $7,$7,0x07       	 # Delay slot
20235		 beq   $7,$0,3f
20236		 nop                    	 # Delay slot
20237		 j     interrupt
20238	3:
20239		 lhu   $24,0x00($23)    	 # Delay slot
20240		 sll   $7,$24,2
20241		 addu  $7,$7,$30
20242		 lw    $7,0x00($7)
20243		 jr    $7
20244		 nop                    	 # Delay slot
20245
20246OP0_0a80:				#:
20247		 addiu $23,$23,2
20248
20249		 andi  $24,$24,0x07
20250		 lhu   $8,0x00($23)
20251		 lhu   $25,0x02($23)
20252		 sll   $8,$8,16
20253		 or    $8,$8,$25
20254		 addiu $23,$23,4
20255		 sll   $24,$24,2
20256		 addu  $24,$24,$21
20257		 lw    $2,0x00($24)
20258		 xor   $2,$2,$8
20259		 and   $16,$0,$0        	 # Clear Carry
20260		 and   $17,$0,$0        	 # Clear Overflow
20261		 slt   $19,$2,$0        	 # Set Sign
20262		 sltiu $18,$2,1         	 # Set Zero
20263		 sw    $2,0x00($24)
20264		 addiu $15,$15,-16
20265		 bgez  $15,3f
20266		 lhu   $24,0x00($23)    	 # Delay slot
20267		 j     MainExit
20268	3:
20269		 sll   $7,$24,2         	 # Delay slot
20270		 addu  $7,$7,$30
20271		 lw    $7,0x00($7)
20272		 jr    $7
20273		 nop                    	 # Delay slot
20274
20275OP0_0a90:				#:
20276		 addiu $23,$23,2
20277
20278		 andi  $24,$24,0x07
20279		 lhu   $8,0x00($23)
20280		 lhu   $25,0x02($23)
20281		 sll   $8,$8,16
20282		 or    $8,$8,$25
20283		 addiu $23,$23,4
20284		 sll   $24,$24,2
20285		 addu  $24,$24,$21
20286		 lw    $14,0x20($24)
20287		 lw    $25,0x84($21)
20288		 sw    $15,m68k_ICount
20289		 sw    $8,0x44($29)
20290		 sw    $14,0x40($29)
20291		 or    $4,$0,$14
20292		 jalr  $25
20293		 sw    $23,0x4C($21)    	 # Delay slot
20294		 lw    $14,0x40($29)
20295		 lw    $8,0x44($29)
20296		 lw    $15,m68k_ICount
20297		 xor   $2,$2,$8
20298		 and   $16,$0,$0        	 # Clear Carry
20299		 and   $17,$0,$0        	 # Clear Overflow
20300		 slt   $19,$2,$0        	 # Set Sign
20301		 sltiu $18,$2,1         	 # Set Zero
20302		 lw    $25,0x90($21)
20303		 sw    $15,m68k_ICount
20304		 or    $5,$0,$2
20305		 or    $4,$0,$14
20306		 jalr  $25
20307		 sw    $23,0x4C($21)    	 # Delay slot
20308		 lw    $15,m68k_ICount
20309		 addiu $15,$15,-28
20310		 bgez  $15,3f
20311		 lhu   $24,0x00($23)    	 # Delay slot
20312		 j     MainExit
20313	3:
20314		 sll   $7,$24,2         	 # Delay slot
20315		 addu  $7,$7,$30
20316		 lw    $7,0x00($7)
20317		 jr    $7
20318		 nop                    	 # Delay slot
20319
20320OP0_0a98:				#:
20321		 addiu $23,$23,2
20322
20323		 andi  $24,$24,0x07
20324		 lhu   $8,0x00($23)
20325		 lhu   $25,0x02($23)
20326		 sll   $8,$8,16
20327		 or    $8,$8,$25
20328		 addiu $23,$23,4
20329		 sll   $24,$24,2
20330		 addu  $24,$24,$21
20331		 lw    $14,0x20($24)
20332		 addiu $25,$14,4
20333		 sw    $25,0x20($24)
20334		 lw    $25,0x84($21)
20335		 sw    $15,m68k_ICount
20336		 sw    $8,0x44($29)
20337		 sw    $14,0x40($29)
20338		 or    $4,$0,$14
20339		 jalr  $25
20340		 sw    $23,0x4C($21)    	 # Delay slot
20341		 lw    $14,0x40($29)
20342		 lw    $8,0x44($29)
20343		 lw    $15,m68k_ICount
20344		 xor   $2,$2,$8
20345		 and   $16,$0,$0        	 # Clear Carry
20346		 and   $17,$0,$0        	 # Clear Overflow
20347		 slt   $19,$2,$0        	 # Set Sign
20348		 sltiu $18,$2,1         	 # Set Zero
20349		 lw    $25,0x90($21)
20350		 sw    $15,m68k_ICount
20351		 or    $5,$0,$2
20352		 or    $4,$0,$14
20353		 jalr  $25
20354		 sw    $23,0x4C($21)    	 # Delay slot
20355		 lw    $15,m68k_ICount
20356		 addiu $15,$15,-28
20357		 bgez  $15,3f
20358		 lhu   $24,0x00($23)    	 # Delay slot
20359		 j     MainExit
20360	3:
20361		 sll   $7,$24,2         	 # Delay slot
20362		 addu  $7,$7,$30
20363		 lw    $7,0x00($7)
20364		 jr    $7
20365		 nop                    	 # Delay slot
20366
20367OP0_0aa0:				#:
20368		 addiu $23,$23,2
20369
20370		 andi  $24,$24,0x07
20371		 lhu   $8,0x00($23)
20372		 lhu   $25,0x02($23)
20373		 sll   $8,$8,16
20374		 or    $8,$8,$25
20375		 addiu $23,$23,4
20376		 sll   $24,$24,2
20377		 addu  $24,$24,$21
20378		 lw    $14,0x20($24)
20379		 addiu $14,$14,-4
20380		 sw    $14,0x20($24)
20381		 lw    $25,0x84($21)
20382		 sw    $15,m68k_ICount
20383		 sw    $8,0x44($29)
20384		 sw    $14,0x40($29)
20385		 or    $4,$0,$14
20386		 jalr  $25
20387		 sw    $23,0x4C($21)    	 # Delay slot
20388		 lw    $14,0x40($29)
20389		 lw    $8,0x44($29)
20390		 lw    $15,m68k_ICount
20391		 xor   $2,$2,$8
20392		 and   $16,$0,$0        	 # Clear Carry
20393		 and   $17,$0,$0        	 # Clear Overflow
20394		 slt   $19,$2,$0        	 # Set Sign
20395		 sltiu $18,$2,1         	 # Set Zero
20396		 lw    $25,0x90($21)
20397		 sw    $15,m68k_ICount
20398		 or    $5,$0,$2
20399		 or    $4,$0,$14
20400		 jalr  $25
20401		 sw    $23,0x4C($21)    	 # Delay slot
20402		 lw    $15,m68k_ICount
20403		 addiu $15,$15,-30
20404		 bgez  $15,3f
20405		 lhu   $24,0x00($23)    	 # Delay slot
20406		 j     MainExit
20407	3:
20408		 sll   $7,$24,2         	 # Delay slot
20409		 addu  $7,$7,$30
20410		 lw    $7,0x00($7)
20411		 jr    $7
20412		 nop                    	 # Delay slot
20413
20414OP0_0aa8:				#:
20415		 addiu $23,$23,2
20416
20417		 andi  $24,$24,0x07
20418		 lhu   $8,0x00($23)
20419		 lhu   $25,0x02($23)
20420		 sll   $8,$8,16
20421		 or    $8,$8,$25
20422		 addiu $23,$23,4
20423		 lh    $7,0x00($23)
20424		 sll   $24,$24,2
20425		 addu  $24,$24,$21
20426		 lw    $14,0x20($24)
20427		 addiu $23,$23,2
20428		 addu  $14,$14,$7
20429		 lw    $25,0x84($21)
20430		 sw    $15,m68k_ICount
20431		 sw    $8,0x44($29)
20432		 sw    $14,0x40($29)
20433		 or    $4,$0,$14
20434		 jalr  $25
20435		 sw    $23,0x4C($21)    	 # Delay slot
20436		 lw    $14,0x40($29)
20437		 lw    $8,0x44($29)
20438		 lw    $15,m68k_ICount
20439		 xor   $2,$2,$8
20440		 and   $16,$0,$0        	 # Clear Carry
20441		 and   $17,$0,$0        	 # Clear Overflow
20442		 slt   $19,$2,$0        	 # Set Sign
20443		 sltiu $18,$2,1         	 # Set Zero
20444		 lw    $25,0x90($21)
20445		 sw    $15,m68k_ICount
20446		 or    $5,$0,$2
20447		 or    $4,$0,$14
20448		 jalr  $25
20449		 sw    $23,0x4C($21)    	 # Delay slot
20450		 lw    $15,m68k_ICount
20451		 addiu $15,$15,-32
20452		 bgez  $15,3f
20453		 lhu   $24,0x00($23)    	 # Delay slot
20454		 j     MainExit
20455	3:
20456		 sll   $7,$24,2         	 # Delay slot
20457		 addu  $7,$7,$30
20458		 lw    $7,0x00($7)
20459		 jr    $7
20460		 nop                    	 # Delay slot
20461
20462OP0_0ab0:				#:
20463		 addiu $23,$23,2
20464
20465		 andi  $24,$24,0x07
20466		 lhu   $8,0x00($23)
20467		 lhu   $25,0x02($23)
20468		 sll   $8,$8,16
20469		 or    $8,$8,$25
20470		 addiu $23,$23,4
20471		 sll   $24,$24,2
20472		 addu  $24,$24,$21
20473		 lw    $14,0x20($24)
20474		 lhu   $7,0x00($23)
20475		 addiu $23,$23,2
20476		 seb   $6,$7
20477		 or    $25,$0,$7
20478		 srl   $7,$7,12
20479		 andi  $25,$25,0x0800
20480		 sll   $7,$7,2
20481		 addu  $7,$7,$21
20482		 bne   $25,$0,0f
20483		 lw    $25,0x00($7)      	 # Delay slot
20484		 seh   $25,$25
20485	0:
20486		 addu  $25,$14,$25
20487		 addu  $14,$25,$6
20488		 lw    $25,0x84($21)
20489		 sw    $15,m68k_ICount
20490		 sw    $8,0x44($29)
20491		 sw    $14,0x40($29)
20492		 or    $4,$0,$14
20493		 jalr  $25
20494		 sw    $23,0x4C($21)    	 # Delay slot
20495		 lw    $14,0x40($29)
20496		 lw    $8,0x44($29)
20497		 lw    $15,m68k_ICount
20498		 xor   $2,$2,$8
20499		 and   $16,$0,$0        	 # Clear Carry
20500		 and   $17,$0,$0        	 # Clear Overflow
20501		 slt   $19,$2,$0        	 # Set Sign
20502		 sltiu $18,$2,1         	 # Set Zero
20503		 lw    $25,0x90($21)
20504		 sw    $15,m68k_ICount
20505		 or    $5,$0,$2
20506		 or    $4,$0,$14
20507		 jalr  $25
20508		 sw    $23,0x4C($21)    	 # Delay slot
20509		 lw    $15,m68k_ICount
20510		 addiu $15,$15,-34
20511		 bgez  $15,3f
20512		 lhu   $24,0x00($23)    	 # Delay slot
20513		 j     MainExit
20514	3:
20515		 sll   $7,$24,2         	 # Delay slot
20516		 addu  $7,$7,$30
20517		 lw    $7,0x00($7)
20518		 jr    $7
20519		 nop                    	 # Delay slot
20520
20521OP0_0ab8:				#:
20522		 addiu $23,$23,2
20523
20524		 lhu   $8,0x00($23)
20525		 lhu   $25,0x02($23)
20526		 sll   $8,$8,16
20527		 or    $8,$8,$25
20528		 addiu $23,$23,4
20529		 lh    $14,0x00($23)
20530		 addiu $23,$23,2
20531		 lw    $25,0x84($21)
20532		 sw    $15,m68k_ICount
20533		 sw    $8,0x44($29)
20534		 sw    $14,0x40($29)
20535		 or    $4,$0,$14
20536		 jalr  $25
20537		 sw    $23,0x4C($21)    	 # Delay slot
20538		 lw    $14,0x40($29)
20539		 lw    $8,0x44($29)
20540		 lw    $15,m68k_ICount
20541		 xor   $2,$2,$8
20542		 and   $16,$0,$0        	 # Clear Carry
20543		 and   $17,$0,$0        	 # Clear Overflow
20544		 slt   $19,$2,$0        	 # Set Sign
20545		 sltiu $18,$2,1         	 # Set Zero
20546		 lw    $25,0x90($21)
20547		 sw    $15,m68k_ICount
20548		 or    $5,$0,$2
20549		 or    $4,$0,$14
20550		 jalr  $25
20551		 sw    $23,0x4C($21)    	 # Delay slot
20552		 lw    $15,m68k_ICount
20553		 addiu $15,$15,-32
20554		 bgez  $15,3f
20555		 lhu   $24,0x00($23)    	 # Delay slot
20556		 j     MainExit
20557	3:
20558		 sll   $7,$24,2         	 # Delay slot
20559		 addu  $7,$7,$30
20560		 lw    $7,0x00($7)
20561		 jr    $7
20562		 nop                    	 # Delay slot
20563
20564OP0_0ab9:				#:
20565		 addiu $23,$23,2
20566
20567		 lhu   $8,0x00($23)
20568		 lhu   $25,0x02($23)
20569		 sll   $8,$8,16
20570		 or    $8,$8,$25
20571		 addiu $23,$23,4
20572		 lhu   $14,0x00($23)
20573		 lhu   $25,0x02($23)
20574		 sll   $14,$14,16
20575		 or    $14,$14,$25
20576		 addiu $23,$23,4
20577		 lw    $25,0x84($21)
20578		 sw    $15,m68k_ICount
20579		 sw    $8,0x44($29)
20580		 sw    $14,0x40($29)
20581		 or    $4,$0,$14
20582		 jalr  $25
20583		 sw    $23,0x4C($21)    	 # Delay slot
20584		 lw    $14,0x40($29)
20585		 lw    $8,0x44($29)
20586		 lw    $15,m68k_ICount
20587		 xor   $2,$2,$8
20588		 and   $16,$0,$0        	 # Clear Carry
20589		 and   $17,$0,$0        	 # Clear Overflow
20590		 slt   $19,$2,$0        	 # Set Sign
20591		 sltiu $18,$2,1         	 # Set Zero
20592		 lw    $25,0x90($21)
20593		 sw    $15,m68k_ICount
20594		 or    $5,$0,$2
20595		 or    $4,$0,$14
20596		 jalr  $25
20597		 sw    $23,0x4C($21)    	 # Delay slot
20598		 lw    $15,m68k_ICount
20599		 addiu $15,$15,-36
20600		 bgez  $15,3f
20601		 lhu   $24,0x00($23)    	 # Delay slot
20602		 j     MainExit
20603	3:
20604		 sll   $7,$24,2         	 # Delay slot
20605		 addu  $7,$7,$30
20606		 lw    $7,0x00($7)
20607		 jr    $7
20608		 nop                    	 # Delay slot
20609
20610OP0_0c00:				#:
20611		 addiu $23,$23,2
20612
20613		 andi  $24,$24,0x07
20614		 lb    $8,0x00($23)
20615		 addiu $23,$23,2
20616		 sll   $24,$24,2
20617		 addu  $24,$24,$21
20618		 lb    $2,0x00($24)
20619		 subu  $9,$2,$8
20620		 sltu  $16,$2,$8       	 # Set Carry
20621		 xor   $17,$2,$8
20622		 xor   $25,$9,$2
20623		 and   $17,$17,$25
20624		 srl   $17,$17,7
20625		 andi  $17,$17,0x01     	 # Set Overflow
20626		 seb  $25,$9
20627		 slt   $19,$25,$0        	 # Set Sign
20628		 sltiu $18,$25,1         	 # Set Zero
20629		 addiu $15,$15,-8
20630		 bgez  $15,3f
20631		 lhu   $24,0x00($23)    	 # Delay slot
20632		 j     MainExit
20633	3:
20634		 sll   $7,$24,2         	 # Delay slot
20635		 addu  $7,$7,$30
20636		 lw    $7,0x00($7)
20637		 jr    $7
20638		 nop                    	 # Delay slot
20639
20640OP0_0c10:				#:
20641		 addiu $23,$23,2
20642
20643		 andi  $24,$24,0x07
20644		 lb    $8,0x00($23)
20645		 addiu $23,$23,2
20646		 sll   $24,$24,2
20647		 addu  $24,$24,$21
20648		 lw    $14,0x20($24)
20649		 lw    $25,0x7C($21)
20650		 sw    $15,m68k_ICount
20651		 sw    $8,0x44($29)
20652		 or    $4,$0,$14
20653		 jalr  $25
20654		 sw    $23,0x4C($21)    	 # Delay slot
20655		 lw    $8,0x44($29)
20656		 lw    $15,m68k_ICount
20657		 seb   $2,$2
20658		 subu  $9,$2,$8
20659		 sltu  $16,$2,$8       	 # Set Carry
20660		 xor   $17,$2,$8
20661		 xor   $25,$9,$2
20662		 and   $17,$17,$25
20663		 srl   $17,$17,7
20664		 andi  $17,$17,0x01     	 # Set Overflow
20665		 seb  $25,$9
20666		 slt   $19,$25,$0        	 # Set Sign
20667		 sltiu $18,$25,1         	 # Set Zero
20668		 addiu $15,$15,-12
20669		 bgez  $15,3f
20670		 lhu   $24,0x00($23)    	 # Delay slot
20671		 j     MainExit
20672	3:
20673		 sll   $7,$24,2         	 # Delay slot
20674		 addu  $7,$7,$30
20675		 lw    $7,0x00($7)
20676		 jr    $7
20677		 nop                    	 # Delay slot
20678
20679OP0_0c18:				#:
20680		 addiu $23,$23,2
20681
20682		 andi  $24,$24,0x07
20683		 lb    $8,0x00($23)
20684		 addiu $23,$23,2
20685		 sll   $24,$24,2
20686		 addu  $24,$24,$21
20687		 lw    $14,0x20($24)
20688		 addiu $25,$14,1
20689		 sw    $25,0x20($24)
20690		 lw    $25,0x7C($21)
20691		 sw    $15,m68k_ICount
20692		 sw    $8,0x44($29)
20693		 or    $4,$0,$14
20694		 jalr  $25
20695		 sw    $23,0x4C($21)    	 # Delay slot
20696		 lw    $8,0x44($29)
20697		 lw    $15,m68k_ICount
20698		 seb   $2,$2
20699		 subu  $9,$2,$8
20700		 sltu  $16,$2,$8       	 # Set Carry
20701		 xor   $17,$2,$8
20702		 xor   $25,$9,$2
20703		 and   $17,$17,$25
20704		 srl   $17,$17,7
20705		 andi  $17,$17,0x01     	 # Set Overflow
20706		 seb  $25,$9
20707		 slt   $19,$25,$0        	 # Set Sign
20708		 sltiu $18,$25,1         	 # Set Zero
20709		 addiu $15,$15,-12
20710		 bgez  $15,3f
20711		 lhu   $24,0x00($23)    	 # Delay slot
20712		 j     MainExit
20713	3:
20714		 sll   $7,$24,2         	 # Delay slot
20715		 addu  $7,$7,$30
20716		 lw    $7,0x00($7)
20717		 jr    $7
20718		 nop                    	 # Delay slot
20719
20720OP0_0c1f:				#:
20721		 addiu $23,$23,2
20722
20723		 lb    $8,0x00($23)
20724		 addiu $23,$23,2
20725		 lw    $14,0x3C($21)    	 # Get A7
20726		 addiu $25,$14,2
20727		 sw    $25,0x3C($21)
20728		 lw    $25,0x7C($21)
20729		 sw    $15,m68k_ICount
20730		 sw    $8,0x44($29)
20731		 or    $4,$0,$14
20732		 jalr  $25
20733		 sw    $23,0x4C($21)    	 # Delay slot
20734		 lw    $8,0x44($29)
20735		 lw    $15,m68k_ICount
20736		 seb   $2,$2
20737		 subu  $9,$2,$8
20738		 sltu  $16,$2,$8       	 # Set Carry
20739		 xor   $17,$2,$8
20740		 xor   $25,$9,$2
20741		 and   $17,$17,$25
20742		 srl   $17,$17,7
20743		 andi  $17,$17,0x01     	 # Set Overflow
20744		 seb  $25,$9
20745		 slt   $19,$25,$0        	 # Set Sign
20746		 sltiu $18,$25,1         	 # Set Zero
20747		 addiu $15,$15,-12
20748		 bgez  $15,3f
20749		 lhu   $24,0x00($23)    	 # Delay slot
20750		 j     MainExit
20751	3:
20752		 sll   $7,$24,2         	 # Delay slot
20753		 addu  $7,$7,$30
20754		 lw    $7,0x00($7)
20755		 jr    $7
20756		 nop                    	 # Delay slot
20757
20758OP0_0c20:				#:
20759		 addiu $23,$23,2
20760
20761		 andi  $24,$24,0x07
20762		 lb    $8,0x00($23)
20763		 addiu $23,$23,2
20764		 sll   $24,$24,2
20765		 addu  $24,$24,$21
20766		 lw    $14,0x20($24)
20767		 addiu $14,$14,-1
20768		 sw    $14,0x20($24)
20769		 lw    $25,0x7C($21)
20770		 sw    $15,m68k_ICount
20771		 sw    $8,0x44($29)
20772		 or    $4,$0,$14
20773		 jalr  $25
20774		 sw    $23,0x4C($21)    	 # Delay slot
20775		 lw    $8,0x44($29)
20776		 lw    $15,m68k_ICount
20777		 seb   $2,$2
20778		 subu  $9,$2,$8
20779		 sltu  $16,$2,$8       	 # Set Carry
20780		 xor   $17,$2,$8
20781		 xor   $25,$9,$2
20782		 and   $17,$17,$25
20783		 srl   $17,$17,7
20784		 andi  $17,$17,0x01     	 # Set Overflow
20785		 seb  $25,$9
20786		 slt   $19,$25,$0        	 # Set Sign
20787		 sltiu $18,$25,1         	 # Set Zero
20788		 addiu $15,$15,-14
20789		 bgez  $15,3f
20790		 lhu   $24,0x00($23)    	 # Delay slot
20791		 j     MainExit
20792	3:
20793		 sll   $7,$24,2         	 # Delay slot
20794		 addu  $7,$7,$30
20795		 lw    $7,0x00($7)
20796		 jr    $7
20797		 nop                    	 # Delay slot
20798
20799OP0_0c27:				#:
20800		 addiu $23,$23,2
20801
20802		 lb    $8,0x00($23)
20803		 addiu $23,$23,2
20804		 lw    $14,0x3C($21)    	 # Get A7
20805		 addiu $14,$14,-2
20806		 sw    $14,0x3C($21)
20807		 lw    $25,0x7C($21)
20808		 sw    $15,m68k_ICount
20809		 sw    $8,0x44($29)
20810		 or    $4,$0,$14
20811		 jalr  $25
20812		 sw    $23,0x4C($21)    	 # Delay slot
20813		 lw    $8,0x44($29)
20814		 lw    $15,m68k_ICount
20815		 seb   $2,$2
20816		 subu  $9,$2,$8
20817		 sltu  $16,$2,$8       	 # Set Carry
20818		 xor   $17,$2,$8
20819		 xor   $25,$9,$2
20820		 and   $17,$17,$25
20821		 srl   $17,$17,7
20822		 andi  $17,$17,0x01     	 # Set Overflow
20823		 seb  $25,$9
20824		 slt   $19,$25,$0        	 # Set Sign
20825		 sltiu $18,$25,1         	 # Set Zero
20826		 addiu $15,$15,-14
20827		 bgez  $15,3f
20828		 lhu   $24,0x00($23)    	 # Delay slot
20829		 j     MainExit
20830	3:
20831		 sll   $7,$24,2         	 # Delay slot
20832		 addu  $7,$7,$30
20833		 lw    $7,0x00($7)
20834		 jr    $7
20835		 nop                    	 # Delay slot
20836
20837OP0_0c28:				#:
20838		 addiu $23,$23,2
20839
20840		 andi  $24,$24,0x07
20841		 lb    $8,0x00($23)
20842		 addiu $23,$23,2
20843		 lh    $7,0x00($23)
20844		 sll   $24,$24,2
20845		 addu  $24,$24,$21
20846		 lw    $14,0x20($24)
20847		 addiu $23,$23,2
20848		 addu  $14,$14,$7
20849		 lw    $25,0x7C($21)
20850		 sw    $15,m68k_ICount
20851		 sw    $8,0x44($29)
20852		 or    $4,$0,$14
20853		 jalr  $25
20854		 sw    $23,0x4C($21)    	 # Delay slot
20855		 lw    $8,0x44($29)
20856		 lw    $15,m68k_ICount
20857		 seb   $2,$2
20858		 subu  $9,$2,$8
20859		 sltu  $16,$2,$8       	 # Set Carry
20860		 xor   $17,$2,$8
20861		 xor   $25,$9,$2
20862		 and   $17,$17,$25
20863		 srl   $17,$17,7
20864		 andi  $17,$17,0x01     	 # Set Overflow
20865		 seb  $25,$9
20866		 slt   $19,$25,$0        	 # Set Sign
20867		 sltiu $18,$25,1         	 # Set Zero
20868		 addiu $15,$15,-16
20869		 bgez  $15,3f
20870		 lhu   $24,0x00($23)    	 # Delay slot
20871		 j     MainExit
20872	3:
20873		 sll   $7,$24,2         	 # Delay slot
20874		 addu  $7,$7,$30
20875		 lw    $7,0x00($7)
20876		 jr    $7
20877		 nop                    	 # Delay slot
20878
20879OP0_0c30:				#:
20880		 addiu $23,$23,2
20881
20882		 andi  $24,$24,0x07
20883		 lb    $8,0x00($23)
20884		 addiu $23,$23,2
20885		 sll   $24,$24,2
20886		 addu  $24,$24,$21
20887		 lw    $14,0x20($24)
20888		 lhu   $7,0x00($23)
20889		 addiu $23,$23,2
20890		 seb   $6,$7
20891		 or    $25,$0,$7
20892		 srl   $7,$7,12
20893		 andi  $25,$25,0x0800
20894		 sll   $7,$7,2
20895		 addu  $7,$7,$21
20896		 bne   $25,$0,0f
20897		 lw    $25,0x00($7)      	 # Delay slot
20898		 seh   $25,$25
20899	0:
20900		 addu  $25,$14,$25
20901		 addu  $14,$25,$6
20902		 lw    $25,0x7C($21)
20903		 sw    $15,m68k_ICount
20904		 sw    $8,0x44($29)
20905		 or    $4,$0,$14
20906		 jalr  $25
20907		 sw    $23,0x4C($21)    	 # Delay slot
20908		 lw    $8,0x44($29)
20909		 lw    $15,m68k_ICount
20910		 seb   $2,$2
20911		 subu  $9,$2,$8
20912		 sltu  $16,$2,$8       	 # Set Carry
20913		 xor   $17,$2,$8
20914		 xor   $25,$9,$2
20915		 and   $17,$17,$25
20916		 srl   $17,$17,7
20917		 andi  $17,$17,0x01     	 # Set Overflow
20918		 seb  $25,$9
20919		 slt   $19,$25,$0        	 # Set Sign
20920		 sltiu $18,$25,1         	 # Set Zero
20921		 addiu $15,$15,-18
20922		 bgez  $15,3f
20923		 lhu   $24,0x00($23)    	 # Delay slot
20924		 j     MainExit
20925	3:
20926		 sll   $7,$24,2         	 # Delay slot
20927		 addu  $7,$7,$30
20928		 lw    $7,0x00($7)
20929		 jr    $7
20930		 nop                    	 # Delay slot
20931
20932OP0_0c38:				#:
20933		 addiu $23,$23,2
20934
20935		 lb    $8,0x00($23)
20936		 addiu $23,$23,2
20937		 lh    $14,0x00($23)
20938		 addiu $23,$23,2
20939		 lw    $25,0x7C($21)
20940		 sw    $15,m68k_ICount
20941		 sw    $8,0x44($29)
20942		 or    $4,$0,$14
20943		 jalr  $25
20944		 sw    $23,0x4C($21)    	 # Delay slot
20945		 lw    $8,0x44($29)
20946		 lw    $15,m68k_ICount
20947		 seb   $2,$2
20948		 subu  $9,$2,$8
20949		 sltu  $16,$2,$8       	 # Set Carry
20950		 xor   $17,$2,$8
20951		 xor   $25,$9,$2
20952		 and   $17,$17,$25
20953		 srl   $17,$17,7
20954		 andi  $17,$17,0x01     	 # Set Overflow
20955		 seb  $25,$9
20956		 slt   $19,$25,$0        	 # Set Sign
20957		 sltiu $18,$25,1         	 # Set Zero
20958		 addiu $15,$15,-16
20959		 bgez  $15,3f
20960		 lhu   $24,0x00($23)    	 # Delay slot
20961		 j     MainExit
20962	3:
20963		 sll   $7,$24,2         	 # Delay slot
20964		 addu  $7,$7,$30
20965		 lw    $7,0x00($7)
20966		 jr    $7
20967		 nop                    	 # Delay slot
20968
20969OP0_0c39:				#:
20970		 addiu $23,$23,2
20971
20972		 lb    $8,0x00($23)
20973		 addiu $23,$23,2
20974		 lhu   $14,0x00($23)
20975		 lhu   $25,0x02($23)
20976		 sll   $14,$14,16
20977		 or    $14,$14,$25
20978		 addiu $23,$23,4
20979		 lw    $25,0x7C($21)
20980		 sw    $15,m68k_ICount
20981		 sw    $8,0x44($29)
20982		 or    $4,$0,$14
20983		 jalr  $25
20984		 sw    $23,0x4C($21)    	 # Delay slot
20985		 lw    $8,0x44($29)
20986		 lw    $15,m68k_ICount
20987		 seb   $2,$2
20988		 subu  $9,$2,$8
20989		 sltu  $16,$2,$8       	 # Set Carry
20990		 xor   $17,$2,$8
20991		 xor   $25,$9,$2
20992		 and   $17,$17,$25
20993		 srl   $17,$17,7
20994		 andi  $17,$17,0x01     	 # Set Overflow
20995		 seb  $25,$9
20996		 slt   $19,$25,$0        	 # Set Sign
20997		 sltiu $18,$25,1         	 # Set Zero
20998		 addiu $15,$15,-20
20999		 bgez  $15,3f
21000		 lhu   $24,0x00($23)    	 # Delay slot
21001		 j     MainExit
21002	3:
21003		 sll   $7,$24,2         	 # Delay slot
21004		 addu  $7,$7,$30
21005		 lw    $7,0x00($7)
21006		 jr    $7
21007		 nop                    	 # Delay slot
21008
21009OP0_0c40:				#:
21010		 addiu $23,$23,2
21011
21012		 andi  $24,$24,0x07
21013		 lh    $8,0x00($23)
21014		 addiu $23,$23,2
21015		 sll   $24,$24,2
21016		 addu  $24,$24,$21
21017		 lh    $2,0x00($24)
21018		 subu  $9,$2,$8
21019		 sltu  $16,$2,$8       	 # Set Carry
21020		 xor   $17,$2,$8
21021		 xor   $25,$9,$2
21022		 and   $17,$17,$25
21023		 srl   $17,$17,15
21024		 andi  $17,$17,0x01     	 # Set Overflow
21025		 seh  $25,$9
21026		 slt   $19,$25,$0        	 # Set Sign
21027		 sltiu $18,$25,1         	 # Set Zero
21028		 addiu $15,$15,-8
21029		 bgez  $15,3f
21030		 lhu   $24,0x00($23)    	 # Delay slot
21031		 j     MainExit
21032	3:
21033		 sll   $7,$24,2         	 # Delay slot
21034		 addu  $7,$7,$30
21035		 lw    $7,0x00($7)
21036		 jr    $7
21037		 nop                    	 # Delay slot
21038
21039OP0_0c50:				#:
21040		 addiu $23,$23,2
21041
21042		 andi  $24,$24,0x07
21043		 lh    $8,0x00($23)
21044		 addiu $23,$23,2
21045		 sll   $24,$24,2
21046		 addu  $24,$24,$21
21047		 lw    $14,0x20($24)
21048		 lw    $25,0x80($21)
21049		 sw    $15,m68k_ICount
21050		 sw    $8,0x44($29)
21051		 or    $4,$0,$14
21052		 jalr  $25
21053		 sw    $23,0x4C($21)    	 # Delay slot
21054		 lw    $8,0x44($29)
21055		 lw    $15,m68k_ICount
21056		 seh   $2,$2
21057		 subu  $9,$2,$8
21058		 sltu  $16,$2,$8       	 # Set Carry
21059		 xor   $17,$2,$8
21060		 xor   $25,$9,$2
21061		 and   $17,$17,$25
21062		 srl   $17,$17,15
21063		 andi  $17,$17,0x01     	 # Set Overflow
21064		 seh  $25,$9
21065		 slt   $19,$25,$0        	 # Set Sign
21066		 sltiu $18,$25,1         	 # Set Zero
21067		 addiu $15,$15,-12
21068		 bgez  $15,3f
21069		 lhu   $24,0x00($23)    	 # Delay slot
21070		 j     MainExit
21071	3:
21072		 sll   $7,$24,2         	 # Delay slot
21073		 addu  $7,$7,$30
21074		 lw    $7,0x00($7)
21075		 jr    $7
21076		 nop                    	 # Delay slot
21077
21078OP0_0c58:				#:
21079		 addiu $23,$23,2
21080
21081		 andi  $24,$24,0x07
21082		 lh    $8,0x00($23)
21083		 addiu $23,$23,2
21084		 sll   $24,$24,2
21085		 addu  $24,$24,$21
21086		 lw    $14,0x20($24)
21087		 addiu $25,$14,2
21088		 sw    $25,0x20($24)
21089		 lw    $25,0x80($21)
21090		 sw    $15,m68k_ICount
21091		 sw    $8,0x44($29)
21092		 or    $4,$0,$14
21093		 jalr  $25
21094		 sw    $23,0x4C($21)    	 # Delay slot
21095		 lw    $8,0x44($29)
21096		 lw    $15,m68k_ICount
21097		 seh   $2,$2
21098		 subu  $9,$2,$8
21099		 sltu  $16,$2,$8       	 # Set Carry
21100		 xor   $17,$2,$8
21101		 xor   $25,$9,$2
21102		 and   $17,$17,$25
21103		 srl   $17,$17,15
21104		 andi  $17,$17,0x01     	 # Set Overflow
21105		 seh  $25,$9
21106		 slt   $19,$25,$0        	 # Set Sign
21107		 sltiu $18,$25,1         	 # Set Zero
21108		 addiu $15,$15,-12
21109		 bgez  $15,3f
21110		 lhu   $24,0x00($23)    	 # Delay slot
21111		 j     MainExit
21112	3:
21113		 sll   $7,$24,2         	 # Delay slot
21114		 addu  $7,$7,$30
21115		 lw    $7,0x00($7)
21116		 jr    $7
21117		 nop                    	 # Delay slot
21118
21119OP0_0c60:				#:
21120		 addiu $23,$23,2
21121
21122		 andi  $24,$24,0x07
21123		 lh    $8,0x00($23)
21124		 addiu $23,$23,2
21125		 sll   $24,$24,2
21126		 addu  $24,$24,$21
21127		 lw    $14,0x20($24)
21128		 addiu $14,$14,-2
21129		 sw    $14,0x20($24)
21130		 lw    $25,0x80($21)
21131		 sw    $15,m68k_ICount
21132		 sw    $8,0x44($29)
21133		 or    $4,$0,$14
21134		 jalr  $25
21135		 sw    $23,0x4C($21)    	 # Delay slot
21136		 lw    $8,0x44($29)
21137		 lw    $15,m68k_ICount
21138		 seh   $2,$2
21139		 subu  $9,$2,$8
21140		 sltu  $16,$2,$8       	 # Set Carry
21141		 xor   $17,$2,$8
21142		 xor   $25,$9,$2
21143		 and   $17,$17,$25
21144		 srl   $17,$17,15
21145		 andi  $17,$17,0x01     	 # Set Overflow
21146		 seh  $25,$9
21147		 slt   $19,$25,$0        	 # Set Sign
21148		 sltiu $18,$25,1         	 # Set Zero
21149		 addiu $15,$15,-14
21150		 bgez  $15,3f
21151		 lhu   $24,0x00($23)    	 # Delay slot
21152		 j     MainExit
21153	3:
21154		 sll   $7,$24,2         	 # Delay slot
21155		 addu  $7,$7,$30
21156		 lw    $7,0x00($7)
21157		 jr    $7
21158		 nop                    	 # Delay slot
21159
21160OP0_0c68:				#:
21161		 addiu $23,$23,2
21162
21163		 andi  $24,$24,0x07
21164		 lh    $8,0x00($23)
21165		 addiu $23,$23,2
21166		 lh    $7,0x00($23)
21167		 sll   $24,$24,2
21168		 addu  $24,$24,$21
21169		 lw    $14,0x20($24)
21170		 addiu $23,$23,2
21171		 addu  $14,$14,$7
21172		 lw    $25,0x80($21)
21173		 sw    $15,m68k_ICount
21174		 sw    $8,0x44($29)
21175		 or    $4,$0,$14
21176		 jalr  $25
21177		 sw    $23,0x4C($21)    	 # Delay slot
21178		 lw    $8,0x44($29)
21179		 lw    $15,m68k_ICount
21180		 seh   $2,$2
21181		 subu  $9,$2,$8
21182		 sltu  $16,$2,$8       	 # Set Carry
21183		 xor   $17,$2,$8
21184		 xor   $25,$9,$2
21185		 and   $17,$17,$25
21186		 srl   $17,$17,15
21187		 andi  $17,$17,0x01     	 # Set Overflow
21188		 seh  $25,$9
21189		 slt   $19,$25,$0        	 # Set Sign
21190		 sltiu $18,$25,1         	 # Set Zero
21191		 addiu $15,$15,-16
21192		 bgez  $15,3f
21193		 lhu   $24,0x00($23)    	 # Delay slot
21194		 j     MainExit
21195	3:
21196		 sll   $7,$24,2         	 # Delay slot
21197		 addu  $7,$7,$30
21198		 lw    $7,0x00($7)
21199		 jr    $7
21200		 nop                    	 # Delay slot
21201
21202OP0_0c70:				#:
21203		 addiu $23,$23,2
21204
21205		 andi  $24,$24,0x07
21206		 lh    $8,0x00($23)
21207		 addiu $23,$23,2
21208		 sll   $24,$24,2
21209		 addu  $24,$24,$21
21210		 lw    $14,0x20($24)
21211		 lhu   $7,0x00($23)
21212		 addiu $23,$23,2
21213		 seb   $6,$7
21214		 or    $25,$0,$7
21215		 srl   $7,$7,12
21216		 andi  $25,$25,0x0800
21217		 sll   $7,$7,2
21218		 addu  $7,$7,$21
21219		 bne   $25,$0,0f
21220		 lw    $25,0x00($7)      	 # Delay slot
21221		 seh   $25,$25
21222	0:
21223		 addu  $25,$14,$25
21224		 addu  $14,$25,$6
21225		 lw    $25,0x80($21)
21226		 sw    $15,m68k_ICount
21227		 sw    $8,0x44($29)
21228		 or    $4,$0,$14
21229		 jalr  $25
21230		 sw    $23,0x4C($21)    	 # Delay slot
21231		 lw    $8,0x44($29)
21232		 lw    $15,m68k_ICount
21233		 seh   $2,$2
21234		 subu  $9,$2,$8
21235		 sltu  $16,$2,$8       	 # Set Carry
21236		 xor   $17,$2,$8
21237		 xor   $25,$9,$2
21238		 and   $17,$17,$25
21239		 srl   $17,$17,15
21240		 andi  $17,$17,0x01     	 # Set Overflow
21241		 seh  $25,$9
21242		 slt   $19,$25,$0        	 # Set Sign
21243		 sltiu $18,$25,1         	 # Set Zero
21244		 addiu $15,$15,-18
21245		 bgez  $15,3f
21246		 lhu   $24,0x00($23)    	 # Delay slot
21247		 j     MainExit
21248	3:
21249		 sll   $7,$24,2         	 # Delay slot
21250		 addu  $7,$7,$30
21251		 lw    $7,0x00($7)
21252		 jr    $7
21253		 nop                    	 # Delay slot
21254
21255OP0_0c78:				#:
21256		 addiu $23,$23,2
21257
21258		 lh    $8,0x00($23)
21259		 addiu $23,$23,2
21260		 lh    $14,0x00($23)
21261		 addiu $23,$23,2
21262		 lw    $25,0x80($21)
21263		 sw    $15,m68k_ICount
21264		 sw    $8,0x44($29)
21265		 or    $4,$0,$14
21266		 jalr  $25
21267		 sw    $23,0x4C($21)    	 # Delay slot
21268		 lw    $8,0x44($29)
21269		 lw    $15,m68k_ICount
21270		 seh   $2,$2
21271		 subu  $9,$2,$8
21272		 sltu  $16,$2,$8       	 # Set Carry
21273		 xor   $17,$2,$8
21274		 xor   $25,$9,$2
21275		 and   $17,$17,$25
21276		 srl   $17,$17,15
21277		 andi  $17,$17,0x01     	 # Set Overflow
21278		 seh  $25,$9
21279		 slt   $19,$25,$0        	 # Set Sign
21280		 sltiu $18,$25,1         	 # Set Zero
21281		 addiu $15,$15,-16
21282		 bgez  $15,3f
21283		 lhu   $24,0x00($23)    	 # Delay slot
21284		 j     MainExit
21285	3:
21286		 sll   $7,$24,2         	 # Delay slot
21287		 addu  $7,$7,$30
21288		 lw    $7,0x00($7)
21289		 jr    $7
21290		 nop                    	 # Delay slot
21291
21292OP0_0c79:				#:
21293		 addiu $23,$23,2
21294
21295		 lh    $8,0x00($23)
21296		 addiu $23,$23,2
21297		 lhu   $14,0x00($23)
21298		 lhu   $25,0x02($23)
21299		 sll   $14,$14,16
21300		 or    $14,$14,$25
21301		 addiu $23,$23,4
21302		 lw    $25,0x80($21)
21303		 sw    $15,m68k_ICount
21304		 sw    $8,0x44($29)
21305		 or    $4,$0,$14
21306		 jalr  $25
21307		 sw    $23,0x4C($21)    	 # Delay slot
21308		 lw    $8,0x44($29)
21309		 lw    $15,m68k_ICount
21310		 seh   $2,$2
21311		 subu  $9,$2,$8
21312		 sltu  $16,$2,$8       	 # Set Carry
21313		 xor   $17,$2,$8
21314		 xor   $25,$9,$2
21315		 and   $17,$17,$25
21316		 srl   $17,$17,15
21317		 andi  $17,$17,0x01     	 # Set Overflow
21318		 seh  $25,$9
21319		 slt   $19,$25,$0        	 # Set Sign
21320		 sltiu $18,$25,1         	 # Set Zero
21321		 addiu $15,$15,-20
21322		 bgez  $15,3f
21323		 lhu   $24,0x00($23)    	 # Delay slot
21324		 j     MainExit
21325	3:
21326		 sll   $7,$24,2         	 # Delay slot
21327		 addu  $7,$7,$30
21328		 lw    $7,0x00($7)
21329		 jr    $7
21330		 nop                    	 # Delay slot
21331
21332OP0_0c80:				#:
21333		 addiu $23,$23,2
21334
21335		 andi  $24,$24,0x07
21336		 lhu   $8,0x00($23)
21337		 lhu   $25,0x02($23)
21338		 sll   $8,$8,16
21339		 or    $8,$8,$25
21340		 addiu $23,$23,4
21341		 sll   $24,$24,2
21342		 addu  $24,$24,$21
21343		 lw    $2,0x00($24)
21344		 subu  $9,$2,$8
21345		 sltu  $16,$2,$8       	 # Set Carry
21346		 xor   $17,$2,$8
21347		 xor   $25,$9,$2
21348		 and   $17,$17,$25
21349		 srl   $17,$17,31        	 # Set Overflow
21350		 slt   $19,$9,$0        	 # Set Sign
21351		 sltiu $18,$9,1         	 # Set Zero
21352		 addiu $15,$15,-14
21353		 bgez  $15,3f
21354		 lhu   $24,0x00($23)    	 # Delay slot
21355		 j     MainExit
21356	3:
21357		 sll   $7,$24,2         	 # Delay slot
21358		 addu  $7,$7,$30
21359		 lw    $7,0x00($7)
21360		 jr    $7
21361		 nop                    	 # Delay slot
21362
21363OP0_0c90:				#:
21364		 addiu $23,$23,2
21365
21366		 andi  $24,$24,0x07
21367		 lhu   $8,0x00($23)
21368		 lhu   $25,0x02($23)
21369		 sll   $8,$8,16
21370		 or    $8,$8,$25
21371		 addiu $23,$23,4
21372		 sll   $24,$24,2
21373		 addu  $24,$24,$21
21374		 lw    $14,0x20($24)
21375		 lw    $25,0x84($21)
21376		 sw    $15,m68k_ICount
21377		 sw    $8,0x44($29)
21378		 or    $4,$0,$14
21379		 jalr  $25
21380		 sw    $23,0x4C($21)    	 # Delay slot
21381		 lw    $8,0x44($29)
21382		 lw    $15,m68k_ICount
21383		 subu  $9,$2,$8
21384		 sltu  $16,$2,$8       	 # Set Carry
21385		 xor   $17,$2,$8
21386		 xor   $25,$9,$2
21387		 and   $17,$17,$25
21388		 srl   $17,$17,31        	 # Set Overflow
21389		 slt   $19,$9,$0        	 # Set Sign
21390		 sltiu $18,$9,1         	 # Set Zero
21391		 addiu $15,$15,-20
21392		 bgez  $15,3f
21393		 lhu   $24,0x00($23)    	 # Delay slot
21394		 j     MainExit
21395	3:
21396		 sll   $7,$24,2         	 # Delay slot
21397		 addu  $7,$7,$30
21398		 lw    $7,0x00($7)
21399		 jr    $7
21400		 nop                    	 # Delay slot
21401
21402OP0_0c98:				#:
21403		 addiu $23,$23,2
21404
21405		 andi  $24,$24,0x07
21406		 lhu   $8,0x00($23)
21407		 lhu   $25,0x02($23)
21408		 sll   $8,$8,16
21409		 or    $8,$8,$25
21410		 addiu $23,$23,4
21411		 sll   $24,$24,2
21412		 addu  $24,$24,$21
21413		 lw    $14,0x20($24)
21414		 addiu $25,$14,4
21415		 sw    $25,0x20($24)
21416		 lw    $25,0x84($21)
21417		 sw    $15,m68k_ICount
21418		 sw    $8,0x44($29)
21419		 or    $4,$0,$14
21420		 jalr  $25
21421		 sw    $23,0x4C($21)    	 # Delay slot
21422		 lw    $8,0x44($29)
21423		 lw    $15,m68k_ICount
21424		 subu  $9,$2,$8
21425		 sltu  $16,$2,$8       	 # Set Carry
21426		 xor   $17,$2,$8
21427		 xor   $25,$9,$2
21428		 and   $17,$17,$25
21429		 srl   $17,$17,31        	 # Set Overflow
21430		 slt   $19,$9,$0        	 # Set Sign
21431		 sltiu $18,$9,1         	 # Set Zero
21432		 addiu $15,$15,-20
21433		 bgez  $15,3f
21434		 lhu   $24,0x00($23)    	 # Delay slot
21435		 j     MainExit
21436	3:
21437		 sll   $7,$24,2         	 # Delay slot
21438		 addu  $7,$7,$30
21439		 lw    $7,0x00($7)
21440		 jr    $7
21441		 nop                    	 # Delay slot
21442
21443OP0_0ca0:				#:
21444		 addiu $23,$23,2
21445
21446		 andi  $24,$24,0x07
21447		 lhu   $8,0x00($23)
21448		 lhu   $25,0x02($23)
21449		 sll   $8,$8,16
21450		 or    $8,$8,$25
21451		 addiu $23,$23,4
21452		 sll   $24,$24,2
21453		 addu  $24,$24,$21
21454		 lw    $14,0x20($24)
21455		 addiu $14,$14,-4
21456		 sw    $14,0x20($24)
21457		 lw    $25,0x84($21)
21458		 sw    $15,m68k_ICount
21459		 sw    $8,0x44($29)
21460		 or    $4,$0,$14
21461		 jalr  $25
21462		 sw    $23,0x4C($21)    	 # Delay slot
21463		 lw    $8,0x44($29)
21464		 lw    $15,m68k_ICount
21465		 subu  $9,$2,$8
21466		 sltu  $16,$2,$8       	 # Set Carry
21467		 xor   $17,$2,$8
21468		 xor   $25,$9,$2
21469		 and   $17,$17,$25
21470		 srl   $17,$17,31        	 # Set Overflow
21471		 slt   $19,$9,$0        	 # Set Sign
21472		 sltiu $18,$9,1         	 # Set Zero
21473		 addiu $15,$15,-22
21474		 bgez  $15,3f
21475		 lhu   $24,0x00($23)    	 # Delay slot
21476		 j     MainExit
21477	3:
21478		 sll   $7,$24,2         	 # Delay slot
21479		 addu  $7,$7,$30
21480		 lw    $7,0x00($7)
21481		 jr    $7
21482		 nop                    	 # Delay slot
21483
21484OP0_0ca8:				#:
21485		 addiu $23,$23,2
21486
21487		 andi  $24,$24,0x07
21488		 lhu   $8,0x00($23)
21489		 lhu   $25,0x02($23)
21490		 sll   $8,$8,16
21491		 or    $8,$8,$25
21492		 addiu $23,$23,4
21493		 lh    $7,0x00($23)
21494		 sll   $24,$24,2
21495		 addu  $24,$24,$21
21496		 lw    $14,0x20($24)
21497		 addiu $23,$23,2
21498		 addu  $14,$14,$7
21499		 lw    $25,0x84($21)
21500		 sw    $15,m68k_ICount
21501		 sw    $8,0x44($29)
21502		 or    $4,$0,$14
21503		 jalr  $25
21504		 sw    $23,0x4C($21)    	 # Delay slot
21505		 lw    $8,0x44($29)
21506		 lw    $15,m68k_ICount
21507		 subu  $9,$2,$8
21508		 sltu  $16,$2,$8       	 # Set Carry
21509		 xor   $17,$2,$8
21510		 xor   $25,$9,$2
21511		 and   $17,$17,$25
21512		 srl   $17,$17,31        	 # Set Overflow
21513		 slt   $19,$9,$0        	 # Set Sign
21514		 sltiu $18,$9,1         	 # Set Zero
21515		 addiu $15,$15,-24
21516		 bgez  $15,3f
21517		 lhu   $24,0x00($23)    	 # Delay slot
21518		 j     MainExit
21519	3:
21520		 sll   $7,$24,2         	 # Delay slot
21521		 addu  $7,$7,$30
21522		 lw    $7,0x00($7)
21523		 jr    $7
21524		 nop                    	 # Delay slot
21525
21526OP0_0cb0:				#:
21527		 addiu $23,$23,2
21528
21529		 andi  $24,$24,0x07
21530		 lhu   $8,0x00($23)
21531		 lhu   $25,0x02($23)
21532		 sll   $8,$8,16
21533		 or    $8,$8,$25
21534		 addiu $23,$23,4
21535		 sll   $24,$24,2
21536		 addu  $24,$24,$21
21537		 lw    $14,0x20($24)
21538		 lhu   $7,0x00($23)
21539		 addiu $23,$23,2
21540		 seb   $6,$7
21541		 or    $25,$0,$7
21542		 srl   $7,$7,12
21543		 andi  $25,$25,0x0800
21544		 sll   $7,$7,2
21545		 addu  $7,$7,$21
21546		 bne   $25,$0,0f
21547		 lw    $25,0x00($7)      	 # Delay slot
21548		 seh   $25,$25
21549	0:
21550		 addu  $25,$14,$25
21551		 addu  $14,$25,$6
21552		 lw    $25,0x84($21)
21553		 sw    $15,m68k_ICount
21554		 sw    $8,0x44($29)
21555		 or    $4,$0,$14
21556		 jalr  $25
21557		 sw    $23,0x4C($21)    	 # Delay slot
21558		 lw    $8,0x44($29)
21559		 lw    $15,m68k_ICount
21560		 subu  $9,$2,$8
21561		 sltu  $16,$2,$8       	 # Set Carry
21562		 xor   $17,$2,$8
21563		 xor   $25,$9,$2
21564		 and   $17,$17,$25
21565		 srl   $17,$17,31        	 # Set Overflow
21566		 slt   $19,$9,$0        	 # Set Sign
21567		 sltiu $18,$9,1         	 # Set Zero
21568		 addiu $15,$15,-26
21569		 bgez  $15,3f
21570		 lhu   $24,0x00($23)    	 # Delay slot
21571		 j     MainExit
21572	3:
21573		 sll   $7,$24,2         	 # Delay slot
21574		 addu  $7,$7,$30
21575		 lw    $7,0x00($7)
21576		 jr    $7
21577		 nop                    	 # Delay slot
21578
21579OP0_0cb8:				#:
21580		 addiu $23,$23,2
21581
21582		 lhu   $8,0x00($23)
21583		 lhu   $25,0x02($23)
21584		 sll   $8,$8,16
21585		 or    $8,$8,$25
21586		 addiu $23,$23,4
21587		 lh    $14,0x00($23)
21588		 addiu $23,$23,2
21589		 lw    $25,0x84($21)
21590		 sw    $15,m68k_ICount
21591		 sw    $8,0x44($29)
21592		 or    $4,$0,$14
21593		 jalr  $25
21594		 sw    $23,0x4C($21)    	 # Delay slot
21595		 lw    $8,0x44($29)
21596		 lw    $15,m68k_ICount
21597		 subu  $9,$2,$8
21598		 sltu  $16,$2,$8       	 # Set Carry
21599		 xor   $17,$2,$8
21600		 xor   $25,$9,$2
21601		 and   $17,$17,$25
21602		 srl   $17,$17,31        	 # Set Overflow
21603		 slt   $19,$9,$0        	 # Set Sign
21604		 sltiu $18,$9,1         	 # Set Zero
21605		 addiu $15,$15,-24
21606		 bgez  $15,3f
21607		 lhu   $24,0x00($23)    	 # Delay slot
21608		 j     MainExit
21609	3:
21610		 sll   $7,$24,2         	 # Delay slot
21611		 addu  $7,$7,$30
21612		 lw    $7,0x00($7)
21613		 jr    $7
21614		 nop                    	 # Delay slot
21615
21616OP0_0cb9:				#:
21617		 addiu $23,$23,2
21618
21619		 lhu   $8,0x00($23)
21620		 lhu   $25,0x02($23)
21621		 sll   $8,$8,16
21622		 or    $8,$8,$25
21623		 addiu $23,$23,4
21624		 lhu   $14,0x00($23)
21625		 lhu   $25,0x02($23)
21626		 sll   $14,$14,16
21627		 or    $14,$14,$25
21628		 addiu $23,$23,4
21629		 lw    $25,0x84($21)
21630		 sw    $15,m68k_ICount
21631		 sw    $8,0x44($29)
21632		 or    $4,$0,$14
21633		 jalr  $25
21634		 sw    $23,0x4C($21)    	 # Delay slot
21635		 lw    $8,0x44($29)
21636		 lw    $15,m68k_ICount
21637		 subu  $9,$2,$8
21638		 sltu  $16,$2,$8       	 # Set Carry
21639		 xor   $17,$2,$8
21640		 xor   $25,$9,$2
21641		 and   $17,$17,$25
21642		 srl   $17,$17,31        	 # Set Overflow
21643		 slt   $19,$9,$0        	 # Set Sign
21644		 sltiu $18,$9,1         	 # Set Zero
21645		 addiu $15,$15,-28
21646		 bgez  $15,3f
21647		 lhu   $24,0x00($23)    	 # Delay slot
21648		 j     MainExit
21649	3:
21650		 sll   $7,$24,2         	 # Delay slot
21651		 addu  $7,$7,$30
21652		 lw    $7,0x00($7)
21653		 jr    $7
21654		 nop                    	 # Delay slot
21655
21656OP0_0100:				#:
21657		 addiu $23,$23,2
21658
21659		 andi  $8,$24,0x07
21660		 srl   $24,$24,7
21661		 andi  $24,$24,0x1C
21662		 addu  $24,$24,$21
21663		 lw    $18,0x00($24)
21664		 ori   $10,$0,1
21665		 sllv  $9,$10,$18
21666		 sll   $8,$8,2
21667		 addu  $8,$8,$21
21668		 lw    $2,0x00($8)
21669		 and   $10,$9,$2
21670		 srlv  $18,$10,$18
21671		 xori  $18,$18,1        	 # Set Zero Flag
21672		 addiu $15,$15,-6
21673		 bgez  $15,3f
21674		 lhu   $24,0x00($23)    	 # Delay slot
21675		 j     MainExit
21676	3:
21677		 sll   $7,$24,2         	 # Delay slot
21678		 addu  $7,$7,$30
21679		 lw    $7,0x00($7)
21680		 jr    $7
21681		 nop                    	 # Delay slot
21682
21683OP0_0110:				#:
21684		 addiu $23,$23,2
21685
21686		 andi  $8,$24,0x07
21687		 srl   $24,$24,7
21688		 andi  $24,$24,0x1C
21689		 addu  $24,$24,$21
21690		 lw    $18,0x00($24)
21691		 ori   $10,$0,1
21692		 andi  $18,$18,0x07
21693		 sllv  $9,$10,$18
21694		 sll   $8,$8,2
21695		 addu  $8,$8,$21
21696		 lw    $14,0x20($8)
21697		 lw    $25,0x7C($21)
21698		 sw    $15,m68k_ICount
21699		 sw    $9,0x44($29)
21700		 sw    $14,0x40($29)
21701		 or    $4,$0,$14
21702		 jalr  $25
21703		 sw    $23,0x4C($21)    	 # Delay slot
21704		 lw    $14,0x40($29)
21705		 lw    $9,0x44($29)
21706		 lw    $15,m68k_ICount
21707		 and   $10,$9,$2
21708		 srlv  $18,$10,$18
21709		 xori  $18,$18,1        	 # Set Zero Flag
21710		 addiu $15,$15,-8
21711		 bgez  $15,3f
21712		 lhu   $24,0x00($23)    	 # Delay slot
21713		 j     MainExit
21714	3:
21715		 sll   $7,$24,2         	 # Delay slot
21716		 addu  $7,$7,$30
21717		 lw    $7,0x00($7)
21718		 jr    $7
21719		 nop                    	 # Delay slot
21720
21721OP0_0118:				#:
21722		 addiu $23,$23,2
21723
21724		 andi  $8,$24,0x07
21725		 srl   $24,$24,7
21726		 andi  $24,$24,0x1C
21727		 addu  $24,$24,$21
21728		 lw    $18,0x00($24)
21729		 ori   $10,$0,1
21730		 andi  $18,$18,0x07
21731		 sllv  $9,$10,$18
21732		 sll   $8,$8,2
21733		 addu  $8,$8,$21
21734		 lw    $14,0x20($8)
21735		 addiu $25,$14,1
21736		 sw    $25,0x20($8)
21737		 lw    $25,0x7C($21)
21738		 sw    $15,m68k_ICount
21739		 sw    $9,0x44($29)
21740		 sw    $14,0x40($29)
21741		 or    $4,$0,$14
21742		 jalr  $25
21743		 sw    $23,0x4C($21)    	 # Delay slot
21744		 lw    $14,0x40($29)
21745		 lw    $9,0x44($29)
21746		 lw    $15,m68k_ICount
21747		 and   $10,$9,$2
21748		 srlv  $18,$10,$18
21749		 xori  $18,$18,1        	 # Set Zero Flag
21750		 addiu $15,$15,-8
21751		 bgez  $15,3f
21752		 lhu   $24,0x00($23)    	 # Delay slot
21753		 j     MainExit
21754	3:
21755		 sll   $7,$24,2         	 # Delay slot
21756		 addu  $7,$7,$30
21757		 lw    $7,0x00($7)
21758		 jr    $7
21759		 nop                    	 # Delay slot
21760
21761OP0_011f:				#:
21762		 addiu $23,$23,2
21763
21764		 srl   $24,$24,7
21765		 andi  $24,$24,0x1C
21766		 addu  $24,$24,$21
21767		 lw    $18,0x00($24)
21768		 ori   $10,$0,1
21769		 andi  $18,$18,0x07
21770		 sllv  $9,$10,$18
21771		 lw    $14,0x3C($21)    	 # Get A7
21772		 addiu $25,$14,2
21773		 sw    $25,0x3C($21)
21774		 lw    $25,0x7C($21)
21775		 sw    $15,m68k_ICount
21776		 sw    $9,0x44($29)
21777		 sw    $14,0x40($29)
21778		 or    $4,$0,$14
21779		 jalr  $25
21780		 sw    $23,0x4C($21)    	 # Delay slot
21781		 lw    $14,0x40($29)
21782		 lw    $9,0x44($29)
21783		 lw    $15,m68k_ICount
21784		 and   $10,$9,$2
21785		 srlv  $18,$10,$18
21786		 xori  $18,$18,1        	 # Set Zero Flag
21787		 addiu $15,$15,-8
21788		 bgez  $15,3f
21789		 lhu   $24,0x00($23)    	 # Delay slot
21790		 j     MainExit
21791	3:
21792		 sll   $7,$24,2         	 # Delay slot
21793		 addu  $7,$7,$30
21794		 lw    $7,0x00($7)
21795		 jr    $7
21796		 nop                    	 # Delay slot
21797
21798OP0_0120:				#:
21799		 addiu $23,$23,2
21800
21801		 andi  $8,$24,0x07
21802		 srl   $24,$24,7
21803		 andi  $24,$24,0x1C
21804		 addu  $24,$24,$21
21805		 lw    $18,0x00($24)
21806		 ori   $10,$0,1
21807		 andi  $18,$18,0x07
21808		 sllv  $9,$10,$18
21809		 sll   $8,$8,2
21810		 addu  $8,$8,$21
21811		 lw    $14,0x20($8)
21812		 addiu $14,$14,-1
21813		 sw    $14,0x20($8)
21814		 lw    $25,0x7C($21)
21815		 sw    $15,m68k_ICount
21816		 sw    $9,0x44($29)
21817		 sw    $14,0x40($29)
21818		 or    $4,$0,$14
21819		 jalr  $25
21820		 sw    $23,0x4C($21)    	 # Delay slot
21821		 lw    $14,0x40($29)
21822		 lw    $9,0x44($29)
21823		 lw    $15,m68k_ICount
21824		 and   $10,$9,$2
21825		 srlv  $18,$10,$18
21826		 xori  $18,$18,1        	 # Set Zero Flag
21827		 addiu $15,$15,-10
21828		 bgez  $15,3f
21829		 lhu   $24,0x00($23)    	 # Delay slot
21830		 j     MainExit
21831	3:
21832		 sll   $7,$24,2         	 # Delay slot
21833		 addu  $7,$7,$30
21834		 lw    $7,0x00($7)
21835		 jr    $7
21836		 nop                    	 # Delay slot
21837
21838OP0_0127:				#:
21839		 addiu $23,$23,2
21840
21841		 srl   $24,$24,7
21842		 andi  $24,$24,0x1C
21843		 addu  $24,$24,$21
21844		 lw    $18,0x00($24)
21845		 ori   $10,$0,1
21846		 andi  $18,$18,0x07
21847		 sllv  $9,$10,$18
21848		 lw    $14,0x3C($21)    	 # Get A7
21849		 addiu $14,$14,-2
21850		 sw    $14,0x3C($21)
21851		 lw    $25,0x7C($21)
21852		 sw    $15,m68k_ICount
21853		 sw    $9,0x44($29)
21854		 sw    $14,0x40($29)
21855		 or    $4,$0,$14
21856		 jalr  $25
21857		 sw    $23,0x4C($21)    	 # Delay slot
21858		 lw    $14,0x40($29)
21859		 lw    $9,0x44($29)
21860		 lw    $15,m68k_ICount
21861		 and   $10,$9,$2
21862		 srlv  $18,$10,$18
21863		 xori  $18,$18,1        	 # Set Zero Flag
21864		 addiu $15,$15,-10
21865		 bgez  $15,3f
21866		 lhu   $24,0x00($23)    	 # Delay slot
21867		 j     MainExit
21868	3:
21869		 sll   $7,$24,2         	 # Delay slot
21870		 addu  $7,$7,$30
21871		 lw    $7,0x00($7)
21872		 jr    $7
21873		 nop                    	 # Delay slot
21874
21875OP0_0128:				#:
21876		 addiu $23,$23,2
21877
21878		 andi  $8,$24,0x07
21879		 srl   $24,$24,7
21880		 andi  $24,$24,0x1C
21881		 addu  $24,$24,$21
21882		 lw    $18,0x00($24)
21883		 ori   $10,$0,1
21884		 andi  $18,$18,0x07
21885		 sllv  $9,$10,$18
21886		 lh    $7,0x00($23)
21887		 sll   $8,$8,2
21888		 addu  $8,$8,$21
21889		 lw    $14,0x20($8)
21890		 addiu $23,$23,2
21891		 addu  $14,$14,$7
21892		 lw    $25,0x7C($21)
21893		 sw    $15,m68k_ICount
21894		 sw    $9,0x44($29)
21895		 sw    $14,0x40($29)
21896		 or    $4,$0,$14
21897		 jalr  $25
21898		 sw    $23,0x4C($21)    	 # Delay slot
21899		 lw    $14,0x40($29)
21900		 lw    $9,0x44($29)
21901		 lw    $15,m68k_ICount
21902		 and   $10,$9,$2
21903		 srlv  $18,$10,$18
21904		 xori  $18,$18,1        	 # Set Zero Flag
21905		 addiu $15,$15,-12
21906		 bgez  $15,3f
21907		 lhu   $24,0x00($23)    	 # Delay slot
21908		 j     MainExit
21909	3:
21910		 sll   $7,$24,2         	 # Delay slot
21911		 addu  $7,$7,$30
21912		 lw    $7,0x00($7)
21913		 jr    $7
21914		 nop                    	 # Delay slot
21915
21916OP0_0130:				#:
21917		 addiu $23,$23,2
21918
21919		 andi  $8,$24,0x07
21920		 srl   $24,$24,7
21921		 andi  $24,$24,0x1C
21922		 addu  $24,$24,$21
21923		 lw    $18,0x00($24)
21924		 ori   $10,$0,1
21925		 andi  $18,$18,0x07
21926		 sllv  $9,$10,$18
21927		 sll   $8,$8,2
21928		 addu  $8,$8,$21
21929		 lw    $14,0x20($8)
21930		 lhu   $7,0x00($23)
21931		 addiu $23,$23,2
21932		 seb   $6,$7
21933		 or    $25,$0,$7
21934		 srl   $7,$7,12
21935		 andi  $25,$25,0x0800
21936		 sll   $7,$7,2
21937		 addu  $7,$7,$21
21938		 bne   $25,$0,0f
21939		 lw    $25,0x00($7)      	 # Delay slot
21940		 seh   $25,$25
21941	0:
21942		 addu  $25,$14,$25
21943		 addu  $14,$25,$6
21944		 lw    $25,0x7C($21)
21945		 sw    $15,m68k_ICount
21946		 sw    $9,0x44($29)
21947		 sw    $14,0x40($29)
21948		 or    $4,$0,$14
21949		 jalr  $25
21950		 sw    $23,0x4C($21)    	 # Delay slot
21951		 lw    $14,0x40($29)
21952		 lw    $9,0x44($29)
21953		 lw    $15,m68k_ICount
21954		 and   $10,$9,$2
21955		 srlv  $18,$10,$18
21956		 xori  $18,$18,1        	 # Set Zero Flag
21957		 addiu $15,$15,-14
21958		 bgez  $15,3f
21959		 lhu   $24,0x00($23)    	 # Delay slot
21960		 j     MainExit
21961	3:
21962		 sll   $7,$24,2         	 # Delay slot
21963		 addu  $7,$7,$30
21964		 lw    $7,0x00($7)
21965		 jr    $7
21966		 nop                    	 # Delay slot
21967
21968OP0_0138:				#:
21969		 addiu $23,$23,2
21970
21971		 srl   $24,$24,7
21972		 andi  $24,$24,0x1C
21973		 addu  $24,$24,$21
21974		 lw    $18,0x00($24)
21975		 ori   $10,$0,1
21976		 andi  $18,$18,0x07
21977		 sllv  $9,$10,$18
21978		 lh    $14,0x00($23)
21979		 addiu $23,$23,2
21980		 lw    $25,0x7C($21)
21981		 sw    $15,m68k_ICount
21982		 sw    $9,0x44($29)
21983		 sw    $14,0x40($29)
21984		 or    $4,$0,$14
21985		 jalr  $25
21986		 sw    $23,0x4C($21)    	 # Delay slot
21987		 lw    $14,0x40($29)
21988		 lw    $9,0x44($29)
21989		 lw    $15,m68k_ICount
21990		 and   $10,$9,$2
21991		 srlv  $18,$10,$18
21992		 xori  $18,$18,1        	 # Set Zero Flag
21993		 addiu $15,$15,-12
21994		 bgez  $15,3f
21995		 lhu   $24,0x00($23)    	 # Delay slot
21996		 j     MainExit
21997	3:
21998		 sll   $7,$24,2         	 # Delay slot
21999		 addu  $7,$7,$30
22000		 lw    $7,0x00($7)
22001		 jr    $7
22002		 nop                    	 # Delay slot
22003
22004OP0_0139:				#:
22005		 addiu $23,$23,2
22006
22007		 srl   $24,$24,7
22008		 andi  $24,$24,0x1C
22009		 addu  $24,$24,$21
22010		 lw    $18,0x00($24)
22011		 ori   $10,$0,1
22012		 andi  $18,$18,0x07
22013		 sllv  $9,$10,$18
22014		 lhu   $14,0x00($23)
22015		 lhu   $25,0x02($23)
22016		 sll   $14,$14,16
22017		 or    $14,$14,$25
22018		 addiu $23,$23,4
22019		 lw    $25,0x7C($21)
22020		 sw    $15,m68k_ICount
22021		 sw    $9,0x44($29)
22022		 sw    $14,0x40($29)
22023		 or    $4,$0,$14
22024		 jalr  $25
22025		 sw    $23,0x4C($21)    	 # Delay slot
22026		 lw    $14,0x40($29)
22027		 lw    $9,0x44($29)
22028		 lw    $15,m68k_ICount
22029		 and   $10,$9,$2
22030		 srlv  $18,$10,$18
22031		 xori  $18,$18,1        	 # Set Zero Flag
22032		 addiu $15,$15,-16
22033		 bgez  $15,3f
22034		 lhu   $24,0x00($23)    	 # Delay slot
22035		 j     MainExit
22036	3:
22037		 sll   $7,$24,2         	 # Delay slot
22038		 addu  $7,$7,$30
22039		 lw    $7,0x00($7)
22040		 jr    $7
22041		 nop                    	 # Delay slot
22042
22043OP0_013a:				#:
22044		 addiu $23,$23,2
22045
22046		 srl   $24,$24,7
22047		 andi  $24,$24,0x1C
22048		 addu  $24,$24,$21
22049		 lw    $18,0x00($24)
22050		 ori   $10,$0,1
22051		 andi  $18,$18,0x07
22052		 sllv  $9,$10,$18
22053		 lh    $7,0x00($23)
22054		 subu  $25,$23,$22
22055		 addu  $14,$25,$7       	 # Add Offset to PC
22056		 addiu $23,$23,2
22057		 lw    $25,0x98($21)
22058		 sw    $15,m68k_ICount
22059		 sw    $9,0x44($29)
22060		 sw    $14,0x40($29)
22061		 or    $4,$0,$14
22062		 jalr  $25
22063		 sw    $23,0x4C($21)    	 # Delay slot
22064		 lw    $14,0x40($29)
22065		 lw    $9,0x44($29)
22066		 lw    $15,m68k_ICount
22067		 and   $10,$9,$2
22068		 srlv  $18,$10,$18
22069		 xori  $18,$18,1        	 # Set Zero Flag
22070		 addiu $15,$15,-12
22071		 bgez  $15,3f
22072		 lhu   $24,0x00($23)    	 # Delay slot
22073		 j     MainExit
22074	3:
22075		 sll   $7,$24,2         	 # Delay slot
22076		 addu  $7,$7,$30
22077		 lw    $7,0x00($7)
22078		 jr    $7
22079		 nop                    	 # Delay slot
22080
22081OP0_013b:				#:
22082		 addiu $23,$23,2
22083
22084		 srl   $24,$24,7
22085		 andi  $24,$24,0x1C
22086		 addu  $24,$24,$21
22087		 lw    $18,0x00($24)
22088		 ori   $10,$0,1
22089		 andi  $18,$18,0x07
22090		 sllv  $9,$10,$18
22091		 subu  $14,$23,$22       	 # Get PC
22092		 lhu   $7,0x00($23)
22093		 addiu $23,$23,2
22094		 seb   $6,$7
22095		 or    $25,$0,$7
22096		 srl   $7,$7,12
22097		 andi  $25,$25,0x0800
22098		 sll   $7,$7,2
22099		 addu  $7,$7,$21
22100		 bne   $25,$0,0f
22101		 lw    $25,0x00($7)      	 # Delay slot
22102		 seh   $25,$25
22103	0:
22104		 addu  $25,$14,$25
22105		 addu  $14,$25,$6
22106		 lw    $25,0x98($21)
22107		 sw    $15,m68k_ICount
22108		 sw    $9,0x44($29)
22109		 sw    $14,0x40($29)
22110		 or    $4,$0,$14
22111		 jalr  $25
22112		 sw    $23,0x4C($21)    	 # Delay slot
22113		 lw    $14,0x40($29)
22114		 lw    $9,0x44($29)
22115		 lw    $15,m68k_ICount
22116		 and   $10,$9,$2
22117		 srlv  $18,$10,$18
22118		 xori  $18,$18,1        	 # Set Zero Flag
22119		 addiu $15,$15,-14
22120		 bgez  $15,3f
22121		 lhu   $24,0x00($23)    	 # Delay slot
22122		 j     MainExit
22123	3:
22124		 sll   $7,$24,2         	 # Delay slot
22125		 addu  $7,$7,$30
22126		 lw    $7,0x00($7)
22127		 jr    $7
22128		 nop                    	 # Delay slot
22129
22130OP0_013c:				#:
22131		 addiu $23,$23,2
22132
22133		 srl   $24,$24,7
22134		 andi  $24,$24,0x1C
22135		 addu  $24,$24,$21
22136		 lw    $18,0x00($24)
22137		 ori   $10,$0,1
22138		 andi  $18,$18,0x07
22139		 sllv  $9,$10,$18
22140		 lbu   $2,0x00($23)
22141		 addiu $23,$23,2
22142		 and   $10,$9,$2
22143		 srlv  $18,$10,$18
22144		 xori  $18,$18,1        	 # Set Zero Flag
22145		 addiu $15,$15,-4
22146		 bgez  $15,3f
22147		 lhu   $24,0x00($23)    	 # Delay slot
22148		 j     MainExit
22149	3:
22150		 sll   $7,$24,2         	 # Delay slot
22151		 addu  $7,$7,$30
22152		 lw    $7,0x00($7)
22153		 jr    $7
22154		 nop                    	 # Delay slot
22155
22156OP0_0140:				#:
22157		 addiu $23,$23,2
22158
22159		 andi  $8,$24,0x07
22160		 srl   $24,$24,7
22161		 andi  $24,$24,0x1C
22162		 addu  $24,$24,$21
22163		 lw    $18,0x00($24)
22164		 ori   $10,$0,1
22165		 sllv  $9,$10,$18
22166		 sll   $8,$8,2
22167		 addu  $8,$8,$21
22168		 lw    $2,0x00($8)
22169		 and   $10,$9,$2
22170		 srlv  $18,$10,$18
22171		 xori  $18,$18,1        	 # Set Zero Flag
22172		 xor   $2,$2,$9
22173		 sw    $2,0x00($8)
22174		 addiu $15,$15,-8
22175		 bgez  $15,3f
22176		 lhu   $24,0x00($23)    	 # Delay slot
22177		 j     MainExit
22178	3:
22179		 sll   $7,$24,2         	 # Delay slot
22180		 addu  $7,$7,$30
22181		 lw    $7,0x00($7)
22182		 jr    $7
22183		 nop                    	 # Delay slot
22184
22185OP0_0150:				#:
22186		 addiu $23,$23,2
22187
22188		 andi  $8,$24,0x07
22189		 srl   $24,$24,7
22190		 andi  $24,$24,0x1C
22191		 addu  $24,$24,$21
22192		 lw    $18,0x00($24)
22193		 ori   $10,$0,1
22194		 andi  $18,$18,0x07
22195		 sllv  $9,$10,$18
22196		 sll   $8,$8,2
22197		 addu  $8,$8,$21
22198		 lw    $14,0x20($8)
22199		 lw    $25,0x7C($21)
22200		 sw    $15,m68k_ICount
22201		 sw    $9,0x44($29)
22202		 sw    $14,0x40($29)
22203		 or    $4,$0,$14
22204		 jalr  $25
22205		 sw    $23,0x4C($21)    	 # Delay slot
22206		 lw    $14,0x40($29)
22207		 lw    $9,0x44($29)
22208		 lw    $15,m68k_ICount
22209		 and   $10,$9,$2
22210		 srlv  $18,$10,$18
22211		 xori  $18,$18,1        	 # Set Zero Flag
22212		 xor   $2,$2,$9
22213		 lw    $25,0x88($21)
22214		 sw    $15,m68k_ICount
22215		 or    $5,$0,$2
22216		 or    $4,$0,$14
22217		 jalr  $25
22218		 sw    $23,0x4C($21)    	 # Delay slot
22219		 lw    $15,m68k_ICount
22220		 addiu $15,$15,-12
22221		 bgez  $15,3f
22222		 lhu   $24,0x00($23)    	 # Delay slot
22223		 j     MainExit
22224	3:
22225		 sll   $7,$24,2         	 # Delay slot
22226		 addu  $7,$7,$30
22227		 lw    $7,0x00($7)
22228		 jr    $7
22229		 nop                    	 # Delay slot
22230
22231OP0_0158:				#:
22232		 addiu $23,$23,2
22233
22234		 andi  $8,$24,0x07
22235		 srl   $24,$24,7
22236		 andi  $24,$24,0x1C
22237		 addu  $24,$24,$21
22238		 lw    $18,0x00($24)
22239		 ori   $10,$0,1
22240		 andi  $18,$18,0x07
22241		 sllv  $9,$10,$18
22242		 sll   $8,$8,2
22243		 addu  $8,$8,$21
22244		 lw    $14,0x20($8)
22245		 addiu $25,$14,1
22246		 sw    $25,0x20($8)
22247		 lw    $25,0x7C($21)
22248		 sw    $15,m68k_ICount
22249		 sw    $9,0x44($29)
22250		 sw    $14,0x40($29)
22251		 or    $4,$0,$14
22252		 jalr  $25
22253		 sw    $23,0x4C($21)    	 # Delay slot
22254		 lw    $14,0x40($29)
22255		 lw    $9,0x44($29)
22256		 lw    $15,m68k_ICount
22257		 and   $10,$9,$2
22258		 srlv  $18,$10,$18
22259		 xori  $18,$18,1        	 # Set Zero Flag
22260		 xor   $2,$2,$9
22261		 lw    $25,0x88($21)
22262		 sw    $15,m68k_ICount
22263		 or    $5,$0,$2
22264		 or    $4,$0,$14
22265		 jalr  $25
22266		 sw    $23,0x4C($21)    	 # Delay slot
22267		 lw    $15,m68k_ICount
22268		 addiu $15,$15,-12
22269		 bgez  $15,3f
22270		 lhu   $24,0x00($23)    	 # Delay slot
22271		 j     MainExit
22272	3:
22273		 sll   $7,$24,2         	 # Delay slot
22274		 addu  $7,$7,$30
22275		 lw    $7,0x00($7)
22276		 jr    $7
22277		 nop                    	 # Delay slot
22278
22279OP0_015f:				#:
22280		 addiu $23,$23,2
22281
22282		 srl   $24,$24,7
22283		 andi  $24,$24,0x1C
22284		 addu  $24,$24,$21
22285		 lw    $18,0x00($24)
22286		 ori   $10,$0,1
22287		 andi  $18,$18,0x07
22288		 sllv  $9,$10,$18
22289		 lw    $14,0x3C($21)    	 # Get A7
22290		 addiu $25,$14,2
22291		 sw    $25,0x3C($21)
22292		 lw    $25,0x7C($21)
22293		 sw    $15,m68k_ICount
22294		 sw    $9,0x44($29)
22295		 sw    $14,0x40($29)
22296		 or    $4,$0,$14
22297		 jalr  $25
22298		 sw    $23,0x4C($21)    	 # Delay slot
22299		 lw    $14,0x40($29)
22300		 lw    $9,0x44($29)
22301		 lw    $15,m68k_ICount
22302		 and   $10,$9,$2
22303		 srlv  $18,$10,$18
22304		 xori  $18,$18,1        	 # Set Zero Flag
22305		 xor   $2,$2,$9
22306		 lw    $25,0x88($21)
22307		 sw    $15,m68k_ICount
22308		 or    $5,$0,$2
22309		 or    $4,$0,$14
22310		 jalr  $25
22311		 sw    $23,0x4C($21)    	 # Delay slot
22312		 lw    $15,m68k_ICount
22313		 addiu $15,$15,-12
22314		 bgez  $15,3f
22315		 lhu   $24,0x00($23)    	 # Delay slot
22316		 j     MainExit
22317	3:
22318		 sll   $7,$24,2         	 # Delay slot
22319		 addu  $7,$7,$30
22320		 lw    $7,0x00($7)
22321		 jr    $7
22322		 nop                    	 # Delay slot
22323
22324OP0_0160:				#:
22325		 addiu $23,$23,2
22326
22327		 andi  $8,$24,0x07
22328		 srl   $24,$24,7
22329		 andi  $24,$24,0x1C
22330		 addu  $24,$24,$21
22331		 lw    $18,0x00($24)
22332		 ori   $10,$0,1
22333		 andi  $18,$18,0x07
22334		 sllv  $9,$10,$18
22335		 sll   $8,$8,2
22336		 addu  $8,$8,$21
22337		 lw    $14,0x20($8)
22338		 addiu $14,$14,-1
22339		 sw    $14,0x20($8)
22340		 lw    $25,0x7C($21)
22341		 sw    $15,m68k_ICount
22342		 sw    $9,0x44($29)
22343		 sw    $14,0x40($29)
22344		 or    $4,$0,$14
22345		 jalr  $25
22346		 sw    $23,0x4C($21)    	 # Delay slot
22347		 lw    $14,0x40($29)
22348		 lw    $9,0x44($29)
22349		 lw    $15,m68k_ICount
22350		 and   $10,$9,$2
22351		 srlv  $18,$10,$18
22352		 xori  $18,$18,1        	 # Set Zero Flag
22353		 xor   $2,$2,$9
22354		 lw    $25,0x88($21)
22355		 sw    $15,m68k_ICount
22356		 or    $5,$0,$2
22357		 or    $4,$0,$14
22358		 jalr  $25
22359		 sw    $23,0x4C($21)    	 # Delay slot
22360		 lw    $15,m68k_ICount
22361		 addiu $15,$15,-14
22362		 bgez  $15,3f
22363		 lhu   $24,0x00($23)    	 # Delay slot
22364		 j     MainExit
22365	3:
22366		 sll   $7,$24,2         	 # Delay slot
22367		 addu  $7,$7,$30
22368		 lw    $7,0x00($7)
22369		 jr    $7
22370		 nop                    	 # Delay slot
22371
22372OP0_0167:				#:
22373		 addiu $23,$23,2
22374
22375		 srl   $24,$24,7
22376		 andi  $24,$24,0x1C
22377		 addu  $24,$24,$21
22378		 lw    $18,0x00($24)
22379		 ori   $10,$0,1
22380		 andi  $18,$18,0x07
22381		 sllv  $9,$10,$18
22382		 lw    $14,0x3C($21)    	 # Get A7
22383		 addiu $14,$14,-2
22384		 sw    $14,0x3C($21)
22385		 lw    $25,0x7C($21)
22386		 sw    $15,m68k_ICount
22387		 sw    $9,0x44($29)
22388		 sw    $14,0x40($29)
22389		 or    $4,$0,$14
22390		 jalr  $25
22391		 sw    $23,0x4C($21)    	 # Delay slot
22392		 lw    $14,0x40($29)
22393		 lw    $9,0x44($29)
22394		 lw    $15,m68k_ICount
22395		 and   $10,$9,$2
22396		 srlv  $18,$10,$18
22397		 xori  $18,$18,1        	 # Set Zero Flag
22398		 xor   $2,$2,$9
22399		 lw    $25,0x88($21)
22400		 sw    $15,m68k_ICount
22401		 or    $5,$0,$2
22402		 or    $4,$0,$14
22403		 jalr  $25
22404		 sw    $23,0x4C($21)    	 # Delay slot
22405		 lw    $15,m68k_ICount
22406		 addiu $15,$15,-14
22407		 bgez  $15,3f
22408		 lhu   $24,0x00($23)    	 # Delay slot
22409		 j     MainExit
22410	3:
22411		 sll   $7,$24,2         	 # Delay slot
22412		 addu  $7,$7,$30
22413		 lw    $7,0x00($7)
22414		 jr    $7
22415		 nop                    	 # Delay slot
22416
22417OP0_0168:				#:
22418		 addiu $23,$23,2
22419
22420		 andi  $8,$24,0x07
22421		 srl   $24,$24,7
22422		 andi  $24,$24,0x1C
22423		 addu  $24,$24,$21
22424		 lw    $18,0x00($24)
22425		 ori   $10,$0,1
22426		 andi  $18,$18,0x07
22427		 sllv  $9,$10,$18
22428		 lh    $7,0x00($23)
22429		 sll   $8,$8,2
22430		 addu  $8,$8,$21
22431		 lw    $14,0x20($8)
22432		 addiu $23,$23,2
22433		 addu  $14,$14,$7
22434		 lw    $25,0x7C($21)
22435		 sw    $15,m68k_ICount
22436		 sw    $9,0x44($29)
22437		 sw    $14,0x40($29)
22438		 or    $4,$0,$14
22439		 jalr  $25
22440		 sw    $23,0x4C($21)    	 # Delay slot
22441		 lw    $14,0x40($29)
22442		 lw    $9,0x44($29)
22443		 lw    $15,m68k_ICount
22444		 and   $10,$9,$2
22445		 srlv  $18,$10,$18
22446		 xori  $18,$18,1        	 # Set Zero Flag
22447		 xor   $2,$2,$9
22448		 lw    $25,0x88($21)
22449		 sw    $15,m68k_ICount
22450		 or    $5,$0,$2
22451		 or    $4,$0,$14
22452		 jalr  $25
22453		 sw    $23,0x4C($21)    	 # Delay slot
22454		 lw    $15,m68k_ICount
22455		 addiu $15,$15,-16
22456		 bgez  $15,3f
22457		 lhu   $24,0x00($23)    	 # Delay slot
22458		 j     MainExit
22459	3:
22460		 sll   $7,$24,2         	 # Delay slot
22461		 addu  $7,$7,$30
22462		 lw    $7,0x00($7)
22463		 jr    $7
22464		 nop                    	 # Delay slot
22465
22466OP0_0170:				#:
22467		 addiu $23,$23,2
22468
22469		 andi  $8,$24,0x07
22470		 srl   $24,$24,7
22471		 andi  $24,$24,0x1C
22472		 addu  $24,$24,$21
22473		 lw    $18,0x00($24)
22474		 ori   $10,$0,1
22475		 andi  $18,$18,0x07
22476		 sllv  $9,$10,$18
22477		 sll   $8,$8,2
22478		 addu  $8,$8,$21
22479		 lw    $14,0x20($8)
22480		 lhu   $7,0x00($23)
22481		 addiu $23,$23,2
22482		 seb   $6,$7
22483		 or    $25,$0,$7
22484		 srl   $7,$7,12
22485		 andi  $25,$25,0x0800
22486		 sll   $7,$7,2
22487		 addu  $7,$7,$21
22488		 bne   $25,$0,0f
22489		 lw    $25,0x00($7)      	 # Delay slot
22490		 seh   $25,$25
22491	0:
22492		 addu  $25,$14,$25
22493		 addu  $14,$25,$6
22494		 lw    $25,0x7C($21)
22495		 sw    $15,m68k_ICount
22496		 sw    $9,0x44($29)
22497		 sw    $14,0x40($29)
22498		 or    $4,$0,$14
22499		 jalr  $25
22500		 sw    $23,0x4C($21)    	 # Delay slot
22501		 lw    $14,0x40($29)
22502		 lw    $9,0x44($29)
22503		 lw    $15,m68k_ICount
22504		 and   $10,$9,$2
22505		 srlv  $18,$10,$18
22506		 xori  $18,$18,1        	 # Set Zero Flag
22507		 xor   $2,$2,$9
22508		 lw    $25,0x88($21)
22509		 sw    $15,m68k_ICount
22510		 or    $5,$0,$2
22511		 or    $4,$0,$14
22512		 jalr  $25
22513		 sw    $23,0x4C($21)    	 # Delay slot
22514		 lw    $15,m68k_ICount
22515		 addiu $15,$15,-18
22516		 bgez  $15,3f
22517		 lhu   $24,0x00($23)    	 # Delay slot
22518		 j     MainExit
22519	3:
22520		 sll   $7,$24,2         	 # Delay slot
22521		 addu  $7,$7,$30
22522		 lw    $7,0x00($7)
22523		 jr    $7
22524		 nop                    	 # Delay slot
22525
22526OP0_0178:				#:
22527		 addiu $23,$23,2
22528
22529		 srl   $24,$24,7
22530		 andi  $24,$24,0x1C
22531		 addu  $24,$24,$21
22532		 lw    $18,0x00($24)
22533		 ori   $10,$0,1
22534		 andi  $18,$18,0x07
22535		 sllv  $9,$10,$18
22536		 lh    $14,0x00($23)
22537		 addiu $23,$23,2
22538		 lw    $25,0x7C($21)
22539		 sw    $15,m68k_ICount
22540		 sw    $9,0x44($29)
22541		 sw    $14,0x40($29)
22542		 or    $4,$0,$14
22543		 jalr  $25
22544		 sw    $23,0x4C($21)    	 # Delay slot
22545		 lw    $14,0x40($29)
22546		 lw    $9,0x44($29)
22547		 lw    $15,m68k_ICount
22548		 and   $10,$9,$2
22549		 srlv  $18,$10,$18
22550		 xori  $18,$18,1        	 # Set Zero Flag
22551		 xor   $2,$2,$9
22552		 lw    $25,0x88($21)
22553		 sw    $15,m68k_ICount
22554		 or    $5,$0,$2
22555		 or    $4,$0,$14
22556		 jalr  $25
22557		 sw    $23,0x4C($21)    	 # Delay slot
22558		 lw    $15,m68k_ICount
22559		 addiu $15,$15,-16
22560		 bgez  $15,3f
22561		 lhu   $24,0x00($23)    	 # Delay slot
22562		 j     MainExit
22563	3:
22564		 sll   $7,$24,2         	 # Delay slot
22565		 addu  $7,$7,$30
22566		 lw    $7,0x00($7)
22567		 jr    $7
22568		 nop                    	 # Delay slot
22569
22570OP0_0179:				#:
22571		 addiu $23,$23,2
22572
22573		 srl   $24,$24,7
22574		 andi  $24,$24,0x1C
22575		 addu  $24,$24,$21
22576		 lw    $18,0x00($24)
22577		 ori   $10,$0,1
22578		 andi  $18,$18,0x07
22579		 sllv  $9,$10,$18
22580		 lhu   $14,0x00($23)
22581		 lhu   $25,0x02($23)
22582		 sll   $14,$14,16
22583		 or    $14,$14,$25
22584		 addiu $23,$23,4
22585		 lw    $25,0x7C($21)
22586		 sw    $15,m68k_ICount
22587		 sw    $9,0x44($29)
22588		 sw    $14,0x40($29)
22589		 or    $4,$0,$14
22590		 jalr  $25
22591		 sw    $23,0x4C($21)    	 # Delay slot
22592		 lw    $14,0x40($29)
22593		 lw    $9,0x44($29)
22594		 lw    $15,m68k_ICount
22595		 and   $10,$9,$2
22596		 srlv  $18,$10,$18
22597		 xori  $18,$18,1        	 # Set Zero Flag
22598		 xor   $2,$2,$9
22599		 lw    $25,0x88($21)
22600		 sw    $15,m68k_ICount
22601		 or    $5,$0,$2
22602		 or    $4,$0,$14
22603		 jalr  $25
22604		 sw    $23,0x4C($21)    	 # Delay slot
22605		 lw    $15,m68k_ICount
22606		 addiu $15,$15,-20
22607		 bgez  $15,3f
22608		 lhu   $24,0x00($23)    	 # Delay slot
22609		 j     MainExit
22610	3:
22611		 sll   $7,$24,2         	 # Delay slot
22612		 addu  $7,$7,$30
22613		 lw    $7,0x00($7)
22614		 jr    $7
22615		 nop                    	 # Delay slot
22616
22617OP0_0180:				#:
22618		 addiu $23,$23,2
22619
22620		 andi  $8,$24,0x07
22621		 srl   $24,$24,7
22622		 andi  $24,$24,0x1C
22623		 addu  $24,$24,$21
22624		 lw    $18,0x00($24)
22625		 ori   $10,$0,1
22626		 sllv  $9,$10,$18
22627		 sll   $8,$8,2
22628		 addu  $8,$8,$21
22629		 lw    $2,0x00($8)
22630		 and   $10,$9,$2
22631		 srlv  $18,$10,$18
22632		 xori  $18,$18,1        	 # Set Zero Flag
22633		 nor   $9,$0,$9
22634		 and   $2,$2,$9
22635		 sw    $2,0x00($8)
22636		 addiu $15,$15,-10
22637		 bgez  $15,3f
22638		 lhu   $24,0x00($23)    	 # Delay slot
22639		 j     MainExit
22640	3:
22641		 sll   $7,$24,2         	 # Delay slot
22642		 addu  $7,$7,$30
22643		 lw    $7,0x00($7)
22644		 jr    $7
22645		 nop                    	 # Delay slot
22646
22647OP0_0190:				#:
22648		 addiu $23,$23,2
22649
22650		 andi  $8,$24,0x07
22651		 srl   $24,$24,7
22652		 andi  $24,$24,0x1C
22653		 addu  $24,$24,$21
22654		 lw    $18,0x00($24)
22655		 ori   $10,$0,1
22656		 andi  $18,$18,0x07
22657		 sllv  $9,$10,$18
22658		 sll   $8,$8,2
22659		 addu  $8,$8,$21
22660		 lw    $14,0x20($8)
22661		 lw    $25,0x7C($21)
22662		 sw    $15,m68k_ICount
22663		 sw    $9,0x44($29)
22664		 sw    $14,0x40($29)
22665		 or    $4,$0,$14
22666		 jalr  $25
22667		 sw    $23,0x4C($21)    	 # Delay slot
22668		 lw    $14,0x40($29)
22669		 lw    $9,0x44($29)
22670		 lw    $15,m68k_ICount
22671		 and   $10,$9,$2
22672		 srlv  $18,$10,$18
22673		 xori  $18,$18,1        	 # Set Zero Flag
22674		 nor   $9,$0,$9
22675		 and   $2,$2,$9
22676		 lw    $25,0x88($21)
22677		 sw    $15,m68k_ICount
22678		 or    $5,$0,$2
22679		 or    $4,$0,$14
22680		 jalr  $25
22681		 sw    $23,0x4C($21)    	 # Delay slot
22682		 lw    $15,m68k_ICount
22683		 addiu $15,$15,-12
22684		 bgez  $15,3f
22685		 lhu   $24,0x00($23)    	 # Delay slot
22686		 j     MainExit
22687	3:
22688		 sll   $7,$24,2         	 # Delay slot
22689		 addu  $7,$7,$30
22690		 lw    $7,0x00($7)
22691		 jr    $7
22692		 nop                    	 # Delay slot
22693
22694OP0_0198:				#:
22695		 addiu $23,$23,2
22696
22697		 andi  $8,$24,0x07
22698		 srl   $24,$24,7
22699		 andi  $24,$24,0x1C
22700		 addu  $24,$24,$21
22701		 lw    $18,0x00($24)
22702		 ori   $10,$0,1
22703		 andi  $18,$18,0x07
22704		 sllv  $9,$10,$18
22705		 sll   $8,$8,2
22706		 addu  $8,$8,$21
22707		 lw    $14,0x20($8)
22708		 addiu $25,$14,1
22709		 sw    $25,0x20($8)
22710		 lw    $25,0x7C($21)
22711		 sw    $15,m68k_ICount
22712		 sw    $9,0x44($29)
22713		 sw    $14,0x40($29)
22714		 or    $4,$0,$14
22715		 jalr  $25
22716		 sw    $23,0x4C($21)    	 # Delay slot
22717		 lw    $14,0x40($29)
22718		 lw    $9,0x44($29)
22719		 lw    $15,m68k_ICount
22720		 and   $10,$9,$2
22721		 srlv  $18,$10,$18
22722		 xori  $18,$18,1        	 # Set Zero Flag
22723		 nor   $9,$0,$9
22724		 and   $2,$2,$9
22725		 lw    $25,0x88($21)
22726		 sw    $15,m68k_ICount
22727		 or    $5,$0,$2
22728		 or    $4,$0,$14
22729		 jalr  $25
22730		 sw    $23,0x4C($21)    	 # Delay slot
22731		 lw    $15,m68k_ICount
22732		 addiu $15,$15,-12
22733		 bgez  $15,3f
22734		 lhu   $24,0x00($23)    	 # Delay slot
22735		 j     MainExit
22736	3:
22737		 sll   $7,$24,2         	 # Delay slot
22738		 addu  $7,$7,$30
22739		 lw    $7,0x00($7)
22740		 jr    $7
22741		 nop                    	 # Delay slot
22742
22743OP0_019f:				#:
22744		 addiu $23,$23,2
22745
22746		 srl   $24,$24,7
22747		 andi  $24,$24,0x1C
22748		 addu  $24,$24,$21
22749		 lw    $18,0x00($24)
22750		 ori   $10,$0,1
22751		 andi  $18,$18,0x07
22752		 sllv  $9,$10,$18
22753		 lw    $14,0x3C($21)    	 # Get A7
22754		 addiu $25,$14,2
22755		 sw    $25,0x3C($21)
22756		 lw    $25,0x7C($21)
22757		 sw    $15,m68k_ICount
22758		 sw    $9,0x44($29)
22759		 sw    $14,0x40($29)
22760		 or    $4,$0,$14
22761		 jalr  $25
22762		 sw    $23,0x4C($21)    	 # Delay slot
22763		 lw    $14,0x40($29)
22764		 lw    $9,0x44($29)
22765		 lw    $15,m68k_ICount
22766		 and   $10,$9,$2
22767		 srlv  $18,$10,$18
22768		 xori  $18,$18,1        	 # Set Zero Flag
22769		 nor   $9,$0,$9
22770		 and   $2,$2,$9
22771		 lw    $25,0x88($21)
22772		 sw    $15,m68k_ICount
22773		 or    $5,$0,$2
22774		 or    $4,$0,$14
22775		 jalr  $25
22776		 sw    $23,0x4C($21)    	 # Delay slot
22777		 lw    $15,m68k_ICount
22778		 addiu $15,$15,-12
22779		 bgez  $15,3f
22780		 lhu   $24,0x00($23)    	 # Delay slot
22781		 j     MainExit
22782	3:
22783		 sll   $7,$24,2         	 # Delay slot
22784		 addu  $7,$7,$30
22785		 lw    $7,0x00($7)
22786		 jr    $7
22787		 nop                    	 # Delay slot
22788
22789OP0_01a0:				#:
22790		 addiu $23,$23,2
22791
22792		 andi  $8,$24,0x07
22793		 srl   $24,$24,7
22794		 andi  $24,$24,0x1C
22795		 addu  $24,$24,$21
22796		 lw    $18,0x00($24)
22797		 ori   $10,$0,1
22798		 andi  $18,$18,0x07
22799		 sllv  $9,$10,$18
22800		 sll   $8,$8,2
22801		 addu  $8,$8,$21
22802		 lw    $14,0x20($8)
22803		 addiu $14,$14,-1
22804		 sw    $14,0x20($8)
22805		 lw    $25,0x7C($21)
22806		 sw    $15,m68k_ICount
22807		 sw    $9,0x44($29)
22808		 sw    $14,0x40($29)
22809		 or    $4,$0,$14
22810		 jalr  $25
22811		 sw    $23,0x4C($21)    	 # Delay slot
22812		 lw    $14,0x40($29)
22813		 lw    $9,0x44($29)
22814		 lw    $15,m68k_ICount
22815		 and   $10,$9,$2
22816		 srlv  $18,$10,$18
22817		 xori  $18,$18,1        	 # Set Zero Flag
22818		 nor   $9,$0,$9
22819		 and   $2,$2,$9
22820		 lw    $25,0x88($21)
22821		 sw    $15,m68k_ICount
22822		 or    $5,$0,$2
22823		 or    $4,$0,$14
22824		 jalr  $25
22825		 sw    $23,0x4C($21)    	 # Delay slot
22826		 lw    $15,m68k_ICount
22827		 addiu $15,$15,-14
22828		 bgez  $15,3f
22829		 lhu   $24,0x00($23)    	 # Delay slot
22830		 j     MainExit
22831	3:
22832		 sll   $7,$24,2         	 # Delay slot
22833		 addu  $7,$7,$30
22834		 lw    $7,0x00($7)
22835		 jr    $7
22836		 nop                    	 # Delay slot
22837
22838OP0_01a7:				#:
22839		 addiu $23,$23,2
22840
22841		 srl   $24,$24,7
22842		 andi  $24,$24,0x1C
22843		 addu  $24,$24,$21
22844		 lw    $18,0x00($24)
22845		 ori   $10,$0,1
22846		 andi  $18,$18,0x07
22847		 sllv  $9,$10,$18
22848		 lw    $14,0x3C($21)    	 # Get A7
22849		 addiu $14,$14,-2
22850		 sw    $14,0x3C($21)
22851		 lw    $25,0x7C($21)
22852		 sw    $15,m68k_ICount
22853		 sw    $9,0x44($29)
22854		 sw    $14,0x40($29)
22855		 or    $4,$0,$14
22856		 jalr  $25
22857		 sw    $23,0x4C($21)    	 # Delay slot
22858		 lw    $14,0x40($29)
22859		 lw    $9,0x44($29)
22860		 lw    $15,m68k_ICount
22861		 and   $10,$9,$2
22862		 srlv  $18,$10,$18
22863		 xori  $18,$18,1        	 # Set Zero Flag
22864		 nor   $9,$0,$9
22865		 and   $2,$2,$9
22866		 lw    $25,0x88($21)
22867		 sw    $15,m68k_ICount
22868		 or    $5,$0,$2
22869		 or    $4,$0,$14
22870		 jalr  $25
22871		 sw    $23,0x4C($21)    	 # Delay slot
22872		 lw    $15,m68k_ICount
22873		 addiu $15,$15,-14
22874		 bgez  $15,3f
22875		 lhu   $24,0x00($23)    	 # Delay slot
22876		 j     MainExit
22877	3:
22878		 sll   $7,$24,2         	 # Delay slot
22879		 addu  $7,$7,$30
22880		 lw    $7,0x00($7)
22881		 jr    $7
22882		 nop                    	 # Delay slot
22883
22884OP0_01a8:				#:
22885		 addiu $23,$23,2
22886
22887		 andi  $8,$24,0x07
22888		 srl   $24,$24,7
22889		 andi  $24,$24,0x1C
22890		 addu  $24,$24,$21
22891		 lw    $18,0x00($24)
22892		 ori   $10,$0,1
22893		 andi  $18,$18,0x07
22894		 sllv  $9,$10,$18
22895		 lh    $7,0x00($23)
22896		 sll   $8,$8,2
22897		 addu  $8,$8,$21
22898		 lw    $14,0x20($8)
22899		 addiu $23,$23,2
22900		 addu  $14,$14,$7
22901		 lw    $25,0x7C($21)
22902		 sw    $15,m68k_ICount
22903		 sw    $9,0x44($29)
22904		 sw    $14,0x40($29)
22905		 or    $4,$0,$14
22906		 jalr  $25
22907		 sw    $23,0x4C($21)    	 # Delay slot
22908		 lw    $14,0x40($29)
22909		 lw    $9,0x44($29)
22910		 lw    $15,m68k_ICount
22911		 and   $10,$9,$2
22912		 srlv  $18,$10,$18
22913		 xori  $18,$18,1        	 # Set Zero Flag
22914		 nor   $9,$0,$9
22915		 and   $2,$2,$9
22916		 lw    $25,0x88($21)
22917		 sw    $15,m68k_ICount
22918		 or    $5,$0,$2
22919		 or    $4,$0,$14
22920		 jalr  $25
22921		 sw    $23,0x4C($21)    	 # Delay slot
22922		 lw    $15,m68k_ICount
22923		 addiu $15,$15,-16
22924		 bgez  $15,3f
22925		 lhu   $24,0x00($23)    	 # Delay slot
22926		 j     MainExit
22927	3:
22928		 sll   $7,$24,2         	 # Delay slot
22929		 addu  $7,$7,$30
22930		 lw    $7,0x00($7)
22931		 jr    $7
22932		 nop                    	 # Delay slot
22933
22934OP0_01b0:				#:
22935		 addiu $23,$23,2
22936
22937		 andi  $8,$24,0x07
22938		 srl   $24,$24,7
22939		 andi  $24,$24,0x1C
22940		 addu  $24,$24,$21
22941		 lw    $18,0x00($24)
22942		 ori   $10,$0,1
22943		 andi  $18,$18,0x07
22944		 sllv  $9,$10,$18
22945		 sll   $8,$8,2
22946		 addu  $8,$8,$21
22947		 lw    $14,0x20($8)
22948		 lhu   $7,0x00($23)
22949		 addiu $23,$23,2
22950		 seb   $6,$7
22951		 or    $25,$0,$7
22952		 srl   $7,$7,12
22953		 andi  $25,$25,0x0800
22954		 sll   $7,$7,2
22955		 addu  $7,$7,$21
22956		 bne   $25,$0,0f
22957		 lw    $25,0x00($7)      	 # Delay slot
22958		 seh   $25,$25
22959	0:
22960		 addu  $25,$14,$25
22961		 addu  $14,$25,$6
22962		 lw    $25,0x7C($21)
22963		 sw    $15,m68k_ICount
22964		 sw    $9,0x44($29)
22965		 sw    $14,0x40($29)
22966		 or    $4,$0,$14
22967		 jalr  $25
22968		 sw    $23,0x4C($21)    	 # Delay slot
22969		 lw    $14,0x40($29)
22970		 lw    $9,0x44($29)
22971		 lw    $15,m68k_ICount
22972		 and   $10,$9,$2
22973		 srlv  $18,$10,$18
22974		 xori  $18,$18,1        	 # Set Zero Flag
22975		 nor   $9,$0,$9
22976		 and   $2,$2,$9
22977		 lw    $25,0x88($21)
22978		 sw    $15,m68k_ICount
22979		 or    $5,$0,$2
22980		 or    $4,$0,$14
22981		 jalr  $25
22982		 sw    $23,0x4C($21)    	 # Delay slot
22983		 lw    $15,m68k_ICount
22984		 addiu $15,$15,-18
22985		 bgez  $15,3f
22986		 lhu   $24,0x00($23)    	 # Delay slot
22987		 j     MainExit
22988	3:
22989		 sll   $7,$24,2         	 # Delay slot
22990		 addu  $7,$7,$30
22991		 lw    $7,0x00($7)
22992		 jr    $7
22993		 nop                    	 # Delay slot
22994
22995OP0_01b8:				#:
22996		 addiu $23,$23,2
22997
22998		 srl   $24,$24,7
22999		 andi  $24,$24,0x1C
23000		 addu  $24,$24,$21
23001		 lw    $18,0x00($24)
23002		 ori   $10,$0,1
23003		 andi  $18,$18,0x07
23004		 sllv  $9,$10,$18
23005		 lh    $14,0x00($23)
23006		 addiu $23,$23,2
23007		 lw    $25,0x7C($21)
23008		 sw    $15,m68k_ICount
23009		 sw    $9,0x44($29)
23010		 sw    $14,0x40($29)
23011		 or    $4,$0,$14
23012		 jalr  $25
23013		 sw    $23,0x4C($21)    	 # Delay slot
23014		 lw    $14,0x40($29)
23015		 lw    $9,0x44($29)
23016		 lw    $15,m68k_ICount
23017		 and   $10,$9,$2
23018		 srlv  $18,$10,$18
23019		 xori  $18,$18,1        	 # Set Zero Flag
23020		 nor   $9,$0,$9
23021		 and   $2,$2,$9
23022		 lw    $25,0x88($21)
23023		 sw    $15,m68k_ICount
23024		 or    $5,$0,$2
23025		 or    $4,$0,$14
23026		 jalr  $25
23027		 sw    $23,0x4C($21)    	 # Delay slot
23028		 lw    $15,m68k_ICount
23029		 addiu $15,$15,-16
23030		 bgez  $15,3f
23031		 lhu   $24,0x00($23)    	 # Delay slot
23032		 j     MainExit
23033	3:
23034		 sll   $7,$24,2         	 # Delay slot
23035		 addu  $7,$7,$30
23036		 lw    $7,0x00($7)
23037		 jr    $7
23038		 nop                    	 # Delay slot
23039
23040OP0_01b9:				#:
23041		 addiu $23,$23,2
23042
23043		 srl   $24,$24,7
23044		 andi  $24,$24,0x1C
23045		 addu  $24,$24,$21
23046		 lw    $18,0x00($24)
23047		 ori   $10,$0,1
23048		 andi  $18,$18,0x07
23049		 sllv  $9,$10,$18
23050		 lhu   $14,0x00($23)
23051		 lhu   $25,0x02($23)
23052		 sll   $14,$14,16
23053		 or    $14,$14,$25
23054		 addiu $23,$23,4
23055		 lw    $25,0x7C($21)
23056		 sw    $15,m68k_ICount
23057		 sw    $9,0x44($29)
23058		 sw    $14,0x40($29)
23059		 or    $4,$0,$14
23060		 jalr  $25
23061		 sw    $23,0x4C($21)    	 # Delay slot
23062		 lw    $14,0x40($29)
23063		 lw    $9,0x44($29)
23064		 lw    $15,m68k_ICount
23065		 and   $10,$9,$2
23066		 srlv  $18,$10,$18
23067		 xori  $18,$18,1        	 # Set Zero Flag
23068		 nor   $9,$0,$9
23069		 and   $2,$2,$9
23070		 lw    $25,0x88($21)
23071		 sw    $15,m68k_ICount
23072		 or    $5,$0,$2
23073		 or    $4,$0,$14
23074		 jalr  $25
23075		 sw    $23,0x4C($21)    	 # Delay slot
23076		 lw    $15,m68k_ICount
23077		 addiu $15,$15,-20
23078		 bgez  $15,3f
23079		 lhu   $24,0x00($23)    	 # Delay slot
23080		 j     MainExit
23081	3:
23082		 sll   $7,$24,2         	 # Delay slot
23083		 addu  $7,$7,$30
23084		 lw    $7,0x00($7)
23085		 jr    $7
23086		 nop                    	 # Delay slot
23087
23088OP0_01c0:				#:
23089		 addiu $23,$23,2
23090
23091		 andi  $8,$24,0x07
23092		 srl   $24,$24,7
23093		 andi  $24,$24,0x1C
23094		 addu  $24,$24,$21
23095		 lw    $18,0x00($24)
23096		 ori   $10,$0,1
23097		 sllv  $9,$10,$18
23098		 sll   $8,$8,2
23099		 addu  $8,$8,$21
23100		 lw    $2,0x00($8)
23101		 and   $10,$9,$2
23102		 srlv  $18,$10,$18
23103		 xori  $18,$18,1        	 # Set Zero Flag
23104		 or    $2,$2,$9
23105		 sw    $2,0x00($8)
23106		 addiu $15,$15,-8
23107		 bgez  $15,3f
23108		 lhu   $24,0x00($23)    	 # Delay slot
23109		 j     MainExit
23110	3:
23111		 sll   $7,$24,2         	 # Delay slot
23112		 addu  $7,$7,$30
23113		 lw    $7,0x00($7)
23114		 jr    $7
23115		 nop                    	 # Delay slot
23116
23117OP0_01d0:				#:
23118		 addiu $23,$23,2
23119
23120		 andi  $8,$24,0x07
23121		 srl   $24,$24,7
23122		 andi  $24,$24,0x1C
23123		 addu  $24,$24,$21
23124		 lw    $18,0x00($24)
23125		 ori   $10,$0,1
23126		 andi  $18,$18,0x07
23127		 sllv  $9,$10,$18
23128		 sll   $8,$8,2
23129		 addu  $8,$8,$21
23130		 lw    $14,0x20($8)
23131		 lw    $25,0x7C($21)
23132		 sw    $15,m68k_ICount
23133		 sw    $9,0x44($29)
23134		 sw    $14,0x40($29)
23135		 or    $4,$0,$14
23136		 jalr  $25
23137		 sw    $23,0x4C($21)    	 # Delay slot
23138		 lw    $14,0x40($29)
23139		 lw    $9,0x44($29)
23140		 lw    $15,m68k_ICount
23141		 and   $10,$9,$2
23142		 srlv  $18,$10,$18
23143		 xori  $18,$18,1        	 # Set Zero Flag
23144		 or    $2,$2,$9
23145		 lw    $25,0x88($21)
23146		 sw    $15,m68k_ICount
23147		 or    $5,$0,$2
23148		 or    $4,$0,$14
23149		 jalr  $25
23150		 sw    $23,0x4C($21)    	 # Delay slot
23151		 lw    $15,m68k_ICount
23152		 addiu $15,$15,-12
23153		 bgez  $15,3f
23154		 lhu   $24,0x00($23)    	 # Delay slot
23155		 j     MainExit
23156	3:
23157		 sll   $7,$24,2         	 # Delay slot
23158		 addu  $7,$7,$30
23159		 lw    $7,0x00($7)
23160		 jr    $7
23161		 nop                    	 # Delay slot
23162
23163OP0_01d8:				#:
23164		 addiu $23,$23,2
23165
23166		 andi  $8,$24,0x07
23167		 srl   $24,$24,7
23168		 andi  $24,$24,0x1C
23169		 addu  $24,$24,$21
23170		 lw    $18,0x00($24)
23171		 ori   $10,$0,1
23172		 andi  $18,$18,0x07
23173		 sllv  $9,$10,$18
23174		 sll   $8,$8,2
23175		 addu  $8,$8,$21
23176		 lw    $14,0x20($8)
23177		 addiu $25,$14,1
23178		 sw    $25,0x20($8)
23179		 lw    $25,0x7C($21)
23180		 sw    $15,m68k_ICount
23181		 sw    $9,0x44($29)
23182		 sw    $14,0x40($29)
23183		 or    $4,$0,$14
23184		 jalr  $25
23185		 sw    $23,0x4C($21)    	 # Delay slot
23186		 lw    $14,0x40($29)
23187		 lw    $9,0x44($29)
23188		 lw    $15,m68k_ICount
23189		 and   $10,$9,$2
23190		 srlv  $18,$10,$18
23191		 xori  $18,$18,1        	 # Set Zero Flag
23192		 or    $2,$2,$9
23193		 lw    $25,0x88($21)
23194		 sw    $15,m68k_ICount
23195		 or    $5,$0,$2
23196		 or    $4,$0,$14
23197		 jalr  $25
23198		 sw    $23,0x4C($21)    	 # Delay slot
23199		 lw    $15,m68k_ICount
23200		 addiu $15,$15,-12
23201		 bgez  $15,3f
23202		 lhu   $24,0x00($23)    	 # Delay slot
23203		 j     MainExit
23204	3:
23205		 sll   $7,$24,2         	 # Delay slot
23206		 addu  $7,$7,$30
23207		 lw    $7,0x00($7)
23208		 jr    $7
23209		 nop                    	 # Delay slot
23210
23211OP0_01df:				#:
23212		 addiu $23,$23,2
23213
23214		 srl   $24,$24,7
23215		 andi  $24,$24,0x1C
23216		 addu  $24,$24,$21
23217		 lw    $18,0x00($24)
23218		 ori   $10,$0,1
23219		 andi  $18,$18,0x07
23220		 sllv  $9,$10,$18
23221		 lw    $14,0x3C($21)    	 # Get A7
23222		 addiu $25,$14,2
23223		 sw    $25,0x3C($21)
23224		 lw    $25,0x7C($21)
23225		 sw    $15,m68k_ICount
23226		 sw    $9,0x44($29)
23227		 sw    $14,0x40($29)
23228		 or    $4,$0,$14
23229		 jalr  $25
23230		 sw    $23,0x4C($21)    	 # Delay slot
23231		 lw    $14,0x40($29)
23232		 lw    $9,0x44($29)
23233		 lw    $15,m68k_ICount
23234		 and   $10,$9,$2
23235		 srlv  $18,$10,$18
23236		 xori  $18,$18,1        	 # Set Zero Flag
23237		 or    $2,$2,$9
23238		 lw    $25,0x88($21)
23239		 sw    $15,m68k_ICount
23240		 or    $5,$0,$2
23241		 or    $4,$0,$14
23242		 jalr  $25
23243		 sw    $23,0x4C($21)    	 # Delay slot
23244		 lw    $15,m68k_ICount
23245		 addiu $15,$15,-12
23246		 bgez  $15,3f
23247		 lhu   $24,0x00($23)    	 # Delay slot
23248		 j     MainExit
23249	3:
23250		 sll   $7,$24,2         	 # Delay slot
23251		 addu  $7,$7,$30
23252		 lw    $7,0x00($7)
23253		 jr    $7
23254		 nop                    	 # Delay slot
23255
23256OP0_01e0:				#:
23257		 addiu $23,$23,2
23258
23259		 andi  $8,$24,0x07
23260		 srl   $24,$24,7
23261		 andi  $24,$24,0x1C
23262		 addu  $24,$24,$21
23263		 lw    $18,0x00($24)
23264		 ori   $10,$0,1
23265		 andi  $18,$18,0x07
23266		 sllv  $9,$10,$18
23267		 sll   $8,$8,2
23268		 addu  $8,$8,$21
23269		 lw    $14,0x20($8)
23270		 addiu $14,$14,-1
23271		 sw    $14,0x20($8)
23272		 lw    $25,0x7C($21)
23273		 sw    $15,m68k_ICount
23274		 sw    $9,0x44($29)
23275		 sw    $14,0x40($29)
23276		 or    $4,$0,$14
23277		 jalr  $25
23278		 sw    $23,0x4C($21)    	 # Delay slot
23279		 lw    $14,0x40($29)
23280		 lw    $9,0x44($29)
23281		 lw    $15,m68k_ICount
23282		 and   $10,$9,$2
23283		 srlv  $18,$10,$18
23284		 xori  $18,$18,1        	 # Set Zero Flag
23285		 or    $2,$2,$9
23286		 lw    $25,0x88($21)
23287		 sw    $15,m68k_ICount
23288		 or    $5,$0,$2
23289		 or    $4,$0,$14
23290		 jalr  $25
23291		 sw    $23,0x4C($21)    	 # Delay slot
23292		 lw    $15,m68k_ICount
23293		 addiu $15,$15,-14
23294		 bgez  $15,3f
23295		 lhu   $24,0x00($23)    	 # Delay slot
23296		 j     MainExit
23297	3:
23298		 sll   $7,$24,2         	 # Delay slot
23299		 addu  $7,$7,$30
23300		 lw    $7,0x00($7)
23301		 jr    $7
23302		 nop                    	 # Delay slot
23303
23304OP0_01e7:				#:
23305		 addiu $23,$23,2
23306
23307		 srl   $24,$24,7
23308		 andi  $24,$24,0x1C
23309		 addu  $24,$24,$21
23310		 lw    $18,0x00($24)
23311		 ori   $10,$0,1
23312		 andi  $18,$18,0x07
23313		 sllv  $9,$10,$18
23314		 lw    $14,0x3C($21)    	 # Get A7
23315		 addiu $14,$14,-2
23316		 sw    $14,0x3C($21)
23317		 lw    $25,0x7C($21)
23318		 sw    $15,m68k_ICount
23319		 sw    $9,0x44($29)
23320		 sw    $14,0x40($29)
23321		 or    $4,$0,$14
23322		 jalr  $25
23323		 sw    $23,0x4C($21)    	 # Delay slot
23324		 lw    $14,0x40($29)
23325		 lw    $9,0x44($29)
23326		 lw    $15,m68k_ICount
23327		 and   $10,$9,$2
23328		 srlv  $18,$10,$18
23329		 xori  $18,$18,1        	 # Set Zero Flag
23330		 or    $2,$2,$9
23331		 lw    $25,0x88($21)
23332		 sw    $15,m68k_ICount
23333		 or    $5,$0,$2
23334		 or    $4,$0,$14
23335		 jalr  $25
23336		 sw    $23,0x4C($21)    	 # Delay slot
23337		 lw    $15,m68k_ICount
23338		 addiu $15,$15,-14
23339		 bgez  $15,3f
23340		 lhu   $24,0x00($23)    	 # Delay slot
23341		 j     MainExit
23342	3:
23343		 sll   $7,$24,2         	 # Delay slot
23344		 addu  $7,$7,$30
23345		 lw    $7,0x00($7)
23346		 jr    $7
23347		 nop                    	 # Delay slot
23348
23349OP0_01e8:				#:
23350		 addiu $23,$23,2
23351
23352		 andi  $8,$24,0x07
23353		 srl   $24,$24,7
23354		 andi  $24,$24,0x1C
23355		 addu  $24,$24,$21
23356		 lw    $18,0x00($24)
23357		 ori   $10,$0,1
23358		 andi  $18,$18,0x07
23359		 sllv  $9,$10,$18
23360		 lh    $7,0x00($23)
23361		 sll   $8,$8,2
23362		 addu  $8,$8,$21
23363		 lw    $14,0x20($8)
23364		 addiu $23,$23,2
23365		 addu  $14,$14,$7
23366		 lw    $25,0x7C($21)
23367		 sw    $15,m68k_ICount
23368		 sw    $9,0x44($29)
23369		 sw    $14,0x40($29)
23370		 or    $4,$0,$14
23371		 jalr  $25
23372		 sw    $23,0x4C($21)    	 # Delay slot
23373		 lw    $14,0x40($29)
23374		 lw    $9,0x44($29)
23375		 lw    $15,m68k_ICount
23376		 and   $10,$9,$2
23377		 srlv  $18,$10,$18
23378		 xori  $18,$18,1        	 # Set Zero Flag
23379		 or    $2,$2,$9
23380		 lw    $25,0x88($21)
23381		 sw    $15,m68k_ICount
23382		 or    $5,$0,$2
23383		 or    $4,$0,$14
23384		 jalr  $25
23385		 sw    $23,0x4C($21)    	 # Delay slot
23386		 lw    $15,m68k_ICount
23387		 addiu $15,$15,-16
23388		 bgez  $15,3f
23389		 lhu   $24,0x00($23)    	 # Delay slot
23390		 j     MainExit
23391	3:
23392		 sll   $7,$24,2         	 # Delay slot
23393		 addu  $7,$7,$30
23394		 lw    $7,0x00($7)
23395		 jr    $7
23396		 nop                    	 # Delay slot
23397
23398OP0_01f0:				#:
23399		 addiu $23,$23,2
23400
23401		 andi  $8,$24,0x07
23402		 srl   $24,$24,7
23403		 andi  $24,$24,0x1C
23404		 addu  $24,$24,$21
23405		 lw    $18,0x00($24)
23406		 ori   $10,$0,1
23407		 andi  $18,$18,0x07
23408		 sllv  $9,$10,$18
23409		 sll   $8,$8,2
23410		 addu  $8,$8,$21
23411		 lw    $14,0x20($8)
23412		 lhu   $7,0x00($23)
23413		 addiu $23,$23,2
23414		 seb   $6,$7
23415		 or    $25,$0,$7
23416		 srl   $7,$7,12
23417		 andi  $25,$25,0x0800
23418		 sll   $7,$7,2
23419		 addu  $7,$7,$21
23420		 bne   $25,$0,0f
23421		 lw    $25,0x00($7)      	 # Delay slot
23422		 seh   $25,$25
23423	0:
23424		 addu  $25,$14,$25
23425		 addu  $14,$25,$6
23426		 lw    $25,0x7C($21)
23427		 sw    $15,m68k_ICount
23428		 sw    $9,0x44($29)
23429		 sw    $14,0x40($29)
23430		 or    $4,$0,$14
23431		 jalr  $25
23432		 sw    $23,0x4C($21)    	 # Delay slot
23433		 lw    $14,0x40($29)
23434		 lw    $9,0x44($29)
23435		 lw    $15,m68k_ICount
23436		 and   $10,$9,$2
23437		 srlv  $18,$10,$18
23438		 xori  $18,$18,1        	 # Set Zero Flag
23439		 or    $2,$2,$9
23440		 lw    $25,0x88($21)
23441		 sw    $15,m68k_ICount
23442		 or    $5,$0,$2
23443		 or    $4,$0,$14
23444		 jalr  $25
23445		 sw    $23,0x4C($21)    	 # Delay slot
23446		 lw    $15,m68k_ICount
23447		 addiu $15,$15,-18
23448		 bgez  $15,3f
23449		 lhu   $24,0x00($23)    	 # Delay slot
23450		 j     MainExit
23451	3:
23452		 sll   $7,$24,2         	 # Delay slot
23453		 addu  $7,$7,$30
23454		 lw    $7,0x00($7)
23455		 jr    $7
23456		 nop                    	 # Delay slot
23457
23458OP0_01f8:				#:
23459		 addiu $23,$23,2
23460
23461		 srl   $24,$24,7
23462		 andi  $24,$24,0x1C
23463		 addu  $24,$24,$21
23464		 lw    $18,0x00($24)
23465		 ori   $10,$0,1
23466		 andi  $18,$18,0x07
23467		 sllv  $9,$10,$18
23468		 lh    $14,0x00($23)
23469		 addiu $23,$23,2
23470		 lw    $25,0x7C($21)
23471		 sw    $15,m68k_ICount
23472		 sw    $9,0x44($29)
23473		 sw    $14,0x40($29)
23474		 or    $4,$0,$14
23475		 jalr  $25
23476		 sw    $23,0x4C($21)    	 # Delay slot
23477		 lw    $14,0x40($29)
23478		 lw    $9,0x44($29)
23479		 lw    $15,m68k_ICount
23480		 and   $10,$9,$2
23481		 srlv  $18,$10,$18
23482		 xori  $18,$18,1        	 # Set Zero Flag
23483		 or    $2,$2,$9
23484		 lw    $25,0x88($21)
23485		 sw    $15,m68k_ICount
23486		 or    $5,$0,$2
23487		 or    $4,$0,$14
23488		 jalr  $25
23489		 sw    $23,0x4C($21)    	 # Delay slot
23490		 lw    $15,m68k_ICount
23491		 addiu $15,$15,-16
23492		 bgez  $15,3f
23493		 lhu   $24,0x00($23)    	 # Delay slot
23494		 j     MainExit
23495	3:
23496		 sll   $7,$24,2         	 # Delay slot
23497		 addu  $7,$7,$30
23498		 lw    $7,0x00($7)
23499		 jr    $7
23500		 nop                    	 # Delay slot
23501
23502OP0_01f9:				#:
23503		 addiu $23,$23,2
23504
23505		 srl   $24,$24,7
23506		 andi  $24,$24,0x1C
23507		 addu  $24,$24,$21
23508		 lw    $18,0x00($24)
23509		 ori   $10,$0,1
23510		 andi  $18,$18,0x07
23511		 sllv  $9,$10,$18
23512		 lhu   $14,0x00($23)
23513		 lhu   $25,0x02($23)
23514		 sll   $14,$14,16
23515		 or    $14,$14,$25
23516		 addiu $23,$23,4
23517		 lw    $25,0x7C($21)
23518		 sw    $15,m68k_ICount
23519		 sw    $9,0x44($29)
23520		 sw    $14,0x40($29)
23521		 or    $4,$0,$14
23522		 jalr  $25
23523		 sw    $23,0x4C($21)    	 # Delay slot
23524		 lw    $14,0x40($29)
23525		 lw    $9,0x44($29)
23526		 lw    $15,m68k_ICount
23527		 and   $10,$9,$2
23528		 srlv  $18,$10,$18
23529		 xori  $18,$18,1        	 # Set Zero Flag
23530		 or    $2,$2,$9
23531		 lw    $25,0x88($21)
23532		 sw    $15,m68k_ICount
23533		 or    $5,$0,$2
23534		 or    $4,$0,$14
23535		 jalr  $25
23536		 sw    $23,0x4C($21)    	 # Delay slot
23537		 lw    $15,m68k_ICount
23538		 addiu $15,$15,-20
23539		 bgez  $15,3f
23540		 lhu   $24,0x00($23)    	 # Delay slot
23541		 j     MainExit
23542	3:
23543		 sll   $7,$24,2         	 # Delay slot
23544		 addu  $7,$7,$30
23545		 lw    $7,0x00($7)
23546		 jr    $7
23547		 nop                    	 # Delay slot
23548
23549OP0_0108:				#:
23550		 addiu $23,$23,2
23551
23552		 andi  $8,$24,0x07
23553		 lh    $7,0x00($23)
23554		 sll   $8,$8,2
23555		 addu  $8,$8,$21
23556		 lw    $14,0x20($8)
23557		 addiu $23,$23,2
23558		 addu  $14,$14,$7
23559		 srl   $24,$24,7
23560		 andi  $24,$24,0x1C
23561		 addu  $24,$24,$21
23562		 lw    $25,0x7C($21)
23563		 sw    $15,m68k_ICount
23564		 sw    $14,0x44($29)
23565		 sw    $24,0x40($29)
23566		 or    $4,$0,$14
23567		 jalr  $25
23568		 sw    $23,0x4C($21)    	 # Delay slot
23569		 lw    $24,0x40($29)
23570		 lw    $14,0x44($29)
23571		 lw    $15,m68k_ICount
23572		 sll   $8,$2,8
23573		 addiu $14,$14,2
23574		 lw    $25,0x7C($21)
23575		 sw    $15,m68k_ICount
23576		 sw    $8,0x44($29)
23577		 sw    $24,0x40($29)
23578		 or    $4,$0,$14
23579		 jalr  $25
23580		 sw    $23,0x4C($21)    	 # Delay slot
23581		 lw    $24,0x40($29)
23582		 lw    $8,0x44($29)
23583		 lw    $15,m68k_ICount
23584		 or    $8,$8,$2
23585		 sh    $8,0x00($24)
23586		 addiu $15,$15,-28
23587		 bgez  $15,3f
23588		 lhu   $24,0x00($23)    	 # Delay slot
23589		 j     MainExit
23590	3:
23591		 sll   $7,$24,2         	 # Delay slot
23592		 addu  $7,$7,$30
23593		 lw    $7,0x00($7)
23594		 jr    $7
23595		 nop                    	 # Delay slot
23596
23597OP0_0148:				#:
23598		 addiu $23,$23,2
23599
23600		 andi  $8,$24,0x07
23601		 lh    $7,0x00($23)
23602		 sll   $8,$8,2
23603		 addu  $8,$8,$21
23604		 lw    $14,0x20($8)
23605		 addiu $23,$23,2
23606		 addu  $14,$14,$7
23607		 srl   $24,$24,7
23608		 andi  $24,$24,0x1C
23609		 addu  $24,$24,$21
23610		 lw    $25,0x7C($21)
23611		 sw    $15,m68k_ICount
23612		 sw    $8,0x44($29)
23613		 sw    $14,0x40($29)
23614		 sw    $24,0x3C($29)
23615		 or    $4,$0,$14
23616		 jalr  $25
23617		 sw    $23,0x4C($21)    	 # Delay slot
23618		 lw    $24,0x3C($29)
23619		 lw    $14,0x40($29)
23620		 lw    $8,0x44($29)
23621		 lw    $15,m68k_ICount
23622		 sll   $8,$2,8
23623		 addiu $14,$14,2
23624		 lw    $25,0x7C($21)
23625		 sw    $15,m68k_ICount
23626		 sw    $8,0x44($29)
23627		 sw    $14,0x40($29)
23628		 sw    $24,0x3C($29)
23629		 or    $4,$0,$14
23630		 jalr  $25
23631		 sw    $23,0x4C($21)    	 # Delay slot
23632		 lw    $24,0x3C($29)
23633		 lw    $14,0x40($29)
23634		 lw    $8,0x44($29)
23635		 lw    $15,m68k_ICount
23636		 or    $8,$8,$2
23637		 addiu $14,$14,2
23638		 sll   $8,$2,16
23639		 lw    $25,0x7C($21)
23640		 sw    $15,m68k_ICount
23641		 sw    $8,0x44($29)
23642		 sw    $14,0x40($29)
23643		 sw    $24,0x3C($29)
23644		 or    $4,$0,$14
23645		 jalr  $25
23646		 sw    $23,0x4C($21)    	 # Delay slot
23647		 lw    $24,0x3C($29)
23648		 lw    $14,0x40($29)
23649		 lw    $8,0x44($29)
23650		 lw    $15,m68k_ICount
23651		 sll   $9,$2,8
23652		 addiu $14,$14,2
23653		 lw    $25,0x7C($21)
23654		 sw    $15,m68k_ICount
23655		 sw    $8,0x44($29)
23656		 sw    $24,0x40($29)
23657		 or    $4,$0,$14
23658		 jalr  $25
23659		 sw    $23,0x4C($21)    	 # Delay slot
23660		 lw    $24,0x40($29)
23661		 lw    $8,0x44($29)
23662		 lw    $15,m68k_ICount
23663		 or    $8,$8,$9
23664		 or    $8,$8,$2
23665		 sw    $8,0x00($24)
23666		 addiu $15,$15,-36
23667		 bgez  $15,3f
23668		 lhu   $24,0x00($23)    	 # Delay slot
23669		 j     MainExit
23670	3:
23671		 sll   $7,$24,2         	 # Delay slot
23672		 addu  $7,$7,$30
23673		 lw    $7,0x00($7)
23674		 jr    $7
23675		 nop                    	 # Delay slot
23676
23677OP0_0188:				#:
23678		 addiu $23,$23,2
23679
23680		 andi  $8,$24,0x07
23681		 lh    $7,0x00($23)
23682		 sll   $8,$8,2
23683		 addu  $8,$8,$21
23684		 lw    $14,0x20($8)
23685		 addiu $23,$23,2
23686		 addu  $14,$14,$7
23687		 srl   $24,$24,7
23688		 andi  $24,$24,0x1C
23689		 addu  $24,$24,$21
23690		 lw    $24,0x00($24)
23691		 sll   $5,$24,8
23692		 lw    $25,0x88($21)
23693		 sw    $15,m68k_ICount
23694		 sw    $8,0x44($29)
23695		 sw    $14,0x40($29)
23696		 sw    $24,0x3C($29)
23697		 or    $4,$0,$14
23698		 jalr  $25
23699		 sw    $23,0x4C($21)    	 # Delay slot
23700		 lw    $24,0x3C($29)
23701		 lw    $14,0x40($29)
23702		 lw    $8,0x44($29)
23703		 lw    $15,m68k_ICount
23704		 addiu $14,$14,2
23705		 or    $5,$0,$24
23706		 lw    $25,0x88($21)
23707		 sw    $15,m68k_ICount
23708		 sw    $8,0x44($29)
23709		 or    $4,$0,$14
23710		 jalr  $25
23711		 sw    $23,0x4C($21)    	 # Delay slot
23712		 lw    $8,0x44($29)
23713		 lw    $15,m68k_ICount
23714		 addiu $15,$15,-28
23715		 bgez  $15,3f
23716		 lhu   $24,0x00($23)    	 # Delay slot
23717		 j     MainExit
23718	3:
23719		 sll   $7,$24,2         	 # Delay slot
23720		 addu  $7,$7,$30
23721		 lw    $7,0x00($7)
23722		 jr    $7
23723		 nop                    	 # Delay slot
23724
23725OP0_01c8:				#:
23726		 addiu $23,$23,2
23727
23728		 andi  $8,$24,0x07
23729		 lh    $7,0x00($23)
23730		 sll   $8,$8,2
23731		 addu  $8,$8,$21
23732		 lw    $14,0x20($8)
23733		 addiu $23,$23,2
23734		 addu  $14,$14,$7
23735		 srl   $24,$24,7
23736		 andi  $24,$24,0x1C
23737		 addu  $24,$24,$21
23738		 lw    $24,0x00($24)
23739		 sll   $5,$24,24
23740		 lw    $25,0x88($21)
23741		 sw    $15,m68k_ICount
23742		 sw    $8,0x44($29)
23743		 sw    $14,0x40($29)
23744		 sw    $24,0x3C($29)
23745		 or    $4,$0,$14
23746		 jalr  $25
23747		 sw    $23,0x4C($21)    	 # Delay slot
23748		 lw    $24,0x3C($29)
23749		 lw    $14,0x40($29)
23750		 lw    $8,0x44($29)
23751		 lw    $15,m68k_ICount
23752		 addiu $14,$14,2
23753		 sll   $5,$24,16
23754		 lw    $25,0x88($21)
23755		 sw    $15,m68k_ICount
23756		 sw    $8,0x44($29)
23757		 sw    $14,0x40($29)
23758		 sw    $24,0x3C($29)
23759		 or    $4,$0,$14
23760		 jalr  $25
23761		 sw    $23,0x4C($21)    	 # Delay slot
23762		 lw    $24,0x3C($29)
23763		 lw    $14,0x40($29)
23764		 lw    $8,0x44($29)
23765		 lw    $15,m68k_ICount
23766		 addiu $14,$14,2
23767		 sll   $5,$24,8
23768		 lw    $25,0x88($21)
23769		 sw    $15,m68k_ICount
23770		 sw    $8,0x44($29)
23771		 sw    $14,0x40($29)
23772		 sw    $24,0x3C($29)
23773		 or    $4,$0,$14
23774		 jalr  $25
23775		 sw    $23,0x4C($21)    	 # Delay slot
23776		 lw    $24,0x3C($29)
23777		 lw    $14,0x40($29)
23778		 lw    $8,0x44($29)
23779		 lw    $15,m68k_ICount
23780		 addiu $14,$14,2
23781		 or    $5,$0,$24
23782		 lw    $25,0x88($21)
23783		 sw    $15,m68k_ICount
23784		 sw    $8,0x44($29)
23785		 or    $4,$0,$14
23786		 jalr  $25
23787		 sw    $23,0x4C($21)    	 # Delay slot
23788		 lw    $8,0x44($29)
23789		 lw    $15,m68k_ICount
23790		 addiu $15,$15,-36
23791		 bgez  $15,3f
23792		 lhu   $24,0x00($23)    	 # Delay slot
23793		 j     MainExit
23794	3:
23795		 sll   $7,$24,2         	 # Delay slot
23796		 addu  $7,$7,$30
23797		 lw    $7,0x00($7)
23798		 jr    $7
23799		 nop                    	 # Delay slot
23800
23801OP0_0800:				#:
23802		 addiu $23,$23,2
23803
23804		 andi  $8,$24,0x07
23805		 lhu   $18,0x00($23)
23806		 addiu $23,$23,2
23807		 ori   $10,$0,1
23808		 sllv  $9,$10,$18
23809		 sll   $8,$8,2
23810		 addu  $8,$8,$21
23811		 lw    $2,0x00($8)
23812		 and   $10,$9,$2
23813		 srlv  $18,$10,$18
23814		 xori  $18,$18,1        	 # Set Zero Flag
23815		 addiu $15,$15,-10
23816		 bgez  $15,3f
23817		 lhu   $24,0x00($23)    	 # Delay slot
23818		 j     MainExit
23819	3:
23820		 sll   $7,$24,2         	 # Delay slot
23821		 addu  $7,$7,$30
23822		 lw    $7,0x00($7)
23823		 jr    $7
23824		 nop                    	 # Delay slot
23825
23826OP0_0810:				#:
23827		 addiu $23,$23,2
23828
23829		 andi  $8,$24,0x07
23830		 lhu   $18,0x00($23)
23831		 addiu $23,$23,2
23832		 and   $18,$18,0x07
23833		 ori   $10,$0,1
23834		 sllv  $9,$10,$18
23835		 sll   $8,$8,2
23836		 addu  $8,$8,$21
23837		 lw    $14,0x20($8)
23838		 lw    $25,0x7C($21)
23839		 sw    $15,m68k_ICount
23840		 sw    $9,0x44($29)
23841		 sw    $14,0x40($29)
23842		 or    $4,$0,$14
23843		 jalr  $25
23844		 sw    $23,0x4C($21)    	 # Delay slot
23845		 lw    $14,0x40($29)
23846		 lw    $9,0x44($29)
23847		 lw    $15,m68k_ICount
23848		 and   $10,$9,$2
23849		 srlv  $18,$10,$18
23850		 xori  $18,$18,1        	 # Set Zero Flag
23851		 addiu $15,$15,-12
23852		 bgez  $15,3f
23853		 lhu   $24,0x00($23)    	 # Delay slot
23854		 j     MainExit
23855	3:
23856		 sll   $7,$24,2         	 # Delay slot
23857		 addu  $7,$7,$30
23858		 lw    $7,0x00($7)
23859		 jr    $7
23860		 nop                    	 # Delay slot
23861
23862OP0_0818:				#:
23863		 addiu $23,$23,2
23864
23865		 andi  $8,$24,0x07
23866		 lhu   $18,0x00($23)
23867		 addiu $23,$23,2
23868		 and   $18,$18,0x07
23869		 ori   $10,$0,1
23870		 sllv  $9,$10,$18
23871		 sll   $8,$8,2
23872		 addu  $8,$8,$21
23873		 lw    $14,0x20($8)
23874		 addiu $25,$14,1
23875		 sw    $25,0x20($8)
23876		 lw    $25,0x7C($21)
23877		 sw    $15,m68k_ICount
23878		 sw    $9,0x44($29)
23879		 sw    $14,0x40($29)
23880		 or    $4,$0,$14
23881		 jalr  $25
23882		 sw    $23,0x4C($21)    	 # Delay slot
23883		 lw    $14,0x40($29)
23884		 lw    $9,0x44($29)
23885		 lw    $15,m68k_ICount
23886		 and   $10,$9,$2
23887		 srlv  $18,$10,$18
23888		 xori  $18,$18,1        	 # Set Zero Flag
23889		 addiu $15,$15,-12
23890		 bgez  $15,3f
23891		 lhu   $24,0x00($23)    	 # Delay slot
23892		 j     MainExit
23893	3:
23894		 sll   $7,$24,2         	 # Delay slot
23895		 addu  $7,$7,$30
23896		 lw    $7,0x00($7)
23897		 jr    $7
23898		 nop                    	 # Delay slot
23899
23900OP0_081f:				#:
23901		 addiu $23,$23,2
23902
23903		 lhu   $18,0x00($23)
23904		 addiu $23,$23,2
23905		 and   $18,$18,0x07
23906		 ori   $10,$0,1
23907		 sllv  $9,$10,$18
23908		 lw    $14,0x3C($21)    	 # Get A7
23909		 addiu $25,$14,2
23910		 sw    $25,0x3C($21)
23911		 lw    $25,0x7C($21)
23912		 sw    $15,m68k_ICount
23913		 sw    $9,0x44($29)
23914		 sw    $14,0x40($29)
23915		 or    $4,$0,$14
23916		 jalr  $25
23917		 sw    $23,0x4C($21)    	 # Delay slot
23918		 lw    $14,0x40($29)
23919		 lw    $9,0x44($29)
23920		 lw    $15,m68k_ICount
23921		 and   $10,$9,$2
23922		 srlv  $18,$10,$18
23923		 xori  $18,$18,1        	 # Set Zero Flag
23924		 addiu $15,$15,-12
23925		 bgez  $15,3f
23926		 lhu   $24,0x00($23)    	 # Delay slot
23927		 j     MainExit
23928	3:
23929		 sll   $7,$24,2         	 # Delay slot
23930		 addu  $7,$7,$30
23931		 lw    $7,0x00($7)
23932		 jr    $7
23933		 nop                    	 # Delay slot
23934
23935OP0_0820:				#:
23936		 addiu $23,$23,2
23937
23938		 andi  $8,$24,0x07
23939		 lhu   $18,0x00($23)
23940		 addiu $23,$23,2
23941		 and   $18,$18,0x07
23942		 ori   $10,$0,1
23943		 sllv  $9,$10,$18
23944		 sll   $8,$8,2
23945		 addu  $8,$8,$21
23946		 lw    $14,0x20($8)
23947		 addiu $14,$14,-1
23948		 sw    $14,0x20($8)
23949		 lw    $25,0x7C($21)
23950		 sw    $15,m68k_ICount
23951		 sw    $9,0x44($29)
23952		 sw    $14,0x40($29)
23953		 or    $4,$0,$14
23954		 jalr  $25
23955		 sw    $23,0x4C($21)    	 # Delay slot
23956		 lw    $14,0x40($29)
23957		 lw    $9,0x44($29)
23958		 lw    $15,m68k_ICount
23959		 and   $10,$9,$2
23960		 srlv  $18,$10,$18
23961		 xori  $18,$18,1        	 # Set Zero Flag
23962		 addiu $15,$15,-14
23963		 bgez  $15,3f
23964		 lhu   $24,0x00($23)    	 # Delay slot
23965		 j     MainExit
23966	3:
23967		 sll   $7,$24,2         	 # Delay slot
23968		 addu  $7,$7,$30
23969		 lw    $7,0x00($7)
23970		 jr    $7
23971		 nop                    	 # Delay slot
23972
23973OP0_0827:				#:
23974		 addiu $23,$23,2
23975
23976		 lhu   $18,0x00($23)
23977		 addiu $23,$23,2
23978		 and   $18,$18,0x07
23979		 ori   $10,$0,1
23980		 sllv  $9,$10,$18
23981		 lw    $14,0x3C($21)    	 # Get A7
23982		 addiu $14,$14,-2
23983		 sw    $14,0x3C($21)
23984		 lw    $25,0x7C($21)
23985		 sw    $15,m68k_ICount
23986		 sw    $9,0x44($29)
23987		 sw    $14,0x40($29)
23988		 or    $4,$0,$14
23989		 jalr  $25
23990		 sw    $23,0x4C($21)    	 # Delay slot
23991		 lw    $14,0x40($29)
23992		 lw    $9,0x44($29)
23993		 lw    $15,m68k_ICount
23994		 and   $10,$9,$2
23995		 srlv  $18,$10,$18
23996		 xori  $18,$18,1        	 # Set Zero Flag
23997		 addiu $15,$15,-14
23998		 bgez  $15,3f
23999		 lhu   $24,0x00($23)    	 # Delay slot
24000		 j     MainExit
24001	3:
24002		 sll   $7,$24,2         	 # Delay slot
24003		 addu  $7,$7,$30
24004		 lw    $7,0x00($7)
24005		 jr    $7
24006		 nop                    	 # Delay slot
24007
24008OP0_0828:				#:
24009		 addiu $23,$23,2
24010
24011		 andi  $8,$24,0x07
24012		 lhu   $18,0x00($23)
24013		 addiu $23,$23,2
24014		 and   $18,$18,0x07
24015		 ori   $10,$0,1
24016		 sllv  $9,$10,$18
24017		 lh    $7,0x00($23)
24018		 sll   $8,$8,2
24019		 addu  $8,$8,$21
24020		 lw    $14,0x20($8)
24021		 addiu $23,$23,2
24022		 addu  $14,$14,$7
24023		 lw    $25,0x7C($21)
24024		 sw    $15,m68k_ICount
24025		 sw    $9,0x44($29)
24026		 sw    $14,0x40($29)
24027		 or    $4,$0,$14
24028		 jalr  $25
24029		 sw    $23,0x4C($21)    	 # Delay slot
24030		 lw    $14,0x40($29)
24031		 lw    $9,0x44($29)
24032		 lw    $15,m68k_ICount
24033		 and   $10,$9,$2
24034		 srlv  $18,$10,$18
24035		 xori  $18,$18,1        	 # Set Zero Flag
24036		 addiu $15,$15,-16
24037		 bgez  $15,3f
24038		 lhu   $24,0x00($23)    	 # Delay slot
24039		 j     MainExit
24040	3:
24041		 sll   $7,$24,2         	 # Delay slot
24042		 addu  $7,$7,$30
24043		 lw    $7,0x00($7)
24044		 jr    $7
24045		 nop                    	 # Delay slot
24046
24047OP0_0830:				#:
24048		 addiu $23,$23,2
24049
24050		 andi  $8,$24,0x07
24051		 lhu   $18,0x00($23)
24052		 addiu $23,$23,2
24053		 and   $18,$18,0x07
24054		 ori   $10,$0,1
24055		 sllv  $9,$10,$18
24056		 sll   $8,$8,2
24057		 addu  $8,$8,$21
24058		 lw    $14,0x20($8)
24059		 lhu   $7,0x00($23)
24060		 addiu $23,$23,2
24061		 seb   $6,$7
24062		 or    $25,$0,$7
24063		 srl   $7,$7,12
24064		 andi  $25,$25,0x0800
24065		 sll   $7,$7,2
24066		 addu  $7,$7,$21
24067		 bne   $25,$0,0f
24068		 lw    $25,0x00($7)      	 # Delay slot
24069		 seh   $25,$25
24070	0:
24071		 addu  $25,$14,$25
24072		 addu  $14,$25,$6
24073		 lw    $25,0x7C($21)
24074		 sw    $15,m68k_ICount
24075		 sw    $9,0x44($29)
24076		 sw    $14,0x40($29)
24077		 or    $4,$0,$14
24078		 jalr  $25
24079		 sw    $23,0x4C($21)    	 # Delay slot
24080		 lw    $14,0x40($29)
24081		 lw    $9,0x44($29)
24082		 lw    $15,m68k_ICount
24083		 and   $10,$9,$2
24084		 srlv  $18,$10,$18
24085		 xori  $18,$18,1        	 # Set Zero Flag
24086		 addiu $15,$15,-18
24087		 bgez  $15,3f
24088		 lhu   $24,0x00($23)    	 # Delay slot
24089		 j     MainExit
24090	3:
24091		 sll   $7,$24,2         	 # Delay slot
24092		 addu  $7,$7,$30
24093		 lw    $7,0x00($7)
24094		 jr    $7
24095		 nop                    	 # Delay slot
24096
24097OP0_0838:				#:
24098		 addiu $23,$23,2
24099
24100		 lhu   $18,0x00($23)
24101		 addiu $23,$23,2
24102		 and   $18,$18,0x07
24103		 ori   $10,$0,1
24104		 sllv  $9,$10,$18
24105		 lh    $14,0x00($23)
24106		 addiu $23,$23,2
24107		 lw    $25,0x7C($21)
24108		 sw    $15,m68k_ICount
24109		 sw    $9,0x44($29)
24110		 sw    $14,0x40($29)
24111		 or    $4,$0,$14
24112		 jalr  $25
24113		 sw    $23,0x4C($21)    	 # Delay slot
24114		 lw    $14,0x40($29)
24115		 lw    $9,0x44($29)
24116		 lw    $15,m68k_ICount
24117		 and   $10,$9,$2
24118		 srlv  $18,$10,$18
24119		 xori  $18,$18,1        	 # Set Zero Flag
24120		 addiu $15,$15,-16
24121		 bgez  $15,3f
24122		 lhu   $24,0x00($23)    	 # Delay slot
24123		 j     MainExit
24124	3:
24125		 sll   $7,$24,2         	 # Delay slot
24126		 addu  $7,$7,$30
24127		 lw    $7,0x00($7)
24128		 jr    $7
24129		 nop                    	 # Delay slot
24130
24131OP0_0839:				#:
24132		 addiu $23,$23,2
24133
24134		 lhu   $18,0x00($23)
24135		 addiu $23,$23,2
24136		 and   $18,$18,0x07
24137		 ori   $10,$0,1
24138		 sllv  $9,$10,$18
24139		 lhu   $14,0x00($23)
24140		 lhu   $25,0x02($23)
24141		 sll   $14,$14,16
24142		 or    $14,$14,$25
24143		 addiu $23,$23,4
24144		 lw    $25,0x7C($21)
24145		 sw    $15,m68k_ICount
24146		 sw    $9,0x44($29)
24147		 sw    $14,0x40($29)
24148		 or    $4,$0,$14
24149		 jalr  $25
24150		 sw    $23,0x4C($21)    	 # Delay slot
24151		 lw    $14,0x40($29)
24152		 lw    $9,0x44($29)
24153		 lw    $15,m68k_ICount
24154		 and   $10,$9,$2
24155		 srlv  $18,$10,$18
24156		 xori  $18,$18,1        	 # Set Zero Flag
24157		 addiu $15,$15,-20
24158		 bgez  $15,3f
24159		 lhu   $24,0x00($23)    	 # Delay slot
24160		 j     MainExit
24161	3:
24162		 sll   $7,$24,2         	 # Delay slot
24163		 addu  $7,$7,$30
24164		 lw    $7,0x00($7)
24165		 jr    $7
24166		 nop                    	 # Delay slot
24167
24168OP0_083a:				#:
24169		 addiu $23,$23,2
24170
24171		 lhu   $18,0x00($23)
24172		 addiu $23,$23,2
24173		 and   $18,$18,0x07
24174		 ori   $10,$0,1
24175		 sllv  $9,$10,$18
24176		 lh    $7,0x00($23)
24177		 subu  $25,$23,$22
24178		 addu  $14,$25,$7       	 # Add Offset to PC
24179		 addiu $23,$23,2
24180		 lw    $25,0x98($21)
24181		 sw    $15,m68k_ICount
24182		 sw    $9,0x44($29)
24183		 sw    $14,0x40($29)
24184		 or    $4,$0,$14
24185		 jalr  $25
24186		 sw    $23,0x4C($21)    	 # Delay slot
24187		 lw    $14,0x40($29)
24188		 lw    $9,0x44($29)
24189		 lw    $15,m68k_ICount
24190		 and   $10,$9,$2
24191		 srlv  $18,$10,$18
24192		 xori  $18,$18,1        	 # Set Zero Flag
24193		 addiu $15,$15,-16
24194		 bgez  $15,3f
24195		 lhu   $24,0x00($23)    	 # Delay slot
24196		 j     MainExit
24197	3:
24198		 sll   $7,$24,2         	 # Delay slot
24199		 addu  $7,$7,$30
24200		 lw    $7,0x00($7)
24201		 jr    $7
24202		 nop                    	 # Delay slot
24203
24204OP0_083b:				#:
24205		 addiu $23,$23,2
24206
24207		 lhu   $18,0x00($23)
24208		 addiu $23,$23,2
24209		 and   $18,$18,0x07
24210		 ori   $10,$0,1
24211		 sllv  $9,$10,$18
24212		 subu  $14,$23,$22       	 # Get PC
24213		 lhu   $7,0x00($23)
24214		 addiu $23,$23,2
24215		 seb   $6,$7
24216		 or    $25,$0,$7
24217		 srl   $7,$7,12
24218		 andi  $25,$25,0x0800
24219		 sll   $7,$7,2
24220		 addu  $7,$7,$21
24221		 bne   $25,$0,0f
24222		 lw    $25,0x00($7)      	 # Delay slot
24223		 seh   $25,$25
24224	0:
24225		 addu  $25,$14,$25
24226		 addu  $14,$25,$6
24227		 lw    $25,0x98($21)
24228		 sw    $15,m68k_ICount
24229		 sw    $9,0x44($29)
24230		 sw    $14,0x40($29)
24231		 or    $4,$0,$14
24232		 jalr  $25
24233		 sw    $23,0x4C($21)    	 # Delay slot
24234		 lw    $14,0x40($29)
24235		 lw    $9,0x44($29)
24236		 lw    $15,m68k_ICount
24237		 and   $10,$9,$2
24238		 srlv  $18,$10,$18
24239		 xori  $18,$18,1        	 # Set Zero Flag
24240		 addiu $15,$15,-18
24241		 bgez  $15,3f
24242		 lhu   $24,0x00($23)    	 # Delay slot
24243		 j     MainExit
24244	3:
24245		 sll   $7,$24,2         	 # Delay slot
24246		 addu  $7,$7,$30
24247		 lw    $7,0x00($7)
24248		 jr    $7
24249		 nop                    	 # Delay slot
24250
24251OP0_0840:				#:
24252		 addiu $23,$23,2
24253
24254		 andi  $8,$24,0x07
24255		 lhu   $18,0x00($23)
24256		 addiu $23,$23,2
24257		 ori   $10,$0,1
24258		 sllv  $9,$10,$18
24259		 sll   $8,$8,2
24260		 addu  $8,$8,$21
24261		 lw    $2,0x00($8)
24262		 and   $10,$9,$2
24263		 srlv  $18,$10,$18
24264		 xori  $18,$18,1        	 # Set Zero Flag
24265		 xor   $2,$2,$9
24266		 sw    $2,0x00($8)
24267		 addiu $15,$15,-12
24268		 bgez  $15,3f
24269		 lhu   $24,0x00($23)    	 # Delay slot
24270		 j     MainExit
24271	3:
24272		 sll   $7,$24,2         	 # Delay slot
24273		 addu  $7,$7,$30
24274		 lw    $7,0x00($7)
24275		 jr    $7
24276		 nop                    	 # Delay slot
24277
24278OP0_0850:				#:
24279		 addiu $23,$23,2
24280
24281		 andi  $8,$24,0x07
24282		 lhu   $18,0x00($23)
24283		 addiu $23,$23,2
24284		 and   $18,$18,0x07
24285		 ori   $10,$0,1
24286		 sllv  $9,$10,$18
24287		 sll   $8,$8,2
24288		 addu  $8,$8,$21
24289		 lw    $14,0x20($8)
24290		 lw    $25,0x7C($21)
24291		 sw    $15,m68k_ICount
24292		 sw    $9,0x44($29)
24293		 sw    $14,0x40($29)
24294		 or    $4,$0,$14
24295		 jalr  $25
24296		 sw    $23,0x4C($21)    	 # Delay slot
24297		 lw    $14,0x40($29)
24298		 lw    $9,0x44($29)
24299		 lw    $15,m68k_ICount
24300		 and   $10,$9,$2
24301		 srlv  $18,$10,$18
24302		 xori  $18,$18,1        	 # Set Zero Flag
24303		 xor   $2,$2,$9
24304		 lw    $25,0x88($21)
24305		 sw    $15,m68k_ICount
24306		 or    $5,$0,$2
24307		 or    $4,$0,$14
24308		 jalr  $25
24309		 sw    $23,0x4C($21)    	 # Delay slot
24310		 lw    $15,m68k_ICount
24311		 addiu $15,$15,-16
24312		 bgez  $15,3f
24313		 lhu   $24,0x00($23)    	 # Delay slot
24314		 j     MainExit
24315	3:
24316		 sll   $7,$24,2         	 # Delay slot
24317		 addu  $7,$7,$30
24318		 lw    $7,0x00($7)
24319		 jr    $7
24320		 nop                    	 # Delay slot
24321
24322OP0_0858:				#:
24323		 addiu $23,$23,2
24324
24325		 andi  $8,$24,0x07
24326		 lhu   $18,0x00($23)
24327		 addiu $23,$23,2
24328		 and   $18,$18,0x07
24329		 ori   $10,$0,1
24330		 sllv  $9,$10,$18
24331		 sll   $8,$8,2
24332		 addu  $8,$8,$21
24333		 lw    $14,0x20($8)
24334		 addiu $25,$14,1
24335		 sw    $25,0x20($8)
24336		 lw    $25,0x7C($21)
24337		 sw    $15,m68k_ICount
24338		 sw    $9,0x44($29)
24339		 sw    $14,0x40($29)
24340		 or    $4,$0,$14
24341		 jalr  $25
24342		 sw    $23,0x4C($21)    	 # Delay slot
24343		 lw    $14,0x40($29)
24344		 lw    $9,0x44($29)
24345		 lw    $15,m68k_ICount
24346		 and   $10,$9,$2
24347		 srlv  $18,$10,$18
24348		 xori  $18,$18,1        	 # Set Zero Flag
24349		 xor   $2,$2,$9
24350		 lw    $25,0x88($21)
24351		 sw    $15,m68k_ICount
24352		 or    $5,$0,$2
24353		 or    $4,$0,$14
24354		 jalr  $25
24355		 sw    $23,0x4C($21)    	 # Delay slot
24356		 lw    $15,m68k_ICount
24357		 addiu $15,$15,-16
24358		 bgez  $15,3f
24359		 lhu   $24,0x00($23)    	 # Delay slot
24360		 j     MainExit
24361	3:
24362		 sll   $7,$24,2         	 # Delay slot
24363		 addu  $7,$7,$30
24364		 lw    $7,0x00($7)
24365		 jr    $7
24366		 nop                    	 # Delay slot
24367
24368OP0_085f:				#:
24369		 addiu $23,$23,2
24370
24371		 lhu   $18,0x00($23)
24372		 addiu $23,$23,2
24373		 and   $18,$18,0x07
24374		 ori   $10,$0,1
24375		 sllv  $9,$10,$18
24376		 lw    $14,0x3C($21)    	 # Get A7
24377		 addiu $25,$14,2
24378		 sw    $25,0x3C($21)
24379		 lw    $25,0x7C($21)
24380		 sw    $15,m68k_ICount
24381		 sw    $9,0x44($29)
24382		 sw    $14,0x40($29)
24383		 or    $4,$0,$14
24384		 jalr  $25
24385		 sw    $23,0x4C($21)    	 # Delay slot
24386		 lw    $14,0x40($29)
24387		 lw    $9,0x44($29)
24388		 lw    $15,m68k_ICount
24389		 and   $10,$9,$2
24390		 srlv  $18,$10,$18
24391		 xori  $18,$18,1        	 # Set Zero Flag
24392		 xor   $2,$2,$9
24393		 lw    $25,0x88($21)
24394		 sw    $15,m68k_ICount
24395		 or    $5,$0,$2
24396		 or    $4,$0,$14
24397		 jalr  $25
24398		 sw    $23,0x4C($21)    	 # Delay slot
24399		 lw    $15,m68k_ICount
24400		 addiu $15,$15,-16
24401		 bgez  $15,3f
24402		 lhu   $24,0x00($23)    	 # Delay slot
24403		 j     MainExit
24404	3:
24405		 sll   $7,$24,2         	 # Delay slot
24406		 addu  $7,$7,$30
24407		 lw    $7,0x00($7)
24408		 jr    $7
24409		 nop                    	 # Delay slot
24410
24411OP0_0860:				#:
24412		 addiu $23,$23,2
24413
24414		 andi  $8,$24,0x07
24415		 lhu   $18,0x00($23)
24416		 addiu $23,$23,2
24417		 and   $18,$18,0x07
24418		 ori   $10,$0,1
24419		 sllv  $9,$10,$18
24420		 sll   $8,$8,2
24421		 addu  $8,$8,$21
24422		 lw    $14,0x20($8)
24423		 addiu $14,$14,-1
24424		 sw    $14,0x20($8)
24425		 lw    $25,0x7C($21)
24426		 sw    $15,m68k_ICount
24427		 sw    $9,0x44($29)
24428		 sw    $14,0x40($29)
24429		 or    $4,$0,$14
24430		 jalr  $25
24431		 sw    $23,0x4C($21)    	 # Delay slot
24432		 lw    $14,0x40($29)
24433		 lw    $9,0x44($29)
24434		 lw    $15,m68k_ICount
24435		 and   $10,$9,$2
24436		 srlv  $18,$10,$18
24437		 xori  $18,$18,1        	 # Set Zero Flag
24438		 xor   $2,$2,$9
24439		 lw    $25,0x88($21)
24440		 sw    $15,m68k_ICount
24441		 or    $5,$0,$2
24442		 or    $4,$0,$14
24443		 jalr  $25
24444		 sw    $23,0x4C($21)    	 # Delay slot
24445		 lw    $15,m68k_ICount
24446		 addiu $15,$15,-18
24447		 bgez  $15,3f
24448		 lhu   $24,0x00($23)    	 # Delay slot
24449		 j     MainExit
24450	3:
24451		 sll   $7,$24,2         	 # Delay slot
24452		 addu  $7,$7,$30
24453		 lw    $7,0x00($7)
24454		 jr    $7
24455		 nop                    	 # Delay slot
24456
24457OP0_0867:				#:
24458		 addiu $23,$23,2
24459
24460		 lhu   $18,0x00($23)
24461		 addiu $23,$23,2
24462		 and   $18,$18,0x07
24463		 ori   $10,$0,1
24464		 sllv  $9,$10,$18
24465		 lw    $14,0x3C($21)    	 # Get A7
24466		 addiu $14,$14,-2
24467		 sw    $14,0x3C($21)
24468		 lw    $25,0x7C($21)
24469		 sw    $15,m68k_ICount
24470		 sw    $9,0x44($29)
24471		 sw    $14,0x40($29)
24472		 or    $4,$0,$14
24473		 jalr  $25
24474		 sw    $23,0x4C($21)    	 # Delay slot
24475		 lw    $14,0x40($29)
24476		 lw    $9,0x44($29)
24477		 lw    $15,m68k_ICount
24478		 and   $10,$9,$2
24479		 srlv  $18,$10,$18
24480		 xori  $18,$18,1        	 # Set Zero Flag
24481		 xor   $2,$2,$9
24482		 lw    $25,0x88($21)
24483		 sw    $15,m68k_ICount
24484		 or    $5,$0,$2
24485		 or    $4,$0,$14
24486		 jalr  $25
24487		 sw    $23,0x4C($21)    	 # Delay slot
24488		 lw    $15,m68k_ICount
24489		 addiu $15,$15,-18
24490		 bgez  $15,3f
24491		 lhu   $24,0x00($23)    	 # Delay slot
24492		 j     MainExit
24493	3:
24494		 sll   $7,$24,2         	 # Delay slot
24495		 addu  $7,$7,$30
24496		 lw    $7,0x00($7)
24497		 jr    $7
24498		 nop                    	 # Delay slot
24499
24500OP0_0868:				#:
24501		 addiu $23,$23,2
24502
24503		 andi  $8,$24,0x07
24504		 lhu   $18,0x00($23)
24505		 addiu $23,$23,2
24506		 and   $18,$18,0x07
24507		 ori   $10,$0,1
24508		 sllv  $9,$10,$18
24509		 lh    $7,0x00($23)
24510		 sll   $8,$8,2
24511		 addu  $8,$8,$21
24512		 lw    $14,0x20($8)
24513		 addiu $23,$23,2
24514		 addu  $14,$14,$7
24515		 lw    $25,0x7C($21)
24516		 sw    $15,m68k_ICount
24517		 sw    $9,0x44($29)
24518		 sw    $14,0x40($29)
24519		 or    $4,$0,$14
24520		 jalr  $25
24521		 sw    $23,0x4C($21)    	 # Delay slot
24522		 lw    $14,0x40($29)
24523		 lw    $9,0x44($29)
24524		 lw    $15,m68k_ICount
24525		 and   $10,$9,$2
24526		 srlv  $18,$10,$18
24527		 xori  $18,$18,1        	 # Set Zero Flag
24528		 xor   $2,$2,$9
24529		 lw    $25,0x88($21)
24530		 sw    $15,m68k_ICount
24531		 or    $5,$0,$2
24532		 or    $4,$0,$14
24533		 jalr  $25
24534		 sw    $23,0x4C($21)    	 # Delay slot
24535		 lw    $15,m68k_ICount
24536		 addiu $15,$15,-20
24537		 bgez  $15,3f
24538		 lhu   $24,0x00($23)    	 # Delay slot
24539		 j     MainExit
24540	3:
24541		 sll   $7,$24,2         	 # Delay slot
24542		 addu  $7,$7,$30
24543		 lw    $7,0x00($7)
24544		 jr    $7
24545		 nop                    	 # Delay slot
24546
24547OP0_0870:				#:
24548		 addiu $23,$23,2
24549
24550		 andi  $8,$24,0x07
24551		 lhu   $18,0x00($23)
24552		 addiu $23,$23,2
24553		 and   $18,$18,0x07
24554		 ori   $10,$0,1
24555		 sllv  $9,$10,$18
24556		 sll   $8,$8,2
24557		 addu  $8,$8,$21
24558		 lw    $14,0x20($8)
24559		 lhu   $7,0x00($23)
24560		 addiu $23,$23,2
24561		 seb   $6,$7
24562		 or    $25,$0,$7
24563		 srl   $7,$7,12
24564		 andi  $25,$25,0x0800
24565		 sll   $7,$7,2
24566		 addu  $7,$7,$21
24567		 bne   $25,$0,0f
24568		 lw    $25,0x00($7)      	 # Delay slot
24569		 seh   $25,$25
24570	0:
24571		 addu  $25,$14,$25
24572		 addu  $14,$25,$6
24573		 lw    $25,0x7C($21)
24574		 sw    $15,m68k_ICount
24575		 sw    $9,0x44($29)
24576		 sw    $14,0x40($29)
24577		 or    $4,$0,$14
24578		 jalr  $25
24579		 sw    $23,0x4C($21)    	 # Delay slot
24580		 lw    $14,0x40($29)
24581		 lw    $9,0x44($29)
24582		 lw    $15,m68k_ICount
24583		 and   $10,$9,$2
24584		 srlv  $18,$10,$18
24585		 xori  $18,$18,1        	 # Set Zero Flag
24586		 xor   $2,$2,$9
24587		 lw    $25,0x88($21)
24588		 sw    $15,m68k_ICount
24589		 or    $5,$0,$2
24590		 or    $4,$0,$14
24591		 jalr  $25
24592		 sw    $23,0x4C($21)    	 # Delay slot
24593		 lw    $15,m68k_ICount
24594		 addiu $15,$15,-22
24595		 bgez  $15,3f
24596		 lhu   $24,0x00($23)    	 # Delay slot
24597		 j     MainExit
24598	3:
24599		 sll   $7,$24,2         	 # Delay slot
24600		 addu  $7,$7,$30
24601		 lw    $7,0x00($7)
24602		 jr    $7
24603		 nop                    	 # Delay slot
24604
24605OP0_0878:				#:
24606		 addiu $23,$23,2
24607
24608		 lhu   $18,0x00($23)
24609		 addiu $23,$23,2
24610		 and   $18,$18,0x07
24611		 ori   $10,$0,1
24612		 sllv  $9,$10,$18
24613		 lh    $14,0x00($23)
24614		 addiu $23,$23,2
24615		 lw    $25,0x7C($21)
24616		 sw    $15,m68k_ICount
24617		 sw    $9,0x44($29)
24618		 sw    $14,0x40($29)
24619		 or    $4,$0,$14
24620		 jalr  $25
24621		 sw    $23,0x4C($21)    	 # Delay slot
24622		 lw    $14,0x40($29)
24623		 lw    $9,0x44($29)
24624		 lw    $15,m68k_ICount
24625		 and   $10,$9,$2
24626		 srlv  $18,$10,$18
24627		 xori  $18,$18,1        	 # Set Zero Flag
24628		 xor   $2,$2,$9
24629		 lw    $25,0x88($21)
24630		 sw    $15,m68k_ICount
24631		 or    $5,$0,$2
24632		 or    $4,$0,$14
24633		 jalr  $25
24634		 sw    $23,0x4C($21)    	 # Delay slot
24635		 lw    $15,m68k_ICount
24636		 addiu $15,$15,-20
24637		 bgez  $15,3f
24638		 lhu   $24,0x00($23)    	 # Delay slot
24639		 j     MainExit
24640	3:
24641		 sll   $7,$24,2         	 # Delay slot
24642		 addu  $7,$7,$30
24643		 lw    $7,0x00($7)
24644		 jr    $7
24645		 nop                    	 # Delay slot
24646
24647OP0_0879:				#:
24648		 addiu $23,$23,2
24649
24650		 lhu   $18,0x00($23)
24651		 addiu $23,$23,2
24652		 and   $18,$18,0x07
24653		 ori   $10,$0,1
24654		 sllv  $9,$10,$18
24655		 lhu   $14,0x00($23)
24656		 lhu   $25,0x02($23)
24657		 sll   $14,$14,16
24658		 or    $14,$14,$25
24659		 addiu $23,$23,4
24660		 lw    $25,0x7C($21)
24661		 sw    $15,m68k_ICount
24662		 sw    $9,0x44($29)
24663		 sw    $14,0x40($29)
24664		 or    $4,$0,$14
24665		 jalr  $25
24666		 sw    $23,0x4C($21)    	 # Delay slot
24667		 lw    $14,0x40($29)
24668		 lw    $9,0x44($29)
24669		 lw    $15,m68k_ICount
24670		 and   $10,$9,$2
24671		 srlv  $18,$10,$18
24672		 xori  $18,$18,1        	 # Set Zero Flag
24673		 xor   $2,$2,$9
24674		 lw    $25,0x88($21)
24675		 sw    $15,m68k_ICount
24676		 or    $5,$0,$2
24677		 or    $4,$0,$14
24678		 jalr  $25
24679		 sw    $23,0x4C($21)    	 # Delay slot
24680		 lw    $15,m68k_ICount
24681		 addiu $15,$15,-24
24682		 bgez  $15,3f
24683		 lhu   $24,0x00($23)    	 # Delay slot
24684		 j     MainExit
24685	3:
24686		 sll   $7,$24,2         	 # Delay slot
24687		 addu  $7,$7,$30
24688		 lw    $7,0x00($7)
24689		 jr    $7
24690		 nop                    	 # Delay slot
24691
24692OP0_0880:				#:
24693		 addiu $23,$23,2
24694
24695		 andi  $8,$24,0x07
24696		 lhu   $18,0x00($23)
24697		 addiu $23,$23,2
24698		 ori   $10,$0,1
24699		 sllv  $9,$10,$18
24700		 sll   $8,$8,2
24701		 addu  $8,$8,$21
24702		 lw    $2,0x00($8)
24703		 and   $10,$9,$2
24704		 srlv  $18,$10,$18
24705		 xori  $18,$18,1        	 # Set Zero Flag
24706		 nor   $9,$0,$9
24707		 and   $2,$2,$9
24708		 sw    $2,0x00($8)
24709		 addiu $15,$15,-14
24710		 bgez  $15,3f
24711		 lhu   $24,0x00($23)    	 # Delay slot
24712		 j     MainExit
24713	3:
24714		 sll   $7,$24,2         	 # Delay slot
24715		 addu  $7,$7,$30
24716		 lw    $7,0x00($7)
24717		 jr    $7
24718		 nop                    	 # Delay slot
24719
24720OP0_0890:				#:
24721		 addiu $23,$23,2
24722
24723		 andi  $8,$24,0x07
24724		 lhu   $18,0x00($23)
24725		 addiu $23,$23,2
24726		 and   $18,$18,0x07
24727		 ori   $10,$0,1
24728		 sllv  $9,$10,$18
24729		 sll   $8,$8,2
24730		 addu  $8,$8,$21
24731		 lw    $14,0x20($8)
24732		 lw    $25,0x7C($21)
24733		 sw    $15,m68k_ICount
24734		 sw    $9,0x44($29)
24735		 sw    $14,0x40($29)
24736		 or    $4,$0,$14
24737		 jalr  $25
24738		 sw    $23,0x4C($21)    	 # Delay slot
24739		 lw    $14,0x40($29)
24740		 lw    $9,0x44($29)
24741		 lw    $15,m68k_ICount
24742		 and   $10,$9,$2
24743		 srlv  $18,$10,$18
24744		 xori  $18,$18,1        	 # Set Zero Flag
24745		 nor   $9,$0,$9
24746		 and   $2,$2,$9
24747		 lw    $25,0x88($21)
24748		 sw    $15,m68k_ICount
24749		 or    $5,$0,$2
24750		 or    $4,$0,$14
24751		 jalr  $25
24752		 sw    $23,0x4C($21)    	 # Delay slot
24753		 lw    $15,m68k_ICount
24754		 addiu $15,$15,-16
24755		 bgez  $15,3f
24756		 lhu   $24,0x00($23)    	 # Delay slot
24757		 j     MainExit
24758	3:
24759		 sll   $7,$24,2         	 # Delay slot
24760		 addu  $7,$7,$30
24761		 lw    $7,0x00($7)
24762		 jr    $7
24763		 nop                    	 # Delay slot
24764
24765OP0_0898:				#:
24766		 addiu $23,$23,2
24767
24768		 andi  $8,$24,0x07
24769		 lhu   $18,0x00($23)
24770		 addiu $23,$23,2
24771		 and   $18,$18,0x07
24772		 ori   $10,$0,1
24773		 sllv  $9,$10,$18
24774		 sll   $8,$8,2
24775		 addu  $8,$8,$21
24776		 lw    $14,0x20($8)
24777		 addiu $25,$14,1
24778		 sw    $25,0x20($8)
24779		 lw    $25,0x7C($21)
24780		 sw    $15,m68k_ICount
24781		 sw    $9,0x44($29)
24782		 sw    $14,0x40($29)
24783		 or    $4,$0,$14
24784		 jalr  $25
24785		 sw    $23,0x4C($21)    	 # Delay slot
24786		 lw    $14,0x40($29)
24787		 lw    $9,0x44($29)
24788		 lw    $15,m68k_ICount
24789		 and   $10,$9,$2
24790		 srlv  $18,$10,$18
24791		 xori  $18,$18,1        	 # Set Zero Flag
24792		 nor   $9,$0,$9
24793		 and   $2,$2,$9
24794		 lw    $25,0x88($21)
24795		 sw    $15,m68k_ICount
24796		 or    $5,$0,$2
24797		 or    $4,$0,$14
24798		 jalr  $25
24799		 sw    $23,0x4C($21)    	 # Delay slot
24800		 lw    $15,m68k_ICount
24801		 addiu $15,$15,-16
24802		 bgez  $15,3f
24803		 lhu   $24,0x00($23)    	 # Delay slot
24804		 j     MainExit
24805	3:
24806		 sll   $7,$24,2         	 # Delay slot
24807		 addu  $7,$7,$30
24808		 lw    $7,0x00($7)
24809		 jr    $7
24810		 nop                    	 # Delay slot
24811
24812OP0_089f:				#:
24813		 addiu $23,$23,2
24814
24815		 lhu   $18,0x00($23)
24816		 addiu $23,$23,2
24817		 and   $18,$18,0x07
24818		 ori   $10,$0,1
24819		 sllv  $9,$10,$18
24820		 lw    $14,0x3C($21)    	 # Get A7
24821		 addiu $25,$14,2
24822		 sw    $25,0x3C($21)
24823		 lw    $25,0x7C($21)
24824		 sw    $15,m68k_ICount
24825		 sw    $9,0x44($29)
24826		 sw    $14,0x40($29)
24827		 or    $4,$0,$14
24828		 jalr  $25
24829		 sw    $23,0x4C($21)    	 # Delay slot
24830		 lw    $14,0x40($29)
24831		 lw    $9,0x44($29)
24832		 lw    $15,m68k_ICount
24833		 and   $10,$9,$2
24834		 srlv  $18,$10,$18
24835		 xori  $18,$18,1        	 # Set Zero Flag
24836		 nor   $9,$0,$9
24837		 and   $2,$2,$9
24838		 lw    $25,0x88($21)
24839		 sw    $15,m68k_ICount
24840		 or    $5,$0,$2
24841		 or    $4,$0,$14
24842		 jalr  $25
24843		 sw    $23,0x4C($21)    	 # Delay slot
24844		 lw    $15,m68k_ICount
24845		 addiu $15,$15,-16
24846		 bgez  $15,3f
24847		 lhu   $24,0x00($23)    	 # Delay slot
24848		 j     MainExit
24849	3:
24850		 sll   $7,$24,2         	 # Delay slot
24851		 addu  $7,$7,$30
24852		 lw    $7,0x00($7)
24853		 jr    $7
24854		 nop                    	 # Delay slot
24855
24856OP0_08a0:				#:
24857		 addiu $23,$23,2
24858
24859		 andi  $8,$24,0x07
24860		 lhu   $18,0x00($23)
24861		 addiu $23,$23,2
24862		 and   $18,$18,0x07
24863		 ori   $10,$0,1
24864		 sllv  $9,$10,$18
24865		 sll   $8,$8,2
24866		 addu  $8,$8,$21
24867		 lw    $14,0x20($8)
24868		 addiu $14,$14,-1
24869		 sw    $14,0x20($8)
24870		 lw    $25,0x7C($21)
24871		 sw    $15,m68k_ICount
24872		 sw    $9,0x44($29)
24873		 sw    $14,0x40($29)
24874		 or    $4,$0,$14
24875		 jalr  $25
24876		 sw    $23,0x4C($21)    	 # Delay slot
24877		 lw    $14,0x40($29)
24878		 lw    $9,0x44($29)
24879		 lw    $15,m68k_ICount
24880		 and   $10,$9,$2
24881		 srlv  $18,$10,$18
24882		 xori  $18,$18,1        	 # Set Zero Flag
24883		 nor   $9,$0,$9
24884		 and   $2,$2,$9
24885		 lw    $25,0x88($21)
24886		 sw    $15,m68k_ICount
24887		 or    $5,$0,$2
24888		 or    $4,$0,$14
24889		 jalr  $25
24890		 sw    $23,0x4C($21)    	 # Delay slot
24891		 lw    $15,m68k_ICount
24892		 addiu $15,$15,-18
24893		 bgez  $15,3f
24894		 lhu   $24,0x00($23)    	 # Delay slot
24895		 j     MainExit
24896	3:
24897		 sll   $7,$24,2         	 # Delay slot
24898		 addu  $7,$7,$30
24899		 lw    $7,0x00($7)
24900		 jr    $7
24901		 nop                    	 # Delay slot
24902
24903OP0_08a7:				#:
24904		 addiu $23,$23,2
24905
24906		 lhu   $18,0x00($23)
24907		 addiu $23,$23,2
24908		 and   $18,$18,0x07
24909		 ori   $10,$0,1
24910		 sllv  $9,$10,$18
24911		 lw    $14,0x3C($21)    	 # Get A7
24912		 addiu $14,$14,-2
24913		 sw    $14,0x3C($21)
24914		 lw    $25,0x7C($21)
24915		 sw    $15,m68k_ICount
24916		 sw    $9,0x44($29)
24917		 sw    $14,0x40($29)
24918		 or    $4,$0,$14
24919		 jalr  $25
24920		 sw    $23,0x4C($21)    	 # Delay slot
24921		 lw    $14,0x40($29)
24922		 lw    $9,0x44($29)
24923		 lw    $15,m68k_ICount
24924		 and   $10,$9,$2
24925		 srlv  $18,$10,$18
24926		 xori  $18,$18,1        	 # Set Zero Flag
24927		 nor   $9,$0,$9
24928		 and   $2,$2,$9
24929		 lw    $25,0x88($21)
24930		 sw    $15,m68k_ICount
24931		 or    $5,$0,$2
24932		 or    $4,$0,$14
24933		 jalr  $25
24934		 sw    $23,0x4C($21)    	 # Delay slot
24935		 lw    $15,m68k_ICount
24936		 addiu $15,$15,-18
24937		 bgez  $15,3f
24938		 lhu   $24,0x00($23)    	 # Delay slot
24939		 j     MainExit
24940	3:
24941		 sll   $7,$24,2         	 # Delay slot
24942		 addu  $7,$7,$30
24943		 lw    $7,0x00($7)
24944		 jr    $7
24945		 nop                    	 # Delay slot
24946
24947OP0_08a8:				#:
24948		 addiu $23,$23,2
24949
24950		 andi  $8,$24,0x07
24951		 lhu   $18,0x00($23)
24952		 addiu $23,$23,2
24953		 and   $18,$18,0x07
24954		 ori   $10,$0,1
24955		 sllv  $9,$10,$18
24956		 lh    $7,0x00($23)
24957		 sll   $8,$8,2
24958		 addu  $8,$8,$21
24959		 lw    $14,0x20($8)
24960		 addiu $23,$23,2
24961		 addu  $14,$14,$7
24962		 lw    $25,0x7C($21)
24963		 sw    $15,m68k_ICount
24964		 sw    $9,0x44($29)
24965		 sw    $14,0x40($29)
24966		 or    $4,$0,$14
24967		 jalr  $25
24968		 sw    $23,0x4C($21)    	 # Delay slot
24969		 lw    $14,0x40($29)
24970		 lw    $9,0x44($29)
24971		 lw    $15,m68k_ICount
24972		 and   $10,$9,$2
24973		 srlv  $18,$10,$18
24974		 xori  $18,$18,1        	 # Set Zero Flag
24975		 nor   $9,$0,$9
24976		 and   $2,$2,$9
24977		 lw    $25,0x88($21)
24978		 sw    $15,m68k_ICount
24979		 or    $5,$0,$2
24980		 or    $4,$0,$14
24981		 jalr  $25
24982		 sw    $23,0x4C($21)    	 # Delay slot
24983		 lw    $15,m68k_ICount
24984		 addiu $15,$15,-20
24985		 bgez  $15,3f
24986		 lhu   $24,0x00($23)    	 # Delay slot
24987		 j     MainExit
24988	3:
24989		 sll   $7,$24,2         	 # Delay slot
24990		 addu  $7,$7,$30
24991		 lw    $7,0x00($7)
24992		 jr    $7
24993		 nop                    	 # Delay slot
24994
24995OP0_08b0:				#:
24996		 addiu $23,$23,2
24997
24998		 andi  $8,$24,0x07
24999		 lhu   $18,0x00($23)
25000		 addiu $23,$23,2
25001		 and   $18,$18,0x07
25002		 ori   $10,$0,1
25003		 sllv  $9,$10,$18
25004		 sll   $8,$8,2
25005		 addu  $8,$8,$21
25006		 lw    $14,0x20($8)
25007		 lhu   $7,0x00($23)
25008		 addiu $23,$23,2
25009		 seb   $6,$7
25010		 or    $25,$0,$7
25011		 srl   $7,$7,12
25012		 andi  $25,$25,0x0800
25013		 sll   $7,$7,2
25014		 addu  $7,$7,$21
25015		 bne   $25,$0,0f
25016		 lw    $25,0x00($7)      	 # Delay slot
25017		 seh   $25,$25
25018	0:
25019		 addu  $25,$14,$25
25020		 addu  $14,$25,$6
25021		 lw    $25,0x7C($21)
25022		 sw    $15,m68k_ICount
25023		 sw    $9,0x44($29)
25024		 sw    $14,0x40($29)
25025		 or    $4,$0,$14
25026		 jalr  $25
25027		 sw    $23,0x4C($21)    	 # Delay slot
25028		 lw    $14,0x40($29)
25029		 lw    $9,0x44($29)
25030		 lw    $15,m68k_ICount
25031		 and   $10,$9,$2
25032		 srlv  $18,$10,$18
25033		 xori  $18,$18,1        	 # Set Zero Flag
25034		 nor   $9,$0,$9
25035		 and   $2,$2,$9
25036		 lw    $25,0x88($21)
25037		 sw    $15,m68k_ICount
25038		 or    $5,$0,$2
25039		 or    $4,$0,$14
25040		 jalr  $25
25041		 sw    $23,0x4C($21)    	 # Delay slot
25042		 lw    $15,m68k_ICount
25043		 addiu $15,$15,-22
25044		 bgez  $15,3f
25045		 lhu   $24,0x00($23)    	 # Delay slot
25046		 j     MainExit
25047	3:
25048		 sll   $7,$24,2         	 # Delay slot
25049		 addu  $7,$7,$30
25050		 lw    $7,0x00($7)
25051		 jr    $7
25052		 nop                    	 # Delay slot
25053
25054OP0_08b8:				#:
25055		 addiu $23,$23,2
25056
25057		 lhu   $18,0x00($23)
25058		 addiu $23,$23,2
25059		 and   $18,$18,0x07
25060		 ori   $10,$0,1
25061		 sllv  $9,$10,$18
25062		 lh    $14,0x00($23)
25063		 addiu $23,$23,2
25064		 lw    $25,0x7C($21)
25065		 sw    $15,m68k_ICount
25066		 sw    $9,0x44($29)
25067		 sw    $14,0x40($29)
25068		 or    $4,$0,$14
25069		 jalr  $25
25070		 sw    $23,0x4C($21)    	 # Delay slot
25071		 lw    $14,0x40($29)
25072		 lw    $9,0x44($29)
25073		 lw    $15,m68k_ICount
25074		 and   $10,$9,$2
25075		 srlv  $18,$10,$18
25076		 xori  $18,$18,1        	 # Set Zero Flag
25077		 nor   $9,$0,$9
25078		 and   $2,$2,$9
25079		 lw    $25,0x88($21)
25080		 sw    $15,m68k_ICount
25081		 or    $5,$0,$2
25082		 or    $4,$0,$14
25083		 jalr  $25
25084		 sw    $23,0x4C($21)    	 # Delay slot
25085		 lw    $15,m68k_ICount
25086		 addiu $15,$15,-20
25087		 bgez  $15,3f
25088		 lhu   $24,0x00($23)    	 # Delay slot
25089		 j     MainExit
25090	3:
25091		 sll   $7,$24,2         	 # Delay slot
25092		 addu  $7,$7,$30
25093		 lw    $7,0x00($7)
25094		 jr    $7
25095		 nop                    	 # Delay slot
25096
25097OP0_08b9:				#:
25098		 addiu $23,$23,2
25099
25100		 lhu   $18,0x00($23)
25101		 addiu $23,$23,2
25102		 and   $18,$18,0x07
25103		 ori   $10,$0,1
25104		 sllv  $9,$10,$18
25105		 lhu   $14,0x00($23)
25106		 lhu   $25,0x02($23)
25107		 sll   $14,$14,16
25108		 or    $14,$14,$25
25109		 addiu $23,$23,4
25110		 lw    $25,0x7C($21)
25111		 sw    $15,m68k_ICount
25112		 sw    $9,0x44($29)
25113		 sw    $14,0x40($29)
25114		 or    $4,$0,$14
25115		 jalr  $25
25116		 sw    $23,0x4C($21)    	 # Delay slot
25117		 lw    $14,0x40($29)
25118		 lw    $9,0x44($29)
25119		 lw    $15,m68k_ICount
25120		 and   $10,$9,$2
25121		 srlv  $18,$10,$18
25122		 xori  $18,$18,1        	 # Set Zero Flag
25123		 nor   $9,$0,$9
25124		 and   $2,$2,$9
25125		 lw    $25,0x88($21)
25126		 sw    $15,m68k_ICount
25127		 or    $5,$0,$2
25128		 or    $4,$0,$14
25129		 jalr  $25
25130		 sw    $23,0x4C($21)    	 # Delay slot
25131		 lw    $15,m68k_ICount
25132		 addiu $15,$15,-24
25133		 bgez  $15,3f
25134		 lhu   $24,0x00($23)    	 # Delay slot
25135		 j     MainExit
25136	3:
25137		 sll   $7,$24,2         	 # Delay slot
25138		 addu  $7,$7,$30
25139		 lw    $7,0x00($7)
25140		 jr    $7
25141		 nop                    	 # Delay slot
25142
25143OP0_08c0:				#:
25144		 addiu $23,$23,2
25145
25146		 andi  $8,$24,0x07
25147		 lhu   $18,0x00($23)
25148		 addiu $23,$23,2
25149		 ori   $10,$0,1
25150		 sllv  $9,$10,$18
25151		 sll   $8,$8,2
25152		 addu  $8,$8,$21
25153		 lw    $2,0x00($8)
25154		 and   $10,$9,$2
25155		 srlv  $18,$10,$18
25156		 xori  $18,$18,1        	 # Set Zero Flag
25157		 or    $2,$2,$9
25158		 sw    $2,0x00($8)
25159		 addiu $15,$15,-12
25160		 bgez  $15,3f
25161		 lhu   $24,0x00($23)    	 # Delay slot
25162		 j     MainExit
25163	3:
25164		 sll   $7,$24,2         	 # Delay slot
25165		 addu  $7,$7,$30
25166		 lw    $7,0x00($7)
25167		 jr    $7
25168		 nop                    	 # Delay slot
25169
25170OP0_08d0:				#:
25171		 addiu $23,$23,2
25172
25173		 andi  $8,$24,0x07
25174		 lhu   $18,0x00($23)
25175		 addiu $23,$23,2
25176		 and   $18,$18,0x07
25177		 ori   $10,$0,1
25178		 sllv  $9,$10,$18
25179		 sll   $8,$8,2
25180		 addu  $8,$8,$21
25181		 lw    $14,0x20($8)
25182		 lw    $25,0x7C($21)
25183		 sw    $15,m68k_ICount
25184		 sw    $9,0x44($29)
25185		 sw    $14,0x40($29)
25186		 or    $4,$0,$14
25187		 jalr  $25
25188		 sw    $23,0x4C($21)    	 # Delay slot
25189		 lw    $14,0x40($29)
25190		 lw    $9,0x44($29)
25191		 lw    $15,m68k_ICount
25192		 and   $10,$9,$2
25193		 srlv  $18,$10,$18
25194		 xori  $18,$18,1        	 # Set Zero Flag
25195		 or    $2,$2,$9
25196		 lw    $25,0x88($21)
25197		 sw    $15,m68k_ICount
25198		 or    $5,$0,$2
25199		 or    $4,$0,$14
25200		 jalr  $25
25201		 sw    $23,0x4C($21)    	 # Delay slot
25202		 lw    $15,m68k_ICount
25203		 addiu $15,$15,-16
25204		 bgez  $15,3f
25205		 lhu   $24,0x00($23)    	 # Delay slot
25206		 j     MainExit
25207	3:
25208		 sll   $7,$24,2         	 # Delay slot
25209		 addu  $7,$7,$30
25210		 lw    $7,0x00($7)
25211		 jr    $7
25212		 nop                    	 # Delay slot
25213
25214OP0_08d8:				#:
25215		 addiu $23,$23,2
25216
25217		 andi  $8,$24,0x07
25218		 lhu   $18,0x00($23)
25219		 addiu $23,$23,2
25220		 and   $18,$18,0x07
25221		 ori   $10,$0,1
25222		 sllv  $9,$10,$18
25223		 sll   $8,$8,2
25224		 addu  $8,$8,$21
25225		 lw    $14,0x20($8)
25226		 addiu $25,$14,1
25227		 sw    $25,0x20($8)
25228		 lw    $25,0x7C($21)
25229		 sw    $15,m68k_ICount
25230		 sw    $9,0x44($29)
25231		 sw    $14,0x40($29)
25232		 or    $4,$0,$14
25233		 jalr  $25
25234		 sw    $23,0x4C($21)    	 # Delay slot
25235		 lw    $14,0x40($29)
25236		 lw    $9,0x44($29)
25237		 lw    $15,m68k_ICount
25238		 and   $10,$9,$2
25239		 srlv  $18,$10,$18
25240		 xori  $18,$18,1        	 # Set Zero Flag
25241		 or    $2,$2,$9
25242		 lw    $25,0x88($21)
25243		 sw    $15,m68k_ICount
25244		 or    $5,$0,$2
25245		 or    $4,$0,$14
25246		 jalr  $25
25247		 sw    $23,0x4C($21)    	 # Delay slot
25248		 lw    $15,m68k_ICount
25249		 addiu $15,$15,-16
25250		 bgez  $15,3f
25251		 lhu   $24,0x00($23)    	 # Delay slot
25252		 j     MainExit
25253	3:
25254		 sll   $7,$24,2         	 # Delay slot
25255		 addu  $7,$7,$30
25256		 lw    $7,0x00($7)
25257		 jr    $7
25258		 nop                    	 # Delay slot
25259
25260OP0_08df:				#:
25261		 addiu $23,$23,2
25262
25263		 lhu   $18,0x00($23)
25264		 addiu $23,$23,2
25265		 and   $18,$18,0x07
25266		 ori   $10,$0,1
25267		 sllv  $9,$10,$18
25268		 lw    $14,0x3C($21)    	 # Get A7
25269		 addiu $25,$14,2
25270		 sw    $25,0x3C($21)
25271		 lw    $25,0x7C($21)
25272		 sw    $15,m68k_ICount
25273		 sw    $9,0x44($29)
25274		 sw    $14,0x40($29)
25275		 or    $4,$0,$14
25276		 jalr  $25
25277		 sw    $23,0x4C($21)    	 # Delay slot
25278		 lw    $14,0x40($29)
25279		 lw    $9,0x44($29)
25280		 lw    $15,m68k_ICount
25281		 and   $10,$9,$2
25282		 srlv  $18,$10,$18
25283		 xori  $18,$18,1        	 # Set Zero Flag
25284		 or    $2,$2,$9
25285		 lw    $25,0x88($21)
25286		 sw    $15,m68k_ICount
25287		 or    $5,$0,$2
25288		 or    $4,$0,$14
25289		 jalr  $25
25290		 sw    $23,0x4C($21)    	 # Delay slot
25291		 lw    $15,m68k_ICount
25292		 addiu $15,$15,-16
25293		 bgez  $15,3f
25294		 lhu   $24,0x00($23)    	 # Delay slot
25295		 j     MainExit
25296	3:
25297		 sll   $7,$24,2         	 # Delay slot
25298		 addu  $7,$7,$30
25299		 lw    $7,0x00($7)
25300		 jr    $7
25301		 nop                    	 # Delay slot
25302
25303OP0_08e0:				#:
25304		 addiu $23,$23,2
25305
25306		 andi  $8,$24,0x07
25307		 lhu   $18,0x00($23)
25308		 addiu $23,$23,2
25309		 and   $18,$18,0x07
25310		 ori   $10,$0,1
25311		 sllv  $9,$10,$18
25312		 sll   $8,$8,2
25313		 addu  $8,$8,$21
25314		 lw    $14,0x20($8)
25315		 addiu $14,$14,-1
25316		 sw    $14,0x20($8)
25317		 lw    $25,0x7C($21)
25318		 sw    $15,m68k_ICount
25319		 sw    $9,0x44($29)
25320		 sw    $14,0x40($29)
25321		 or    $4,$0,$14
25322		 jalr  $25
25323		 sw    $23,0x4C($21)    	 # Delay slot
25324		 lw    $14,0x40($29)
25325		 lw    $9,0x44($29)
25326		 lw    $15,m68k_ICount
25327		 and   $10,$9,$2
25328		 srlv  $18,$10,$18
25329		 xori  $18,$18,1        	 # Set Zero Flag
25330		 or    $2,$2,$9
25331		 lw    $25,0x88($21)
25332		 sw    $15,m68k_ICount
25333		 or    $5,$0,$2
25334		 or    $4,$0,$14
25335		 jalr  $25
25336		 sw    $23,0x4C($21)    	 # Delay slot
25337		 lw    $15,m68k_ICount
25338		 addiu $15,$15,-18
25339		 bgez  $15,3f
25340		 lhu   $24,0x00($23)    	 # Delay slot
25341		 j     MainExit
25342	3:
25343		 sll   $7,$24,2         	 # Delay slot
25344		 addu  $7,$7,$30
25345		 lw    $7,0x00($7)
25346		 jr    $7
25347		 nop                    	 # Delay slot
25348
25349OP0_08e7:				#:
25350		 addiu $23,$23,2
25351
25352		 lhu   $18,0x00($23)
25353		 addiu $23,$23,2
25354		 and   $18,$18,0x07
25355		 ori   $10,$0,1
25356		 sllv  $9,$10,$18
25357		 lw    $14,0x3C($21)    	 # Get A7
25358		 addiu $14,$14,-2
25359		 sw    $14,0x3C($21)
25360		 lw    $25,0x7C($21)
25361		 sw    $15,m68k_ICount
25362		 sw    $9,0x44($29)
25363		 sw    $14,0x40($29)
25364		 or    $4,$0,$14
25365		 jalr  $25
25366		 sw    $23,0x4C($21)    	 # Delay slot
25367		 lw    $14,0x40($29)
25368		 lw    $9,0x44($29)
25369		 lw    $15,m68k_ICount
25370		 and   $10,$9,$2
25371		 srlv  $18,$10,$18
25372		 xori  $18,$18,1        	 # Set Zero Flag
25373		 or    $2,$2,$9
25374		 lw    $25,0x88($21)
25375		 sw    $15,m68k_ICount
25376		 or    $5,$0,$2
25377		 or    $4,$0,$14
25378		 jalr  $25
25379		 sw    $23,0x4C($21)    	 # Delay slot
25380		 lw    $15,m68k_ICount
25381		 addiu $15,$15,-18
25382		 bgez  $15,3f
25383		 lhu   $24,0x00($23)    	 # Delay slot
25384		 j     MainExit
25385	3:
25386		 sll   $7,$24,2         	 # Delay slot
25387		 addu  $7,$7,$30
25388		 lw    $7,0x00($7)
25389		 jr    $7
25390		 nop                    	 # Delay slot
25391
25392OP0_08e8:				#:
25393		 addiu $23,$23,2
25394
25395		 andi  $8,$24,0x07
25396		 lhu   $18,0x00($23)
25397		 addiu $23,$23,2
25398		 and   $18,$18,0x07
25399		 ori   $10,$0,1
25400		 sllv  $9,$10,$18
25401		 lh    $7,0x00($23)
25402		 sll   $8,$8,2
25403		 addu  $8,$8,$21
25404		 lw    $14,0x20($8)
25405		 addiu $23,$23,2
25406		 addu  $14,$14,$7
25407		 lw    $25,0x7C($21)
25408		 sw    $15,m68k_ICount
25409		 sw    $9,0x44($29)
25410		 sw    $14,0x40($29)
25411		 or    $4,$0,$14
25412		 jalr  $25
25413		 sw    $23,0x4C($21)    	 # Delay slot
25414		 lw    $14,0x40($29)
25415		 lw    $9,0x44($29)
25416		 lw    $15,m68k_ICount
25417		 and   $10,$9,$2
25418		 srlv  $18,$10,$18
25419		 xori  $18,$18,1        	 # Set Zero Flag
25420		 or    $2,$2,$9
25421		 lw    $25,0x88($21)
25422		 sw    $15,m68k_ICount
25423		 or    $5,$0,$2
25424		 or    $4,$0,$14
25425		 jalr  $25
25426		 sw    $23,0x4C($21)    	 # Delay slot
25427		 lw    $15,m68k_ICount
25428		 addiu $15,$15,-20
25429		 bgez  $15,3f
25430		 lhu   $24,0x00($23)    	 # Delay slot
25431		 j     MainExit
25432	3:
25433		 sll   $7,$24,2         	 # Delay slot
25434		 addu  $7,$7,$30
25435		 lw    $7,0x00($7)
25436		 jr    $7
25437		 nop                    	 # Delay slot
25438
25439OP0_08f0:				#:
25440		 addiu $23,$23,2
25441
25442		 andi  $8,$24,0x07
25443		 lhu   $18,0x00($23)
25444		 addiu $23,$23,2
25445		 and   $18,$18,0x07
25446		 ori   $10,$0,1
25447		 sllv  $9,$10,$18
25448		 sll   $8,$8,2
25449		 addu  $8,$8,$21
25450		 lw    $14,0x20($8)
25451		 lhu   $7,0x00($23)
25452		 addiu $23,$23,2
25453		 seb   $6,$7
25454		 or    $25,$0,$7
25455		 srl   $7,$7,12
25456		 andi  $25,$25,0x0800
25457		 sll   $7,$7,2
25458		 addu  $7,$7,$21
25459		 bne   $25,$0,0f
25460		 lw    $25,0x00($7)      	 # Delay slot
25461		 seh   $25,$25
25462	0:
25463		 addu  $25,$14,$25
25464		 addu  $14,$25,$6
25465		 lw    $25,0x7C($21)
25466		 sw    $15,m68k_ICount
25467		 sw    $9,0x44($29)
25468		 sw    $14,0x40($29)
25469		 or    $4,$0,$14
25470		 jalr  $25
25471		 sw    $23,0x4C($21)    	 # Delay slot
25472		 lw    $14,0x40($29)
25473		 lw    $9,0x44($29)
25474		 lw    $15,m68k_ICount
25475		 and   $10,$9,$2
25476		 srlv  $18,$10,$18
25477		 xori  $18,$18,1        	 # Set Zero Flag
25478		 or    $2,$2,$9
25479		 lw    $25,0x88($21)
25480		 sw    $15,m68k_ICount
25481		 or    $5,$0,$2
25482		 or    $4,$0,$14
25483		 jalr  $25
25484		 sw    $23,0x4C($21)    	 # Delay slot
25485		 lw    $15,m68k_ICount
25486		 addiu $15,$15,-22
25487		 bgez  $15,3f
25488		 lhu   $24,0x00($23)    	 # Delay slot
25489		 j     MainExit
25490	3:
25491		 sll   $7,$24,2         	 # Delay slot
25492		 addu  $7,$7,$30
25493		 lw    $7,0x00($7)
25494		 jr    $7
25495		 nop                    	 # Delay slot
25496
25497OP0_08f8:				#:
25498		 addiu $23,$23,2
25499
25500		 lhu   $18,0x00($23)
25501		 addiu $23,$23,2
25502		 and   $18,$18,0x07
25503		 ori   $10,$0,1
25504		 sllv  $9,$10,$18
25505		 lh    $14,0x00($23)
25506		 addiu $23,$23,2
25507		 lw    $25,0x7C($21)
25508		 sw    $15,m68k_ICount
25509		 sw    $9,0x44($29)
25510		 sw    $14,0x40($29)
25511		 or    $4,$0,$14
25512		 jalr  $25
25513		 sw    $23,0x4C($21)    	 # Delay slot
25514		 lw    $14,0x40($29)
25515		 lw    $9,0x44($29)
25516		 lw    $15,m68k_ICount
25517		 and   $10,$9,$2
25518		 srlv  $18,$10,$18
25519		 xori  $18,$18,1        	 # Set Zero Flag
25520		 or    $2,$2,$9
25521		 lw    $25,0x88($21)
25522		 sw    $15,m68k_ICount
25523		 or    $5,$0,$2
25524		 or    $4,$0,$14
25525		 jalr  $25
25526		 sw    $23,0x4C($21)    	 # Delay slot
25527		 lw    $15,m68k_ICount
25528		 addiu $15,$15,-20
25529		 bgez  $15,3f
25530		 lhu   $24,0x00($23)    	 # Delay slot
25531		 j     MainExit
25532	3:
25533		 sll   $7,$24,2         	 # Delay slot
25534		 addu  $7,$7,$30
25535		 lw    $7,0x00($7)
25536		 jr    $7
25537		 nop                    	 # Delay slot
25538
25539OP0_08f9:				#:
25540		 addiu $23,$23,2
25541
25542		 lhu   $18,0x00($23)
25543		 addiu $23,$23,2
25544		 and   $18,$18,0x07
25545		 ori   $10,$0,1
25546		 sllv  $9,$10,$18
25547		 lhu   $14,0x00($23)
25548		 lhu   $25,0x02($23)
25549		 sll   $14,$14,16
25550		 or    $14,$14,$25
25551		 addiu $23,$23,4
25552		 lw    $25,0x7C($21)
25553		 sw    $15,m68k_ICount
25554		 sw    $9,0x44($29)
25555		 sw    $14,0x40($29)
25556		 or    $4,$0,$14
25557		 jalr  $25
25558		 sw    $23,0x4C($21)    	 # Delay slot
25559		 lw    $14,0x40($29)
25560		 lw    $9,0x44($29)
25561		 lw    $15,m68k_ICount
25562		 and   $10,$9,$2
25563		 srlv  $18,$10,$18
25564		 xori  $18,$18,1        	 # Set Zero Flag
25565		 or    $2,$2,$9
25566		 lw    $25,0x88($21)
25567		 sw    $15,m68k_ICount
25568		 or    $5,$0,$2
25569		 or    $4,$0,$14
25570		 jalr  $25
25571		 sw    $23,0x4C($21)    	 # Delay slot
25572		 lw    $15,m68k_ICount
25573		 addiu $15,$15,-24
25574		 bgez  $15,3f
25575		 lhu   $24,0x00($23)    	 # Delay slot
25576		 j     MainExit
25577	3:
25578		 sll   $7,$24,2         	 # Delay slot
25579		 addu  $7,$7,$30
25580		 lw    $7,0x00($7)
25581		 jr    $7
25582		 nop                    	 # Delay slot
25583
25584OP0_41d0:				#:
25585		 addiu $23,$23,2
25586
25587		 andi  $8,$24,0x07
25588		 srl   $24,$24,7
25589		 andi  $24,$24,0x1C
25590		 addu  $24,$24,$21
25591		 sll   $8,$8,2
25592		 addu  $8,$8,$21
25593		 lw    $14,0x20($8)
25594		 sw    $14,0x20($24)
25595		 addiu $15,$15,-12
25596		 bgez  $15,3f
25597		 lhu   $24,0x00($23)    	 # Delay slot
25598		 j     MainExit
25599	3:
25600		 sll   $7,$24,2         	 # Delay slot
25601		 addu  $7,$7,$30
25602		 lw    $7,0x00($7)
25603		 jr    $7
25604		 nop                    	 # Delay slot
25605
25606OP0_41e8:				#:
25607		 addiu $23,$23,2
25608
25609		 andi  $8,$24,0x07
25610		 srl   $24,$24,7
25611		 andi  $24,$24,0x1C
25612		 addu  $24,$24,$21
25613		 lh    $7,0x00($23)
25614		 sll   $8,$8,2
25615		 addu  $8,$8,$21
25616		 lw    $14,0x20($8)
25617		 addiu $23,$23,2
25618		 addu  $14,$14,$7
25619		 sw    $14,0x20($24)
25620		 addiu $15,$15,-20
25621		 bgez  $15,3f
25622		 lhu   $24,0x00($23)    	 # Delay slot
25623		 j     MainExit
25624	3:
25625		 sll   $7,$24,2         	 # Delay slot
25626		 addu  $7,$7,$30
25627		 lw    $7,0x00($7)
25628		 jr    $7
25629		 nop                    	 # Delay slot
25630
25631OP0_41f0:				#:
25632		 addiu $23,$23,2
25633
25634		 andi  $8,$24,0x07
25635		 srl   $24,$24,7
25636		 andi  $24,$24,0x1C
25637		 addu  $24,$24,$21
25638		 sll   $8,$8,2
25639		 addu  $8,$8,$21
25640		 lw    $14,0x20($8)
25641		 lhu   $7,0x00($23)
25642		 addiu $23,$23,2
25643		 seb   $6,$7
25644		 or    $25,$0,$7
25645		 srl   $7,$7,12
25646		 andi  $25,$25,0x0800
25647		 sll   $7,$7,2
25648		 addu  $7,$7,$21
25649		 bne   $25,$0,0f
25650		 lw    $25,0x00($7)      	 # Delay slot
25651		 seh   $25,$25
25652	0:
25653		 addu  $25,$14,$25
25654		 addu  $14,$25,$6
25655		 sw    $14,0x20($24)
25656		 addiu $15,$15,-26
25657		 bgez  $15,3f
25658		 lhu   $24,0x00($23)    	 # Delay slot
25659		 j     MainExit
25660	3:
25661		 sll   $7,$24,2         	 # Delay slot
25662		 addu  $7,$7,$30
25663		 lw    $7,0x00($7)
25664		 jr    $7
25665		 nop                    	 # Delay slot
25666
25667OP0_41f8:				#:
25668		 addiu $23,$23,2
25669
25670		 srl   $24,$24,7
25671		 andi  $24,$24,0x1C
25672		 addu  $24,$24,$21
25673		 lh    $14,0x00($23)
25674		 addiu $23,$23,2
25675		 sw    $14,0x20($24)
25676		 addiu $15,$15,-20
25677		 bgez  $15,3f
25678		 lhu   $24,0x00($23)    	 # Delay slot
25679		 j     MainExit
25680	3:
25681		 sll   $7,$24,2         	 # Delay slot
25682		 addu  $7,$7,$30
25683		 lw    $7,0x00($7)
25684		 jr    $7
25685		 nop                    	 # Delay slot
25686
25687OP0_41f9:				#:
25688		 addiu $23,$23,2
25689
25690		 srl   $24,$24,7
25691		 andi  $24,$24,0x1C
25692		 addu  $24,$24,$21
25693		 lhu   $14,0x00($23)
25694		 lhu   $25,0x02($23)
25695		 sll   $14,$14,16
25696		 or    $14,$14,$25
25697		 addiu $23,$23,4
25698		 sw    $14,0x20($24)
25699		 addiu $15,$15,-24
25700		 bgez  $15,3f
25701		 lhu   $24,0x00($23)    	 # Delay slot
25702		 j     MainExit
25703	3:
25704		 sll   $7,$24,2         	 # Delay slot
25705		 addu  $7,$7,$30
25706		 lw    $7,0x00($7)
25707		 jr    $7
25708		 nop                    	 # Delay slot
25709
25710OP0_41fa:				#:
25711		 addiu $23,$23,2
25712
25713		 srl   $24,$24,7
25714		 andi  $24,$24,0x1C
25715		 addu  $24,$24,$21
25716		 lh    $7,0x00($23)
25717		 subu  $25,$23,$22
25718		 addu  $14,$25,$7       	 # Add Offset to PC
25719		 addiu $23,$23,2
25720		 sw    $14,0x20($24)
25721		 addiu $15,$15,-20
25722		 bgez  $15,3f
25723		 lhu   $24,0x00($23)    	 # Delay slot
25724		 j     MainExit
25725	3:
25726		 sll   $7,$24,2         	 # Delay slot
25727		 addu  $7,$7,$30
25728		 lw    $7,0x00($7)
25729		 jr    $7
25730		 nop                    	 # Delay slot
25731
25732OP0_41fb:				#:
25733		 addiu $23,$23,2
25734
25735		 srl   $24,$24,7
25736		 andi  $24,$24,0x1C
25737		 addu  $24,$24,$21
25738		 subu  $14,$23,$22       	 # Get PC
25739		 lhu   $7,0x00($23)
25740		 addiu $23,$23,2
25741		 seb   $6,$7
25742		 or    $25,$0,$7
25743		 srl   $7,$7,12
25744		 andi  $25,$25,0x0800
25745		 sll   $7,$7,2
25746		 addu  $7,$7,$21
25747		 bne   $25,$0,0f
25748		 lw    $25,0x00($7)      	 # Delay slot
25749		 seh   $25,$25
25750	0:
25751		 addu  $25,$14,$25
25752		 addu  $14,$25,$6
25753		 sw    $14,0x20($24)
25754		 addiu $15,$15,-22
25755		 bgez  $15,3f
25756		 lhu   $24,0x00($23)    	 # Delay slot
25757		 j     MainExit
25758	3:
25759		 sll   $7,$24,2         	 # Delay slot
25760		 addu  $7,$7,$30
25761		 lw    $7,0x00($7)
25762		 jr    $7
25763		 nop                    	 # Delay slot
25764
25765OP0_4850:				#:
25766		 addiu $23,$23,2
25767
25768		 andi  $24,$24,0x07
25769		 sll   $24,$24,2
25770		 addu  $24,$24,$21
25771		 lw    $14,0x20($24)
25772		 lw    $4,0x3C($21)     	 # Push onto Stack
25773		 addiu $4,$4,-4
25774		 sw    $4,0x3C($21)
25775		 lw    $25,0x90($21)
25776		 sw    $15,m68k_ICount
25777		 or    $5,$0,$14
25778		 jalr  $25
25779		 sw    $23,0x4C($21)    	 # Delay slot
25780		 lw    $15,m68k_ICount
25781		 addiu $15,$15,-20
25782		 bgez  $15,3f
25783		 lhu   $24,0x00($23)    	 # Delay slot
25784		 j     MainExit
25785	3:
25786		 sll   $7,$24,2         	 # Delay slot
25787		 addu  $7,$7,$30
25788		 lw    $7,0x00($7)
25789		 jr    $7
25790		 nop                    	 # Delay slot
25791
25792OP0_4868:				#:
25793		 addiu $23,$23,2
25794
25795		 andi  $24,$24,0x07
25796		 lh    $7,0x00($23)
25797		 sll   $24,$24,2
25798		 addu  $24,$24,$21
25799		 lw    $14,0x20($24)
25800		 addiu $23,$23,2
25801		 addu  $14,$14,$7
25802		 lw    $4,0x3C($21)     	 # Push onto Stack
25803		 addiu $4,$4,-4
25804		 sw    $4,0x3C($21)
25805		 lw    $25,0x90($21)
25806		 sw    $15,m68k_ICount
25807		 or    $5,$0,$14
25808		 jalr  $25
25809		 sw    $23,0x4C($21)    	 # Delay slot
25810		 lw    $15,m68k_ICount
25811		 addiu $15,$15,-28
25812		 bgez  $15,3f
25813		 lhu   $24,0x00($23)    	 # Delay slot
25814		 j     MainExit
25815	3:
25816		 sll   $7,$24,2         	 # Delay slot
25817		 addu  $7,$7,$30
25818		 lw    $7,0x00($7)
25819		 jr    $7
25820		 nop                    	 # Delay slot
25821
25822OP0_4870:				#:
25823		 addiu $23,$23,2
25824
25825		 andi  $24,$24,0x07
25826		 sll   $24,$24,2
25827		 addu  $24,$24,$21
25828		 lw    $14,0x20($24)
25829		 lhu   $7,0x00($23)
25830		 addiu $23,$23,2
25831		 seb   $6,$7
25832		 or    $25,$0,$7
25833		 srl   $7,$7,12
25834		 andi  $25,$25,0x0800
25835		 sll   $7,$7,2
25836		 addu  $7,$7,$21
25837		 bne   $25,$0,0f
25838		 lw    $25,0x00($7)      	 # Delay slot
25839		 seh   $25,$25
25840	0:
25841		 addu  $25,$14,$25
25842		 addu  $14,$25,$6
25843		 lw    $4,0x3C($21)     	 # Push onto Stack
25844		 addiu $4,$4,-4
25845		 sw    $4,0x3C($21)
25846		 lw    $25,0x90($21)
25847		 sw    $15,m68k_ICount
25848		 or    $5,$0,$14
25849		 jalr  $25
25850		 sw    $23,0x4C($21)    	 # Delay slot
25851		 lw    $15,m68k_ICount
25852		 addiu $15,$15,-34
25853		 bgez  $15,3f
25854		 lhu   $24,0x00($23)    	 # Delay slot
25855		 j     MainExit
25856	3:
25857		 sll   $7,$24,2         	 # Delay slot
25858		 addu  $7,$7,$30
25859		 lw    $7,0x00($7)
25860		 jr    $7
25861		 nop                    	 # Delay slot
25862
25863OP0_4878:				#:
25864		 addiu $23,$23,2
25865
25866		 lh    $14,0x00($23)
25867		 addiu $23,$23,2
25868		 lw    $4,0x3C($21)     	 # Push onto Stack
25869		 addiu $4,$4,-4
25870		 sw    $4,0x3C($21)
25871		 lw    $25,0x90($21)
25872		 sw    $15,m68k_ICount
25873		 or    $5,$0,$14
25874		 jalr  $25
25875		 sw    $23,0x4C($21)    	 # Delay slot
25876		 lw    $15,m68k_ICount
25877		 addiu $15,$15,-28
25878		 bgez  $15,3f
25879		 lhu   $24,0x00($23)    	 # Delay slot
25880		 j     MainExit
25881	3:
25882		 sll   $7,$24,2         	 # Delay slot
25883		 addu  $7,$7,$30
25884		 lw    $7,0x00($7)
25885		 jr    $7
25886		 nop                    	 # Delay slot
25887
25888OP0_4879:				#:
25889		 addiu $23,$23,2
25890
25891		 lhu   $14,0x00($23)
25892		 lhu   $25,0x02($23)
25893		 sll   $14,$14,16
25894		 or    $14,$14,$25
25895		 addiu $23,$23,4
25896		 lw    $4,0x3C($21)     	 # Push onto Stack
25897		 addiu $4,$4,-4
25898		 sw    $4,0x3C($21)
25899		 lw    $25,0x90($21)
25900		 sw    $15,m68k_ICount
25901		 or    $5,$0,$14
25902		 jalr  $25
25903		 sw    $23,0x4C($21)    	 # Delay slot
25904		 lw    $15,m68k_ICount
25905		 addiu $15,$15,-32
25906		 bgez  $15,3f
25907		 lhu   $24,0x00($23)    	 # Delay slot
25908		 j     MainExit
25909	3:
25910		 sll   $7,$24,2         	 # Delay slot
25911		 addu  $7,$7,$30
25912		 lw    $7,0x00($7)
25913		 jr    $7
25914		 nop                    	 # Delay slot
25915
25916OP0_487a:				#:
25917		 addiu $23,$23,2
25918
25919		 lh    $7,0x00($23)
25920		 subu  $25,$23,$22
25921		 addu  $14,$25,$7       	 # Add Offset to PC
25922		 addiu $23,$23,2
25923		 lw    $4,0x3C($21)     	 # Push onto Stack
25924		 addiu $4,$4,-4
25925		 sw    $4,0x3C($21)
25926		 lw    $25,0x90($21)
25927		 sw    $15,m68k_ICount
25928		 or    $5,$0,$14
25929		 jalr  $25
25930		 sw    $23,0x4C($21)    	 # Delay slot
25931		 lw    $15,m68k_ICount
25932		 addiu $15,$15,-28
25933		 bgez  $15,3f
25934		 lhu   $24,0x00($23)    	 # Delay slot
25935		 j     MainExit
25936	3:
25937		 sll   $7,$24,2         	 # Delay slot
25938		 addu  $7,$7,$30
25939		 lw    $7,0x00($7)
25940		 jr    $7
25941		 nop                    	 # Delay slot
25942
25943OP0_487b:				#:
25944		 addiu $23,$23,2
25945
25946		 subu  $14,$23,$22       	 # Get PC
25947		 lhu   $7,0x00($23)
25948		 addiu $23,$23,2
25949		 seb   $6,$7
25950		 or    $25,$0,$7
25951		 srl   $7,$7,12
25952		 andi  $25,$25,0x0800
25953		 sll   $7,$7,2
25954		 addu  $7,$7,$21
25955		 bne   $25,$0,0f
25956		 lw    $25,0x00($7)      	 # Delay slot
25957		 seh   $25,$25
25958	0:
25959		 addu  $25,$14,$25
25960		 addu  $14,$25,$6
25961		 lw    $4,0x3C($21)     	 # Push onto Stack
25962		 addiu $4,$4,-4
25963		 sw    $4,0x3C($21)
25964		 lw    $25,0x90($21)
25965		 sw    $15,m68k_ICount
25966		 or    $5,$0,$14
25967		 jalr  $25
25968		 sw    $23,0x4C($21)    	 # Delay slot
25969		 lw    $15,m68k_ICount
25970		 addiu $15,$15,-30
25971		 bgez  $15,3f
25972		 lhu   $24,0x00($23)    	 # Delay slot
25973		 j     MainExit
25974	3:
25975		 sll   $7,$24,2         	 # Delay slot
25976		 addu  $7,$7,$30
25977		 lw    $7,0x00($7)
25978		 jr    $7
25979		 nop                    	 # Delay slot
25980
25981OP0_40c0:				#:
25982		 addiu $23,$23,2
25983
25984		 andi  $24,$24,0x07
25985		 lbu   $2,0x44($21)
25986		 sll   $2,$2,4
25987		 or    $2,$2,$20
25988		 sll   $2,$2,1
25989		 or    $2,$2,$19
25990		 sll   $2,$2,1
25991		 or    $2,$2,$18
25992		 sll   $2,$2,1
25993		 or    $2,$2,$17
25994		 sll   $2,$2,1
25995		 or    $2,$2,$16
25996		 sll   $24,$24,2
25997		 addu  $24,$24,$21
25998		 sh    $2,0x00($24)
25999		 addiu $15,$15,-6
26000		 bgez  $15,3f
26001		 lhu   $24,0x00($23)    	 # Delay slot
26002		 j     MainExit
26003	3:
26004		 sll   $7,$24,2         	 # Delay slot
26005		 addu  $7,$7,$30
26006		 lw    $7,0x00($7)
26007		 jr    $7
26008		 nop                    	 # Delay slot
26009
26010OP0_40d0:				#:
26011		 addiu $23,$23,2
26012
26013		 andi  $24,$24,0x07
26014		 lbu   $2,0x44($21)
26015		 sll   $2,$2,4
26016		 or    $2,$2,$20
26017		 sll   $2,$2,1
26018		 or    $2,$2,$19
26019		 sll   $2,$2,1
26020		 or    $2,$2,$18
26021		 sll   $2,$2,1
26022		 or    $2,$2,$17
26023		 sll   $2,$2,1
26024		 or    $2,$2,$16
26025		 sll   $24,$24,2
26026		 addu  $24,$24,$21
26027		 lw    $14,0x20($24)
26028		 lw    $25,0x8C($21)
26029		 sw    $15,m68k_ICount
26030		 or    $5,$0,$2
26031		 or    $4,$0,$14
26032		 jalr  $25
26033		 sw    $23,0x4C($21)    	 # Delay slot
26034		 lw    $15,m68k_ICount
26035		 addiu $15,$15,-12
26036		 bgez  $15,3f
26037		 lhu   $24,0x00($23)    	 # Delay slot
26038		 j     MainExit
26039	3:
26040		 sll   $7,$24,2         	 # Delay slot
26041		 addu  $7,$7,$30
26042		 lw    $7,0x00($7)
26043		 jr    $7
26044		 nop                    	 # Delay slot
26045
26046OP0_40d8:				#:
26047		 addiu $23,$23,2
26048
26049		 andi  $24,$24,0x07
26050		 lbu   $2,0x44($21)
26051		 sll   $2,$2,4
26052		 or    $2,$2,$20
26053		 sll   $2,$2,1
26054		 or    $2,$2,$19
26055		 sll   $2,$2,1
26056		 or    $2,$2,$18
26057		 sll   $2,$2,1
26058		 or    $2,$2,$17
26059		 sll   $2,$2,1
26060		 or    $2,$2,$16
26061		 sll   $24,$24,2
26062		 addu  $24,$24,$21
26063		 lw    $14,0x20($24)
26064		 addiu $25,$14,2
26065		 sw    $25,0x20($24)
26066		 lw    $25,0x8C($21)
26067		 sw    $15,m68k_ICount
26068		 or    $5,$0,$2
26069		 or    $4,$0,$14
26070		 jalr  $25
26071		 sw    $23,0x4C($21)    	 # Delay slot
26072		 lw    $15,m68k_ICount
26073		 addiu $15,$15,-12
26074		 bgez  $15,3f
26075		 lhu   $24,0x00($23)    	 # Delay slot
26076		 j     MainExit
26077	3:
26078		 sll   $7,$24,2         	 # Delay slot
26079		 addu  $7,$7,$30
26080		 lw    $7,0x00($7)
26081		 jr    $7
26082		 nop                    	 # Delay slot
26083
26084OP0_40e0:				#:
26085		 addiu $23,$23,2
26086
26087		 andi  $24,$24,0x07
26088		 lbu   $2,0x44($21)
26089		 sll   $2,$2,4
26090		 or    $2,$2,$20
26091		 sll   $2,$2,1
26092		 or    $2,$2,$19
26093		 sll   $2,$2,1
26094		 or    $2,$2,$18
26095		 sll   $2,$2,1
26096		 or    $2,$2,$17
26097		 sll   $2,$2,1
26098		 or    $2,$2,$16
26099		 sll   $24,$24,2
26100		 addu  $24,$24,$21
26101		 lw    $14,0x20($24)
26102		 addiu $14,$14,-2
26103		 sw    $14,0x20($24)
26104		 lw    $25,0x8C($21)
26105		 sw    $15,m68k_ICount
26106		 or    $5,$0,$2
26107		 or    $4,$0,$14
26108		 jalr  $25
26109		 sw    $23,0x4C($21)    	 # Delay slot
26110		 lw    $15,m68k_ICount
26111		 addiu $15,$15,-14
26112		 bgez  $15,3f
26113		 lhu   $24,0x00($23)    	 # Delay slot
26114		 j     MainExit
26115	3:
26116		 sll   $7,$24,2         	 # Delay slot
26117		 addu  $7,$7,$30
26118		 lw    $7,0x00($7)
26119		 jr    $7
26120		 nop                    	 # Delay slot
26121
26122OP0_40e8:				#:
26123		 addiu $23,$23,2
26124
26125		 andi  $24,$24,0x07
26126		 lbu   $2,0x44($21)
26127		 sll   $2,$2,4
26128		 or    $2,$2,$20
26129		 sll   $2,$2,1
26130		 or    $2,$2,$19
26131		 sll   $2,$2,1
26132		 or    $2,$2,$18
26133		 sll   $2,$2,1
26134		 or    $2,$2,$17
26135		 sll   $2,$2,1
26136		 or    $2,$2,$16
26137		 lh    $7,0x00($23)
26138		 sll   $24,$24,2
26139		 addu  $24,$24,$21
26140		 lw    $14,0x20($24)
26141		 addiu $23,$23,2
26142		 addu  $14,$14,$7
26143		 lw    $25,0x8C($21)
26144		 sw    $15,m68k_ICount
26145		 or    $5,$0,$2
26146		 or    $4,$0,$14
26147		 jalr  $25
26148		 sw    $23,0x4C($21)    	 # Delay slot
26149		 lw    $15,m68k_ICount
26150		 addiu $15,$15,-16
26151		 bgez  $15,3f
26152		 lhu   $24,0x00($23)    	 # Delay slot
26153		 j     MainExit
26154	3:
26155		 sll   $7,$24,2         	 # Delay slot
26156		 addu  $7,$7,$30
26157		 lw    $7,0x00($7)
26158		 jr    $7
26159		 nop                    	 # Delay slot
26160
26161OP0_40f0:				#:
26162		 addiu $23,$23,2
26163
26164		 andi  $24,$24,0x07
26165		 lbu   $2,0x44($21)
26166		 sll   $2,$2,4
26167		 or    $2,$2,$20
26168		 sll   $2,$2,1
26169		 or    $2,$2,$19
26170		 sll   $2,$2,1
26171		 or    $2,$2,$18
26172		 sll   $2,$2,1
26173		 or    $2,$2,$17
26174		 sll   $2,$2,1
26175		 or    $2,$2,$16
26176		 sll   $24,$24,2
26177		 addu  $24,$24,$21
26178		 lw    $14,0x20($24)
26179		 lhu   $7,0x00($23)
26180		 addiu $23,$23,2
26181		 seb   $6,$7
26182		 or    $25,$0,$7
26183		 srl   $7,$7,12
26184		 andi  $25,$25,0x0800
26185		 sll   $7,$7,2
26186		 addu  $7,$7,$21
26187		 bne   $25,$0,0f
26188		 lw    $25,0x00($7)      	 # Delay slot
26189		 seh   $25,$25
26190	0:
26191		 addu  $25,$14,$25
26192		 addu  $14,$25,$6
26193		 lw    $25,0x8C($21)
26194		 sw    $15,m68k_ICount
26195		 or    $5,$0,$2
26196		 or    $4,$0,$14
26197		 jalr  $25
26198		 sw    $23,0x4C($21)    	 # Delay slot
26199		 lw    $15,m68k_ICount
26200		 addiu $15,$15,-18
26201		 bgez  $15,3f
26202		 lhu   $24,0x00($23)    	 # Delay slot
26203		 j     MainExit
26204	3:
26205		 sll   $7,$24,2         	 # Delay slot
26206		 addu  $7,$7,$30
26207		 lw    $7,0x00($7)
26208		 jr    $7
26209		 nop                    	 # Delay slot
26210
26211OP0_40f8:				#:
26212		 addiu $23,$23,2
26213
26214		 lbu   $2,0x44($21)
26215		 sll   $2,$2,4
26216		 or    $2,$2,$20
26217		 sll   $2,$2,1
26218		 or    $2,$2,$19
26219		 sll   $2,$2,1
26220		 or    $2,$2,$18
26221		 sll   $2,$2,1
26222		 or    $2,$2,$17
26223		 sll   $2,$2,1
26224		 or    $2,$2,$16
26225		 lh    $14,0x00($23)
26226		 addiu $23,$23,2
26227		 lw    $25,0x8C($21)
26228		 sw    $15,m68k_ICount
26229		 or    $5,$0,$2
26230		 or    $4,$0,$14
26231		 jalr  $25
26232		 sw    $23,0x4C($21)    	 # Delay slot
26233		 lw    $15,m68k_ICount
26234		 addiu $15,$15,-16
26235		 bgez  $15,3f
26236		 lhu   $24,0x00($23)    	 # Delay slot
26237		 j     MainExit
26238	3:
26239		 sll   $7,$24,2         	 # Delay slot
26240		 addu  $7,$7,$30
26241		 lw    $7,0x00($7)
26242		 jr    $7
26243		 nop                    	 # Delay slot
26244
26245OP0_40f9:				#:
26246		 addiu $23,$23,2
26247
26248		 lbu   $2,0x44($21)
26249		 sll   $2,$2,4
26250		 or    $2,$2,$20
26251		 sll   $2,$2,1
26252		 or    $2,$2,$19
26253		 sll   $2,$2,1
26254		 or    $2,$2,$18
26255		 sll   $2,$2,1
26256		 or    $2,$2,$17
26257		 sll   $2,$2,1
26258		 or    $2,$2,$16
26259		 lhu   $14,0x00($23)
26260		 lhu   $25,0x02($23)
26261		 sll   $14,$14,16
26262		 or    $14,$14,$25
26263		 addiu $23,$23,4
26264		 lw    $25,0x8C($21)
26265		 sw    $15,m68k_ICount
26266		 or    $5,$0,$2
26267		 or    $4,$0,$14
26268		 jalr  $25
26269		 sw    $23,0x4C($21)    	 # Delay slot
26270		 lw    $15,m68k_ICount
26271		 addiu $15,$15,-20
26272		 bgez  $15,3f
26273		 lhu   $24,0x00($23)    	 # Delay slot
26274		 j     MainExit
26275	3:
26276		 sll   $7,$24,2         	 # Delay slot
26277		 addu  $7,$7,$30
26278		 lw    $7,0x00($7)
26279		 jr    $7
26280		 nop                    	 # Delay slot
26281
26282OP0_42c0:				#:
26283		 addiu $23,$23,2
26284
26285		 lw    $25,0x70($21)
26286		 bne   $25,$0,0f
26287		 andi  $24,$24,0x07     	 # Delay slot
26288		 j     ILLEGAL
26289	0:
26290		 nop                    	 # Delay slot
26291
26292		 or    $2,$0,$20
26293		 sll   $2,$2,1
26294		 or    $2,$2,$19
26295		 sll   $2,$2,1
26296		 or    $2,$2,$18
26297		 sll   $2,$2,1
26298		 or    $2,$2,$17
26299		 sll   $2,$2,1
26300		 or    $2,$2,$16
26301		 sll   $24,$24,2
26302		 addu  $24,$24,$21
26303		 sh    $2,0x00($24)
26304		 addiu $15,$15,-6
26305		 bgez  $15,3f
26306		 lhu   $24,0x00($23)    	 # Delay slot
26307		 j     MainExit
26308	3:
26309		 sll   $7,$24,2         	 # Delay slot
26310		 addu  $7,$7,$30
26311		 lw    $7,0x00($7)
26312		 jr    $7
26313		 nop                    	 # Delay slot
26314
26315OP0_42d0:				#:
26316		 addiu $23,$23,2
26317
26318		 lw    $25,0x70($21)
26319		 bne   $25,$0,0f
26320		 andi  $24,$24,0x07     	 # Delay slot
26321		 j     ILLEGAL
26322	0:
26323		 nop                    	 # Delay slot
26324
26325		 or    $2,$0,$20
26326		 sll   $2,$2,1
26327		 or    $2,$2,$19
26328		 sll   $2,$2,1
26329		 or    $2,$2,$18
26330		 sll   $2,$2,1
26331		 or    $2,$2,$17
26332		 sll   $2,$2,1
26333		 or    $2,$2,$16
26334		 sll   $24,$24,2
26335		 addu  $24,$24,$21
26336		 lw    $14,0x20($24)
26337		 lw    $25,0x8C($21)
26338		 sw    $15,m68k_ICount
26339		 or    $5,$0,$2
26340		 or    $4,$0,$14
26341		 jalr  $25
26342		 sw    $23,0x4C($21)    	 # Delay slot
26343		 lw    $15,m68k_ICount
26344		 addiu $15,$15,-12
26345		 bgez  $15,3f
26346		 lhu   $24,0x00($23)    	 # Delay slot
26347		 j     MainExit
26348	3:
26349		 sll   $7,$24,2         	 # Delay slot
26350		 addu  $7,$7,$30
26351		 lw    $7,0x00($7)
26352		 jr    $7
26353		 nop                    	 # Delay slot
26354
26355OP0_42d8:				#:
26356		 addiu $23,$23,2
26357
26358		 lw    $25,0x70($21)
26359		 bne   $25,$0,0f
26360		 andi  $24,$24,0x07     	 # Delay slot
26361		 j     ILLEGAL
26362	0:
26363		 nop                    	 # Delay slot
26364
26365		 or    $2,$0,$20
26366		 sll   $2,$2,1
26367		 or    $2,$2,$19
26368		 sll   $2,$2,1
26369		 or    $2,$2,$18
26370		 sll   $2,$2,1
26371		 or    $2,$2,$17
26372		 sll   $2,$2,1
26373		 or    $2,$2,$16
26374		 sll   $24,$24,2
26375		 addu  $24,$24,$21
26376		 lw    $14,0x20($24)
26377		 addiu $25,$14,2
26378		 sw    $25,0x20($24)
26379		 lw    $25,0x8C($21)
26380		 sw    $15,m68k_ICount
26381		 or    $5,$0,$2
26382		 or    $4,$0,$14
26383		 jalr  $25
26384		 sw    $23,0x4C($21)    	 # Delay slot
26385		 lw    $15,m68k_ICount
26386		 addiu $15,$15,-12
26387		 bgez  $15,3f
26388		 lhu   $24,0x00($23)    	 # Delay slot
26389		 j     MainExit
26390	3:
26391		 sll   $7,$24,2         	 # Delay slot
26392		 addu  $7,$7,$30
26393		 lw    $7,0x00($7)
26394		 jr    $7
26395		 nop                    	 # Delay slot
26396
26397OP0_42e0:				#:
26398		 addiu $23,$23,2
26399
26400		 lw    $25,0x70($21)
26401		 bne   $25,$0,0f
26402		 andi  $24,$24,0x07     	 # Delay slot
26403		 j     ILLEGAL
26404	0:
26405		 nop                    	 # Delay slot
26406
26407		 or    $2,$0,$20
26408		 sll   $2,$2,1
26409		 or    $2,$2,$19
26410		 sll   $2,$2,1
26411		 or    $2,$2,$18
26412		 sll   $2,$2,1
26413		 or    $2,$2,$17
26414		 sll   $2,$2,1
26415		 or    $2,$2,$16
26416		 sll   $24,$24,2
26417		 addu  $24,$24,$21
26418		 lw    $14,0x20($24)
26419		 addiu $14,$14,-2
26420		 sw    $14,0x20($24)
26421		 lw    $25,0x8C($21)
26422		 sw    $15,m68k_ICount
26423		 or    $5,$0,$2
26424		 or    $4,$0,$14
26425		 jalr  $25
26426		 sw    $23,0x4C($21)    	 # Delay slot
26427		 lw    $15,m68k_ICount
26428		 addiu $15,$15,-14
26429		 bgez  $15,3f
26430		 lhu   $24,0x00($23)    	 # Delay slot
26431		 j     MainExit
26432	3:
26433		 sll   $7,$24,2         	 # Delay slot
26434		 addu  $7,$7,$30
26435		 lw    $7,0x00($7)
26436		 jr    $7
26437		 nop                    	 # Delay slot
26438
26439OP0_42e8:				#:
26440		 addiu $23,$23,2
26441
26442		 lw    $25,0x70($21)
26443		 bne   $25,$0,0f
26444		 andi  $24,$24,0x07     	 # Delay slot
26445		 j     ILLEGAL
26446	0:
26447		 nop                    	 # Delay slot
26448
26449		 or    $2,$0,$20
26450		 sll   $2,$2,1
26451		 or    $2,$2,$19
26452		 sll   $2,$2,1
26453		 or    $2,$2,$18
26454		 sll   $2,$2,1
26455		 or    $2,$2,$17
26456		 sll   $2,$2,1
26457		 or    $2,$2,$16
26458		 lh    $7,0x00($23)
26459		 sll   $24,$24,2
26460		 addu  $24,$24,$21
26461		 lw    $14,0x20($24)
26462		 addiu $23,$23,2
26463		 addu  $14,$14,$7
26464		 lw    $25,0x8C($21)
26465		 sw    $15,m68k_ICount
26466		 or    $5,$0,$2
26467		 or    $4,$0,$14
26468		 jalr  $25
26469		 sw    $23,0x4C($21)    	 # Delay slot
26470		 lw    $15,m68k_ICount
26471		 addiu $15,$15,-16
26472		 bgez  $15,3f
26473		 lhu   $24,0x00($23)    	 # Delay slot
26474		 j     MainExit
26475	3:
26476		 sll   $7,$24,2         	 # Delay slot
26477		 addu  $7,$7,$30
26478		 lw    $7,0x00($7)
26479		 jr    $7
26480		 nop                    	 # Delay slot
26481
26482OP0_42f0:				#:
26483		 addiu $23,$23,2
26484
26485		 lw    $25,0x70($21)
26486		 bne   $25,$0,0f
26487		 andi  $24,$24,0x07     	 # Delay slot
26488		 j     ILLEGAL
26489	0:
26490		 nop                    	 # Delay slot
26491
26492		 or    $2,$0,$20
26493		 sll   $2,$2,1
26494		 or    $2,$2,$19
26495		 sll   $2,$2,1
26496		 or    $2,$2,$18
26497		 sll   $2,$2,1
26498		 or    $2,$2,$17
26499		 sll   $2,$2,1
26500		 or    $2,$2,$16
26501		 sll   $24,$24,2
26502		 addu  $24,$24,$21
26503		 lw    $14,0x20($24)
26504		 lhu   $7,0x00($23)
26505		 addiu $23,$23,2
26506		 seb   $6,$7
26507		 or    $25,$0,$7
26508		 srl   $7,$7,12
26509		 andi  $25,$25,0x0800
26510		 sll   $7,$7,2
26511		 addu  $7,$7,$21
26512		 bne   $25,$0,0f
26513		 lw    $25,0x00($7)      	 # Delay slot
26514		 seh   $25,$25
26515	0:
26516		 addu  $25,$14,$25
26517		 addu  $14,$25,$6
26518		 lw    $25,0x8C($21)
26519		 sw    $15,m68k_ICount
26520		 or    $5,$0,$2
26521		 or    $4,$0,$14
26522		 jalr  $25
26523		 sw    $23,0x4C($21)    	 # Delay slot
26524		 lw    $15,m68k_ICount
26525		 addiu $15,$15,-18
26526		 bgez  $15,3f
26527		 lhu   $24,0x00($23)    	 # Delay slot
26528		 j     MainExit
26529	3:
26530		 sll   $7,$24,2         	 # Delay slot
26531		 addu  $7,$7,$30
26532		 lw    $7,0x00($7)
26533		 jr    $7
26534		 nop                    	 # Delay slot
26535
26536OP0_42f8:				#:
26537		 addiu $23,$23,2
26538
26539		 lw    $25,0x70($21)
26540		 bne   $25,$0,0f
26541		 nop                    	 # Delay slot
26542		 j     ILLEGAL
26543	0:
26544		 nop                    	 # Delay slot
26545
26546		 or    $2,$0,$20
26547		 sll   $2,$2,1
26548		 or    $2,$2,$19
26549		 sll   $2,$2,1
26550		 or    $2,$2,$18
26551		 sll   $2,$2,1
26552		 or    $2,$2,$17
26553		 sll   $2,$2,1
26554		 or    $2,$2,$16
26555		 lh    $14,0x00($23)
26556		 addiu $23,$23,2
26557		 lw    $25,0x8C($21)
26558		 sw    $15,m68k_ICount
26559		 or    $5,$0,$2
26560		 or    $4,$0,$14
26561		 jalr  $25
26562		 sw    $23,0x4C($21)    	 # Delay slot
26563		 lw    $15,m68k_ICount
26564		 addiu $15,$15,-16
26565		 bgez  $15,3f
26566		 lhu   $24,0x00($23)    	 # Delay slot
26567		 j     MainExit
26568	3:
26569		 sll   $7,$24,2         	 # Delay slot
26570		 addu  $7,$7,$30
26571		 lw    $7,0x00($7)
26572		 jr    $7
26573		 nop                    	 # Delay slot
26574
26575OP0_42f9:				#:
26576		 addiu $23,$23,2
26577
26578		 lw    $25,0x70($21)
26579		 bne   $25,$0,0f
26580		 nop                    	 # Delay slot
26581		 j     ILLEGAL
26582	0:
26583		 nop                    	 # Delay slot
26584
26585		 or    $2,$0,$20
26586		 sll   $2,$2,1
26587		 or    $2,$2,$19
26588		 sll   $2,$2,1
26589		 or    $2,$2,$18
26590		 sll   $2,$2,1
26591		 or    $2,$2,$17
26592		 sll   $2,$2,1
26593		 or    $2,$2,$16
26594		 lhu   $14,0x00($23)
26595		 lhu   $25,0x02($23)
26596		 sll   $14,$14,16
26597		 or    $14,$14,$25
26598		 addiu $23,$23,4
26599		 lw    $25,0x8C($21)
26600		 sw    $15,m68k_ICount
26601		 or    $5,$0,$2
26602		 or    $4,$0,$14
26603		 jalr  $25
26604		 sw    $23,0x4C($21)    	 # Delay slot
26605		 lw    $15,m68k_ICount
26606		 addiu $15,$15,-20
26607		 bgez  $15,3f
26608		 lhu   $24,0x00($23)    	 # Delay slot
26609		 j     MainExit
26610	3:
26611		 sll   $7,$24,2         	 # Delay slot
26612		 addu  $7,$7,$30
26613		 lw    $7,0x00($7)
26614		 jr    $7
26615		 nop                    	 # Delay slot
26616
26617OP0_44c0:				#:
26618		 addiu $23,$23,2
26619
26620		 andi  $24,$24,0x07
26621		 sll   $24,$24,2
26622		 addu  $24,$24,$21
26623		 lhu   $2,0x00($24)
26624		 or    $20,$0,$2
26625		 or    $19,$0,$2
26626		 or    $18,$0,$2
26627		 or    $17,$0,$2
26628		 or    $16,$0,$2
26629		 andi  $20,$20,0x10
26630		 andi  $19,$19,0x08
26631		 andi  $18,$18,0x04
26632		 andi  $17,$17,0x02
26633		 andi  $16,$16,0x01
26634		 srl   $20,$20,4
26635		 srl   $19,$19,3
26636		 srl   $18,$18,2
26637		 srl   $17,$17,1
26638		 addiu $15,$15,-12
26639		 bgez  $15,3f
26640		 lhu   $24,0x00($23)    	 # Delay slot
26641		 j     MainExit
26642	3:
26643		 sll   $7,$24,2         	 # Delay slot
26644		 addu  $7,$7,$30
26645		 lw    $7,0x00($7)
26646		 jr    $7
26647		 nop                    	 # Delay slot
26648
26649OP0_44d0:				#:
26650		 addiu $23,$23,2
26651
26652		 andi  $24,$24,0x07
26653		 sll   $24,$24,2
26654		 addu  $24,$24,$21
26655		 lw    $14,0x20($24)
26656		 lw    $25,0x80($21)
26657		 sw    $15,m68k_ICount
26658		 or    $4,$0,$14
26659		 jalr  $25
26660		 sw    $23,0x4C($21)    	 # Delay slot
26661		 lw    $15,m68k_ICount
26662		 or    $20,$0,$2
26663		 or    $19,$0,$2
26664		 or    $18,$0,$2
26665		 or    $17,$0,$2
26666		 or    $16,$0,$2
26667		 andi  $20,$20,0x10
26668		 andi  $19,$19,0x08
26669		 andi  $18,$18,0x04
26670		 andi  $17,$17,0x02
26671		 andi  $16,$16,0x01
26672		 srl   $20,$20,4
26673		 srl   $19,$19,3
26674		 srl   $18,$18,2
26675		 srl   $17,$17,1
26676		 addiu $15,$15,-16
26677		 bgez  $15,3f
26678		 lhu   $24,0x00($23)    	 # Delay slot
26679		 j     MainExit
26680	3:
26681		 sll   $7,$24,2         	 # Delay slot
26682		 addu  $7,$7,$30
26683		 lw    $7,0x00($7)
26684		 jr    $7
26685		 nop                    	 # Delay slot
26686
26687OP0_44d8:				#:
26688		 addiu $23,$23,2
26689
26690		 andi  $24,$24,0x07
26691		 sll   $24,$24,2
26692		 addu  $24,$24,$21
26693		 lw    $14,0x20($24)
26694		 addiu $25,$14,2
26695		 sw    $25,0x20($24)
26696		 lw    $25,0x80($21)
26697		 sw    $15,m68k_ICount
26698		 or    $4,$0,$14
26699		 jalr  $25
26700		 sw    $23,0x4C($21)    	 # Delay slot
26701		 lw    $15,m68k_ICount
26702		 or    $20,$0,$2
26703		 or    $19,$0,$2
26704		 or    $18,$0,$2
26705		 or    $17,$0,$2
26706		 or    $16,$0,$2
26707		 andi  $20,$20,0x10
26708		 andi  $19,$19,0x08
26709		 andi  $18,$18,0x04
26710		 andi  $17,$17,0x02
26711		 andi  $16,$16,0x01
26712		 srl   $20,$20,4
26713		 srl   $19,$19,3
26714		 srl   $18,$18,2
26715		 srl   $17,$17,1
26716		 addiu $15,$15,-16
26717		 bgez  $15,3f
26718		 lhu   $24,0x00($23)    	 # Delay slot
26719		 j     MainExit
26720	3:
26721		 sll   $7,$24,2         	 # Delay slot
26722		 addu  $7,$7,$30
26723		 lw    $7,0x00($7)
26724		 jr    $7
26725		 nop                    	 # Delay slot
26726
26727OP0_44e0:				#:
26728		 addiu $23,$23,2
26729
26730		 andi  $24,$24,0x07
26731		 sll   $24,$24,2
26732		 addu  $24,$24,$21
26733		 lw    $14,0x20($24)
26734		 addiu $14,$14,-2
26735		 sw    $14,0x20($24)
26736		 lw    $25,0x80($21)
26737		 sw    $15,m68k_ICount
26738		 or    $4,$0,$14
26739		 jalr  $25
26740		 sw    $23,0x4C($21)    	 # Delay slot
26741		 lw    $15,m68k_ICount
26742		 or    $20,$0,$2
26743		 or    $19,$0,$2
26744		 or    $18,$0,$2
26745		 or    $17,$0,$2
26746		 or    $16,$0,$2
26747		 andi  $20,$20,0x10
26748		 andi  $19,$19,0x08
26749		 andi  $18,$18,0x04
26750		 andi  $17,$17,0x02
26751		 andi  $16,$16,0x01
26752		 srl   $20,$20,4
26753		 srl   $19,$19,3
26754		 srl   $18,$18,2
26755		 srl   $17,$17,1
26756		 addiu $15,$15,-18
26757		 bgez  $15,3f
26758		 lhu   $24,0x00($23)    	 # Delay slot
26759		 j     MainExit
26760	3:
26761		 sll   $7,$24,2         	 # Delay slot
26762		 addu  $7,$7,$30
26763		 lw    $7,0x00($7)
26764		 jr    $7
26765		 nop                    	 # Delay slot
26766
26767OP0_44e8:				#:
26768		 addiu $23,$23,2
26769
26770		 andi  $24,$24,0x07
26771		 lh    $7,0x00($23)
26772		 sll   $24,$24,2
26773		 addu  $24,$24,$21
26774		 lw    $14,0x20($24)
26775		 addiu $23,$23,2
26776		 addu  $14,$14,$7
26777		 lw    $25,0x80($21)
26778		 sw    $15,m68k_ICount
26779		 or    $4,$0,$14
26780		 jalr  $25
26781		 sw    $23,0x4C($21)    	 # Delay slot
26782		 lw    $15,m68k_ICount
26783		 or    $20,$0,$2
26784		 or    $19,$0,$2
26785		 or    $18,$0,$2
26786		 or    $17,$0,$2
26787		 or    $16,$0,$2
26788		 andi  $20,$20,0x10
26789		 andi  $19,$19,0x08
26790		 andi  $18,$18,0x04
26791		 andi  $17,$17,0x02
26792		 andi  $16,$16,0x01
26793		 srl   $20,$20,4
26794		 srl   $19,$19,3
26795		 srl   $18,$18,2
26796		 srl   $17,$17,1
26797		 addiu $15,$15,-20
26798		 bgez  $15,3f
26799		 lhu   $24,0x00($23)    	 # Delay slot
26800		 j     MainExit
26801	3:
26802		 sll   $7,$24,2         	 # Delay slot
26803		 addu  $7,$7,$30
26804		 lw    $7,0x00($7)
26805		 jr    $7
26806		 nop                    	 # Delay slot
26807
26808OP0_44f0:				#:
26809		 addiu $23,$23,2
26810
26811		 andi  $24,$24,0x07
26812		 sll   $24,$24,2
26813		 addu  $24,$24,$21
26814		 lw    $14,0x20($24)
26815		 lhu   $7,0x00($23)
26816		 addiu $23,$23,2
26817		 seb   $6,$7
26818		 or    $25,$0,$7
26819		 srl   $7,$7,12
26820		 andi  $25,$25,0x0800
26821		 sll   $7,$7,2
26822		 addu  $7,$7,$21
26823		 bne   $25,$0,0f
26824		 lw    $25,0x00($7)      	 # Delay slot
26825		 seh   $25,$25
26826	0:
26827		 addu  $25,$14,$25
26828		 addu  $14,$25,$6
26829		 lw    $25,0x80($21)
26830		 sw    $15,m68k_ICount
26831		 or    $4,$0,$14
26832		 jalr  $25
26833		 sw    $23,0x4C($21)    	 # Delay slot
26834		 lw    $15,m68k_ICount
26835		 or    $20,$0,$2
26836		 or    $19,$0,$2
26837		 or    $18,$0,$2
26838		 or    $17,$0,$2
26839		 or    $16,$0,$2
26840		 andi  $20,$20,0x10
26841		 andi  $19,$19,0x08
26842		 andi  $18,$18,0x04
26843		 andi  $17,$17,0x02
26844		 andi  $16,$16,0x01
26845		 srl   $20,$20,4
26846		 srl   $19,$19,3
26847		 srl   $18,$18,2
26848		 srl   $17,$17,1
26849		 addiu $15,$15,-22
26850		 bgez  $15,3f
26851		 lhu   $24,0x00($23)    	 # Delay slot
26852		 j     MainExit
26853	3:
26854		 sll   $7,$24,2         	 # Delay slot
26855		 addu  $7,$7,$30
26856		 lw    $7,0x00($7)
26857		 jr    $7
26858		 nop                    	 # Delay slot
26859
26860OP0_44f8:				#:
26861		 addiu $23,$23,2
26862
26863		 lh    $14,0x00($23)
26864		 addiu $23,$23,2
26865		 lw    $25,0x80($21)
26866		 sw    $15,m68k_ICount
26867		 or    $4,$0,$14
26868		 jalr  $25
26869		 sw    $23,0x4C($21)    	 # Delay slot
26870		 lw    $15,m68k_ICount
26871		 or    $20,$0,$2
26872		 or    $19,$0,$2
26873		 or    $18,$0,$2
26874		 or    $17,$0,$2
26875		 or    $16,$0,$2
26876		 andi  $20,$20,0x10
26877		 andi  $19,$19,0x08
26878		 andi  $18,$18,0x04
26879		 andi  $17,$17,0x02
26880		 andi  $16,$16,0x01
26881		 srl   $20,$20,4
26882		 srl   $19,$19,3
26883		 srl   $18,$18,2
26884		 srl   $17,$17,1
26885		 addiu $15,$15,-20
26886		 bgez  $15,3f
26887		 lhu   $24,0x00($23)    	 # Delay slot
26888		 j     MainExit
26889	3:
26890		 sll   $7,$24,2         	 # Delay slot
26891		 addu  $7,$7,$30
26892		 lw    $7,0x00($7)
26893		 jr    $7
26894		 nop                    	 # Delay slot
26895
26896OP0_44f9:				#:
26897		 addiu $23,$23,2
26898
26899		 lhu   $14,0x00($23)
26900		 lhu   $25,0x02($23)
26901		 sll   $14,$14,16
26902		 or    $14,$14,$25
26903		 addiu $23,$23,4
26904		 lw    $25,0x80($21)
26905		 sw    $15,m68k_ICount
26906		 or    $4,$0,$14
26907		 jalr  $25
26908		 sw    $23,0x4C($21)    	 # Delay slot
26909		 lw    $15,m68k_ICount
26910		 or    $20,$0,$2
26911		 or    $19,$0,$2
26912		 or    $18,$0,$2
26913		 or    $17,$0,$2
26914		 or    $16,$0,$2
26915		 andi  $20,$20,0x10
26916		 andi  $19,$19,0x08
26917		 andi  $18,$18,0x04
26918		 andi  $17,$17,0x02
26919		 andi  $16,$16,0x01
26920		 srl   $20,$20,4
26921		 srl   $19,$19,3
26922		 srl   $18,$18,2
26923		 srl   $17,$17,1
26924		 addiu $15,$15,-24
26925		 bgez  $15,3f
26926		 lhu   $24,0x00($23)    	 # Delay slot
26927		 j     MainExit
26928	3:
26929		 sll   $7,$24,2         	 # Delay slot
26930		 addu  $7,$7,$30
26931		 lw    $7,0x00($7)
26932		 jr    $7
26933		 nop                    	 # Delay slot
26934
26935OP0_44fa:				#:
26936		 addiu $23,$23,2
26937
26938		 lh    $7,0x00($23)
26939		 subu  $25,$23,$22
26940		 addu  $14,$25,$7       	 # Add Offset to PC
26941		 addiu $23,$23,2
26942		 lw    $25,0x9C($21)
26943		 sw    $15,m68k_ICount
26944		 or    $4,$0,$14
26945		 jalr  $25
26946		 sw    $23,0x4C($21)    	 # Delay slot
26947		 lw    $15,m68k_ICount
26948		 or    $20,$0,$2
26949		 or    $19,$0,$2
26950		 or    $18,$0,$2
26951		 or    $17,$0,$2
26952		 or    $16,$0,$2
26953		 andi  $20,$20,0x10
26954		 andi  $19,$19,0x08
26955		 andi  $18,$18,0x04
26956		 andi  $17,$17,0x02
26957		 andi  $16,$16,0x01
26958		 srl   $20,$20,4
26959		 srl   $19,$19,3
26960		 srl   $18,$18,2
26961		 srl   $17,$17,1
26962		 addiu $15,$15,-20
26963		 bgez  $15,3f
26964		 lhu   $24,0x00($23)    	 # Delay slot
26965		 j     MainExit
26966	3:
26967		 sll   $7,$24,2         	 # Delay slot
26968		 addu  $7,$7,$30
26969		 lw    $7,0x00($7)
26970		 jr    $7
26971		 nop                    	 # Delay slot
26972
26973OP0_44fb:				#:
26974		 addiu $23,$23,2
26975
26976		 subu  $14,$23,$22       	 # Get PC
26977		 lhu   $7,0x00($23)
26978		 addiu $23,$23,2
26979		 seb   $6,$7
26980		 or    $25,$0,$7
26981		 srl   $7,$7,12
26982		 andi  $25,$25,0x0800
26983		 sll   $7,$7,2
26984		 addu  $7,$7,$21
26985		 bne   $25,$0,0f
26986		 lw    $25,0x00($7)      	 # Delay slot
26987		 seh   $25,$25
26988	0:
26989		 addu  $25,$14,$25
26990		 addu  $14,$25,$6
26991		 lw    $25,0x9C($21)
26992		 sw    $15,m68k_ICount
26993		 or    $4,$0,$14
26994		 jalr  $25
26995		 sw    $23,0x4C($21)    	 # Delay slot
26996		 lw    $15,m68k_ICount
26997		 or    $20,$0,$2
26998		 or    $19,$0,$2
26999		 or    $18,$0,$2
27000		 or    $17,$0,$2
27001		 or    $16,$0,$2
27002		 andi  $20,$20,0x10
27003		 andi  $19,$19,0x08
27004		 andi  $18,$18,0x04
27005		 andi  $17,$17,0x02
27006		 andi  $16,$16,0x01
27007		 srl   $20,$20,4
27008		 srl   $19,$19,3
27009		 srl   $18,$18,2
27010		 srl   $17,$17,1
27011		 addiu $15,$15,-22
27012		 bgez  $15,3f
27013		 lhu   $24,0x00($23)    	 # Delay slot
27014		 j     MainExit
27015	3:
27016		 sll   $7,$24,2         	 # Delay slot
27017		 addu  $7,$7,$30
27018		 lw    $7,0x00($7)
27019		 jr    $7
27020		 nop                    	 # Delay slot
27021
27022OP0_44fc:				#:
27023		 addiu $23,$23,2
27024
27025		 lhu   $2,0x00($23)
27026		 addiu $23,$23,2
27027		 or    $20,$0,$2
27028		 or    $19,$0,$2
27029		 or    $18,$0,$2
27030		 or    $17,$0,$2
27031		 or    $16,$0,$2
27032		 andi  $20,$20,0x10
27033		 andi  $19,$19,0x08
27034		 andi  $18,$18,0x04
27035		 andi  $17,$17,0x02
27036		 andi  $16,$16,0x01
27037		 srl   $20,$20,4
27038		 srl   $19,$19,3
27039		 srl   $18,$18,2
27040		 srl   $17,$17,1
27041		 addiu $15,$15,-12
27042		 bgez  $15,3f
27043		 lhu   $24,0x00($23)    	 # Delay slot
27044		 j     MainExit
27045	3:
27046		 sll   $7,$24,2         	 # Delay slot
27047		 addu  $7,$7,$30
27048		 lw    $7,0x00($7)
27049		 jr    $7
27050		 nop                    	 # Delay slot
27051
27052OP0_46c0:				#:
27053		 lbu   $8,0x44($21)
27054		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27055		 beq   $8,$0,9f
27056		 addiu $23,$23,2        	 # Delay slot
27057
27058		 andi  $24,$24,0x07
27059		 sll   $24,$24,2
27060		 addu  $24,$24,$21
27061		 lhu   $2,0x00($24)
27062		 andi  $25,$2,0x2000    	 # User Mode ?
27063		 bne   $25,$0,0f
27064		 or    $18,$0,$2       	 # Delay slot
27065		 lw    $16,0x3C($21)
27066		 lw    $17,0x68($21)
27067		 sw    $16,0x40($21)
27068		 sw    $17,0x3C($21)
27069	0:
27070		 srl   $18,$18,8
27071		 sb    $18,0x44($21)    	 # T, S & I
27072		 or    $20,$0,$2
27073		 or    $19,$0,$2
27074		 or    $18,$0,$2
27075		 or    $17,$0,$2
27076		 or    $16,$0,$2
27077		 andi  $20,$20,0x10
27078		 andi  $19,$19,0x08
27079		 andi  $18,$18,0x04
27080		 andi  $17,$17,0x02
27081		 andi  $16,$16,0x01
27082		 srl   $20,$20,4
27083		 srl   $19,$19,3
27084		 srl   $18,$18,2
27085		 srl   $17,$17,1
27086		 addiu $15,$15,-12
27087		 bgez  $15,3f
27088		 lbu   $7,0x50($21)     	 # Delay slot
27089		 j     MainExit
27090	3:
27091 # Check for Interrupt waiting
27092
27093		 andi  $7,$7,0x07       	 # Delay slot
27094		 beq   $7,$0,3f
27095		 nop                    	 # Delay slot
27096		 j     interrupt
27097	3:
27098		 lhu   $24,0x00($23)    	 # Delay slot
27099		 sll   $7,$24,2
27100		 addu  $7,$7,$30
27101		 lw    $7,0x00($7)
27102		 jr    $7
27103		 nop                    	 # Delay slot
27104
27105	9:
27106		 addiu $23,$23,-2
27107		 jal   Exception
27108		 ori   $2,$0,8
27109
27110		 addiu $15,$15,-12
27111		 bgez  $15,3f
27112		 lbu   $7,0x50($21)     	 # Delay slot
27113		 j     MainExit
27114	3:
27115 # Check for Interrupt waiting
27116
27117		 andi  $7,$7,0x07       	 # Delay slot
27118		 beq   $7,$0,3f
27119		 nop                    	 # Delay slot
27120		 j     interrupt
27121	3:
27122		 lhu   $24,0x00($23)    	 # Delay slot
27123		 sll   $7,$24,2
27124		 addu  $7,$7,$30
27125		 lw    $7,0x00($7)
27126		 jr    $7
27127		 nop                    	 # Delay slot
27128
27129OP0_46d0:				#:
27130		 lbu   $8,0x44($21)
27131		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27132		 beq   $8,$0,9f
27133		 addiu $23,$23,2        	 # Delay slot
27134
27135		 andi  $24,$24,0x07
27136		 sll   $24,$24,2
27137		 addu  $24,$24,$21
27138		 lw    $14,0x20($24)
27139		 lw    $25,0x80($21)
27140		 sw    $15,m68k_ICount
27141		 or    $4,$0,$14
27142		 jalr  $25
27143		 sw    $23,0x4C($21)    	 # Delay slot
27144		 lw    $15,m68k_ICount
27145		 andi  $25,$2,0x2000    	 # User Mode ?
27146		 bne   $25,$0,0f
27147		 or    $18,$0,$2       	 # Delay slot
27148		 lw    $16,0x3C($21)
27149		 lw    $17,0x68($21)
27150		 sw    $16,0x40($21)
27151		 sw    $17,0x3C($21)
27152	0:
27153		 srl   $18,$18,8
27154		 sb    $18,0x44($21)    	 # T, S & I
27155		 or    $20,$0,$2
27156		 or    $19,$0,$2
27157		 or    $18,$0,$2
27158		 or    $17,$0,$2
27159		 or    $16,$0,$2
27160		 andi  $20,$20,0x10
27161		 andi  $19,$19,0x08
27162		 andi  $18,$18,0x04
27163		 andi  $17,$17,0x02
27164		 andi  $16,$16,0x01
27165		 srl   $20,$20,4
27166		 srl   $19,$19,3
27167		 srl   $18,$18,2
27168		 srl   $17,$17,1
27169		 addiu $15,$15,-16
27170		 bgez  $15,3f
27171		 lbu   $7,0x50($21)     	 # Delay slot
27172		 j     MainExit
27173	3:
27174 # Check for Interrupt waiting
27175
27176		 andi  $7,$7,0x07       	 # Delay slot
27177		 beq   $7,$0,3f
27178		 nop                    	 # Delay slot
27179		 j     interrupt
27180	3:
27181		 lhu   $24,0x00($23)    	 # Delay slot
27182		 sll   $7,$24,2
27183		 addu  $7,$7,$30
27184		 lw    $7,0x00($7)
27185		 jr    $7
27186		 nop                    	 # Delay slot
27187
27188	9:
27189		 addiu $23,$23,-2
27190		 jal   Exception
27191		 ori   $2,$0,8
27192
27193		 addiu $15,$15,-16
27194		 bgez  $15,3f
27195		 lbu   $7,0x50($21)     	 # Delay slot
27196		 j     MainExit
27197	3:
27198 # Check for Interrupt waiting
27199
27200		 andi  $7,$7,0x07       	 # Delay slot
27201		 beq   $7,$0,3f
27202		 nop                    	 # Delay slot
27203		 j     interrupt
27204	3:
27205		 lhu   $24,0x00($23)    	 # Delay slot
27206		 sll   $7,$24,2
27207		 addu  $7,$7,$30
27208		 lw    $7,0x00($7)
27209		 jr    $7
27210		 nop                    	 # Delay slot
27211
27212OP0_46d8:				#:
27213		 lbu   $8,0x44($21)
27214		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27215		 beq   $8,$0,9f
27216		 addiu $23,$23,2        	 # Delay slot
27217
27218		 andi  $24,$24,0x07
27219		 sll   $24,$24,2
27220		 addu  $24,$24,$21
27221		 lw    $14,0x20($24)
27222		 addiu $25,$14,2
27223		 sw    $25,0x20($24)
27224		 lw    $25,0x80($21)
27225		 sw    $15,m68k_ICount
27226		 or    $4,$0,$14
27227		 jalr  $25
27228		 sw    $23,0x4C($21)    	 # Delay slot
27229		 lw    $15,m68k_ICount
27230		 andi  $25,$2,0x2000    	 # User Mode ?
27231		 bne   $25,$0,0f
27232		 or    $18,$0,$2       	 # Delay slot
27233		 lw    $16,0x3C($21)
27234		 lw    $17,0x68($21)
27235		 sw    $16,0x40($21)
27236		 sw    $17,0x3C($21)
27237	0:
27238		 srl   $18,$18,8
27239		 sb    $18,0x44($21)    	 # T, S & I
27240		 or    $20,$0,$2
27241		 or    $19,$0,$2
27242		 or    $18,$0,$2
27243		 or    $17,$0,$2
27244		 or    $16,$0,$2
27245		 andi  $20,$20,0x10
27246		 andi  $19,$19,0x08
27247		 andi  $18,$18,0x04
27248		 andi  $17,$17,0x02
27249		 andi  $16,$16,0x01
27250		 srl   $20,$20,4
27251		 srl   $19,$19,3
27252		 srl   $18,$18,2
27253		 srl   $17,$17,1
27254		 addiu $15,$15,-16
27255		 bgez  $15,3f
27256		 lbu   $7,0x50($21)     	 # Delay slot
27257		 j     MainExit
27258	3:
27259 # Check for Interrupt waiting
27260
27261		 andi  $7,$7,0x07       	 # Delay slot
27262		 beq   $7,$0,3f
27263		 nop                    	 # Delay slot
27264		 j     interrupt
27265	3:
27266		 lhu   $24,0x00($23)    	 # Delay slot
27267		 sll   $7,$24,2
27268		 addu  $7,$7,$30
27269		 lw    $7,0x00($7)
27270		 jr    $7
27271		 nop                    	 # Delay slot
27272
27273	9:
27274		 addiu $23,$23,-2
27275		 jal   Exception
27276		 ori   $2,$0,8
27277
27278		 addiu $15,$15,-16
27279		 bgez  $15,3f
27280		 lbu   $7,0x50($21)     	 # Delay slot
27281		 j     MainExit
27282	3:
27283 # Check for Interrupt waiting
27284
27285		 andi  $7,$7,0x07       	 # Delay slot
27286		 beq   $7,$0,3f
27287		 nop                    	 # Delay slot
27288		 j     interrupt
27289	3:
27290		 lhu   $24,0x00($23)    	 # Delay slot
27291		 sll   $7,$24,2
27292		 addu  $7,$7,$30
27293		 lw    $7,0x00($7)
27294		 jr    $7
27295		 nop                    	 # Delay slot
27296
27297OP0_46e0:				#:
27298		 lbu   $8,0x44($21)
27299		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27300		 beq   $8,$0,9f
27301		 addiu $23,$23,2        	 # Delay slot
27302
27303		 andi  $24,$24,0x07
27304		 sll   $24,$24,2
27305		 addu  $24,$24,$21
27306		 lw    $14,0x20($24)
27307		 addiu $14,$14,-2
27308		 sw    $14,0x20($24)
27309		 lw    $25,0x80($21)
27310		 sw    $15,m68k_ICount
27311		 or    $4,$0,$14
27312		 jalr  $25
27313		 sw    $23,0x4C($21)    	 # Delay slot
27314		 lw    $15,m68k_ICount
27315		 andi  $25,$2,0x2000    	 # User Mode ?
27316		 bne   $25,$0,0f
27317		 or    $18,$0,$2       	 # Delay slot
27318		 lw    $16,0x3C($21)
27319		 lw    $17,0x68($21)
27320		 sw    $16,0x40($21)
27321		 sw    $17,0x3C($21)
27322	0:
27323		 srl   $18,$18,8
27324		 sb    $18,0x44($21)    	 # T, S & I
27325		 or    $20,$0,$2
27326		 or    $19,$0,$2
27327		 or    $18,$0,$2
27328		 or    $17,$0,$2
27329		 or    $16,$0,$2
27330		 andi  $20,$20,0x10
27331		 andi  $19,$19,0x08
27332		 andi  $18,$18,0x04
27333		 andi  $17,$17,0x02
27334		 andi  $16,$16,0x01
27335		 srl   $20,$20,4
27336		 srl   $19,$19,3
27337		 srl   $18,$18,2
27338		 srl   $17,$17,1
27339		 addiu $15,$15,-18
27340		 bgez  $15,3f
27341		 lbu   $7,0x50($21)     	 # Delay slot
27342		 j     MainExit
27343	3:
27344 # Check for Interrupt waiting
27345
27346		 andi  $7,$7,0x07       	 # Delay slot
27347		 beq   $7,$0,3f
27348		 nop                    	 # Delay slot
27349		 j     interrupt
27350	3:
27351		 lhu   $24,0x00($23)    	 # Delay slot
27352		 sll   $7,$24,2
27353		 addu  $7,$7,$30
27354		 lw    $7,0x00($7)
27355		 jr    $7
27356		 nop                    	 # Delay slot
27357
27358	9:
27359		 addiu $23,$23,-2
27360		 jal   Exception
27361		 ori   $2,$0,8
27362
27363		 addiu $15,$15,-18
27364		 bgez  $15,3f
27365		 lbu   $7,0x50($21)     	 # Delay slot
27366		 j     MainExit
27367	3:
27368 # Check for Interrupt waiting
27369
27370		 andi  $7,$7,0x07       	 # Delay slot
27371		 beq   $7,$0,3f
27372		 nop                    	 # Delay slot
27373		 j     interrupt
27374	3:
27375		 lhu   $24,0x00($23)    	 # Delay slot
27376		 sll   $7,$24,2
27377		 addu  $7,$7,$30
27378		 lw    $7,0x00($7)
27379		 jr    $7
27380		 nop                    	 # Delay slot
27381
27382OP0_46e8:				#:
27383		 lbu   $8,0x44($21)
27384		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27385		 beq   $8,$0,9f
27386		 addiu $23,$23,2        	 # Delay slot
27387
27388		 andi  $24,$24,0x07
27389		 lh    $7,0x00($23)
27390		 sll   $24,$24,2
27391		 addu  $24,$24,$21
27392		 lw    $14,0x20($24)
27393		 addiu $23,$23,2
27394		 addu  $14,$14,$7
27395		 lw    $25,0x80($21)
27396		 sw    $15,m68k_ICount
27397		 or    $4,$0,$14
27398		 jalr  $25
27399		 sw    $23,0x4C($21)    	 # Delay slot
27400		 lw    $15,m68k_ICount
27401		 andi  $25,$2,0x2000    	 # User Mode ?
27402		 bne   $25,$0,0f
27403		 or    $18,$0,$2       	 # Delay slot
27404		 lw    $16,0x3C($21)
27405		 lw    $17,0x68($21)
27406		 sw    $16,0x40($21)
27407		 sw    $17,0x3C($21)
27408	0:
27409		 srl   $18,$18,8
27410		 sb    $18,0x44($21)    	 # T, S & I
27411		 or    $20,$0,$2
27412		 or    $19,$0,$2
27413		 or    $18,$0,$2
27414		 or    $17,$0,$2
27415		 or    $16,$0,$2
27416		 andi  $20,$20,0x10
27417		 andi  $19,$19,0x08
27418		 andi  $18,$18,0x04
27419		 andi  $17,$17,0x02
27420		 andi  $16,$16,0x01
27421		 srl   $20,$20,4
27422		 srl   $19,$19,3
27423		 srl   $18,$18,2
27424		 srl   $17,$17,1
27425		 addiu $15,$15,-20
27426		 bgez  $15,3f
27427		 lbu   $7,0x50($21)     	 # Delay slot
27428		 j     MainExit
27429	3:
27430 # Check for Interrupt waiting
27431
27432		 andi  $7,$7,0x07       	 # Delay slot
27433		 beq   $7,$0,3f
27434		 nop                    	 # Delay slot
27435		 j     interrupt
27436	3:
27437		 lhu   $24,0x00($23)    	 # Delay slot
27438		 sll   $7,$24,2
27439		 addu  $7,$7,$30
27440		 lw    $7,0x00($7)
27441		 jr    $7
27442		 nop                    	 # Delay slot
27443
27444	9:
27445		 addiu $23,$23,-2
27446		 jal   Exception
27447		 ori   $2,$0,8
27448
27449		 addiu $15,$15,-20
27450		 bgez  $15,3f
27451		 lbu   $7,0x50($21)     	 # Delay slot
27452		 j     MainExit
27453	3:
27454 # Check for Interrupt waiting
27455
27456		 andi  $7,$7,0x07       	 # Delay slot
27457		 beq   $7,$0,3f
27458		 nop                    	 # Delay slot
27459		 j     interrupt
27460	3:
27461		 lhu   $24,0x00($23)    	 # Delay slot
27462		 sll   $7,$24,2
27463		 addu  $7,$7,$30
27464		 lw    $7,0x00($7)
27465		 jr    $7
27466		 nop                    	 # Delay slot
27467
27468OP0_46f0:				#:
27469		 lbu   $8,0x44($21)
27470		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27471		 beq   $8,$0,9f
27472		 addiu $23,$23,2        	 # Delay slot
27473
27474		 andi  $24,$24,0x07
27475		 sll   $24,$24,2
27476		 addu  $24,$24,$21
27477		 lw    $14,0x20($24)
27478		 lhu   $7,0x00($23)
27479		 addiu $23,$23,2
27480		 seb   $6,$7
27481		 or    $25,$0,$7
27482		 srl   $7,$7,12
27483		 andi  $25,$25,0x0800
27484		 sll   $7,$7,2
27485		 addu  $7,$7,$21
27486		 bne   $25,$0,0f
27487		 lw    $25,0x00($7)      	 # Delay slot
27488		 seh   $25,$25
27489	0:
27490		 addu  $25,$14,$25
27491		 addu  $14,$25,$6
27492		 lw    $25,0x80($21)
27493		 sw    $15,m68k_ICount
27494		 or    $4,$0,$14
27495		 jalr  $25
27496		 sw    $23,0x4C($21)    	 # Delay slot
27497		 lw    $15,m68k_ICount
27498		 andi  $25,$2,0x2000    	 # User Mode ?
27499		 bne   $25,$0,0f
27500		 or    $18,$0,$2       	 # Delay slot
27501		 lw    $16,0x3C($21)
27502		 lw    $17,0x68($21)
27503		 sw    $16,0x40($21)
27504		 sw    $17,0x3C($21)
27505	0:
27506		 srl   $18,$18,8
27507		 sb    $18,0x44($21)    	 # T, S & I
27508		 or    $20,$0,$2
27509		 or    $19,$0,$2
27510		 or    $18,$0,$2
27511		 or    $17,$0,$2
27512		 or    $16,$0,$2
27513		 andi  $20,$20,0x10
27514		 andi  $19,$19,0x08
27515		 andi  $18,$18,0x04
27516		 andi  $17,$17,0x02
27517		 andi  $16,$16,0x01
27518		 srl   $20,$20,4
27519		 srl   $19,$19,3
27520		 srl   $18,$18,2
27521		 srl   $17,$17,1
27522		 addiu $15,$15,-22
27523		 bgez  $15,3f
27524		 lbu   $7,0x50($21)     	 # Delay slot
27525		 j     MainExit
27526	3:
27527 # Check for Interrupt waiting
27528
27529		 andi  $7,$7,0x07       	 # Delay slot
27530		 beq   $7,$0,3f
27531		 nop                    	 # Delay slot
27532		 j     interrupt
27533	3:
27534		 lhu   $24,0x00($23)    	 # Delay slot
27535		 sll   $7,$24,2
27536		 addu  $7,$7,$30
27537		 lw    $7,0x00($7)
27538		 jr    $7
27539		 nop                    	 # Delay slot
27540
27541	9:
27542		 addiu $23,$23,-2
27543		 jal   Exception
27544		 ori   $2,$0,8
27545
27546		 addiu $15,$15,-22
27547		 bgez  $15,3f
27548		 lbu   $7,0x50($21)     	 # Delay slot
27549		 j     MainExit
27550	3:
27551 # Check for Interrupt waiting
27552
27553		 andi  $7,$7,0x07       	 # Delay slot
27554		 beq   $7,$0,3f
27555		 nop                    	 # Delay slot
27556		 j     interrupt
27557	3:
27558		 lhu   $24,0x00($23)    	 # Delay slot
27559		 sll   $7,$24,2
27560		 addu  $7,$7,$30
27561		 lw    $7,0x00($7)
27562		 jr    $7
27563		 nop                    	 # Delay slot
27564
27565OP0_46f8:				#:
27566		 lbu   $8,0x44($21)
27567		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27568		 beq   $8,$0,9f
27569		 addiu $23,$23,2        	 # Delay slot
27570
27571		 lh    $14,0x00($23)
27572		 addiu $23,$23,2
27573		 lw    $25,0x80($21)
27574		 sw    $15,m68k_ICount
27575		 or    $4,$0,$14
27576		 jalr  $25
27577		 sw    $23,0x4C($21)    	 # Delay slot
27578		 lw    $15,m68k_ICount
27579		 andi  $25,$2,0x2000    	 # User Mode ?
27580		 bne   $25,$0,0f
27581		 or    $18,$0,$2       	 # Delay slot
27582		 lw    $16,0x3C($21)
27583		 lw    $17,0x68($21)
27584		 sw    $16,0x40($21)
27585		 sw    $17,0x3C($21)
27586	0:
27587		 srl   $18,$18,8
27588		 sb    $18,0x44($21)    	 # T, S & I
27589		 or    $20,$0,$2
27590		 or    $19,$0,$2
27591		 or    $18,$0,$2
27592		 or    $17,$0,$2
27593		 or    $16,$0,$2
27594		 andi  $20,$20,0x10
27595		 andi  $19,$19,0x08
27596		 andi  $18,$18,0x04
27597		 andi  $17,$17,0x02
27598		 andi  $16,$16,0x01
27599		 srl   $20,$20,4
27600		 srl   $19,$19,3
27601		 srl   $18,$18,2
27602		 srl   $17,$17,1
27603		 addiu $15,$15,-20
27604		 bgez  $15,3f
27605		 lbu   $7,0x50($21)     	 # Delay slot
27606		 j     MainExit
27607	3:
27608 # Check for Interrupt waiting
27609
27610		 andi  $7,$7,0x07       	 # Delay slot
27611		 beq   $7,$0,3f
27612		 nop                    	 # Delay slot
27613		 j     interrupt
27614	3:
27615		 lhu   $24,0x00($23)    	 # Delay slot
27616		 sll   $7,$24,2
27617		 addu  $7,$7,$30
27618		 lw    $7,0x00($7)
27619		 jr    $7
27620		 nop                    	 # Delay slot
27621
27622	9:
27623		 addiu $23,$23,-2
27624		 jal   Exception
27625		 ori   $2,$0,8
27626
27627		 addiu $15,$15,-20
27628		 bgez  $15,3f
27629		 lbu   $7,0x50($21)     	 # Delay slot
27630		 j     MainExit
27631	3:
27632 # Check for Interrupt waiting
27633
27634		 andi  $7,$7,0x07       	 # Delay slot
27635		 beq   $7,$0,3f
27636		 nop                    	 # Delay slot
27637		 j     interrupt
27638	3:
27639		 lhu   $24,0x00($23)    	 # Delay slot
27640		 sll   $7,$24,2
27641		 addu  $7,$7,$30
27642		 lw    $7,0x00($7)
27643		 jr    $7
27644		 nop                    	 # Delay slot
27645
27646OP0_46f9:				#:
27647		 lbu   $8,0x44($21)
27648		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27649		 beq   $8,$0,9f
27650		 addiu $23,$23,2        	 # Delay slot
27651
27652		 lhu   $14,0x00($23)
27653		 lhu   $25,0x02($23)
27654		 sll   $14,$14,16
27655		 or    $14,$14,$25
27656		 addiu $23,$23,4
27657		 lw    $25,0x80($21)
27658		 sw    $15,m68k_ICount
27659		 or    $4,$0,$14
27660		 jalr  $25
27661		 sw    $23,0x4C($21)    	 # Delay slot
27662		 lw    $15,m68k_ICount
27663		 andi  $25,$2,0x2000    	 # User Mode ?
27664		 bne   $25,$0,0f
27665		 or    $18,$0,$2       	 # Delay slot
27666		 lw    $16,0x3C($21)
27667		 lw    $17,0x68($21)
27668		 sw    $16,0x40($21)
27669		 sw    $17,0x3C($21)
27670	0:
27671		 srl   $18,$18,8
27672		 sb    $18,0x44($21)    	 # T, S & I
27673		 or    $20,$0,$2
27674		 or    $19,$0,$2
27675		 or    $18,$0,$2
27676		 or    $17,$0,$2
27677		 or    $16,$0,$2
27678		 andi  $20,$20,0x10
27679		 andi  $19,$19,0x08
27680		 andi  $18,$18,0x04
27681		 andi  $17,$17,0x02
27682		 andi  $16,$16,0x01
27683		 srl   $20,$20,4
27684		 srl   $19,$19,3
27685		 srl   $18,$18,2
27686		 srl   $17,$17,1
27687		 addiu $15,$15,-24
27688		 bgez  $15,3f
27689		 lbu   $7,0x50($21)     	 # Delay slot
27690		 j     MainExit
27691	3:
27692 # Check for Interrupt waiting
27693
27694		 andi  $7,$7,0x07       	 # Delay slot
27695		 beq   $7,$0,3f
27696		 nop                    	 # Delay slot
27697		 j     interrupt
27698	3:
27699		 lhu   $24,0x00($23)    	 # Delay slot
27700		 sll   $7,$24,2
27701		 addu  $7,$7,$30
27702		 lw    $7,0x00($7)
27703		 jr    $7
27704		 nop                    	 # Delay slot
27705
27706	9:
27707		 addiu $23,$23,-2
27708		 jal   Exception
27709		 ori   $2,$0,8
27710
27711		 addiu $15,$15,-24
27712		 bgez  $15,3f
27713		 lbu   $7,0x50($21)     	 # Delay slot
27714		 j     MainExit
27715	3:
27716 # Check for Interrupt waiting
27717
27718		 andi  $7,$7,0x07       	 # Delay slot
27719		 beq   $7,$0,3f
27720		 nop                    	 # Delay slot
27721		 j     interrupt
27722	3:
27723		 lhu   $24,0x00($23)    	 # Delay slot
27724		 sll   $7,$24,2
27725		 addu  $7,$7,$30
27726		 lw    $7,0x00($7)
27727		 jr    $7
27728		 nop                    	 # Delay slot
27729
27730OP0_46fa:				#:
27731		 lbu   $8,0x44($21)
27732		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27733		 beq   $8,$0,9f
27734		 addiu $23,$23,2        	 # Delay slot
27735
27736		 lh    $7,0x00($23)
27737		 subu  $25,$23,$22
27738		 addu  $14,$25,$7       	 # Add Offset to PC
27739		 addiu $23,$23,2
27740		 lw    $25,0x9C($21)
27741		 sw    $15,m68k_ICount
27742		 or    $4,$0,$14
27743		 jalr  $25
27744		 sw    $23,0x4C($21)    	 # Delay slot
27745		 lw    $15,m68k_ICount
27746		 andi  $25,$2,0x2000    	 # User Mode ?
27747		 bne   $25,$0,0f
27748		 or    $18,$0,$2       	 # Delay slot
27749		 lw    $16,0x3C($21)
27750		 lw    $17,0x68($21)
27751		 sw    $16,0x40($21)
27752		 sw    $17,0x3C($21)
27753	0:
27754		 srl   $18,$18,8
27755		 sb    $18,0x44($21)    	 # T, S & I
27756		 or    $20,$0,$2
27757		 or    $19,$0,$2
27758		 or    $18,$0,$2
27759		 or    $17,$0,$2
27760		 or    $16,$0,$2
27761		 andi  $20,$20,0x10
27762		 andi  $19,$19,0x08
27763		 andi  $18,$18,0x04
27764		 andi  $17,$17,0x02
27765		 andi  $16,$16,0x01
27766		 srl   $20,$20,4
27767		 srl   $19,$19,3
27768		 srl   $18,$18,2
27769		 srl   $17,$17,1
27770		 addiu $15,$15,-20
27771		 bgez  $15,3f
27772		 lbu   $7,0x50($21)     	 # Delay slot
27773		 j     MainExit
27774	3:
27775 # Check for Interrupt waiting
27776
27777		 andi  $7,$7,0x07       	 # Delay slot
27778		 beq   $7,$0,3f
27779		 nop                    	 # Delay slot
27780		 j     interrupt
27781	3:
27782		 lhu   $24,0x00($23)    	 # Delay slot
27783		 sll   $7,$24,2
27784		 addu  $7,$7,$30
27785		 lw    $7,0x00($7)
27786		 jr    $7
27787		 nop                    	 # Delay slot
27788
27789	9:
27790		 addiu $23,$23,-2
27791		 jal   Exception
27792		 ori   $2,$0,8
27793
27794		 addiu $15,$15,-20
27795		 bgez  $15,3f
27796		 lbu   $7,0x50($21)     	 # Delay slot
27797		 j     MainExit
27798	3:
27799 # Check for Interrupt waiting
27800
27801		 andi  $7,$7,0x07       	 # Delay slot
27802		 beq   $7,$0,3f
27803		 nop                    	 # Delay slot
27804		 j     interrupt
27805	3:
27806		 lhu   $24,0x00($23)    	 # Delay slot
27807		 sll   $7,$24,2
27808		 addu  $7,$7,$30
27809		 lw    $7,0x00($7)
27810		 jr    $7
27811		 nop                    	 # Delay slot
27812
27813OP0_46fb:				#:
27814		 lbu   $8,0x44($21)
27815		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27816		 beq   $8,$0,9f
27817		 addiu $23,$23,2        	 # Delay slot
27818
27819		 subu  $14,$23,$22       	 # Get PC
27820		 lhu   $7,0x00($23)
27821		 addiu $23,$23,2
27822		 seb   $6,$7
27823		 or    $25,$0,$7
27824		 srl   $7,$7,12
27825		 andi  $25,$25,0x0800
27826		 sll   $7,$7,2
27827		 addu  $7,$7,$21
27828		 bne   $25,$0,0f
27829		 lw    $25,0x00($7)      	 # Delay slot
27830		 seh   $25,$25
27831	0:
27832		 addu  $25,$14,$25
27833		 addu  $14,$25,$6
27834		 lw    $25,0x9C($21)
27835		 sw    $15,m68k_ICount
27836		 or    $4,$0,$14
27837		 jalr  $25
27838		 sw    $23,0x4C($21)    	 # Delay slot
27839		 lw    $15,m68k_ICount
27840		 andi  $25,$2,0x2000    	 # User Mode ?
27841		 bne   $25,$0,0f
27842		 or    $18,$0,$2       	 # Delay slot
27843		 lw    $16,0x3C($21)
27844		 lw    $17,0x68($21)
27845		 sw    $16,0x40($21)
27846		 sw    $17,0x3C($21)
27847	0:
27848		 srl   $18,$18,8
27849		 sb    $18,0x44($21)    	 # T, S & I
27850		 or    $20,$0,$2
27851		 or    $19,$0,$2
27852		 or    $18,$0,$2
27853		 or    $17,$0,$2
27854		 or    $16,$0,$2
27855		 andi  $20,$20,0x10
27856		 andi  $19,$19,0x08
27857		 andi  $18,$18,0x04
27858		 andi  $17,$17,0x02
27859		 andi  $16,$16,0x01
27860		 srl   $20,$20,4
27861		 srl   $19,$19,3
27862		 srl   $18,$18,2
27863		 srl   $17,$17,1
27864		 addiu $15,$15,-22
27865		 bgez  $15,3f
27866		 lbu   $7,0x50($21)     	 # Delay slot
27867		 j     MainExit
27868	3:
27869 # Check for Interrupt waiting
27870
27871		 andi  $7,$7,0x07       	 # Delay slot
27872		 beq   $7,$0,3f
27873		 nop                    	 # Delay slot
27874		 j     interrupt
27875	3:
27876		 lhu   $24,0x00($23)    	 # Delay slot
27877		 sll   $7,$24,2
27878		 addu  $7,$7,$30
27879		 lw    $7,0x00($7)
27880		 jr    $7
27881		 nop                    	 # Delay slot
27882
27883	9:
27884		 addiu $23,$23,-2
27885		 jal   Exception
27886		 ori   $2,$0,8
27887
27888		 addiu $15,$15,-22
27889		 bgez  $15,3f
27890		 lbu   $7,0x50($21)     	 # Delay slot
27891		 j     MainExit
27892	3:
27893 # Check for Interrupt waiting
27894
27895		 andi  $7,$7,0x07       	 # Delay slot
27896		 beq   $7,$0,3f
27897		 nop                    	 # Delay slot
27898		 j     interrupt
27899	3:
27900		 lhu   $24,0x00($23)    	 # Delay slot
27901		 sll   $7,$24,2
27902		 addu  $7,$7,$30
27903		 lw    $7,0x00($7)
27904		 jr    $7
27905		 nop                    	 # Delay slot
27906
27907OP0_46fc:				#:
27908		 lbu   $8,0x44($21)
27909		 andi  $8,$8,0x20       	 # Supervisor Mode ?
27910		 beq   $8,$0,9f
27911		 addiu $23,$23,2        	 # Delay slot
27912
27913		 lhu   $2,0x00($23)
27914		 addiu $23,$23,2
27915		 andi  $25,$2,0x2000    	 # User Mode ?
27916		 bne   $25,$0,0f
27917		 or    $18,$0,$2       	 # Delay slot
27918		 lw    $16,0x3C($21)
27919		 lw    $17,0x68($21)
27920		 sw    $16,0x40($21)
27921		 sw    $17,0x3C($21)
27922	0:
27923		 srl   $18,$18,8
27924		 sb    $18,0x44($21)    	 # T, S & I
27925		 or    $20,$0,$2
27926		 or    $19,$0,$2
27927		 or    $18,$0,$2
27928		 or    $17,$0,$2
27929		 or    $16,$0,$2
27930		 andi  $20,$20,0x10
27931		 andi  $19,$19,0x08
27932		 andi  $18,$18,0x04
27933		 andi  $17,$17,0x02
27934		 andi  $16,$16,0x01
27935		 srl   $20,$20,4
27936		 srl   $19,$19,3
27937		 srl   $18,$18,2
27938		 srl   $17,$17,1
27939		 addiu $15,$15,-12
27940		 bgez  $15,3f
27941		 lbu   $7,0x50($21)     	 # Delay slot
27942		 j     MainExit
27943	3:
27944 # Check for Interrupt waiting
27945
27946		 andi  $7,$7,0x07       	 # Delay slot
27947		 beq   $7,$0,3f
27948		 nop                    	 # Delay slot
27949		 j     interrupt
27950	3:
27951		 lhu   $24,0x00($23)    	 # Delay slot
27952		 sll   $7,$24,2
27953		 addu  $7,$7,$30
27954		 lw    $7,0x00($7)
27955		 jr    $7
27956		 nop                    	 # Delay slot
27957
27958	9:
27959		 addiu $23,$23,-2
27960		 jal   Exception
27961		 ori   $2,$0,8
27962
27963		 addiu $15,$15,-12
27964		 bgez  $15,3f
27965		 lbu   $7,0x50($21)     	 # Delay slot
27966		 j     MainExit
27967	3:
27968 # Check for Interrupt waiting
27969
27970		 andi  $7,$7,0x07       	 # Delay slot
27971		 beq   $7,$0,3f
27972		 nop                    	 # Delay slot
27973		 j     interrupt
27974	3:
27975		 lhu   $24,0x00($23)    	 # Delay slot
27976		 sll   $7,$24,2
27977		 addu  $7,$7,$30
27978		 lw    $7,0x00($7)
27979		 jr    $7
27980		 nop                    	 # Delay slot
27981
27982OP0_5000:				#:
27983		 addiu $23,$23,2
27984
27985		 andi  $16,$24,0x07
27986		 sll   $16,$16,2
27987		 addu  $16,$16,$21
27988		 lb    $9,0x00($16)
27989		 srl   $24,$24,9
27990		 addiu $24,$24,-1       	 # Move range down
27991		 andi  $24,$24,0x07     	 # Mask out lower bits
27992		 addiu $24,$24,1        	 # correct range
27993		 addu  $2,$9,$24
27994		 sb    $2,0x00($16)
27995		 sltu  $16,$2,$24       	 # Set Carry
27996		 xor   $17,$9,$24
27997		 nor   $17,$0,$17
27998		 xor   $25,$2,$9
27999		 and   $17,$17,$25
28000		 srl   $17,$17,7
28001		 andi  $17,$17,0x01     	 # Set Overflow
28002		 seb  $25,$2
28003		 slt   $19,$25,$0        	 # Set Sign
28004		 sltiu $18,$25,1         	 # Set Zero
28005		 or    $20,$0,$16      	 # Copy Carry to X
28006		 addiu $15,$15,-4
28007		 bgez  $15,3f
28008		 lhu   $24,0x00($23)    	 # Delay slot
28009		 j     MainExit
28010	3:
28011		 sll   $7,$24,2         	 # Delay slot
28012		 addu  $7,$7,$30
28013		 lw    $7,0x00($7)
28014		 jr    $7
28015		 nop                    	 # Delay slot
28016
28017OP0_5088:				#:
28018		 addiu $23,$23,2
28019
28020		 andi  $8,$24,0x07
28021		 sll   $8,$8,2
28022		 addu  $8,$8,$21
28023		 lw    $9,0x20($8)
28024		 srl   $24,$24,9
28025		 addiu $24,$24,-1       	 # Move range down
28026		 andi  $24,$24,0x07     	 # Mask out lower bits
28027		 addiu $24,$24,1        	 # correct range
28028		 addu  $2,$9,$24
28029		 sw    $2,0x20($8)
28030		 addiu $15,$15,-8
28031		 bgez  $15,3f
28032		 lhu   $24,0x00($23)    	 # Delay slot
28033		 j     MainExit
28034	3:
28035		 sll   $7,$24,2         	 # Delay slot
28036		 addu  $7,$7,$30
28037		 lw    $7,0x00($7)
28038		 jr    $7
28039		 nop                    	 # Delay slot
28040
28041OP0_5010:				#:
28042		 addiu $23,$23,2
28043
28044		 andi  $16,$24,0x07
28045		 sll   $16,$16,2
28046		 addu  $16,$16,$21
28047		 lw    $14,0x20($16)
28048		 lw    $25,0x7C($21)
28049		 sw    $15,m68k_ICount
28050		 sw    $14,0x44($29)
28051		 sw    $24,0x40($29)
28052		 or    $4,$0,$14
28053		 jalr  $25
28054		 sw    $23,0x4C($21)    	 # Delay slot
28055		 lw    $24,0x40($29)
28056		 lw    $14,0x44($29)
28057		 lw    $15,m68k_ICount
28058		 seb   $9,$2
28059		 srl   $24,$24,9
28060		 addiu $24,$24,-1       	 # Move range down
28061		 andi  $24,$24,0x07     	 # Mask out lower bits
28062		 addiu $24,$24,1        	 # correct range
28063		 addu  $2,$9,$24
28064		 sltu  $16,$2,$24       	 # Set Carry
28065		 xor   $17,$9,$24
28066		 nor   $17,$0,$17
28067		 xor   $25,$2,$9
28068		 and   $17,$17,$25
28069		 srl   $17,$17,7
28070		 andi  $17,$17,0x01     	 # Set Overflow
28071		 seb  $25,$2
28072		 slt   $19,$25,$0        	 # Set Sign
28073		 sltiu $18,$25,1         	 # Set Zero
28074		 or    $20,$0,$16      	 # Copy Carry to X
28075		 lw    $25,0x88($21)
28076		 sw    $15,m68k_ICount
28077		 or    $5,$0,$2
28078		 or    $4,$0,$14
28079		 jalr  $25
28080		 sw    $23,0x4C($21)    	 # Delay slot
28081		 lw    $15,m68k_ICount
28082		 addiu $15,$15,-12
28083		 bgez  $15,3f
28084		 lhu   $24,0x00($23)    	 # Delay slot
28085		 j     MainExit
28086	3:
28087		 sll   $7,$24,2         	 # Delay slot
28088		 addu  $7,$7,$30
28089		 lw    $7,0x00($7)
28090		 jr    $7
28091		 nop                    	 # Delay slot
28092
28093OP0_5018:				#:
28094		 addiu $23,$23,2
28095
28096		 andi  $16,$24,0x07
28097		 sll   $16,$16,2
28098		 addu  $16,$16,$21
28099		 lw    $14,0x20($16)
28100		 addiu $25,$14,1
28101		 sw    $25,0x20($16)
28102		 lw    $25,0x7C($21)
28103		 sw    $15,m68k_ICount
28104		 sw    $14,0x44($29)
28105		 sw    $24,0x40($29)
28106		 or    $4,$0,$14
28107		 jalr  $25
28108		 sw    $23,0x4C($21)    	 # Delay slot
28109		 lw    $24,0x40($29)
28110		 lw    $14,0x44($29)
28111		 lw    $15,m68k_ICount
28112		 seb   $9,$2
28113		 srl   $24,$24,9
28114		 addiu $24,$24,-1       	 # Move range down
28115		 andi  $24,$24,0x07     	 # Mask out lower bits
28116		 addiu $24,$24,1        	 # correct range
28117		 addu  $2,$9,$24
28118		 sltu  $16,$2,$24       	 # Set Carry
28119		 xor   $17,$9,$24
28120		 nor   $17,$0,$17
28121		 xor   $25,$2,$9
28122		 and   $17,$17,$25
28123		 srl   $17,$17,7
28124		 andi  $17,$17,0x01     	 # Set Overflow
28125		 seb  $25,$2
28126		 slt   $19,$25,$0        	 # Set Sign
28127		 sltiu $18,$25,1         	 # Set Zero
28128		 or    $20,$0,$16      	 # Copy Carry to X
28129		 lw    $25,0x88($21)
28130		 sw    $15,m68k_ICount
28131		 or    $5,$0,$2
28132		 or    $4,$0,$14
28133		 jalr  $25
28134		 sw    $23,0x4C($21)    	 # Delay slot
28135		 lw    $15,m68k_ICount
28136		 addiu $15,$15,-12
28137		 bgez  $15,3f
28138		 lhu   $24,0x00($23)    	 # Delay slot
28139		 j     MainExit
28140	3:
28141		 sll   $7,$24,2         	 # Delay slot
28142		 addu  $7,$7,$30
28143		 lw    $7,0x00($7)
28144		 jr    $7
28145		 nop                    	 # Delay slot
28146
28147OP0_501f:				#:
28148		 addiu $23,$23,2
28149
28150		 lw    $14,0x3C($21)    	 # Get A7
28151		 addiu $25,$14,2
28152		 sw    $25,0x3C($21)
28153		 lw    $25,0x7C($21)
28154		 sw    $15,m68k_ICount
28155		 sw    $14,0x44($29)
28156		 sw    $24,0x40($29)
28157		 or    $4,$0,$14
28158		 jalr  $25
28159		 sw    $23,0x4C($21)    	 # Delay slot
28160		 lw    $24,0x40($29)
28161		 lw    $14,0x44($29)
28162		 lw    $15,m68k_ICount
28163		 seb   $9,$2
28164		 srl   $24,$24,9
28165		 addiu $24,$24,-1       	 # Move range down
28166		 andi  $24,$24,0x07     	 # Mask out lower bits
28167		 addiu $24,$24,1        	 # correct range
28168		 addu  $2,$9,$24
28169		 sltu  $16,$2,$24       	 # Set Carry
28170		 xor   $17,$9,$24
28171		 nor   $17,$0,$17
28172		 xor   $25,$2,$9
28173		 and   $17,$17,$25
28174		 srl   $17,$17,7
28175		 andi  $17,$17,0x01     	 # Set Overflow
28176		 seb  $25,$2
28177		 slt   $19,$25,$0        	 # Set Sign
28178		 sltiu $18,$25,1         	 # Set Zero
28179		 or    $20,$0,$16      	 # Copy Carry to X
28180		 lw    $25,0x88($21)
28181		 sw    $15,m68k_ICount
28182		 or    $5,$0,$2
28183		 or    $4,$0,$14
28184		 jalr  $25
28185		 sw    $23,0x4C($21)    	 # Delay slot
28186		 lw    $15,m68k_ICount
28187		 addiu $15,$15,-12
28188		 bgez  $15,3f
28189		 lhu   $24,0x00($23)    	 # Delay slot
28190		 j     MainExit
28191	3:
28192		 sll   $7,$24,2         	 # Delay slot
28193		 addu  $7,$7,$30
28194		 lw    $7,0x00($7)
28195		 jr    $7
28196		 nop                    	 # Delay slot
28197
28198OP0_5020:				#:
28199		 addiu $23,$23,2
28200
28201		 andi  $16,$24,0x07
28202		 sll   $16,$16,2
28203		 addu  $16,$16,$21
28204		 lw    $14,0x20($16)
28205		 addiu $14,$14,-1
28206		 sw    $14,0x20($16)
28207		 lw    $25,0x7C($21)
28208		 sw    $15,m68k_ICount
28209		 sw    $14,0x44($29)
28210		 sw    $24,0x40($29)
28211		 or    $4,$0,$14
28212		 jalr  $25
28213		 sw    $23,0x4C($21)    	 # Delay slot
28214		 lw    $24,0x40($29)
28215		 lw    $14,0x44($29)
28216		 lw    $15,m68k_ICount
28217		 seb   $9,$2
28218		 srl   $24,$24,9
28219		 addiu $24,$24,-1       	 # Move range down
28220		 andi  $24,$24,0x07     	 # Mask out lower bits
28221		 addiu $24,$24,1        	 # correct range
28222		 addu  $2,$9,$24
28223		 sltu  $16,$2,$24       	 # Set Carry
28224		 xor   $17,$9,$24
28225		 nor   $17,$0,$17
28226		 xor   $25,$2,$9
28227		 and   $17,$17,$25
28228		 srl   $17,$17,7
28229		 andi  $17,$17,0x01     	 # Set Overflow
28230		 seb  $25,$2
28231		 slt   $19,$25,$0        	 # Set Sign
28232		 sltiu $18,$25,1         	 # Set Zero
28233		 or    $20,$0,$16      	 # Copy Carry to X
28234		 lw    $25,0x88($21)
28235		 sw    $15,m68k_ICount
28236		 or    $5,$0,$2
28237		 or    $4,$0,$14
28238		 jalr  $25
28239		 sw    $23,0x4C($21)    	 # Delay slot
28240		 lw    $15,m68k_ICount
28241		 addiu $15,$15,-14
28242		 bgez  $15,3f
28243		 lhu   $24,0x00($23)    	 # Delay slot
28244		 j     MainExit
28245	3:
28246		 sll   $7,$24,2         	 # Delay slot
28247		 addu  $7,$7,$30
28248		 lw    $7,0x00($7)
28249		 jr    $7
28250		 nop                    	 # Delay slot
28251
28252OP0_5027:				#:
28253		 addiu $23,$23,2
28254
28255		 lw    $14,0x3C($21)    	 # Get A7
28256		 addiu $14,$14,-2
28257		 sw    $14,0x3C($21)
28258		 lw    $25,0x7C($21)
28259		 sw    $15,m68k_ICount
28260		 sw    $14,0x44($29)
28261		 sw    $24,0x40($29)
28262		 or    $4,$0,$14
28263		 jalr  $25
28264		 sw    $23,0x4C($21)    	 # Delay slot
28265		 lw    $24,0x40($29)
28266		 lw    $14,0x44($29)
28267		 lw    $15,m68k_ICount
28268		 seb   $9,$2
28269		 srl   $24,$24,9
28270		 addiu $24,$24,-1       	 # Move range down
28271		 andi  $24,$24,0x07     	 # Mask out lower bits
28272		 addiu $24,$24,1        	 # correct range
28273		 addu  $2,$9,$24
28274		 sltu  $16,$2,$24       	 # Set Carry
28275		 xor   $17,$9,$24
28276		 nor   $17,$0,$17
28277		 xor   $25,$2,$9
28278		 and   $17,$17,$25
28279		 srl   $17,$17,7
28280		 andi  $17,$17,0x01     	 # Set Overflow
28281		 seb  $25,$2
28282		 slt   $19,$25,$0        	 # Set Sign
28283		 sltiu $18,$25,1         	 # Set Zero
28284		 or    $20,$0,$16      	 # Copy Carry to X
28285		 lw    $25,0x88($21)
28286		 sw    $15,m68k_ICount
28287		 or    $5,$0,$2
28288		 or    $4,$0,$14
28289		 jalr  $25
28290		 sw    $23,0x4C($21)    	 # Delay slot
28291		 lw    $15,m68k_ICount
28292		 addiu $15,$15,-14
28293		 bgez  $15,3f
28294		 lhu   $24,0x00($23)    	 # Delay slot
28295		 j     MainExit
28296	3:
28297		 sll   $7,$24,2         	 # Delay slot
28298		 addu  $7,$7,$30
28299		 lw    $7,0x00($7)
28300		 jr    $7
28301		 nop                    	 # Delay slot
28302
28303OP0_5028:				#:
28304		 addiu $23,$23,2
28305
28306		 andi  $16,$24,0x07
28307		 lh    $7,0x00($23)
28308		 sll   $16,$16,2
28309		 addu  $16,$16,$21
28310		 lw    $14,0x20($16)
28311		 addiu $23,$23,2
28312		 addu  $14,$14,$7
28313		 lw    $25,0x7C($21)
28314		 sw    $15,m68k_ICount
28315		 sw    $14,0x44($29)
28316		 sw    $24,0x40($29)
28317		 or    $4,$0,$14
28318		 jalr  $25
28319		 sw    $23,0x4C($21)    	 # Delay slot
28320		 lw    $24,0x40($29)
28321		 lw    $14,0x44($29)
28322		 lw    $15,m68k_ICount
28323		 seb   $9,$2
28324		 srl   $24,$24,9
28325		 addiu $24,$24,-1       	 # Move range down
28326		 andi  $24,$24,0x07     	 # Mask out lower bits
28327		 addiu $24,$24,1        	 # correct range
28328		 addu  $2,$9,$24
28329		 sltu  $16,$2,$24       	 # Set Carry
28330		 xor   $17,$9,$24
28331		 nor   $17,$0,$17
28332		 xor   $25,$2,$9
28333		 and   $17,$17,$25
28334		 srl   $17,$17,7
28335		 andi  $17,$17,0x01     	 # Set Overflow
28336		 seb  $25,$2
28337		 slt   $19,$25,$0        	 # Set Sign
28338		 sltiu $18,$25,1         	 # Set Zero
28339		 or    $20,$0,$16      	 # Copy Carry to X
28340		 lw    $25,0x88($21)
28341		 sw    $15,m68k_ICount
28342		 or    $5,$0,$2
28343		 or    $4,$0,$14
28344		 jalr  $25
28345		 sw    $23,0x4C($21)    	 # Delay slot
28346		 lw    $15,m68k_ICount
28347		 addiu $15,$15,-16
28348		 bgez  $15,3f
28349		 lhu   $24,0x00($23)    	 # Delay slot
28350		 j     MainExit
28351	3:
28352		 sll   $7,$24,2         	 # Delay slot
28353		 addu  $7,$7,$30
28354		 lw    $7,0x00($7)
28355		 jr    $7
28356		 nop                    	 # Delay slot
28357
28358OP0_5030:				#:
28359		 addiu $23,$23,2
28360
28361		 andi  $16,$24,0x07
28362		 sll   $16,$16,2
28363		 addu  $16,$16,$21
28364		 lw    $14,0x20($16)
28365		 lhu   $7,0x00($23)
28366		 addiu $23,$23,2
28367		 seb   $6,$7
28368		 or    $25,$0,$7
28369		 srl   $7,$7,12
28370		 andi  $25,$25,0x0800
28371		 sll   $7,$7,2
28372		 addu  $7,$7,$21
28373		 bne   $25,$0,0f
28374		 lw    $25,0x00($7)      	 # Delay slot
28375		 seh   $25,$25
28376	0:
28377		 addu  $25,$14,$25
28378		 addu  $14,$25,$6
28379		 lw    $25,0x7C($21)
28380		 sw    $15,m68k_ICount
28381		 sw    $14,0x44($29)
28382		 sw    $24,0x40($29)
28383		 or    $4,$0,$14
28384		 jalr  $25
28385		 sw    $23,0x4C($21)    	 # Delay slot
28386		 lw    $24,0x40($29)
28387		 lw    $14,0x44($29)
28388		 lw    $15,m68k_ICount
28389		 seb   $9,$2
28390		 srl   $24,$24,9
28391		 addiu $24,$24,-1       	 # Move range down
28392		 andi  $24,$24,0x07     	 # Mask out lower bits
28393		 addiu $24,$24,1        	 # correct range
28394		 addu  $2,$9,$24
28395		 sltu  $16,$2,$24       	 # Set Carry
28396		 xor   $17,$9,$24
28397		 nor   $17,$0,$17
28398		 xor   $25,$2,$9
28399		 and   $17,$17,$25
28400		 srl   $17,$17,7
28401		 andi  $17,$17,0x01     	 # Set Overflow
28402		 seb  $25,$2
28403		 slt   $19,$25,$0        	 # Set Sign
28404		 sltiu $18,$25,1         	 # Set Zero
28405		 or    $20,$0,$16      	 # Copy Carry to X
28406		 lw    $25,0x88($21)
28407		 sw    $15,m68k_ICount
28408		 or    $5,$0,$2
28409		 or    $4,$0,$14
28410		 jalr  $25
28411		 sw    $23,0x4C($21)    	 # Delay slot
28412		 lw    $15,m68k_ICount
28413		 addiu $15,$15,-18
28414		 bgez  $15,3f
28415		 lhu   $24,0x00($23)    	 # Delay slot
28416		 j     MainExit
28417	3:
28418		 sll   $7,$24,2         	 # Delay slot
28419		 addu  $7,$7,$30
28420		 lw    $7,0x00($7)
28421		 jr    $7
28422		 nop                    	 # Delay slot
28423
28424OP0_5038:				#:
28425		 addiu $23,$23,2
28426
28427		 lh    $14,0x00($23)
28428		 addiu $23,$23,2
28429		 lw    $25,0x7C($21)
28430		 sw    $15,m68k_ICount
28431		 sw    $14,0x44($29)
28432		 sw    $24,0x40($29)
28433		 or    $4,$0,$14
28434		 jalr  $25
28435		 sw    $23,0x4C($21)    	 # Delay slot
28436		 lw    $24,0x40($29)
28437		 lw    $14,0x44($29)
28438		 lw    $15,m68k_ICount
28439		 seb   $9,$2
28440		 srl   $24,$24,9
28441		 addiu $24,$24,-1       	 # Move range down
28442		 andi  $24,$24,0x07     	 # Mask out lower bits
28443		 addiu $24,$24,1        	 # correct range
28444		 addu  $2,$9,$24
28445		 sltu  $16,$2,$24       	 # Set Carry
28446		 xor   $17,$9,$24
28447		 nor   $17,$0,$17
28448		 xor   $25,$2,$9
28449		 and   $17,$17,$25
28450		 srl   $17,$17,7
28451		 andi  $17,$17,0x01     	 # Set Overflow
28452		 seb  $25,$2
28453		 slt   $19,$25,$0        	 # Set Sign
28454		 sltiu $18,$25,1         	 # Set Zero
28455		 or    $20,$0,$16      	 # Copy Carry to X
28456		 lw    $25,0x88($21)
28457		 sw    $15,m68k_ICount
28458		 or    $5,$0,$2
28459		 or    $4,$0,$14
28460		 jalr  $25
28461		 sw    $23,0x4C($21)    	 # Delay slot
28462		 lw    $15,m68k_ICount
28463		 addiu $15,$15,-16
28464		 bgez  $15,3f
28465		 lhu   $24,0x00($23)    	 # Delay slot
28466		 j     MainExit
28467	3:
28468		 sll   $7,$24,2         	 # Delay slot
28469		 addu  $7,$7,$30
28470		 lw    $7,0x00($7)
28471		 jr    $7
28472		 nop                    	 # Delay slot
28473
28474OP0_5039:				#:
28475		 addiu $23,$23,2
28476
28477		 lhu   $14,0x00($23)
28478		 lhu   $25,0x02($23)
28479		 sll   $14,$14,16
28480		 or    $14,$14,$25
28481		 addiu $23,$23,4
28482		 lw    $25,0x7C($21)
28483		 sw    $15,m68k_ICount
28484		 sw    $14,0x44($29)
28485		 sw    $24,0x40($29)
28486		 or    $4,$0,$14
28487		 jalr  $25
28488		 sw    $23,0x4C($21)    	 # Delay slot
28489		 lw    $24,0x40($29)
28490		 lw    $14,0x44($29)
28491		 lw    $15,m68k_ICount
28492		 seb   $9,$2
28493		 srl   $24,$24,9
28494		 addiu $24,$24,-1       	 # Move range down
28495		 andi  $24,$24,0x07     	 # Mask out lower bits
28496		 addiu $24,$24,1        	 # correct range
28497		 addu  $2,$9,$24
28498		 sltu  $16,$2,$24       	 # Set Carry
28499		 xor   $17,$9,$24
28500		 nor   $17,$0,$17
28501		 xor   $25,$2,$9
28502		 and   $17,$17,$25
28503		 srl   $17,$17,7
28504		 andi  $17,$17,0x01     	 # Set Overflow
28505		 seb  $25,$2
28506		 slt   $19,$25,$0        	 # Set Sign
28507		 sltiu $18,$25,1         	 # Set Zero
28508		 or    $20,$0,$16      	 # Copy Carry to X
28509		 lw    $25,0x88($21)
28510		 sw    $15,m68k_ICount
28511		 or    $5,$0,$2
28512		 or    $4,$0,$14
28513		 jalr  $25
28514		 sw    $23,0x4C($21)    	 # Delay slot
28515		 lw    $15,m68k_ICount
28516		 addiu $15,$15,-20
28517		 bgez  $15,3f
28518		 lhu   $24,0x00($23)    	 # Delay slot
28519		 j     MainExit
28520	3:
28521		 sll   $7,$24,2         	 # Delay slot
28522		 addu  $7,$7,$30
28523		 lw    $7,0x00($7)
28524		 jr    $7
28525		 nop                    	 # Delay slot
28526
28527OP0_5040:				#:
28528		 addiu $23,$23,2
28529
28530		 andi  $16,$24,0x07
28531		 sll   $16,$16,2
28532		 addu  $16,$16,$21
28533		 lh    $9,0x00($16)
28534		 srl   $24,$24,9
28535		 addiu $24,$24,-1       	 # Move range down
28536		 andi  $24,$24,0x07     	 # Mask out lower bits
28537		 addiu $24,$24,1        	 # correct range
28538		 addu  $2,$9,$24
28539		 sh    $2,0x00($16)
28540		 sltu  $16,$2,$24       	 # Set Carry
28541		 xor   $17,$9,$24
28542		 nor   $17,$0,$17
28543		 xor   $25,$2,$9
28544		 and   $17,$17,$25
28545		 srl   $17,$17,15
28546		 andi  $17,$17,0x01     	 # Set Overflow
28547		 seh  $25,$2
28548		 slt   $19,$25,$0        	 # Set Sign
28549		 sltiu $18,$25,1         	 # Set Zero
28550		 or    $20,$0,$16      	 # Copy Carry to X
28551		 addiu $15,$15,-4
28552		 bgez  $15,3f
28553		 lhu   $24,0x00($23)    	 # Delay slot
28554		 j     MainExit
28555	3:
28556		 sll   $7,$24,2         	 # Delay slot
28557		 addu  $7,$7,$30
28558		 lw    $7,0x00($7)
28559		 jr    $7
28560		 nop                    	 # Delay slot
28561
28562OP0_5050:				#:
28563		 addiu $23,$23,2
28564
28565		 andi  $16,$24,0x07
28566		 sll   $16,$16,2
28567		 addu  $16,$16,$21
28568		 lw    $14,0x20($16)
28569		 lw    $25,0x80($21)
28570		 sw    $15,m68k_ICount
28571		 sw    $14,0x44($29)
28572		 sw    $24,0x40($29)
28573		 or    $4,$0,$14
28574		 jalr  $25
28575		 sw    $23,0x4C($21)    	 # Delay slot
28576		 lw    $24,0x40($29)
28577		 lw    $14,0x44($29)
28578		 lw    $15,m68k_ICount
28579		 seh   $9,$2
28580		 srl   $24,$24,9
28581		 addiu $24,$24,-1       	 # Move range down
28582		 andi  $24,$24,0x07     	 # Mask out lower bits
28583		 addiu $24,$24,1        	 # correct range
28584		 addu  $2,$9,$24
28585		 sltu  $16,$2,$24       	 # Set Carry
28586		 xor   $17,$9,$24
28587		 nor   $17,$0,$17
28588		 xor   $25,$2,$9
28589		 and   $17,$17,$25
28590		 srl   $17,$17,15
28591		 andi  $17,$17,0x01     	 # Set Overflow
28592		 seh  $25,$2
28593		 slt   $19,$25,$0        	 # Set Sign
28594		 sltiu $18,$25,1         	 # Set Zero
28595		 or    $20,$0,$16      	 # Copy Carry to X
28596		 lw    $25,0x8C($21)
28597		 sw    $15,m68k_ICount
28598		 or    $5,$0,$2
28599		 or    $4,$0,$14
28600		 jalr  $25
28601		 sw    $23,0x4C($21)    	 # Delay slot
28602		 lw    $15,m68k_ICount
28603		 addiu $15,$15,-12
28604		 bgez  $15,3f
28605		 lhu   $24,0x00($23)    	 # Delay slot
28606		 j     MainExit
28607	3:
28608		 sll   $7,$24,2         	 # Delay slot
28609		 addu  $7,$7,$30
28610		 lw    $7,0x00($7)
28611		 jr    $7
28612		 nop                    	 # Delay slot
28613
28614OP0_5058:				#:
28615		 addiu $23,$23,2
28616
28617		 andi  $16,$24,0x07
28618		 sll   $16,$16,2
28619		 addu  $16,$16,$21
28620		 lw    $14,0x20($16)
28621		 addiu $25,$14,2
28622		 sw    $25,0x20($16)
28623		 lw    $25,0x80($21)
28624		 sw    $15,m68k_ICount
28625		 sw    $14,0x44($29)
28626		 sw    $24,0x40($29)
28627		 or    $4,$0,$14
28628		 jalr  $25
28629		 sw    $23,0x4C($21)    	 # Delay slot
28630		 lw    $24,0x40($29)
28631		 lw    $14,0x44($29)
28632		 lw    $15,m68k_ICount
28633		 seh   $9,$2
28634		 srl   $24,$24,9
28635		 addiu $24,$24,-1       	 # Move range down
28636		 andi  $24,$24,0x07     	 # Mask out lower bits
28637		 addiu $24,$24,1        	 # correct range
28638		 addu  $2,$9,$24
28639		 sltu  $16,$2,$24       	 # Set Carry
28640		 xor   $17,$9,$24
28641		 nor   $17,$0,$17
28642		 xor   $25,$2,$9
28643		 and   $17,$17,$25
28644		 srl   $17,$17,15
28645		 andi  $17,$17,0x01     	 # Set Overflow
28646		 seh  $25,$2
28647		 slt   $19,$25,$0        	 # Set Sign
28648		 sltiu $18,$25,1         	 # Set Zero
28649		 or    $20,$0,$16      	 # Copy Carry to X
28650		 lw    $25,0x8C($21)
28651		 sw    $15,m68k_ICount
28652		 or    $5,$0,$2
28653		 or    $4,$0,$14
28654		 jalr  $25
28655		 sw    $23,0x4C($21)    	 # Delay slot
28656		 lw    $15,m68k_ICount
28657		 addiu $15,$15,-12
28658		 bgez  $15,3f
28659		 lhu   $24,0x00($23)    	 # Delay slot
28660		 j     MainExit
28661	3:
28662		 sll   $7,$24,2         	 # Delay slot
28663		 addu  $7,$7,$30
28664		 lw    $7,0x00($7)
28665		 jr    $7
28666		 nop                    	 # Delay slot
28667
28668OP0_5060:				#:
28669		 addiu $23,$23,2
28670
28671		 andi  $16,$24,0x07
28672		 sll   $16,$16,2
28673		 addu  $16,$16,$21
28674		 lw    $14,0x20($16)
28675		 addiu $14,$14,-2
28676		 sw    $14,0x20($16)
28677		 lw    $25,0x80($21)
28678		 sw    $15,m68k_ICount
28679		 sw    $14,0x44($29)
28680		 sw    $24,0x40($29)
28681		 or    $4,$0,$14
28682		 jalr  $25
28683		 sw    $23,0x4C($21)    	 # Delay slot
28684		 lw    $24,0x40($29)
28685		 lw    $14,0x44($29)
28686		 lw    $15,m68k_ICount
28687		 seh   $9,$2
28688		 srl   $24,$24,9
28689		 addiu $24,$24,-1       	 # Move range down
28690		 andi  $24,$24,0x07     	 # Mask out lower bits
28691		 addiu $24,$24,1        	 # correct range
28692		 addu  $2,$9,$24
28693		 sltu  $16,$2,$24       	 # Set Carry
28694		 xor   $17,$9,$24
28695		 nor   $17,$0,$17
28696		 xor   $25,$2,$9
28697		 and   $17,$17,$25
28698		 srl   $17,$17,15
28699		 andi  $17,$17,0x01     	 # Set Overflow
28700		 seh  $25,$2
28701		 slt   $19,$25,$0        	 # Set Sign
28702		 sltiu $18,$25,1         	 # Set Zero
28703		 or    $20,$0,$16      	 # Copy Carry to X
28704		 lw    $25,0x8C($21)
28705		 sw    $15,m68k_ICount
28706		 or    $5,$0,$2
28707		 or    $4,$0,$14
28708		 jalr  $25
28709		 sw    $23,0x4C($21)    	 # Delay slot
28710		 lw    $15,m68k_ICount
28711		 addiu $15,$15,-14
28712		 bgez  $15,3f
28713		 lhu   $24,0x00($23)    	 # Delay slot
28714		 j     MainExit
28715	3:
28716		 sll   $7,$24,2         	 # Delay slot
28717		 addu  $7,$7,$30
28718		 lw    $7,0x00($7)
28719		 jr    $7
28720		 nop                    	 # Delay slot
28721
28722OP0_5068:				#:
28723		 addiu $23,$23,2
28724
28725		 andi  $16,$24,0x07
28726		 lh    $7,0x00($23)
28727		 sll   $16,$16,2
28728		 addu  $16,$16,$21
28729		 lw    $14,0x20($16)
28730		 addiu $23,$23,2
28731		 addu  $14,$14,$7
28732		 lw    $25,0x80($21)
28733		 sw    $15,m68k_ICount
28734		 sw    $14,0x44($29)
28735		 sw    $24,0x40($29)
28736		 or    $4,$0,$14
28737		 jalr  $25
28738		 sw    $23,0x4C($21)    	 # Delay slot
28739		 lw    $24,0x40($29)
28740		 lw    $14,0x44($29)
28741		 lw    $15,m68k_ICount
28742		 seh   $9,$2
28743		 srl   $24,$24,9
28744		 addiu $24,$24,-1       	 # Move range down
28745		 andi  $24,$24,0x07     	 # Mask out lower bits
28746		 addiu $24,$24,1        	 # correct range
28747		 addu  $2,$9,$24
28748		 sltu  $16,$2,$24       	 # Set Carry
28749		 xor   $17,$9,$24
28750		 nor   $17,$0,$17
28751		 xor   $25,$2,$9
28752		 and   $17,$17,$25
28753		 srl   $17,$17,15
28754		 andi  $17,$17,0x01     	 # Set Overflow
28755		 seh  $25,$2
28756		 slt   $19,$25,$0        	 # Set Sign
28757		 sltiu $18,$25,1         	 # Set Zero
28758		 or    $20,$0,$16      	 # Copy Carry to X
28759		 lw    $25,0x8C($21)
28760		 sw    $15,m68k_ICount
28761		 or    $5,$0,$2
28762		 or    $4,$0,$14
28763		 jalr  $25
28764		 sw    $23,0x4C($21)    	 # Delay slot
28765		 lw    $15,m68k_ICount
28766		 addiu $15,$15,-16
28767		 bgez  $15,3f
28768		 lhu   $24,0x00($23)    	 # Delay slot
28769		 j     MainExit
28770	3:
28771		 sll   $7,$24,2         	 # Delay slot
28772		 addu  $7,$7,$30
28773		 lw    $7,0x00($7)
28774		 jr    $7
28775		 nop                    	 # Delay slot
28776
28777OP0_5070:				#:
28778		 addiu $23,$23,2
28779
28780		 andi  $16,$24,0x07
28781		 sll   $16,$16,2
28782		 addu  $16,$16,$21
28783		 lw    $14,0x20($16)
28784		 lhu   $7,0x00($23)
28785		 addiu $23,$23,2
28786		 seb   $6,$7
28787		 or    $25,$0,$7
28788		 srl   $7,$7,12
28789		 andi  $25,$25,0x0800
28790		 sll   $7,$7,2
28791		 addu  $7,$7,$21
28792		 bne   $25,$0,0f
28793		 lw    $25,0x00($7)      	 # Delay slot
28794		 seh   $25,$25
28795	0:
28796		 addu  $25,$14,$25
28797		 addu  $14,$25,$6
28798		 lw    $25,0x80($21)
28799		 sw    $15,m68k_ICount
28800		 sw    $14,0x44($29)
28801		 sw    $24,0x40($29)
28802		 or    $4,$0,$14
28803		 jalr  $25
28804		 sw    $23,0x4C($21)    	 # Delay slot
28805		 lw    $24,0x40($29)
28806		 lw    $14,0x44($29)
28807		 lw    $15,m68k_ICount
28808		 seh   $9,$2
28809		 srl   $24,$24,9
28810		 addiu $24,$24,-1       	 # Move range down
28811		 andi  $24,$24,0x07     	 # Mask out lower bits
28812		 addiu $24,$24,1        	 # correct range
28813		 addu  $2,$9,$24
28814		 sltu  $16,$2,$24       	 # Set Carry
28815		 xor   $17,$9,$24
28816		 nor   $17,$0,$17
28817		 xor   $25,$2,$9
28818		 and   $17,$17,$25
28819		 srl   $17,$17,15
28820		 andi  $17,$17,0x01     	 # Set Overflow
28821		 seh  $25,$2
28822		 slt   $19,$25,$0        	 # Set Sign
28823		 sltiu $18,$25,1         	 # Set Zero
28824		 or    $20,$0,$16      	 # Copy Carry to X
28825		 lw    $25,0x8C($21)
28826		 sw    $15,m68k_ICount
28827		 or    $5,$0,$2
28828		 or    $4,$0,$14
28829		 jalr  $25
28830		 sw    $23,0x4C($21)    	 # Delay slot
28831		 lw    $15,m68k_ICount
28832		 addiu $15,$15,-18
28833		 bgez  $15,3f
28834		 lhu   $24,0x00($23)    	 # Delay slot
28835		 j     MainExit
28836	3:
28837		 sll   $7,$24,2         	 # Delay slot
28838		 addu  $7,$7,$30
28839		 lw    $7,0x00($7)
28840		 jr    $7
28841		 nop                    	 # Delay slot
28842
28843OP0_5078:				#:
28844		 addiu $23,$23,2
28845
28846		 lh    $14,0x00($23)
28847		 addiu $23,$23,2
28848		 lw    $25,0x80($21)
28849		 sw    $15,m68k_ICount
28850		 sw    $14,0x44($29)
28851		 sw    $24,0x40($29)
28852		 or    $4,$0,$14
28853		 jalr  $25
28854		 sw    $23,0x4C($21)    	 # Delay slot
28855		 lw    $24,0x40($29)
28856		 lw    $14,0x44($29)
28857		 lw    $15,m68k_ICount
28858		 seh   $9,$2
28859		 srl   $24,$24,9
28860		 addiu $24,$24,-1       	 # Move range down
28861		 andi  $24,$24,0x07     	 # Mask out lower bits
28862		 addiu $24,$24,1        	 # correct range
28863		 addu  $2,$9,$24
28864		 sltu  $16,$2,$24       	 # Set Carry
28865		 xor   $17,$9,$24
28866		 nor   $17,$0,$17
28867		 xor   $25,$2,$9
28868		 and   $17,$17,$25
28869		 srl   $17,$17,15
28870		 andi  $17,$17,0x01     	 # Set Overflow
28871		 seh  $25,$2
28872		 slt   $19,$25,$0        	 # Set Sign
28873		 sltiu $18,$25,1         	 # Set Zero
28874		 or    $20,$0,$16      	 # Copy Carry to X
28875		 lw    $25,0x8C($21)
28876		 sw    $15,m68k_ICount
28877		 or    $5,$0,$2
28878		 or    $4,$0,$14
28879		 jalr  $25
28880		 sw    $23,0x4C($21)    	 # Delay slot
28881		 lw    $15,m68k_ICount
28882		 addiu $15,$15,-16
28883		 bgez  $15,3f
28884		 lhu   $24,0x00($23)    	 # Delay slot
28885		 j     MainExit
28886	3:
28887		 sll   $7,$24,2         	 # Delay slot
28888		 addu  $7,$7,$30
28889		 lw    $7,0x00($7)
28890		 jr    $7
28891		 nop                    	 # Delay slot
28892
28893OP0_5079:				#:
28894		 addiu $23,$23,2
28895
28896		 lhu   $14,0x00($23)
28897		 lhu   $25,0x02($23)
28898		 sll   $14,$14,16
28899		 or    $14,$14,$25
28900		 addiu $23,$23,4
28901		 lw    $25,0x80($21)
28902		 sw    $15,m68k_ICount
28903		 sw    $14,0x44($29)
28904		 sw    $24,0x40($29)
28905		 or    $4,$0,$14
28906		 jalr  $25
28907		 sw    $23,0x4C($21)    	 # Delay slot
28908		 lw    $24,0x40($29)
28909		 lw    $14,0x44($29)
28910		 lw    $15,m68k_ICount
28911		 seh   $9,$2
28912		 srl   $24,$24,9
28913		 addiu $24,$24,-1       	 # Move range down
28914		 andi  $24,$24,0x07     	 # Mask out lower bits
28915		 addiu $24,$24,1        	 # correct range
28916		 addu  $2,$9,$24
28917		 sltu  $16,$2,$24       	 # Set Carry
28918		 xor   $17,$9,$24
28919		 nor   $17,$0,$17
28920		 xor   $25,$2,$9
28921		 and   $17,$17,$25
28922		 srl   $17,$17,15
28923		 andi  $17,$17,0x01     	 # Set Overflow
28924		 seh  $25,$2
28925		 slt   $19,$25,$0        	 # Set Sign
28926		 sltiu $18,$25,1         	 # Set Zero
28927		 or    $20,$0,$16      	 # Copy Carry to X
28928		 lw    $25,0x8C($21)
28929		 sw    $15,m68k_ICount
28930		 or    $5,$0,$2
28931		 or    $4,$0,$14
28932		 jalr  $25
28933		 sw    $23,0x4C($21)    	 # Delay slot
28934		 lw    $15,m68k_ICount
28935		 addiu $15,$15,-20
28936		 bgez  $15,3f
28937		 lhu   $24,0x00($23)    	 # Delay slot
28938		 j     MainExit
28939	3:
28940		 sll   $7,$24,2         	 # Delay slot
28941		 addu  $7,$7,$30
28942		 lw    $7,0x00($7)
28943		 jr    $7
28944		 nop                    	 # Delay slot
28945
28946OP0_5080:				#:
28947		 addiu $23,$23,2
28948
28949		 andi  $16,$24,0x07
28950		 sll   $16,$16,2
28951		 addu  $16,$16,$21
28952		 lw    $9,0x00($16)
28953		 srl   $24,$24,9
28954		 addiu $24,$24,-1       	 # Move range down
28955		 andi  $24,$24,0x07     	 # Mask out lower bits
28956		 addiu $24,$24,1        	 # correct range
28957		 addu  $2,$9,$24
28958		 sw    $2,0x00($16)
28959		 sltu  $16,$2,$24       	 # Set Carry
28960		 xor   $17,$9,$24
28961		 nor   $17,$0,$17
28962		 xor   $25,$2,$9
28963		 and   $17,$17,$25
28964		 srl   $17,$17,31        	 # Set Overflow
28965		 slt   $19,$2,$0        	 # Set Sign
28966		 sltiu $18,$2,1         	 # Set Zero
28967		 or    $20,$0,$16      	 # Copy Carry to X
28968		 addiu $15,$15,-8
28969		 bgez  $15,3f
28970		 lhu   $24,0x00($23)    	 # Delay slot
28971		 j     MainExit
28972	3:
28973		 sll   $7,$24,2         	 # Delay slot
28974		 addu  $7,$7,$30
28975		 lw    $7,0x00($7)
28976		 jr    $7
28977		 nop                    	 # Delay slot
28978
28979OP0_5090:				#:
28980		 addiu $23,$23,2
28981
28982		 andi  $16,$24,0x07
28983		 sll   $16,$16,2
28984		 addu  $16,$16,$21
28985		 lw    $14,0x20($16)
28986		 lw    $25,0x84($21)
28987		 sw    $15,m68k_ICount
28988		 sw    $14,0x44($29)
28989		 sw    $24,0x40($29)
28990		 or    $4,$0,$14
28991		 jalr  $25
28992		 sw    $23,0x4C($21)    	 # Delay slot
28993		 lw    $24,0x40($29)
28994		 lw    $14,0x44($29)
28995		 lw    $15,m68k_ICount
28996		 or    $9,$0,$2
28997		 srl   $24,$24,9
28998		 addiu $24,$24,-1       	 # Move range down
28999		 andi  $24,$24,0x07     	 # Mask out lower bits
29000		 addiu $24,$24,1        	 # correct range
29001		 addu  $2,$9,$24
29002		 sltu  $16,$2,$24       	 # Set Carry
29003		 xor   $17,$9,$24
29004		 nor   $17,$0,$17
29005		 xor   $25,$2,$9
29006		 and   $17,$17,$25
29007		 srl   $17,$17,31        	 # Set Overflow
29008		 slt   $19,$2,$0        	 # Set Sign
29009		 sltiu $18,$2,1         	 # Set Zero
29010		 or    $20,$0,$16      	 # Copy Carry to X
29011		 lw    $25,0x90($21)
29012		 sw    $15,m68k_ICount
29013		 or    $5,$0,$2
29014		 or    $4,$0,$14
29015		 jalr  $25
29016		 sw    $23,0x4C($21)    	 # Delay slot
29017		 lw    $15,m68k_ICount
29018		 addiu $15,$15,-20
29019		 bgez  $15,3f
29020		 lhu   $24,0x00($23)    	 # Delay slot
29021		 j     MainExit
29022	3:
29023		 sll   $7,$24,2         	 # Delay slot
29024		 addu  $7,$7,$30
29025		 lw    $7,0x00($7)
29026		 jr    $7
29027		 nop                    	 # Delay slot
29028
29029OP0_5098:				#:
29030		 addiu $23,$23,2
29031
29032		 andi  $16,$24,0x07
29033		 sll   $16,$16,2
29034		 addu  $16,$16,$21
29035		 lw    $14,0x20($16)
29036		 addiu $25,$14,4
29037		 sw    $25,0x20($16)
29038		 lw    $25,0x84($21)
29039		 sw    $15,m68k_ICount
29040		 sw    $14,0x44($29)
29041		 sw    $24,0x40($29)
29042		 or    $4,$0,$14
29043		 jalr  $25
29044		 sw    $23,0x4C($21)    	 # Delay slot
29045		 lw    $24,0x40($29)
29046		 lw    $14,0x44($29)
29047		 lw    $15,m68k_ICount
29048		 or    $9,$0,$2
29049		 srl   $24,$24,9
29050		 addiu $24,$24,-1       	 # Move range down
29051		 andi  $24,$24,0x07     	 # Mask out lower bits
29052		 addiu $24,$24,1        	 # correct range
29053		 addu  $2,$9,$24
29054		 sltu  $16,$2,$24       	 # Set Carry
29055		 xor   $17,$9,$24
29056		 nor   $17,$0,$17
29057		 xor   $25,$2,$9
29058		 and   $17,$17,$25
29059		 srl   $17,$17,31        	 # Set Overflow
29060		 slt   $19,$2,$0        	 # Set Sign
29061		 sltiu $18,$2,1         	 # Set Zero
29062		 or    $20,$0,$16      	 # Copy Carry to X
29063		 lw    $25,0x90($21)
29064		 sw    $15,m68k_ICount
29065		 or    $5,$0,$2
29066		 or    $4,$0,$14
29067		 jalr  $25
29068		 sw    $23,0x4C($21)    	 # Delay slot
29069		 lw    $15,m68k_ICount
29070		 addiu $15,$15,-20
29071		 bgez  $15,3f
29072		 lhu   $24,0x00($23)    	 # Delay slot
29073		 j     MainExit
29074	3:
29075		 sll   $7,$24,2         	 # Delay slot
29076		 addu  $7,$7,$30
29077		 lw    $7,0x00($7)
29078		 jr    $7
29079		 nop                    	 # Delay slot
29080
29081OP0_50a0:				#:
29082		 addiu $23,$23,2
29083
29084		 andi  $16,$24,0x07
29085		 sll   $16,$16,2
29086		 addu  $16,$16,$21
29087		 lw    $14,0x20($16)
29088		 addiu $14,$14,-4
29089		 sw    $14,0x20($16)
29090		 lw    $25,0x84($21)
29091		 sw    $15,m68k_ICount
29092		 sw    $14,0x44($29)
29093		 sw    $24,0x40($29)
29094		 or    $4,$0,$14
29095		 jalr  $25
29096		 sw    $23,0x4C($21)    	 # Delay slot
29097		 lw    $24,0x40($29)
29098		 lw    $14,0x44($29)
29099		 lw    $15,m68k_ICount
29100		 or    $9,$0,$2
29101		 srl   $24,$24,9
29102		 addiu $24,$24,-1       	 # Move range down
29103		 andi  $24,$24,0x07     	 # Mask out lower bits
29104		 addiu $24,$24,1        	 # correct range
29105		 addu  $2,$9,$24
29106		 sltu  $16,$2,$24       	 # Set Carry
29107		 xor   $17,$9,$24
29108		 nor   $17,$0,$17
29109		 xor   $25,$2,$9
29110		 and   $17,$17,$25
29111		 srl   $17,$17,31        	 # Set Overflow
29112		 slt   $19,$2,$0        	 # Set Sign
29113		 sltiu $18,$2,1         	 # Set Zero
29114		 or    $20,$0,$16      	 # Copy Carry to X
29115		 lw    $25,0x90($21)
29116		 sw    $15,m68k_ICount
29117		 or    $5,$0,$2
29118		 or    $4,$0,$14
29119		 jalr  $25
29120		 sw    $23,0x4C($21)    	 # Delay slot
29121		 lw    $15,m68k_ICount
29122		 addiu $15,$15,-22
29123		 bgez  $15,3f
29124		 lhu   $24,0x00($23)    	 # Delay slot
29125		 j     MainExit
29126	3:
29127		 sll   $7,$24,2         	 # Delay slot
29128		 addu  $7,$7,$30
29129		 lw    $7,0x00($7)
29130		 jr    $7
29131		 nop                    	 # Delay slot
29132
29133OP0_50a8:				#:
29134		 addiu $23,$23,2
29135
29136		 andi  $16,$24,0x07
29137		 lh    $7,0x00($23)
29138		 sll   $16,$16,2
29139		 addu  $16,$16,$21
29140		 lw    $14,0x20($16)
29141		 addiu $23,$23,2
29142		 addu  $14,$14,$7
29143		 lw    $25,0x84($21)
29144		 sw    $15,m68k_ICount
29145		 sw    $14,0x44($29)
29146		 sw    $24,0x40($29)
29147		 or    $4,$0,$14
29148		 jalr  $25
29149		 sw    $23,0x4C($21)    	 # Delay slot
29150		 lw    $24,0x40($29)
29151		 lw    $14,0x44($29)
29152		 lw    $15,m68k_ICount
29153		 or    $9,$0,$2
29154		 srl   $24,$24,9
29155		 addiu $24,$24,-1       	 # Move range down
29156		 andi  $24,$24,0x07     	 # Mask out lower bits
29157		 addiu $24,$24,1        	 # correct range
29158		 addu  $2,$9,$24
29159		 sltu  $16,$2,$24       	 # Set Carry
29160		 xor   $17,$9,$24
29161		 nor   $17,$0,$17
29162		 xor   $25,$2,$9
29163		 and   $17,$17,$25
29164		 srl   $17,$17,31        	 # Set Overflow
29165		 slt   $19,$2,$0        	 # Set Sign
29166		 sltiu $18,$2,1         	 # Set Zero
29167		 or    $20,$0,$16      	 # Copy Carry to X
29168		 lw    $25,0x90($21)
29169		 sw    $15,m68k_ICount
29170		 or    $5,$0,$2
29171		 or    $4,$0,$14
29172		 jalr  $25
29173		 sw    $23,0x4C($21)    	 # Delay slot
29174		 lw    $15,m68k_ICount
29175		 addiu $15,$15,-24
29176		 bgez  $15,3f
29177		 lhu   $24,0x00($23)    	 # Delay slot
29178		 j     MainExit
29179	3:
29180		 sll   $7,$24,2         	 # Delay slot
29181		 addu  $7,$7,$30
29182		 lw    $7,0x00($7)
29183		 jr    $7
29184		 nop                    	 # Delay slot
29185
29186OP0_50b0:				#:
29187		 addiu $23,$23,2
29188
29189		 andi  $16,$24,0x07
29190		 sll   $16,$16,2
29191		 addu  $16,$16,$21
29192		 lw    $14,0x20($16)
29193		 lhu   $7,0x00($23)
29194		 addiu $23,$23,2
29195		 seb   $6,$7
29196		 or    $25,$0,$7
29197		 srl   $7,$7,12
29198		 andi  $25,$25,0x0800
29199		 sll   $7,$7,2
29200		 addu  $7,$7,$21
29201		 bne   $25,$0,0f
29202		 lw    $25,0x00($7)      	 # Delay slot
29203		 seh   $25,$25
29204	0:
29205		 addu  $25,$14,$25
29206		 addu  $14,$25,$6
29207		 lw    $25,0x84($21)
29208		 sw    $15,m68k_ICount
29209		 sw    $14,0x44($29)
29210		 sw    $24,0x40($29)
29211		 or    $4,$0,$14
29212		 jalr  $25
29213		 sw    $23,0x4C($21)    	 # Delay slot
29214		 lw    $24,0x40($29)
29215		 lw    $14,0x44($29)
29216		 lw    $15,m68k_ICount
29217		 or    $9,$0,$2
29218		 srl   $24,$24,9
29219		 addiu $24,$24,-1       	 # Move range down
29220		 andi  $24,$24,0x07     	 # Mask out lower bits
29221		 addiu $24,$24,1        	 # correct range
29222		 addu  $2,$9,$24
29223		 sltu  $16,$2,$24       	 # Set Carry
29224		 xor   $17,$9,$24
29225		 nor   $17,$0,$17
29226		 xor   $25,$2,$9
29227		 and   $17,$17,$25
29228		 srl   $17,$17,31        	 # Set Overflow
29229		 slt   $19,$2,$0        	 # Set Sign
29230		 sltiu $18,$2,1         	 # Set Zero
29231		 or    $20,$0,$16      	 # Copy Carry to X
29232		 lw    $25,0x90($21)
29233		 sw    $15,m68k_ICount
29234		 or    $5,$0,$2
29235		 or    $4,$0,$14
29236		 jalr  $25
29237		 sw    $23,0x4C($21)    	 # Delay slot
29238		 lw    $15,m68k_ICount
29239		 addiu $15,$15,-26
29240		 bgez  $15,3f
29241		 lhu   $24,0x00($23)    	 # Delay slot
29242		 j     MainExit
29243	3:
29244		 sll   $7,$24,2         	 # Delay slot
29245		 addu  $7,$7,$30
29246		 lw    $7,0x00($7)
29247		 jr    $7
29248		 nop                    	 # Delay slot
29249
29250OP0_50b8:				#:
29251		 addiu $23,$23,2
29252
29253		 lh    $14,0x00($23)
29254		 addiu $23,$23,2
29255		 lw    $25,0x84($21)
29256		 sw    $15,m68k_ICount
29257		 sw    $14,0x44($29)
29258		 sw    $24,0x40($29)
29259		 or    $4,$0,$14
29260		 jalr  $25
29261		 sw    $23,0x4C($21)    	 # Delay slot
29262		 lw    $24,0x40($29)
29263		 lw    $14,0x44($29)
29264		 lw    $15,m68k_ICount
29265		 or    $9,$0,$2
29266		 srl   $24,$24,9
29267		 addiu $24,$24,-1       	 # Move range down
29268		 andi  $24,$24,0x07     	 # Mask out lower bits
29269		 addiu $24,$24,1        	 # correct range
29270		 addu  $2,$9,$24
29271		 sltu  $16,$2,$24       	 # Set Carry
29272		 xor   $17,$9,$24
29273		 nor   $17,$0,$17
29274		 xor   $25,$2,$9
29275		 and   $17,$17,$25
29276		 srl   $17,$17,31        	 # Set Overflow
29277		 slt   $19,$2,$0        	 # Set Sign
29278		 sltiu $18,$2,1         	 # Set Zero
29279		 or    $20,$0,$16      	 # Copy Carry to X
29280		 lw    $25,0x90($21)
29281		 sw    $15,m68k_ICount
29282		 or    $5,$0,$2
29283		 or    $4,$0,$14
29284		 jalr  $25
29285		 sw    $23,0x4C($21)    	 # Delay slot
29286		 lw    $15,m68k_ICount
29287		 addiu $15,$15,-24
29288		 bgez  $15,3f
29289		 lhu   $24,0x00($23)    	 # Delay slot
29290		 j     MainExit
29291	3:
29292		 sll   $7,$24,2         	 # Delay slot
29293		 addu  $7,$7,$30
29294		 lw    $7,0x00($7)
29295		 jr    $7
29296		 nop                    	 # Delay slot
29297
29298OP0_50b9:				#:
29299		 addiu $23,$23,2
29300
29301		 lhu   $14,0x00($23)
29302		 lhu   $25,0x02($23)
29303		 sll   $14,$14,16
29304		 or    $14,$14,$25
29305		 addiu $23,$23,4
29306		 lw    $25,0x84($21)
29307		 sw    $15,m68k_ICount
29308		 sw    $14,0x44($29)
29309		 sw    $24,0x40($29)
29310		 or    $4,$0,$14
29311		 jalr  $25
29312		 sw    $23,0x4C($21)    	 # Delay slot
29313		 lw    $24,0x40($29)
29314		 lw    $14,0x44($29)
29315		 lw    $15,m68k_ICount
29316		 or    $9,$0,$2
29317		 srl   $24,$24,9
29318		 addiu $24,$24,-1       	 # Move range down
29319		 andi  $24,$24,0x07     	 # Mask out lower bits
29320		 addiu $24,$24,1        	 # correct range
29321		 addu  $2,$9,$24
29322		 sltu  $16,$2,$24       	 # Set Carry
29323		 xor   $17,$9,$24
29324		 nor   $17,$0,$17
29325		 xor   $25,$2,$9
29326		 and   $17,$17,$25
29327		 srl   $17,$17,31        	 # Set Overflow
29328		 slt   $19,$2,$0        	 # Set Sign
29329		 sltiu $18,$2,1         	 # Set Zero
29330		 or    $20,$0,$16      	 # Copy Carry to X
29331		 lw    $25,0x90($21)
29332		 sw    $15,m68k_ICount
29333		 or    $5,$0,$2
29334		 or    $4,$0,$14
29335		 jalr  $25
29336		 sw    $23,0x4C($21)    	 # Delay slot
29337		 lw    $15,m68k_ICount
29338		 addiu $15,$15,-28
29339		 bgez  $15,3f
29340		 lhu   $24,0x00($23)    	 # Delay slot
29341		 j     MainExit
29342	3:
29343		 sll   $7,$24,2         	 # Delay slot
29344		 addu  $7,$7,$30
29345		 lw    $7,0x00($7)
29346		 jr    $7
29347		 nop                    	 # Delay slot
29348
29349OP0_50c0:				#:
29350		 addiu $23,$23,2
29351
29352		 andi  $24,$24,0x07
29353		 addiu $2,$0,-1
29354		 sll   $24,$24,2
29355		 addu  $24,$24,$21
29356		 sb    $2,0x00($24)
29357		 andi  $2,$2,0x02
29358		 addiu $15,$15,-4
29359		 subu  $15,$15,$2
29360		 bgez  $15,3f
29361		 lhu   $24,0x00($23)    	 # Delay slot
29362		 j     MainExit
29363	3:
29364		 sll   $7,$24,2         	 # Delay slot
29365		 addu  $7,$7,$30
29366		 lw    $7,0x00($7)
29367		 jr    $7
29368		 nop                    	 # Delay slot
29369
29370OP0_50c8:				#:
29371		 bgez  $0,1f
29372		 andi  $24,$24,0x07     	 # Delay slot
29373		 sll   $24,$24,2
29374		 addu  $24,$24,$21
29375		 lhu   $8,0x00($24)
29376		 addiu $9,$8,-1
29377		 beq   $8,$0,9f         	 # Is it -1
29378		 sh    $9,0x00($24)     	 # Delay slot
29379
29380		 addiu $23,$23,2
29381
29382		 lh    $2,0x00($23)
29383		 addu  $23,$23,$2
29384		 addiu $15,$15,-10
29385		 bgez  $15,3f
29386		 lhu   $24,0x00($23)    	 # Delay slot
29387		 j     MainExit
29388	3:
29389		 sll   $7,$24,2         	 # Delay slot
29390		 addu  $7,$7,$30
29391		 lw    $7,0x00($7)
29392		 jr    $7
29393		 nop                    	 # Delay slot
29394
29395	9:
29396	1:
29397		 addiu $23,$23,4
29398
29399		 addiu $15,$15,-12
29400		 bgez  $15,3f
29401		 lhu   $24,0x00($23)    	 # Delay slot
29402		 j     MainExit
29403	3:
29404		 sll   $7,$24,2         	 # Delay slot
29405		 addu  $7,$7,$30
29406		 lw    $7,0x00($7)
29407		 jr    $7
29408		 nop                    	 # Delay slot
29409
29410OP0_50d0:				#:
29411		 addiu $23,$23,2
29412
29413		 andi  $24,$24,0x07
29414		 sll   $24,$24,2
29415		 addu  $24,$24,$21
29416		 lw    $14,0x20($24)
29417		 addiu $2,$0,-1
29418		 lw    $25,0x88($21)
29419		 sw    $15,m68k_ICount
29420		 or    $5,$0,$2
29421		 or    $4,$0,$14
29422		 jalr  $25
29423		 sw    $23,0x4C($21)    	 # Delay slot
29424		 lw    $15,m68k_ICount
29425		 addiu $15,$15,-12
29426		 bgez  $15,3f
29427		 lhu   $24,0x00($23)    	 # Delay slot
29428		 j     MainExit
29429	3:
29430		 sll   $7,$24,2         	 # Delay slot
29431		 addu  $7,$7,$30
29432		 lw    $7,0x00($7)
29433		 jr    $7
29434		 nop                    	 # Delay slot
29435
29436OP0_50d8:				#:
29437		 addiu $23,$23,2
29438
29439		 andi  $24,$24,0x07
29440		 sll   $24,$24,2
29441		 addu  $24,$24,$21
29442		 lw    $14,0x20($24)
29443		 addiu $25,$14,1
29444		 sw    $25,0x20($24)
29445		 addiu $2,$0,-1
29446		 lw    $25,0x88($21)
29447		 sw    $15,m68k_ICount
29448		 or    $5,$0,$2
29449		 or    $4,$0,$14
29450		 jalr  $25
29451		 sw    $23,0x4C($21)    	 # Delay slot
29452		 lw    $15,m68k_ICount
29453		 addiu $15,$15,-12
29454		 bgez  $15,3f
29455		 lhu   $24,0x00($23)    	 # Delay slot
29456		 j     MainExit
29457	3:
29458		 sll   $7,$24,2         	 # Delay slot
29459		 addu  $7,$7,$30
29460		 lw    $7,0x00($7)
29461		 jr    $7
29462		 nop                    	 # Delay slot
29463
29464OP0_50df:				#:
29465		 addiu $23,$23,2
29466
29467		 lw    $14,0x3C($21)    	 # Get A7
29468		 addiu $25,$14,2
29469		 sw    $25,0x3C($21)
29470		 addiu $2,$0,-1
29471		 lw    $25,0x88($21)
29472		 sw    $15,m68k_ICount
29473		 or    $5,$0,$2
29474		 or    $4,$0,$14
29475		 jalr  $25
29476		 sw    $23,0x4C($21)    	 # Delay slot
29477		 lw    $15,m68k_ICount
29478		 addiu $15,$15,-12
29479		 bgez  $15,3f
29480		 lhu   $24,0x00($23)    	 # Delay slot
29481		 j     MainExit
29482	3:
29483		 sll   $7,$24,2         	 # Delay slot
29484		 addu  $7,$7,$30
29485		 lw    $7,0x00($7)
29486		 jr    $7
29487		 nop                    	 # Delay slot
29488
29489OP0_50e0:				#:
29490		 addiu $23,$23,2
29491
29492		 andi  $24,$24,0x07
29493		 sll   $24,$24,2
29494		 addu  $24,$24,$21
29495		 lw    $14,0x20($24)
29496		 addiu $14,$14,-1
29497		 sw    $14,0x20($24)
29498		 addiu $2,$0,-1
29499		 lw    $25,0x88($21)
29500		 sw    $15,m68k_ICount
29501		 or    $5,$0,$2
29502		 or    $4,$0,$14
29503		 jalr  $25
29504		 sw    $23,0x4C($21)    	 # Delay slot
29505		 lw    $15,m68k_ICount
29506		 addiu $15,$15,-14
29507		 bgez  $15,3f
29508		 lhu   $24,0x00($23)    	 # Delay slot
29509		 j     MainExit
29510	3:
29511		 sll   $7,$24,2         	 # Delay slot
29512		 addu  $7,$7,$30
29513		 lw    $7,0x00($7)
29514		 jr    $7
29515		 nop                    	 # Delay slot
29516
29517OP0_50e7:				#:
29518		 addiu $23,$23,2
29519
29520		 lw    $14,0x3C($21)    	 # Get A7
29521		 addiu $14,$14,-2
29522		 sw    $14,0x3C($21)
29523		 addiu $2,$0,-1
29524		 lw    $25,0x88($21)
29525		 sw    $15,m68k_ICount
29526		 or    $5,$0,$2
29527		 or    $4,$0,$14
29528		 jalr  $25
29529		 sw    $23,0x4C($21)    	 # Delay slot
29530		 lw    $15,m68k_ICount
29531		 addiu $15,$15,-14
29532		 bgez  $15,3f
29533		 lhu   $24,0x00($23)    	 # Delay slot
29534		 j     MainExit
29535	3:
29536		 sll   $7,$24,2         	 # Delay slot
29537		 addu  $7,$7,$30
29538		 lw    $7,0x00($7)
29539		 jr    $7
29540		 nop                    	 # Delay slot
29541
29542OP0_50e8:				#:
29543		 addiu $23,$23,2
29544
29545		 andi  $24,$24,0x07
29546		 lh    $7,0x00($23)
29547		 sll   $24,$24,2
29548		 addu  $24,$24,$21
29549		 lw    $14,0x20($24)
29550		 addiu $23,$23,2
29551		 addu  $14,$14,$7
29552		 addiu $2,$0,-1
29553		 lw    $25,0x88($21)
29554		 sw    $15,m68k_ICount
29555		 or    $5,$0,$2
29556		 or    $4,$0,$14
29557		 jalr  $25
29558		 sw    $23,0x4C($21)    	 # Delay slot
29559		 lw    $15,m68k_ICount
29560		 addiu $15,$15,-16
29561		 bgez  $15,3f
29562		 lhu   $24,0x00($23)    	 # Delay slot
29563		 j     MainExit
29564	3:
29565		 sll   $7,$24,2         	 # Delay slot
29566		 addu  $7,$7,$30
29567		 lw    $7,0x00($7)
29568		 jr    $7
29569		 nop                    	 # Delay slot
29570
29571OP0_50f0:				#:
29572		 addiu $23,$23,2
29573
29574		 andi  $24,$24,0x07
29575		 sll   $24,$24,2
29576		 addu  $24,$24,$21
29577		 lw    $14,0x20($24)
29578		 lhu   $7,0x00($23)
29579		 addiu $23,$23,2
29580		 seb   $6,$7
29581		 or    $25,$0,$7
29582		 srl   $7,$7,12
29583		 andi  $25,$25,0x0800
29584		 sll   $7,$7,2
29585		 addu  $7,$7,$21
29586		 bne   $25,$0,0f
29587		 lw    $25,0x00($7)      	 # Delay slot
29588		 seh   $25,$25
29589	0:
29590		 addu  $25,$14,$25
29591		 addu  $14,$25,$6
29592		 addiu $2,$0,-1
29593		 lw    $25,0x88($21)
29594		 sw    $15,m68k_ICount
29595		 or    $5,$0,$2
29596		 or    $4,$0,$14
29597		 jalr  $25
29598		 sw    $23,0x4C($21)    	 # Delay slot
29599		 lw    $15,m68k_ICount
29600		 addiu $15,$15,-18
29601		 bgez  $15,3f
29602		 lhu   $24,0x00($23)    	 # Delay slot
29603		 j     MainExit
29604	3:
29605		 sll   $7,$24,2         	 # Delay slot
29606		 addu  $7,$7,$30
29607		 lw    $7,0x00($7)
29608		 jr    $7
29609		 nop                    	 # Delay slot
29610
29611OP0_50f8:				#:
29612		 addiu $23,$23,2
29613
29614		 lh    $14,0x00($23)
29615		 addiu $23,$23,2
29616		 addiu $2,$0,-1
29617		 lw    $25,0x88($21)
29618		 sw    $15,m68k_ICount
29619		 or    $5,$0,$2
29620		 or    $4,$0,$14
29621		 jalr  $25
29622		 sw    $23,0x4C($21)    	 # Delay slot
29623		 lw    $15,m68k_ICount
29624		 addiu $15,$15,-16
29625		 bgez  $15,3f
29626		 lhu   $24,0x00($23)    	 # Delay slot
29627		 j     MainExit
29628	3:
29629		 sll   $7,$24,2         	 # Delay slot
29630		 addu  $7,$7,$30
29631		 lw    $7,0x00($7)
29632		 jr    $7
29633		 nop                    	 # Delay slot
29634
29635OP0_50f9:				#:
29636		 addiu $23,$23,2
29637
29638		 lhu   $14,0x00($23)
29639		 lhu   $25,0x02($23)
29640		 sll   $14,$14,16
29641		 or    $14,$14,$25
29642		 addiu $23,$23,4
29643		 addiu $2,$0,-1
29644		 lw    $25,0x88($21)
29645		 sw    $15,m68k_ICount
29646		 or    $5,$0,$2
29647		 or    $4,$0,$14
29648		 jalr  $25
29649		 sw    $23,0x4C($21)    	 # Delay slot
29650		 lw    $15,m68k_ICount
29651		 addiu $15,$15,-20
29652		 bgez  $15,3f
29653		 lhu   $24,0x00($23)    	 # Delay slot
29654		 j     MainExit
29655	3:
29656		 sll   $7,$24,2         	 # Delay slot
29657		 addu  $7,$7,$30
29658		 lw    $7,0x00($7)
29659		 jr    $7
29660		 nop                    	 # Delay slot
29661
29662OP0_5100:				#:
29663		 addiu $23,$23,2
29664
29665		 andi  $16,$24,0x07
29666		 sll   $16,$16,2
29667		 addu  $16,$16,$21
29668		 lb    $9,0x00($16)
29669		 srl   $24,$24,9
29670		 addiu $24,$24,-1       	 # Move range down
29671		 andi  $24,$24,0x07     	 # Mask out lower bits
29672		 addiu $24,$24,1        	 # correct range
29673		 subu  $2,$9,$24
29674		 sb    $2,0x00($16)
29675		 sltu  $16,$9,$24       	 # Set Carry
29676		 xor   $17,$9,$24
29677		 xor   $25,$2,$9
29678		 and   $17,$17,$25
29679		 srl   $17,$17,7
29680		 andi  $17,$17,0x01     	 # Set Overflow
29681		 seb  $25,$2
29682		 slt   $19,$25,$0        	 # Set Sign
29683		 sltiu $18,$25,1         	 # Set Zero
29684		 or    $20,$0,$16      	 # Copy Carry to X
29685		 addiu $15,$15,-4
29686		 bgez  $15,3f
29687		 lhu   $24,0x00($23)    	 # Delay slot
29688		 j     MainExit
29689	3:
29690		 sll   $7,$24,2         	 # Delay slot
29691		 addu  $7,$7,$30
29692		 lw    $7,0x00($7)
29693		 jr    $7
29694		 nop                    	 # Delay slot
29695
29696OP0_5188:				#:
29697		 addiu $23,$23,2
29698
29699		 andi  $8,$24,0x07
29700		 sll   $8,$8,2
29701		 addu  $8,$8,$21
29702		 lw    $9,0x20($8)
29703		 srl   $24,$24,9
29704		 addiu $24,$24,-1       	 # Move range down
29705		 andi  $24,$24,0x07     	 # Mask out lower bits
29706		 addiu $24,$24,1        	 # correct range
29707		 subu  $2,$9,$24
29708		 sw    $2,0x20($8)
29709		 addiu $15,$15,-8
29710		 bgez  $15,3f
29711		 lhu   $24,0x00($23)    	 # Delay slot
29712		 j     MainExit
29713	3:
29714		 sll   $7,$24,2         	 # Delay slot
29715		 addu  $7,$7,$30
29716		 lw    $7,0x00($7)
29717		 jr    $7
29718		 nop                    	 # Delay slot
29719
29720OP0_5110:				#:
29721		 addiu $23,$23,2
29722
29723		 andi  $16,$24,0x07
29724		 sll   $16,$16,2
29725		 addu  $16,$16,$21
29726		 lw    $14,0x20($16)
29727		 lw    $25,0x7C($21)
29728		 sw    $15,m68k_ICount
29729		 sw    $14,0x44($29)
29730		 sw    $24,0x40($29)
29731		 or    $4,$0,$14
29732		 jalr  $25
29733		 sw    $23,0x4C($21)    	 # Delay slot
29734		 lw    $24,0x40($29)
29735		 lw    $14,0x44($29)
29736		 lw    $15,m68k_ICount
29737		 seb   $9,$2
29738		 srl   $24,$24,9
29739		 addiu $24,$24,-1       	 # Move range down
29740		 andi  $24,$24,0x07     	 # Mask out lower bits
29741		 addiu $24,$24,1        	 # correct range
29742		 subu  $2,$9,$24
29743		 sltu  $16,$9,$24       	 # Set Carry
29744		 xor   $17,$9,$24
29745		 xor   $25,$2,$9
29746		 and   $17,$17,$25
29747		 srl   $17,$17,7
29748		 andi  $17,$17,0x01     	 # Set Overflow
29749		 seb  $25,$2
29750		 slt   $19,$25,$0        	 # Set Sign
29751		 sltiu $18,$25,1         	 # Set Zero
29752		 or    $20,$0,$16      	 # Copy Carry to X
29753		 lw    $25,0x88($21)
29754		 sw    $15,m68k_ICount
29755		 or    $5,$0,$2
29756		 or    $4,$0,$14
29757		 jalr  $25
29758		 sw    $23,0x4C($21)    	 # Delay slot
29759		 lw    $15,m68k_ICount
29760		 addiu $15,$15,-12
29761		 bgez  $15,3f
29762		 lhu   $24,0x00($23)    	 # Delay slot
29763		 j     MainExit
29764	3:
29765		 sll   $7,$24,2         	 # Delay slot
29766		 addu  $7,$7,$30
29767		 lw    $7,0x00($7)
29768		 jr    $7
29769		 nop                    	 # Delay slot
29770
29771OP0_5118:				#:
29772		 addiu $23,$23,2
29773
29774		 andi  $16,$24,0x07
29775		 sll   $16,$16,2
29776		 addu  $16,$16,$21
29777		 lw    $14,0x20($16)
29778		 addiu $25,$14,1
29779		 sw    $25,0x20($16)
29780		 lw    $25,0x7C($21)
29781		 sw    $15,m68k_ICount
29782		 sw    $14,0x44($29)
29783		 sw    $24,0x40($29)
29784		 or    $4,$0,$14
29785		 jalr  $25
29786		 sw    $23,0x4C($21)    	 # Delay slot
29787		 lw    $24,0x40($29)
29788		 lw    $14,0x44($29)
29789		 lw    $15,m68k_ICount
29790		 seb   $9,$2
29791		 srl   $24,$24,9
29792		 addiu $24,$24,-1       	 # Move range down
29793		 andi  $24,$24,0x07     	 # Mask out lower bits
29794		 addiu $24,$24,1        	 # correct range
29795		 subu  $2,$9,$24
29796		 sltu  $16,$9,$24       	 # Set Carry
29797		 xor   $17,$9,$24
29798		 xor   $25,$2,$9
29799		 and   $17,$17,$25
29800		 srl   $17,$17,7
29801		 andi  $17,$17,0x01     	 # Set Overflow
29802		 seb  $25,$2
29803		 slt   $19,$25,$0        	 # Set Sign
29804		 sltiu $18,$25,1         	 # Set Zero
29805		 or    $20,$0,$16      	 # Copy Carry to X
29806		 lw    $25,0x88($21)
29807		 sw    $15,m68k_ICount
29808		 or    $5,$0,$2
29809		 or    $4,$0,$14
29810		 jalr  $25
29811		 sw    $23,0x4C($21)    	 # Delay slot
29812		 lw    $15,m68k_ICount
29813		 addiu $15,$15,-12
29814		 bgez  $15,3f
29815		 lhu   $24,0x00($23)    	 # Delay slot
29816		 j     MainExit
29817	3:
29818		 sll   $7,$24,2         	 # Delay slot
29819		 addu  $7,$7,$30
29820		 lw    $7,0x00($7)
29821		 jr    $7
29822		 nop                    	 # Delay slot
29823
29824OP0_511f:				#:
29825		 addiu $23,$23,2
29826
29827		 lw    $14,0x3C($21)    	 # Get A7
29828		 addiu $25,$14,2
29829		 sw    $25,0x3C($21)
29830		 lw    $25,0x7C($21)
29831		 sw    $15,m68k_ICount
29832		 sw    $14,0x44($29)
29833		 sw    $24,0x40($29)
29834		 or    $4,$0,$14
29835		 jalr  $25
29836		 sw    $23,0x4C($21)    	 # Delay slot
29837		 lw    $24,0x40($29)
29838		 lw    $14,0x44($29)
29839		 lw    $15,m68k_ICount
29840		 seb   $9,$2
29841		 srl   $24,$24,9
29842		 addiu $24,$24,-1       	 # Move range down
29843		 andi  $24,$24,0x07     	 # Mask out lower bits
29844		 addiu $24,$24,1        	 # correct range
29845		 subu  $2,$9,$24
29846		 sltu  $16,$9,$24       	 # Set Carry
29847		 xor   $17,$9,$24
29848		 xor   $25,$2,$9
29849		 and   $17,$17,$25
29850		 srl   $17,$17,7
29851		 andi  $17,$17,0x01     	 # Set Overflow
29852		 seb  $25,$2
29853		 slt   $19,$25,$0        	 # Set Sign
29854		 sltiu $18,$25,1         	 # Set Zero
29855		 or    $20,$0,$16      	 # Copy Carry to X
29856		 lw    $25,0x88($21)
29857		 sw    $15,m68k_ICount
29858		 or    $5,$0,$2
29859		 or    $4,$0,$14
29860		 jalr  $25
29861		 sw    $23,0x4C($21)    	 # Delay slot
29862		 lw    $15,m68k_ICount
29863		 addiu $15,$15,-12
29864		 bgez  $15,3f
29865		 lhu   $24,0x00($23)    	 # Delay slot
29866		 j     MainExit
29867	3:
29868		 sll   $7,$24,2         	 # Delay slot
29869		 addu  $7,$7,$30
29870		 lw    $7,0x00($7)
29871		 jr    $7
29872		 nop                    	 # Delay slot
29873
29874OP0_5120:				#:
29875		 addiu $23,$23,2
29876
29877		 andi  $16,$24,0x07
29878		 sll   $16,$16,2
29879		 addu  $16,$16,$21
29880		 lw    $14,0x20($16)
29881		 addiu $14,$14,-1
29882		 sw    $14,0x20($16)
29883		 lw    $25,0x7C($21)
29884		 sw    $15,m68k_ICount
29885		 sw    $14,0x44($29)
29886		 sw    $24,0x40($29)
29887		 or    $4,$0,$14
29888		 jalr  $25
29889		 sw    $23,0x4C($21)    	 # Delay slot
29890		 lw    $24,0x40($29)
29891		 lw    $14,0x44($29)
29892		 lw    $15,m68k_ICount
29893		 seb   $9,$2
29894		 srl   $24,$24,9
29895		 addiu $24,$24,-1       	 # Move range down
29896		 andi  $24,$24,0x07     	 # Mask out lower bits
29897		 addiu $24,$24,1        	 # correct range
29898		 subu  $2,$9,$24
29899		 sltu  $16,$9,$24       	 # Set Carry
29900		 xor   $17,$9,$24
29901		 xor   $25,$2,$9
29902		 and   $17,$17,$25
29903		 srl   $17,$17,7
29904		 andi  $17,$17,0x01     	 # Set Overflow
29905		 seb  $25,$2
29906		 slt   $19,$25,$0        	 # Set Sign
29907		 sltiu $18,$25,1         	 # Set Zero
29908		 or    $20,$0,$16      	 # Copy Carry to X
29909		 lw    $25,0x88($21)
29910		 sw    $15,m68k_ICount
29911		 or    $5,$0,$2
29912		 or    $4,$0,$14
29913		 jalr  $25
29914		 sw    $23,0x4C($21)    	 # Delay slot
29915		 lw    $15,m68k_ICount
29916		 addiu $15,$15,-14
29917		 bgez  $15,3f
29918		 lhu   $24,0x00($23)    	 # Delay slot
29919		 j     MainExit
29920	3:
29921		 sll   $7,$24,2         	 # Delay slot
29922		 addu  $7,$7,$30
29923		 lw    $7,0x00($7)
29924		 jr    $7
29925		 nop                    	 # Delay slot
29926
29927OP0_5127:				#:
29928		 addiu $23,$23,2
29929
29930		 lw    $14,0x3C($21)    	 # Get A7
29931		 addiu $14,$14,-2
29932		 sw    $14,0x3C($21)
29933		 lw    $25,0x7C($21)
29934		 sw    $15,m68k_ICount
29935		 sw    $14,0x44($29)
29936		 sw    $24,0x40($29)
29937		 or    $4,$0,$14
29938		 jalr  $25
29939		 sw    $23,0x4C($21)    	 # Delay slot
29940		 lw    $24,0x40($29)
29941		 lw    $14,0x44($29)
29942		 lw    $15,m68k_ICount
29943		 seb   $9,$2
29944		 srl   $24,$24,9
29945		 addiu $24,$24,-1       	 # Move range down
29946		 andi  $24,$24,0x07     	 # Mask out lower bits
29947		 addiu $24,$24,1        	 # correct range
29948		 subu  $2,$9,$24
29949		 sltu  $16,$9,$24       	 # Set Carry
29950		 xor   $17,$9,$24
29951		 xor   $25,$2,$9
29952		 and   $17,$17,$25
29953		 srl   $17,$17,7
29954		 andi  $17,$17,0x01     	 # Set Overflow
29955		 seb  $25,$2
29956		 slt   $19,$25,$0        	 # Set Sign
29957		 sltiu $18,$25,1         	 # Set Zero
29958		 or    $20,$0,$16      	 # Copy Carry to X
29959		 lw    $25,0x88($21)
29960		 sw    $15,m68k_ICount
29961		 or    $5,$0,$2
29962		 or    $4,$0,$14
29963		 jalr  $25
29964		 sw    $23,0x4C($21)    	 # Delay slot
29965		 lw    $15,m68k_ICount
29966		 addiu $15,$15,-14
29967		 bgez  $15,3f
29968		 lhu   $24,0x00($23)    	 # Delay slot
29969		 j     MainExit
29970	3:
29971		 sll   $7,$24,2         	 # Delay slot
29972		 addu  $7,$7,$30
29973		 lw    $7,0x00($7)
29974		 jr    $7
29975		 nop                    	 # Delay slot
29976
29977OP0_5128:				#:
29978		 addiu $23,$23,2
29979
29980		 andi  $16,$24,0x07
29981		 lh    $7,0x00($23)
29982		 sll   $16,$16,2
29983		 addu  $16,$16,$21
29984		 lw    $14,0x20($16)
29985		 addiu $23,$23,2
29986		 addu  $14,$14,$7
29987		 lw    $25,0x7C($21)
29988		 sw    $15,m68k_ICount
29989		 sw    $14,0x44($29)
29990		 sw    $24,0x40($29)
29991		 or    $4,$0,$14
29992		 jalr  $25
29993		 sw    $23,0x4C($21)    	 # Delay slot
29994		 lw    $24,0x40($29)
29995		 lw    $14,0x44($29)
29996		 lw    $15,m68k_ICount
29997		 seb   $9,$2
29998		 srl   $24,$24,9
29999		 addiu $24,$24,-1       	 # Move range down
30000		 andi  $24,$24,0x07     	 # Mask out lower bits
30001		 addiu $24,$24,1        	 # correct range
30002		 subu  $2,$9,$24
30003		 sltu  $16,$9,$24       	 # Set Carry
30004		 xor   $17,$9,$24
30005		 xor   $25,$2,$9
30006		 and   $17,$17,$25
30007		 srl   $17,$17,7
30008		 andi  $17,$17,0x01     	 # Set Overflow
30009		 seb  $25,$2
30010		 slt   $19,$25,$0        	 # Set Sign
30011		 sltiu $18,$25,1         	 # Set Zero
30012		 or    $20,$0,$16      	 # Copy Carry to X
30013		 lw    $25,0x88($21)
30014		 sw    $15,m68k_ICount
30015		 or    $5,$0,$2
30016		 or    $4,$0,$14
30017		 jalr  $25
30018		 sw    $23,0x4C($21)    	 # Delay slot
30019		 lw    $15,m68k_ICount
30020		 addiu $15,$15,-16
30021		 bgez  $15,3f
30022		 lhu   $24,0x00($23)    	 # Delay slot
30023		 j     MainExit
30024	3:
30025		 sll   $7,$24,2         	 # Delay slot
30026		 addu  $7,$7,$30
30027		 lw    $7,0x00($7)
30028		 jr    $7
30029		 nop                    	 # Delay slot
30030
30031OP0_5130:				#:
30032		 addiu $23,$23,2
30033
30034		 andi  $16,$24,0x07
30035		 sll   $16,$16,2
30036		 addu  $16,$16,$21
30037		 lw    $14,0x20($16)
30038		 lhu   $7,0x00($23)
30039		 addiu $23,$23,2
30040		 seb   $6,$7
30041		 or    $25,$0,$7
30042		 srl   $7,$7,12
30043		 andi  $25,$25,0x0800
30044		 sll   $7,$7,2
30045		 addu  $7,$7,$21
30046		 bne   $25,$0,0f
30047		 lw    $25,0x00($7)      	 # Delay slot
30048		 seh   $25,$25
30049	0:
30050		 addu  $25,$14,$25
30051		 addu  $14,$25,$6
30052		 lw    $25,0x7C($21)
30053		 sw    $15,m68k_ICount
30054		 sw    $14,0x44($29)
30055		 sw    $24,0x40($29)
30056		 or    $4,$0,$14
30057		 jalr  $25
30058		 sw    $23,0x4C($21)    	 # Delay slot
30059		 lw    $24,0x40($29)
30060		 lw    $14,0x44($29)
30061		 lw    $15,m68k_ICount
30062		 seb   $9,$2
30063		 srl   $24,$24,9
30064		 addiu $24,$24,-1       	 # Move range down
30065		 andi  $24,$24,0x07     	 # Mask out lower bits
30066		 addiu $24,$24,1        	 # correct range
30067		 subu  $2,$9,$24
30068		 sltu  $16,$9,$24       	 # Set Carry
30069		 xor   $17,$9,$24
30070		 xor   $25,$2,$9
30071		 and   $17,$17,$25
30072		 srl   $17,$17,7
30073		 andi  $17,$17,0x01     	 # Set Overflow
30074		 seb  $25,$2
30075		 slt   $19,$25,$0        	 # Set Sign
30076		 sltiu $18,$25,1         	 # Set Zero
30077		 or    $20,$0,$16      	 # Copy Carry to X
30078		 lw    $25,0x88($21)
30079		 sw    $15,m68k_ICount
30080		 or    $5,$0,$2
30081		 or    $4,$0,$14
30082		 jalr  $25
30083		 sw    $23,0x4C($21)    	 # Delay slot
30084		 lw    $15,m68k_ICount
30085		 addiu $15,$15,-18
30086		 bgez  $15,3f
30087		 lhu   $24,0x00($23)    	 # Delay slot
30088		 j     MainExit
30089	3:
30090		 sll   $7,$24,2         	 # Delay slot
30091		 addu  $7,$7,$30
30092		 lw    $7,0x00($7)
30093		 jr    $7
30094		 nop                    	 # Delay slot
30095
30096OP0_5138:				#:
30097		 addiu $23,$23,2
30098
30099		 lh    $14,0x00($23)
30100		 addiu $23,$23,2
30101		 lw    $25,0x7C($21)
30102		 sw    $15,m68k_ICount
30103		 sw    $14,0x44($29)
30104		 sw    $24,0x40($29)
30105		 or    $4,$0,$14
30106		 jalr  $25
30107		 sw    $23,0x4C($21)    	 # Delay slot
30108		 lw    $24,0x40($29)
30109		 lw    $14,0x44($29)
30110		 lw    $15,m68k_ICount
30111		 seb   $9,$2
30112		 srl   $24,$24,9
30113		 addiu $24,$24,-1       	 # Move range down
30114		 andi  $24,$24,0x07     	 # Mask out lower bits
30115		 addiu $24,$24,1        	 # correct range
30116		 subu  $2,$9,$24
30117		 sltu  $16,$9,$24       	 # Set Carry
30118		 xor   $17,$9,$24
30119		 xor   $25,$2,$9
30120		 and   $17,$17,$25
30121		 srl   $17,$17,7
30122		 andi  $17,$17,0x01     	 # Set Overflow
30123		 seb  $25,$2
30124		 slt   $19,$25,$0        	 # Set Sign
30125		 sltiu $18,$25,1         	 # Set Zero
30126		 or    $20,$0,$16      	 # Copy Carry to X
30127		 lw    $25,0x88($21)
30128		 sw    $15,m68k_ICount
30129		 or    $5,$0,$2
30130		 or    $4,$0,$14
30131		 jalr  $25
30132		 sw    $23,0x4C($21)    	 # Delay slot
30133		 lw    $15,m68k_ICount
30134		 addiu $15,$15,-16
30135		 bgez  $15,3f
30136		 lhu   $24,0x00($23)    	 # Delay slot
30137		 j     MainExit
30138	3:
30139		 sll   $7,$24,2         	 # Delay slot
30140		 addu  $7,$7,$30
30141		 lw    $7,0x00($7)
30142		 jr    $7
30143		 nop                    	 # Delay slot
30144
30145OP0_5139:				#:
30146		 addiu $23,$23,2
30147
30148		 lhu   $14,0x00($23)
30149		 lhu   $25,0x02($23)
30150		 sll   $14,$14,16
30151		 or    $14,$14,$25
30152		 addiu $23,$23,4
30153		 lw    $25,0x7C($21)
30154		 sw    $15,m68k_ICount
30155		 sw    $14,0x44($29)
30156		 sw    $24,0x40($29)
30157		 or    $4,$0,$14
30158		 jalr  $25
30159		 sw    $23,0x4C($21)    	 # Delay slot
30160		 lw    $24,0x40($29)
30161		 lw    $14,0x44($29)
30162		 lw    $15,m68k_ICount
30163		 seb   $9,$2
30164		 srl   $24,$24,9
30165		 addiu $24,$24,-1       	 # Move range down
30166		 andi  $24,$24,0x07     	 # Mask out lower bits
30167		 addiu $24,$24,1        	 # correct range
30168		 subu  $2,$9,$24
30169		 sltu  $16,$9,$24       	 # Set Carry
30170		 xor   $17,$9,$24
30171		 xor   $25,$2,$9
30172		 and   $17,$17,$25
30173		 srl   $17,$17,7
30174		 andi  $17,$17,0x01     	 # Set Overflow
30175		 seb  $25,$2
30176		 slt   $19,$25,$0        	 # Set Sign
30177		 sltiu $18,$25,1         	 # Set Zero
30178		 or    $20,$0,$16      	 # Copy Carry to X
30179		 lw    $25,0x88($21)
30180		 sw    $15,m68k_ICount
30181		 or    $5,$0,$2
30182		 or    $4,$0,$14
30183		 jalr  $25
30184		 sw    $23,0x4C($21)    	 # Delay slot
30185		 lw    $15,m68k_ICount
30186		 addiu $15,$15,-20
30187		 bgez  $15,3f
30188		 lhu   $24,0x00($23)    	 # Delay slot
30189		 j     MainExit
30190	3:
30191		 sll   $7,$24,2         	 # Delay slot
30192		 addu  $7,$7,$30
30193		 lw    $7,0x00($7)
30194		 jr    $7
30195		 nop                    	 # Delay slot
30196
30197OP0_5140:				#:
30198		 addiu $23,$23,2
30199
30200		 andi  $16,$24,0x07
30201		 sll   $16,$16,2
30202		 addu  $16,$16,$21
30203		 lh    $9,0x00($16)
30204		 srl   $24,$24,9
30205		 addiu $24,$24,-1       	 # Move range down
30206		 andi  $24,$24,0x07     	 # Mask out lower bits
30207		 addiu $24,$24,1        	 # correct range
30208		 subu  $2,$9,$24
30209		 sh    $2,0x00($16)
30210		 sltu  $16,$9,$24       	 # Set Carry
30211		 xor   $17,$9,$24
30212		 xor   $25,$2,$9
30213		 and   $17,$17,$25
30214		 srl   $17,$17,15
30215		 andi  $17,$17,0x01     	 # Set Overflow
30216		 seh  $25,$2
30217		 slt   $19,$25,$0        	 # Set Sign
30218		 sltiu $18,$25,1         	 # Set Zero
30219		 or    $20,$0,$16      	 # Copy Carry to X
30220		 addiu $15,$15,-4
30221		 bgez  $15,3f
30222		 lhu   $24,0x00($23)    	 # Delay slot
30223		 j     MainExit
30224	3:
30225		 sll   $7,$24,2         	 # Delay slot
30226		 addu  $7,$7,$30
30227		 lw    $7,0x00($7)
30228		 jr    $7
30229		 nop                    	 # Delay slot
30230
30231OP0_5150:				#:
30232		 addiu $23,$23,2
30233
30234		 andi  $16,$24,0x07
30235		 sll   $16,$16,2
30236		 addu  $16,$16,$21
30237		 lw    $14,0x20($16)
30238		 lw    $25,0x80($21)
30239		 sw    $15,m68k_ICount
30240		 sw    $14,0x44($29)
30241		 sw    $24,0x40($29)
30242		 or    $4,$0,$14
30243		 jalr  $25
30244		 sw    $23,0x4C($21)    	 # Delay slot
30245		 lw    $24,0x40($29)
30246		 lw    $14,0x44($29)
30247		 lw    $15,m68k_ICount
30248		 seh   $9,$2
30249		 srl   $24,$24,9
30250		 addiu $24,$24,-1       	 # Move range down
30251		 andi  $24,$24,0x07     	 # Mask out lower bits
30252		 addiu $24,$24,1        	 # correct range
30253		 subu  $2,$9,$24
30254		 sltu  $16,$9,$24       	 # Set Carry
30255		 xor   $17,$9,$24
30256		 xor   $25,$2,$9
30257		 and   $17,$17,$25
30258		 srl   $17,$17,15
30259		 andi  $17,$17,0x01     	 # Set Overflow
30260		 seh  $25,$2
30261		 slt   $19,$25,$0        	 # Set Sign
30262		 sltiu $18,$25,1         	 # Set Zero
30263		 or    $20,$0,$16      	 # Copy Carry to X
30264		 lw    $25,0x8C($21)
30265		 sw    $15,m68k_ICount
30266		 or    $5,$0,$2
30267		 or    $4,$0,$14
30268		 jalr  $25
30269		 sw    $23,0x4C($21)    	 # Delay slot
30270		 lw    $15,m68k_ICount
30271		 addiu $15,$15,-12
30272		 bgez  $15,3f
30273		 lhu   $24,0x00($23)    	 # Delay slot
30274		 j     MainExit
30275	3:
30276		 sll   $7,$24,2         	 # Delay slot
30277		 addu  $7,$7,$30
30278		 lw    $7,0x00($7)
30279		 jr    $7
30280		 nop                    	 # Delay slot
30281
30282OP0_5158:				#:
30283		 addiu $23,$23,2
30284
30285		 andi  $16,$24,0x07
30286		 sll   $16,$16,2
30287		 addu  $16,$16,$21
30288		 lw    $14,0x20($16)
30289		 addiu $25,$14,2
30290		 sw    $25,0x20($16)
30291		 lw    $25,0x80($21)
30292		 sw    $15,m68k_ICount
30293		 sw    $14,0x44($29)
30294		 sw    $24,0x40($29)
30295		 or    $4,$0,$14
30296		 jalr  $25
30297		 sw    $23,0x4C($21)    	 # Delay slot
30298		 lw    $24,0x40($29)
30299		 lw    $14,0x44($29)
30300		 lw    $15,m68k_ICount
30301		 seh   $9,$2
30302		 srl   $24,$24,9
30303		 addiu $24,$24,-1       	 # Move range down
30304		 andi  $24,$24,0x07     	 # Mask out lower bits
30305		 addiu $24,$24,1        	 # correct range
30306		 subu  $2,$9,$24
30307		 sltu  $16,$9,$24       	 # Set Carry
30308		 xor   $17,$9,$24
30309		 xor   $25,$2,$9
30310		 and   $17,$17,$25
30311		 srl   $17,$17,15
30312		 andi  $17,$17,0x01     	 # Set Overflow
30313		 seh  $25,$2
30314		 slt   $19,$25,$0        	 # Set Sign
30315		 sltiu $18,$25,1         	 # Set Zero
30316		 or    $20,$0,$16      	 # Copy Carry to X
30317		 lw    $25,0x8C($21)
30318		 sw    $15,m68k_ICount
30319		 or    $5,$0,$2
30320		 or    $4,$0,$14
30321		 jalr  $25
30322		 sw    $23,0x4C($21)    	 # Delay slot
30323		 lw    $15,m68k_ICount
30324		 addiu $15,$15,-12
30325		 bgez  $15,3f
30326		 lhu   $24,0x00($23)    	 # Delay slot
30327		 j     MainExit
30328	3:
30329		 sll   $7,$24,2         	 # Delay slot
30330		 addu  $7,$7,$30
30331		 lw    $7,0x00($7)
30332		 jr    $7
30333		 nop                    	 # Delay slot
30334
30335OP0_5160:				#:
30336		 addiu $23,$23,2
30337
30338		 andi  $16,$24,0x07
30339		 sll   $16,$16,2
30340		 addu  $16,$16,$21
30341		 lw    $14,0x20($16)
30342		 addiu $14,$14,-2
30343		 sw    $14,0x20($16)
30344		 lw    $25,0x80($21)
30345		 sw    $15,m68k_ICount
30346		 sw    $14,0x44($29)
30347		 sw    $24,0x40($29)
30348		 or    $4,$0,$14
30349		 jalr  $25
30350		 sw    $23,0x4C($21)    	 # Delay slot
30351		 lw    $24,0x40($29)
30352		 lw    $14,0x44($29)
30353		 lw    $15,m68k_ICount
30354		 seh   $9,$2
30355		 srl   $24,$24,9
30356		 addiu $24,$24,-1       	 # Move range down
30357		 andi  $24,$24,0x07     	 # Mask out lower bits
30358		 addiu $24,$24,1        	 # correct range
30359		 subu  $2,$9,$24
30360		 sltu  $16,$9,$24       	 # Set Carry
30361		 xor   $17,$9,$24
30362		 xor   $25,$2,$9
30363		 and   $17,$17,$25
30364		 srl   $17,$17,15
30365		 andi  $17,$17,0x01     	 # Set Overflow
30366		 seh  $25,$2
30367		 slt   $19,$25,$0        	 # Set Sign
30368		 sltiu $18,$25,1         	 # Set Zero
30369		 or    $20,$0,$16      	 # Copy Carry to X
30370		 lw    $25,0x8C($21)
30371		 sw    $15,m68k_ICount
30372		 or    $5,$0,$2
30373		 or    $4,$0,$14
30374		 jalr  $25
30375		 sw    $23,0x4C($21)    	 # Delay slot
30376		 lw    $15,m68k_ICount
30377		 addiu $15,$15,-14
30378		 bgez  $15,3f
30379		 lhu   $24,0x00($23)    	 # Delay slot
30380		 j     MainExit
30381	3:
30382		 sll   $7,$24,2         	 # Delay slot
30383		 addu  $7,$7,$30
30384		 lw    $7,0x00($7)
30385		 jr    $7
30386		 nop                    	 # Delay slot
30387
30388OP0_5168:				#:
30389		 addiu $23,$23,2
30390
30391		 andi  $16,$24,0x07
30392		 lh    $7,0x00($23)
30393		 sll   $16,$16,2
30394		 addu  $16,$16,$21
30395		 lw    $14,0x20($16)
30396		 addiu $23,$23,2
30397		 addu  $14,$14,$7
30398		 lw    $25,0x80($21)
30399		 sw    $15,m68k_ICount
30400		 sw    $14,0x44($29)
30401		 sw    $24,0x40($29)
30402		 or    $4,$0,$14
30403		 jalr  $25
30404		 sw    $23,0x4C($21)    	 # Delay slot
30405		 lw    $24,0x40($29)
30406		 lw    $14,0x44($29)
30407		 lw    $15,m68k_ICount
30408		 seh   $9,$2
30409		 srl   $24,$24,9
30410		 addiu $24,$24,-1       	 # Move range down
30411		 andi  $24,$24,0x07     	 # Mask out lower bits
30412		 addiu $24,$24,1        	 # correct range
30413		 subu  $2,$9,$24
30414		 sltu  $16,$9,$24       	 # Set Carry
30415		 xor   $17,$9,$24
30416		 xor   $25,$2,$9
30417		 and   $17,$17,$25
30418		 srl   $17,$17,15
30419		 andi  $17,$17,0x01     	 # Set Overflow
30420		 seh  $25,$2
30421		 slt   $19,$25,$0        	 # Set Sign
30422		 sltiu $18,$25,1         	 # Set Zero
30423		 or    $20,$0,$16      	 # Copy Carry to X
30424		 lw    $25,0x8C($21)
30425		 sw    $15,m68k_ICount
30426		 or    $5,$0,$2
30427		 or    $4,$0,$14
30428		 jalr  $25
30429		 sw    $23,0x4C($21)    	 # Delay slot
30430		 lw    $15,m68k_ICount
30431		 addiu $15,$15,-16
30432		 bgez  $15,3f
30433		 lhu   $24,0x00($23)    	 # Delay slot
30434		 j     MainExit
30435	3:
30436		 sll   $7,$24,2         	 # Delay slot
30437		 addu  $7,$7,$30
30438		 lw    $7,0x00($7)
30439		 jr    $7
30440		 nop                    	 # Delay slot
30441
30442OP0_5170:				#:
30443		 addiu $23,$23,2
30444
30445		 andi  $16,$24,0x07
30446		 sll   $16,$16,2
30447		 addu  $16,$16,$21
30448		 lw    $14,0x20($16)
30449		 lhu   $7,0x00($23)
30450		 addiu $23,$23,2
30451		 seb   $6,$7
30452		 or    $25,$0,$7
30453		 srl   $7,$7,12
30454		 andi  $25,$25,0x0800
30455		 sll   $7,$7,2
30456		 addu  $7,$7,$21
30457		 bne   $25,$0,0f
30458		 lw    $25,0x00($7)      	 # Delay slot
30459		 seh   $25,$25
30460	0:
30461		 addu  $25,$14,$25
30462		 addu  $14,$25,$6
30463		 lw    $25,0x80($21)
30464		 sw    $15,m68k_ICount
30465		 sw    $14,0x44($29)
30466		 sw    $24,0x40($29)
30467		 or    $4,$0,$14
30468		 jalr  $25
30469		 sw    $23,0x4C($21)    	 # Delay slot
30470		 lw    $24,0x40($29)
30471		 lw    $14,0x44($29)
30472		 lw    $15,m68k_ICount
30473		 seh   $9,$2
30474		 srl   $24,$24,9
30475		 addiu $24,$24,-1       	 # Move range down
30476		 andi  $24,$24,0x07     	 # Mask out lower bits
30477		 addiu $24,$24,1        	 # correct range
30478		 subu  $2,$9,$24
30479		 sltu  $16,$9,$24       	 # Set Carry
30480		 xor   $17,$9,$24
30481		 xor   $25,$2,$9
30482		 and   $17,$17,$25
30483		 srl   $17,$17,15
30484		 andi  $17,$17,0x01     	 # Set Overflow
30485		 seh  $25,$2
30486		 slt   $19,$25,$0        	 # Set Sign
30487		 sltiu $18,$25,1         	 # Set Zero
30488		 or    $20,$0,$16      	 # Copy Carry to X
30489		 lw    $25,0x8C($21)
30490		 sw    $15,m68k_ICount
30491		 or    $5,$0,$2
30492		 or    $4,$0,$14
30493		 jalr  $25
30494		 sw    $23,0x4C($21)    	 # Delay slot
30495		 lw    $15,m68k_ICount
30496		 addiu $15,$15,-18
30497		 bgez  $15,3f
30498		 lhu   $24,0x00($23)    	 # Delay slot
30499		 j     MainExit
30500	3:
30501		 sll   $7,$24,2         	 # Delay slot
30502		 addu  $7,$7,$30
30503		 lw    $7,0x00($7)
30504		 jr    $7
30505		 nop                    	 # Delay slot
30506
30507OP0_5178:				#:
30508		 addiu $23,$23,2
30509
30510		 lh    $14,0x00($23)
30511		 addiu $23,$23,2
30512		 lw    $25,0x80($21)
30513		 sw    $15,m68k_ICount
30514		 sw    $14,0x44($29)
30515		 sw    $24,0x40($29)
30516		 or    $4,$0,$14
30517		 jalr  $25
30518		 sw    $23,0x4C($21)    	 # Delay slot
30519		 lw    $24,0x40($29)
30520		 lw    $14,0x44($29)
30521		 lw    $15,m68k_ICount
30522		 seh   $9,$2
30523		 srl   $24,$24,9
30524		 addiu $24,$24,-1       	 # Move range down
30525		 andi  $24,$24,0x07     	 # Mask out lower bits
30526		 addiu $24,$24,1        	 # correct range
30527		 subu  $2,$9,$24
30528		 sltu  $16,$9,$24       	 # Set Carry
30529		 xor   $17,$9,$24
30530		 xor   $25,$2,$9
30531		 and   $17,$17,$25
30532		 srl   $17,$17,15
30533		 andi  $17,$17,0x01     	 # Set Overflow
30534		 seh  $25,$2
30535		 slt   $19,$25,$0        	 # Set Sign
30536		 sltiu $18,$25,1         	 # Set Zero
30537		 or    $20,$0,$16      	 # Copy Carry to X
30538		 lw    $25,0x8C($21)
30539		 sw    $15,m68k_ICount
30540		 or    $5,$0,$2
30541		 or    $4,$0,$14
30542		 jalr  $25
30543		 sw    $23,0x4C($21)    	 # Delay slot
30544		 lw    $15,m68k_ICount
30545		 addiu $15,$15,-16
30546		 bgez  $15,3f
30547		 lhu   $24,0x00($23)    	 # Delay slot
30548		 j     MainExit
30549	3:
30550		 sll   $7,$24,2         	 # Delay slot
30551		 addu  $7,$7,$30
30552		 lw    $7,0x00($7)
30553		 jr    $7
30554		 nop                    	 # Delay slot
30555
30556OP0_5179:				#:
30557		 addiu $23,$23,2
30558
30559		 lhu   $14,0x00($23)
30560		 lhu   $25,0x02($23)
30561		 sll   $14,$14,16
30562		 or    $14,$14,$25
30563		 addiu $23,$23,4
30564		 lw    $25,0x80($21)
30565		 sw    $15,m68k_ICount
30566		 sw    $14,0x44($29)
30567		 sw    $24,0x40($29)
30568		 or    $4,$0,$14
30569		 jalr  $25
30570		 sw    $23,0x4C($21)    	 # Delay slot
30571		 lw    $24,0x40($29)
30572		 lw    $14,0x44($29)
30573		 lw    $15,m68k_ICount
30574		 seh   $9,$2
30575		 srl   $24,$24,9
30576		 addiu $24,$24,-1       	 # Move range down
30577		 andi  $24,$24,0x07     	 # Mask out lower bits
30578		 addiu $24,$24,1        	 # correct range
30579		 subu  $2,$9,$24
30580		 sltu  $16,$9,$24       	 # Set Carry
30581		 xor   $17,$9,$24
30582		 xor   $25,$2,$9
30583		 and   $17,$17,$25
30584		 srl   $17,$17,15
30585		 andi  $17,$17,0x01     	 # Set Overflow
30586		 seh  $25,$2
30587		 slt   $19,$25,$0        	 # Set Sign
30588		 sltiu $18,$25,1         	 # Set Zero
30589		 or    $20,$0,$16      	 # Copy Carry to X
30590		 lw    $25,0x8C($21)
30591		 sw    $15,m68k_ICount
30592		 or    $5,$0,$2
30593		 or    $4,$0,$14
30594		 jalr  $25
30595		 sw    $23,0x4C($21)    	 # Delay slot
30596		 lw    $15,m68k_ICount
30597		 addiu $15,$15,-20
30598		 bgez  $15,3f
30599		 lhu   $24,0x00($23)    	 # Delay slot
30600		 j     MainExit
30601	3:
30602		 sll   $7,$24,2         	 # Delay slot
30603		 addu  $7,$7,$30
30604		 lw    $7,0x00($7)
30605		 jr    $7
30606		 nop                    	 # Delay slot
30607
30608OP0_5180:				#:
30609		 addiu $23,$23,2
30610
30611		 andi  $16,$24,0x07
30612		 sll   $16,$16,2
30613		 addu  $16,$16,$21
30614		 lw    $9,0x00($16)
30615		 srl   $24,$24,9
30616		 addiu $24,$24,-1       	 # Move range down
30617		 andi  $24,$24,0x07     	 # Mask out lower bits
30618		 addiu $24,$24,1        	 # correct range
30619		 subu  $2,$9,$24
30620		 sw    $2,0x00($16)
30621		 sltu  $16,$9,$24       	 # Set Carry
30622		 xor   $17,$9,$24
30623		 xor   $25,$2,$9
30624		 and   $17,$17,$25
30625		 srl   $17,$17,31        	 # Set Overflow
30626		 slt   $19,$2,$0        	 # Set Sign
30627		 sltiu $18,$2,1         	 # Set Zero
30628		 or    $20,$0,$16      	 # Copy Carry to X
30629		 addiu $15,$15,-8
30630		 bgez  $15,3f
30631		 lhu   $24,0x00($23)    	 # Delay slot
30632		 j     MainExit
30633	3:
30634		 sll   $7,$24,2         	 # Delay slot
30635		 addu  $7,$7,$30
30636		 lw    $7,0x00($7)
30637		 jr    $7
30638		 nop                    	 # Delay slot
30639
30640OP0_5190:				#:
30641		 addiu $23,$23,2
30642
30643		 andi  $16,$24,0x07
30644		 sll   $16,$16,2
30645		 addu  $16,$16,$21
30646		 lw    $14,0x20($16)
30647		 lw    $25,0x84($21)
30648		 sw    $15,m68k_ICount
30649		 sw    $14,0x44($29)
30650		 sw    $24,0x40($29)
30651		 or    $4,$0,$14
30652		 jalr  $25
30653		 sw    $23,0x4C($21)    	 # Delay slot
30654		 lw    $24,0x40($29)
30655		 lw    $14,0x44($29)
30656		 lw    $15,m68k_ICount
30657		 or    $9,$0,$2
30658		 srl   $24,$24,9
30659		 addiu $24,$24,-1       	 # Move range down
30660		 andi  $24,$24,0x07     	 # Mask out lower bits
30661		 addiu $24,$24,1        	 # correct range
30662		 subu  $2,$9,$24
30663		 sltu  $16,$9,$24       	 # Set Carry
30664		 xor   $17,$9,$24
30665		 xor   $25,$2,$9
30666		 and   $17,$17,$25
30667		 srl   $17,$17,31        	 # Set Overflow
30668		 slt   $19,$2,$0        	 # Set Sign
30669		 sltiu $18,$2,1         	 # Set Zero
30670		 or    $20,$0,$16      	 # Copy Carry to X
30671		 lw    $25,0x90($21)
30672		 sw    $15,m68k_ICount
30673		 or    $5,$0,$2
30674		 or    $4,$0,$14
30675		 jalr  $25
30676		 sw    $23,0x4C($21)    	 # Delay slot
30677		 lw    $15,m68k_ICount
30678		 addiu $15,$15,-20
30679		 bgez  $15,3f
30680		 lhu   $24,0x00($23)    	 # Delay slot
30681		 j     MainExit
30682	3:
30683		 sll   $7,$24,2         	 # Delay slot
30684		 addu  $7,$7,$30
30685		 lw    $7,0x00($7)
30686		 jr    $7
30687		 nop                    	 # Delay slot
30688
30689OP0_5198:				#:
30690		 addiu $23,$23,2
30691
30692		 andi  $16,$24,0x07
30693		 sll   $16,$16,2
30694		 addu  $16,$16,$21
30695		 lw    $14,0x20($16)
30696		 addiu $25,$14,4
30697		 sw    $25,0x20($16)
30698		 lw    $25,0x84($21)
30699		 sw    $15,m68k_ICount
30700		 sw    $14,0x44($29)
30701		 sw    $24,0x40($29)
30702		 or    $4,$0,$14
30703		 jalr  $25
30704		 sw    $23,0x4C($21)    	 # Delay slot
30705		 lw    $24,0x40($29)
30706		 lw    $14,0x44($29)
30707		 lw    $15,m68k_ICount
30708		 or    $9,$0,$2
30709		 srl   $24,$24,9
30710		 addiu $24,$24,-1       	 # Move range down
30711		 andi  $24,$24,0x07     	 # Mask out lower bits
30712		 addiu $24,$24,1        	 # correct range
30713		 subu  $2,$9,$24
30714		 sltu  $16,$9,$24       	 # Set Carry
30715		 xor   $17,$9,$24
30716		 xor   $25,$2,$9
30717		 and   $17,$17,$25
30718		 srl   $17,$17,31        	 # Set Overflow
30719		 slt   $19,$2,$0        	 # Set Sign
30720		 sltiu $18,$2,1         	 # Set Zero
30721		 or    $20,$0,$16      	 # Copy Carry to X
30722		 lw    $25,0x90($21)
30723		 sw    $15,m68k_ICount
30724		 or    $5,$0,$2
30725		 or    $4,$0,$14
30726		 jalr  $25
30727		 sw    $23,0x4C($21)    	 # Delay slot
30728		 lw    $15,m68k_ICount
30729		 addiu $15,$15,-20
30730		 bgez  $15,3f
30731		 lhu   $24,0x00($23)    	 # Delay slot
30732		 j     MainExit
30733	3:
30734		 sll   $7,$24,2         	 # Delay slot
30735		 addu  $7,$7,$30
30736		 lw    $7,0x00($7)
30737		 jr    $7
30738		 nop                    	 # Delay slot
30739
30740OP0_51a0:				#:
30741		 addiu $23,$23,2
30742
30743		 andi  $16,$24,0x07
30744		 sll   $16,$16,2
30745		 addu  $16,$16,$21
30746		 lw    $14,0x20($16)
30747		 addiu $14,$14,-4
30748		 sw    $14,0x20($16)
30749		 lw    $25,0x84($21)
30750		 sw    $15,m68k_ICount
30751		 sw    $14,0x44($29)
30752		 sw    $24,0x40($29)
30753		 or    $4,$0,$14
30754		 jalr  $25
30755		 sw    $23,0x4C($21)    	 # Delay slot
30756		 lw    $24,0x40($29)
30757		 lw    $14,0x44($29)
30758		 lw    $15,m68k_ICount
30759		 or    $9,$0,$2
30760		 srl   $24,$24,9
30761		 addiu $24,$24,-1       	 # Move range down
30762		 andi  $24,$24,0x07     	 # Mask out lower bits
30763		 addiu $24,$24,1        	 # correct range
30764		 subu  $2,$9,$24
30765		 sltu  $16,$9,$24       	 # Set Carry
30766		 xor   $17,$9,$24
30767		 xor   $25,$2,$9
30768		 and   $17,$17,$25
30769		 srl   $17,$17,31        	 # Set Overflow
30770		 slt   $19,$2,$0        	 # Set Sign
30771		 sltiu $18,$2,1         	 # Set Zero
30772		 or    $20,$0,$16      	 # Copy Carry to X
30773		 lw    $25,0x90($21)
30774		 sw    $15,m68k_ICount
30775		 or    $5,$0,$2
30776		 or    $4,$0,$14
30777		 jalr  $25
30778		 sw    $23,0x4C($21)    	 # Delay slot
30779		 lw    $15,m68k_ICount
30780		 addiu $15,$15,-22
30781		 bgez  $15,3f
30782		 lhu   $24,0x00($23)    	 # Delay slot
30783		 j     MainExit
30784	3:
30785		 sll   $7,$24,2         	 # Delay slot
30786		 addu  $7,$7,$30
30787		 lw    $7,0x00($7)
30788		 jr    $7
30789		 nop                    	 # Delay slot
30790
30791OP0_51a8:				#:
30792		 addiu $23,$23,2
30793
30794		 andi  $16,$24,0x07
30795		 lh    $7,0x00($23)
30796		 sll   $16,$16,2
30797		 addu  $16,$16,$21
30798		 lw    $14,0x20($16)
30799		 addiu $23,$23,2
30800		 addu  $14,$14,$7
30801		 lw    $25,0x84($21)
30802		 sw    $15,m68k_ICount
30803		 sw    $14,0x44($29)
30804		 sw    $24,0x40($29)
30805		 or    $4,$0,$14
30806		 jalr  $25
30807		 sw    $23,0x4C($21)    	 # Delay slot
30808		 lw    $24,0x40($29)
30809		 lw    $14,0x44($29)
30810		 lw    $15,m68k_ICount
30811		 or    $9,$0,$2
30812		 srl   $24,$24,9
30813		 addiu $24,$24,-1       	 # Move range down
30814		 andi  $24,$24,0x07     	 # Mask out lower bits
30815		 addiu $24,$24,1        	 # correct range
30816		 subu  $2,$9,$24
30817		 sltu  $16,$9,$24       	 # Set Carry
30818		 xor   $17,$9,$24
30819		 xor   $25,$2,$9
30820		 and   $17,$17,$25
30821		 srl   $17,$17,31        	 # Set Overflow
30822		 slt   $19,$2,$0        	 # Set Sign
30823		 sltiu $18,$2,1         	 # Set Zero
30824		 or    $20,$0,$16      	 # Copy Carry to X
30825		 lw    $25,0x90($21)
30826		 sw    $15,m68k_ICount
30827		 or    $5,$0,$2
30828		 or    $4,$0,$14
30829		 jalr  $25
30830		 sw    $23,0x4C($21)    	 # Delay slot
30831		 lw    $15,m68k_ICount
30832		 addiu $15,$15,-24
30833		 bgez  $15,3f
30834		 lhu   $24,0x00($23)    	 # Delay slot
30835		 j     MainExit
30836	3:
30837		 sll   $7,$24,2         	 # Delay slot
30838		 addu  $7,$7,$30
30839		 lw    $7,0x00($7)
30840		 jr    $7
30841		 nop                    	 # Delay slot
30842
30843OP0_51b0:				#:
30844		 addiu $23,$23,2
30845
30846		 andi  $16,$24,0x07
30847		 sll   $16,$16,2
30848		 addu  $16,$16,$21
30849		 lw    $14,0x20($16)
30850		 lhu   $7,0x00($23)
30851		 addiu $23,$23,2
30852		 seb   $6,$7
30853		 or    $25,$0,$7
30854		 srl   $7,$7,12
30855		 andi  $25,$25,0x0800
30856		 sll   $7,$7,2
30857		 addu  $7,$7,$21
30858		 bne   $25,$0,0f
30859		 lw    $25,0x00($7)      	 # Delay slot
30860		 seh   $25,$25
30861	0:
30862		 addu  $25,$14,$25
30863		 addu  $14,$25,$6
30864		 lw    $25,0x84($21)
30865		 sw    $15,m68k_ICount
30866		 sw    $14,0x44($29)
30867		 sw    $24,0x40($29)
30868		 or    $4,$0,$14
30869		 jalr  $25
30870		 sw    $23,0x4C($21)    	 # Delay slot
30871		 lw    $24,0x40($29)
30872		 lw    $14,0x44($29)
30873		 lw    $15,m68k_ICount
30874		 or    $9,$0,$2
30875		 srl   $24,$24,9
30876		 addiu $24,$24,-1       	 # Move range down
30877		 andi  $24,$24,0x07     	 # Mask out lower bits
30878		 addiu $24,$24,1        	 # correct range
30879		 subu  $2,$9,$24
30880		 sltu  $16,$9,$24       	 # Set Carry
30881		 xor   $17,$9,$24
30882		 xor   $25,$2,$9
30883		 and   $17,$17,$25
30884		 srl   $17,$17,31        	 # Set Overflow
30885		 slt   $19,$2,$0        	 # Set Sign
30886		 sltiu $18,$2,1         	 # Set Zero
30887		 or    $20,$0,$16      	 # Copy Carry to X
30888		 lw    $25,0x90($21)
30889		 sw    $15,m68k_ICount
30890		 or    $5,$0,$2
30891		 or    $4,$0,$14
30892		 jalr  $25
30893		 sw    $23,0x4C($21)    	 # Delay slot
30894		 lw    $15,m68k_ICount
30895		 addiu $15,$15,-26
30896		 bgez  $15,3f
30897		 lhu   $24,0x00($23)    	 # Delay slot
30898		 j     MainExit
30899	3:
30900		 sll   $7,$24,2         	 # Delay slot
30901		 addu  $7,$7,$30
30902		 lw    $7,0x00($7)
30903		 jr    $7
30904		 nop                    	 # Delay slot
30905
30906OP0_51b8:				#:
30907		 addiu $23,$23,2
30908
30909		 lh    $14,0x00($23)
30910		 addiu $23,$23,2
30911		 lw    $25,0x84($21)
30912		 sw    $15,m68k_ICount
30913		 sw    $14,0x44($29)
30914		 sw    $24,0x40($29)
30915		 or    $4,$0,$14
30916		 jalr  $25
30917		 sw    $23,0x4C($21)    	 # Delay slot
30918		 lw    $24,0x40($29)
30919		 lw    $14,0x44($29)
30920		 lw    $15,m68k_ICount
30921		 or    $9,$0,$2
30922		 srl   $24,$24,9
30923		 addiu $24,$24,-1       	 # Move range down
30924		 andi  $24,$24,0x07     	 # Mask out lower bits
30925		 addiu $24,$24,1        	 # correct range
30926		 subu  $2,$9,$24
30927		 sltu  $16,$9,$24       	 # Set Carry
30928		 xor   $17,$9,$24
30929		 xor   $25,$2,$9
30930		 and   $17,$17,$25
30931		 srl   $17,$17,31        	 # Set Overflow
30932		 slt   $19,$2,$0        	 # Set Sign
30933		 sltiu $18,$2,1         	 # Set Zero
30934		 or    $20,$0,$16      	 # Copy Carry to X
30935		 lw    $25,0x90($21)
30936		 sw    $15,m68k_ICount
30937		 or    $5,$0,$2
30938		 or    $4,$0,$14
30939		 jalr  $25
30940		 sw    $23,0x4C($21)    	 # Delay slot
30941		 lw    $15,m68k_ICount
30942		 addiu $15,$15,-24
30943		 bgez  $15,3f
30944		 lhu   $24,0x00($23)    	 # Delay slot
30945		 j     MainExit
30946	3:
30947		 sll   $7,$24,2         	 # Delay slot
30948		 addu  $7,$7,$30
30949		 lw    $7,0x00($7)
30950		 jr    $7
30951		 nop                    	 # Delay slot
30952
30953OP0_51b9:				#:
30954		 addiu $23,$23,2
30955
30956		 lhu   $14,0x00($23)
30957		 lhu   $25,0x02($23)
30958		 sll   $14,$14,16
30959		 or    $14,$14,$25
30960		 addiu $23,$23,4
30961		 lw    $25,0x84($21)
30962		 sw    $15,m68k_ICount
30963		 sw    $14,0x44($29)
30964		 sw    $24,0x40($29)
30965		 or    $4,$0,$14
30966		 jalr  $25
30967		 sw    $23,0x4C($21)    	 # Delay slot
30968		 lw    $24,0x40($29)
30969		 lw    $14,0x44($29)
30970		 lw    $15,m68k_ICount
30971		 or    $9,$0,$2
30972		 srl   $24,$24,9
30973		 addiu $24,$24,-1       	 # Move range down
30974		 andi  $24,$24,0x07     	 # Mask out lower bits
30975		 addiu $24,$24,1        	 # correct range
30976		 subu  $2,$9,$24
30977		 sltu  $16,$9,$24       	 # Set Carry
30978		 xor   $17,$9,$24
30979		 xor   $25,$2,$9
30980		 and   $17,$17,$25
30981		 srl   $17,$17,31        	 # Set Overflow
30982		 slt   $19,$2,$0        	 # Set Sign
30983		 sltiu $18,$2,1         	 # Set Zero
30984		 or    $20,$0,$16      	 # Copy Carry to X
30985		 lw    $25,0x90($21)
30986		 sw    $15,m68k_ICount
30987		 or    $5,$0,$2
30988		 or    $4,$0,$14
30989		 jalr  $25
30990		 sw    $23,0x4C($21)    	 # Delay slot
30991		 lw    $15,m68k_ICount
30992		 addiu $15,$15,-28
30993		 bgez  $15,3f
30994		 lhu   $24,0x00($23)    	 # Delay slot
30995		 j     MainExit
30996	3:
30997		 sll   $7,$24,2         	 # Delay slot
30998		 addu  $7,$7,$30
30999		 lw    $7,0x00($7)
31000		 jr    $7
31001		 nop                    	 # Delay slot
31002
31003OP0_51c0:				#:
31004		 addiu $23,$23,2
31005
31006		 andi  $24,$24,0x07
31007		 and   $2,$0,$0
31008		 sll   $24,$24,2
31009		 addu  $24,$24,$21
31010		 sb    $2,0x00($24)
31011		 andi  $2,$2,0x02
31012		 addiu $15,$15,-4
31013		 subu  $15,$15,$2
31014		 bgez  $15,3f
31015		 lhu   $24,0x00($23)    	 # Delay slot
31016		 j     MainExit
31017	3:
31018		 sll   $7,$24,2         	 # Delay slot
31019		 addu  $7,$7,$30
31020		 lw    $7,0x00($7)
31021		 jr    $7
31022		 nop                    	 # Delay slot
31023
31024OP0_51c8:				#:
31025		 andi  $24,$24,0x07
31026		 sll   $24,$24,2
31027		 addu  $24,$24,$21
31028		 lhu   $8,0x00($24)
31029		 addiu $9,$8,-1
31030		 beq   $8,$0,9f         	 # Is it -1
31031		 sh    $9,0x00($24)     	 # Delay slot
31032
31033		 addiu $23,$23,2
31034
31035		 lh    $2,0x00($23)
31036		 addu  $23,$23,$2
31037		 addiu $15,$15,-10
31038		 bgez  $15,3f
31039		 lhu   $24,0x00($23)    	 # Delay slot
31040		 j     MainExit
31041	3:
31042		 sll   $7,$24,2         	 # Delay slot
31043		 addu  $7,$7,$30
31044		 lw    $7,0x00($7)
31045		 jr    $7
31046		 nop                    	 # Delay slot
31047
31048	9:
31049	1:
31050		 addiu $23,$23,4
31051
31052		 addiu $15,$15,-12
31053		 bgez  $15,3f
31054		 lhu   $24,0x00($23)    	 # Delay slot
31055		 j     MainExit
31056	3:
31057		 sll   $7,$24,2         	 # Delay slot
31058		 addu  $7,$7,$30
31059		 lw    $7,0x00($7)
31060		 jr    $7
31061		 nop                    	 # Delay slot
31062
31063OP0_51d0:				#:
31064		 addiu $23,$23,2
31065
31066		 andi  $24,$24,0x07
31067		 sll   $24,$24,2
31068		 addu  $24,$24,$21
31069		 lw    $14,0x20($24)
31070		 and   $2,$0,$0
31071		 lw    $25,0x88($21)
31072		 sw    $15,m68k_ICount
31073		 or    $5,$0,$2
31074		 or    $4,$0,$14
31075		 jalr  $25
31076		 sw    $23,0x4C($21)    	 # Delay slot
31077		 lw    $15,m68k_ICount
31078		 addiu $15,$15,-12
31079		 bgez  $15,3f
31080		 lhu   $24,0x00($23)    	 # Delay slot
31081		 j     MainExit
31082	3:
31083		 sll   $7,$24,2         	 # Delay slot
31084		 addu  $7,$7,$30
31085		 lw    $7,0x00($7)
31086		 jr    $7
31087		 nop                    	 # Delay slot
31088
31089OP0_51d8:				#:
31090		 addiu $23,$23,2
31091
31092		 andi  $24,$24,0x07
31093		 sll   $24,$24,2
31094		 addu  $24,$24,$21
31095		 lw    $14,0x20($24)
31096		 addiu $25,$14,1
31097		 sw    $25,0x20($24)
31098		 and   $2,$0,$0
31099		 lw    $25,0x88($21)
31100		 sw    $15,m68k_ICount
31101		 or    $5,$0,$2
31102		 or    $4,$0,$14
31103		 jalr  $25
31104		 sw    $23,0x4C($21)    	 # Delay slot
31105		 lw    $15,m68k_ICount
31106		 addiu $15,$15,-12
31107		 bgez  $15,3f
31108		 lhu   $24,0x00($23)    	 # Delay slot
31109		 j     MainExit
31110	3:
31111		 sll   $7,$24,2         	 # Delay slot
31112		 addu  $7,$7,$30
31113		 lw    $7,0x00($7)
31114		 jr    $7
31115		 nop                    	 # Delay slot
31116
31117OP0_51df:				#:
31118		 addiu $23,$23,2
31119
31120		 lw    $14,0x3C($21)    	 # Get A7
31121		 addiu $25,$14,2
31122		 sw    $25,0x3C($21)
31123		 and   $2,$0,$0
31124		 lw    $25,0x88($21)
31125		 sw    $15,m68k_ICount
31126		 or    $5,$0,$2
31127		 or    $4,$0,$14
31128		 jalr  $25
31129		 sw    $23,0x4C($21)    	 # Delay slot
31130		 lw    $15,m68k_ICount
31131		 addiu $15,$15,-12
31132		 bgez  $15,3f
31133		 lhu   $24,0x00($23)    	 # Delay slot
31134		 j     MainExit
31135	3:
31136		 sll   $7,$24,2         	 # Delay slot
31137		 addu  $7,$7,$30
31138		 lw    $7,0x00($7)
31139		 jr    $7
31140		 nop                    	 # Delay slot
31141
31142OP0_51e0:				#:
31143		 addiu $23,$23,2
31144
31145		 andi  $24,$24,0x07
31146		 sll   $24,$24,2
31147		 addu  $24,$24,$21
31148		 lw    $14,0x20($24)
31149		 addiu $14,$14,-1
31150		 sw    $14,0x20($24)
31151		 and   $2,$0,$0
31152		 lw    $25,0x88($21)
31153		 sw    $15,m68k_ICount
31154		 or    $5,$0,$2
31155		 or    $4,$0,$14
31156		 jalr  $25
31157		 sw    $23,0x4C($21)    	 # Delay slot
31158		 lw    $15,m68k_ICount
31159		 addiu $15,$15,-14
31160		 bgez  $15,3f
31161		 lhu   $24,0x00($23)    	 # Delay slot
31162		 j     MainExit
31163	3:
31164		 sll   $7,$24,2         	 # Delay slot
31165		 addu  $7,$7,$30
31166		 lw    $7,0x00($7)
31167		 jr    $7
31168		 nop                    	 # Delay slot
31169
31170OP0_51e7:				#:
31171		 addiu $23,$23,2
31172
31173		 lw    $14,0x3C($21)    	 # Get A7
31174		 addiu $14,$14,-2
31175		 sw    $14,0x3C($21)
31176		 and   $2,$0,$0
31177		 lw    $25,0x88($21)
31178		 sw    $15,m68k_ICount
31179		 or    $5,$0,$2
31180		 or    $4,$0,$14
31181		 jalr  $25
31182		 sw    $23,0x4C($21)    	 # Delay slot
31183		 lw    $15,m68k_ICount
31184		 addiu $15,$15,-14
31185		 bgez  $15,3f
31186		 lhu   $24,0x00($23)    	 # Delay slot
31187		 j     MainExit
31188	3:
31189		 sll   $7,$24,2         	 # Delay slot
31190		 addu  $7,$7,$30
31191		 lw    $7,0x00($7)
31192		 jr    $7
31193		 nop                    	 # Delay slot
31194
31195OP0_51e8:				#:
31196		 addiu $23,$23,2
31197
31198		 andi  $24,$24,0x07
31199		 lh    $7,0x00($23)
31200		 sll   $24,$24,2
31201		 addu  $24,$24,$21
31202		 lw    $14,0x20($24)
31203		 addiu $23,$23,2
31204		 addu  $14,$14,$7
31205		 and   $2,$0,$0
31206		 lw    $25,0x88($21)
31207		 sw    $15,m68k_ICount
31208		 or    $5,$0,$2
31209		 or    $4,$0,$14
31210		 jalr  $25
31211		 sw    $23,0x4C($21)    	 # Delay slot
31212		 lw    $15,m68k_ICount
31213		 addiu $15,$15,-16
31214		 bgez  $15,3f
31215		 lhu   $24,0x00($23)    	 # Delay slot
31216		 j     MainExit
31217	3:
31218		 sll   $7,$24,2         	 # Delay slot
31219		 addu  $7,$7,$30
31220		 lw    $7,0x00($7)
31221		 jr    $7
31222		 nop                    	 # Delay slot
31223
31224OP0_51f0:				#:
31225		 addiu $23,$23,2
31226
31227		 andi  $24,$24,0x07
31228		 sll   $24,$24,2
31229		 addu  $24,$24,$21
31230		 lw    $14,0x20($24)
31231		 lhu   $7,0x00($23)
31232		 addiu $23,$23,2
31233		 seb   $6,$7
31234		 or    $25,$0,$7
31235		 srl   $7,$7,12
31236		 andi  $25,$25,0x0800
31237		 sll   $7,$7,2
31238		 addu  $7,$7,$21
31239		 bne   $25,$0,0f
31240		 lw    $25,0x00($7)      	 # Delay slot
31241		 seh   $25,$25
31242	0:
31243		 addu  $25,$14,$25
31244		 addu  $14,$25,$6
31245		 and   $2,$0,$0
31246		 lw    $25,0x88($21)
31247		 sw    $15,m68k_ICount
31248		 or    $5,$0,$2
31249		 or    $4,$0,$14
31250		 jalr  $25
31251		 sw    $23,0x4C($21)    	 # Delay slot
31252		 lw    $15,m68k_ICount
31253		 addiu $15,$15,-18
31254		 bgez  $15,3f
31255		 lhu   $24,0x00($23)    	 # Delay slot
31256		 j     MainExit
31257	3:
31258		 sll   $7,$24,2         	 # Delay slot
31259		 addu  $7,$7,$30
31260		 lw    $7,0x00($7)
31261		 jr    $7
31262		 nop                    	 # Delay slot
31263
31264OP0_51f8:				#:
31265		 addiu $23,$23,2
31266
31267		 lh    $14,0x00($23)
31268		 addiu $23,$23,2
31269		 and   $2,$0,$0
31270		 lw    $25,0x88($21)
31271		 sw    $15,m68k_ICount
31272		 or    $5,$0,$2
31273		 or    $4,$0,$14
31274		 jalr  $25
31275		 sw    $23,0x4C($21)    	 # Delay slot
31276		 lw    $15,m68k_ICount
31277		 addiu $15,$15,-16
31278		 bgez  $15,3f
31279		 lhu   $24,0x00($23)    	 # Delay slot
31280		 j     MainExit
31281	3:
31282		 sll   $7,$24,2         	 # Delay slot
31283		 addu  $7,$7,$30
31284		 lw    $7,0x00($7)
31285		 jr    $7
31286		 nop                    	 # Delay slot
31287
31288OP0_51f9:				#:
31289		 addiu $23,$23,2
31290
31291		 lhu   $14,0x00($23)
31292		 lhu   $25,0x02($23)
31293		 sll   $14,$14,16
31294		 or    $14,$14,$25
31295		 addiu $23,$23,4
31296		 and   $2,$0,$0
31297		 lw    $25,0x88($21)
31298		 sw    $15,m68k_ICount
31299		 or    $5,$0,$2
31300		 or    $4,$0,$14
31301		 jalr  $25
31302		 sw    $23,0x4C($21)    	 # Delay slot
31303		 lw    $15,m68k_ICount
31304		 addiu $15,$15,-20
31305		 bgez  $15,3f
31306		 lhu   $24,0x00($23)    	 # Delay slot
31307		 j     MainExit
31308	3:
31309		 sll   $7,$24,2         	 # Delay slot
31310		 addu  $7,$7,$30
31311		 lw    $7,0x00($7)
31312		 jr    $7
31313		 nop                    	 # Delay slot
31314
31315OP0_52c0:				#:
31316		 addiu $23,$23,2
31317
31318		 andi  $24,$24,0x07
31319		 nor   $2,$16,$18
31320		 andi  $2,$2,1
31321		 subu  $2,$0,$2
31322		 sll   $24,$24,2
31323		 addu  $24,$24,$21
31324		 sb    $2,0x00($24)
31325		 andi  $2,$2,0x02
31326		 addiu $15,$15,-4
31327		 subu  $15,$15,$2
31328		 bgez  $15,3f
31329		 lhu   $24,0x00($23)    	 # Delay slot
31330		 j     MainExit
31331	3:
31332		 sll   $7,$24,2         	 # Delay slot
31333		 addu  $7,$7,$30
31334		 lw    $7,0x00($7)
31335		 jr    $7
31336		 nop                    	 # Delay slot
31337
31338OP0_52c8:				#:
31339		 nor   $25,$16,$18
31340		 andi  $25,$25,1
31341		 bne   $25,$0,1f
31342		 andi  $24,$24,0x07     	 # Delay slot
31343		 sll   $24,$24,2
31344		 addu  $24,$24,$21
31345		 lhu   $8,0x00($24)
31346		 addiu $9,$8,-1
31347		 beq   $8,$0,9f         	 # Is it -1
31348		 sh    $9,0x00($24)     	 # Delay slot
31349
31350		 addiu $23,$23,2
31351
31352		 lh    $2,0x00($23)
31353		 addu  $23,$23,$2
31354		 addiu $15,$15,-10
31355		 bgez  $15,3f
31356		 lhu   $24,0x00($23)    	 # Delay slot
31357		 j     MainExit
31358	3:
31359		 sll   $7,$24,2         	 # Delay slot
31360		 addu  $7,$7,$30
31361		 lw    $7,0x00($7)
31362		 jr    $7
31363		 nop                    	 # Delay slot
31364
31365	9:
31366	1:
31367		 addiu $23,$23,4
31368
31369		 addiu $15,$15,-12
31370		 bgez  $15,3f
31371		 lhu   $24,0x00($23)    	 # Delay slot
31372		 j     MainExit
31373	3:
31374		 sll   $7,$24,2         	 # Delay slot
31375		 addu  $7,$7,$30
31376		 lw    $7,0x00($7)
31377		 jr    $7
31378		 nop                    	 # Delay slot
31379
31380OP0_52d0:				#:
31381		 addiu $23,$23,2
31382
31383		 andi  $24,$24,0x07
31384		 sll   $24,$24,2
31385		 addu  $24,$24,$21
31386		 lw    $14,0x20($24)
31387		 nor   $2,$16,$18
31388		 andi  $2,$2,1
31389		 subu  $2,$0,$2
31390		 lw    $25,0x88($21)
31391		 sw    $15,m68k_ICount
31392		 or    $5,$0,$2
31393		 or    $4,$0,$14
31394		 jalr  $25
31395		 sw    $23,0x4C($21)    	 # Delay slot
31396		 lw    $15,m68k_ICount
31397		 addiu $15,$15,-12
31398		 bgez  $15,3f
31399		 lhu   $24,0x00($23)    	 # Delay slot
31400		 j     MainExit
31401	3:
31402		 sll   $7,$24,2         	 # Delay slot
31403		 addu  $7,$7,$30
31404		 lw    $7,0x00($7)
31405		 jr    $7
31406		 nop                    	 # Delay slot
31407
31408OP0_52d8:				#:
31409		 addiu $23,$23,2
31410
31411		 andi  $24,$24,0x07
31412		 sll   $24,$24,2
31413		 addu  $24,$24,$21
31414		 lw    $14,0x20($24)
31415		 addiu $25,$14,1
31416		 sw    $25,0x20($24)
31417		 nor   $2,$16,$18
31418		 andi  $2,$2,1
31419		 subu  $2,$0,$2
31420		 lw    $25,0x88($21)
31421		 sw    $15,m68k_ICount
31422		 or    $5,$0,$2
31423		 or    $4,$0,$14
31424		 jalr  $25
31425		 sw    $23,0x4C($21)    	 # Delay slot
31426		 lw    $15,m68k_ICount
31427		 addiu $15,$15,-12
31428		 bgez  $15,3f
31429		 lhu   $24,0x00($23)    	 # Delay slot
31430		 j     MainExit
31431	3:
31432		 sll   $7,$24,2         	 # Delay slot
31433		 addu  $7,$7,$30
31434		 lw    $7,0x00($7)
31435		 jr    $7
31436		 nop                    	 # Delay slot
31437
31438OP0_52df:				#:
31439		 addiu $23,$23,2
31440
31441		 lw    $14,0x3C($21)    	 # Get A7
31442		 addiu $25,$14,2
31443		 sw    $25,0x3C($21)
31444		 nor   $2,$16,$18
31445		 andi  $2,$2,1
31446		 subu  $2,$0,$2
31447		 lw    $25,0x88($21)
31448		 sw    $15,m68k_ICount
31449		 or    $5,$0,$2
31450		 or    $4,$0,$14
31451		 jalr  $25
31452		 sw    $23,0x4C($21)    	 # Delay slot
31453		 lw    $15,m68k_ICount
31454		 addiu $15,$15,-12
31455		 bgez  $15,3f
31456		 lhu   $24,0x00($23)    	 # Delay slot
31457		 j     MainExit
31458	3:
31459		 sll   $7,$24,2         	 # Delay slot
31460		 addu  $7,$7,$30
31461		 lw    $7,0x00($7)
31462		 jr    $7
31463		 nop                    	 # Delay slot
31464
31465OP0_52e0:				#:
31466		 addiu $23,$23,2
31467
31468		 andi  $24,$24,0x07
31469		 sll   $24,$24,2
31470		 addu  $24,$24,$21
31471		 lw    $14,0x20($24)
31472		 addiu $14,$14,-1
31473		 sw    $14,0x20($24)
31474		 nor   $2,$16,$18
31475		 andi  $2,$2,1
31476		 subu  $2,$0,$2
31477		 lw    $25,0x88($21)
31478		 sw    $15,m68k_ICount
31479		 or    $5,$0,$2
31480		 or    $4,$0,$14
31481		 jalr  $25
31482		 sw    $23,0x4C($21)    	 # Delay slot
31483		 lw    $15,m68k_ICount
31484		 addiu $15,$15,-14
31485		 bgez  $15,3f
31486		 lhu   $24,0x00($23)    	 # Delay slot
31487		 j     MainExit
31488	3:
31489		 sll   $7,$24,2         	 # Delay slot
31490		 addu  $7,$7,$30
31491		 lw    $7,0x00($7)
31492		 jr    $7
31493		 nop                    	 # Delay slot
31494
31495OP0_52e7:				#:
31496		 addiu $23,$23,2
31497
31498		 lw    $14,0x3C($21)    	 # Get A7
31499		 addiu $14,$14,-2
31500		 sw    $14,0x3C($21)
31501		 nor   $2,$16,$18
31502		 andi  $2,$2,1
31503		 subu  $2,$0,$2
31504		 lw    $25,0x88($21)
31505		 sw    $15,m68k_ICount
31506		 or    $5,$0,$2
31507		 or    $4,$0,$14
31508		 jalr  $25
31509		 sw    $23,0x4C($21)    	 # Delay slot
31510		 lw    $15,m68k_ICount
31511		 addiu $15,$15,-14
31512		 bgez  $15,3f
31513		 lhu   $24,0x00($23)    	 # Delay slot
31514		 j     MainExit
31515	3:
31516		 sll   $7,$24,2         	 # Delay slot
31517		 addu  $7,$7,$30
31518		 lw    $7,0x00($7)
31519		 jr    $7
31520		 nop                    	 # Delay slot
31521
31522OP0_52e8:				#:
31523		 addiu $23,$23,2
31524
31525		 andi  $24,$24,0x07
31526		 lh    $7,0x00($23)
31527		 sll   $24,$24,2
31528		 addu  $24,$24,$21
31529		 lw    $14,0x20($24)
31530		 addiu $23,$23,2
31531		 addu  $14,$14,$7
31532		 nor   $2,$16,$18
31533		 andi  $2,$2,1
31534		 subu  $2,$0,$2
31535		 lw    $25,0x88($21)
31536		 sw    $15,m68k_ICount
31537		 or    $5,$0,$2
31538		 or    $4,$0,$14
31539		 jalr  $25
31540		 sw    $23,0x4C($21)    	 # Delay slot
31541		 lw    $15,m68k_ICount
31542		 addiu $15,$15,-16
31543		 bgez  $15,3f
31544		 lhu   $24,0x00($23)    	 # Delay slot
31545		 j     MainExit
31546	3:
31547		 sll   $7,$24,2         	 # Delay slot
31548		 addu  $7,$7,$30
31549		 lw    $7,0x00($7)
31550		 jr    $7
31551		 nop                    	 # Delay slot
31552
31553OP0_52f0:				#:
31554		 addiu $23,$23,2
31555
31556		 andi  $24,$24,0x07
31557		 sll   $24,$24,2
31558		 addu  $24,$24,$21
31559		 lw    $14,0x20($24)
31560		 lhu   $7,0x00($23)
31561		 addiu $23,$23,2
31562		 seb   $6,$7
31563		 or    $25,$0,$7
31564		 srl   $7,$7,12
31565		 andi  $25,$25,0x0800
31566		 sll   $7,$7,2
31567		 addu  $7,$7,$21
31568		 bne   $25,$0,0f
31569		 lw    $25,0x00($7)      	 # Delay slot
31570		 seh   $25,$25
31571	0:
31572		 addu  $25,$14,$25
31573		 addu  $14,$25,$6
31574		 nor   $2,$16,$18
31575		 andi  $2,$2,1
31576		 subu  $2,$0,$2
31577		 lw    $25,0x88($21)
31578		 sw    $15,m68k_ICount
31579		 or    $5,$0,$2
31580		 or    $4,$0,$14
31581		 jalr  $25
31582		 sw    $23,0x4C($21)    	 # Delay slot
31583		 lw    $15,m68k_ICount
31584		 addiu $15,$15,-18
31585		 bgez  $15,3f
31586		 lhu   $24,0x00($23)    	 # Delay slot
31587		 j     MainExit
31588	3:
31589		 sll   $7,$24,2         	 # Delay slot
31590		 addu  $7,$7,$30
31591		 lw    $7,0x00($7)
31592		 jr    $7
31593		 nop                    	 # Delay slot
31594
31595OP0_52f8:				#:
31596		 addiu $23,$23,2
31597
31598		 lh    $14,0x00($23)
31599		 addiu $23,$23,2
31600		 nor   $2,$16,$18
31601		 andi  $2,$2,1
31602		 subu  $2,$0,$2
31603		 lw    $25,0x88($21)
31604		 sw    $15,m68k_ICount
31605		 or    $5,$0,$2
31606		 or    $4,$0,$14
31607		 jalr  $25
31608		 sw    $23,0x4C($21)    	 # Delay slot
31609		 lw    $15,m68k_ICount
31610		 addiu $15,$15,-16
31611		 bgez  $15,3f
31612		 lhu   $24,0x00($23)    	 # Delay slot
31613		 j     MainExit
31614	3:
31615		 sll   $7,$24,2         	 # Delay slot
31616		 addu  $7,$7,$30
31617		 lw    $7,0x00($7)
31618		 jr    $7
31619		 nop                    	 # Delay slot
31620
31621OP0_52f9:				#:
31622		 addiu $23,$23,2
31623
31624		 lhu   $14,0x00($23)
31625		 lhu   $25,0x02($23)
31626		 sll   $14,$14,16
31627		 or    $14,$14,$25
31628		 addiu $23,$23,4
31629		 nor   $2,$16,$18
31630		 andi  $2,$2,1
31631		 subu  $2,$0,$2
31632		 lw    $25,0x88($21)
31633		 sw    $15,m68k_ICount
31634		 or    $5,$0,$2
31635		 or    $4,$0,$14
31636		 jalr  $25
31637		 sw    $23,0x4C($21)    	 # Delay slot
31638		 lw    $15,m68k_ICount
31639		 addiu $15,$15,-20
31640		 bgez  $15,3f
31641		 lhu   $24,0x00($23)    	 # Delay slot
31642		 j     MainExit
31643	3:
31644		 sll   $7,$24,2         	 # Delay slot
31645		 addu  $7,$7,$30
31646		 lw    $7,0x00($7)
31647		 jr    $7
31648		 nop                    	 # Delay slot
31649
31650OP0_53c0:				#:
31651		 addiu $23,$23,2
31652
31653		 andi  $24,$24,0x07
31654		 or    $2,$16,$18
31655		 subu  $2,$0,$2
31656		 sll   $24,$24,2
31657		 addu  $24,$24,$21
31658		 sb    $2,0x00($24)
31659		 andi  $2,$2,0x02
31660		 addiu $15,$15,-4
31661		 subu  $15,$15,$2
31662		 bgez  $15,3f
31663		 lhu   $24,0x00($23)    	 # Delay slot
31664		 j     MainExit
31665	3:
31666		 sll   $7,$24,2         	 # Delay slot
31667		 addu  $7,$7,$30
31668		 lw    $7,0x00($7)
31669		 jr    $7
31670		 nop                    	 # Delay slot
31671
31672OP0_53c8:				#:
31673		 or   $25,$16,$18
31674		 bne   $25,$0,1f
31675		 andi  $24,$24,0x07     	 # Delay slot
31676		 sll   $24,$24,2
31677		 addu  $24,$24,$21
31678		 lhu   $8,0x00($24)
31679		 addiu $9,$8,-1
31680		 beq   $8,$0,9f         	 # Is it -1
31681		 sh    $9,0x00($24)     	 # Delay slot
31682
31683		 addiu $23,$23,2
31684
31685		 lh    $2,0x00($23)
31686		 addu  $23,$23,$2
31687		 addiu $15,$15,-10
31688		 bgez  $15,3f
31689		 lhu   $24,0x00($23)    	 # Delay slot
31690		 j     MainExit
31691	3:
31692		 sll   $7,$24,2         	 # Delay slot
31693		 addu  $7,$7,$30
31694		 lw    $7,0x00($7)
31695		 jr    $7
31696		 nop                    	 # Delay slot
31697
31698	9:
31699	1:
31700		 addiu $23,$23,4
31701
31702		 addiu $15,$15,-12
31703		 bgez  $15,3f
31704		 lhu   $24,0x00($23)    	 # Delay slot
31705		 j     MainExit
31706	3:
31707		 sll   $7,$24,2         	 # Delay slot
31708		 addu  $7,$7,$30
31709		 lw    $7,0x00($7)
31710		 jr    $7
31711		 nop                    	 # Delay slot
31712
31713OP0_53d0:				#:
31714		 addiu $23,$23,2
31715
31716		 andi  $24,$24,0x07
31717		 sll   $24,$24,2
31718		 addu  $24,$24,$21
31719		 lw    $14,0x20($24)
31720		 or    $2,$16,$18
31721		 subu  $2,$0,$2
31722		 lw    $25,0x88($21)
31723		 sw    $15,m68k_ICount
31724		 or    $5,$0,$2
31725		 or    $4,$0,$14
31726		 jalr  $25
31727		 sw    $23,0x4C($21)    	 # Delay slot
31728		 lw    $15,m68k_ICount
31729		 addiu $15,$15,-12
31730		 bgez  $15,3f
31731		 lhu   $24,0x00($23)    	 # Delay slot
31732		 j     MainExit
31733	3:
31734		 sll   $7,$24,2         	 # Delay slot
31735		 addu  $7,$7,$30
31736		 lw    $7,0x00($7)
31737		 jr    $7
31738		 nop                    	 # Delay slot
31739
31740OP0_53d8:				#:
31741		 addiu $23,$23,2
31742
31743		 andi  $24,$24,0x07
31744		 sll   $24,$24,2
31745		 addu  $24,$24,$21
31746		 lw    $14,0x20($24)
31747		 addiu $25,$14,1
31748		 sw    $25,0x20($24)
31749		 or    $2,$16,$18
31750		 subu  $2,$0,$2
31751		 lw    $25,0x88($21)
31752		 sw    $15,m68k_ICount
31753		 or    $5,$0,$2
31754		 or    $4,$0,$14
31755		 jalr  $25
31756		 sw    $23,0x4C($21)    	 # Delay slot
31757		 lw    $15,m68k_ICount
31758		 addiu $15,$15,-12
31759		 bgez  $15,3f
31760		 lhu   $24,0x00($23)    	 # Delay slot
31761		 j     MainExit
31762	3:
31763		 sll   $7,$24,2         	 # Delay slot
31764		 addu  $7,$7,$30
31765		 lw    $7,0x00($7)
31766		 jr    $7
31767		 nop                    	 # Delay slot
31768
31769OP0_53df:				#:
31770		 addiu $23,$23,2
31771
31772		 lw    $14,0x3C($21)    	 # Get A7
31773		 addiu $25,$14,2
31774		 sw    $25,0x3C($21)
31775		 or    $2,$16,$18
31776		 subu  $2,$0,$2
31777		 lw    $25,0x88($21)
31778		 sw    $15,m68k_ICount
31779		 or    $5,$0,$2
31780		 or    $4,$0,$14
31781		 jalr  $25
31782		 sw    $23,0x4C($21)    	 # Delay slot
31783		 lw    $15,m68k_ICount
31784		 addiu $15,$15,-12
31785		 bgez  $15,3f
31786		 lhu   $24,0x00($23)    	 # Delay slot
31787		 j     MainExit
31788	3:
31789		 sll   $7,$24,2         	 # Delay slot
31790		 addu  $7,$7,$30
31791		 lw    $7,0x00($7)
31792		 jr    $7
31793		 nop                    	 # Delay slot
31794
31795OP0_53e0:				#:
31796		 addiu $23,$23,2
31797
31798		 andi  $24,$24,0x07
31799		 sll   $24,$24,2
31800		 addu  $24,$24,$21
31801		 lw    $14,0x20($24)
31802		 addiu $14,$14,-1
31803		 sw    $14,0x20($24)
31804		 or    $2,$16,$18
31805		 subu  $2,$0,$2
31806		 lw    $25,0x88($21)
31807		 sw    $15,m68k_ICount
31808		 or    $5,$0,$2
31809		 or    $4,$0,$14
31810		 jalr  $25
31811		 sw    $23,0x4C($21)    	 # Delay slot
31812		 lw    $15,m68k_ICount
31813		 addiu $15,$15,-14
31814		 bgez  $15,3f
31815		 lhu   $24,0x00($23)    	 # Delay slot
31816		 j     MainExit
31817	3:
31818		 sll   $7,$24,2         	 # Delay slot
31819		 addu  $7,$7,$30
31820		 lw    $7,0x00($7)
31821		 jr    $7
31822		 nop                    	 # Delay slot
31823
31824OP0_53e7:				#:
31825		 addiu $23,$23,2
31826
31827		 lw    $14,0x3C($21)    	 # Get A7
31828		 addiu $14,$14,-2
31829		 sw    $14,0x3C($21)
31830		 or    $2,$16,$18
31831		 subu  $2,$0,$2
31832		 lw    $25,0x88($21)
31833		 sw    $15,m68k_ICount
31834		 or    $5,$0,$2
31835		 or    $4,$0,$14
31836		 jalr  $25
31837		 sw    $23,0x4C($21)    	 # Delay slot
31838		 lw    $15,m68k_ICount
31839		 addiu $15,$15,-14
31840		 bgez  $15,3f
31841		 lhu   $24,0x00($23)    	 # Delay slot
31842		 j     MainExit
31843	3:
31844		 sll   $7,$24,2         	 # Delay slot
31845		 addu  $7,$7,$30
31846		 lw    $7,0x00($7)
31847		 jr    $7
31848		 nop                    	 # Delay slot
31849
31850OP0_53e8:				#:
31851		 addiu $23,$23,2
31852
31853		 andi  $24,$24,0x07
31854		 lh    $7,0x00($23)
31855		 sll   $24,$24,2
31856		 addu  $24,$24,$21
31857		 lw    $14,0x20($24)
31858		 addiu $23,$23,2
31859		 addu  $14,$14,$7
31860		 or    $2,$16,$18
31861		 subu  $2,$0,$2
31862		 lw    $25,0x88($21)
31863		 sw    $15,m68k_ICount
31864		 or    $5,$0,$2
31865		 or    $4,$0,$14
31866		 jalr  $25
31867		 sw    $23,0x4C($21)    	 # Delay slot
31868		 lw    $15,m68k_ICount
31869		 addiu $15,$15,-16
31870		 bgez  $15,3f
31871		 lhu   $24,0x00($23)    	 # Delay slot
31872		 j     MainExit
31873	3:
31874		 sll   $7,$24,2         	 # Delay slot
31875		 addu  $7,$7,$30
31876		 lw    $7,0x00($7)
31877		 jr    $7
31878		 nop                    	 # Delay slot
31879
31880OP0_53f0:				#:
31881		 addiu $23,$23,2
31882
31883		 andi  $24,$24,0x07
31884		 sll   $24,$24,2
31885		 addu  $24,$24,$21
31886		 lw    $14,0x20($24)
31887		 lhu   $7,0x00($23)
31888		 addiu $23,$23,2
31889		 seb   $6,$7
31890		 or    $25,$0,$7
31891		 srl   $7,$7,12
31892		 andi  $25,$25,0x0800
31893		 sll   $7,$7,2
31894		 addu  $7,$7,$21
31895		 bne   $25,$0,0f
31896		 lw    $25,0x00($7)      	 # Delay slot
31897		 seh   $25,$25
31898	0:
31899		 addu  $25,$14,$25
31900		 addu  $14,$25,$6
31901		 or    $2,$16,$18
31902		 subu  $2,$0,$2
31903		 lw    $25,0x88($21)
31904		 sw    $15,m68k_ICount
31905		 or    $5,$0,$2
31906		 or    $4,$0,$14
31907		 jalr  $25
31908		 sw    $23,0x4C($21)    	 # Delay slot
31909		 lw    $15,m68k_ICount
31910		 addiu $15,$15,-18
31911		 bgez  $15,3f
31912		 lhu   $24,0x00($23)    	 # Delay slot
31913		 j     MainExit
31914	3:
31915		 sll   $7,$24,2         	 # Delay slot
31916		 addu  $7,$7,$30
31917		 lw    $7,0x00($7)
31918		 jr    $7
31919		 nop                    	 # Delay slot
31920
31921OP0_53f8:				#:
31922		 addiu $23,$23,2
31923
31924		 lh    $14,0x00($23)
31925		 addiu $23,$23,2
31926		 or    $2,$16,$18
31927		 subu  $2,$0,$2
31928		 lw    $25,0x88($21)
31929		 sw    $15,m68k_ICount
31930		 or    $5,$0,$2
31931		 or    $4,$0,$14
31932		 jalr  $25
31933		 sw    $23,0x4C($21)    	 # Delay slot
31934		 lw    $15,m68k_ICount
31935		 addiu $15,$15,-16
31936		 bgez  $15,3f
31937		 lhu   $24,0x00($23)    	 # Delay slot
31938		 j     MainExit
31939	3:
31940		 sll   $7,$24,2         	 # Delay slot
31941		 addu  $7,$7,$30
31942		 lw    $7,0x00($7)
31943		 jr    $7
31944		 nop                    	 # Delay slot
31945
31946OP0_53f9:				#:
31947		 addiu $23,$23,2
31948
31949		 lhu   $14,0x00($23)
31950		 lhu   $25,0x02($23)
31951		 sll   $14,$14,16
31952		 or    $14,$14,$25
31953		 addiu $23,$23,4
31954		 or    $2,$16,$18
31955		 subu  $2,$0,$2
31956		 lw    $25,0x88($21)
31957		 sw    $15,m68k_ICount
31958		 or    $5,$0,$2
31959		 or    $4,$0,$14
31960		 jalr  $25
31961		 sw    $23,0x4C($21)    	 # Delay slot
31962		 lw    $15,m68k_ICount
31963		 addiu $15,$15,-20
31964		 bgez  $15,3f
31965		 lhu   $24,0x00($23)    	 # Delay slot
31966		 j     MainExit
31967	3:
31968		 sll   $7,$24,2         	 # Delay slot
31969		 addu  $7,$7,$30
31970		 lw    $7,0x00($7)
31971		 jr    $7
31972		 nop                    	 # Delay slot
31973
31974OP0_54c0:				#:
31975		 addiu $23,$23,2
31976
31977		 andi  $24,$24,0x07
31978		 xori  $2,$16,1         	 # Check Carry
31979		 subu  $2,$0,$2
31980		 sll   $24,$24,2
31981		 addu  $24,$24,$21
31982		 sb    $2,0x00($24)
31983		 andi  $2,$2,0x02
31984		 addiu $15,$15,-4
31985		 subu  $15,$15,$2
31986		 bgez  $15,3f
31987		 lhu   $24,0x00($23)    	 # Delay slot
31988		 j     MainExit
31989	3:
31990		 sll   $7,$24,2         	 # Delay slot
31991		 addu  $7,$7,$30
31992		 lw    $7,0x00($7)
31993		 jr    $7
31994		 nop                    	 # Delay slot
31995
31996OP0_54c8:				#:
31997		 beq   $16,$0,1f        	 # check carry
31998		 andi  $24,$24,0x07     	 # Delay slot
31999		 sll   $24,$24,2
32000		 addu  $24,$24,$21
32001		 lhu   $8,0x00($24)
32002		 addiu $9,$8,-1
32003		 beq   $8,$0,9f         	 # Is it -1
32004		 sh    $9,0x00($24)     	 # Delay slot
32005
32006		 addiu $23,$23,2
32007
32008		 lh    $2,0x00($23)
32009		 addu  $23,$23,$2
32010		 addiu $15,$15,-10
32011		 bgez  $15,3f
32012		 lhu   $24,0x00($23)    	 # Delay slot
32013		 j     MainExit
32014	3:
32015		 sll   $7,$24,2         	 # Delay slot
32016		 addu  $7,$7,$30
32017		 lw    $7,0x00($7)
32018		 jr    $7
32019		 nop                    	 # Delay slot
32020
32021	9:
32022	1:
32023		 addiu $23,$23,4
32024
32025		 addiu $15,$15,-12
32026		 bgez  $15,3f
32027		 lhu   $24,0x00($23)    	 # Delay slot
32028		 j     MainExit
32029	3:
32030		 sll   $7,$24,2         	 # Delay slot
32031		 addu  $7,$7,$30
32032		 lw    $7,0x00($7)
32033		 jr    $7
32034		 nop                    	 # Delay slot
32035
32036OP0_54d0:				#:
32037		 addiu $23,$23,2
32038
32039		 andi  $24,$24,0x07
32040		 sll   $24,$24,2
32041		 addu  $24,$24,$21
32042		 lw    $14,0x20($24)
32043		 xori  $2,$16,1         	 # Check Carry
32044		 subu  $2,$0,$2
32045		 lw    $25,0x88($21)
32046		 sw    $15,m68k_ICount
32047		 or    $5,$0,$2
32048		 or    $4,$0,$14
32049		 jalr  $25
32050		 sw    $23,0x4C($21)    	 # Delay slot
32051		 lw    $15,m68k_ICount
32052		 addiu $15,$15,-12
32053		 bgez  $15,3f
32054		 lhu   $24,0x00($23)    	 # Delay slot
32055		 j     MainExit
32056	3:
32057		 sll   $7,$24,2         	 # Delay slot
32058		 addu  $7,$7,$30
32059		 lw    $7,0x00($7)
32060		 jr    $7
32061		 nop                    	 # Delay slot
32062
32063OP0_54d8:				#:
32064		 addiu $23,$23,2
32065
32066		 andi  $24,$24,0x07
32067		 sll   $24,$24,2
32068		 addu  $24,$24,$21
32069		 lw    $14,0x20($24)
32070		 addiu $25,$14,1
32071		 sw    $25,0x20($24)
32072		 xori  $2,$16,1         	 # Check Carry
32073		 subu  $2,$0,$2
32074		 lw    $25,0x88($21)
32075		 sw    $15,m68k_ICount
32076		 or    $5,$0,$2
32077		 or    $4,$0,$14
32078		 jalr  $25
32079		 sw    $23,0x4C($21)    	 # Delay slot
32080		 lw    $15,m68k_ICount
32081		 addiu $15,$15,-12
32082		 bgez  $15,3f
32083		 lhu   $24,0x00($23)    	 # Delay slot
32084		 j     MainExit
32085	3:
32086		 sll   $7,$24,2         	 # Delay slot
32087		 addu  $7,$7,$30
32088		 lw    $7,0x00($7)
32089		 jr    $7
32090		 nop                    	 # Delay slot
32091
32092OP0_54df:				#:
32093		 addiu $23,$23,2
32094
32095		 lw    $14,0x3C($21)    	 # Get A7
32096		 addiu $25,$14,2
32097		 sw    $25,0x3C($21)
32098		 xori  $2,$16,1         	 # Check Carry
32099		 subu  $2,$0,$2
32100		 lw    $25,0x88($21)
32101		 sw    $15,m68k_ICount
32102		 or    $5,$0,$2
32103		 or    $4,$0,$14
32104		 jalr  $25
32105		 sw    $23,0x4C($21)    	 # Delay slot
32106		 lw    $15,m68k_ICount
32107		 addiu $15,$15,-12
32108		 bgez  $15,3f
32109		 lhu   $24,0x00($23)    	 # Delay slot
32110		 j     MainExit
32111	3:
32112		 sll   $7,$24,2         	 # Delay slot
32113		 addu  $7,$7,$30
32114		 lw    $7,0x00($7)
32115		 jr    $7
32116		 nop                    	 # Delay slot
32117
32118OP0_54e0:				#:
32119		 addiu $23,$23,2
32120
32121		 andi  $24,$24,0x07
32122		 sll   $24,$24,2
32123		 addu  $24,$24,$21
32124		 lw    $14,0x20($24)
32125		 addiu $14,$14,-1
32126		 sw    $14,0x20($24)
32127		 xori  $2,$16,1         	 # Check Carry
32128		 subu  $2,$0,$2
32129		 lw    $25,0x88($21)
32130		 sw    $15,m68k_ICount
32131		 or    $5,$0,$2
32132		 or    $4,$0,$14
32133		 jalr  $25
32134		 sw    $23,0x4C($21)    	 # Delay slot
32135		 lw    $15,m68k_ICount
32136		 addiu $15,$15,-14
32137		 bgez  $15,3f
32138		 lhu   $24,0x00($23)    	 # Delay slot
32139		 j     MainExit
32140	3:
32141		 sll   $7,$24,2         	 # Delay slot
32142		 addu  $7,$7,$30
32143		 lw    $7,0x00($7)
32144		 jr    $7
32145		 nop                    	 # Delay slot
32146
32147OP0_54e7:				#:
32148		 addiu $23,$23,2
32149
32150		 lw    $14,0x3C($21)    	 # Get A7
32151		 addiu $14,$14,-2
32152		 sw    $14,0x3C($21)
32153		 xori  $2,$16,1         	 # Check Carry
32154		 subu  $2,$0,$2
32155		 lw    $25,0x88($21)
32156		 sw    $15,m68k_ICount
32157		 or    $5,$0,$2
32158		 or    $4,$0,$14
32159		 jalr  $25
32160		 sw    $23,0x4C($21)    	 # Delay slot
32161		 lw    $15,m68k_ICount
32162		 addiu $15,$15,-14
32163		 bgez  $15,3f
32164		 lhu   $24,0x00($23)    	 # Delay slot
32165		 j     MainExit
32166	3:
32167		 sll   $7,$24,2         	 # Delay slot
32168		 addu  $7,$7,$30
32169		 lw    $7,0x00($7)
32170		 jr    $7
32171		 nop                    	 # Delay slot
32172
32173OP0_54e8:				#:
32174		 addiu $23,$23,2
32175
32176		 andi  $24,$24,0x07
32177		 lh    $7,0x00($23)
32178		 sll   $24,$24,2
32179		 addu  $24,$24,$21
32180		 lw    $14,0x20($24)
32181		 addiu $23,$23,2
32182		 addu  $14,$14,$7
32183		 xori  $2,$16,1         	 # Check Carry
32184		 subu  $2,$0,$2
32185		 lw    $25,0x88($21)
32186		 sw    $15,m68k_ICount
32187		 or    $5,$0,$2
32188		 or    $4,$0,$14
32189		 jalr  $25
32190		 sw    $23,0x4C($21)    	 # Delay slot
32191		 lw    $15,m68k_ICount
32192		 addiu $15,$15,-16
32193		 bgez  $15,3f
32194		 lhu   $24,0x00($23)    	 # Delay slot
32195		 j     MainExit
32196	3:
32197		 sll   $7,$24,2         	 # Delay slot
32198		 addu  $7,$7,$30
32199		 lw    $7,0x00($7)
32200		 jr    $7
32201		 nop                    	 # Delay slot
32202
32203OP0_54f0:				#:
32204		 addiu $23,$23,2
32205
32206		 andi  $24,$24,0x07
32207		 sll   $24,$24,2
32208		 addu  $24,$24,$21
32209		 lw    $14,0x20($24)
32210		 lhu   $7,0x00($23)
32211		 addiu $23,$23,2
32212		 seb   $6,$7
32213		 or    $25,$0,$7
32214		 srl   $7,$7,12
32215		 andi  $25,$25,0x0800
32216		 sll   $7,$7,2
32217		 addu  $7,$7,$21
32218		 bne   $25,$0,0f
32219		 lw    $25,0x00($7)      	 # Delay slot
32220		 seh   $25,$25
32221	0:
32222		 addu  $25,$14,$25
32223		 addu  $14,$25,$6
32224		 xori  $2,$16,1         	 # Check Carry
32225		 subu  $2,$0,$2
32226		 lw    $25,0x88($21)
32227		 sw    $15,m68k_ICount
32228		 or    $5,$0,$2
32229		 or    $4,$0,$14
32230		 jalr  $25
32231		 sw    $23,0x4C($21)    	 # Delay slot
32232		 lw    $15,m68k_ICount
32233		 addiu $15,$15,-18
32234		 bgez  $15,3f
32235		 lhu   $24,0x00($23)    	 # Delay slot
32236		 j     MainExit
32237	3:
32238		 sll   $7,$24,2         	 # Delay slot
32239		 addu  $7,$7,$30
32240		 lw    $7,0x00($7)
32241		 jr    $7
32242		 nop                    	 # Delay slot
32243
32244OP0_54f8:				#:
32245		 addiu $23,$23,2
32246
32247		 lh    $14,0x00($23)
32248		 addiu $23,$23,2
32249		 xori  $2,$16,1         	 # Check Carry
32250		 subu  $2,$0,$2
32251		 lw    $25,0x88($21)
32252		 sw    $15,m68k_ICount
32253		 or    $5,$0,$2
32254		 or    $4,$0,$14
32255		 jalr  $25
32256		 sw    $23,0x4C($21)    	 # Delay slot
32257		 lw    $15,m68k_ICount
32258		 addiu $15,$15,-16
32259		 bgez  $15,3f
32260		 lhu   $24,0x00($23)    	 # Delay slot
32261		 j     MainExit
32262	3:
32263		 sll   $7,$24,2         	 # Delay slot
32264		 addu  $7,$7,$30
32265		 lw    $7,0x00($7)
32266		 jr    $7
32267		 nop                    	 # Delay slot
32268
32269OP0_54f9:				#:
32270		 addiu $23,$23,2
32271
32272		 lhu   $14,0x00($23)
32273		 lhu   $25,0x02($23)
32274		 sll   $14,$14,16
32275		 or    $14,$14,$25
32276		 addiu $23,$23,4
32277		 xori  $2,$16,1         	 # Check Carry
32278		 subu  $2,$0,$2
32279		 lw    $25,0x88($21)
32280		 sw    $15,m68k_ICount
32281		 or    $5,$0,$2
32282		 or    $4,$0,$14
32283		 jalr  $25
32284		 sw    $23,0x4C($21)    	 # Delay slot
32285		 lw    $15,m68k_ICount
32286		 addiu $15,$15,-20
32287		 bgez  $15,3f
32288		 lhu   $24,0x00($23)    	 # Delay slot
32289		 j     MainExit
32290	3:
32291		 sll   $7,$24,2         	 # Delay slot
32292		 addu  $7,$7,$30
32293		 lw    $7,0x00($7)
32294		 jr    $7
32295		 nop                    	 # Delay slot
32296
32297OP0_55c0:				#:
32298		 addiu $23,$23,2
32299
32300		 andi  $24,$24,0x07
32301		 or    $2,$0,$16        	 # Check Carry
32302		 subu  $2,$0,$2
32303		 sll   $24,$24,2
32304		 addu  $24,$24,$21
32305		 sb    $2,0x00($24)
32306		 andi  $2,$2,0x02
32307		 addiu $15,$15,-4
32308		 subu  $15,$15,$2
32309		 bgez  $15,3f
32310		 lhu   $24,0x00($23)    	 # Delay slot
32311		 j     MainExit
32312	3:
32313		 sll   $7,$24,2         	 # Delay slot
32314		 addu  $7,$7,$30
32315		 lw    $7,0x00($7)
32316		 jr    $7
32317		 nop                    	 # Delay slot
32318
32319OP0_55c8:				#:
32320		 bne   $16,$0,1f        	 # check carry
32321		 andi  $24,$24,0x07     	 # Delay slot
32322		 sll   $24,$24,2
32323		 addu  $24,$24,$21
32324		 lhu   $8,0x00($24)
32325		 addiu $9,$8,-1
32326		 beq   $8,$0,9f         	 # Is it -1
32327		 sh    $9,0x00($24)     	 # Delay slot
32328
32329		 addiu $23,$23,2
32330
32331		 lh    $2,0x00($23)
32332		 addu  $23,$23,$2
32333		 addiu $15,$15,-10
32334		 bgez  $15,3f
32335		 lhu   $24,0x00($23)    	 # Delay slot
32336		 j     MainExit
32337	3:
32338		 sll   $7,$24,2         	 # Delay slot
32339		 addu  $7,$7,$30
32340		 lw    $7,0x00($7)
32341		 jr    $7
32342		 nop                    	 # Delay slot
32343
32344	9:
32345	1:
32346		 addiu $23,$23,4
32347
32348		 addiu $15,$15,-12
32349		 bgez  $15,3f
32350		 lhu   $24,0x00($23)    	 # Delay slot
32351		 j     MainExit
32352	3:
32353		 sll   $7,$24,2         	 # Delay slot
32354		 addu  $7,$7,$30
32355		 lw    $7,0x00($7)
32356		 jr    $7
32357		 nop                    	 # Delay slot
32358
32359OP0_55d0:				#:
32360		 addiu $23,$23,2
32361
32362		 andi  $24,$24,0x07
32363		 sll   $24,$24,2
32364		 addu  $24,$24,$21
32365		 lw    $14,0x20($24)
32366		 or    $2,$0,$16        	 # Check Carry
32367		 subu  $2,$0,$2
32368		 lw    $25,0x88($21)
32369		 sw    $15,m68k_ICount
32370		 or    $5,$0,$2
32371		 or    $4,$0,$14
32372		 jalr  $25
32373		 sw    $23,0x4C($21)    	 # Delay slot
32374		 lw    $15,m68k_ICount
32375		 addiu $15,$15,-12
32376		 bgez  $15,3f
32377		 lhu   $24,0x00($23)    	 # Delay slot
32378		 j     MainExit
32379	3:
32380		 sll   $7,$24,2         	 # Delay slot
32381		 addu  $7,$7,$30
32382		 lw    $7,0x00($7)
32383		 jr    $7
32384		 nop                    	 # Delay slot
32385
32386OP0_55d8:				#:
32387		 addiu $23,$23,2
32388
32389		 andi  $24,$24,0x07
32390		 sll   $24,$24,2
32391		 addu  $24,$24,$21
32392		 lw    $14,0x20($24)
32393		 addiu $25,$14,1
32394		 sw    $25,0x20($24)
32395		 or    $2,$0,$16        	 # Check Carry
32396		 subu  $2,$0,$2
32397		 lw    $25,0x88($21)
32398		 sw    $15,m68k_ICount
32399		 or    $5,$0,$2
32400		 or    $4,$0,$14
32401		 jalr  $25
32402		 sw    $23,0x4C($21)    	 # Delay slot
32403		 lw    $15,m68k_ICount
32404		 addiu $15,$15,-12
32405		 bgez  $15,3f
32406		 lhu   $24,0x00($23)    	 # Delay slot
32407		 j     MainExit
32408	3:
32409		 sll   $7,$24,2         	 # Delay slot
32410		 addu  $7,$7,$30
32411		 lw    $7,0x00($7)
32412		 jr    $7
32413		 nop                    	 # Delay slot
32414
32415OP0_55df:				#:
32416		 addiu $23,$23,2
32417
32418		 lw    $14,0x3C($21)    	 # Get A7
32419		 addiu $25,$14,2
32420		 sw    $25,0x3C($21)
32421		 or    $2,$0,$16        	 # Check Carry
32422		 subu  $2,$0,$2
32423		 lw    $25,0x88($21)
32424		 sw    $15,m68k_ICount
32425		 or    $5,$0,$2
32426		 or    $4,$0,$14
32427		 jalr  $25
32428		 sw    $23,0x4C($21)    	 # Delay slot
32429		 lw    $15,m68k_ICount
32430		 addiu $15,$15,-12
32431		 bgez  $15,3f
32432		 lhu   $24,0x00($23)    	 # Delay slot
32433		 j     MainExit
32434	3:
32435		 sll   $7,$24,2         	 # Delay slot
32436		 addu  $7,$7,$30
32437		 lw    $7,0x00($7)
32438		 jr    $7
32439		 nop                    	 # Delay slot
32440
32441OP0_55e0:				#:
32442		 addiu $23,$23,2
32443
32444		 andi  $24,$24,0x07
32445		 sll   $24,$24,2
32446		 addu  $24,$24,$21
32447		 lw    $14,0x20($24)
32448		 addiu $14,$14,-1
32449		 sw    $14,0x20($24)
32450		 or    $2,$0,$16        	 # Check Carry
32451		 subu  $2,$0,$2
32452		 lw    $25,0x88($21)
32453		 sw    $15,m68k_ICount
32454		 or    $5,$0,$2
32455		 or    $4,$0,$14
32456		 jalr  $25
32457		 sw    $23,0x4C($21)    	 # Delay slot
32458		 lw    $15,m68k_ICount
32459		 addiu $15,$15,-14
32460		 bgez  $15,3f
32461		 lhu   $24,0x00($23)    	 # Delay slot
32462		 j     MainExit
32463	3:
32464		 sll   $7,$24,2         	 # Delay slot
32465		 addu  $7,$7,$30
32466		 lw    $7,0x00($7)
32467		 jr    $7
32468		 nop                    	 # Delay slot
32469
32470OP0_55e7:				#:
32471		 addiu $23,$23,2
32472
32473		 lw    $14,0x3C($21)    	 # Get A7
32474		 addiu $14,$14,-2
32475		 sw    $14,0x3C($21)
32476		 or    $2,$0,$16        	 # Check Carry
32477		 subu  $2,$0,$2
32478		 lw    $25,0x88($21)
32479		 sw    $15,m68k_ICount
32480		 or    $5,$0,$2
32481		 or    $4,$0,$14
32482		 jalr  $25
32483		 sw    $23,0x4C($21)    	 # Delay slot
32484		 lw    $15,m68k_ICount
32485		 addiu $15,$15,-14
32486		 bgez  $15,3f
32487		 lhu   $24,0x00($23)    	 # Delay slot
32488		 j     MainExit
32489	3:
32490		 sll   $7,$24,2         	 # Delay slot
32491		 addu  $7,$7,$30
32492		 lw    $7,0x00($7)
32493		 jr    $7
32494		 nop                    	 # Delay slot
32495
32496OP0_55e8:				#:
32497		 addiu $23,$23,2
32498
32499		 andi  $24,$24,0x07
32500		 lh    $7,0x00($23)
32501		 sll   $24,$24,2
32502		 addu  $24,$24,$21
32503		 lw    $14,0x20($24)
32504		 addiu $23,$23,2
32505		 addu  $14,$14,$7
32506		 or    $2,$0,$16        	 # Check Carry
32507		 subu  $2,$0,$2
32508		 lw    $25,0x88($21)
32509		 sw    $15,m68k_ICount
32510		 or    $5,$0,$2
32511		 or    $4,$0,$14
32512		 jalr  $25
32513		 sw    $23,0x4C($21)    	 # Delay slot
32514		 lw    $15,m68k_ICount
32515		 addiu $15,$15,-16
32516		 bgez  $15,3f
32517		 lhu   $24,0x00($23)    	 # Delay slot
32518		 j     MainExit
32519	3:
32520		 sll   $7,$24,2         	 # Delay slot
32521		 addu  $7,$7,$30
32522		 lw    $7,0x00($7)
32523		 jr    $7
32524		 nop                    	 # Delay slot
32525
32526OP0_55f0:				#:
32527		 addiu $23,$23,2
32528
32529		 andi  $24,$24,0x07
32530		 sll   $24,$24,2
32531		 addu  $24,$24,$21
32532		 lw    $14,0x20($24)
32533		 lhu   $7,0x00($23)
32534		 addiu $23,$23,2
32535		 seb   $6,$7
32536		 or    $25,$0,$7
32537		 srl   $7,$7,12
32538		 andi  $25,$25,0x0800
32539		 sll   $7,$7,2
32540		 addu  $7,$7,$21
32541		 bne   $25,$0,0f
32542		 lw    $25,0x00($7)      	 # Delay slot
32543		 seh   $25,$25
32544	0:
32545		 addu  $25,$14,$25
32546		 addu  $14,$25,$6
32547		 or    $2,$0,$16        	 # Check Carry
32548		 subu  $2,$0,$2
32549		 lw    $25,0x88($21)
32550		 sw    $15,m68k_ICount
32551		 or    $5,$0,$2
32552		 or    $4,$0,$14
32553		 jalr  $25
32554		 sw    $23,0x4C($21)    	 # Delay slot
32555		 lw    $15,m68k_ICount
32556		 addiu $15,$15,-18
32557		 bgez  $15,3f
32558		 lhu   $24,0x00($23)    	 # Delay slot
32559		 j     MainExit
32560	3:
32561		 sll   $7,$24,2         	 # Delay slot
32562		 addu  $7,$7,$30
32563		 lw    $7,0x00($7)
32564		 jr    $7
32565		 nop                    	 # Delay slot
32566
32567OP0_55f8:				#:
32568		 addiu $23,$23,2
32569
32570		 lh    $14,0x00($23)
32571		 addiu $23,$23,2
32572		 or    $2,$0,$16        	 # Check Carry
32573		 subu  $2,$0,$2
32574		 lw    $25,0x88($21)
32575		 sw    $15,m68k_ICount
32576		 or    $5,$0,$2
32577		 or    $4,$0,$14
32578		 jalr  $25
32579		 sw    $23,0x4C($21)    	 # Delay slot
32580		 lw    $15,m68k_ICount
32581		 addiu $15,$15,-16
32582		 bgez  $15,3f
32583		 lhu   $24,0x00($23)    	 # Delay slot
32584		 j     MainExit
32585	3:
32586		 sll   $7,$24,2         	 # Delay slot
32587		 addu  $7,$7,$30
32588		 lw    $7,0x00($7)
32589		 jr    $7
32590		 nop                    	 # Delay slot
32591
32592OP0_55f9:				#:
32593		 addiu $23,$23,2
32594
32595		 lhu   $14,0x00($23)
32596		 lhu   $25,0x02($23)
32597		 sll   $14,$14,16
32598		 or    $14,$14,$25
32599		 addiu $23,$23,4
32600		 or    $2,$0,$16        	 # Check Carry
32601		 subu  $2,$0,$2
32602		 lw    $25,0x88($21)
32603		 sw    $15,m68k_ICount
32604		 or    $5,$0,$2
32605		 or    $4,$0,$14
32606		 jalr  $25
32607		 sw    $23,0x4C($21)    	 # Delay slot
32608		 lw    $15,m68k_ICount
32609		 addiu $15,$15,-20
32610		 bgez  $15,3f
32611		 lhu   $24,0x00($23)    	 # Delay slot
32612		 j     MainExit
32613	3:
32614		 sll   $7,$24,2         	 # Delay slot
32615		 addu  $7,$7,$30
32616		 lw    $7,0x00($7)
32617		 jr    $7
32618		 nop                    	 # Delay slot
32619
32620OP0_56c0:				#:
32621		 addiu $23,$23,2
32622
32623		 andi  $24,$24,0x07
32624		 xori  $2,$18,1         	 # Check Zero
32625		 subu  $2,$0,$2
32626		 sll   $24,$24,2
32627		 addu  $24,$24,$21
32628		 sb    $2,0x00($24)
32629		 andi  $2,$2,0x02
32630		 addiu $15,$15,-4
32631		 subu  $15,$15,$2
32632		 bgez  $15,3f
32633		 lhu   $24,0x00($23)    	 # Delay slot
32634		 j     MainExit
32635	3:
32636		 sll   $7,$24,2         	 # Delay slot
32637		 addu  $7,$7,$30
32638		 lw    $7,0x00($7)
32639		 jr    $7
32640		 nop                    	 # Delay slot
32641
32642OP0_56c8:				#:
32643		 beq   $18,$0,1f        	 # Check zero
32644		 andi  $24,$24,0x07     	 # Delay slot
32645		 sll   $24,$24,2
32646		 addu  $24,$24,$21
32647		 lhu   $8,0x00($24)
32648		 addiu $9,$8,-1
32649		 beq   $8,$0,9f         	 # Is it -1
32650		 sh    $9,0x00($24)     	 # Delay slot
32651
32652		 addiu $23,$23,2
32653
32654		 lh    $2,0x00($23)
32655		 addu  $23,$23,$2
32656		 addiu $15,$15,-10
32657		 bgez  $15,3f
32658		 lhu   $24,0x00($23)    	 # Delay slot
32659		 j     MainExit
32660	3:
32661		 sll   $7,$24,2         	 # Delay slot
32662		 addu  $7,$7,$30
32663		 lw    $7,0x00($7)
32664		 jr    $7
32665		 nop                    	 # Delay slot
32666
32667	9:
32668	1:
32669		 addiu $23,$23,4
32670
32671		 addiu $15,$15,-12
32672		 bgez  $15,3f
32673		 lhu   $24,0x00($23)    	 # Delay slot
32674		 j     MainExit
32675	3:
32676		 sll   $7,$24,2         	 # Delay slot
32677		 addu  $7,$7,$30
32678		 lw    $7,0x00($7)
32679		 jr    $7
32680		 nop                    	 # Delay slot
32681
32682OP0_56d0:				#:
32683		 addiu $23,$23,2
32684
32685		 andi  $24,$24,0x07
32686		 sll   $24,$24,2
32687		 addu  $24,$24,$21
32688		 lw    $14,0x20($24)
32689		 xori  $2,$18,1         	 # Check Zero
32690		 subu  $2,$0,$2
32691		 lw    $25,0x88($21)
32692		 sw    $15,m68k_ICount
32693		 or    $5,$0,$2
32694		 or    $4,$0,$14
32695		 jalr  $25
32696		 sw    $23,0x4C($21)    	 # Delay slot
32697		 lw    $15,m68k_ICount
32698		 addiu $15,$15,-12
32699		 bgez  $15,3f
32700		 lhu   $24,0x00($23)    	 # Delay slot
32701		 j     MainExit
32702	3:
32703		 sll   $7,$24,2         	 # Delay slot
32704		 addu  $7,$7,$30
32705		 lw    $7,0x00($7)
32706		 jr    $7
32707		 nop                    	 # Delay slot
32708
32709OP0_56d8:				#:
32710		 addiu $23,$23,2
32711
32712		 andi  $24,$24,0x07
32713		 sll   $24,$24,2
32714		 addu  $24,$24,$21
32715		 lw    $14,0x20($24)
32716		 addiu $25,$14,1
32717		 sw    $25,0x20($24)
32718		 xori  $2,$18,1         	 # Check Zero
32719		 subu  $2,$0,$2
32720		 lw    $25,0x88($21)
32721		 sw    $15,m68k_ICount
32722		 or    $5,$0,$2
32723		 or    $4,$0,$14
32724		 jalr  $25
32725		 sw    $23,0x4C($21)    	 # Delay slot
32726		 lw    $15,m68k_ICount
32727		 addiu $15,$15,-12
32728		 bgez  $15,3f
32729		 lhu   $24,0x00($23)    	 # Delay slot
32730		 j     MainExit
32731	3:
32732		 sll   $7,$24,2         	 # Delay slot
32733		 addu  $7,$7,$30
32734		 lw    $7,0x00($7)
32735		 jr    $7
32736		 nop                    	 # Delay slot
32737
32738OP0_56df:				#:
32739		 addiu $23,$23,2
32740
32741		 lw    $14,0x3C($21)    	 # Get A7
32742		 addiu $25,$14,2
32743		 sw    $25,0x3C($21)
32744		 xori  $2,$18,1         	 # Check Zero
32745		 subu  $2,$0,$2
32746		 lw    $25,0x88($21)
32747		 sw    $15,m68k_ICount
32748		 or    $5,$0,$2
32749		 or    $4,$0,$14
32750		 jalr  $25
32751		 sw    $23,0x4C($21)    	 # Delay slot
32752		 lw    $15,m68k_ICount
32753		 addiu $15,$15,-12
32754		 bgez  $15,3f
32755		 lhu   $24,0x00($23)    	 # Delay slot
32756		 j     MainExit
32757	3:
32758		 sll   $7,$24,2         	 # Delay slot
32759		 addu  $7,$7,$30
32760		 lw    $7,0x00($7)
32761		 jr    $7
32762		 nop                    	 # Delay slot
32763
32764OP0_56e0:				#:
32765		 addiu $23,$23,2
32766
32767		 andi  $24,$24,0x07
32768		 sll   $24,$24,2
32769		 addu  $24,$24,$21
32770		 lw    $14,0x20($24)
32771		 addiu $14,$14,-1
32772		 sw    $14,0x20($24)
32773		 xori  $2,$18,1         	 # Check Zero
32774		 subu  $2,$0,$2
32775		 lw    $25,0x88($21)
32776		 sw    $15,m68k_ICount
32777		 or    $5,$0,$2
32778		 or    $4,$0,$14
32779		 jalr  $25
32780		 sw    $23,0x4C($21)    	 # Delay slot
32781		 lw    $15,m68k_ICount
32782		 addiu $15,$15,-14
32783		 bgez  $15,3f
32784		 lhu   $24,0x00($23)    	 # Delay slot
32785		 j     MainExit
32786	3:
32787		 sll   $7,$24,2         	 # Delay slot
32788		 addu  $7,$7,$30
32789		 lw    $7,0x00($7)
32790		 jr    $7
32791		 nop                    	 # Delay slot
32792
32793OP0_56e7:				#:
32794		 addiu $23,$23,2
32795
32796		 lw    $14,0x3C($21)    	 # Get A7
32797		 addiu $14,$14,-2
32798		 sw    $14,0x3C($21)
32799		 xori  $2,$18,1         	 # Check Zero
32800		 subu  $2,$0,$2
32801		 lw    $25,0x88($21)
32802		 sw    $15,m68k_ICount
32803		 or    $5,$0,$2
32804		 or    $4,$0,$14
32805		 jalr  $25
32806		 sw    $23,0x4C($21)    	 # Delay slot
32807		 lw    $15,m68k_ICount
32808		 addiu $15,$15,-14
32809		 bgez  $15,3f
32810		 lhu   $24,0x00($23)    	 # Delay slot
32811		 j     MainExit
32812	3:
32813		 sll   $7,$24,2         	 # Delay slot
32814		 addu  $7,$7,$30
32815		 lw    $7,0x00($7)
32816		 jr    $7
32817		 nop                    	 # Delay slot
32818
32819OP0_56e8:				#:
32820		 addiu $23,$23,2
32821
32822		 andi  $24,$24,0x07
32823		 lh    $7,0x00($23)
32824		 sll   $24,$24,2
32825		 addu  $24,$24,$21
32826		 lw    $14,0x20($24)
32827		 addiu $23,$23,2
32828		 addu  $14,$14,$7
32829		 xori  $2,$18,1         	 # Check Zero
32830		 subu  $2,$0,$2
32831		 lw    $25,0x88($21)
32832		 sw    $15,m68k_ICount
32833		 or    $5,$0,$2
32834		 or    $4,$0,$14
32835		 jalr  $25
32836		 sw    $23,0x4C($21)    	 # Delay slot
32837		 lw    $15,m68k_ICount
32838		 addiu $15,$15,-16
32839		 bgez  $15,3f
32840		 lhu   $24,0x00($23)    	 # Delay slot
32841		 j     MainExit
32842	3:
32843		 sll   $7,$24,2         	 # Delay slot
32844		 addu  $7,$7,$30
32845		 lw    $7,0x00($7)
32846		 jr    $7
32847		 nop                    	 # Delay slot
32848
32849OP0_56f0:				#:
32850		 addiu $23,$23,2
32851
32852		 andi  $24,$24,0x07
32853		 sll   $24,$24,2
32854		 addu  $24,$24,$21
32855		 lw    $14,0x20($24)
32856		 lhu   $7,0x00($23)
32857		 addiu $23,$23,2
32858		 seb   $6,$7
32859		 or    $25,$0,$7
32860		 srl   $7,$7,12
32861		 andi  $25,$25,0x0800
32862		 sll   $7,$7,2
32863		 addu  $7,$7,$21
32864		 bne   $25,$0,0f
32865		 lw    $25,0x00($7)      	 # Delay slot
32866		 seh   $25,$25
32867	0:
32868		 addu  $25,$14,$25
32869		 addu  $14,$25,$6
32870		 xori  $2,$18,1         	 # Check Zero
32871		 subu  $2,$0,$2
32872		 lw    $25,0x88($21)
32873		 sw    $15,m68k_ICount
32874		 or    $5,$0,$2
32875		 or    $4,$0,$14
32876		 jalr  $25
32877		 sw    $23,0x4C($21)    	 # Delay slot
32878		 lw    $15,m68k_ICount
32879		 addiu $15,$15,-18
32880		 bgez  $15,3f
32881		 lhu   $24,0x00($23)    	 # Delay slot
32882		 j     MainExit
32883	3:
32884		 sll   $7,$24,2         	 # Delay slot
32885		 addu  $7,$7,$30
32886		 lw    $7,0x00($7)
32887		 jr    $7
32888		 nop                    	 # Delay slot
32889
32890OP0_56f8:				#:
32891		 addiu $23,$23,2
32892
32893		 lh    $14,0x00($23)
32894		 addiu $23,$23,2
32895		 xori  $2,$18,1         	 # Check Zero
32896		 subu  $2,$0,$2
32897		 lw    $25,0x88($21)
32898		 sw    $15,m68k_ICount
32899		 or    $5,$0,$2
32900		 or    $4,$0,$14
32901		 jalr  $25
32902		 sw    $23,0x4C($21)    	 # Delay slot
32903		 lw    $15,m68k_ICount
32904		 addiu $15,$15,-16
32905		 bgez  $15,3f
32906		 lhu   $24,0x00($23)    	 # Delay slot
32907		 j     MainExit
32908	3:
32909		 sll   $7,$24,2         	 # Delay slot
32910		 addu  $7,$7,$30
32911		 lw    $7,0x00($7)
32912		 jr    $7
32913		 nop                    	 # Delay slot
32914
32915OP0_56f9:				#:
32916		 addiu $23,$23,2
32917
32918		 lhu   $14,0x00($23)
32919		 lhu   $25,0x02($23)
32920		 sll   $14,$14,16
32921		 or    $14,$14,$25
32922		 addiu $23,$23,4
32923		 xori  $2,$18,1         	 # Check Zero
32924		 subu  $2,$0,$2
32925		 lw    $25,0x88($21)
32926		 sw    $15,m68k_ICount
32927		 or    $5,$0,$2
32928		 or    $4,$0,$14
32929		 jalr  $25
32930		 sw    $23,0x4C($21)    	 # Delay slot
32931		 lw    $15,m68k_ICount
32932		 addiu $15,$15,-20
32933		 bgez  $15,3f
32934		 lhu   $24,0x00($23)    	 # Delay slot
32935		 j     MainExit
32936	3:
32937		 sll   $7,$24,2         	 # Delay slot
32938		 addu  $7,$7,$30
32939		 lw    $7,0x00($7)
32940		 jr    $7
32941		 nop                    	 # Delay slot
32942
32943OP0_57c0:				#:
32944		 addiu $23,$23,2
32945
32946		 andi  $24,$24,0x07
32947		 or    $2,$0,$18        	 # Check Zero
32948		 subu  $2,$0,$2
32949		 sll   $24,$24,2
32950		 addu  $24,$24,$21
32951		 sb    $2,0x00($24)
32952		 andi  $2,$2,0x02
32953		 addiu $15,$15,-4
32954		 subu  $15,$15,$2
32955		 bgez  $15,3f
32956		 lhu   $24,0x00($23)    	 # Delay slot
32957		 j     MainExit
32958	3:
32959		 sll   $7,$24,2         	 # Delay slot
32960		 addu  $7,$7,$30
32961		 lw    $7,0x00($7)
32962		 jr    $7
32963		 nop                    	 # Delay slot
32964
32965OP0_57c8:				#:
32966		 bne   $18,$0,1f        	 # Check zero
32967		 andi  $24,$24,0x07     	 # Delay slot
32968		 sll   $24,$24,2
32969		 addu  $24,$24,$21
32970		 lhu   $8,0x00($24)
32971		 addiu $9,$8,-1
32972		 beq   $8,$0,9f         	 # Is it -1
32973		 sh    $9,0x00($24)     	 # Delay slot
32974
32975		 addiu $23,$23,2
32976
32977		 lh    $2,0x00($23)
32978		 addu  $23,$23,$2
32979		 addiu $15,$15,-10
32980		 bgez  $15,3f
32981		 lhu   $24,0x00($23)    	 # Delay slot
32982		 j     MainExit
32983	3:
32984		 sll   $7,$24,2         	 # Delay slot
32985		 addu  $7,$7,$30
32986		 lw    $7,0x00($7)
32987		 jr    $7
32988		 nop                    	 # Delay slot
32989
32990	9:
32991	1:
32992		 addiu $23,$23,4
32993
32994		 addiu $15,$15,-12
32995		 bgez  $15,3f
32996		 lhu   $24,0x00($23)    	 # Delay slot
32997		 j     MainExit
32998	3:
32999		 sll   $7,$24,2         	 # Delay slot
33000		 addu  $7,$7,$30
33001		 lw    $7,0x00($7)
33002		 jr    $7
33003		 nop                    	 # Delay slot
33004
33005OP0_57d0:				#:
33006		 addiu $23,$23,2
33007
33008		 andi  $24,$24,0x07
33009		 sll   $24,$24,2
33010		 addu  $24,$24,$21
33011		 lw    $14,0x20($24)
33012		 or    $2,$0,$18        	 # Check Zero
33013		 subu  $2,$0,$2
33014		 lw    $25,0x88($21)
33015		 sw    $15,m68k_ICount
33016		 or    $5,$0,$2
33017		 or    $4,$0,$14
33018		 jalr  $25
33019		 sw    $23,0x4C($21)    	 # Delay slot
33020		 lw    $15,m68k_ICount
33021		 addiu $15,$15,-12
33022		 bgez  $15,3f
33023		 lhu   $24,0x00($23)    	 # Delay slot
33024		 j     MainExit
33025	3:
33026		 sll   $7,$24,2         	 # Delay slot
33027		 addu  $7,$7,$30
33028		 lw    $7,0x00($7)
33029		 jr    $7
33030		 nop                    	 # Delay slot
33031
33032OP0_57d8:				#:
33033		 addiu $23,$23,2
33034
33035		 andi  $24,$24,0x07
33036		 sll   $24,$24,2
33037		 addu  $24,$24,$21
33038		 lw    $14,0x20($24)
33039		 addiu $25,$14,1
33040		 sw    $25,0x20($24)
33041		 or    $2,$0,$18        	 # Check Zero
33042		 subu  $2,$0,$2
33043		 lw    $25,0x88($21)
33044		 sw    $15,m68k_ICount
33045		 or    $5,$0,$2
33046		 or    $4,$0,$14
33047		 jalr  $25
33048		 sw    $23,0x4C($21)    	 # Delay slot
33049		 lw    $15,m68k_ICount
33050		 addiu $15,$15,-12
33051		 bgez  $15,3f
33052		 lhu   $24,0x00($23)    	 # Delay slot
33053		 j     MainExit
33054	3:
33055		 sll   $7,$24,2         	 # Delay slot
33056		 addu  $7,$7,$30
33057		 lw    $7,0x00($7)
33058		 jr    $7
33059		 nop                    	 # Delay slot
33060
33061OP0_57df:				#:
33062		 addiu $23,$23,2
33063
33064		 lw    $14,0x3C($21)    	 # Get A7
33065		 addiu $25,$14,2
33066		 sw    $25,0x3C($21)
33067		 or    $2,$0,$18        	 # Check Zero
33068		 subu  $2,$0,$2
33069		 lw    $25,0x88($21)
33070		 sw    $15,m68k_ICount
33071		 or    $5,$0,$2
33072		 or    $4,$0,$14
33073		 jalr  $25
33074		 sw    $23,0x4C($21)    	 # Delay slot
33075		 lw    $15,m68k_ICount
33076		 addiu $15,$15,-12
33077		 bgez  $15,3f
33078		 lhu   $24,0x00($23)    	 # Delay slot
33079		 j     MainExit
33080	3:
33081		 sll   $7,$24,2         	 # Delay slot
33082		 addu  $7,$7,$30
33083		 lw    $7,0x00($7)
33084		 jr    $7
33085		 nop                    	 # Delay slot
33086
33087OP0_57e0:				#:
33088		 addiu $23,$23,2
33089
33090		 andi  $24,$24,0x07
33091		 sll   $24,$24,2
33092		 addu  $24,$24,$21
33093		 lw    $14,0x20($24)
33094		 addiu $14,$14,-1
33095		 sw    $14,0x20($24)
33096		 or    $2,$0,$18        	 # Check Zero
33097		 subu  $2,$0,$2
33098		 lw    $25,0x88($21)
33099		 sw    $15,m68k_ICount
33100		 or    $5,$0,$2
33101		 or    $4,$0,$14
33102		 jalr  $25
33103		 sw    $23,0x4C($21)    	 # Delay slot
33104		 lw    $15,m68k_ICount
33105		 addiu $15,$15,-14
33106		 bgez  $15,3f
33107		 lhu   $24,0x00($23)    	 # Delay slot
33108		 j     MainExit
33109	3:
33110		 sll   $7,$24,2         	 # Delay slot
33111		 addu  $7,$7,$30
33112		 lw    $7,0x00($7)
33113		 jr    $7
33114		 nop                    	 # Delay slot
33115
33116OP0_57e7:				#:
33117		 addiu $23,$23,2
33118
33119		 lw    $14,0x3C($21)    	 # Get A7
33120		 addiu $14,$14,-2
33121		 sw    $14,0x3C($21)
33122		 or    $2,$0,$18        	 # Check Zero
33123		 subu  $2,$0,$2
33124		 lw    $25,0x88($21)
33125		 sw    $15,m68k_ICount
33126		 or    $5,$0,$2
33127		 or    $4,$0,$14
33128		 jalr  $25
33129		 sw    $23,0x4C($21)    	 # Delay slot
33130		 lw    $15,m68k_ICount
33131		 addiu $15,$15,-14
33132		 bgez  $15,3f
33133		 lhu   $24,0x00($23)    	 # Delay slot
33134		 j     MainExit
33135	3:
33136		 sll   $7,$24,2         	 # Delay slot
33137		 addu  $7,$7,$30
33138		 lw    $7,0x00($7)
33139		 jr    $7
33140		 nop                    	 # Delay slot
33141
33142OP0_57e8:				#:
33143		 addiu $23,$23,2
33144
33145		 andi  $24,$24,0x07
33146		 lh    $7,0x00($23)
33147		 sll   $24,$24,2
33148		 addu  $24,$24,$21
33149		 lw    $14,0x20($24)
33150		 addiu $23,$23,2
33151		 addu  $14,$14,$7
33152		 or    $2,$0,$18        	 # Check Zero
33153		 subu  $2,$0,$2
33154		 lw    $25,0x88($21)
33155		 sw    $15,m68k_ICount
33156		 or    $5,$0,$2
33157		 or    $4,$0,$14
33158		 jalr  $25
33159		 sw    $23,0x4C($21)    	 # Delay slot
33160		 lw    $15,m68k_ICount
33161		 addiu $15,$15,-16
33162		 bgez  $15,3f
33163		 lhu   $24,0x00($23)    	 # Delay slot
33164		 j     MainExit
33165	3:
33166		 sll   $7,$24,2         	 # Delay slot
33167		 addu  $7,$7,$30
33168		 lw    $7,0x00($7)
33169		 jr    $7
33170		 nop                    	 # Delay slot
33171
33172OP0_57f0:				#:
33173		 addiu $23,$23,2
33174
33175		 andi  $24,$24,0x07
33176		 sll   $24,$24,2
33177		 addu  $24,$24,$21
33178		 lw    $14,0x20($24)
33179		 lhu   $7,0x00($23)
33180		 addiu $23,$23,2
33181		 seb   $6,$7
33182		 or    $25,$0,$7
33183		 srl   $7,$7,12
33184		 andi  $25,$25,0x0800
33185		 sll   $7,$7,2
33186		 addu  $7,$7,$21
33187		 bne   $25,$0,0f
33188		 lw    $25,0x00($7)      	 # Delay slot
33189		 seh   $25,$25
33190	0:
33191		 addu  $25,$14,$25
33192		 addu  $14,$25,$6
33193		 or    $2,$0,$18        	 # Check Zero
33194		 subu  $2,$0,$2
33195		 lw    $25,0x88($21)
33196		 sw    $15,m68k_ICount
33197		 or    $5,$0,$2
33198		 or    $4,$0,$14
33199		 jalr  $25
33200		 sw    $23,0x4C($21)    	 # Delay slot
33201		 lw    $15,m68k_ICount
33202		 addiu $15,$15,-18
33203		 bgez  $15,3f
33204		 lhu   $24,0x00($23)    	 # Delay slot
33205		 j     MainExit
33206	3:
33207		 sll   $7,$24,2         	 # Delay slot
33208		 addu  $7,$7,$30
33209		 lw    $7,0x00($7)
33210		 jr    $7
33211		 nop                    	 # Delay slot
33212
33213OP0_57f8:				#:
33214		 addiu $23,$23,2
33215
33216		 lh    $14,0x00($23)
33217		 addiu $23,$23,2
33218		 or    $2,$0,$18        	 # Check Zero
33219		 subu  $2,$0,$2
33220		 lw    $25,0x88($21)
33221		 sw    $15,m68k_ICount
33222		 or    $5,$0,$2
33223		 or    $4,$0,$14
33224		 jalr  $25
33225		 sw    $23,0x4C($21)    	 # Delay slot
33226		 lw    $15,m68k_ICount
33227		 addiu $15,$15,-16
33228		 bgez  $15,3f
33229		 lhu   $24,0x00($23)    	 # Delay slot
33230		 j     MainExit
33231	3:
33232		 sll   $7,$24,2         	 # Delay slot
33233		 addu  $7,$7,$30
33234		 lw    $7,0x00($7)
33235		 jr    $7
33236		 nop                    	 # Delay slot
33237
33238OP0_57f9:				#:
33239		 addiu $23,$23,2
33240
33241		 lhu   $14,0x00($23)
33242		 lhu   $25,0x02($23)
33243		 sll   $14,$14,16
33244		 or    $14,$14,$25
33245		 addiu $23,$23,4
33246		 or    $2,$0,$18        	 # Check Zero
33247		 subu  $2,$0,$2
33248		 lw    $25,0x88($21)
33249		 sw    $15,m68k_ICount
33250		 or    $5,$0,$2
33251		 or    $4,$0,$14
33252		 jalr  $25
33253		 sw    $23,0x4C($21)    	 # Delay slot
33254		 lw    $15,m68k_ICount
33255		 addiu $15,$15,-20
33256		 bgez  $15,3f
33257		 lhu   $24,0x00($23)    	 # Delay slot
33258		 j     MainExit
33259	3:
33260		 sll   $7,$24,2         	 # Delay slot
33261		 addu  $7,$7,$30
33262		 lw    $7,0x00($7)
33263		 jr    $7
33264		 nop                    	 # Delay slot
33265
33266OP0_58c0:				#:
33267		 addiu $23,$23,2
33268
33269		 andi  $24,$24,0x07
33270		 xori  $2,$17,1         	 # Check Overflow
33271		 subu  $2,$0,$2
33272		 sll   $24,$24,2
33273		 addu  $24,$24,$21
33274		 sb    $2,0x00($24)
33275		 andi  $2,$2,0x02
33276		 addiu $15,$15,-4
33277		 subu  $15,$15,$2
33278		 bgez  $15,3f
33279		 lhu   $24,0x00($23)    	 # Delay slot
33280		 j     MainExit
33281	3:
33282		 sll   $7,$24,2         	 # Delay slot
33283		 addu  $7,$7,$30
33284		 lw    $7,0x00($7)
33285		 jr    $7
33286		 nop                    	 # Delay slot
33287
33288OP0_58c8:				#:
33289		 beq   $17,$0,1f        	 # Check Overflow
33290		 andi  $24,$24,0x07     	 # Delay slot
33291		 sll   $24,$24,2
33292		 addu  $24,$24,$21
33293		 lhu   $8,0x00($24)
33294		 addiu $9,$8,-1
33295		 beq   $8,$0,9f         	 # Is it -1
33296		 sh    $9,0x00($24)     	 # Delay slot
33297
33298		 addiu $23,$23,2
33299
33300		 lh    $2,0x00($23)
33301		 addu  $23,$23,$2
33302		 addiu $15,$15,-10
33303		 bgez  $15,3f
33304		 lhu   $24,0x00($23)    	 # Delay slot
33305		 j     MainExit
33306	3:
33307		 sll   $7,$24,2         	 # Delay slot
33308		 addu  $7,$7,$30
33309		 lw    $7,0x00($7)
33310		 jr    $7
33311		 nop                    	 # Delay slot
33312
33313	9:
33314	1:
33315		 addiu $23,$23,4
33316
33317		 addiu $15,$15,-12
33318		 bgez  $15,3f
33319		 lhu   $24,0x00($23)    	 # Delay slot
33320		 j     MainExit
33321	3:
33322		 sll   $7,$24,2         	 # Delay slot
33323		 addu  $7,$7,$30
33324		 lw    $7,0x00($7)
33325		 jr    $7
33326		 nop                    	 # Delay slot
33327
33328OP0_58d0:				#:
33329		 addiu $23,$23,2
33330
33331		 andi  $24,$24,0x07
33332		 sll   $24,$24,2
33333		 addu  $24,$24,$21
33334		 lw    $14,0x20($24)
33335		 xori  $2,$17,1         	 # Check Overflow
33336		 subu  $2,$0,$2
33337		 lw    $25,0x88($21)
33338		 sw    $15,m68k_ICount
33339		 or    $5,$0,$2
33340		 or    $4,$0,$14
33341		 jalr  $25
33342		 sw    $23,0x4C($21)    	 # Delay slot
33343		 lw    $15,m68k_ICount
33344		 addiu $15,$15,-12
33345		 bgez  $15,3f
33346		 lhu   $24,0x00($23)    	 # Delay slot
33347		 j     MainExit
33348	3:
33349		 sll   $7,$24,2         	 # Delay slot
33350		 addu  $7,$7,$30
33351		 lw    $7,0x00($7)
33352		 jr    $7
33353		 nop                    	 # Delay slot
33354
33355OP0_58d8:				#:
33356		 addiu $23,$23,2
33357
33358		 andi  $24,$24,0x07
33359		 sll   $24,$24,2
33360		 addu  $24,$24,$21
33361		 lw    $14,0x20($24)
33362		 addiu $25,$14,1
33363		 sw    $25,0x20($24)
33364		 xori  $2,$17,1         	 # Check Overflow
33365		 subu  $2,$0,$2
33366		 lw    $25,0x88($21)
33367		 sw    $15,m68k_ICount
33368		 or    $5,$0,$2
33369		 or    $4,$0,$14
33370		 jalr  $25
33371		 sw    $23,0x4C($21)    	 # Delay slot
33372		 lw    $15,m68k_ICount
33373		 addiu $15,$15,-12
33374		 bgez  $15,3f
33375		 lhu   $24,0x00($23)    	 # Delay slot
33376		 j     MainExit
33377	3:
33378		 sll   $7,$24,2         	 # Delay slot
33379		 addu  $7,$7,$30
33380		 lw    $7,0x00($7)
33381		 jr    $7
33382		 nop                    	 # Delay slot
33383
33384OP0_58df:				#:
33385		 addiu $23,$23,2
33386
33387		 lw    $14,0x3C($21)    	 # Get A7
33388		 addiu $25,$14,2
33389		 sw    $25,0x3C($21)
33390		 xori  $2,$17,1         	 # Check Overflow
33391		 subu  $2,$0,$2
33392		 lw    $25,0x88($21)
33393		 sw    $15,m68k_ICount
33394		 or    $5,$0,$2
33395		 or    $4,$0,$14
33396		 jalr  $25
33397		 sw    $23,0x4C($21)    	 # Delay slot
33398		 lw    $15,m68k_ICount
33399		 addiu $15,$15,-12
33400		 bgez  $15,3f
33401		 lhu   $24,0x00($23)    	 # Delay slot
33402		 j     MainExit
33403	3:
33404		 sll   $7,$24,2         	 # Delay slot
33405		 addu  $7,$7,$30
33406		 lw    $7,0x00($7)
33407		 jr    $7
33408		 nop                    	 # Delay slot
33409
33410OP0_58e0:				#:
33411		 addiu $23,$23,2
33412
33413		 andi  $24,$24,0x07
33414		 sll   $24,$24,2
33415		 addu  $24,$24,$21
33416		 lw    $14,0x20($24)
33417		 addiu $14,$14,-1
33418		 sw    $14,0x20($24)
33419		 xori  $2,$17,1         	 # Check Overflow
33420		 subu  $2,$0,$2
33421		 lw    $25,0x88($21)
33422		 sw    $15,m68k_ICount
33423		 or    $5,$0,$2
33424		 or    $4,$0,$14
33425		 jalr  $25
33426		 sw    $23,0x4C($21)    	 # Delay slot
33427		 lw    $15,m68k_ICount
33428		 addiu $15,$15,-14
33429		 bgez  $15,3f
33430		 lhu   $24,0x00($23)    	 # Delay slot
33431		 j     MainExit
33432	3:
33433		 sll   $7,$24,2         	 # Delay slot
33434		 addu  $7,$7,$30
33435		 lw    $7,0x00($7)
33436		 jr    $7
33437		 nop                    	 # Delay slot
33438
33439OP0_58e7:				#:
33440		 addiu $23,$23,2
33441
33442		 lw    $14,0x3C($21)    	 # Get A7
33443		 addiu $14,$14,-2
33444		 sw    $14,0x3C($21)
33445		 xori  $2,$17,1         	 # Check Overflow
33446		 subu  $2,$0,$2
33447		 lw    $25,0x88($21)
33448		 sw    $15,m68k_ICount
33449		 or    $5,$0,$2
33450		 or    $4,$0,$14
33451		 jalr  $25
33452		 sw    $23,0x4C($21)    	 # Delay slot
33453		 lw    $15,m68k_ICount
33454		 addiu $15,$15,-14
33455		 bgez  $15,3f
33456		 lhu   $24,0x00($23)    	 # Delay slot
33457		 j     MainExit
33458	3:
33459		 sll   $7,$24,2         	 # Delay slot
33460		 addu  $7,$7,$30
33461		 lw    $7,0x00($7)
33462		 jr    $7
33463		 nop                    	 # Delay slot
33464
33465OP0_58e8:				#:
33466		 addiu $23,$23,2
33467
33468		 andi  $24,$24,0x07
33469		 lh    $7,0x00($23)
33470		 sll   $24,$24,2
33471		 addu  $24,$24,$21
33472		 lw    $14,0x20($24)
33473		 addiu $23,$23,2
33474		 addu  $14,$14,$7
33475		 xori  $2,$17,1         	 # Check Overflow
33476		 subu  $2,$0,$2
33477		 lw    $25,0x88($21)
33478		 sw    $15,m68k_ICount
33479		 or    $5,$0,$2
33480		 or    $4,$0,$14
33481		 jalr  $25
33482		 sw    $23,0x4C($21)    	 # Delay slot
33483		 lw    $15,m68k_ICount
33484		 addiu $15,$15,-16
33485		 bgez  $15,3f
33486		 lhu   $24,0x00($23)    	 # Delay slot
33487		 j     MainExit
33488	3:
33489		 sll   $7,$24,2         	 # Delay slot
33490		 addu  $7,$7,$30
33491		 lw    $7,0x00($7)
33492		 jr    $7
33493		 nop                    	 # Delay slot
33494
33495OP0_58f0:				#:
33496		 addiu $23,$23,2
33497
33498		 andi  $24,$24,0x07
33499		 sll   $24,$24,2
33500		 addu  $24,$24,$21
33501		 lw    $14,0x20($24)
33502		 lhu   $7,0x00($23)
33503		 addiu $23,$23,2
33504		 seb   $6,$7
33505		 or    $25,$0,$7
33506		 srl   $7,$7,12
33507		 andi  $25,$25,0x0800
33508		 sll   $7,$7,2
33509		 addu  $7,$7,$21
33510		 bne   $25,$0,0f
33511		 lw    $25,0x00($7)      	 # Delay slot
33512		 seh   $25,$25
33513	0:
33514		 addu  $25,$14,$25
33515		 addu  $14,$25,$6
33516		 xori  $2,$17,1         	 # Check Overflow
33517		 subu  $2,$0,$2
33518		 lw    $25,0x88($21)
33519		 sw    $15,m68k_ICount
33520		 or    $5,$0,$2
33521		 or    $4,$0,$14
33522		 jalr  $25
33523		 sw    $23,0x4C($21)    	 # Delay slot
33524		 lw    $15,m68k_ICount
33525		 addiu $15,$15,-18
33526		 bgez  $15,3f
33527		 lhu   $24,0x00($23)    	 # Delay slot
33528		 j     MainExit
33529	3:
33530		 sll   $7,$24,2         	 # Delay slot
33531		 addu  $7,$7,$30
33532		 lw    $7,0x00($7)
33533		 jr    $7
33534		 nop                    	 # Delay slot
33535
33536OP0_58f8:				#:
33537		 addiu $23,$23,2
33538
33539		 lh    $14,0x00($23)
33540		 addiu $23,$23,2
33541		 xori  $2,$17,1         	 # Check Overflow
33542		 subu  $2,$0,$2
33543		 lw    $25,0x88($21)
33544		 sw    $15,m68k_ICount
33545		 or    $5,$0,$2
33546		 or    $4,$0,$14
33547		 jalr  $25
33548		 sw    $23,0x4C($21)    	 # Delay slot
33549		 lw    $15,m68k_ICount
33550		 addiu $15,$15,-16
33551		 bgez  $15,3f
33552		 lhu   $24,0x00($23)    	 # Delay slot
33553		 j     MainExit
33554	3:
33555		 sll   $7,$24,2         	 # Delay slot
33556		 addu  $7,$7,$30
33557		 lw    $7,0x00($7)
33558		 jr    $7
33559		 nop                    	 # Delay slot
33560
33561OP0_58f9:				#:
33562		 addiu $23,$23,2
33563
33564		 lhu   $14,0x00($23)
33565		 lhu   $25,0x02($23)
33566		 sll   $14,$14,16
33567		 or    $14,$14,$25
33568		 addiu $23,$23,4
33569		 xori  $2,$17,1         	 # Check Overflow
33570		 subu  $2,$0,$2
33571		 lw    $25,0x88($21)
33572		 sw    $15,m68k_ICount
33573		 or    $5,$0,$2
33574		 or    $4,$0,$14
33575		 jalr  $25
33576		 sw    $23,0x4C($21)    	 # Delay slot
33577		 lw    $15,m68k_ICount
33578		 addiu $15,$15,-20
33579		 bgez  $15,3f
33580		 lhu   $24,0x00($23)    	 # Delay slot
33581		 j     MainExit
33582	3:
33583		 sll   $7,$24,2         	 # Delay slot
33584		 addu  $7,$7,$30
33585		 lw    $7,0x00($7)
33586		 jr    $7
33587		 nop                    	 # Delay slot
33588
33589OP0_59c0:				#:
33590		 addiu $23,$23,2
33591
33592		 andi  $24,$24,0x07
33593		 or    $2,$0,$17        	 # Check Overflow
33594		 subu  $2,$0,$2
33595		 sll   $24,$24,2
33596		 addu  $24,$24,$21
33597		 sb    $2,0x00($24)
33598		 andi  $2,$2,0x02
33599		 addiu $15,$15,-4
33600		 subu  $15,$15,$2
33601		 bgez  $15,3f
33602		 lhu   $24,0x00($23)    	 # Delay slot
33603		 j     MainExit
33604	3:
33605		 sll   $7,$24,2         	 # Delay slot
33606		 addu  $7,$7,$30
33607		 lw    $7,0x00($7)
33608		 jr    $7
33609		 nop                    	 # Delay slot
33610
33611OP0_59c8:				#:
33612		 bne   $17,$0,1f        	 # Check Overflow
33613		 andi  $24,$24,0x07     	 # Delay slot
33614		 sll   $24,$24,2
33615		 addu  $24,$24,$21
33616		 lhu   $8,0x00($24)
33617		 addiu $9,$8,-1
33618		 beq   $8,$0,9f         	 # Is it -1
33619		 sh    $9,0x00($24)     	 # Delay slot
33620
33621		 addiu $23,$23,2
33622
33623		 lh    $2,0x00($23)
33624		 addu  $23,$23,$2
33625		 addiu $15,$15,-10
33626		 bgez  $15,3f
33627		 lhu   $24,0x00($23)    	 # Delay slot
33628		 j     MainExit
33629	3:
33630		 sll   $7,$24,2         	 # Delay slot
33631		 addu  $7,$7,$30
33632		 lw    $7,0x00($7)
33633		 jr    $7
33634		 nop                    	 # Delay slot
33635
33636	9:
33637	1:
33638		 addiu $23,$23,4
33639
33640		 addiu $15,$15,-12
33641		 bgez  $15,3f
33642		 lhu   $24,0x00($23)    	 # Delay slot
33643		 j     MainExit
33644	3:
33645		 sll   $7,$24,2         	 # Delay slot
33646		 addu  $7,$7,$30
33647		 lw    $7,0x00($7)
33648		 jr    $7
33649		 nop                    	 # Delay slot
33650
33651OP0_59d0:				#:
33652		 addiu $23,$23,2
33653
33654		 andi  $24,$24,0x07
33655		 sll   $24,$24,2
33656		 addu  $24,$24,$21
33657		 lw    $14,0x20($24)
33658		 or    $2,$0,$17        	 # Check Overflow
33659		 subu  $2,$0,$2
33660		 lw    $25,0x88($21)
33661		 sw    $15,m68k_ICount
33662		 or    $5,$0,$2
33663		 or    $4,$0,$14
33664		 jalr  $25
33665		 sw    $23,0x4C($21)    	 # Delay slot
33666		 lw    $15,m68k_ICount
33667		 addiu $15,$15,-12
33668		 bgez  $15,3f
33669		 lhu   $24,0x00($23)    	 # Delay slot
33670		 j     MainExit
33671	3:
33672		 sll   $7,$24,2         	 # Delay slot
33673		 addu  $7,$7,$30
33674		 lw    $7,0x00($7)
33675		 jr    $7
33676		 nop                    	 # Delay slot
33677
33678OP0_59d8:				#:
33679		 addiu $23,$23,2
33680
33681		 andi  $24,$24,0x07
33682		 sll   $24,$24,2
33683		 addu  $24,$24,$21
33684		 lw    $14,0x20($24)
33685		 addiu $25,$14,1
33686		 sw    $25,0x20($24)
33687		 or    $2,$0,$17        	 # Check Overflow
33688		 subu  $2,$0,$2
33689		 lw    $25,0x88($21)
33690		 sw    $15,m68k_ICount
33691		 or    $5,$0,$2
33692		 or    $4,$0,$14
33693		 jalr  $25
33694		 sw    $23,0x4C($21)    	 # Delay slot
33695		 lw    $15,m68k_ICount
33696		 addiu $15,$15,-12
33697		 bgez  $15,3f
33698		 lhu   $24,0x00($23)    	 # Delay slot
33699		 j     MainExit
33700	3:
33701		 sll   $7,$24,2         	 # Delay slot
33702		 addu  $7,$7,$30
33703		 lw    $7,0x00($7)
33704		 jr    $7
33705		 nop                    	 # Delay slot
33706
33707OP0_59df:				#:
33708		 addiu $23,$23,2
33709
33710		 lw    $14,0x3C($21)    	 # Get A7
33711		 addiu $25,$14,2
33712		 sw    $25,0x3C($21)
33713		 or    $2,$0,$17        	 # Check Overflow
33714		 subu  $2,$0,$2
33715		 lw    $25,0x88($21)
33716		 sw    $15,m68k_ICount
33717		 or    $5,$0,$2
33718		 or    $4,$0,$14
33719		 jalr  $25
33720		 sw    $23,0x4C($21)    	 # Delay slot
33721		 lw    $15,m68k_ICount
33722		 addiu $15,$15,-12
33723		 bgez  $15,3f
33724		 lhu   $24,0x00($23)    	 # Delay slot
33725		 j     MainExit
33726	3:
33727		 sll   $7,$24,2         	 # Delay slot
33728		 addu  $7,$7,$30
33729		 lw    $7,0x00($7)
33730		 jr    $7
33731		 nop                    	 # Delay slot
33732
33733OP0_59e0:				#:
33734		 addiu $23,$23,2
33735
33736		 andi  $24,$24,0x07
33737		 sll   $24,$24,2
33738		 addu  $24,$24,$21
33739		 lw    $14,0x20($24)
33740		 addiu $14,$14,-1
33741		 sw    $14,0x20($24)
33742		 or    $2,$0,$17        	 # Check Overflow
33743		 subu  $2,$0,$2
33744		 lw    $25,0x88($21)
33745		 sw    $15,m68k_ICount
33746		 or    $5,$0,$2
33747		 or    $4,$0,$14
33748		 jalr  $25
33749		 sw    $23,0x4C($21)    	 # Delay slot
33750		 lw    $15,m68k_ICount
33751		 addiu $15,$15,-14
33752		 bgez  $15,3f
33753		 lhu   $24,0x00($23)    	 # Delay slot
33754		 j     MainExit
33755	3:
33756		 sll   $7,$24,2         	 # Delay slot
33757		 addu  $7,$7,$30
33758		 lw    $7,0x00($7)
33759		 jr    $7
33760		 nop                    	 # Delay slot
33761
33762OP0_59e7:				#:
33763		 addiu $23,$23,2
33764
33765		 lw    $14,0x3C($21)    	 # Get A7
33766		 addiu $14,$14,-2
33767		 sw    $14,0x3C($21)
33768		 or    $2,$0,$17        	 # Check Overflow
33769		 subu  $2,$0,$2
33770		 lw    $25,0x88($21)
33771		 sw    $15,m68k_ICount
33772		 or    $5,$0,$2
33773		 or    $4,$0,$14
33774		 jalr  $25
33775		 sw    $23,0x4C($21)    	 # Delay slot
33776		 lw    $15,m68k_ICount
33777		 addiu $15,$15,-14
33778		 bgez  $15,3f
33779		 lhu   $24,0x00($23)    	 # Delay slot
33780		 j     MainExit
33781	3:
33782		 sll   $7,$24,2         	 # Delay slot
33783		 addu  $7,$7,$30
33784		 lw    $7,0x00($7)
33785		 jr    $7
33786		 nop                    	 # Delay slot
33787
33788OP0_59e8:				#:
33789		 addiu $23,$23,2
33790
33791		 andi  $24,$24,0x07
33792		 lh    $7,0x00($23)
33793		 sll   $24,$24,2
33794		 addu  $24,$24,$21
33795		 lw    $14,0x20($24)
33796		 addiu $23,$23,2
33797		 addu  $14,$14,$7
33798		 or    $2,$0,$17        	 # Check Overflow
33799		 subu  $2,$0,$2
33800		 lw    $25,0x88($21)
33801		 sw    $15,m68k_ICount
33802		 or    $5,$0,$2
33803		 or    $4,$0,$14
33804		 jalr  $25
33805		 sw    $23,0x4C($21)    	 # Delay slot
33806		 lw    $15,m68k_ICount
33807		 addiu $15,$15,-16
33808		 bgez  $15,3f
33809		 lhu   $24,0x00($23)    	 # Delay slot
33810		 j     MainExit
33811	3:
33812		 sll   $7,$24,2         	 # Delay slot
33813		 addu  $7,$7,$30
33814		 lw    $7,0x00($7)
33815		 jr    $7
33816		 nop                    	 # Delay slot
33817
33818OP0_59f0:				#:
33819		 addiu $23,$23,2
33820
33821		 andi  $24,$24,0x07
33822		 sll   $24,$24,2
33823		 addu  $24,$24,$21
33824		 lw    $14,0x20($24)
33825		 lhu   $7,0x00($23)
33826		 addiu $23,$23,2
33827		 seb   $6,$7
33828		 or    $25,$0,$7
33829		 srl   $7,$7,12
33830		 andi  $25,$25,0x0800
33831		 sll   $7,$7,2
33832		 addu  $7,$7,$21
33833		 bne   $25,$0,0f
33834		 lw    $25,0x00($7)      	 # Delay slot
33835		 seh   $25,$25
33836	0:
33837		 addu  $25,$14,$25
33838		 addu  $14,$25,$6
33839		 or    $2,$0,$17        	 # Check Overflow
33840		 subu  $2,$0,$2
33841		 lw    $25,0x88($21)
33842		 sw    $15,m68k_ICount
33843		 or    $5,$0,$2
33844		 or    $4,$0,$14
33845		 jalr  $25
33846		 sw    $23,0x4C($21)    	 # Delay slot
33847		 lw    $15,m68k_ICount
33848		 addiu $15,$15,-18
33849		 bgez  $15,3f
33850		 lhu   $24,0x00($23)    	 # Delay slot
33851		 j     MainExit
33852	3:
33853		 sll   $7,$24,2         	 # Delay slot
33854		 addu  $7,$7,$30
33855		 lw    $7,0x00($7)
33856		 jr    $7
33857		 nop                    	 # Delay slot
33858
33859OP0_59f8:				#:
33860		 addiu $23,$23,2
33861
33862		 lh    $14,0x00($23)
33863		 addiu $23,$23,2
33864		 or    $2,$0,$17        	 # Check Overflow
33865		 subu  $2,$0,$2
33866		 lw    $25,0x88($21)
33867		 sw    $15,m68k_ICount
33868		 or    $5,$0,$2
33869		 or    $4,$0,$14
33870		 jalr  $25
33871		 sw    $23,0x4C($21)    	 # Delay slot
33872		 lw    $15,m68k_ICount
33873		 addiu $15,$15,-16
33874		 bgez  $15,3f
33875		 lhu   $24,0x00($23)    	 # Delay slot
33876		 j     MainExit
33877	3:
33878		 sll   $7,$24,2         	 # Delay slot
33879		 addu  $7,$7,$30
33880		 lw    $7,0x00($7)
33881		 jr    $7
33882		 nop                    	 # Delay slot
33883
33884OP0_59f9:				#:
33885		 addiu $23,$23,2
33886
33887		 lhu   $14,0x00($23)
33888		 lhu   $25,0x02($23)
33889		 sll   $14,$14,16
33890		 or    $14,$14,$25
33891		 addiu $23,$23,4
33892		 or    $2,$0,$17        	 # Check Overflow
33893		 subu  $2,$0,$2
33894		 lw    $25,0x88($21)
33895		 sw    $15,m68k_ICount
33896		 or    $5,$0,$2
33897		 or    $4,$0,$14
33898		 jalr  $25
33899		 sw    $23,0x4C($21)    	 # Delay slot
33900		 lw    $15,m68k_ICount
33901		 addiu $15,$15,-20
33902		 bgez  $15,3f
33903		 lhu   $24,0x00($23)    	 # Delay slot
33904		 j     MainExit
33905	3:
33906		 sll   $7,$24,2         	 # Delay slot
33907		 addu  $7,$7,$30
33908		 lw    $7,0x00($7)
33909		 jr    $7
33910		 nop                    	 # Delay slot
33911
33912OP0_5ac0:				#:
33913		 addiu $23,$23,2
33914
33915		 andi  $24,$24,0x07
33916		 xori  $2,$19,1         	 # Check Sign
33917		 subu  $2,$0,$2
33918		 sll   $24,$24,2
33919		 addu  $24,$24,$21
33920		 sb    $2,0x00($24)
33921		 andi  $2,$2,0x02
33922		 addiu $15,$15,-4
33923		 subu  $15,$15,$2
33924		 bgez  $15,3f
33925		 lhu   $24,0x00($23)    	 # Delay slot
33926		 j     MainExit
33927	3:
33928		 sll   $7,$24,2         	 # Delay slot
33929		 addu  $7,$7,$30
33930		 lw    $7,0x00($7)
33931		 jr    $7
33932		 nop                    	 # Delay slot
33933
33934OP0_5ac8:				#:
33935		 beq   $19,$0,1f        	 # Check Sign
33936		 andi  $24,$24,0x07     	 # Delay slot
33937		 sll   $24,$24,2
33938		 addu  $24,$24,$21
33939		 lhu   $8,0x00($24)
33940		 addiu $9,$8,-1
33941		 beq   $8,$0,9f         	 # Is it -1
33942		 sh    $9,0x00($24)     	 # Delay slot
33943
33944		 addiu $23,$23,2
33945
33946		 lh    $2,0x00($23)
33947		 addu  $23,$23,$2
33948		 addiu $15,$15,-10
33949		 bgez  $15,3f
33950		 lhu   $24,0x00($23)    	 # Delay slot
33951		 j     MainExit
33952	3:
33953		 sll   $7,$24,2         	 # Delay slot
33954		 addu  $7,$7,$30
33955		 lw    $7,0x00($7)
33956		 jr    $7
33957		 nop                    	 # Delay slot
33958
33959	9:
33960	1:
33961		 addiu $23,$23,4
33962
33963		 addiu $15,$15,-12
33964		 bgez  $15,3f
33965		 lhu   $24,0x00($23)    	 # Delay slot
33966		 j     MainExit
33967	3:
33968		 sll   $7,$24,2         	 # Delay slot
33969		 addu  $7,$7,$30
33970		 lw    $7,0x00($7)
33971		 jr    $7
33972		 nop                    	 # Delay slot
33973
33974OP0_5ad0:				#:
33975		 addiu $23,$23,2
33976
33977		 andi  $24,$24,0x07
33978		 sll   $24,$24,2
33979		 addu  $24,$24,$21
33980		 lw    $14,0x20($24)
33981		 xori  $2,$19,1         	 # Check Sign
33982		 subu  $2,$0,$2
33983		 lw    $25,0x88($21)
33984		 sw    $15,m68k_ICount
33985		 or    $5,$0,$2
33986		 or    $4,$0,$14
33987		 jalr  $25
33988		 sw    $23,0x4C($21)    	 # Delay slot
33989		 lw    $15,m68k_ICount
33990		 addiu $15,$15,-12
33991		 bgez  $15,3f
33992		 lhu   $24,0x00($23)    	 # Delay slot
33993		 j     MainExit
33994	3:
33995		 sll   $7,$24,2         	 # Delay slot
33996		 addu  $7,$7,$30
33997		 lw    $7,0x00($7)
33998		 jr    $7
33999		 nop                    	 # Delay slot
34000
34001OP0_5ad8:				#:
34002		 addiu $23,$23,2
34003
34004		 andi  $24,$24,0x07
34005		 sll   $24,$24,2
34006		 addu  $24,$24,$21
34007		 lw    $14,0x20($24)
34008		 addiu $25,$14,1
34009		 sw    $25,0x20($24)
34010		 xori  $2,$19,1         	 # Check Sign
34011		 subu  $2,$0,$2
34012		 lw    $25,0x88($21)
34013		 sw    $15,m68k_ICount
34014		 or    $5,$0,$2
34015		 or    $4,$0,$14
34016		 jalr  $25
34017		 sw    $23,0x4C($21)    	 # Delay slot
34018		 lw    $15,m68k_ICount
34019		 addiu $15,$15,-12
34020		 bgez  $15,3f
34021		 lhu   $24,0x00($23)    	 # Delay slot
34022		 j     MainExit
34023	3:
34024		 sll   $7,$24,2         	 # Delay slot
34025		 addu  $7,$7,$30
34026		 lw    $7,0x00($7)
34027		 jr    $7
34028		 nop                    	 # Delay slot
34029
34030OP0_5adf:				#:
34031		 addiu $23,$23,2
34032
34033		 lw    $14,0x3C($21)    	 # Get A7
34034		 addiu $25,$14,2
34035		 sw    $25,0x3C($21)
34036		 xori  $2,$19,1         	 # Check Sign
34037		 subu  $2,$0,$2
34038		 lw    $25,0x88($21)
34039		 sw    $15,m68k_ICount
34040		 or    $5,$0,$2
34041		 or    $4,$0,$14
34042		 jalr  $25
34043		 sw    $23,0x4C($21)    	 # Delay slot
34044		 lw    $15,m68k_ICount
34045		 addiu $15,$15,-12
34046		 bgez  $15,3f
34047		 lhu   $24,0x00($23)    	 # Delay slot
34048		 j     MainExit
34049	3:
34050		 sll   $7,$24,2         	 # Delay slot
34051		 addu  $7,$7,$30
34052		 lw    $7,0x00($7)
34053		 jr    $7
34054		 nop                    	 # Delay slot
34055
34056OP0_5ae0:				#:
34057		 addiu $23,$23,2
34058
34059		 andi  $24,$24,0x07
34060		 sll   $24,$24,2
34061		 addu  $24,$24,$21
34062		 lw    $14,0x20($24)
34063		 addiu $14,$14,-1
34064		 sw    $14,0x20($24)
34065		 xori  $2,$19,1         	 # Check Sign
34066		 subu  $2,$0,$2
34067		 lw    $25,0x88($21)
34068		 sw    $15,m68k_ICount
34069		 or    $5,$0,$2
34070		 or    $4,$0,$14
34071		 jalr  $25
34072		 sw    $23,0x4C($21)    	 # Delay slot
34073		 lw    $15,m68k_ICount
34074		 addiu $15,$15,-14
34075		 bgez  $15,3f
34076		 lhu   $24,0x00($23)    	 # Delay slot
34077		 j     MainExit
34078	3:
34079		 sll   $7,$24,2         	 # Delay slot
34080		 addu  $7,$7,$30
34081		 lw    $7,0x00($7)
34082		 jr    $7
34083		 nop                    	 # Delay slot
34084
34085OP0_5ae7:				#:
34086		 addiu $23,$23,2
34087
34088		 lw    $14,0x3C($21)    	 # Get A7
34089		 addiu $14,$14,-2
34090		 sw    $14,0x3C($21)
34091		 xori  $2,$19,1         	 # Check Sign
34092		 subu  $2,$0,$2
34093		 lw    $25,0x88($21)
34094		 sw    $15,m68k_ICount
34095		 or    $5,$0,$2
34096		 or    $4,$0,$14
34097		 jalr  $25
34098		 sw    $23,0x4C($21)    	 # Delay slot
34099		 lw    $15,m68k_ICount
34100		 addiu $15,$15,-14
34101		 bgez  $15,3f
34102		 lhu   $24,0x00($23)    	 # Delay slot
34103		 j     MainExit
34104	3:
34105		 sll   $7,$24,2         	 # Delay slot
34106		 addu  $7,$7,$30
34107		 lw    $7,0x00($7)
34108		 jr    $7
34109		 nop                    	 # Delay slot
34110
34111OP0_5ae8:				#:
34112		 addiu $23,$23,2
34113
34114		 andi  $24,$24,0x07
34115		 lh    $7,0x00($23)
34116		 sll   $24,$24,2
34117		 addu  $24,$24,$21
34118		 lw    $14,0x20($24)
34119		 addiu $23,$23,2
34120		 addu  $14,$14,$7
34121		 xori  $2,$19,1         	 # Check Sign
34122		 subu  $2,$0,$2
34123		 lw    $25,0x88($21)
34124		 sw    $15,m68k_ICount
34125		 or    $5,$0,$2
34126		 or    $4,$0,$14
34127		 jalr  $25
34128		 sw    $23,0x4C($21)    	 # Delay slot
34129		 lw    $15,m68k_ICount
34130		 addiu $15,$15,-16
34131		 bgez  $15,3f
34132		 lhu   $24,0x00($23)    	 # Delay slot
34133		 j     MainExit
34134	3:
34135		 sll   $7,$24,2         	 # Delay slot
34136		 addu  $7,$7,$30
34137		 lw    $7,0x00($7)
34138		 jr    $7
34139		 nop                    	 # Delay slot
34140
34141OP0_5af0:				#:
34142		 addiu $23,$23,2
34143
34144		 andi  $24,$24,0x07
34145		 sll   $24,$24,2
34146		 addu  $24,$24,$21
34147		 lw    $14,0x20($24)
34148		 lhu   $7,0x00($23)
34149		 addiu $23,$23,2
34150		 seb   $6,$7
34151		 or    $25,$0,$7
34152		 srl   $7,$7,12
34153		 andi  $25,$25,0x0800
34154		 sll   $7,$7,2
34155		 addu  $7,$7,$21
34156		 bne   $25,$0,0f
34157		 lw    $25,0x00($7)      	 # Delay slot
34158		 seh   $25,$25
34159	0:
34160		 addu  $25,$14,$25
34161		 addu  $14,$25,$6
34162		 xori  $2,$19,1         	 # Check Sign
34163		 subu  $2,$0,$2
34164		 lw    $25,0x88($21)
34165		 sw    $15,m68k_ICount
34166		 or    $5,$0,$2
34167		 or    $4,$0,$14
34168		 jalr  $25
34169		 sw    $23,0x4C($21)    	 # Delay slot
34170		 lw    $15,m68k_ICount
34171		 addiu $15,$15,-18
34172		 bgez  $15,3f
34173		 lhu   $24,0x00($23)    	 # Delay slot
34174		 j     MainExit
34175	3:
34176		 sll   $7,$24,2         	 # Delay slot
34177		 addu  $7,$7,$30
34178		 lw    $7,0x00($7)
34179		 jr    $7
34180		 nop                    	 # Delay slot
34181
34182OP0_5af8:				#:
34183		 addiu $23,$23,2
34184
34185		 lh    $14,0x00($23)
34186		 addiu $23,$23,2
34187		 xori  $2,$19,1         	 # Check Sign
34188		 subu  $2,$0,$2
34189		 lw    $25,0x88($21)
34190		 sw    $15,m68k_ICount
34191		 or    $5,$0,$2
34192		 or    $4,$0,$14
34193		 jalr  $25
34194		 sw    $23,0x4C($21)    	 # Delay slot
34195		 lw    $15,m68k_ICount
34196		 addiu $15,$15,-16
34197		 bgez  $15,3f
34198		 lhu   $24,0x00($23)    	 # Delay slot
34199		 j     MainExit
34200	3:
34201		 sll   $7,$24,2         	 # Delay slot
34202		 addu  $7,$7,$30
34203		 lw    $7,0x00($7)
34204		 jr    $7
34205		 nop                    	 # Delay slot
34206
34207OP0_5af9:				#:
34208		 addiu $23,$23,2
34209
34210		 lhu   $14,0x00($23)
34211		 lhu   $25,0x02($23)
34212		 sll   $14,$14,16
34213		 or    $14,$14,$25
34214		 addiu $23,$23,4
34215		 xori  $2,$19,1         	 # Check Sign
34216		 subu  $2,$0,$2
34217		 lw    $25,0x88($21)
34218		 sw    $15,m68k_ICount
34219		 or    $5,$0,$2
34220		 or    $4,$0,$14
34221		 jalr  $25
34222		 sw    $23,0x4C($21)    	 # Delay slot
34223		 lw    $15,m68k_ICount
34224		 addiu $15,$15,-20
34225		 bgez  $15,3f
34226		 lhu   $24,0x00($23)    	 # Delay slot
34227		 j     MainExit
34228	3:
34229		 sll   $7,$24,2         	 # Delay slot
34230		 addu  $7,$7,$30
34231		 lw    $7,0x00($7)
34232		 jr    $7
34233		 nop                    	 # Delay slot
34234
34235OP0_5bc0:				#:
34236		 addiu $23,$23,2
34237
34238		 andi  $24,$24,0x07
34239		 or    $2,$0,$19        	 # Check Sign
34240		 subu  $2,$0,$2
34241		 sll   $24,$24,2
34242		 addu  $24,$24,$21
34243		 sb    $2,0x00($24)
34244		 andi  $2,$2,0x02
34245		 addiu $15,$15,-4
34246		 subu  $15,$15,$2
34247		 bgez  $15,3f
34248		 lhu   $24,0x00($23)    	 # Delay slot
34249		 j     MainExit
34250	3:
34251		 sll   $7,$24,2         	 # Delay slot
34252		 addu  $7,$7,$30
34253		 lw    $7,0x00($7)
34254		 jr    $7
34255		 nop                    	 # Delay slot
34256
34257OP0_5bc8:				#:
34258		 bne   $19,$0,1f        	 # Check Sign
34259		 andi  $24,$24,0x07     	 # Delay slot
34260		 sll   $24,$24,2
34261		 addu  $24,$24,$21
34262		 lhu   $8,0x00($24)
34263		 addiu $9,$8,-1
34264		 beq   $8,$0,9f         	 # Is it -1
34265		 sh    $9,0x00($24)     	 # Delay slot
34266
34267		 addiu $23,$23,2
34268
34269		 lh    $2,0x00($23)
34270		 addu  $23,$23,$2
34271		 addiu $15,$15,-10
34272		 bgez  $15,3f
34273		 lhu   $24,0x00($23)    	 # Delay slot
34274		 j     MainExit
34275	3:
34276		 sll   $7,$24,2         	 # Delay slot
34277		 addu  $7,$7,$30
34278		 lw    $7,0x00($7)
34279		 jr    $7
34280		 nop                    	 # Delay slot
34281
34282	9:
34283	1:
34284		 addiu $23,$23,4
34285
34286		 addiu $15,$15,-12
34287		 bgez  $15,3f
34288		 lhu   $24,0x00($23)    	 # Delay slot
34289		 j     MainExit
34290	3:
34291		 sll   $7,$24,2         	 # Delay slot
34292		 addu  $7,$7,$30
34293		 lw    $7,0x00($7)
34294		 jr    $7
34295		 nop                    	 # Delay slot
34296
34297OP0_5bd0:				#:
34298		 addiu $23,$23,2
34299
34300		 andi  $24,$24,0x07
34301		 sll   $24,$24,2
34302		 addu  $24,$24,$21
34303		 lw    $14,0x20($24)
34304		 or    $2,$0,$19        	 # Check Sign
34305		 subu  $2,$0,$2
34306		 lw    $25,0x88($21)
34307		 sw    $15,m68k_ICount
34308		 or    $5,$0,$2
34309		 or    $4,$0,$14
34310		 jalr  $25
34311		 sw    $23,0x4C($21)    	 # Delay slot
34312		 lw    $15,m68k_ICount
34313		 addiu $15,$15,-12
34314		 bgez  $15,3f
34315		 lhu   $24,0x00($23)    	 # Delay slot
34316		 j     MainExit
34317	3:
34318		 sll   $7,$24,2         	 # Delay slot
34319		 addu  $7,$7,$30
34320		 lw    $7,0x00($7)
34321		 jr    $7
34322		 nop                    	 # Delay slot
34323
34324OP0_5bd8:				#:
34325		 addiu $23,$23,2
34326
34327		 andi  $24,$24,0x07
34328		 sll   $24,$24,2
34329		 addu  $24,$24,$21
34330		 lw    $14,0x20($24)
34331		 addiu $25,$14,1
34332		 sw    $25,0x20($24)
34333		 or    $2,$0,$19        	 # Check Sign
34334		 subu  $2,$0,$2
34335		 lw    $25,0x88($21)
34336		 sw    $15,m68k_ICount
34337		 or    $5,$0,$2
34338		 or    $4,$0,$14
34339		 jalr  $25
34340		 sw    $23,0x4C($21)    	 # Delay slot
34341		 lw    $15,m68k_ICount
34342		 addiu $15,$15,-12
34343		 bgez  $15,3f
34344		 lhu   $24,0x00($23)    	 # Delay slot
34345		 j     MainExit
34346	3:
34347		 sll   $7,$24,2         	 # Delay slot
34348		 addu  $7,$7,$30
34349		 lw    $7,0x00($7)
34350		 jr    $7
34351		 nop                    	 # Delay slot
34352
34353OP0_5bdf:				#:
34354		 addiu $23,$23,2
34355
34356		 lw    $14,0x3C($21)    	 # Get A7
34357		 addiu $25,$14,2
34358		 sw    $25,0x3C($21)
34359		 or    $2,$0,$19        	 # Check Sign
34360		 subu  $2,$0,$2
34361		 lw    $25,0x88($21)
34362		 sw    $15,m68k_ICount
34363		 or    $5,$0,$2
34364		 or    $4,$0,$14
34365		 jalr  $25
34366		 sw    $23,0x4C($21)    	 # Delay slot
34367		 lw    $15,m68k_ICount
34368		 addiu $15,$15,-12
34369		 bgez  $15,3f
34370		 lhu   $24,0x00($23)    	 # Delay slot
34371		 j     MainExit
34372	3:
34373		 sll   $7,$24,2         	 # Delay slot
34374		 addu  $7,$7,$30
34375		 lw    $7,0x00($7)
34376		 jr    $7
34377		 nop                    	 # Delay slot
34378
34379OP0_5be0:				#:
34380		 addiu $23,$23,2
34381
34382		 andi  $24,$24,0x07
34383		 sll   $24,$24,2
34384		 addu  $24,$24,$21
34385		 lw    $14,0x20($24)
34386		 addiu $14,$14,-1
34387		 sw    $14,0x20($24)
34388		 or    $2,$0,$19        	 # Check Sign
34389		 subu  $2,$0,$2
34390		 lw    $25,0x88($21)
34391		 sw    $15,m68k_ICount
34392		 or    $5,$0,$2
34393		 or    $4,$0,$14
34394		 jalr  $25
34395		 sw    $23,0x4C($21)    	 # Delay slot
34396		 lw    $15,m68k_ICount
34397		 addiu $15,$15,-14
34398		 bgez  $15,3f
34399		 lhu   $24,0x00($23)    	 # Delay slot
34400		 j     MainExit
34401	3:
34402		 sll   $7,$24,2         	 # Delay slot
34403		 addu  $7,$7,$30
34404		 lw    $7,0x00($7)
34405		 jr    $7
34406		 nop                    	 # Delay slot
34407
34408OP0_5be7:				#:
34409		 addiu $23,$23,2
34410
34411		 lw    $14,0x3C($21)    	 # Get A7
34412		 addiu $14,$14,-2
34413		 sw    $14,0x3C($21)
34414		 or    $2,$0,$19        	 # Check Sign
34415		 subu  $2,$0,$2
34416		 lw    $25,0x88($21)
34417		 sw    $15,m68k_ICount
34418		 or    $5,$0,$2
34419		 or    $4,$0,$14
34420		 jalr  $25
34421		 sw    $23,0x4C($21)    	 # Delay slot
34422		 lw    $15,m68k_ICount
34423		 addiu $15,$15,-14
34424		 bgez  $15,3f
34425		 lhu   $24,0x00($23)    	 # Delay slot
34426		 j     MainExit
34427	3:
34428		 sll   $7,$24,2         	 # Delay slot
34429		 addu  $7,$7,$30
34430		 lw    $7,0x00($7)
34431		 jr    $7
34432		 nop                    	 # Delay slot
34433
34434OP0_5be8:				#:
34435		 addiu $23,$23,2
34436
34437		 andi  $24,$24,0x07
34438		 lh    $7,0x00($23)
34439		 sll   $24,$24,2
34440		 addu  $24,$24,$21
34441		 lw    $14,0x20($24)
34442		 addiu $23,$23,2
34443		 addu  $14,$14,$7
34444		 or    $2,$0,$19        	 # Check Sign
34445		 subu  $2,$0,$2
34446		 lw    $25,0x88($21)
34447		 sw    $15,m68k_ICount
34448		 or    $5,$0,$2
34449		 or    $4,$0,$14
34450		 jalr  $25
34451		 sw    $23,0x4C($21)    	 # Delay slot
34452		 lw    $15,m68k_ICount
34453		 addiu $15,$15,-16
34454		 bgez  $15,3f
34455		 lhu   $24,0x00($23)    	 # Delay slot
34456		 j     MainExit
34457	3:
34458		 sll   $7,$24,2         	 # Delay slot
34459		 addu  $7,$7,$30
34460		 lw    $7,0x00($7)
34461		 jr    $7
34462		 nop                    	 # Delay slot
34463
34464OP0_5bf0:				#:
34465		 addiu $23,$23,2
34466
34467		 andi  $24,$24,0x07
34468		 sll   $24,$24,2
34469		 addu  $24,$24,$21
34470		 lw    $14,0x20($24)
34471		 lhu   $7,0x00($23)
34472		 addiu $23,$23,2
34473		 seb   $6,$7
34474		 or    $25,$0,$7
34475		 srl   $7,$7,12
34476		 andi  $25,$25,0x0800
34477		 sll   $7,$7,2
34478		 addu  $7,$7,$21
34479		 bne   $25,$0,0f
34480		 lw    $25,0x00($7)      	 # Delay slot
34481		 seh   $25,$25
34482	0:
34483		 addu  $25,$14,$25
34484		 addu  $14,$25,$6
34485		 or    $2,$0,$19        	 # Check Sign
34486		 subu  $2,$0,$2
34487		 lw    $25,0x88($21)
34488		 sw    $15,m68k_ICount
34489		 or    $5,$0,$2
34490		 or    $4,$0,$14
34491		 jalr  $25
34492		 sw    $23,0x4C($21)    	 # Delay slot
34493		 lw    $15,m68k_ICount
34494		 addiu $15,$15,-18
34495		 bgez  $15,3f
34496		 lhu   $24,0x00($23)    	 # Delay slot
34497		 j     MainExit
34498	3:
34499		 sll   $7,$24,2         	 # Delay slot
34500		 addu  $7,$7,$30
34501		 lw    $7,0x00($7)
34502		 jr    $7
34503		 nop                    	 # Delay slot
34504
34505OP0_5bf8:				#:
34506		 addiu $23,$23,2
34507
34508		 lh    $14,0x00($23)
34509		 addiu $23,$23,2
34510		 or    $2,$0,$19        	 # Check Sign
34511		 subu  $2,$0,$2
34512		 lw    $25,0x88($21)
34513		 sw    $15,m68k_ICount
34514		 or    $5,$0,$2
34515		 or    $4,$0,$14
34516		 jalr  $25
34517		 sw    $23,0x4C($21)    	 # Delay slot
34518		 lw    $15,m68k_ICount
34519		 addiu $15,$15,-16
34520		 bgez  $15,3f
34521		 lhu   $24,0x00($23)    	 # Delay slot
34522		 j     MainExit
34523	3:
34524		 sll   $7,$24,2         	 # Delay slot
34525		 addu  $7,$7,$30
34526		 lw    $7,0x00($7)
34527		 jr    $7
34528		 nop                    	 # Delay slot
34529
34530OP0_5bf9:				#:
34531		 addiu $23,$23,2
34532
34533		 lhu   $14,0x00($23)
34534		 lhu   $25,0x02($23)
34535		 sll   $14,$14,16
34536		 or    $14,$14,$25
34537		 addiu $23,$23,4
34538		 or    $2,$0,$19        	 # Check Sign
34539		 subu  $2,$0,$2
34540		 lw    $25,0x88($21)
34541		 sw    $15,m68k_ICount
34542		 or    $5,$0,$2
34543		 or    $4,$0,$14
34544		 jalr  $25
34545		 sw    $23,0x4C($21)    	 # Delay slot
34546		 lw    $15,m68k_ICount
34547		 addiu $15,$15,-20
34548		 bgez  $15,3f
34549		 lhu   $24,0x00($23)    	 # Delay slot
34550		 j     MainExit
34551	3:
34552		 sll   $7,$24,2         	 # Delay slot
34553		 addu  $7,$7,$30
34554		 lw    $7,0x00($7)
34555		 jr    $7
34556		 nop                    	 # Delay slot
34557
34558OP0_5cc0:				#:
34559		 addiu $23,$23,2
34560
34561		 andi  $24,$24,0x07
34562		 xor   $2,$19,$17
34563		 addiu $2,$2,-1
34564		 sll   $24,$24,2
34565		 addu  $24,$24,$21
34566		 sb    $2,0x00($24)
34567		 andi  $2,$2,0x02
34568		 addiu $15,$15,-4
34569		 subu  $15,$15,$2
34570		 bgez  $15,3f
34571		 lhu   $24,0x00($23)    	 # Delay slot
34572		 j     MainExit
34573	3:
34574		 sll   $7,$24,2         	 # Delay slot
34575		 addu  $7,$7,$30
34576		 lw    $7,0x00($7)
34577		 jr    $7
34578		 nop                    	 # Delay slot
34579
34580OP0_5cc8:				#:
34581		 beq   $19,$17,1f
34582		 andi  $24,$24,0x07     	 # Delay slot
34583		 sll   $24,$24,2
34584		 addu  $24,$24,$21
34585		 lhu   $8,0x00($24)
34586		 addiu $9,$8,-1
34587		 beq   $8,$0,9f         	 # Is it -1
34588		 sh    $9,0x00($24)     	 # Delay slot
34589
34590		 addiu $23,$23,2
34591
34592		 lh    $2,0x00($23)
34593		 addu  $23,$23,$2
34594		 addiu $15,$15,-10
34595		 bgez  $15,3f
34596		 lhu   $24,0x00($23)    	 # Delay slot
34597		 j     MainExit
34598	3:
34599		 sll   $7,$24,2         	 # Delay slot
34600		 addu  $7,$7,$30
34601		 lw    $7,0x00($7)
34602		 jr    $7
34603		 nop                    	 # Delay slot
34604
34605	9:
34606	1:
34607		 addiu $23,$23,4
34608
34609		 addiu $15,$15,-12
34610		 bgez  $15,3f
34611		 lhu   $24,0x00($23)    	 # Delay slot
34612		 j     MainExit
34613	3:
34614		 sll   $7,$24,2         	 # Delay slot
34615		 addu  $7,$7,$30
34616		 lw    $7,0x00($7)
34617		 jr    $7
34618		 nop                    	 # Delay slot
34619
34620OP0_5cd0:				#:
34621		 addiu $23,$23,2
34622
34623		 andi  $24,$24,0x07
34624		 sll   $24,$24,2
34625		 addu  $24,$24,$21
34626		 lw    $14,0x20($24)
34627		 xor   $2,$19,$17
34628		 addiu $2,$2,-1
34629		 lw    $25,0x88($21)
34630		 sw    $15,m68k_ICount
34631		 or    $5,$0,$2
34632		 or    $4,$0,$14
34633		 jalr  $25
34634		 sw    $23,0x4C($21)    	 # Delay slot
34635		 lw    $15,m68k_ICount
34636		 addiu $15,$15,-12
34637		 bgez  $15,3f
34638		 lhu   $24,0x00($23)    	 # Delay slot
34639		 j     MainExit
34640	3:
34641		 sll   $7,$24,2         	 # Delay slot
34642		 addu  $7,$7,$30
34643		 lw    $7,0x00($7)
34644		 jr    $7
34645		 nop                    	 # Delay slot
34646
34647OP0_5cd8:				#:
34648		 addiu $23,$23,2
34649
34650		 andi  $24,$24,0x07
34651		 sll   $24,$24,2
34652		 addu  $24,$24,$21
34653		 lw    $14,0x20($24)
34654		 addiu $25,$14,1
34655		 sw    $25,0x20($24)
34656		 xor   $2,$19,$17
34657		 addiu $2,$2,-1
34658		 lw    $25,0x88($21)
34659		 sw    $15,m68k_ICount
34660		 or    $5,$0,$2
34661		 or    $4,$0,$14
34662		 jalr  $25
34663		 sw    $23,0x4C($21)    	 # Delay slot
34664		 lw    $15,m68k_ICount
34665		 addiu $15,$15,-12
34666		 bgez  $15,3f
34667		 lhu   $24,0x00($23)    	 # Delay slot
34668		 j     MainExit
34669	3:
34670		 sll   $7,$24,2         	 # Delay slot
34671		 addu  $7,$7,$30
34672		 lw    $7,0x00($7)
34673		 jr    $7
34674		 nop                    	 # Delay slot
34675
34676OP0_5cdf:				#:
34677		 addiu $23,$23,2
34678
34679		 lw    $14,0x3C($21)    	 # Get A7
34680		 addiu $25,$14,2
34681		 sw    $25,0x3C($21)
34682		 xor   $2,$19,$17
34683		 addiu $2,$2,-1
34684		 lw    $25,0x88($21)
34685		 sw    $15,m68k_ICount
34686		 or    $5,$0,$2
34687		 or    $4,$0,$14
34688		 jalr  $25
34689		 sw    $23,0x4C($21)    	 # Delay slot
34690		 lw    $15,m68k_ICount
34691		 addiu $15,$15,-12
34692		 bgez  $15,3f
34693		 lhu   $24,0x00($23)    	 # Delay slot
34694		 j     MainExit
34695	3:
34696		 sll   $7,$24,2         	 # Delay slot
34697		 addu  $7,$7,$30
34698		 lw    $7,0x00($7)
34699		 jr    $7
34700		 nop                    	 # Delay slot
34701
34702OP0_5ce0:				#:
34703		 addiu $23,$23,2
34704
34705		 andi  $24,$24,0x07
34706		 sll   $24,$24,2
34707		 addu  $24,$24,$21
34708		 lw    $14,0x20($24)
34709		 addiu $14,$14,-1
34710		 sw    $14,0x20($24)
34711		 xor   $2,$19,$17
34712		 addiu $2,$2,-1
34713		 lw    $25,0x88($21)
34714		 sw    $15,m68k_ICount
34715		 or    $5,$0,$2
34716		 or    $4,$0,$14
34717		 jalr  $25
34718		 sw    $23,0x4C($21)    	 # Delay slot
34719		 lw    $15,m68k_ICount
34720		 addiu $15,$15,-14
34721		 bgez  $15,3f
34722		 lhu   $24,0x00($23)    	 # Delay slot
34723		 j     MainExit
34724	3:
34725		 sll   $7,$24,2         	 # Delay slot
34726		 addu  $7,$7,$30
34727		 lw    $7,0x00($7)
34728		 jr    $7
34729		 nop                    	 # Delay slot
34730
34731OP0_5ce7:				#:
34732		 addiu $23,$23,2
34733
34734		 lw    $14,0x3C($21)    	 # Get A7
34735		 addiu $14,$14,-2
34736		 sw    $14,0x3C($21)
34737		 xor   $2,$19,$17
34738		 addiu $2,$2,-1
34739		 lw    $25,0x88($21)
34740		 sw    $15,m68k_ICount
34741		 or    $5,$0,$2
34742		 or    $4,$0,$14
34743		 jalr  $25
34744		 sw    $23,0x4C($21)    	 # Delay slot
34745		 lw    $15,m68k_ICount
34746		 addiu $15,$15,-14
34747		 bgez  $15,3f
34748		 lhu   $24,0x00($23)    	 # Delay slot
34749		 j     MainExit
34750	3:
34751		 sll   $7,$24,2         	 # Delay slot
34752		 addu  $7,$7,$30
34753		 lw    $7,0x00($7)
34754		 jr    $7
34755		 nop                    	 # Delay slot
34756
34757OP0_5ce8:				#:
34758		 addiu $23,$23,2
34759
34760		 andi  $24,$24,0x07
34761		 lh    $7,0x00($23)
34762		 sll   $24,$24,2
34763		 addu  $24,$24,$21
34764		 lw    $14,0x20($24)
34765		 addiu $23,$23,2
34766		 addu  $14,$14,$7
34767		 xor   $2,$19,$17
34768		 addiu $2,$2,-1
34769		 lw    $25,0x88($21)
34770		 sw    $15,m68k_ICount
34771		 or    $5,$0,$2
34772		 or    $4,$0,$14
34773		 jalr  $25
34774		 sw    $23,0x4C($21)    	 # Delay slot
34775		 lw    $15,m68k_ICount
34776		 addiu $15,$15,-16
34777		 bgez  $15,3f
34778		 lhu   $24,0x00($23)    	 # Delay slot
34779		 j     MainExit
34780	3:
34781		 sll   $7,$24,2         	 # Delay slot
34782		 addu  $7,$7,$30
34783		 lw    $7,0x00($7)
34784		 jr    $7
34785		 nop                    	 # Delay slot
34786
34787OP0_5cf0:				#:
34788		 addiu $23,$23,2
34789
34790		 andi  $24,$24,0x07
34791		 sll   $24,$24,2
34792		 addu  $24,$24,$21
34793		 lw    $14,0x20($24)
34794		 lhu   $7,0x00($23)
34795		 addiu $23,$23,2
34796		 seb   $6,$7
34797		 or    $25,$0,$7
34798		 srl   $7,$7,12
34799		 andi  $25,$25,0x0800
34800		 sll   $7,$7,2
34801		 addu  $7,$7,$21
34802		 bne   $25,$0,0f
34803		 lw    $25,0x00($7)      	 # Delay slot
34804		 seh   $25,$25
34805	0:
34806		 addu  $25,$14,$25
34807		 addu  $14,$25,$6
34808		 xor   $2,$19,$17
34809		 addiu $2,$2,-1
34810		 lw    $25,0x88($21)
34811		 sw    $15,m68k_ICount
34812		 or    $5,$0,$2
34813		 or    $4,$0,$14
34814		 jalr  $25
34815		 sw    $23,0x4C($21)    	 # Delay slot
34816		 lw    $15,m68k_ICount
34817		 addiu $15,$15,-18
34818		 bgez  $15,3f
34819		 lhu   $24,0x00($23)    	 # Delay slot
34820		 j     MainExit
34821	3:
34822		 sll   $7,$24,2         	 # Delay slot
34823		 addu  $7,$7,$30
34824		 lw    $7,0x00($7)
34825		 jr    $7
34826		 nop                    	 # Delay slot
34827
34828OP0_5cf8:				#:
34829		 addiu $23,$23,2
34830
34831		 lh    $14,0x00($23)
34832		 addiu $23,$23,2
34833		 xor   $2,$19,$17
34834		 addiu $2,$2,-1
34835		 lw    $25,0x88($21)
34836		 sw    $15,m68k_ICount
34837		 or    $5,$0,$2
34838		 or    $4,$0,$14
34839		 jalr  $25
34840		 sw    $23,0x4C($21)    	 # Delay slot
34841		 lw    $15,m68k_ICount
34842		 addiu $15,$15,-16
34843		 bgez  $15,3f
34844		 lhu   $24,0x00($23)    	 # Delay slot
34845		 j     MainExit
34846	3:
34847		 sll   $7,$24,2         	 # Delay slot
34848		 addu  $7,$7,$30
34849		 lw    $7,0x00($7)
34850		 jr    $7
34851		 nop                    	 # Delay slot
34852
34853OP0_5cf9:				#:
34854		 addiu $23,$23,2
34855
34856		 lhu   $14,0x00($23)
34857		 lhu   $25,0x02($23)
34858		 sll   $14,$14,16
34859		 or    $14,$14,$25
34860		 addiu $23,$23,4
34861		 xor   $2,$19,$17
34862		 addiu $2,$2,-1
34863		 lw    $25,0x88($21)
34864		 sw    $15,m68k_ICount
34865		 or    $5,$0,$2
34866		 or    $4,$0,$14
34867		 jalr  $25
34868		 sw    $23,0x4C($21)    	 # Delay slot
34869		 lw    $15,m68k_ICount
34870		 addiu $15,$15,-20
34871		 bgez  $15,3f
34872		 lhu   $24,0x00($23)    	 # Delay slot
34873		 j     MainExit
34874	3:
34875		 sll   $7,$24,2         	 # Delay slot
34876		 addu  $7,$7,$30
34877		 lw    $7,0x00($7)
34878		 jr    $7
34879		 nop                    	 # Delay slot
34880
34881OP0_5dc0:				#:
34882		 addiu $23,$23,2
34883
34884		 andi  $24,$24,0x07
34885		 xor   $2,$19,$17
34886		 subu  $2,$0,$2
34887		 sll   $24,$24,2
34888		 addu  $24,$24,$21
34889		 sb    $2,0x00($24)
34890		 andi  $2,$2,0x02
34891		 addiu $15,$15,-4
34892		 subu  $15,$15,$2
34893		 bgez  $15,3f
34894		 lhu   $24,0x00($23)    	 # Delay slot
34895		 j     MainExit
34896	3:
34897		 sll   $7,$24,2         	 # Delay slot
34898		 addu  $7,$7,$30
34899		 lw    $7,0x00($7)
34900		 jr    $7
34901		 nop                    	 # Delay slot
34902
34903OP0_5dc8:				#:
34904		 bne   $19,$17,1f
34905		 andi  $24,$24,0x07     	 # Delay slot
34906		 sll   $24,$24,2
34907		 addu  $24,$24,$21
34908		 lhu   $8,0x00($24)
34909		 addiu $9,$8,-1
34910		 beq   $8,$0,9f         	 # Is it -1
34911		 sh    $9,0x00($24)     	 # Delay slot
34912
34913		 addiu $23,$23,2
34914
34915		 lh    $2,0x00($23)
34916		 addu  $23,$23,$2
34917		 addiu $15,$15,-10
34918		 bgez  $15,3f
34919		 lhu   $24,0x00($23)    	 # Delay slot
34920		 j     MainExit
34921	3:
34922		 sll   $7,$24,2         	 # Delay slot
34923		 addu  $7,$7,$30
34924		 lw    $7,0x00($7)
34925		 jr    $7
34926		 nop                    	 # Delay slot
34927
34928	9:
34929	1:
34930		 addiu $23,$23,4
34931
34932		 addiu $15,$15,-12
34933		 bgez  $15,3f
34934		 lhu   $24,0x00($23)    	 # Delay slot
34935		 j     MainExit
34936	3:
34937		 sll   $7,$24,2         	 # Delay slot
34938		 addu  $7,$7,$30
34939		 lw    $7,0x00($7)
34940		 jr    $7
34941		 nop                    	 # Delay slot
34942
34943OP0_5dd0:				#:
34944		 addiu $23,$23,2
34945
34946		 andi  $24,$24,0x07
34947		 sll   $24,$24,2
34948		 addu  $24,$24,$21
34949		 lw    $14,0x20($24)
34950		 xor   $2,$19,$17
34951		 subu  $2,$0,$2
34952		 lw    $25,0x88($21)
34953		 sw    $15,m68k_ICount
34954		 or    $5,$0,$2
34955		 or    $4,$0,$14
34956		 jalr  $25
34957		 sw    $23,0x4C($21)    	 # Delay slot
34958		 lw    $15,m68k_ICount
34959		 addiu $15,$15,-12
34960		 bgez  $15,3f
34961		 lhu   $24,0x00($23)    	 # Delay slot
34962		 j     MainExit
34963	3:
34964		 sll   $7,$24,2         	 # Delay slot
34965		 addu  $7,$7,$30
34966		 lw    $7,0x00($7)
34967		 jr    $7
34968		 nop                    	 # Delay slot
34969
34970OP0_5dd8:				#:
34971		 addiu $23,$23,2
34972
34973		 andi  $24,$24,0x07
34974		 sll   $24,$24,2
34975		 addu  $24,$24,$21
34976		 lw    $14,0x20($24)
34977		 addiu $25,$14,1
34978		 sw    $25,0x20($24)
34979		 xor   $2,$19,$17
34980		 subu  $2,$0,$2
34981		 lw    $25,0x88($21)
34982		 sw    $15,m68k_ICount
34983		 or    $5,$0,$2
34984		 or    $4,$0,$14
34985		 jalr  $25
34986		 sw    $23,0x4C($21)    	 # Delay slot
34987		 lw    $15,m68k_ICount
34988		 addiu $15,$15,-12
34989		 bgez  $15,3f
34990		 lhu   $24,0x00($23)    	 # Delay slot
34991		 j     MainExit
34992	3:
34993		 sll   $7,$24,2         	 # Delay slot
34994		 addu  $7,$7,$30
34995		 lw    $7,0x00($7)
34996		 jr    $7
34997		 nop                    	 # Delay slot
34998
34999OP0_5ddf:				#:
35000		 addiu $23,$23,2
35001
35002		 lw    $14,0x3C($21)    	 # Get A7
35003		 addiu $25,$14,2
35004		 sw    $25,0x3C($21)
35005		 xor   $2,$19,$17
35006		 subu  $2,$0,$2
35007		 lw    $25,0x88($21)
35008		 sw    $15,m68k_ICount
35009		 or    $5,$0,$2
35010		 or    $4,$0,$14
35011		 jalr  $25
35012		 sw    $23,0x4C($21)    	 # Delay slot
35013		 lw    $15,m68k_ICount
35014		 addiu $15,$15,-12
35015		 bgez  $15,3f
35016		 lhu   $24,0x00($23)    	 # Delay slot
35017		 j     MainExit
35018	3:
35019		 sll   $7,$24,2         	 # Delay slot
35020		 addu  $7,$7,$30
35021		 lw    $7,0x00($7)
35022		 jr    $7
35023		 nop                    	 # Delay slot
35024
35025OP0_5de0:				#:
35026		 addiu $23,$23,2
35027
35028		 andi  $24,$24,0x07
35029		 sll   $24,$24,2
35030		 addu  $24,$24,$21
35031		 lw    $14,0x20($24)
35032		 addiu $14,$14,-1
35033		 sw    $14,0x20($24)
35034		 xor   $2,$19,$17
35035		 subu  $2,$0,$2
35036		 lw    $25,0x88($21)
35037		 sw    $15,m68k_ICount
35038		 or    $5,$0,$2
35039		 or    $4,$0,$14
35040		 jalr  $25
35041		 sw    $23,0x4C($21)    	 # Delay slot
35042		 lw    $15,m68k_ICount
35043		 addiu $15,$15,-14
35044		 bgez  $15,3f
35045		 lhu   $24,0x00($23)    	 # Delay slot
35046		 j     MainExit
35047	3:
35048		 sll   $7,$24,2         	 # Delay slot
35049		 addu  $7,$7,$30
35050		 lw    $7,0x00($7)
35051		 jr    $7
35052		 nop                    	 # Delay slot
35053
35054OP0_5de7:				#:
35055		 addiu $23,$23,2
35056
35057		 lw    $14,0x3C($21)    	 # Get A7
35058		 addiu $14,$14,-2
35059		 sw    $14,0x3C($21)
35060		 xor   $2,$19,$17
35061		 subu  $2,$0,$2
35062		 lw    $25,0x88($21)
35063		 sw    $15,m68k_ICount
35064		 or    $5,$0,$2
35065		 or    $4,$0,$14
35066		 jalr  $25
35067		 sw    $23,0x4C($21)    	 # Delay slot
35068		 lw    $15,m68k_ICount
35069		 addiu $15,$15,-14
35070		 bgez  $15,3f
35071		 lhu   $24,0x00($23)    	 # Delay slot
35072		 j     MainExit
35073	3:
35074		 sll   $7,$24,2         	 # Delay slot
35075		 addu  $7,$7,$30
35076		 lw    $7,0x00($7)
35077		 jr    $7
35078		 nop                    	 # Delay slot
35079
35080OP0_5de8:				#:
35081		 addiu $23,$23,2
35082
35083		 andi  $24,$24,0x07
35084		 lh    $7,0x00($23)
35085		 sll   $24,$24,2
35086		 addu  $24,$24,$21
35087		 lw    $14,0x20($24)
35088		 addiu $23,$23,2
35089		 addu  $14,$14,$7
35090		 xor   $2,$19,$17
35091		 subu  $2,$0,$2
35092		 lw    $25,0x88($21)
35093		 sw    $15,m68k_ICount
35094		 or    $5,$0,$2
35095		 or    $4,$0,$14
35096		 jalr  $25
35097		 sw    $23,0x4C($21)    	 # Delay slot
35098		 lw    $15,m68k_ICount
35099		 addiu $15,$15,-16
35100		 bgez  $15,3f
35101		 lhu   $24,0x00($23)    	 # Delay slot
35102		 j     MainExit
35103	3:
35104		 sll   $7,$24,2         	 # Delay slot
35105		 addu  $7,$7,$30
35106		 lw    $7,0x00($7)
35107		 jr    $7
35108		 nop                    	 # Delay slot
35109
35110OP0_5df0:				#:
35111		 addiu $23,$23,2
35112
35113		 andi  $24,$24,0x07
35114		 sll   $24,$24,2
35115		 addu  $24,$24,$21
35116		 lw    $14,0x20($24)
35117		 lhu   $7,0x00($23)
35118		 addiu $23,$23,2
35119		 seb   $6,$7
35120		 or    $25,$0,$7
35121		 srl   $7,$7,12
35122		 andi  $25,$25,0x0800
35123		 sll   $7,$7,2
35124		 addu  $7,$7,$21
35125		 bne   $25,$0,0f
35126		 lw    $25,0x00($7)      	 # Delay slot
35127		 seh   $25,$25
35128	0:
35129		 addu  $25,$14,$25
35130		 addu  $14,$25,$6
35131		 xor   $2,$19,$17
35132		 subu  $2,$0,$2
35133		 lw    $25,0x88($21)
35134		 sw    $15,m68k_ICount
35135		 or    $5,$0,$2
35136		 or    $4,$0,$14
35137		 jalr  $25
35138		 sw    $23,0x4C($21)    	 # Delay slot
35139		 lw    $15,m68k_ICount
35140		 addiu $15,$15,-18
35141		 bgez  $15,3f
35142		 lhu   $24,0x00($23)    	 # Delay slot
35143		 j     MainExit
35144	3:
35145		 sll   $7,$24,2         	 # Delay slot
35146		 addu  $7,$7,$30
35147		 lw    $7,0x00($7)
35148		 jr    $7
35149		 nop                    	 # Delay slot
35150
35151OP0_5df8:				#:
35152		 addiu $23,$23,2
35153
35154		 lh    $14,0x00($23)
35155		 addiu $23,$23,2
35156		 xor   $2,$19,$17
35157		 subu  $2,$0,$2
35158		 lw    $25,0x88($21)
35159		 sw    $15,m68k_ICount
35160		 or    $5,$0,$2
35161		 or    $4,$0,$14
35162		 jalr  $25
35163		 sw    $23,0x4C($21)    	 # Delay slot
35164		 lw    $15,m68k_ICount
35165		 addiu $15,$15,-16
35166		 bgez  $15,3f
35167		 lhu   $24,0x00($23)    	 # Delay slot
35168		 j     MainExit
35169	3:
35170		 sll   $7,$24,2         	 # Delay slot
35171		 addu  $7,$7,$30
35172		 lw    $7,0x00($7)
35173		 jr    $7
35174		 nop                    	 # Delay slot
35175
35176OP0_5df9:				#:
35177		 addiu $23,$23,2
35178
35179		 lhu   $14,0x00($23)
35180		 lhu   $25,0x02($23)
35181		 sll   $14,$14,16
35182		 or    $14,$14,$25
35183		 addiu $23,$23,4
35184		 xor   $2,$19,$17
35185		 subu  $2,$0,$2
35186		 lw    $25,0x88($21)
35187		 sw    $15,m68k_ICount
35188		 or    $5,$0,$2
35189		 or    $4,$0,$14
35190		 jalr  $25
35191		 sw    $23,0x4C($21)    	 # Delay slot
35192		 lw    $15,m68k_ICount
35193		 addiu $15,$15,-20
35194		 bgez  $15,3f
35195		 lhu   $24,0x00($23)    	 # Delay slot
35196		 j     MainExit
35197	3:
35198		 sll   $7,$24,2         	 # Delay slot
35199		 addu  $7,$7,$30
35200		 lw    $7,0x00($7)
35201		 jr    $7
35202		 nop                    	 # Delay slot
35203
35204OP0_5ec0:				#:
35205		 addiu $23,$23,2
35206
35207		 andi  $24,$24,0x07
35208		 xor   $2,$19,$17
35209		 or    $2,$2,$18
35210		 addiu $2,$2,-1
35211		 sll   $24,$24,2
35212		 addu  $24,$24,$21
35213		 sb    $2,0x00($24)
35214		 andi  $2,$2,0x02
35215		 addiu $15,$15,-4
35216		 subu  $15,$15,$2
35217		 bgez  $15,3f
35218		 lhu   $24,0x00($23)    	 # Delay slot
35219		 j     MainExit
35220	3:
35221		 sll   $7,$24,2         	 # Delay slot
35222		 addu  $7,$7,$30
35223		 lw    $7,0x00($7)
35224		 jr    $7
35225		 nop                    	 # Delay slot
35226
35227OP0_5ec8:				#:
35228		 xor    $25,$19,$17
35229		 or     $25,$25,$18
35230		 beq   $25,$0,1f
35231		 andi  $24,$24,0x07     	 # Delay slot
35232		 sll   $24,$24,2
35233		 addu  $24,$24,$21
35234		 lhu   $8,0x00($24)
35235		 addiu $9,$8,-1
35236		 beq   $8,$0,9f         	 # Is it -1
35237		 sh    $9,0x00($24)     	 # Delay slot
35238
35239		 addiu $23,$23,2
35240
35241		 lh    $2,0x00($23)
35242		 addu  $23,$23,$2
35243		 addiu $15,$15,-10
35244		 bgez  $15,3f
35245		 lhu   $24,0x00($23)    	 # Delay slot
35246		 j     MainExit
35247	3:
35248		 sll   $7,$24,2         	 # Delay slot
35249		 addu  $7,$7,$30
35250		 lw    $7,0x00($7)
35251		 jr    $7
35252		 nop                    	 # Delay slot
35253
35254	9:
35255	1:
35256		 addiu $23,$23,4
35257
35258		 addiu $15,$15,-12
35259		 bgez  $15,3f
35260		 lhu   $24,0x00($23)    	 # Delay slot
35261		 j     MainExit
35262	3:
35263		 sll   $7,$24,2         	 # Delay slot
35264		 addu  $7,$7,$30
35265		 lw    $7,0x00($7)
35266		 jr    $7
35267		 nop                    	 # Delay slot
35268
35269OP0_5ed0:				#:
35270		 addiu $23,$23,2
35271
35272		 andi  $24,$24,0x07
35273		 sll   $24,$24,2
35274		 addu  $24,$24,$21
35275		 lw    $14,0x20($24)
35276		 xor   $2,$19,$17
35277		 or    $2,$2,$18
35278		 addiu $2,$2,-1
35279		 lw    $25,0x88($21)
35280		 sw    $15,m68k_ICount
35281		 or    $5,$0,$2
35282		 or    $4,$0,$14
35283		 jalr  $25
35284		 sw    $23,0x4C($21)    	 # Delay slot
35285		 lw    $15,m68k_ICount
35286		 addiu $15,$15,-12
35287		 bgez  $15,3f
35288		 lhu   $24,0x00($23)    	 # Delay slot
35289		 j     MainExit
35290	3:
35291		 sll   $7,$24,2         	 # Delay slot
35292		 addu  $7,$7,$30
35293		 lw    $7,0x00($7)
35294		 jr    $7
35295		 nop                    	 # Delay slot
35296
35297OP0_5ed8:				#:
35298		 addiu $23,$23,2
35299
35300		 andi  $24,$24,0x07
35301		 sll   $24,$24,2
35302		 addu  $24,$24,$21
35303		 lw    $14,0x20($24)
35304		 addiu $25,$14,1
35305		 sw    $25,0x20($24)
35306		 xor   $2,$19,$17
35307		 or    $2,$2,$18
35308		 addiu $2,$2,-1
35309		 lw    $25,0x88($21)
35310		 sw    $15,m68k_ICount
35311		 or    $5,$0,$2
35312		 or    $4,$0,$14
35313		 jalr  $25
35314		 sw    $23,0x4C($21)    	 # Delay slot
35315		 lw    $15,m68k_ICount
35316		 addiu $15,$15,-12
35317		 bgez  $15,3f
35318		 lhu   $24,0x00($23)    	 # Delay slot
35319		 j     MainExit
35320	3:
35321		 sll   $7,$24,2         	 # Delay slot
35322		 addu  $7,$7,$30
35323		 lw    $7,0x00($7)
35324		 jr    $7
35325		 nop                    	 # Delay slot
35326
35327OP0_5edf:				#:
35328		 addiu $23,$23,2
35329
35330		 lw    $14,0x3C($21)    	 # Get A7
35331		 addiu $25,$14,2
35332		 sw    $25,0x3C($21)
35333		 xor   $2,$19,$17
35334		 or    $2,$2,$18
35335		 addiu $2,$2,-1
35336		 lw    $25,0x88($21)
35337		 sw    $15,m68k_ICount
35338		 or    $5,$0,$2
35339		 or    $4,$0,$14
35340		 jalr  $25
35341		 sw    $23,0x4C($21)    	 # Delay slot
35342		 lw    $15,m68k_ICount
35343		 addiu $15,$15,-12
35344		 bgez  $15,3f
35345		 lhu   $24,0x00($23)    	 # Delay slot
35346		 j     MainExit
35347	3:
35348		 sll   $7,$24,2         	 # Delay slot
35349		 addu  $7,$7,$30
35350		 lw    $7,0x00($7)
35351		 jr    $7
35352		 nop                    	 # Delay slot
35353
35354OP0_5ee0:				#:
35355		 addiu $23,$23,2
35356
35357		 andi  $24,$24,0x07
35358		 sll   $24,$24,2
35359		 addu  $24,$24,$21
35360		 lw    $14,0x20($24)
35361		 addiu $14,$14,-1
35362		 sw    $14,0x20($24)
35363		 xor   $2,$19,$17
35364		 or    $2,$2,$18
35365		 addiu $2,$2,-1
35366		 lw    $25,0x88($21)
35367		 sw    $15,m68k_ICount
35368		 or    $5,$0,$2
35369		 or    $4,$0,$14
35370		 jalr  $25
35371		 sw    $23,0x4C($21)    	 # Delay slot
35372		 lw    $15,m68k_ICount
35373		 addiu $15,$15,-14
35374		 bgez  $15,3f
35375		 lhu   $24,0x00($23)    	 # Delay slot
35376		 j     MainExit
35377	3:
35378		 sll   $7,$24,2         	 # Delay slot
35379		 addu  $7,$7,$30
35380		 lw    $7,0x00($7)
35381		 jr    $7
35382		 nop                    	 # Delay slot
35383
35384OP0_5ee7:				#:
35385		 addiu $23,$23,2
35386
35387		 lw    $14,0x3C($21)    	 # Get A7
35388		 addiu $14,$14,-2
35389		 sw    $14,0x3C($21)
35390		 xor   $2,$19,$17
35391		 or    $2,$2,$18
35392		 addiu $2,$2,-1
35393		 lw    $25,0x88($21)
35394		 sw    $15,m68k_ICount
35395		 or    $5,$0,$2
35396		 or    $4,$0,$14
35397		 jalr  $25
35398		 sw    $23,0x4C($21)    	 # Delay slot
35399		 lw    $15,m68k_ICount
35400		 addiu $15,$15,-14
35401		 bgez  $15,3f
35402		 lhu   $24,0x00($23)    	 # Delay slot
35403		 j     MainExit
35404	3:
35405		 sll   $7,$24,2         	 # Delay slot
35406		 addu  $7,$7,$30
35407		 lw    $7,0x00($7)
35408		 jr    $7
35409		 nop                    	 # Delay slot
35410
35411OP0_5ee8:				#:
35412		 addiu $23,$23,2
35413
35414		 andi  $24,$24,0x07
35415		 lh    $7,0x00($23)
35416		 sll   $24,$24,2
35417		 addu  $24,$24,$21
35418		 lw    $14,0x20($24)
35419		 addiu $23,$23,2
35420		 addu  $14,$14,$7
35421		 xor   $2,$19,$17
35422		 or    $2,$2,$18
35423		 addiu $2,$2,-1
35424		 lw    $25,0x88($21)
35425		 sw    $15,m68k_ICount
35426		 or    $5,$0,$2
35427		 or    $4,$0,$14
35428		 jalr  $25
35429		 sw    $23,0x4C($21)    	 # Delay slot
35430		 lw    $15,m68k_ICount
35431		 addiu $15,$15,-16
35432		 bgez  $15,3f
35433		 lhu   $24,0x00($23)    	 # Delay slot
35434		 j     MainExit
35435	3:
35436		 sll   $7,$24,2         	 # Delay slot
35437		 addu  $7,$7,$30
35438		 lw    $7,0x00($7)
35439		 jr    $7
35440		 nop                    	 # Delay slot
35441
35442OP0_5ef0:				#:
35443		 addiu $23,$23,2
35444
35445		 andi  $24,$24,0x07
35446		 sll   $24,$24,2
35447		 addu  $24,$24,$21
35448		 lw    $14,0x20($24)
35449		 lhu   $7,0x00($23)
35450		 addiu $23,$23,2
35451		 seb   $6,$7
35452		 or    $25,$0,$7
35453		 srl   $7,$7,12
35454		 andi  $25,$25,0x0800
35455		 sll   $7,$7,2
35456		 addu  $7,$7,$21
35457		 bne   $25,$0,0f
35458		 lw    $25,0x00($7)      	 # Delay slot
35459		 seh   $25,$25
35460	0:
35461		 addu  $25,$14,$25
35462		 addu  $14,$25,$6
35463		 xor   $2,$19,$17
35464		 or    $2,$2,$18
35465		 addiu $2,$2,-1
35466		 lw    $25,0x88($21)
35467		 sw    $15,m68k_ICount
35468		 or    $5,$0,$2
35469		 or    $4,$0,$14
35470		 jalr  $25
35471		 sw    $23,0x4C($21)    	 # Delay slot
35472		 lw    $15,m68k_ICount
35473		 addiu $15,$15,-18
35474		 bgez  $15,3f
35475		 lhu   $24,0x00($23)    	 # Delay slot
35476		 j     MainExit
35477	3:
35478		 sll   $7,$24,2         	 # Delay slot
35479		 addu  $7,$7,$30
35480		 lw    $7,0x00($7)
35481		 jr    $7
35482		 nop                    	 # Delay slot
35483
35484OP0_5ef8:				#:
35485		 addiu $23,$23,2
35486
35487		 lh    $14,0x00($23)
35488		 addiu $23,$23,2
35489		 xor   $2,$19,$17
35490		 or    $2,$2,$18
35491		 addiu $2,$2,-1
35492		 lw    $25,0x88($21)
35493		 sw    $15,m68k_ICount
35494		 or    $5,$0,$2
35495		 or    $4,$0,$14
35496		 jalr  $25
35497		 sw    $23,0x4C($21)    	 # Delay slot
35498		 lw    $15,m68k_ICount
35499		 addiu $15,$15,-16
35500		 bgez  $15,3f
35501		 lhu   $24,0x00($23)    	 # Delay slot
35502		 j     MainExit
35503	3:
35504		 sll   $7,$24,2         	 # Delay slot
35505		 addu  $7,$7,$30
35506		 lw    $7,0x00($7)
35507		 jr    $7
35508		 nop                    	 # Delay slot
35509
35510OP0_5ef9:				#:
35511		 addiu $23,$23,2
35512
35513		 lhu   $14,0x00($23)
35514		 lhu   $25,0x02($23)
35515		 sll   $14,$14,16
35516		 or    $14,$14,$25
35517		 addiu $23,$23,4
35518		 xor   $2,$19,$17
35519		 or    $2,$2,$18
35520		 addiu $2,$2,-1
35521		 lw    $25,0x88($21)
35522		 sw    $15,m68k_ICount
35523		 or    $5,$0,$2
35524		 or    $4,$0,$14
35525		 jalr  $25
35526		 sw    $23,0x4C($21)    	 # Delay slot
35527		 lw    $15,m68k_ICount
35528		 addiu $15,$15,-20
35529		 bgez  $15,3f
35530		 lhu   $24,0x00($23)    	 # Delay slot
35531		 j     MainExit
35532	3:
35533		 sll   $7,$24,2         	 # Delay slot
35534		 addu  $7,$7,$30
35535		 lw    $7,0x00($7)
35536		 jr    $7
35537		 nop                    	 # Delay slot
35538
35539OP0_5fc0:				#:
35540		 addiu $23,$23,2
35541
35542		 andi  $24,$24,0x07
35543		 xor   $2,$19,$17
35544		 or    $2,$2,$18
35545		 subu  $2,$0,$2
35546		 sll   $24,$24,2
35547		 addu  $24,$24,$21
35548		 sb    $2,0x00($24)
35549		 andi  $2,$2,0x02
35550		 addiu $15,$15,-4
35551		 subu  $15,$15,$2
35552		 bgez  $15,3f
35553		 lhu   $24,0x00($23)    	 # Delay slot
35554		 j     MainExit
35555	3:
35556		 sll   $7,$24,2         	 # Delay slot
35557		 addu  $7,$7,$30
35558		 lw    $7,0x00($7)
35559		 jr    $7
35560		 nop                    	 # Delay slot
35561
35562OP0_5fc8:				#:
35563		 xor    $25,$19,$17
35564		 or     $25,$25,$18
35565		 bne   $25,$0,1f
35566		 andi  $24,$24,0x07     	 # Delay slot
35567		 sll   $24,$24,2
35568		 addu  $24,$24,$21
35569		 lhu   $8,0x00($24)
35570		 addiu $9,$8,-1
35571		 beq   $8,$0,9f         	 # Is it -1
35572		 sh    $9,0x00($24)     	 # Delay slot
35573
35574		 addiu $23,$23,2
35575
35576		 lh    $2,0x00($23)
35577		 addu  $23,$23,$2
35578		 addiu $15,$15,-10
35579		 bgez  $15,3f
35580		 lhu   $24,0x00($23)    	 # Delay slot
35581		 j     MainExit
35582	3:
35583		 sll   $7,$24,2         	 # Delay slot
35584		 addu  $7,$7,$30
35585		 lw    $7,0x00($7)
35586		 jr    $7
35587		 nop                    	 # Delay slot
35588
35589	9:
35590	1:
35591		 addiu $23,$23,4
35592
35593		 addiu $15,$15,-12
35594		 bgez  $15,3f
35595		 lhu   $24,0x00($23)    	 # Delay slot
35596		 j     MainExit
35597	3:
35598		 sll   $7,$24,2         	 # Delay slot
35599		 addu  $7,$7,$30
35600		 lw    $7,0x00($7)
35601		 jr    $7
35602		 nop                    	 # Delay slot
35603
35604OP0_5fd0:				#:
35605		 addiu $23,$23,2
35606
35607		 andi  $24,$24,0x07
35608		 sll   $24,$24,2
35609		 addu  $24,$24,$21
35610		 lw    $14,0x20($24)
35611		 xor   $2,$19,$17
35612		 or    $2,$2,$18
35613		 subu  $2,$0,$2
35614		 lw    $25,0x88($21)
35615		 sw    $15,m68k_ICount
35616		 or    $5,$0,$2
35617		 or    $4,$0,$14
35618		 jalr  $25
35619		 sw    $23,0x4C($21)    	 # Delay slot
35620		 lw    $15,m68k_ICount
35621		 addiu $15,$15,-12
35622		 bgez  $15,3f
35623		 lhu   $24,0x00($23)    	 # Delay slot
35624		 j     MainExit
35625	3:
35626		 sll   $7,$24,2         	 # Delay slot
35627		 addu  $7,$7,$30
35628		 lw    $7,0x00($7)
35629		 jr    $7
35630		 nop                    	 # Delay slot
35631
35632OP0_5fd8:				#:
35633		 addiu $23,$23,2
35634
35635		 andi  $24,$24,0x07
35636		 sll   $24,$24,2
35637		 addu  $24,$24,$21
35638		 lw    $14,0x20($24)
35639		 addiu $25,$14,1
35640		 sw    $25,0x20($24)
35641		 xor   $2,$19,$17
35642		 or    $2,$2,$18
35643		 subu  $2,$0,$2
35644		 lw    $25,0x88($21)
35645		 sw    $15,m68k_ICount
35646		 or    $5,$0,$2
35647		 or    $4,$0,$14
35648		 jalr  $25
35649		 sw    $23,0x4C($21)    	 # Delay slot
35650		 lw    $15,m68k_ICount
35651		 addiu $15,$15,-12
35652		 bgez  $15,3f
35653		 lhu   $24,0x00($23)    	 # Delay slot
35654		 j     MainExit
35655	3:
35656		 sll   $7,$24,2         	 # Delay slot
35657		 addu  $7,$7,$30
35658		 lw    $7,0x00($7)
35659		 jr    $7
35660		 nop                    	 # Delay slot
35661
35662OP0_5fdf:				#:
35663		 addiu $23,$23,2
35664
35665		 lw    $14,0x3C($21)    	 # Get A7
35666		 addiu $25,$14,2
35667		 sw    $25,0x3C($21)
35668		 xor   $2,$19,$17
35669		 or    $2,$2,$18
35670		 subu  $2,$0,$2
35671		 lw    $25,0x88($21)
35672		 sw    $15,m68k_ICount
35673		 or    $5,$0,$2
35674		 or    $4,$0,$14
35675		 jalr  $25
35676		 sw    $23,0x4C($21)    	 # Delay slot
35677		 lw    $15,m68k_ICount
35678		 addiu $15,$15,-12
35679		 bgez  $15,3f
35680		 lhu   $24,0x00($23)    	 # Delay slot
35681		 j     MainExit
35682	3:
35683		 sll   $7,$24,2         	 # Delay slot
35684		 addu  $7,$7,$30
35685		 lw    $7,0x00($7)
35686		 jr    $7
35687		 nop                    	 # Delay slot
35688
35689OP0_5fe0:				#:
35690		 addiu $23,$23,2
35691
35692		 andi  $24,$24,0x07
35693		 sll   $24,$24,2
35694		 addu  $24,$24,$21
35695		 lw    $14,0x20($24)
35696		 addiu $14,$14,-1
35697		 sw    $14,0x20($24)
35698		 xor   $2,$19,$17
35699		 or    $2,$2,$18
35700		 subu  $2,$0,$2
35701		 lw    $25,0x88($21)
35702		 sw    $15,m68k_ICount
35703		 or    $5,$0,$2
35704		 or    $4,$0,$14
35705		 jalr  $25
35706		 sw    $23,0x4C($21)    	 # Delay slot
35707		 lw    $15,m68k_ICount
35708		 addiu $15,$15,-14
35709		 bgez  $15,3f
35710		 lhu   $24,0x00($23)    	 # Delay slot
35711		 j     MainExit
35712	3:
35713		 sll   $7,$24,2         	 # Delay slot
35714		 addu  $7,$7,$30
35715		 lw    $7,0x00($7)
35716		 jr    $7
35717		 nop                    	 # Delay slot
35718
35719OP0_5fe7:				#:
35720		 addiu $23,$23,2
35721
35722		 lw    $14,0x3C($21)    	 # Get A7
35723		 addiu $14,$14,-2
35724		 sw    $14,0x3C($21)
35725		 xor   $2,$19,$17
35726		 or    $2,$2,$18
35727		 subu  $2,$0,$2
35728		 lw    $25,0x88($21)
35729		 sw    $15,m68k_ICount
35730		 or    $5,$0,$2
35731		 or    $4,$0,$14
35732		 jalr  $25
35733		 sw    $23,0x4C($21)    	 # Delay slot
35734		 lw    $15,m68k_ICount
35735		 addiu $15,$15,-14
35736		 bgez  $15,3f
35737		 lhu   $24,0x00($23)    	 # Delay slot
35738		 j     MainExit
35739	3:
35740		 sll   $7,$24,2         	 # Delay slot
35741		 addu  $7,$7,$30
35742		 lw    $7,0x00($7)
35743		 jr    $7
35744		 nop                    	 # Delay slot
35745
35746OP0_5fe8:				#:
35747		 addiu $23,$23,2
35748
35749		 andi  $24,$24,0x07
35750		 lh    $7,0x00($23)
35751		 sll   $24,$24,2
35752		 addu  $24,$24,$21
35753		 lw    $14,0x20($24)
35754		 addiu $23,$23,2
35755		 addu  $14,$14,$7
35756		 xor   $2,$19,$17
35757		 or    $2,$2,$18
35758		 subu  $2,$0,$2
35759		 lw    $25,0x88($21)
35760		 sw    $15,m68k_ICount
35761		 or    $5,$0,$2
35762		 or    $4,$0,$14
35763		 jalr  $25
35764		 sw    $23,0x4C($21)    	 # Delay slot
35765		 lw    $15,m68k_ICount
35766		 addiu $15,$15,-16
35767		 bgez  $15,3f
35768		 lhu   $24,0x00($23)    	 # Delay slot
35769		 j     MainExit
35770	3:
35771		 sll   $7,$24,2         	 # Delay slot
35772		 addu  $7,$7,$30
35773		 lw    $7,0x00($7)
35774		 jr    $7
35775		 nop                    	 # Delay slot
35776
35777OP0_5ff0:				#:
35778		 addiu $23,$23,2
35779
35780		 andi  $24,$24,0x07
35781		 sll   $24,$24,2
35782		 addu  $24,$24,$21
35783		 lw    $14,0x20($24)
35784		 lhu   $7,0x00($23)
35785		 addiu $23,$23,2
35786		 seb   $6,$7
35787		 or    $25,$0,$7
35788		 srl   $7,$7,12
35789		 andi  $25,$25,0x0800
35790		 sll   $7,$7,2
35791		 addu  $7,$7,$21
35792		 bne   $25,$0,0f
35793		 lw    $25,0x00($7)      	 # Delay slot
35794		 seh   $25,$25
35795	0:
35796		 addu  $25,$14,$25
35797		 addu  $14,$25,$6
35798		 xor   $2,$19,$17
35799		 or    $2,$2,$18
35800		 subu  $2,$0,$2
35801		 lw    $25,0x88($21)
35802		 sw    $15,m68k_ICount
35803		 or    $5,$0,$2
35804		 or    $4,$0,$14
35805		 jalr  $25
35806		 sw    $23,0x4C($21)    	 # Delay slot
35807		 lw    $15,m68k_ICount
35808		 addiu $15,$15,-18
35809		 bgez  $15,3f
35810		 lhu   $24,0x00($23)    	 # Delay slot
35811		 j     MainExit
35812	3:
35813		 sll   $7,$24,2         	 # Delay slot
35814		 addu  $7,$7,$30
35815		 lw    $7,0x00($7)
35816		 jr    $7
35817		 nop                    	 # Delay slot
35818
35819OP0_5ff8:				#:
35820		 addiu $23,$23,2
35821
35822		 lh    $14,0x00($23)
35823		 addiu $23,$23,2
35824		 xor   $2,$19,$17
35825		 or    $2,$2,$18
35826		 subu  $2,$0,$2
35827		 lw    $25,0x88($21)
35828		 sw    $15,m68k_ICount
35829		 or    $5,$0,$2
35830		 or    $4,$0,$14
35831		 jalr  $25
35832		 sw    $23,0x4C($21)    	 # Delay slot
35833		 lw    $15,m68k_ICount
35834		 addiu $15,$15,-16
35835		 bgez  $15,3f
35836		 lhu   $24,0x00($23)    	 # Delay slot
35837		 j     MainExit
35838	3:
35839		 sll   $7,$24,2         	 # Delay slot
35840		 addu  $7,$7,$30
35841		 lw    $7,0x00($7)
35842		 jr    $7
35843		 nop                    	 # Delay slot
35844
35845OP0_5ff9:				#:
35846		 addiu $23,$23,2
35847
35848		 lhu   $14,0x00($23)
35849		 lhu   $25,0x02($23)
35850		 sll   $14,$14,16
35851		 or    $14,$14,$25
35852		 addiu $23,$23,4
35853		 xor   $2,$19,$17
35854		 or    $2,$2,$18
35855		 subu  $2,$0,$2
35856		 lw    $25,0x88($21)
35857		 sw    $15,m68k_ICount
35858		 or    $5,$0,$2
35859		 or    $4,$0,$14
35860		 jalr  $25
35861		 sw    $23,0x4C($21)    	 # Delay slot
35862		 lw    $15,m68k_ICount
35863		 addiu $15,$15,-20
35864		 bgez  $15,3f
35865		 lhu   $24,0x00($23)    	 # Delay slot
35866		 j     MainExit
35867	3:
35868		 sll   $7,$24,2         	 # Delay slot
35869		 addu  $7,$7,$30
35870		 lw    $7,0x00($7)
35871		 jr    $7
35872		 nop                    	 # Delay slot
35873
35874OP0_6000:				#:
35875		 addiu $23,$23,2
35876
35877		 lh    $2,0x00($23)
35878		 addu  $23,$23,$2
35879		 andi  $25,$23,0x01
35880		 beq   $25,$0,2f
35881		 subu  $5,$23,$22     	 # Delay slot
35882		 addiu $23,$23,-2
35883		 jal   Exception
35884		 ori   $2,$0,3
35885
35886		 addiu $15,$15,-10
35887		 bgez  $15,3f
35888		 lhu   $24,0x00($23)    	 # Delay slot
35889		 j     MainExit
35890	3:
35891		 sll   $7,$24,2         	 # Delay slot
35892		 addu  $7,$7,$30
35893		 lw    $7,0x00($7)
35894		 jr    $7
35895		 nop                    	 # Delay slot
35896
35897	2:
35898		 sw    $5,0x74($21)
35899		 lw    $6,mem_amask
35900		 lw    $25,0x94($21)
35901		 and   $23,$5,$6
35902		 sw    $15,m68k_ICount
35903		 jalr  $25
35904		 or    $4,$0,$23   	 # Delay slot
35905		 lw    $15,m68k_ICount
35906		 lw    $22,OP_ROM
35907		 addu  $23,$23,$22
35908 # End of Banking code:
35909		 addiu $15,$15,-10
35910		 bgez  $15,3f
35911		 lhu   $24,0x00($23)    	 # Delay slot
35912		 j     MainExit
35913	3:
35914		 sll   $7,$24,2         	 # Delay slot
35915		 addu  $7,$7,$30
35916		 lw    $7,0x00($7)
35917		 jr    $7
35918		 nop                    	 # Delay slot
35919
35920OP0_6001:				#:
35921		 addiu $23,$23,2
35922
35923		 seb   $24,$24
35924		 addu  $23,$23,$24
35925		 andi  $25,$23,0x01
35926		 beq   $25,$0,2f
35927		 subu  $5,$23,$22     	 # Delay slot
35928		 addiu $23,$23,-2
35929		 jal   Exception
35930		 ori   $2,$0,3
35931
35932		 addiu $15,$15,-10
35933		 bgez  $15,3f
35934		 lhu   $24,0x00($23)    	 # Delay slot
35935		 j     MainExit
35936	3:
35937		 sll   $7,$24,2         	 # Delay slot
35938		 addu  $7,$7,$30
35939		 lw    $7,0x00($7)
35940		 jr    $7
35941		 nop                    	 # Delay slot
35942
35943	2:
35944		 sw    $5,0x74($21)
35945		 lw    $6,mem_amask
35946		 lw    $25,0x94($21)
35947		 and   $23,$5,$6
35948		 sw    $15,m68k_ICount
35949		 jalr  $25
35950		 or    $4,$0,$23   	 # Delay slot
35951		 lw    $15,m68k_ICount
35952		 lw    $22,OP_ROM
35953		 addu  $23,$23,$22
35954 # End of Banking code:
35955		 addiu $15,$15,-10
35956		 bgez  $15,3f
35957		 lhu   $24,0x00($23)    	 # Delay slot
35958		 j     MainExit
35959	3:
35960		 sll   $7,$24,2         	 # Delay slot
35961		 addu  $7,$7,$30
35962		 lw    $7,0x00($7)
35963		 jr    $7
35964		 nop                    	 # Delay slot
35965
35966OP0_6100:				#:
35967		 addiu $23,$23,2
35968
35969		 lh    $24,0x00($23)
35970		 addu  $24,$23,$24
35971		 addiu $23,$23,2
35972		 lw    $5,0x74($21)
35973		 lui   $25,0xFF00
35974		 lw    $4,0x3C($21)     	 # Push onto Stack
35975		 and   $5,$5,$25
35976		 subu  $25,$23,$22
35977		 addiu $4,$4,-4
35978		 sw    $4,0x3C($21)
35979		 or    $5,$5,$25
35980		 lw    $25,0x90($21)
35981		 sw    $15,m68k_ICount
35982		 sw    $24,0x44($29)
35983		 jalr  $25
35984		 sw    $23,0x4C($21)    	 # Delay slot
35985		 lw    $24,0x44($29)
35986		 lw    $15,m68k_ICount
35987		 or    $23,$0,$24
35988
35989		 andi  $25,$23,0x01
35990		 beq   $25,$0,2f
35991		 subu  $5,$23,$22     	 # Delay slot
35992		 addiu $23,$23,-2
35993		 jal   Exception
35994		 ori   $2,$0,3
35995
35996		 addiu $15,$15,-18
35997		 bgez  $15,3f
35998		 lhu   $24,0x00($23)    	 # Delay slot
35999		 j     MainExit
36000	3:
36001		 sll   $7,$24,2         	 # Delay slot
36002		 addu  $7,$7,$30
36003		 lw    $7,0x00($7)
36004		 jr    $7
36005		 nop                    	 # Delay slot
36006
36007	2:
36008		 sw    $5,0x74($21)
36009		 lw    $6,mem_amask
36010		 lw    $25,0x94($21)
36011		 and   $23,$5,$6
36012		 sw    $15,m68k_ICount
36013		 jalr  $25
36014		 or    $4,$0,$23   	 # Delay slot
36015		 lw    $15,m68k_ICount
36016		 lw    $22,OP_ROM
36017		 addu  $23,$23,$22
36018 # End of Banking code:
36019		 addiu $15,$15,-18
36020		 bgez  $15,3f
36021		 lhu   $24,0x00($23)    	 # Delay slot
36022		 j     MainExit
36023	3:
36024		 sll   $7,$24,2         	 # Delay slot
36025		 addu  $7,$7,$30
36026		 lw    $7,0x00($7)
36027		 jr    $7
36028		 nop                    	 # Delay slot
36029
36030OP0_6101:				#:
36031		 addiu $23,$23,2
36032
36033		 lw    $5,0x74($21)
36034		 lui   $25,0xFF00
36035		 lw    $4,0x3C($21)     	 # Push onto Stack
36036		 and   $5,$5,$25
36037		 subu  $25,$23,$22
36038		 addiu $4,$4,-4
36039		 sw    $4,0x3C($21)
36040		 or    $5,$5,$25
36041		 lw    $25,0x90($21)
36042		 sw    $15,m68k_ICount
36043		 sw    $24,0x44($29)
36044		 jalr  $25
36045		 sw    $23,0x4C($21)    	 # Delay slot
36046		 lw    $24,0x44($29)
36047		 lw    $15,m68k_ICount
36048		 seb   $24,$24
36049		 addu  $23,$23,$24
36050		 andi  $25,$23,0x01
36051		 beq   $25,$0,2f
36052		 subu  $5,$23,$22     	 # Delay slot
36053		 addiu $23,$23,-2
36054		 jal   Exception
36055		 ori   $2,$0,3
36056
36057		 addiu $15,$15,-18
36058		 bgez  $15,3f
36059		 lhu   $24,0x00($23)    	 # Delay slot
36060		 j     MainExit
36061	3:
36062		 sll   $7,$24,2         	 # Delay slot
36063		 addu  $7,$7,$30
36064		 lw    $7,0x00($7)
36065		 jr    $7
36066		 nop                    	 # Delay slot
36067
36068	2:
36069		 sw    $5,0x74($21)
36070		 lw    $6,mem_amask
36071		 lw    $25,0x94($21)
36072		 and   $23,$5,$6
36073		 sw    $15,m68k_ICount
36074		 jalr  $25
36075		 or    $4,$0,$23   	 # Delay slot
36076		 lw    $15,m68k_ICount
36077		 lw    $22,OP_ROM
36078		 addu  $23,$23,$22
36079 # End of Banking code:
36080		 addiu $15,$15,-18
36081		 bgez  $15,3f
36082		 lhu   $24,0x00($23)    	 # Delay slot
36083		 j     MainExit
36084	3:
36085		 sll   $7,$24,2         	 # Delay slot
36086		 addu  $7,$7,$30
36087		 lw    $7,0x00($7)
36088		 jr    $7
36089		 nop                    	 # Delay slot
36090
36091OP0_6200:				#:
36092		 nor   $25,$16,$18
36093		 andi  $25,$25,1
36094		 bne   $25,$0,1f
36095		 addiu $23,$23,2        	 # Delay slot
36096
36097		 addiu $23,$23,2
36098		 addiu $15,$15,-8
36099		 bgez  $15,3f
36100		 lhu   $24,0x00($23)    	 # Delay slot
36101		 j     MainExit
36102	3:
36103		 sll   $7,$24,2         	 # Delay slot
36104		 addu  $7,$7,$30
36105		 lw    $7,0x00($7)
36106		 jr    $7
36107		 nop                    	 # Delay slot
36108
36109	1:
36110		 lh    $2,0x00($23)
36111		 addu  $23,$23,$2
36112		 andi  $25,$23,0x01
36113		 beq   $25,$0,2f
36114		 subu  $5,$23,$22     	 # Delay slot
36115		 addiu $23,$23,-2
36116		 jal   Exception
36117		 ori   $2,$0,3
36118
36119		 addiu $15,$15,-10
36120		 bgez  $15,3f
36121		 lhu   $24,0x00($23)    	 # Delay slot
36122		 j     MainExit
36123	3:
36124		 sll   $7,$24,2         	 # Delay slot
36125		 addu  $7,$7,$30
36126		 lw    $7,0x00($7)
36127		 jr    $7
36128		 nop                    	 # Delay slot
36129
36130	2:
36131		 sw    $5,0x74($21)
36132		 lw    $6,mem_amask
36133		 lw    $25,0x94($21)
36134		 and   $23,$5,$6
36135		 sw    $15,m68k_ICount
36136		 jalr  $25
36137		 or    $4,$0,$23   	 # Delay slot
36138		 lw    $15,m68k_ICount
36139		 lw    $22,OP_ROM
36140		 addu  $23,$23,$22
36141 # End of Banking code:
36142		 addiu $15,$15,-10
36143		 bgez  $15,3f
36144		 lhu   $24,0x00($23)    	 # Delay slot
36145		 j     MainExit
36146	3:
36147		 sll   $7,$24,2         	 # Delay slot
36148		 addu  $7,$7,$30
36149		 lw    $7,0x00($7)
36150		 jr    $7
36151		 nop                    	 # Delay slot
36152
36153OP0_6201:				#:
36154		 nor   $25,$16,$18
36155		 andi  $25,$25,1
36156		 bne   $25,$0,1f
36157		 addiu $23,$23,2        	 # Delay slot
36158
36159		 addiu $15,$15,-8
36160		 bgez  $15,3f
36161		 lhu   $24,0x00($23)    	 # Delay slot
36162		 j     MainExit
36163	3:
36164		 sll   $7,$24,2         	 # Delay slot
36165		 addu  $7,$7,$30
36166		 lw    $7,0x00($7)
36167		 jr    $7
36168		 nop                    	 # Delay slot
36169
36170	1:
36171		 seb   $24,$24
36172		 addu  $23,$23,$24
36173		 andi  $25,$23,0x01
36174		 beq   $25,$0,2f
36175		 subu  $5,$23,$22     	 # Delay slot
36176		 addiu $23,$23,-2
36177		 jal   Exception
36178		 ori   $2,$0,3
36179
36180		 addiu $15,$15,-10
36181		 bgez  $15,3f
36182		 lhu   $24,0x00($23)    	 # Delay slot
36183		 j     MainExit
36184	3:
36185		 sll   $7,$24,2         	 # Delay slot
36186		 addu  $7,$7,$30
36187		 lw    $7,0x00($7)
36188		 jr    $7
36189		 nop                    	 # Delay slot
36190
36191	2:
36192		 sw    $5,0x74($21)
36193		 lw    $6,mem_amask
36194		 lw    $25,0x94($21)
36195		 and   $23,$5,$6
36196		 sw    $15,m68k_ICount
36197		 jalr  $25
36198		 or    $4,$0,$23   	 # Delay slot
36199		 lw    $15,m68k_ICount
36200		 lw    $22,OP_ROM
36201		 addu  $23,$23,$22
36202 # End of Banking code:
36203		 addiu $15,$15,-10
36204		 bgez  $15,3f
36205		 lhu   $24,0x00($23)    	 # Delay slot
36206		 j     MainExit
36207	3:
36208		 sll   $7,$24,2         	 # Delay slot
36209		 addu  $7,$7,$30
36210		 lw    $7,0x00($7)
36211		 jr    $7
36212		 nop                    	 # Delay slot
36213
36214OP0_6300:				#:
36215		 or   $25,$16,$18
36216		 bne   $25,$0,1f
36217		 addiu $23,$23,2        	 # Delay slot
36218
36219		 addiu $23,$23,2
36220		 addiu $15,$15,-8
36221		 bgez  $15,3f
36222		 lhu   $24,0x00($23)    	 # Delay slot
36223		 j     MainExit
36224	3:
36225		 sll   $7,$24,2         	 # Delay slot
36226		 addu  $7,$7,$30
36227		 lw    $7,0x00($7)
36228		 jr    $7
36229		 nop                    	 # Delay slot
36230
36231	1:
36232		 lh    $2,0x00($23)
36233		 addu  $23,$23,$2
36234		 andi  $25,$23,0x01
36235		 beq   $25,$0,2f
36236		 subu  $5,$23,$22     	 # Delay slot
36237		 addiu $23,$23,-2
36238		 jal   Exception
36239		 ori   $2,$0,3
36240
36241		 addiu $15,$15,-10
36242		 bgez  $15,3f
36243		 lhu   $24,0x00($23)    	 # Delay slot
36244		 j     MainExit
36245	3:
36246		 sll   $7,$24,2         	 # Delay slot
36247		 addu  $7,$7,$30
36248		 lw    $7,0x00($7)
36249		 jr    $7
36250		 nop                    	 # Delay slot
36251
36252	2:
36253		 sw    $5,0x74($21)
36254		 lw    $6,mem_amask
36255		 lw    $25,0x94($21)
36256		 and   $23,$5,$6
36257		 sw    $15,m68k_ICount
36258		 jalr  $25
36259		 or    $4,$0,$23   	 # Delay slot
36260		 lw    $15,m68k_ICount
36261		 lw    $22,OP_ROM
36262		 addu  $23,$23,$22
36263 # End of Banking code:
36264		 addiu $15,$15,-10
36265		 bgez  $15,3f
36266		 lhu   $24,0x00($23)    	 # Delay slot
36267		 j     MainExit
36268	3:
36269		 sll   $7,$24,2         	 # Delay slot
36270		 addu  $7,$7,$30
36271		 lw    $7,0x00($7)
36272		 jr    $7
36273		 nop                    	 # Delay slot
36274
36275OP0_6301:				#:
36276		 or   $25,$16,$18
36277		 bne   $25,$0,1f
36278		 addiu $23,$23,2        	 # Delay slot
36279
36280		 addiu $15,$15,-8
36281		 bgez  $15,3f
36282		 lhu   $24,0x00($23)    	 # Delay slot
36283		 j     MainExit
36284	3:
36285		 sll   $7,$24,2         	 # Delay slot
36286		 addu  $7,$7,$30
36287		 lw    $7,0x00($7)
36288		 jr    $7
36289		 nop                    	 # Delay slot
36290
36291	1:
36292		 seb   $24,$24
36293		 addu  $23,$23,$24
36294		 andi  $25,$23,0x01
36295		 beq   $25,$0,2f
36296		 subu  $5,$23,$22     	 # Delay slot
36297		 addiu $23,$23,-2
36298		 jal   Exception
36299		 ori   $2,$0,3
36300
36301		 addiu $15,$15,-10
36302		 bgez  $15,3f
36303		 lhu   $24,0x00($23)    	 # Delay slot
36304		 j     MainExit
36305	3:
36306		 sll   $7,$24,2         	 # Delay slot
36307		 addu  $7,$7,$30
36308		 lw    $7,0x00($7)
36309		 jr    $7
36310		 nop                    	 # Delay slot
36311
36312	2:
36313		 sw    $5,0x74($21)
36314		 lw    $6,mem_amask
36315		 lw    $25,0x94($21)
36316		 and   $23,$5,$6
36317		 sw    $15,m68k_ICount
36318		 jalr  $25
36319		 or    $4,$0,$23   	 # Delay slot
36320		 lw    $15,m68k_ICount
36321		 lw    $22,OP_ROM
36322		 addu  $23,$23,$22
36323 # End of Banking code:
36324		 addiu $15,$15,-10
36325		 bgez  $15,3f
36326		 lhu   $24,0x00($23)    	 # Delay slot
36327		 j     MainExit
36328	3:
36329		 sll   $7,$24,2         	 # Delay slot
36330		 addu  $7,$7,$30
36331		 lw    $7,0x00($7)
36332		 jr    $7
36333		 nop                    	 # Delay slot
36334
36335OP0_6400:				#:
36336		 beq   $16,$0,1f        	 # check carry
36337		 addiu $23,$23,2        	 # Delay slot
36338
36339		 addiu $23,$23,2
36340		 addiu $15,$15,-8
36341		 bgez  $15,3f
36342		 lhu   $24,0x00($23)    	 # Delay slot
36343		 j     MainExit
36344	3:
36345		 sll   $7,$24,2         	 # Delay slot
36346		 addu  $7,$7,$30
36347		 lw    $7,0x00($7)
36348		 jr    $7
36349		 nop                    	 # Delay slot
36350
36351	1:
36352		 lh    $2,0x00($23)
36353		 addu  $23,$23,$2
36354		 andi  $25,$23,0x01
36355		 beq   $25,$0,2f
36356		 subu  $5,$23,$22     	 # Delay slot
36357		 addiu $23,$23,-2
36358		 jal   Exception
36359		 ori   $2,$0,3
36360
36361		 addiu $15,$15,-10
36362		 bgez  $15,3f
36363		 lhu   $24,0x00($23)    	 # Delay slot
36364		 j     MainExit
36365	3:
36366		 sll   $7,$24,2         	 # Delay slot
36367		 addu  $7,$7,$30
36368		 lw    $7,0x00($7)
36369		 jr    $7
36370		 nop                    	 # Delay slot
36371
36372	2:
36373		 sw    $5,0x74($21)
36374		 lw    $6,mem_amask
36375		 lw    $25,0x94($21)
36376		 and   $23,$5,$6
36377		 sw    $15,m68k_ICount
36378		 jalr  $25
36379		 or    $4,$0,$23   	 # Delay slot
36380		 lw    $15,m68k_ICount
36381		 lw    $22,OP_ROM
36382		 addu  $23,$23,$22
36383 # End of Banking code:
36384		 addiu $15,$15,-10
36385		 bgez  $15,3f
36386		 lhu   $24,0x00($23)    	 # Delay slot
36387		 j     MainExit
36388	3:
36389		 sll   $7,$24,2         	 # Delay slot
36390		 addu  $7,$7,$30
36391		 lw    $7,0x00($7)
36392		 jr    $7
36393		 nop                    	 # Delay slot
36394
36395OP0_6401:				#:
36396		 beq   $16,$0,1f        	 # check carry
36397		 addiu $23,$23,2        	 # Delay slot
36398
36399		 addiu $15,$15,-8
36400		 bgez  $15,3f
36401		 lhu   $24,0x00($23)    	 # Delay slot
36402		 j     MainExit
36403	3:
36404		 sll   $7,$24,2         	 # Delay slot
36405		 addu  $7,$7,$30
36406		 lw    $7,0x00($7)
36407		 jr    $7
36408		 nop                    	 # Delay slot
36409
36410	1:
36411		 seb   $24,$24
36412		 addu  $23,$23,$24
36413		 andi  $25,$23,0x01
36414		 beq   $25,$0,2f
36415		 subu  $5,$23,$22     	 # Delay slot
36416		 addiu $23,$23,-2
36417		 jal   Exception
36418		 ori   $2,$0,3
36419
36420		 addiu $15,$15,-10
36421		 bgez  $15,3f
36422		 lhu   $24,0x00($23)    	 # Delay slot
36423		 j     MainExit
36424	3:
36425		 sll   $7,$24,2         	 # Delay slot
36426		 addu  $7,$7,$30
36427		 lw    $7,0x00($7)
36428		 jr    $7
36429		 nop                    	 # Delay slot
36430
36431	2:
36432		 sw    $5,0x74($21)
36433		 lw    $6,mem_amask
36434		 lw    $25,0x94($21)
36435		 and   $23,$5,$6
36436		 sw    $15,m68k_ICount
36437		 jalr  $25
36438		 or    $4,$0,$23   	 # Delay slot
36439		 lw    $15,m68k_ICount
36440		 lw    $22,OP_ROM
36441		 addu  $23,$23,$22
36442 # End of Banking code:
36443		 addiu $15,$15,-10
36444		 bgez  $15,3f
36445		 lhu   $24,0x00($23)    	 # Delay slot
36446		 j     MainExit
36447	3:
36448		 sll   $7,$24,2         	 # Delay slot
36449		 addu  $7,$7,$30
36450		 lw    $7,0x00($7)
36451		 jr    $7
36452		 nop                    	 # Delay slot
36453
36454OP0_6500:				#:
36455		 bne   $16,$0,1f        	 # check carry
36456		 addiu $23,$23,2        	 # Delay slot
36457
36458		 addiu $23,$23,2
36459		 addiu $15,$15,-8
36460		 bgez  $15,3f
36461		 lhu   $24,0x00($23)    	 # Delay slot
36462		 j     MainExit
36463	3:
36464		 sll   $7,$24,2         	 # Delay slot
36465		 addu  $7,$7,$30
36466		 lw    $7,0x00($7)
36467		 jr    $7
36468		 nop                    	 # Delay slot
36469
36470	1:
36471		 lh    $2,0x00($23)
36472		 addu  $23,$23,$2
36473		 andi  $25,$23,0x01
36474		 beq   $25,$0,2f
36475		 subu  $5,$23,$22     	 # Delay slot
36476		 addiu $23,$23,-2
36477		 jal   Exception
36478		 ori   $2,$0,3
36479
36480		 addiu $15,$15,-10
36481		 bgez  $15,3f
36482		 lhu   $24,0x00($23)    	 # Delay slot
36483		 j     MainExit
36484	3:
36485		 sll   $7,$24,2         	 # Delay slot
36486		 addu  $7,$7,$30
36487		 lw    $7,0x00($7)
36488		 jr    $7
36489		 nop                    	 # Delay slot
36490
36491	2:
36492		 sw    $5,0x74($21)
36493		 lw    $6,mem_amask
36494		 lw    $25,0x94($21)
36495		 and   $23,$5,$6
36496		 sw    $15,m68k_ICount
36497		 jalr  $25
36498		 or    $4,$0,$23   	 # Delay slot
36499		 lw    $15,m68k_ICount
36500		 lw    $22,OP_ROM
36501		 addu  $23,$23,$22
36502 # End of Banking code:
36503		 addiu $15,$15,-10
36504		 bgez  $15,3f
36505		 lhu   $24,0x00($23)    	 # Delay slot
36506		 j     MainExit
36507	3:
36508		 sll   $7,$24,2         	 # Delay slot
36509		 addu  $7,$7,$30
36510		 lw    $7,0x00($7)
36511		 jr    $7
36512		 nop                    	 # Delay slot
36513
36514OP0_6501:				#:
36515		 bne   $16,$0,1f        	 # check carry
36516		 addiu $23,$23,2        	 # Delay slot
36517
36518		 addiu $15,$15,-8
36519		 bgez  $15,3f
36520		 lhu   $24,0x00($23)    	 # Delay slot
36521		 j     MainExit
36522	3:
36523		 sll   $7,$24,2         	 # Delay slot
36524		 addu  $7,$7,$30
36525		 lw    $7,0x00($7)
36526		 jr    $7
36527		 nop                    	 # Delay slot
36528
36529	1:
36530		 seb   $24,$24
36531		 addu  $23,$23,$24
36532		 andi  $25,$23,0x01
36533		 beq   $25,$0,2f
36534		 subu  $5,$23,$22     	 # Delay slot
36535		 addiu $23,$23,-2
36536		 jal   Exception
36537		 ori   $2,$0,3
36538
36539		 addiu $15,$15,-10
36540		 bgez  $15,3f
36541		 lhu   $24,0x00($23)    	 # Delay slot
36542		 j     MainExit
36543	3:
36544		 sll   $7,$24,2         	 # Delay slot
36545		 addu  $7,$7,$30
36546		 lw    $7,0x00($7)
36547		 jr    $7
36548		 nop                    	 # Delay slot
36549
36550	2:
36551		 sw    $5,0x74($21)
36552		 lw    $6,mem_amask
36553		 lw    $25,0x94($21)
36554		 and   $23,$5,$6
36555		 sw    $15,m68k_ICount
36556		 jalr  $25
36557		 or    $4,$0,$23   	 # Delay slot
36558		 lw    $15,m68k_ICount
36559		 lw    $22,OP_ROM
36560		 addu  $23,$23,$22
36561 # End of Banking code:
36562		 addiu $15,$15,-10
36563		 bgez  $15,3f
36564		 lhu   $24,0x00($23)    	 # Delay slot
36565		 j     MainExit
36566	3:
36567		 sll   $7,$24,2         	 # Delay slot
36568		 addu  $7,$7,$30
36569		 lw    $7,0x00($7)
36570		 jr    $7
36571		 nop                    	 # Delay slot
36572
36573OP0_6600:				#:
36574		 beq   $18,$0,1f        	 # Check zero
36575		 addiu $23,$23,2        	 # Delay slot
36576
36577		 addiu $23,$23,2
36578		 addiu $15,$15,-8
36579		 bgez  $15,3f
36580		 lhu   $24,0x00($23)    	 # Delay slot
36581		 j     MainExit
36582	3:
36583		 sll   $7,$24,2         	 # Delay slot
36584		 addu  $7,$7,$30
36585		 lw    $7,0x00($7)
36586		 jr    $7
36587		 nop                    	 # Delay slot
36588
36589	1:
36590		 lh    $2,0x00($23)
36591		 addu  $23,$23,$2
36592		 andi  $25,$23,0x01
36593		 beq   $25,$0,2f
36594		 subu  $5,$23,$22     	 # Delay slot
36595		 addiu $23,$23,-2
36596		 jal   Exception
36597		 ori   $2,$0,3
36598
36599		 addiu $15,$15,-10
36600		 bgez  $15,3f
36601		 lhu   $24,0x00($23)    	 # Delay slot
36602		 j     MainExit
36603	3:
36604		 sll   $7,$24,2         	 # Delay slot
36605		 addu  $7,$7,$30
36606		 lw    $7,0x00($7)
36607		 jr    $7
36608		 nop                    	 # Delay slot
36609
36610	2:
36611		 sw    $5,0x74($21)
36612		 lw    $6,mem_amask
36613		 lw    $25,0x94($21)
36614		 and   $23,$5,$6
36615		 sw    $15,m68k_ICount
36616		 jalr  $25
36617		 or    $4,$0,$23   	 # Delay slot
36618		 lw    $15,m68k_ICount
36619		 lw    $22,OP_ROM
36620		 addu  $23,$23,$22
36621 # End of Banking code:
36622		 addiu $15,$15,-10
36623		 bgez  $15,3f
36624		 lhu   $24,0x00($23)    	 # Delay slot
36625		 j     MainExit
36626	3:
36627		 sll   $7,$24,2         	 # Delay slot
36628		 addu  $7,$7,$30
36629		 lw    $7,0x00($7)
36630		 jr    $7
36631		 nop                    	 # Delay slot
36632
36633OP0_6601:				#:
36634		 beq   $18,$0,1f        	 # Check zero
36635		 addiu $23,$23,2        	 # Delay slot
36636
36637		 addiu $15,$15,-8
36638		 bgez  $15,3f
36639		 lhu   $24,0x00($23)    	 # Delay slot
36640		 j     MainExit
36641	3:
36642		 sll   $7,$24,2         	 # Delay slot
36643		 addu  $7,$7,$30
36644		 lw    $7,0x00($7)
36645		 jr    $7
36646		 nop                    	 # Delay slot
36647
36648	1:
36649		 seb   $24,$24
36650		 addu  $23,$23,$24
36651		 andi  $25,$23,0x01
36652		 beq   $25,$0,2f
36653		 subu  $5,$23,$22     	 # Delay slot
36654		 addiu $23,$23,-2
36655		 jal   Exception
36656		 ori   $2,$0,3
36657
36658		 addiu $15,$15,-10
36659		 bgez  $15,3f
36660		 lhu   $24,0x00($23)    	 # Delay slot
36661		 j     MainExit
36662	3:
36663		 sll   $7,$24,2         	 # Delay slot
36664		 addu  $7,$7,$30
36665		 lw    $7,0x00($7)
36666		 jr    $7
36667		 nop                    	 # Delay slot
36668
36669	2:
36670		 sw    $5,0x74($21)
36671		 lw    $6,mem_amask
36672		 lw    $25,0x94($21)
36673		 and   $23,$5,$6
36674		 sw    $15,m68k_ICount
36675		 jalr  $25
36676		 or    $4,$0,$23   	 # Delay slot
36677		 lw    $15,m68k_ICount
36678		 lw    $22,OP_ROM
36679		 addu  $23,$23,$22
36680 # End of Banking code:
36681		 addiu $15,$15,-10
36682		 bgez  $15,3f
36683		 lhu   $24,0x00($23)    	 # Delay slot
36684		 j     MainExit
36685	3:
36686		 sll   $7,$24,2         	 # Delay slot
36687		 addu  $7,$7,$30
36688		 lw    $7,0x00($7)
36689		 jr    $7
36690		 nop                    	 # Delay slot
36691
36692OP0_6700:				#:
36693		 bne   $18,$0,1f        	 # Check zero
36694		 addiu $23,$23,2        	 # Delay slot
36695
36696		 addiu $23,$23,2
36697		 addiu $15,$15,-8
36698		 bgez  $15,3f
36699		 lhu   $24,0x00($23)    	 # Delay slot
36700		 j     MainExit
36701	3:
36702		 sll   $7,$24,2         	 # Delay slot
36703		 addu  $7,$7,$30
36704		 lw    $7,0x00($7)
36705		 jr    $7
36706		 nop                    	 # Delay slot
36707
36708	1:
36709		 lh    $2,0x00($23)
36710		 addu  $23,$23,$2
36711		 andi  $25,$23,0x01
36712		 beq   $25,$0,2f
36713		 subu  $5,$23,$22     	 # Delay slot
36714		 addiu $23,$23,-2
36715		 jal   Exception
36716		 ori   $2,$0,3
36717
36718		 addiu $15,$15,-10
36719		 bgez  $15,3f
36720		 lhu   $24,0x00($23)    	 # Delay slot
36721		 j     MainExit
36722	3:
36723		 sll   $7,$24,2         	 # Delay slot
36724		 addu  $7,$7,$30
36725		 lw    $7,0x00($7)
36726		 jr    $7
36727		 nop                    	 # Delay slot
36728
36729	2:
36730		 sw    $5,0x74($21)
36731		 lw    $6,mem_amask
36732		 lw    $25,0x94($21)
36733		 and   $23,$5,$6
36734		 sw    $15,m68k_ICount
36735		 jalr  $25
36736		 or    $4,$0,$23   	 # Delay slot
36737		 lw    $15,m68k_ICount
36738		 lw    $22,OP_ROM
36739		 addu  $23,$23,$22
36740 # End of Banking code:
36741		 addiu $15,$15,-10
36742		 bgez  $15,3f
36743		 lhu   $24,0x00($23)    	 # Delay slot
36744		 j     MainExit
36745	3:
36746		 sll   $7,$24,2         	 # Delay slot
36747		 addu  $7,$7,$30
36748		 lw    $7,0x00($7)
36749		 jr    $7
36750		 nop                    	 # Delay slot
36751
36752OP0_6701:				#:
36753		 bne   $18,$0,1f        	 # Check zero
36754		 addiu $23,$23,2        	 # Delay slot
36755
36756		 addiu $15,$15,-8
36757		 bgez  $15,3f
36758		 lhu   $24,0x00($23)    	 # Delay slot
36759		 j     MainExit
36760	3:
36761		 sll   $7,$24,2         	 # Delay slot
36762		 addu  $7,$7,$30
36763		 lw    $7,0x00($7)
36764		 jr    $7
36765		 nop                    	 # Delay slot
36766
36767	1:
36768		 seb   $24,$24
36769		 addu  $23,$23,$24
36770		 andi  $25,$23,0x01
36771		 beq   $25,$0,2f
36772		 subu  $5,$23,$22     	 # Delay slot
36773		 addiu $23,$23,-2
36774		 jal   Exception
36775		 ori   $2,$0,3
36776
36777		 addiu $15,$15,-10
36778		 bgez  $15,3f
36779		 lhu   $24,0x00($23)    	 # Delay slot
36780		 j     MainExit
36781	3:
36782		 sll   $7,$24,2         	 # Delay slot
36783		 addu  $7,$7,$30
36784		 lw    $7,0x00($7)
36785		 jr    $7
36786		 nop                    	 # Delay slot
36787
36788	2:
36789		 sw    $5,0x74($21)
36790		 lw    $6,mem_amask
36791		 lw    $25,0x94($21)
36792		 and   $23,$5,$6
36793		 sw    $15,m68k_ICount
36794		 jalr  $25
36795		 or    $4,$0,$23   	 # Delay slot
36796		 lw    $15,m68k_ICount
36797		 lw    $22,OP_ROM
36798		 addu  $23,$23,$22
36799 # End of Banking code:
36800		 addiu $15,$15,-10
36801		 bgez  $15,3f
36802		 lhu   $24,0x00($23)    	 # Delay slot
36803		 j     MainExit
36804	3:
36805		 sll   $7,$24,2         	 # Delay slot
36806		 addu  $7,$7,$30
36807		 lw    $7,0x00($7)
36808		 jr    $7
36809		 nop                    	 # Delay slot
36810
36811OP0_6800:				#:
36812		 beq   $17,$0,1f        	 # Check Overflow
36813		 addiu $23,$23,2        	 # Delay slot
36814
36815		 addiu $23,$23,2
36816		 addiu $15,$15,-8
36817		 bgez  $15,3f
36818		 lhu   $24,0x00($23)    	 # Delay slot
36819		 j     MainExit
36820	3:
36821		 sll   $7,$24,2         	 # Delay slot
36822		 addu  $7,$7,$30
36823		 lw    $7,0x00($7)
36824		 jr    $7
36825		 nop                    	 # Delay slot
36826
36827	1:
36828		 lh    $2,0x00($23)
36829		 addu  $23,$23,$2
36830		 andi  $25,$23,0x01
36831		 beq   $25,$0,2f
36832		 subu  $5,$23,$22     	 # Delay slot
36833		 addiu $23,$23,-2
36834		 jal   Exception
36835		 ori   $2,$0,3
36836
36837		 addiu $15,$15,-10
36838		 bgez  $15,3f
36839		 lhu   $24,0x00($23)    	 # Delay slot
36840		 j     MainExit
36841	3:
36842		 sll   $7,$24,2         	 # Delay slot
36843		 addu  $7,$7,$30
36844		 lw    $7,0x00($7)
36845		 jr    $7
36846		 nop                    	 # Delay slot
36847
36848	2:
36849		 sw    $5,0x74($21)
36850		 lw    $6,mem_amask
36851		 lw    $25,0x94($21)
36852		 and   $23,$5,$6
36853		 sw    $15,m68k_ICount
36854		 jalr  $25
36855		 or    $4,$0,$23   	 # Delay slot
36856		 lw    $15,m68k_ICount
36857		 lw    $22,OP_ROM
36858		 addu  $23,$23,$22
36859 # End of Banking code:
36860		 addiu $15,$15,-10
36861		 bgez  $15,3f
36862		 lhu   $24,0x00($23)    	 # Delay slot
36863		 j     MainExit
36864	3:
36865		 sll   $7,$24,2         	 # Delay slot
36866		 addu  $7,$7,$30
36867		 lw    $7,0x00($7)
36868		 jr    $7
36869		 nop                    	 # Delay slot
36870
36871OP0_6801:				#:
36872		 beq   $17,$0,1f        	 # Check Overflow
36873		 addiu $23,$23,2        	 # Delay slot
36874
36875		 addiu $15,$15,-8
36876		 bgez  $15,3f
36877		 lhu   $24,0x00($23)    	 # Delay slot
36878		 j     MainExit
36879	3:
36880		 sll   $7,$24,2         	 # Delay slot
36881		 addu  $7,$7,$30
36882		 lw    $7,0x00($7)
36883		 jr    $7
36884		 nop                    	 # Delay slot
36885
36886	1:
36887		 seb   $24,$24
36888		 addu  $23,$23,$24
36889		 andi  $25,$23,0x01
36890		 beq   $25,$0,2f
36891		 subu  $5,$23,$22     	 # Delay slot
36892		 addiu $23,$23,-2
36893		 jal   Exception
36894		 ori   $2,$0,3
36895
36896		 addiu $15,$15,-10
36897		 bgez  $15,3f
36898		 lhu   $24,0x00($23)    	 # Delay slot
36899		 j     MainExit
36900	3:
36901		 sll   $7,$24,2         	 # Delay slot
36902		 addu  $7,$7,$30
36903		 lw    $7,0x00($7)
36904		 jr    $7
36905		 nop                    	 # Delay slot
36906
36907	2:
36908		 sw    $5,0x74($21)
36909		 lw    $6,mem_amask
36910		 lw    $25,0x94($21)
36911		 and   $23,$5,$6
36912		 sw    $15,m68k_ICount
36913		 jalr  $25
36914		 or    $4,$0,$23   	 # Delay slot
36915		 lw    $15,m68k_ICount
36916		 lw    $22,OP_ROM
36917		 addu  $23,$23,$22
36918 # End of Banking code:
36919		 addiu $15,$15,-10
36920		 bgez  $15,3f
36921		 lhu   $24,0x00($23)    	 # Delay slot
36922		 j     MainExit
36923	3:
36924		 sll   $7,$24,2         	 # Delay slot
36925		 addu  $7,$7,$30
36926		 lw    $7,0x00($7)
36927		 jr    $7
36928		 nop                    	 # Delay slot
36929
36930OP0_6900:				#:
36931		 bne   $17,$0,1f        	 # Check Overflow
36932		 addiu $23,$23,2        	 # Delay slot
36933
36934		 addiu $23,$23,2
36935		 addiu $15,$15,-8
36936		 bgez  $15,3f
36937		 lhu   $24,0x00($23)    	 # Delay slot
36938		 j     MainExit
36939	3:
36940		 sll   $7,$24,2         	 # Delay slot
36941		 addu  $7,$7,$30
36942		 lw    $7,0x00($7)
36943		 jr    $7
36944		 nop                    	 # Delay slot
36945
36946	1:
36947		 lh    $2,0x00($23)
36948		 addu  $23,$23,$2
36949		 andi  $25,$23,0x01
36950		 beq   $25,$0,2f
36951		 subu  $5,$23,$22     	 # Delay slot
36952		 addiu $23,$23,-2
36953		 jal   Exception
36954		 ori   $2,$0,3
36955
36956		 addiu $15,$15,-10
36957		 bgez  $15,3f
36958		 lhu   $24,0x00($23)    	 # Delay slot
36959		 j     MainExit
36960	3:
36961		 sll   $7,$24,2         	 # Delay slot
36962		 addu  $7,$7,$30
36963		 lw    $7,0x00($7)
36964		 jr    $7
36965		 nop                    	 # Delay slot
36966
36967	2:
36968		 sw    $5,0x74($21)
36969		 lw    $6,mem_amask
36970		 lw    $25,0x94($21)
36971		 and   $23,$5,$6
36972		 sw    $15,m68k_ICount
36973		 jalr  $25
36974		 or    $4,$0,$23   	 # Delay slot
36975		 lw    $15,m68k_ICount
36976		 lw    $22,OP_ROM
36977		 addu  $23,$23,$22
36978 # End of Banking code:
36979		 addiu $15,$15,-10
36980		 bgez  $15,3f
36981		 lhu   $24,0x00($23)    	 # Delay slot
36982		 j     MainExit
36983	3:
36984		 sll   $7,$24,2         	 # Delay slot
36985		 addu  $7,$7,$30
36986		 lw    $7,0x00($7)
36987		 jr    $7
36988		 nop                    	 # Delay slot
36989
36990OP0_6901:				#:
36991		 bne   $17,$0,1f        	 # Check Overflow
36992		 addiu $23,$23,2        	 # Delay slot
36993
36994		 addiu $15,$15,-8
36995		 bgez  $15,3f
36996		 lhu   $24,0x00($23)    	 # Delay slot
36997		 j     MainExit
36998	3:
36999		 sll   $7,$24,2         	 # Delay slot
37000		 addu  $7,$7,$30
37001		 lw    $7,0x00($7)
37002		 jr    $7
37003		 nop                    	 # Delay slot
37004
37005	1:
37006		 seb   $24,$24
37007		 addu  $23,$23,$24
37008		 andi  $25,$23,0x01
37009		 beq   $25,$0,2f
37010		 subu  $5,$23,$22     	 # Delay slot
37011		 addiu $23,$23,-2
37012		 jal   Exception
37013		 ori   $2,$0,3
37014
37015		 addiu $15,$15,-10
37016		 bgez  $15,3f
37017		 lhu   $24,0x00($23)    	 # Delay slot
37018		 j     MainExit
37019	3:
37020		 sll   $7,$24,2         	 # Delay slot
37021		 addu  $7,$7,$30
37022		 lw    $7,0x00($7)
37023		 jr    $7
37024		 nop                    	 # Delay slot
37025
37026	2:
37027		 sw    $5,0x74($21)
37028		 lw    $6,mem_amask
37029		 lw    $25,0x94($21)
37030		 and   $23,$5,$6
37031		 sw    $15,m68k_ICount
37032		 jalr  $25
37033		 or    $4,$0,$23   	 # Delay slot
37034		 lw    $15,m68k_ICount
37035		 lw    $22,OP_ROM
37036		 addu  $23,$23,$22
37037 # End of Banking code:
37038		 addiu $15,$15,-10
37039		 bgez  $15,3f
37040		 lhu   $24,0x00($23)    	 # Delay slot
37041		 j     MainExit
37042	3:
37043		 sll   $7,$24,2         	 # Delay slot
37044		 addu  $7,$7,$30
37045		 lw    $7,0x00($7)
37046		 jr    $7
37047		 nop                    	 # Delay slot
37048
37049OP0_6a00:				#:
37050		 beq   $19,$0,1f        	 # Check Sign
37051		 addiu $23,$23,2        	 # Delay slot
37052
37053		 addiu $23,$23,2
37054		 addiu $15,$15,-8
37055		 bgez  $15,3f
37056		 lhu   $24,0x00($23)    	 # Delay slot
37057		 j     MainExit
37058	3:
37059		 sll   $7,$24,2         	 # Delay slot
37060		 addu  $7,$7,$30
37061		 lw    $7,0x00($7)
37062		 jr    $7
37063		 nop                    	 # Delay slot
37064
37065	1:
37066		 lh    $2,0x00($23)
37067		 addu  $23,$23,$2
37068		 andi  $25,$23,0x01
37069		 beq   $25,$0,2f
37070		 subu  $5,$23,$22     	 # Delay slot
37071		 addiu $23,$23,-2
37072		 jal   Exception
37073		 ori   $2,$0,3
37074
37075		 addiu $15,$15,-10
37076		 bgez  $15,3f
37077		 lhu   $24,0x00($23)    	 # Delay slot
37078		 j     MainExit
37079	3:
37080		 sll   $7,$24,2         	 # Delay slot
37081		 addu  $7,$7,$30
37082		 lw    $7,0x00($7)
37083		 jr    $7
37084		 nop                    	 # Delay slot
37085
37086	2:
37087		 sw    $5,0x74($21)
37088		 lw    $6,mem_amask
37089		 lw    $25,0x94($21)
37090		 and   $23,$5,$6
37091		 sw    $15,m68k_ICount
37092		 jalr  $25
37093		 or    $4,$0,$23   	 # Delay slot
37094		 lw    $15,m68k_ICount
37095		 lw    $22,OP_ROM
37096		 addu  $23,$23,$22
37097 # End of Banking code:
37098		 addiu $15,$15,-10
37099		 bgez  $15,3f
37100		 lhu   $24,0x00($23)    	 # Delay slot
37101		 j     MainExit
37102	3:
37103		 sll   $7,$24,2         	 # Delay slot
37104		 addu  $7,$7,$30
37105		 lw    $7,0x00($7)
37106		 jr    $7
37107		 nop                    	 # Delay slot
37108
37109OP0_6a01:				#:
37110		 beq   $19,$0,1f        	 # Check Sign
37111		 addiu $23,$23,2        	 # Delay slot
37112
37113		 addiu $15,$15,-8
37114		 bgez  $15,3f
37115		 lhu   $24,0x00($23)    	 # Delay slot
37116		 j     MainExit
37117	3:
37118		 sll   $7,$24,2         	 # Delay slot
37119		 addu  $7,$7,$30
37120		 lw    $7,0x00($7)
37121		 jr    $7
37122		 nop                    	 # Delay slot
37123
37124	1:
37125		 seb   $24,$24
37126		 addu  $23,$23,$24
37127		 andi  $25,$23,0x01
37128		 beq   $25,$0,2f
37129		 subu  $5,$23,$22     	 # Delay slot
37130		 addiu $23,$23,-2
37131		 jal   Exception
37132		 ori   $2,$0,3
37133
37134		 addiu $15,$15,-10
37135		 bgez  $15,3f
37136		 lhu   $24,0x00($23)    	 # Delay slot
37137		 j     MainExit
37138	3:
37139		 sll   $7,$24,2         	 # Delay slot
37140		 addu  $7,$7,$30
37141		 lw    $7,0x00($7)
37142		 jr    $7
37143		 nop                    	 # Delay slot
37144
37145	2:
37146		 sw    $5,0x74($21)
37147		 lw    $6,mem_amask
37148		 lw    $25,0x94($21)
37149		 and   $23,$5,$6
37150		 sw    $15,m68k_ICount
37151		 jalr  $25
37152		 or    $4,$0,$23   	 # Delay slot
37153		 lw    $15,m68k_ICount
37154		 lw    $22,OP_ROM
37155		 addu  $23,$23,$22
37156 # End of Banking code:
37157		 addiu $15,$15,-10
37158		 bgez  $15,3f
37159		 lhu   $24,0x00($23)    	 # Delay slot
37160		 j     MainExit
37161	3:
37162		 sll   $7,$24,2         	 # Delay slot
37163		 addu  $7,$7,$30
37164		 lw    $7,0x00($7)
37165		 jr    $7
37166		 nop                    	 # Delay slot
37167
37168OP0_6b00:				#:
37169		 bne   $19,$0,1f        	 # Check Sign
37170		 addiu $23,$23,2        	 # Delay slot
37171
37172		 addiu $23,$23,2
37173		 addiu $15,$15,-8
37174		 bgez  $15,3f
37175		 lhu   $24,0x00($23)    	 # Delay slot
37176		 j     MainExit
37177	3:
37178		 sll   $7,$24,2         	 # Delay slot
37179		 addu  $7,$7,$30
37180		 lw    $7,0x00($7)
37181		 jr    $7
37182		 nop                    	 # Delay slot
37183
37184	1:
37185		 lh    $2,0x00($23)
37186		 addu  $23,$23,$2
37187		 andi  $25,$23,0x01
37188		 beq   $25,$0,2f
37189		 subu  $5,$23,$22     	 # Delay slot
37190		 addiu $23,$23,-2
37191		 jal   Exception
37192		 ori   $2,$0,3
37193
37194		 addiu $15,$15,-10
37195		 bgez  $15,3f
37196		 lhu   $24,0x00($23)    	 # Delay slot
37197		 j     MainExit
37198	3:
37199		 sll   $7,$24,2         	 # Delay slot
37200		 addu  $7,$7,$30
37201		 lw    $7,0x00($7)
37202		 jr    $7
37203		 nop                    	 # Delay slot
37204
37205	2:
37206		 sw    $5,0x74($21)
37207		 lw    $6,mem_amask
37208		 lw    $25,0x94($21)
37209		 and   $23,$5,$6
37210		 sw    $15,m68k_ICount
37211		 jalr  $25
37212		 or    $4,$0,$23   	 # Delay slot
37213		 lw    $15,m68k_ICount
37214		 lw    $22,OP_ROM
37215		 addu  $23,$23,$22
37216 # End of Banking code:
37217		 addiu $15,$15,-10
37218		 bgez  $15,3f
37219		 lhu   $24,0x00($23)    	 # Delay slot
37220		 j     MainExit
37221	3:
37222		 sll   $7,$24,2         	 # Delay slot
37223		 addu  $7,$7,$30
37224		 lw    $7,0x00($7)
37225		 jr    $7
37226		 nop                    	 # Delay slot
37227
37228OP0_6b01:				#:
37229		 bne   $19,$0,1f        	 # Check Sign
37230		 addiu $23,$23,2        	 # Delay slot
37231
37232		 addiu $15,$15,-8
37233		 bgez  $15,3f
37234		 lhu   $24,0x00($23)    	 # Delay slot
37235		 j     MainExit
37236	3:
37237		 sll   $7,$24,2         	 # Delay slot
37238		 addu  $7,$7,$30
37239		 lw    $7,0x00($7)
37240		 jr    $7
37241		 nop                    	 # Delay slot
37242
37243	1:
37244		 seb   $24,$24
37245		 addu  $23,$23,$24
37246		 andi  $25,$23,0x01
37247		 beq   $25,$0,2f
37248		 subu  $5,$23,$22     	 # Delay slot
37249		 addiu $23,$23,-2
37250		 jal   Exception
37251		 ori   $2,$0,3
37252
37253		 addiu $15,$15,-10
37254		 bgez  $15,3f
37255		 lhu   $24,0x00($23)    	 # Delay slot
37256		 j     MainExit
37257	3:
37258		 sll   $7,$24,2         	 # Delay slot
37259		 addu  $7,$7,$30
37260		 lw    $7,0x00($7)
37261		 jr    $7
37262		 nop                    	 # Delay slot
37263
37264	2:
37265		 sw    $5,0x74($21)
37266		 lw    $6,mem_amask
37267		 lw    $25,0x94($21)
37268		 and   $23,$5,$6
37269		 sw    $15,m68k_ICount
37270		 jalr  $25
37271		 or    $4,$0,$23   	 # Delay slot
37272		 lw    $15,m68k_ICount
37273		 lw    $22,OP_ROM
37274		 addu  $23,$23,$22
37275 # End of Banking code:
37276		 addiu $15,$15,-10
37277		 bgez  $15,3f
37278		 lhu   $24,0x00($23)    	 # Delay slot
37279		 j     MainExit
37280	3:
37281		 sll   $7,$24,2         	 # Delay slot
37282		 addu  $7,$7,$30
37283		 lw    $7,0x00($7)
37284		 jr    $7
37285		 nop                    	 # Delay slot
37286
37287OP0_6c00:				#:
37288		 beq   $19,$17,1f
37289		 addiu $23,$23,2        	 # Delay slot
37290
37291		 addiu $23,$23,2
37292		 addiu $15,$15,-8
37293		 bgez  $15,3f
37294		 lhu   $24,0x00($23)    	 # Delay slot
37295		 j     MainExit
37296	3:
37297		 sll   $7,$24,2         	 # Delay slot
37298		 addu  $7,$7,$30
37299		 lw    $7,0x00($7)
37300		 jr    $7
37301		 nop                    	 # Delay slot
37302
37303	1:
37304		 lh    $2,0x00($23)
37305		 addu  $23,$23,$2
37306		 andi  $25,$23,0x01
37307		 beq   $25,$0,2f
37308		 subu  $5,$23,$22     	 # Delay slot
37309		 addiu $23,$23,-2
37310		 jal   Exception
37311		 ori   $2,$0,3
37312
37313		 addiu $15,$15,-10
37314		 bgez  $15,3f
37315		 lhu   $24,0x00($23)    	 # Delay slot
37316		 j     MainExit
37317	3:
37318		 sll   $7,$24,2         	 # Delay slot
37319		 addu  $7,$7,$30
37320		 lw    $7,0x00($7)
37321		 jr    $7
37322		 nop                    	 # Delay slot
37323
37324	2:
37325		 sw    $5,0x74($21)
37326		 lw    $6,mem_amask
37327		 lw    $25,0x94($21)
37328		 and   $23,$5,$6
37329		 sw    $15,m68k_ICount
37330		 jalr  $25
37331		 or    $4,$0,$23   	 # Delay slot
37332		 lw    $15,m68k_ICount
37333		 lw    $22,OP_ROM
37334		 addu  $23,$23,$22
37335 # End of Banking code:
37336		 addiu $15,$15,-10
37337		 bgez  $15,3f
37338		 lhu   $24,0x00($23)    	 # Delay slot
37339		 j     MainExit
37340	3:
37341		 sll   $7,$24,2         	 # Delay slot
37342		 addu  $7,$7,$30
37343		 lw    $7,0x00($7)
37344		 jr    $7
37345		 nop                    	 # Delay slot
37346
37347OP0_6c01:				#:
37348		 beq   $19,$17,1f
37349		 addiu $23,$23,2        	 # Delay slot
37350
37351		 addiu $15,$15,-8
37352		 bgez  $15,3f
37353		 lhu   $24,0x00($23)    	 # Delay slot
37354		 j     MainExit
37355	3:
37356		 sll   $7,$24,2         	 # Delay slot
37357		 addu  $7,$7,$30
37358		 lw    $7,0x00($7)
37359		 jr    $7
37360		 nop                    	 # Delay slot
37361
37362	1:
37363		 seb   $24,$24
37364		 addu  $23,$23,$24
37365		 andi  $25,$23,0x01
37366		 beq   $25,$0,2f
37367		 subu  $5,$23,$22     	 # Delay slot
37368		 addiu $23,$23,-2
37369		 jal   Exception
37370		 ori   $2,$0,3
37371
37372		 addiu $15,$15,-10
37373		 bgez  $15,3f
37374		 lhu   $24,0x00($23)    	 # Delay slot
37375		 j     MainExit
37376	3:
37377		 sll   $7,$24,2         	 # Delay slot
37378		 addu  $7,$7,$30
37379		 lw    $7,0x00($7)
37380		 jr    $7
37381		 nop                    	 # Delay slot
37382
37383	2:
37384		 sw    $5,0x74($21)
37385		 lw    $6,mem_amask
37386		 lw    $25,0x94($21)
37387		 and   $23,$5,$6
37388		 sw    $15,m68k_ICount
37389		 jalr  $25
37390		 or    $4,$0,$23   	 # Delay slot
37391		 lw    $15,m68k_ICount
37392		 lw    $22,OP_ROM
37393		 addu  $23,$23,$22
37394 # End of Banking code:
37395		 addiu $15,$15,-10
37396		 bgez  $15,3f
37397		 lhu   $24,0x00($23)    	 # Delay slot
37398		 j     MainExit
37399	3:
37400		 sll   $7,$24,2         	 # Delay slot
37401		 addu  $7,$7,$30
37402		 lw    $7,0x00($7)
37403		 jr    $7
37404		 nop                    	 # Delay slot
37405
37406OP0_6d00:				#:
37407		 bne   $19,$17,1f
37408		 addiu $23,$23,2        	 # Delay slot
37409
37410		 addiu $23,$23,2
37411		 addiu $15,$15,-8
37412		 bgez  $15,3f
37413		 lhu   $24,0x00($23)    	 # Delay slot
37414		 j     MainExit
37415	3:
37416		 sll   $7,$24,2         	 # Delay slot
37417		 addu  $7,$7,$30
37418		 lw    $7,0x00($7)
37419		 jr    $7
37420		 nop                    	 # Delay slot
37421
37422	1:
37423		 lh    $2,0x00($23)
37424		 addu  $23,$23,$2
37425		 andi  $25,$23,0x01
37426		 beq   $25,$0,2f
37427		 subu  $5,$23,$22     	 # Delay slot
37428		 addiu $23,$23,-2
37429		 jal   Exception
37430		 ori   $2,$0,3
37431
37432		 addiu $15,$15,-10
37433		 bgez  $15,3f
37434		 lhu   $24,0x00($23)    	 # Delay slot
37435		 j     MainExit
37436	3:
37437		 sll   $7,$24,2         	 # Delay slot
37438		 addu  $7,$7,$30
37439		 lw    $7,0x00($7)
37440		 jr    $7
37441		 nop                    	 # Delay slot
37442
37443	2:
37444		 sw    $5,0x74($21)
37445		 lw    $6,mem_amask
37446		 lw    $25,0x94($21)
37447		 and   $23,$5,$6
37448		 sw    $15,m68k_ICount
37449		 jalr  $25
37450		 or    $4,$0,$23   	 # Delay slot
37451		 lw    $15,m68k_ICount
37452		 lw    $22,OP_ROM
37453		 addu  $23,$23,$22
37454 # End of Banking code:
37455		 addiu $15,$15,-10
37456		 bgez  $15,3f
37457		 lhu   $24,0x00($23)    	 # Delay slot
37458		 j     MainExit
37459	3:
37460		 sll   $7,$24,2         	 # Delay slot
37461		 addu  $7,$7,$30
37462		 lw    $7,0x00($7)
37463		 jr    $7
37464		 nop                    	 # Delay slot
37465
37466OP0_6d01:				#:
37467		 bne   $19,$17,1f
37468		 addiu $23,$23,2        	 # Delay slot
37469
37470		 addiu $15,$15,-8
37471		 bgez  $15,3f
37472		 lhu   $24,0x00($23)    	 # Delay slot
37473		 j     MainExit
37474	3:
37475		 sll   $7,$24,2         	 # Delay slot
37476		 addu  $7,$7,$30
37477		 lw    $7,0x00($7)
37478		 jr    $7
37479		 nop                    	 # Delay slot
37480
37481	1:
37482		 seb   $24,$24
37483		 addu  $23,$23,$24
37484		 andi  $25,$23,0x01
37485		 beq   $25,$0,2f
37486		 subu  $5,$23,$22     	 # Delay slot
37487		 addiu $23,$23,-2
37488		 jal   Exception
37489		 ori   $2,$0,3
37490
37491		 addiu $15,$15,-10
37492		 bgez  $15,3f
37493		 lhu   $24,0x00($23)    	 # Delay slot
37494		 j     MainExit
37495	3:
37496		 sll   $7,$24,2         	 # Delay slot
37497		 addu  $7,$7,$30
37498		 lw    $7,0x00($7)
37499		 jr    $7
37500		 nop                    	 # Delay slot
37501
37502	2:
37503		 sw    $5,0x74($21)
37504		 lw    $6,mem_amask
37505		 lw    $25,0x94($21)
37506		 and   $23,$5,$6
37507		 sw    $15,m68k_ICount
37508		 jalr  $25
37509		 or    $4,$0,$23   	 # Delay slot
37510		 lw    $15,m68k_ICount
37511		 lw    $22,OP_ROM
37512		 addu  $23,$23,$22
37513 # End of Banking code:
37514		 addiu $15,$15,-10
37515		 bgez  $15,3f
37516		 lhu   $24,0x00($23)    	 # Delay slot
37517		 j     MainExit
37518	3:
37519		 sll   $7,$24,2         	 # Delay slot
37520		 addu  $7,$7,$30
37521		 lw    $7,0x00($7)
37522		 jr    $7
37523		 nop                    	 # Delay slot
37524
37525OP0_6e00:				#:
37526		 xor    $25,$19,$17
37527		 or     $25,$25,$18
37528		 beq   $25,$0,1f
37529		 addiu $23,$23,2        	 # Delay slot
37530
37531		 addiu $23,$23,2
37532		 addiu $15,$15,-8
37533		 bgez  $15,3f
37534		 lhu   $24,0x00($23)    	 # Delay slot
37535		 j     MainExit
37536	3:
37537		 sll   $7,$24,2         	 # Delay slot
37538		 addu  $7,$7,$30
37539		 lw    $7,0x00($7)
37540		 jr    $7
37541		 nop                    	 # Delay slot
37542
37543	1:
37544		 lh    $2,0x00($23)
37545		 addu  $23,$23,$2
37546		 andi  $25,$23,0x01
37547		 beq   $25,$0,2f
37548		 subu  $5,$23,$22     	 # Delay slot
37549		 addiu $23,$23,-2
37550		 jal   Exception
37551		 ori   $2,$0,3
37552
37553		 addiu $15,$15,-10
37554		 bgez  $15,3f
37555		 lhu   $24,0x00($23)    	 # Delay slot
37556		 j     MainExit
37557	3:
37558		 sll   $7,$24,2         	 # Delay slot
37559		 addu  $7,$7,$30
37560		 lw    $7,0x00($7)
37561		 jr    $7
37562		 nop                    	 # Delay slot
37563
37564	2:
37565		 sw    $5,0x74($21)
37566		 lw    $6,mem_amask
37567		 lw    $25,0x94($21)
37568		 and   $23,$5,$6
37569		 sw    $15,m68k_ICount
37570		 jalr  $25
37571		 or    $4,$0,$23   	 # Delay slot
37572		 lw    $15,m68k_ICount
37573		 lw    $22,OP_ROM
37574		 addu  $23,$23,$22
37575 # End of Banking code:
37576		 addiu $15,$15,-10
37577		 bgez  $15,3f
37578		 lhu   $24,0x00($23)    	 # Delay slot
37579		 j     MainExit
37580	3:
37581		 sll   $7,$24,2         	 # Delay slot
37582		 addu  $7,$7,$30
37583		 lw    $7,0x00($7)
37584		 jr    $7
37585		 nop                    	 # Delay slot
37586
37587OP0_6e01:				#:
37588		 xor    $25,$19,$17
37589		 or     $25,$25,$18
37590		 beq   $25,$0,1f
37591		 addiu $23,$23,2        	 # Delay slot
37592
37593		 addiu $15,$15,-8
37594		 bgez  $15,3f
37595		 lhu   $24,0x00($23)    	 # Delay slot
37596		 j     MainExit
37597	3:
37598		 sll   $7,$24,2         	 # Delay slot
37599		 addu  $7,$7,$30
37600		 lw    $7,0x00($7)
37601		 jr    $7
37602		 nop                    	 # Delay slot
37603
37604	1:
37605		 seb   $24,$24
37606		 addu  $23,$23,$24
37607		 andi  $25,$23,0x01
37608		 beq   $25,$0,2f
37609		 subu  $5,$23,$22     	 # Delay slot
37610		 addiu $23,$23,-2
37611		 jal   Exception
37612		 ori   $2,$0,3
37613
37614		 addiu $15,$15,-10
37615		 bgez  $15,3f
37616		 lhu   $24,0x00($23)    	 # Delay slot
37617		 j     MainExit
37618	3:
37619		 sll   $7,$24,2         	 # Delay slot
37620		 addu  $7,$7,$30
37621		 lw    $7,0x00($7)
37622		 jr    $7
37623		 nop                    	 # Delay slot
37624
37625	2:
37626		 sw    $5,0x74($21)
37627		 lw    $6,mem_amask
37628		 lw    $25,0x94($21)
37629		 and   $23,$5,$6
37630		 sw    $15,m68k_ICount
37631		 jalr  $25
37632		 or    $4,$0,$23   	 # Delay slot
37633		 lw    $15,m68k_ICount
37634		 lw    $22,OP_ROM
37635		 addu  $23,$23,$22
37636 # End of Banking code:
37637		 addiu $15,$15,-10
37638		 bgez  $15,3f
37639		 lhu   $24,0x00($23)    	 # Delay slot
37640		 j     MainExit
37641	3:
37642		 sll   $7,$24,2         	 # Delay slot
37643		 addu  $7,$7,$30
37644		 lw    $7,0x00($7)
37645		 jr    $7
37646		 nop                    	 # Delay slot
37647
37648OP0_6f00:				#:
37649		 xor    $25,$19,$17
37650		 or     $25,$25,$18
37651		 bne   $25,$0,1f
37652		 addiu $23,$23,2        	 # Delay slot
37653
37654		 addiu $23,$23,2
37655		 addiu $15,$15,-8
37656		 bgez  $15,3f
37657		 lhu   $24,0x00($23)    	 # Delay slot
37658		 j     MainExit
37659	3:
37660		 sll   $7,$24,2         	 # Delay slot
37661		 addu  $7,$7,$30
37662		 lw    $7,0x00($7)
37663		 jr    $7
37664		 nop                    	 # Delay slot
37665
37666	1:
37667		 lh    $2,0x00($23)
37668		 addu  $23,$23,$2
37669		 andi  $25,$23,0x01
37670		 beq   $25,$0,2f
37671		 subu  $5,$23,$22     	 # Delay slot
37672		 addiu $23,$23,-2
37673		 jal   Exception
37674		 ori   $2,$0,3
37675
37676		 addiu $15,$15,-10
37677		 bgez  $15,3f
37678		 lhu   $24,0x00($23)    	 # Delay slot
37679		 j     MainExit
37680	3:
37681		 sll   $7,$24,2         	 # Delay slot
37682		 addu  $7,$7,$30
37683		 lw    $7,0x00($7)
37684		 jr    $7
37685		 nop                    	 # Delay slot
37686
37687	2:
37688		 sw    $5,0x74($21)
37689		 lw    $6,mem_amask
37690		 lw    $25,0x94($21)
37691		 and   $23,$5,$6
37692		 sw    $15,m68k_ICount
37693		 jalr  $25
37694		 or    $4,$0,$23   	 # Delay slot
37695		 lw    $15,m68k_ICount
37696		 lw    $22,OP_ROM
37697		 addu  $23,$23,$22
37698 # End of Banking code:
37699		 addiu $15,$15,-10
37700		 bgez  $15,3f
37701		 lhu   $24,0x00($23)    	 # Delay slot
37702		 j     MainExit
37703	3:
37704		 sll   $7,$24,2         	 # Delay slot
37705		 addu  $7,$7,$30
37706		 lw    $7,0x00($7)
37707		 jr    $7
37708		 nop                    	 # Delay slot
37709
37710OP0_6f01:				#:
37711		 xor    $25,$19,$17
37712		 or     $25,$25,$18
37713		 bne   $25,$0,1f
37714		 addiu $23,$23,2        	 # Delay slot
37715
37716		 addiu $15,$15,-8
37717		 bgez  $15,3f
37718		 lhu   $24,0x00($23)    	 # Delay slot
37719		 j     MainExit
37720	3:
37721		 sll   $7,$24,2         	 # Delay slot
37722		 addu  $7,$7,$30
37723		 lw    $7,0x00($7)
37724		 jr    $7
37725		 nop                    	 # Delay slot
37726
37727	1:
37728		 seb   $24,$24
37729		 addu  $23,$23,$24
37730		 andi  $25,$23,0x01
37731		 beq   $25,$0,2f
37732		 subu  $5,$23,$22     	 # Delay slot
37733		 addiu $23,$23,-2
37734		 jal   Exception
37735		 ori   $2,$0,3
37736
37737		 addiu $15,$15,-10
37738		 bgez  $15,3f
37739		 lhu   $24,0x00($23)    	 # Delay slot
37740		 j     MainExit
37741	3:
37742		 sll   $7,$24,2         	 # Delay slot
37743		 addu  $7,$7,$30
37744		 lw    $7,0x00($7)
37745		 jr    $7
37746		 nop                    	 # Delay slot
37747
37748	2:
37749		 sw    $5,0x74($21)
37750		 lw    $6,mem_amask
37751		 lw    $25,0x94($21)
37752		 and   $23,$5,$6
37753		 sw    $15,m68k_ICount
37754		 jalr  $25
37755		 or    $4,$0,$23   	 # Delay slot
37756		 lw    $15,m68k_ICount
37757		 lw    $22,OP_ROM
37758		 addu  $23,$23,$22
37759 # End of Banking code:
37760		 addiu $15,$15,-10
37761		 bgez  $15,3f
37762		 lhu   $24,0x00($23)    	 # Delay slot
37763		 j     MainExit
37764	3:
37765		 sll   $7,$24,2         	 # Delay slot
37766		 addu  $7,$7,$30
37767		 lw    $7,0x00($7)
37768		 jr    $7
37769		 nop                    	 # Delay slot
37770
37771OP0_7000:				#:
37772
37773		 addiu $23,$23,2
37774
37775		 seb   $2,$24
37776		 srl   $24,$24,7
37777		 andi  $24,$24,0x1C
37778		 and   $16,$0,$0        	 # Clear Carry
37779		 and   $17,$0,$0        	 # Clear Overflow
37780		 srl   $19,$2,31         	 # Set Sign
37781		 sltiu $18,$2,1         	 # Set Zero
37782		 addu  $24,$24,$21
37783		 sw    $2,0x00($24)
37784		 addiu $15,$15,-4
37785		 bgez  $15,3f
37786		 lhu   $24,0x00($23)    	 # Delay slot
37787		 j     MainExit
37788	3:
37789		 sll   $7,$24,2         	 # Delay slot
37790		 addu  $7,$7,$30
37791		 lw    $7,0x00($7)
37792		 jr    $7
37793		 nop                    	 # Delay slot
37794
37795OP0_8100:				#:
37796		 addiu $23,$23,2
37797
37798		 andi  $8,$24,0x07
37799		 srl   $24,$24,7
37800		 andi  $24,$24,0x1C
37801		 sll   $8,$8,2
37802		 addu  $8,$8,$21
37803		 lbu   $8,0x00($8)
37804		 addu  $24,$24,$21
37805		 lbu   $9,0x00($24)
37806		 subu  $17,$9,$8
37807		 subu  $17,$17,$20
37808		 andi  $17,$17,0xFF
37809		 andi  $10,$8,0x0F
37810		 andi  $11,$9,0x0F
37811		 andi  $8,$8,0xF0
37812		 andi  $9,$9,0xF0
37813		 subu  $11,$11,$10
37814		 subu  $11,$11,$20
37815		 subu  $9,$9,$8
37816		 sltiu $12,$11,10
37817		 xori  $12,$12,1
37818		 sll   $12,$12,1
37819		 subu  $11,$11,$12
37820		 sll   $12,$12,1
37821		 subu  $11,$11,$12
37822		 addu  $2,$9,$11
37823		 sltiu $16,$2,0x9a
37824		 xori  $16,$16,1        	 # Set Carry
37825		 sll   $12,$16,5
37826		 addu  $2,$2,$12
37827		 sll   $12,$12,2
37828		 addu  $2,$2,$12
37829		 xor   $19,$17,$2
37830		 and   $17,$17,$19
37831		 srl   $17,$17,7        	 # Set Overflow
37832		 sltiu $25,$2,1
37833		 and   $18,$18,$25       	 # Set Zero
37834		 srl   $19,$2,7         	 # Set Sign
37835		 or    $20,$0,$16       	 # Copy Carry to X
37836		 sb    $2,0x00($24)
37837		 addiu $15,$15,-6
37838		 bgez  $15,3f
37839		 lhu   $24,0x00($23)    	 # Delay slot
37840		 j     MainExit
37841	3:
37842		 sll   $7,$24,2         	 # Delay slot
37843		 addu  $7,$7,$30
37844		 lw    $7,0x00($7)
37845		 jr    $7
37846		 nop                    	 # Delay slot
37847
37848OP0_8108:				#:
37849		 addiu $23,$23,2
37850
37851		 andi  $8,$24,0x07
37852		 srl   $24,$24,7
37853		 andi  $24,$24,0x1C
37854		 sll   $8,$8,2
37855		 addu  $8,$8,$21
37856		 lw    $14,0x20($8)
37857		 addiu $14,$14,-1
37858		 sw    $14,0x20($8)
37859		 lw    $25,0x7C($21)
37860		 sw    $15,m68k_ICount
37861		 sw    $24,0x44($29)
37862		 or    $4,$0,$14
37863		 jalr  $25
37864		 sw    $23,0x4C($21)    	 # Delay slot
37865		 lw    $24,0x44($29)
37866		 lw    $15,m68k_ICount
37867		 or    $8,$0,$2
37868		 addu  $24,$24,$21
37869		 lw    $14,0x20($24)
37870		 addiu $14,$14,-1
37871		 sw    $14,0x20($24)
37872		 lw    $25,0x7C($21)
37873		 sw    $15,m68k_ICount
37874		 sw    $8,0x44($29)
37875		 sw    $14,0x40($29)
37876		 sw    $24,0x3C($29)
37877		 or    $4,$0,$14
37878		 jalr  $25
37879		 sw    $23,0x4C($21)    	 # Delay slot
37880		 lw    $24,0x3C($29)
37881		 lw    $14,0x40($29)
37882		 lw    $8,0x44($29)
37883		 lw    $15,m68k_ICount
37884		 or    $9,$0,$2
37885		 subu  $17,$9,$8
37886		 subu  $17,$17,$20
37887		 andi  $17,$17,0xFF
37888		 andi  $10,$8,0x0F
37889		 andi  $11,$9,0x0F
37890		 andi  $8,$8,0xF0
37891		 andi  $9,$9,0xF0
37892		 subu  $11,$11,$10
37893		 subu  $11,$11,$20
37894		 subu  $9,$9,$8
37895		 sltiu $12,$11,10
37896		 xori  $12,$12,1
37897		 sll   $12,$12,1
37898		 subu  $11,$11,$12
37899		 sll   $12,$12,1
37900		 subu  $11,$11,$12
37901		 addu  $2,$9,$11
37902		 sltiu $16,$2,0x9a
37903		 xori  $16,$16,1        	 # Set Carry
37904		 sll   $12,$16,5
37905		 addu  $2,$2,$12
37906		 sll   $12,$12,2
37907		 addu  $2,$2,$12
37908		 xor   $19,$17,$2
37909		 and   $17,$17,$19
37910		 srl   $17,$17,7        	 # Set Overflow
37911		 sltiu $25,$2,1
37912		 and   $18,$18,$25       	 # Set Zero
37913		 srl   $19,$2,7         	 # Set Sign
37914		 or    $20,$0,$16       	 # Copy Carry to X
37915		 lw    $25,0x88($21)
37916		 sw    $15,m68k_ICount
37917		 or    $5,$0,$2
37918		 or    $4,$0,$14
37919		 jalr  $25
37920		 sw    $23,0x4C($21)    	 # Delay slot
37921		 lw    $15,m68k_ICount
37922		 addiu $15,$15,-18
37923		 bgez  $15,3f
37924		 lhu   $24,0x00($23)    	 # Delay slot
37925		 j     MainExit
37926	3:
37927		 sll   $7,$24,2         	 # Delay slot
37928		 addu  $7,$7,$30
37929		 lw    $7,0x00($7)
37930		 jr    $7
37931		 nop                    	 # Delay slot
37932
37933OP0_810f:				#:
37934		 addiu $23,$23,2
37935
37936		 andi  $8,$24,0x07
37937		 srl   $24,$24,7
37938		 andi  $24,$24,0x1C
37939		 lw    $14,0x3C($21)    	 # Get A7
37940		 addiu $14,$14,-2
37941		 sw    $14,0x3C($21)
37942		 lw    $25,0x7C($21)
37943		 sw    $15,m68k_ICount
37944		 sw    $24,0x44($29)
37945		 or    $4,$0,$14
37946		 jalr  $25
37947		 sw    $23,0x4C($21)    	 # Delay slot
37948		 lw    $24,0x44($29)
37949		 lw    $15,m68k_ICount
37950		 or    $8,$0,$2
37951		 addu  $24,$24,$21
37952		 lw    $14,0x20($24)
37953		 addiu $14,$14,-1
37954		 sw    $14,0x20($24)
37955		 lw    $25,0x7C($21)
37956		 sw    $15,m68k_ICount
37957		 sw    $8,0x44($29)
37958		 sw    $14,0x40($29)
37959		 sw    $24,0x3C($29)
37960		 or    $4,$0,$14
37961		 jalr  $25
37962		 sw    $23,0x4C($21)    	 # Delay slot
37963		 lw    $24,0x3C($29)
37964		 lw    $14,0x40($29)
37965		 lw    $8,0x44($29)
37966		 lw    $15,m68k_ICount
37967		 or    $9,$0,$2
37968		 subu  $17,$9,$8
37969		 subu  $17,$17,$20
37970		 andi  $17,$17,0xFF
37971		 andi  $10,$8,0x0F
37972		 andi  $11,$9,0x0F
37973		 andi  $8,$8,0xF0
37974		 andi  $9,$9,0xF0
37975		 subu  $11,$11,$10
37976		 subu  $11,$11,$20
37977		 subu  $9,$9,$8
37978		 sltiu $12,$11,10
37979		 xori  $12,$12,1
37980		 sll   $12,$12,1
37981		 subu  $11,$11,$12
37982		 sll   $12,$12,1
37983		 subu  $11,$11,$12
37984		 addu  $2,$9,$11
37985		 sltiu $16,$2,0x9a
37986		 xori  $16,$16,1        	 # Set Carry
37987		 sll   $12,$16,5
37988		 addu  $2,$2,$12
37989		 sll   $12,$12,2
37990		 addu  $2,$2,$12
37991		 xor   $19,$17,$2
37992		 and   $17,$17,$19
37993		 srl   $17,$17,7        	 # Set Overflow
37994		 sltiu $25,$2,1
37995		 and   $18,$18,$25       	 # Set Zero
37996		 srl   $19,$2,7         	 # Set Sign
37997		 or    $20,$0,$16       	 # Copy Carry to X
37998		 lw    $25,0x88($21)
37999		 sw    $15,m68k_ICount
38000		 or    $5,$0,$2
38001		 or    $4,$0,$14
38002		 jalr  $25
38003		 sw    $23,0x4C($21)    	 # Delay slot
38004		 lw    $15,m68k_ICount
38005		 addiu $15,$15,-18
38006		 bgez  $15,3f
38007		 lhu   $24,0x00($23)    	 # Delay slot
38008		 j     MainExit
38009	3:
38010		 sll   $7,$24,2         	 # Delay slot
38011		 addu  $7,$7,$30
38012		 lw    $7,0x00($7)
38013		 jr    $7
38014		 nop                    	 # Delay slot
38015
38016OP0_8f08:				#:
38017		 addiu $23,$23,2
38018
38019		 andi  $8,$24,0x07
38020		 srl   $24,$24,7
38021		 andi  $24,$24,0x1C
38022		 sll   $8,$8,2
38023		 addu  $8,$8,$21
38024		 lw    $14,0x20($8)
38025		 addiu $14,$14,-1
38026		 sw    $14,0x20($8)
38027		 lw    $25,0x7C($21)
38028		 sw    $15,m68k_ICount
38029		 sw    $24,0x44($29)
38030		 or    $4,$0,$14
38031		 jalr  $25
38032		 sw    $23,0x4C($21)    	 # Delay slot
38033		 lw    $24,0x44($29)
38034		 lw    $15,m68k_ICount
38035		 or    $8,$0,$2
38036		 lw    $14,0x3C($21)    	 # Get A7
38037		 addiu $14,$14,-2
38038		 sw    $14,0x3C($21)
38039		 lw    $25,0x7C($21)
38040		 sw    $15,m68k_ICount
38041		 sw    $8,0x44($29)
38042		 sw    $14,0x40($29)
38043		 sw    $24,0x3C($29)
38044		 or    $4,$0,$14
38045		 jalr  $25
38046		 sw    $23,0x4C($21)    	 # Delay slot
38047		 lw    $24,0x3C($29)
38048		 lw    $14,0x40($29)
38049		 lw    $8,0x44($29)
38050		 lw    $15,m68k_ICount
38051		 or    $9,$0,$2
38052		 subu  $17,$9,$8
38053		 subu  $17,$17,$20
38054		 andi  $17,$17,0xFF
38055		 andi  $10,$8,0x0F
38056		 andi  $11,$9,0x0F
38057		 andi  $8,$8,0xF0
38058		 andi  $9,$9,0xF0
38059		 subu  $11,$11,$10
38060		 subu  $11,$11,$20
38061		 subu  $9,$9,$8
38062		 sltiu $12,$11,10
38063		 xori  $12,$12,1
38064		 sll   $12,$12,1
38065		 subu  $11,$11,$12
38066		 sll   $12,$12,1
38067		 subu  $11,$11,$12
38068		 addu  $2,$9,$11
38069		 sltiu $16,$2,0x9a
38070		 xori  $16,$16,1        	 # Set Carry
38071		 sll   $12,$16,5
38072		 addu  $2,$2,$12
38073		 sll   $12,$12,2
38074		 addu  $2,$2,$12
38075		 xor   $19,$17,$2
38076		 and   $17,$17,$19
38077		 srl   $17,$17,7        	 # Set Overflow
38078		 sltiu $25,$2,1
38079		 and   $18,$18,$25       	 # Set Zero
38080		 srl   $19,$2,7         	 # Set Sign
38081		 or    $20,$0,$16       	 # Copy Carry to X
38082		 lw    $25,0x88($21)
38083		 sw    $15,m68k_ICount
38084		 or    $5,$0,$2
38085		 or    $4,$0,$14
38086		 jalr  $25
38087		 sw    $23,0x4C($21)    	 # Delay slot
38088		 lw    $15,m68k_ICount
38089		 addiu $15,$15,-18
38090		 bgez  $15,3f
38091		 lhu   $24,0x00($23)    	 # Delay slot
38092		 j     MainExit
38093	3:
38094		 sll   $7,$24,2         	 # Delay slot
38095		 addu  $7,$7,$30
38096		 lw    $7,0x00($7)
38097		 jr    $7
38098		 nop                    	 # Delay slot
38099
38100OP0_8f0f:				#:
38101		 addiu $23,$23,2
38102
38103		 andi  $8,$24,0x07
38104		 srl   $24,$24,7
38105		 andi  $24,$24,0x1C
38106		 lw    $14,0x3C($21)    	 # Get A7
38107		 addiu $14,$14,-2
38108		 sw    $14,0x3C($21)
38109		 lw    $25,0x7C($21)
38110		 sw    $15,m68k_ICount
38111		 sw    $24,0x44($29)
38112		 or    $4,$0,$14
38113		 jalr  $25
38114		 sw    $23,0x4C($21)    	 # Delay slot
38115		 lw    $24,0x44($29)
38116		 lw    $15,m68k_ICount
38117		 or    $8,$0,$2
38118		 lw    $14,0x3C($21)    	 # Get A7
38119		 addiu $14,$14,-2
38120		 sw    $14,0x3C($21)
38121		 lw    $25,0x7C($21)
38122		 sw    $15,m68k_ICount
38123		 sw    $8,0x44($29)
38124		 sw    $14,0x40($29)
38125		 sw    $24,0x3C($29)
38126		 or    $4,$0,$14
38127		 jalr  $25
38128		 sw    $23,0x4C($21)    	 # Delay slot
38129		 lw    $24,0x3C($29)
38130		 lw    $14,0x40($29)
38131		 lw    $8,0x44($29)
38132		 lw    $15,m68k_ICount
38133		 or    $9,$0,$2
38134		 subu  $17,$9,$8
38135		 subu  $17,$17,$20
38136		 andi  $17,$17,0xFF
38137		 andi  $10,$8,0x0F
38138		 andi  $11,$9,0x0F
38139		 andi  $8,$8,0xF0
38140		 andi  $9,$9,0xF0
38141		 subu  $11,$11,$10
38142		 subu  $11,$11,$20
38143		 subu  $9,$9,$8
38144		 sltiu $12,$11,10
38145		 xori  $12,$12,1
38146		 sll   $12,$12,1
38147		 subu  $11,$11,$12
38148		 sll   $12,$12,1
38149		 subu  $11,$11,$12
38150		 addu  $2,$9,$11
38151		 sltiu $16,$2,0x9a
38152		 xori  $16,$16,1        	 # Set Carry
38153		 sll   $12,$16,5
38154		 addu  $2,$2,$12
38155		 sll   $12,$12,2
38156		 addu  $2,$2,$12
38157		 xor   $19,$17,$2
38158		 and   $17,$17,$19
38159		 srl   $17,$17,7        	 # Set Overflow
38160		 sltiu $25,$2,1
38161		 and   $18,$18,$25       	 # Set Zero
38162		 srl   $19,$2,7         	 # Set Sign
38163		 or    $20,$0,$16       	 # Copy Carry to X
38164		 lw    $25,0x88($21)
38165		 sw    $15,m68k_ICount
38166		 or    $5,$0,$2
38167		 or    $4,$0,$14
38168		 jalr  $25
38169		 sw    $23,0x4C($21)    	 # Delay slot
38170		 lw    $15,m68k_ICount
38171		 addiu $15,$15,-18
38172		 bgez  $15,3f
38173		 lhu   $24,0x00($23)    	 # Delay slot
38174		 j     MainExit
38175	3:
38176		 sll   $7,$24,2         	 # Delay slot
38177		 addu  $7,$7,$30
38178		 lw    $7,0x00($7)
38179		 jr    $7
38180		 nop                    	 # Delay slot
38181
38182OP0_c100:				#:
38183		 addiu $23,$23,2
38184
38185		 andi  $8,$24,0x07
38186		 srl   $24,$24,7
38187		 andi  $24,$24,0x1C
38188		 sll   $8,$8,2
38189		 addu  $8,$8,$21
38190		 lbu   $8,0x00($8)
38191		 addu  $24,$24,$21
38192		 lbu   $9,0x00($24)
38193		 addu  $17,$9,$8
38194		 addu  $17,$17,$20
38195		 andi  $17,$17,0xFF
38196		 andi  $10,$8,0x0F
38197		 andi  $11,$9,0x0F
38198		 andi  $8,$8,0xF0
38199		 andi  $9,$9,0xF0
38200		 addu  $11,$11,$10
38201		 addu  $11,$11,$20
38202		 addu  $9,$9,$8
38203		 sltiu $12,$11,10
38204		 xori  $12,$12,1
38205		 sll   $12,$12,1
38206		 addu  $11,$11,$12
38207		 sll   $12,$12,1
38208		 addu  $11,$11,$12
38209		 addu  $2,$9,$11
38210		 sltiu $16,$2,0x9a
38211		 xori  $16,$16,1        	 # Set Carry
38212		 sll   $12,$16,5
38213		 subu  $2,$2,$12
38214		 sll   $12,$12,2
38215		 subu  $2,$2,$12
38216		 nor   $17,$0,$17
38217		 xor   $19,$17,$2
38218		 and   $17,$17,$19
38219		 srl   $17,$17,7
38220		 andi  $17,$17,0x01     	 # Set Overflow
38221		 sltiu $25,$2,1
38222		 and   $18,$18,$25       	 # Set Zero
38223		 srl   $19,$2,7         	 # Set Sign
38224		 or    $20,$0,$16       	 # Copy Carry to X
38225		 sb    $2,0x00($24)
38226		 addiu $15,$15,-6
38227		 bgez  $15,3f
38228		 lhu   $24,0x00($23)    	 # Delay slot
38229		 j     MainExit
38230	3:
38231		 sll   $7,$24,2         	 # Delay slot
38232		 addu  $7,$7,$30
38233		 lw    $7,0x00($7)
38234		 jr    $7
38235		 nop                    	 # Delay slot
38236
38237OP0_c108:				#:
38238		 addiu $23,$23,2
38239
38240		 andi  $8,$24,0x07
38241		 srl   $24,$24,7
38242		 andi  $24,$24,0x1C
38243		 sll   $8,$8,2
38244		 addu  $8,$8,$21
38245		 lw    $14,0x20($8)
38246		 addiu $14,$14,-1
38247		 sw    $14,0x20($8)
38248		 lw    $25,0x7C($21)
38249		 sw    $15,m68k_ICount
38250		 sw    $24,0x44($29)
38251		 or    $4,$0,$14
38252		 jalr  $25
38253		 sw    $23,0x4C($21)    	 # Delay slot
38254		 lw    $24,0x44($29)
38255		 lw    $15,m68k_ICount
38256		 or    $8,$0,$2
38257		 addu  $24,$24,$21
38258		 lw    $14,0x20($24)
38259		 addiu $14,$14,-1
38260		 sw    $14,0x20($24)
38261		 lw    $25,0x7C($21)
38262		 sw    $15,m68k_ICount
38263		 sw    $8,0x44($29)
38264		 sw    $14,0x40($29)
38265		 sw    $24,0x3C($29)
38266		 or    $4,$0,$14
38267		 jalr  $25
38268		 sw    $23,0x4C($21)    	 # Delay slot
38269		 lw    $24,0x3C($29)
38270		 lw    $14,0x40($29)
38271		 lw    $8,0x44($29)
38272		 lw    $15,m68k_ICount
38273		 or    $9,$0,$2
38274		 addu  $17,$9,$8
38275		 addu  $17,$17,$20
38276		 andi  $17,$17,0xFF
38277		 andi  $10,$8,0x0F
38278		 andi  $11,$9,0x0F
38279		 andi  $8,$8,0xF0
38280		 andi  $9,$9,0xF0
38281		 addu  $11,$11,$10
38282		 addu  $11,$11,$20
38283		 addu  $9,$9,$8
38284		 sltiu $12,$11,10
38285		 xori  $12,$12,1
38286		 sll   $12,$12,1
38287		 addu  $11,$11,$12
38288		 sll   $12,$12,1
38289		 addu  $11,$11,$12
38290		 addu  $2,$9,$11
38291		 sltiu $16,$2,0x9a
38292		 xori  $16,$16,1        	 # Set Carry
38293		 sll   $12,$16,5
38294		 subu  $2,$2,$12
38295		 sll   $12,$12,2
38296		 subu  $2,$2,$12
38297		 nor   $17,$0,$17
38298		 xor   $19,$17,$2
38299		 and   $17,$17,$19
38300		 srl   $17,$17,7
38301		 andi  $17,$17,0x01     	 # Set Overflow
38302		 sltiu $25,$2,1
38303		 and   $18,$18,$25       	 # Set Zero
38304		 srl   $19,$2,7         	 # Set Sign
38305		 or    $20,$0,$16       	 # Copy Carry to X
38306		 lw    $25,0x88($21)
38307		 sw    $15,m68k_ICount
38308		 or    $5,$0,$2
38309		 or    $4,$0,$14
38310		 jalr  $25
38311		 sw    $23,0x4C($21)    	 # Delay slot
38312		 lw    $15,m68k_ICount
38313		 addiu $15,$15,-18
38314		 bgez  $15,3f
38315		 lhu   $24,0x00($23)    	 # Delay slot
38316		 j     MainExit
38317	3:
38318		 sll   $7,$24,2         	 # Delay slot
38319		 addu  $7,$7,$30
38320		 lw    $7,0x00($7)
38321		 jr    $7
38322		 nop                    	 # Delay slot
38323
38324OP0_c10f:				#:
38325		 addiu $23,$23,2
38326
38327		 andi  $8,$24,0x07
38328		 srl   $24,$24,7
38329		 andi  $24,$24,0x1C
38330		 lw    $14,0x3C($21)    	 # Get A7
38331		 addiu $14,$14,-2
38332		 sw    $14,0x3C($21)
38333		 lw    $25,0x7C($21)
38334		 sw    $15,m68k_ICount
38335		 sw    $24,0x44($29)
38336		 or    $4,$0,$14
38337		 jalr  $25
38338		 sw    $23,0x4C($21)    	 # Delay slot
38339		 lw    $24,0x44($29)
38340		 lw    $15,m68k_ICount
38341		 or    $8,$0,$2
38342		 addu  $24,$24,$21
38343		 lw    $14,0x20($24)
38344		 addiu $14,$14,-1
38345		 sw    $14,0x20($24)
38346		 lw    $25,0x7C($21)
38347		 sw    $15,m68k_ICount
38348		 sw    $8,0x44($29)
38349		 sw    $14,0x40($29)
38350		 sw    $24,0x3C($29)
38351		 or    $4,$0,$14
38352		 jalr  $25
38353		 sw    $23,0x4C($21)    	 # Delay slot
38354		 lw    $24,0x3C($29)
38355		 lw    $14,0x40($29)
38356		 lw    $8,0x44($29)
38357		 lw    $15,m68k_ICount
38358		 or    $9,$0,$2
38359		 addu  $17,$9,$8
38360		 addu  $17,$17,$20
38361		 andi  $17,$17,0xFF
38362		 andi  $10,$8,0x0F
38363		 andi  $11,$9,0x0F
38364		 andi  $8,$8,0xF0
38365		 andi  $9,$9,0xF0
38366		 addu  $11,$11,$10
38367		 addu  $11,$11,$20
38368		 addu  $9,$9,$8
38369		 sltiu $12,$11,10
38370		 xori  $12,$12,1
38371		 sll   $12,$12,1
38372		 addu  $11,$11,$12
38373		 sll   $12,$12,1
38374		 addu  $11,$11,$12
38375		 addu  $2,$9,$11
38376		 sltiu $16,$2,0x9a
38377		 xori  $16,$16,1        	 # Set Carry
38378		 sll   $12,$16,5
38379		 subu  $2,$2,$12
38380		 sll   $12,$12,2
38381		 subu  $2,$2,$12
38382		 nor   $17,$0,$17
38383		 xor   $19,$17,$2
38384		 and   $17,$17,$19
38385		 srl   $17,$17,7
38386		 andi  $17,$17,0x01     	 # Set Overflow
38387		 sltiu $25,$2,1
38388		 and   $18,$18,$25       	 # Set Zero
38389		 srl   $19,$2,7         	 # Set Sign
38390		 or    $20,$0,$16       	 # Copy Carry to X
38391		 lw    $25,0x88($21)
38392		 sw    $15,m68k_ICount
38393		 or    $5,$0,$2
38394		 or    $4,$0,$14
38395		 jalr  $25
38396		 sw    $23,0x4C($21)    	 # Delay slot
38397		 lw    $15,m68k_ICount
38398		 addiu $15,$15,-18
38399		 bgez  $15,3f
38400		 lhu   $24,0x00($23)    	 # Delay slot
38401		 j     MainExit
38402	3:
38403		 sll   $7,$24,2         	 # Delay slot
38404		 addu  $7,$7,$30
38405		 lw    $7,0x00($7)
38406		 jr    $7
38407		 nop                    	 # Delay slot
38408
38409OP0_cf08:				#:
38410		 addiu $23,$23,2
38411
38412		 andi  $8,$24,0x07
38413		 srl   $24,$24,7
38414		 andi  $24,$24,0x1C
38415		 sll   $8,$8,2
38416		 addu  $8,$8,$21
38417		 lw    $14,0x20($8)
38418		 addiu $14,$14,-1
38419		 sw    $14,0x20($8)
38420		 lw    $25,0x7C($21)
38421		 sw    $15,m68k_ICount
38422		 sw    $24,0x44($29)
38423		 or    $4,$0,$14
38424		 jalr  $25
38425		 sw    $23,0x4C($21)    	 # Delay slot
38426		 lw    $24,0x44($29)
38427		 lw    $15,m68k_ICount
38428		 or    $8,$0,$2
38429		 lw    $14,0x3C($21)    	 # Get A7
38430		 addiu $14,$14,-2
38431		 sw    $14,0x3C($21)
38432		 lw    $25,0x7C($21)
38433		 sw    $15,m68k_ICount
38434		 sw    $8,0x44($29)
38435		 sw    $14,0x40($29)
38436		 sw    $24,0x3C($29)
38437		 or    $4,$0,$14
38438		 jalr  $25
38439		 sw    $23,0x4C($21)    	 # Delay slot
38440		 lw    $24,0x3C($29)
38441		 lw    $14,0x40($29)
38442		 lw    $8,0x44($29)
38443		 lw    $15,m68k_ICount
38444		 or    $9,$0,$2
38445		 addu  $17,$9,$8
38446		 addu  $17,$17,$20
38447		 andi  $17,$17,0xFF
38448		 andi  $10,$8,0x0F
38449		 andi  $11,$9,0x0F
38450		 andi  $8,$8,0xF0
38451		 andi  $9,$9,0xF0
38452		 addu  $11,$11,$10
38453		 addu  $11,$11,$20
38454		 addu  $9,$9,$8
38455		 sltiu $12,$11,10
38456		 xori  $12,$12,1
38457		 sll   $12,$12,1
38458		 addu  $11,$11,$12
38459		 sll   $12,$12,1
38460		 addu  $11,$11,$12
38461		 addu  $2,$9,$11
38462		 sltiu $16,$2,0x9a
38463		 xori  $16,$16,1        	 # Set Carry
38464		 sll   $12,$16,5
38465		 subu  $2,$2,$12
38466		 sll   $12,$12,2
38467		 subu  $2,$2,$12
38468		 nor   $17,$0,$17
38469		 xor   $19,$17,$2
38470		 and   $17,$17,$19
38471		 srl   $17,$17,7
38472		 andi  $17,$17,0x01     	 # Set Overflow
38473		 sltiu $25,$2,1
38474		 and   $18,$18,$25       	 # Set Zero
38475		 srl   $19,$2,7         	 # Set Sign
38476		 or    $20,$0,$16       	 # Copy Carry to X
38477		 lw    $25,0x88($21)
38478		 sw    $15,m68k_ICount
38479		 or    $5,$0,$2
38480		 or    $4,$0,$14
38481		 jalr  $25
38482		 sw    $23,0x4C($21)    	 # Delay slot
38483		 lw    $15,m68k_ICount
38484		 addiu $15,$15,-18
38485		 bgez  $15,3f
38486		 lhu   $24,0x00($23)    	 # Delay slot
38487		 j     MainExit
38488	3:
38489		 sll   $7,$24,2         	 # Delay slot
38490		 addu  $7,$7,$30
38491		 lw    $7,0x00($7)
38492		 jr    $7
38493		 nop                    	 # Delay slot
38494
38495OP0_cf0f:				#:
38496		 addiu $23,$23,2
38497
38498		 andi  $8,$24,0x07
38499		 srl   $24,$24,7
38500		 andi  $24,$24,0x1C
38501		 lw    $14,0x3C($21)    	 # Get A7
38502		 addiu $14,$14,-2
38503		 sw    $14,0x3C($21)
38504		 lw    $25,0x7C($21)
38505		 sw    $15,m68k_ICount
38506		 sw    $24,0x44($29)
38507		 or    $4,$0,$14
38508		 jalr  $25
38509		 sw    $23,0x4C($21)    	 # Delay slot
38510		 lw    $24,0x44($29)
38511		 lw    $15,m68k_ICount
38512		 or    $8,$0,$2
38513		 lw    $14,0x3C($21)    	 # Get A7
38514		 addiu $14,$14,-2
38515		 sw    $14,0x3C($21)
38516		 lw    $25,0x7C($21)
38517		 sw    $15,m68k_ICount
38518		 sw    $8,0x44($29)
38519		 sw    $14,0x40($29)
38520		 sw    $24,0x3C($29)
38521		 or    $4,$0,$14
38522		 jalr  $25
38523		 sw    $23,0x4C($21)    	 # Delay slot
38524		 lw    $24,0x3C($29)
38525		 lw    $14,0x40($29)
38526		 lw    $8,0x44($29)
38527		 lw    $15,m68k_ICount
38528		 or    $9,$0,$2
38529		 addu  $17,$9,$8
38530		 addu  $17,$17,$20
38531		 andi  $17,$17,0xFF
38532		 andi  $10,$8,0x0F
38533		 andi  $11,$9,0x0F
38534		 andi  $8,$8,0xF0
38535		 andi  $9,$9,0xF0
38536		 addu  $11,$11,$10
38537		 addu  $11,$11,$20
38538		 addu  $9,$9,$8
38539		 sltiu $12,$11,10
38540		 xori  $12,$12,1
38541		 sll   $12,$12,1
38542		 addu  $11,$11,$12
38543		 sll   $12,$12,1
38544		 addu  $11,$11,$12
38545		 addu  $2,$9,$11
38546		 sltiu $16,$2,0x9a
38547		 xori  $16,$16,1        	 # Set Carry
38548		 sll   $12,$16,5
38549		 subu  $2,$2,$12
38550		 sll   $12,$12,2
38551		 subu  $2,$2,$12
38552		 nor   $17,$0,$17
38553		 xor   $19,$17,$2
38554		 and   $17,$17,$19
38555		 srl   $17,$17,7
38556		 andi  $17,$17,0x01     	 # Set Overflow
38557		 sltiu $25,$2,1
38558		 and   $18,$18,$25       	 # Set Zero
38559		 srl   $19,$2,7         	 # Set Sign
38560		 or    $20,$0,$16       	 # Copy Carry to X
38561		 lw    $25,0x88($21)
38562		 sw    $15,m68k_ICount
38563		 or    $5,$0,$2
38564		 or    $4,$0,$14
38565		 jalr  $25
38566		 sw    $23,0x4C($21)    	 # Delay slot
38567		 lw    $15,m68k_ICount
38568		 addiu $15,$15,-18
38569		 bgez  $15,3f
38570		 lhu   $24,0x00($23)    	 # Delay slot
38571		 j     MainExit
38572	3:
38573		 sll   $7,$24,2         	 # Delay slot
38574		 addu  $7,$7,$30
38575		 lw    $7,0x00($7)
38576		 jr    $7
38577		 nop                    	 # Delay slot
38578
38579OP0_8000:				#:
38580		 addiu $23,$23,2
38581
38582		 andi  $8,$24,0x07
38583		 srl   $24,$24,7
38584		 andi  $24,$24,0x1C
38585		 addu  $24,$24,$21
38586		 lb    $9,0x00($24)
38587		 sll   $8,$8,2
38588		 addu  $8,$8,$21
38589		 lb    $2,0x00($8)
38590		 or   $10,$9,$2
38591		 sb    $10,0x00($24)
38592		 and   $16,$0,$0        	 # Clear Carry
38593		 and   $17,$0,$0        	 # Clear Overflow
38594		 slt   $19,$10,$0        	 # Set Sign
38595		 sltiu $18,$10,1         	 # Set Zero
38596		 addiu $15,$15,-4
38597		 bgez  $15,3f
38598		 lhu   $24,0x00($23)    	 # Delay slot
38599		 j     MainExit
38600	3:
38601		 sll   $7,$24,2         	 # Delay slot
38602		 addu  $7,$7,$30
38603		 lw    $7,0x00($7)
38604		 jr    $7
38605		 nop                    	 # Delay slot
38606
38607OP0_8010:				#:
38608		 addiu $23,$23,2
38609
38610		 andi  $8,$24,0x07
38611		 srl   $24,$24,7
38612		 andi  $24,$24,0x1C
38613		 addu  $24,$24,$21
38614		 lb    $9,0x00($24)
38615		 sll   $8,$8,2
38616		 addu  $8,$8,$21
38617		 lw    $14,0x20($8)
38618		 lw    $25,0x7C($21)
38619		 sw    $15,m68k_ICount
38620		 sw    $9,0x44($29)
38621		 sw    $24,0x40($29)
38622		 or    $4,$0,$14
38623		 jalr  $25
38624		 sw    $23,0x4C($21)    	 # Delay slot
38625		 lw    $24,0x40($29)
38626		 lw    $9,0x44($29)
38627		 lw    $15,m68k_ICount
38628		 seb   $2,$2
38629		 or   $10,$9,$2
38630		 sb    $10,0x00($24)
38631		 and   $16,$0,$0        	 # Clear Carry
38632		 and   $17,$0,$0        	 # Clear Overflow
38633		 slt   $19,$10,$0        	 # Set Sign
38634		 sltiu $18,$10,1         	 # Set Zero
38635		 addiu $15,$15,-8
38636		 bgez  $15,3f
38637		 lhu   $24,0x00($23)    	 # Delay slot
38638		 j     MainExit
38639	3:
38640		 sll   $7,$24,2         	 # Delay slot
38641		 addu  $7,$7,$30
38642		 lw    $7,0x00($7)
38643		 jr    $7
38644		 nop                    	 # Delay slot
38645
38646OP0_8018:				#:
38647		 addiu $23,$23,2
38648
38649		 andi  $8,$24,0x07
38650		 srl   $24,$24,7
38651		 andi  $24,$24,0x1C
38652		 addu  $24,$24,$21
38653		 lb    $9,0x00($24)
38654		 sll   $8,$8,2
38655		 addu  $8,$8,$21
38656		 lw    $14,0x20($8)
38657		 addiu $25,$14,1
38658		 sw    $25,0x20($8)
38659		 lw    $25,0x7C($21)
38660		 sw    $15,m68k_ICount
38661		 sw    $9,0x44($29)
38662		 sw    $24,0x40($29)
38663		 or    $4,$0,$14
38664		 jalr  $25
38665		 sw    $23,0x4C($21)    	 # Delay slot
38666		 lw    $24,0x40($29)
38667		 lw    $9,0x44($29)
38668		 lw    $15,m68k_ICount
38669		 seb   $2,$2
38670		 or   $10,$9,$2
38671		 sb    $10,0x00($24)
38672		 and   $16,$0,$0        	 # Clear Carry
38673		 and   $17,$0,$0        	 # Clear Overflow
38674		 slt   $19,$10,$0        	 # Set Sign
38675		 sltiu $18,$10,1         	 # Set Zero
38676		 addiu $15,$15,-8
38677		 bgez  $15,3f
38678		 lhu   $24,0x00($23)    	 # Delay slot
38679		 j     MainExit
38680	3:
38681		 sll   $7,$24,2         	 # Delay slot
38682		 addu  $7,$7,$30
38683		 lw    $7,0x00($7)
38684		 jr    $7
38685		 nop                    	 # Delay slot
38686
38687OP0_801f:				#:
38688		 addiu $23,$23,2
38689
38690		 srl   $24,$24,7
38691		 andi  $24,$24,0x1C
38692		 addu  $24,$24,$21
38693		 lb    $9,0x00($24)
38694		 lw    $14,0x3C($21)    	 # Get A7
38695		 addiu $25,$14,2
38696		 sw    $25,0x3C($21)
38697		 lw    $25,0x7C($21)
38698		 sw    $15,m68k_ICount
38699		 sw    $9,0x44($29)
38700		 sw    $24,0x40($29)
38701		 or    $4,$0,$14
38702		 jalr  $25
38703		 sw    $23,0x4C($21)    	 # Delay slot
38704		 lw    $24,0x40($29)
38705		 lw    $9,0x44($29)
38706		 lw    $15,m68k_ICount
38707		 seb   $2,$2
38708		 or   $10,$9,$2
38709		 sb    $10,0x00($24)
38710		 and   $16,$0,$0        	 # Clear Carry
38711		 and   $17,$0,$0        	 # Clear Overflow
38712		 slt   $19,$10,$0        	 # Set Sign
38713		 sltiu $18,$10,1         	 # Set Zero
38714		 addiu $15,$15,-8
38715		 bgez  $15,3f
38716		 lhu   $24,0x00($23)    	 # Delay slot
38717		 j     MainExit
38718	3:
38719		 sll   $7,$24,2         	 # Delay slot
38720		 addu  $7,$7,$30
38721		 lw    $7,0x00($7)
38722		 jr    $7
38723		 nop                    	 # Delay slot
38724
38725OP0_8020:				#:
38726		 addiu $23,$23,2
38727
38728		 andi  $8,$24,0x07
38729		 srl   $24,$24,7
38730		 andi  $24,$24,0x1C
38731		 addu  $24,$24,$21
38732		 lb    $9,0x00($24)
38733		 sll   $8,$8,2
38734		 addu  $8,$8,$21
38735		 lw    $14,0x20($8)
38736		 addiu $14,$14,-1
38737		 sw    $14,0x20($8)
38738		 lw    $25,0x7C($21)
38739		 sw    $15,m68k_ICount
38740		 sw    $9,0x44($29)
38741		 sw    $24,0x40($29)
38742		 or    $4,$0,$14
38743		 jalr  $25
38744		 sw    $23,0x4C($21)    	 # Delay slot
38745		 lw    $24,0x40($29)
38746		 lw    $9,0x44($29)
38747		 lw    $15,m68k_ICount
38748		 seb   $2,$2
38749		 or   $10,$9,$2
38750		 sb    $10,0x00($24)
38751		 and   $16,$0,$0        	 # Clear Carry
38752		 and   $17,$0,$0        	 # Clear Overflow
38753		 slt   $19,$10,$0        	 # Set Sign
38754		 sltiu $18,$10,1         	 # Set Zero
38755		 addiu $15,$15,-10
38756		 bgez  $15,3f
38757		 lhu   $24,0x00($23)    	 # Delay slot
38758		 j     MainExit
38759	3:
38760		 sll   $7,$24,2         	 # Delay slot
38761		 addu  $7,$7,$30
38762		 lw    $7,0x00($7)
38763		 jr    $7
38764		 nop                    	 # Delay slot
38765
38766OP0_8027:				#:
38767		 addiu $23,$23,2
38768
38769		 srl   $24,$24,7
38770		 andi  $24,$24,0x1C
38771		 addu  $24,$24,$21
38772		 lb    $9,0x00($24)
38773		 lw    $14,0x3C($21)    	 # Get A7
38774		 addiu $14,$14,-2
38775		 sw    $14,0x3C($21)
38776		 lw    $25,0x7C($21)
38777		 sw    $15,m68k_ICount
38778		 sw    $9,0x44($29)
38779		 sw    $24,0x40($29)
38780		 or    $4,$0,$14
38781		 jalr  $25
38782		 sw    $23,0x4C($21)    	 # Delay slot
38783		 lw    $24,0x40($29)
38784		 lw    $9,0x44($29)
38785		 lw    $15,m68k_ICount
38786		 seb   $2,$2
38787		 or   $10,$9,$2
38788		 sb    $10,0x00($24)
38789		 and   $16,$0,$0        	 # Clear Carry
38790		 and   $17,$0,$0        	 # Clear Overflow
38791		 slt   $19,$10,$0        	 # Set Sign
38792		 sltiu $18,$10,1         	 # Set Zero
38793		 addiu $15,$15,-10
38794		 bgez  $15,3f
38795		 lhu   $24,0x00($23)    	 # Delay slot
38796		 j     MainExit
38797	3:
38798		 sll   $7,$24,2         	 # Delay slot
38799		 addu  $7,$7,$30
38800		 lw    $7,0x00($7)
38801		 jr    $7
38802		 nop                    	 # Delay slot
38803
38804OP0_8028:				#:
38805		 addiu $23,$23,2
38806
38807		 andi  $8,$24,0x07
38808		 srl   $24,$24,7
38809		 andi  $24,$24,0x1C
38810		 addu  $24,$24,$21
38811		 lb    $9,0x00($24)
38812		 lh    $7,0x00($23)
38813		 sll   $8,$8,2
38814		 addu  $8,$8,$21
38815		 lw    $14,0x20($8)
38816		 addiu $23,$23,2
38817		 addu  $14,$14,$7
38818		 lw    $25,0x7C($21)
38819		 sw    $15,m68k_ICount
38820		 sw    $9,0x44($29)
38821		 sw    $24,0x40($29)
38822		 or    $4,$0,$14
38823		 jalr  $25
38824		 sw    $23,0x4C($21)    	 # Delay slot
38825		 lw    $24,0x40($29)
38826		 lw    $9,0x44($29)
38827		 lw    $15,m68k_ICount
38828		 seb   $2,$2
38829		 or   $10,$9,$2
38830		 sb    $10,0x00($24)
38831		 and   $16,$0,$0        	 # Clear Carry
38832		 and   $17,$0,$0        	 # Clear Overflow
38833		 slt   $19,$10,$0        	 # Set Sign
38834		 sltiu $18,$10,1         	 # Set Zero
38835		 addiu $15,$15,-12
38836		 bgez  $15,3f
38837		 lhu   $24,0x00($23)    	 # Delay slot
38838		 j     MainExit
38839	3:
38840		 sll   $7,$24,2         	 # Delay slot
38841		 addu  $7,$7,$30
38842		 lw    $7,0x00($7)
38843		 jr    $7
38844		 nop                    	 # Delay slot
38845
38846OP0_8030:				#:
38847		 addiu $23,$23,2
38848
38849		 andi  $8,$24,0x07
38850		 srl   $24,$24,7
38851		 andi  $24,$24,0x1C
38852		 addu  $24,$24,$21
38853		 lb    $9,0x00($24)
38854		 sll   $8,$8,2
38855		 addu  $8,$8,$21
38856		 lw    $14,0x20($8)
38857		 lhu   $7,0x00($23)
38858		 addiu $23,$23,2
38859		 seb   $6,$7
38860		 or    $25,$0,$7
38861		 srl   $7,$7,12
38862		 andi  $25,$25,0x0800
38863		 sll   $7,$7,2
38864		 addu  $7,$7,$21
38865		 bne   $25,$0,0f
38866		 lw    $25,0x00($7)      	 # Delay slot
38867		 seh   $25,$25
38868	0:
38869		 addu  $25,$14,$25
38870		 addu  $14,$25,$6
38871		 lw    $25,0x7C($21)
38872		 sw    $15,m68k_ICount
38873		 sw    $9,0x44($29)
38874		 sw    $24,0x40($29)
38875		 or    $4,$0,$14
38876		 jalr  $25
38877		 sw    $23,0x4C($21)    	 # Delay slot
38878		 lw    $24,0x40($29)
38879		 lw    $9,0x44($29)
38880		 lw    $15,m68k_ICount
38881		 seb   $2,$2
38882		 or   $10,$9,$2
38883		 sb    $10,0x00($24)
38884		 and   $16,$0,$0        	 # Clear Carry
38885		 and   $17,$0,$0        	 # Clear Overflow
38886		 slt   $19,$10,$0        	 # Set Sign
38887		 sltiu $18,$10,1         	 # Set Zero
38888		 addiu $15,$15,-14
38889		 bgez  $15,3f
38890		 lhu   $24,0x00($23)    	 # Delay slot
38891		 j     MainExit
38892	3:
38893		 sll   $7,$24,2         	 # Delay slot
38894		 addu  $7,$7,$30
38895		 lw    $7,0x00($7)
38896		 jr    $7
38897		 nop                    	 # Delay slot
38898
38899OP0_8038:				#:
38900		 addiu $23,$23,2
38901
38902		 srl   $24,$24,7
38903		 andi  $24,$24,0x1C
38904		 addu  $24,$24,$21
38905		 lb    $9,0x00($24)
38906		 lh    $14,0x00($23)
38907		 addiu $23,$23,2
38908		 lw    $25,0x7C($21)
38909		 sw    $15,m68k_ICount
38910		 sw    $9,0x44($29)
38911		 sw    $24,0x40($29)
38912		 or    $4,$0,$14
38913		 jalr  $25
38914		 sw    $23,0x4C($21)    	 # Delay slot
38915		 lw    $24,0x40($29)
38916		 lw    $9,0x44($29)
38917		 lw    $15,m68k_ICount
38918		 seb   $2,$2
38919		 or   $10,$9,$2
38920		 sb    $10,0x00($24)
38921		 and   $16,$0,$0        	 # Clear Carry
38922		 and   $17,$0,$0        	 # Clear Overflow
38923		 slt   $19,$10,$0        	 # Set Sign
38924		 sltiu $18,$10,1         	 # Set Zero
38925		 addiu $15,$15,-12
38926		 bgez  $15,3f
38927		 lhu   $24,0x00($23)    	 # Delay slot
38928		 j     MainExit
38929	3:
38930		 sll   $7,$24,2         	 # Delay slot
38931		 addu  $7,$7,$30
38932		 lw    $7,0x00($7)
38933		 jr    $7
38934		 nop                    	 # Delay slot
38935
38936OP0_8039:				#:
38937		 addiu $23,$23,2
38938
38939		 srl   $24,$24,7
38940		 andi  $24,$24,0x1C
38941		 addu  $24,$24,$21
38942		 lb    $9,0x00($24)
38943		 lhu   $14,0x00($23)
38944		 lhu   $25,0x02($23)
38945		 sll   $14,$14,16
38946		 or    $14,$14,$25
38947		 addiu $23,$23,4
38948		 lw    $25,0x7C($21)
38949		 sw    $15,m68k_ICount
38950		 sw    $9,0x44($29)
38951		 sw    $24,0x40($29)
38952		 or    $4,$0,$14
38953		 jalr  $25
38954		 sw    $23,0x4C($21)    	 # Delay slot
38955		 lw    $24,0x40($29)
38956		 lw    $9,0x44($29)
38957		 lw    $15,m68k_ICount
38958		 seb   $2,$2
38959		 or   $10,$9,$2
38960		 sb    $10,0x00($24)
38961		 and   $16,$0,$0        	 # Clear Carry
38962		 and   $17,$0,$0        	 # Clear Overflow
38963		 slt   $19,$10,$0        	 # Set Sign
38964		 sltiu $18,$10,1         	 # Set Zero
38965		 addiu $15,$15,-16
38966		 bgez  $15,3f
38967		 lhu   $24,0x00($23)    	 # Delay slot
38968		 j     MainExit
38969	3:
38970		 sll   $7,$24,2         	 # Delay slot
38971		 addu  $7,$7,$30
38972		 lw    $7,0x00($7)
38973		 jr    $7
38974		 nop                    	 # Delay slot
38975
38976OP0_803a:				#:
38977		 addiu $23,$23,2
38978
38979		 srl   $24,$24,7
38980		 andi  $24,$24,0x1C
38981		 addu  $24,$24,$21
38982		 lb    $9,0x00($24)
38983		 lh    $7,0x00($23)
38984		 subu  $25,$23,$22
38985		 addu  $14,$25,$7       	 # Add Offset to PC
38986		 addiu $23,$23,2
38987		 lw    $25,0x98($21)
38988		 sw    $15,m68k_ICount
38989		 sw    $9,0x44($29)
38990		 sw    $24,0x40($29)
38991		 or    $4,$0,$14
38992		 jalr  $25
38993		 sw    $23,0x4C($21)    	 # Delay slot
38994		 lw    $24,0x40($29)
38995		 lw    $9,0x44($29)
38996		 lw    $15,m68k_ICount
38997		 seb   $2,$2
38998		 or   $10,$9,$2
38999		 sb    $10,0x00($24)
39000		 and   $16,$0,$0        	 # Clear Carry
39001		 and   $17,$0,$0        	 # Clear Overflow
39002		 slt   $19,$10,$0        	 # Set Sign
39003		 sltiu $18,$10,1         	 # Set Zero
39004		 addiu $15,$15,-12
39005		 bgez  $15,3f
39006		 lhu   $24,0x00($23)    	 # Delay slot
39007		 j     MainExit
39008	3:
39009		 sll   $7,$24,2         	 # Delay slot
39010		 addu  $7,$7,$30
39011		 lw    $7,0x00($7)
39012		 jr    $7
39013		 nop                    	 # Delay slot
39014
39015OP0_803b:				#:
39016		 addiu $23,$23,2
39017
39018		 srl   $24,$24,7
39019		 andi  $24,$24,0x1C
39020		 addu  $24,$24,$21
39021		 lb    $9,0x00($24)
39022		 subu  $14,$23,$22       	 # Get PC
39023		 lhu   $7,0x00($23)
39024		 addiu $23,$23,2
39025		 seb   $6,$7
39026		 or    $25,$0,$7
39027		 srl   $7,$7,12
39028		 andi  $25,$25,0x0800
39029		 sll   $7,$7,2
39030		 addu  $7,$7,$21
39031		 bne   $25,$0,0f
39032		 lw    $25,0x00($7)      	 # Delay slot
39033		 seh   $25,$25
39034	0:
39035		 addu  $25,$14,$25
39036		 addu  $14,$25,$6
39037		 lw    $25,0x98($21)
39038		 sw    $15,m68k_ICount
39039		 sw    $9,0x44($29)
39040		 sw    $24,0x40($29)
39041		 or    $4,$0,$14
39042		 jalr  $25
39043		 sw    $23,0x4C($21)    	 # Delay slot
39044		 lw    $24,0x40($29)
39045		 lw    $9,0x44($29)
39046		 lw    $15,m68k_ICount
39047		 seb   $2,$2
39048		 or   $10,$9,$2
39049		 sb    $10,0x00($24)
39050		 and   $16,$0,$0        	 # Clear Carry
39051		 and   $17,$0,$0        	 # Clear Overflow
39052		 slt   $19,$10,$0        	 # Set Sign
39053		 sltiu $18,$10,1         	 # Set Zero
39054		 addiu $15,$15,-14
39055		 bgez  $15,3f
39056		 lhu   $24,0x00($23)    	 # Delay slot
39057		 j     MainExit
39058	3:
39059		 sll   $7,$24,2         	 # Delay slot
39060		 addu  $7,$7,$30
39061		 lw    $7,0x00($7)
39062		 jr    $7
39063		 nop                    	 # Delay slot
39064
39065OP0_803c:				#:
39066		 addiu $23,$23,2
39067
39068		 srl   $24,$24,7
39069		 andi  $24,$24,0x1C
39070		 addu  $24,$24,$21
39071		 lb    $9,0x00($24)
39072		 lb    $2,0x00($23)
39073		 addiu $23,$23,2
39074		 or   $10,$9,$2
39075		 sb    $10,0x00($24)
39076		 and   $16,$0,$0        	 # Clear Carry
39077		 and   $17,$0,$0        	 # Clear Overflow
39078		 slt   $19,$10,$0        	 # Set Sign
39079		 sltiu $18,$10,1         	 # Set Zero
39080		 addiu $15,$15,-4
39081		 bgez  $15,3f
39082		 lhu   $24,0x00($23)    	 # Delay slot
39083		 j     MainExit
39084	3:
39085		 sll   $7,$24,2         	 # Delay slot
39086		 addu  $7,$7,$30
39087		 lw    $7,0x00($7)
39088		 jr    $7
39089		 nop                    	 # Delay slot
39090
39091OP0_8040:				#:
39092		 addiu $23,$23,2
39093
39094		 andi  $8,$24,0x07
39095		 srl   $24,$24,7
39096		 andi  $24,$24,0x1C
39097		 addu  $24,$24,$21
39098		 lh    $9,0x00($24)
39099		 sll   $8,$8,2
39100		 addu  $8,$8,$21
39101		 lh    $2,0x00($8)
39102		 or   $10,$9,$2
39103		 sh    $10,0x00($24)
39104		 and   $16,$0,$0        	 # Clear Carry
39105		 and   $17,$0,$0        	 # Clear Overflow
39106		 slt   $19,$10,$0        	 # Set Sign
39107		 sltiu $18,$10,1         	 # Set Zero
39108		 addiu $15,$15,-4
39109		 bgez  $15,3f
39110		 lhu   $24,0x00($23)    	 # Delay slot
39111		 j     MainExit
39112	3:
39113		 sll   $7,$24,2         	 # Delay slot
39114		 addu  $7,$7,$30
39115		 lw    $7,0x00($7)
39116		 jr    $7
39117		 nop                    	 # Delay slot
39118
39119OP0_8050:				#:
39120		 addiu $23,$23,2
39121
39122		 andi  $8,$24,0x07
39123		 srl   $24,$24,7
39124		 andi  $24,$24,0x1C
39125		 addu  $24,$24,$21
39126		 lh    $9,0x00($24)
39127		 sll   $8,$8,2
39128		 addu  $8,$8,$21
39129		 lw    $14,0x20($8)
39130		 lw    $25,0x80($21)
39131		 sw    $15,m68k_ICount
39132		 sw    $9,0x44($29)
39133		 sw    $24,0x40($29)
39134		 or    $4,$0,$14
39135		 jalr  $25
39136		 sw    $23,0x4C($21)    	 # Delay slot
39137		 lw    $24,0x40($29)
39138		 lw    $9,0x44($29)
39139		 lw    $15,m68k_ICount
39140		 seh   $2,$2
39141		 or   $10,$9,$2
39142		 sh    $10,0x00($24)
39143		 and   $16,$0,$0        	 # Clear Carry
39144		 and   $17,$0,$0        	 # Clear Overflow
39145		 slt   $19,$10,$0        	 # Set Sign
39146		 sltiu $18,$10,1         	 # Set Zero
39147		 addiu $15,$15,-8
39148		 bgez  $15,3f
39149		 lhu   $24,0x00($23)    	 # Delay slot
39150		 j     MainExit
39151	3:
39152		 sll   $7,$24,2         	 # Delay slot
39153		 addu  $7,$7,$30
39154		 lw    $7,0x00($7)
39155		 jr    $7
39156		 nop                    	 # Delay slot
39157
39158OP0_8058:				#:
39159		 addiu $23,$23,2
39160
39161		 andi  $8,$24,0x07
39162		 srl   $24,$24,7
39163		 andi  $24,$24,0x1C
39164		 addu  $24,$24,$21
39165		 lh    $9,0x00($24)
39166		 sll   $8,$8,2
39167		 addu  $8,$8,$21
39168		 lw    $14,0x20($8)
39169		 addiu $25,$14,2
39170		 sw    $25,0x20($8)
39171		 lw    $25,0x80($21)
39172		 sw    $15,m68k_ICount
39173		 sw    $9,0x44($29)
39174		 sw    $24,0x40($29)
39175		 or    $4,$0,$14
39176		 jalr  $25
39177		 sw    $23,0x4C($21)    	 # Delay slot
39178		 lw    $24,0x40($29)
39179		 lw    $9,0x44($29)
39180		 lw    $15,m68k_ICount
39181		 seh   $2,$2
39182		 or   $10,$9,$2
39183		 sh    $10,0x00($24)
39184		 and   $16,$0,$0        	 # Clear Carry
39185		 and   $17,$0,$0        	 # Clear Overflow
39186		 slt   $19,$10,$0        	 # Set Sign
39187		 sltiu $18,$10,1         	 # Set Zero
39188		 addiu $15,$15,-8
39189		 bgez  $15,3f
39190		 lhu   $24,0x00($23)    	 # Delay slot
39191		 j     MainExit
39192	3:
39193		 sll   $7,$24,2         	 # Delay slot
39194		 addu  $7,$7,$30
39195		 lw    $7,0x00($7)
39196		 jr    $7
39197		 nop                    	 # Delay slot
39198
39199OP0_8060:				#:
39200		 addiu $23,$23,2
39201
39202		 andi  $8,$24,0x07
39203		 srl   $24,$24,7
39204		 andi  $24,$24,0x1C
39205		 addu  $24,$24,$21
39206		 lh    $9,0x00($24)
39207		 sll   $8,$8,2
39208		 addu  $8,$8,$21
39209		 lw    $14,0x20($8)
39210		 addiu $14,$14,-2
39211		 sw    $14,0x20($8)
39212		 lw    $25,0x80($21)
39213		 sw    $15,m68k_ICount
39214		 sw    $9,0x44($29)
39215		 sw    $24,0x40($29)
39216		 or    $4,$0,$14
39217		 jalr  $25
39218		 sw    $23,0x4C($21)    	 # Delay slot
39219		 lw    $24,0x40($29)
39220		 lw    $9,0x44($29)
39221		 lw    $15,m68k_ICount
39222		 seh   $2,$2
39223		 or   $10,$9,$2
39224		 sh    $10,0x00($24)
39225		 and   $16,$0,$0        	 # Clear Carry
39226		 and   $17,$0,$0        	 # Clear Overflow
39227		 slt   $19,$10,$0        	 # Set Sign
39228		 sltiu $18,$10,1         	 # Set Zero
39229		 addiu $15,$15,-10
39230		 bgez  $15,3f
39231		 lhu   $24,0x00($23)    	 # Delay slot
39232		 j     MainExit
39233	3:
39234		 sll   $7,$24,2         	 # Delay slot
39235		 addu  $7,$7,$30
39236		 lw    $7,0x00($7)
39237		 jr    $7
39238		 nop                    	 # Delay slot
39239
39240OP0_8068:				#:
39241		 addiu $23,$23,2
39242
39243		 andi  $8,$24,0x07
39244		 srl   $24,$24,7
39245		 andi  $24,$24,0x1C
39246		 addu  $24,$24,$21
39247		 lh    $9,0x00($24)
39248		 lh    $7,0x00($23)
39249		 sll   $8,$8,2
39250		 addu  $8,$8,$21
39251		 lw    $14,0x20($8)
39252		 addiu $23,$23,2
39253		 addu  $14,$14,$7
39254		 lw    $25,0x80($21)
39255		 sw    $15,m68k_ICount
39256		 sw    $9,0x44($29)
39257		 sw    $24,0x40($29)
39258		 or    $4,$0,$14
39259		 jalr  $25
39260		 sw    $23,0x4C($21)    	 # Delay slot
39261		 lw    $24,0x40($29)
39262		 lw    $9,0x44($29)
39263		 lw    $15,m68k_ICount
39264		 seh   $2,$2
39265		 or   $10,$9,$2
39266		 sh    $10,0x00($24)
39267		 and   $16,$0,$0        	 # Clear Carry
39268		 and   $17,$0,$0        	 # Clear Overflow
39269		 slt   $19,$10,$0        	 # Set Sign
39270		 sltiu $18,$10,1         	 # Set Zero
39271		 addiu $15,$15,-12
39272		 bgez  $15,3f
39273		 lhu   $24,0x00($23)    	 # Delay slot
39274		 j     MainExit
39275	3:
39276		 sll   $7,$24,2         	 # Delay slot
39277		 addu  $7,$7,$30
39278		 lw    $7,0x00($7)
39279		 jr    $7
39280		 nop                    	 # Delay slot
39281
39282OP0_8070:				#:
39283		 addiu $23,$23,2
39284
39285		 andi  $8,$24,0x07
39286		 srl   $24,$24,7
39287		 andi  $24,$24,0x1C
39288		 addu  $24,$24,$21
39289		 lh    $9,0x00($24)
39290		 sll   $8,$8,2
39291		 addu  $8,$8,$21
39292		 lw    $14,0x20($8)
39293		 lhu   $7,0x00($23)
39294		 addiu $23,$23,2
39295		 seb   $6,$7
39296		 or    $25,$0,$7
39297		 srl   $7,$7,12
39298		 andi  $25,$25,0x0800
39299		 sll   $7,$7,2
39300		 addu  $7,$7,$21
39301		 bne   $25,$0,0f
39302		 lw    $25,0x00($7)      	 # Delay slot
39303		 seh   $25,$25
39304	0:
39305		 addu  $25,$14,$25
39306		 addu  $14,$25,$6
39307		 lw    $25,0x80($21)
39308		 sw    $15,m68k_ICount
39309		 sw    $9,0x44($29)
39310		 sw    $24,0x40($29)
39311		 or    $4,$0,$14
39312		 jalr  $25
39313		 sw    $23,0x4C($21)    	 # Delay slot
39314		 lw    $24,0x40($29)
39315		 lw    $9,0x44($29)
39316		 lw    $15,m68k_ICount
39317		 seh   $2,$2
39318		 or   $10,$9,$2
39319		 sh    $10,0x00($24)
39320		 and   $16,$0,$0        	 # Clear Carry
39321		 and   $17,$0,$0        	 # Clear Overflow
39322		 slt   $19,$10,$0        	 # Set Sign
39323		 sltiu $18,$10,1         	 # Set Zero
39324		 addiu $15,$15,-14
39325		 bgez  $15,3f
39326		 lhu   $24,0x00($23)    	 # Delay slot
39327		 j     MainExit
39328	3:
39329		 sll   $7,$24,2         	 # Delay slot
39330		 addu  $7,$7,$30
39331		 lw    $7,0x00($7)
39332		 jr    $7
39333		 nop                    	 # Delay slot
39334
39335OP0_8078:				#:
39336		 addiu $23,$23,2
39337
39338		 srl   $24,$24,7
39339		 andi  $24,$24,0x1C
39340		 addu  $24,$24,$21
39341		 lh    $9,0x00($24)
39342		 lh    $14,0x00($23)
39343		 addiu $23,$23,2
39344		 lw    $25,0x80($21)
39345		 sw    $15,m68k_ICount
39346		 sw    $9,0x44($29)
39347		 sw    $24,0x40($29)
39348		 or    $4,$0,$14
39349		 jalr  $25
39350		 sw    $23,0x4C($21)    	 # Delay slot
39351		 lw    $24,0x40($29)
39352		 lw    $9,0x44($29)
39353		 lw    $15,m68k_ICount
39354		 seh   $2,$2
39355		 or   $10,$9,$2
39356		 sh    $10,0x00($24)
39357		 and   $16,$0,$0        	 # Clear Carry
39358		 and   $17,$0,$0        	 # Clear Overflow
39359		 slt   $19,$10,$0        	 # Set Sign
39360		 sltiu $18,$10,1         	 # Set Zero
39361		 addiu $15,$15,-12
39362		 bgez  $15,3f
39363		 lhu   $24,0x00($23)    	 # Delay slot
39364		 j     MainExit
39365	3:
39366		 sll   $7,$24,2         	 # Delay slot
39367		 addu  $7,$7,$30
39368		 lw    $7,0x00($7)
39369		 jr    $7
39370		 nop                    	 # Delay slot
39371
39372OP0_8079:				#:
39373		 addiu $23,$23,2
39374
39375		 srl   $24,$24,7
39376		 andi  $24,$24,0x1C
39377		 addu  $24,$24,$21
39378		 lh    $9,0x00($24)
39379		 lhu   $14,0x00($23)
39380		 lhu   $25,0x02($23)
39381		 sll   $14,$14,16
39382		 or    $14,$14,$25
39383		 addiu $23,$23,4
39384		 lw    $25,0x80($21)
39385		 sw    $15,m68k_ICount
39386		 sw    $9,0x44($29)
39387		 sw    $24,0x40($29)
39388		 or    $4,$0,$14
39389		 jalr  $25
39390		 sw    $23,0x4C($21)    	 # Delay slot
39391		 lw    $24,0x40($29)
39392		 lw    $9,0x44($29)
39393		 lw    $15,m68k_ICount
39394		 seh   $2,$2
39395		 or   $10,$9,$2
39396		 sh    $10,0x00($24)
39397		 and   $16,$0,$0        	 # Clear Carry
39398		 and   $17,$0,$0        	 # Clear Overflow
39399		 slt   $19,$10,$0        	 # Set Sign
39400		 sltiu $18,$10,1         	 # Set Zero
39401		 addiu $15,$15,-16
39402		 bgez  $15,3f
39403		 lhu   $24,0x00($23)    	 # Delay slot
39404		 j     MainExit
39405	3:
39406		 sll   $7,$24,2         	 # Delay slot
39407		 addu  $7,$7,$30
39408		 lw    $7,0x00($7)
39409		 jr    $7
39410		 nop                    	 # Delay slot
39411
39412OP0_807a:				#:
39413		 addiu $23,$23,2
39414
39415		 srl   $24,$24,7
39416		 andi  $24,$24,0x1C
39417		 addu  $24,$24,$21
39418		 lh    $9,0x00($24)
39419		 lh    $7,0x00($23)
39420		 subu  $25,$23,$22
39421		 addu  $14,$25,$7       	 # Add Offset to PC
39422		 addiu $23,$23,2
39423		 lw    $25,0x9C($21)
39424		 sw    $15,m68k_ICount
39425		 sw    $9,0x44($29)
39426		 sw    $24,0x40($29)
39427		 or    $4,$0,$14
39428		 jalr  $25
39429		 sw    $23,0x4C($21)    	 # Delay slot
39430		 lw    $24,0x40($29)
39431		 lw    $9,0x44($29)
39432		 lw    $15,m68k_ICount
39433		 seh   $2,$2
39434		 or   $10,$9,$2
39435		 sh    $10,0x00($24)
39436		 and   $16,$0,$0        	 # Clear Carry
39437		 and   $17,$0,$0        	 # Clear Overflow
39438		 slt   $19,$10,$0        	 # Set Sign
39439		 sltiu $18,$10,1         	 # Set Zero
39440		 addiu $15,$15,-12
39441		 bgez  $15,3f
39442		 lhu   $24,0x00($23)    	 # Delay slot
39443		 j     MainExit
39444	3:
39445		 sll   $7,$24,2         	 # Delay slot
39446		 addu  $7,$7,$30
39447		 lw    $7,0x00($7)
39448		 jr    $7
39449		 nop                    	 # Delay slot
39450
39451OP0_807b:				#:
39452		 addiu $23,$23,2
39453
39454		 srl   $24,$24,7
39455		 andi  $24,$24,0x1C
39456		 addu  $24,$24,$21
39457		 lh    $9,0x00($24)
39458		 subu  $14,$23,$22       	 # Get PC
39459		 lhu   $7,0x00($23)
39460		 addiu $23,$23,2
39461		 seb   $6,$7
39462		 or    $25,$0,$7
39463		 srl   $7,$7,12
39464		 andi  $25,$25,0x0800
39465		 sll   $7,$7,2
39466		 addu  $7,$7,$21
39467		 bne   $25,$0,0f
39468		 lw    $25,0x00($7)      	 # Delay slot
39469		 seh   $25,$25
39470	0:
39471		 addu  $25,$14,$25
39472		 addu  $14,$25,$6
39473		 lw    $25,0x9C($21)
39474		 sw    $15,m68k_ICount
39475		 sw    $9,0x44($29)
39476		 sw    $24,0x40($29)
39477		 or    $4,$0,$14
39478		 jalr  $25
39479		 sw    $23,0x4C($21)    	 # Delay slot
39480		 lw    $24,0x40($29)
39481		 lw    $9,0x44($29)
39482		 lw    $15,m68k_ICount
39483		 seh   $2,$2
39484		 or   $10,$9,$2
39485		 sh    $10,0x00($24)
39486		 and   $16,$0,$0        	 # Clear Carry
39487		 and   $17,$0,$0        	 # Clear Overflow
39488		 slt   $19,$10,$0        	 # Set Sign
39489		 sltiu $18,$10,1         	 # Set Zero
39490		 addiu $15,$15,-14
39491		 bgez  $15,3f
39492		 lhu   $24,0x00($23)    	 # Delay slot
39493		 j     MainExit
39494	3:
39495		 sll   $7,$24,2         	 # Delay slot
39496		 addu  $7,$7,$30
39497		 lw    $7,0x00($7)
39498		 jr    $7
39499		 nop                    	 # Delay slot
39500
39501OP0_807c:				#:
39502		 addiu $23,$23,2
39503
39504		 srl   $24,$24,7
39505		 andi  $24,$24,0x1C
39506		 addu  $24,$24,$21
39507		 lh    $9,0x00($24)
39508		 lh    $2,0x00($23)
39509		 addiu $23,$23,2
39510		 or   $10,$9,$2
39511		 sh    $10,0x00($24)
39512		 and   $16,$0,$0        	 # Clear Carry
39513		 and   $17,$0,$0        	 # Clear Overflow
39514		 slt   $19,$10,$0        	 # Set Sign
39515		 sltiu $18,$10,1         	 # Set Zero
39516		 addiu $15,$15,-4
39517		 bgez  $15,3f
39518		 lhu   $24,0x00($23)    	 # Delay slot
39519		 j     MainExit
39520	3:
39521		 sll   $7,$24,2         	 # Delay slot
39522		 addu  $7,$7,$30
39523		 lw    $7,0x00($7)
39524		 jr    $7
39525		 nop                    	 # Delay slot
39526
39527OP0_8080:				#:
39528		 addiu $23,$23,2
39529
39530		 andi  $8,$24,0x07
39531		 srl   $24,$24,7
39532		 andi  $24,$24,0x1C
39533		 addu  $24,$24,$21
39534		 lw    $9,0x00($24)
39535		 sll   $8,$8,2
39536		 addu  $8,$8,$21
39537		 lw    $2,0x00($8)
39538		 or   $10,$9,$2
39539		 sw    $10,0x00($24)
39540		 and   $16,$0,$0        	 # Clear Carry
39541		 and   $17,$0,$0        	 # Clear Overflow
39542		 slt   $19,$10,$0        	 # Set Sign
39543		 sltiu $18,$10,1         	 # Set Zero
39544		 addiu $15,$15,-8
39545		 bgez  $15,3f
39546		 lhu   $24,0x00($23)    	 # Delay slot
39547		 j     MainExit
39548	3:
39549		 sll   $7,$24,2         	 # Delay slot
39550		 addu  $7,$7,$30
39551		 lw    $7,0x00($7)
39552		 jr    $7
39553		 nop                    	 # Delay slot
39554
39555OP0_8090:				#:
39556		 addiu $23,$23,2
39557
39558		 andi  $8,$24,0x07
39559		 srl   $24,$24,7
39560		 andi  $24,$24,0x1C
39561		 addu  $24,$24,$21
39562		 lw    $9,0x00($24)
39563		 sll   $8,$8,2
39564		 addu  $8,$8,$21
39565		 lw    $14,0x20($8)
39566		 lw    $25,0x84($21)
39567		 sw    $15,m68k_ICount
39568		 sw    $9,0x44($29)
39569		 sw    $24,0x40($29)
39570		 or    $4,$0,$14
39571		 jalr  $25
39572		 sw    $23,0x4C($21)    	 # Delay slot
39573		 lw    $24,0x40($29)
39574		 lw    $9,0x44($29)
39575		 lw    $15,m68k_ICount
39576		 or   $10,$9,$2
39577		 sw    $10,0x00($24)
39578		 and   $16,$0,$0        	 # Clear Carry
39579		 and   $17,$0,$0        	 # Clear Overflow
39580		 slt   $19,$10,$0        	 # Set Sign
39581		 sltiu $18,$10,1         	 # Set Zero
39582		 addiu $15,$15,-14
39583		 bgez  $15,3f
39584		 lhu   $24,0x00($23)    	 # Delay slot
39585		 j     MainExit
39586	3:
39587		 sll   $7,$24,2         	 # Delay slot
39588		 addu  $7,$7,$30
39589		 lw    $7,0x00($7)
39590		 jr    $7
39591		 nop                    	 # Delay slot
39592
39593OP0_8098:				#:
39594		 addiu $23,$23,2
39595
39596		 andi  $8,$24,0x07
39597		 srl   $24,$24,7
39598		 andi  $24,$24,0x1C
39599		 addu  $24,$24,$21
39600		 lw    $9,0x00($24)
39601		 sll   $8,$8,2
39602		 addu  $8,$8,$21
39603		 lw    $14,0x20($8)
39604		 addiu $25,$14,4
39605		 sw    $25,0x20($8)
39606		 lw    $25,0x84($21)
39607		 sw    $15,m68k_ICount
39608		 sw    $9,0x44($29)
39609		 sw    $24,0x40($29)
39610		 or    $4,$0,$14
39611		 jalr  $25
39612		 sw    $23,0x4C($21)    	 # Delay slot
39613		 lw    $24,0x40($29)
39614		 lw    $9,0x44($29)
39615		 lw    $15,m68k_ICount
39616		 or   $10,$9,$2
39617		 sw    $10,0x00($24)
39618		 and   $16,$0,$0        	 # Clear Carry
39619		 and   $17,$0,$0        	 # Clear Overflow
39620		 slt   $19,$10,$0        	 # Set Sign
39621		 sltiu $18,$10,1         	 # Set Zero
39622		 addiu $15,$15,-14
39623		 bgez  $15,3f
39624		 lhu   $24,0x00($23)    	 # Delay slot
39625		 j     MainExit
39626	3:
39627		 sll   $7,$24,2         	 # Delay slot
39628		 addu  $7,$7,$30
39629		 lw    $7,0x00($7)
39630		 jr    $7
39631		 nop                    	 # Delay slot
39632
39633OP0_80a0:				#:
39634		 addiu $23,$23,2
39635
39636		 andi  $8,$24,0x07
39637		 srl   $24,$24,7
39638		 andi  $24,$24,0x1C
39639		 addu  $24,$24,$21
39640		 lw    $9,0x00($24)
39641		 sll   $8,$8,2
39642		 addu  $8,$8,$21
39643		 lw    $14,0x20($8)
39644		 addiu $14,$14,-4
39645		 sw    $14,0x20($8)
39646		 lw    $25,0x84($21)
39647		 sw    $15,m68k_ICount
39648		 sw    $9,0x44($29)
39649		 sw    $24,0x40($29)
39650		 or    $4,$0,$14
39651		 jalr  $25
39652		 sw    $23,0x4C($21)    	 # Delay slot
39653		 lw    $24,0x40($29)
39654		 lw    $9,0x44($29)
39655		 lw    $15,m68k_ICount
39656		 or   $10,$9,$2
39657		 sw    $10,0x00($24)
39658		 and   $16,$0,$0        	 # Clear Carry
39659		 and   $17,$0,$0        	 # Clear Overflow
39660		 slt   $19,$10,$0        	 # Set Sign
39661		 sltiu $18,$10,1         	 # Set Zero
39662		 addiu $15,$15,-16
39663		 bgez  $15,3f
39664		 lhu   $24,0x00($23)    	 # Delay slot
39665		 j     MainExit
39666	3:
39667		 sll   $7,$24,2         	 # Delay slot
39668		 addu  $7,$7,$30
39669		 lw    $7,0x00($7)
39670		 jr    $7
39671		 nop                    	 # Delay slot
39672
39673OP0_80a8:				#:
39674		 addiu $23,$23,2
39675
39676		 andi  $8,$24,0x07
39677		 srl   $24,$24,7
39678		 andi  $24,$24,0x1C
39679		 addu  $24,$24,$21
39680		 lw    $9,0x00($24)
39681		 lh    $7,0x00($23)
39682		 sll   $8,$8,2
39683		 addu  $8,$8,$21
39684		 lw    $14,0x20($8)
39685		 addiu $23,$23,2
39686		 addu  $14,$14,$7
39687		 lw    $25,0x84($21)
39688		 sw    $15,m68k_ICount
39689		 sw    $9,0x44($29)
39690		 sw    $24,0x40($29)
39691		 or    $4,$0,$14
39692		 jalr  $25
39693		 sw    $23,0x4C($21)    	 # Delay slot
39694		 lw    $24,0x40($29)
39695		 lw    $9,0x44($29)
39696		 lw    $15,m68k_ICount
39697		 or   $10,$9,$2
39698		 sw    $10,0x00($24)
39699		 and   $16,$0,$0        	 # Clear Carry
39700		 and   $17,$0,$0        	 # Clear Overflow
39701		 slt   $19,$10,$0        	 # Set Sign
39702		 sltiu $18,$10,1         	 # Set Zero
39703		 addiu $15,$15,-18
39704		 bgez  $15,3f
39705		 lhu   $24,0x00($23)    	 # Delay slot
39706		 j     MainExit
39707	3:
39708		 sll   $7,$24,2         	 # Delay slot
39709		 addu  $7,$7,$30
39710		 lw    $7,0x00($7)
39711		 jr    $7
39712		 nop                    	 # Delay slot
39713
39714OP0_80b0:				#:
39715		 addiu $23,$23,2
39716
39717		 andi  $8,$24,0x07
39718		 srl   $24,$24,7
39719		 andi  $24,$24,0x1C
39720		 addu  $24,$24,$21
39721		 lw    $9,0x00($24)
39722		 sll   $8,$8,2
39723		 addu  $8,$8,$21
39724		 lw    $14,0x20($8)
39725		 lhu   $7,0x00($23)
39726		 addiu $23,$23,2
39727		 seb   $6,$7
39728		 or    $25,$0,$7
39729		 srl   $7,$7,12
39730		 andi  $25,$25,0x0800
39731		 sll   $7,$7,2
39732		 addu  $7,$7,$21
39733		 bne   $25,$0,0f
39734		 lw    $25,0x00($7)      	 # Delay slot
39735		 seh   $25,$25
39736	0:
39737		 addu  $25,$14,$25
39738		 addu  $14,$25,$6
39739		 lw    $25,0x84($21)
39740		 sw    $15,m68k_ICount
39741		 sw    $9,0x44($29)
39742		 sw    $24,0x40($29)
39743		 or    $4,$0,$14
39744		 jalr  $25
39745		 sw    $23,0x4C($21)    	 # Delay slot
39746		 lw    $24,0x40($29)
39747		 lw    $9,0x44($29)
39748		 lw    $15,m68k_ICount
39749		 or   $10,$9,$2
39750		 sw    $10,0x00($24)
39751		 and   $16,$0,$0        	 # Clear Carry
39752		 and   $17,$0,$0        	 # Clear Overflow
39753		 slt   $19,$10,$0        	 # Set Sign
39754		 sltiu $18,$10,1         	 # Set Zero
39755		 addiu $15,$15,-20
39756		 bgez  $15,3f
39757		 lhu   $24,0x00($23)    	 # Delay slot
39758		 j     MainExit
39759	3:
39760		 sll   $7,$24,2         	 # Delay slot
39761		 addu  $7,$7,$30
39762		 lw    $7,0x00($7)
39763		 jr    $7
39764		 nop                    	 # Delay slot
39765
39766OP0_80b8:				#:
39767		 addiu $23,$23,2
39768
39769		 srl   $24,$24,7
39770		 andi  $24,$24,0x1C
39771		 addu  $24,$24,$21
39772		 lw    $9,0x00($24)
39773		 lh    $14,0x00($23)
39774		 addiu $23,$23,2
39775		 lw    $25,0x84($21)
39776		 sw    $15,m68k_ICount
39777		 sw    $9,0x44($29)
39778		 sw    $24,0x40($29)
39779		 or    $4,$0,$14
39780		 jalr  $25
39781		 sw    $23,0x4C($21)    	 # Delay slot
39782		 lw    $24,0x40($29)
39783		 lw    $9,0x44($29)
39784		 lw    $15,m68k_ICount
39785		 or   $10,$9,$2
39786		 sw    $10,0x00($24)
39787		 and   $16,$0,$0        	 # Clear Carry
39788		 and   $17,$0,$0        	 # Clear Overflow
39789		 slt   $19,$10,$0        	 # Set Sign
39790		 sltiu $18,$10,1         	 # Set Zero
39791		 addiu $15,$15,-18
39792		 bgez  $15,3f
39793		 lhu   $24,0x00($23)    	 # Delay slot
39794		 j     MainExit
39795	3:
39796		 sll   $7,$24,2         	 # Delay slot
39797		 addu  $7,$7,$30
39798		 lw    $7,0x00($7)
39799		 jr    $7
39800		 nop                    	 # Delay slot
39801
39802OP0_80b9:				#:
39803		 addiu $23,$23,2
39804
39805		 srl   $24,$24,7
39806		 andi  $24,$24,0x1C
39807		 addu  $24,$24,$21
39808		 lw    $9,0x00($24)
39809		 lhu   $14,0x00($23)
39810		 lhu   $25,0x02($23)
39811		 sll   $14,$14,16
39812		 or    $14,$14,$25
39813		 addiu $23,$23,4
39814		 lw    $25,0x84($21)
39815		 sw    $15,m68k_ICount
39816		 sw    $9,0x44($29)
39817		 sw    $24,0x40($29)
39818		 or    $4,$0,$14
39819		 jalr  $25
39820		 sw    $23,0x4C($21)    	 # Delay slot
39821		 lw    $24,0x40($29)
39822		 lw    $9,0x44($29)
39823		 lw    $15,m68k_ICount
39824		 or   $10,$9,$2
39825		 sw    $10,0x00($24)
39826		 and   $16,$0,$0        	 # Clear Carry
39827		 and   $17,$0,$0        	 # Clear Overflow
39828		 slt   $19,$10,$0        	 # Set Sign
39829		 sltiu $18,$10,1         	 # Set Zero
39830		 addiu $15,$15,-22
39831		 bgez  $15,3f
39832		 lhu   $24,0x00($23)    	 # Delay slot
39833		 j     MainExit
39834	3:
39835		 sll   $7,$24,2         	 # Delay slot
39836		 addu  $7,$7,$30
39837		 lw    $7,0x00($7)
39838		 jr    $7
39839		 nop                    	 # Delay slot
39840
39841OP0_80ba:				#:
39842		 addiu $23,$23,2
39843
39844		 srl   $24,$24,7
39845		 andi  $24,$24,0x1C
39846		 addu  $24,$24,$21
39847		 lw    $9,0x00($24)
39848		 lh    $7,0x00($23)
39849		 subu  $25,$23,$22
39850		 addu  $14,$25,$7       	 # Add Offset to PC
39851		 addiu $23,$23,2
39852		 lw    $25,0xA0($21)
39853		 sw    $15,m68k_ICount
39854		 sw    $9,0x44($29)
39855		 sw    $24,0x40($29)
39856		 or    $4,$0,$14
39857		 jalr  $25
39858		 sw    $23,0x4C($21)    	 # Delay slot
39859		 lw    $24,0x40($29)
39860		 lw    $9,0x44($29)
39861		 lw    $15,m68k_ICount
39862		 or   $10,$9,$2
39863		 sw    $10,0x00($24)
39864		 and   $16,$0,$0        	 # Clear Carry
39865		 and   $17,$0,$0        	 # Clear Overflow
39866		 slt   $19,$10,$0        	 # Set Sign
39867		 sltiu $18,$10,1         	 # Set Zero
39868		 addiu $15,$15,-18
39869		 bgez  $15,3f
39870		 lhu   $24,0x00($23)    	 # Delay slot
39871		 j     MainExit
39872	3:
39873		 sll   $7,$24,2         	 # Delay slot
39874		 addu  $7,$7,$30
39875		 lw    $7,0x00($7)
39876		 jr    $7
39877		 nop                    	 # Delay slot
39878
39879OP0_80bb:				#:
39880		 addiu $23,$23,2
39881
39882		 srl   $24,$24,7
39883		 andi  $24,$24,0x1C
39884		 addu  $24,$24,$21
39885		 lw    $9,0x00($24)
39886		 subu  $14,$23,$22       	 # Get PC
39887		 lhu   $7,0x00($23)
39888		 addiu $23,$23,2
39889		 seb   $6,$7
39890		 or    $25,$0,$7
39891		 srl   $7,$7,12
39892		 andi  $25,$25,0x0800
39893		 sll   $7,$7,2
39894		 addu  $7,$7,$21
39895		 bne   $25,$0,0f
39896		 lw    $25,0x00($7)      	 # Delay slot
39897		 seh   $25,$25
39898	0:
39899		 addu  $25,$14,$25
39900		 addu  $14,$25,$6
39901		 lw    $25,0xA0($21)
39902		 sw    $15,m68k_ICount
39903		 sw    $9,0x44($29)
39904		 sw    $24,0x40($29)
39905		 or    $4,$0,$14
39906		 jalr  $25
39907		 sw    $23,0x4C($21)    	 # Delay slot
39908		 lw    $24,0x40($29)
39909		 lw    $9,0x44($29)
39910		 lw    $15,m68k_ICount
39911		 or   $10,$9,$2
39912		 sw    $10,0x00($24)
39913		 and   $16,$0,$0        	 # Clear Carry
39914		 and   $17,$0,$0        	 # Clear Overflow
39915		 slt   $19,$10,$0        	 # Set Sign
39916		 sltiu $18,$10,1         	 # Set Zero
39917		 addiu $15,$15,-20
39918		 bgez  $15,3f
39919		 lhu   $24,0x00($23)    	 # Delay slot
39920		 j     MainExit
39921	3:
39922		 sll   $7,$24,2         	 # Delay slot
39923		 addu  $7,$7,$30
39924		 lw    $7,0x00($7)
39925		 jr    $7
39926		 nop                    	 # Delay slot
39927
39928OP0_80bc:				#:
39929		 addiu $23,$23,2
39930
39931		 srl   $24,$24,7
39932		 andi  $24,$24,0x1C
39933		 addu  $24,$24,$21
39934		 lw    $9,0x00($24)
39935		 lhu   $2,0x00($23)
39936		 lhu   $25,0x02($23)
39937		 sll   $2,$2,16
39938		 or    $2,$2,$25
39939		 addiu $23,$23,4
39940		 or   $10,$9,$2
39941		 sw    $10,0x00($24)
39942		 and   $16,$0,$0        	 # Clear Carry
39943		 and   $17,$0,$0        	 # Clear Overflow
39944		 slt   $19,$10,$0        	 # Set Sign
39945		 sltiu $18,$10,1         	 # Set Zero
39946		 addiu $15,$15,-6
39947		 bgez  $15,3f
39948		 lhu   $24,0x00($23)    	 # Delay slot
39949		 j     MainExit
39950	3:
39951		 sll   $7,$24,2         	 # Delay slot
39952		 addu  $7,$7,$30
39953		 lw    $7,0x00($7)
39954		 jr    $7
39955		 nop                    	 # Delay slot
39956
39957OP0_8110:				#:
39958		 addiu $23,$23,2
39959
39960		 andi  $8,$24,0x07
39961		 srl   $24,$24,7
39962		 andi  $24,$24,0x1C
39963		 addu  $24,$24,$21
39964		 lb    $9,0x00($24)
39965		 sll   $8,$8,2
39966		 addu  $8,$8,$21
39967		 lw    $14,0x20($8)
39968		 lw    $25,0x7C($21)
39969		 sw    $15,m68k_ICount
39970		 sw    $9,0x44($29)
39971		 sw    $14,0x40($29)
39972		 sw    $24,0x3C($29)
39973		 or    $4,$0,$14
39974		 jalr  $25
39975		 sw    $23,0x4C($21)    	 # Delay slot
39976		 lw    $24,0x3C($29)
39977		 lw    $14,0x40($29)
39978		 lw    $9,0x44($29)
39979		 lw    $15,m68k_ICount
39980		 seb   $10,$2
39981		 or   $2,$10,$9
39982		 and   $16,$0,$0        	 # Clear Carry
39983		 and   $17,$0,$0        	 # Clear Overflow
39984		 slt   $19,$2,$0        	 # Set Sign
39985		 sltiu $18,$2,1         	 # Set Zero
39986		 lw    $25,0x88($21)
39987		 sw    $15,m68k_ICount
39988		 sw    $9,0x44($29)
39989		 sw    $14,0x40($29)
39990		 sw    $24,0x3C($29)
39991		 or    $5,$0,$2
39992		 or    $4,$0,$14
39993		 jalr  $25
39994		 sw    $23,0x4C($21)    	 # Delay slot
39995		 lw    $24,0x3C($29)
39996		 lw    $14,0x40($29)
39997		 lw    $9,0x44($29)
39998		 lw    $15,m68k_ICount
39999		 addiu $15,$15,-12
40000		 bgez  $15,3f
40001		 lhu   $24,0x00($23)    	 # Delay slot
40002		 j     MainExit
40003	3:
40004		 sll   $7,$24,2         	 # Delay slot
40005		 addu  $7,$7,$30
40006		 lw    $7,0x00($7)
40007		 jr    $7
40008		 nop                    	 # Delay slot
40009
40010OP0_8118:				#:
40011		 addiu $23,$23,2
40012
40013		 andi  $8,$24,0x07
40014		 srl   $24,$24,7
40015		 andi  $24,$24,0x1C
40016		 addu  $24,$24,$21
40017		 lb    $9,0x00($24)
40018		 sll   $8,$8,2
40019		 addu  $8,$8,$21
40020		 lw    $14,0x20($8)
40021		 addiu $25,$14,1
40022		 sw    $25,0x20($8)
40023		 lw    $25,0x7C($21)
40024		 sw    $15,m68k_ICount
40025		 sw    $9,0x44($29)
40026		 sw    $14,0x40($29)
40027		 sw    $24,0x3C($29)
40028		 or    $4,$0,$14
40029		 jalr  $25
40030		 sw    $23,0x4C($21)    	 # Delay slot
40031		 lw    $24,0x3C($29)
40032		 lw    $14,0x40($29)
40033		 lw    $9,0x44($29)
40034		 lw    $15,m68k_ICount
40035		 seb   $10,$2
40036		 or   $2,$10,$9
40037		 and   $16,$0,$0        	 # Clear Carry
40038		 and   $17,$0,$0        	 # Clear Overflow
40039		 slt   $19,$2,$0        	 # Set Sign
40040		 sltiu $18,$2,1         	 # Set Zero
40041		 lw    $25,0x88($21)
40042		 sw    $15,m68k_ICount
40043		 sw    $9,0x44($29)
40044		 sw    $14,0x40($29)
40045		 sw    $24,0x3C($29)
40046		 or    $5,$0,$2
40047		 or    $4,$0,$14
40048		 jalr  $25
40049		 sw    $23,0x4C($21)    	 # Delay slot
40050		 lw    $24,0x3C($29)
40051		 lw    $14,0x40($29)
40052		 lw    $9,0x44($29)
40053		 lw    $15,m68k_ICount
40054		 addiu $15,$15,-12
40055		 bgez  $15,3f
40056		 lhu   $24,0x00($23)    	 # Delay slot
40057		 j     MainExit
40058	3:
40059		 sll   $7,$24,2         	 # Delay slot
40060		 addu  $7,$7,$30
40061		 lw    $7,0x00($7)
40062		 jr    $7
40063		 nop                    	 # Delay slot
40064
40065OP0_811f:				#:
40066		 addiu $23,$23,2
40067
40068		 srl   $24,$24,7
40069		 andi  $24,$24,0x1C
40070		 addu  $24,$24,$21
40071		 lb    $9,0x00($24)
40072		 lw    $14,0x3C($21)    	 # Get A7
40073		 addiu $25,$14,2
40074		 sw    $25,0x3C($21)
40075		 lw    $25,0x7C($21)
40076		 sw    $15,m68k_ICount
40077		 sw    $9,0x44($29)
40078		 sw    $14,0x40($29)
40079		 sw    $24,0x3C($29)
40080		 or    $4,$0,$14
40081		 jalr  $25
40082		 sw    $23,0x4C($21)    	 # Delay slot
40083		 lw    $24,0x3C($29)
40084		 lw    $14,0x40($29)
40085		 lw    $9,0x44($29)
40086		 lw    $15,m68k_ICount
40087		 seb   $10,$2
40088		 or   $2,$10,$9
40089		 and   $16,$0,$0        	 # Clear Carry
40090		 and   $17,$0,$0        	 # Clear Overflow
40091		 slt   $19,$2,$0        	 # Set Sign
40092		 sltiu $18,$2,1         	 # Set Zero
40093		 lw    $25,0x88($21)
40094		 sw    $15,m68k_ICount
40095		 sw    $9,0x44($29)
40096		 sw    $14,0x40($29)
40097		 sw    $24,0x3C($29)
40098		 or    $5,$0,$2
40099		 or    $4,$0,$14
40100		 jalr  $25
40101		 sw    $23,0x4C($21)    	 # Delay slot
40102		 lw    $24,0x3C($29)
40103		 lw    $14,0x40($29)
40104		 lw    $9,0x44($29)
40105		 lw    $15,m68k_ICount
40106		 addiu $15,$15,-12
40107		 bgez  $15,3f
40108		 lhu   $24,0x00($23)    	 # Delay slot
40109		 j     MainExit
40110	3:
40111		 sll   $7,$24,2         	 # Delay slot
40112		 addu  $7,$7,$30
40113		 lw    $7,0x00($7)
40114		 jr    $7
40115		 nop                    	 # Delay slot
40116
40117OP0_8120:				#:
40118		 addiu $23,$23,2
40119
40120		 andi  $8,$24,0x07
40121		 srl   $24,$24,7
40122		 andi  $24,$24,0x1C
40123		 addu  $24,$24,$21
40124		 lb    $9,0x00($24)
40125		 sll   $8,$8,2
40126		 addu  $8,$8,$21
40127		 lw    $14,0x20($8)
40128		 addiu $14,$14,-1
40129		 sw    $14,0x20($8)
40130		 lw    $25,0x7C($21)
40131		 sw    $15,m68k_ICount
40132		 sw    $9,0x44($29)
40133		 sw    $14,0x40($29)
40134		 sw    $24,0x3C($29)
40135		 or    $4,$0,$14
40136		 jalr  $25
40137		 sw    $23,0x4C($21)    	 # Delay slot
40138		 lw    $24,0x3C($29)
40139		 lw    $14,0x40($29)
40140		 lw    $9,0x44($29)
40141		 lw    $15,m68k_ICount
40142		 seb   $10,$2
40143		 or   $2,$10,$9
40144		 and   $16,$0,$0        	 # Clear Carry
40145		 and   $17,$0,$0        	 # Clear Overflow
40146		 slt   $19,$2,$0        	 # Set Sign
40147		 sltiu $18,$2,1         	 # Set Zero
40148		 lw    $25,0x88($21)
40149		 sw    $15,m68k_ICount
40150		 sw    $9,0x44($29)
40151		 sw    $14,0x40($29)
40152		 sw    $24,0x3C($29)
40153		 or    $5,$0,$2
40154		 or    $4,$0,$14
40155		 jalr  $25
40156		 sw    $23,0x4C($21)    	 # Delay slot
40157		 lw    $24,0x3C($29)
40158		 lw    $14,0x40($29)
40159		 lw    $9,0x44($29)
40160		 lw    $15,m68k_ICount
40161		 addiu $15,$15,-14
40162		 bgez  $15,3f
40163		 lhu   $24,0x00($23)    	 # Delay slot
40164		 j     MainExit
40165	3:
40166		 sll   $7,$24,2         	 # Delay slot
40167		 addu  $7,$7,$30
40168		 lw    $7,0x00($7)
40169		 jr    $7
40170		 nop                    	 # Delay slot
40171
40172OP0_8127:				#:
40173		 addiu $23,$23,2
40174
40175		 srl   $24,$24,7
40176		 andi  $24,$24,0x1C
40177		 addu  $24,$24,$21
40178		 lb    $9,0x00($24)
40179		 lw    $14,0x3C($21)    	 # Get A7
40180		 addiu $14,$14,-2
40181		 sw    $14,0x3C($21)
40182		 lw    $25,0x7C($21)
40183		 sw    $15,m68k_ICount
40184		 sw    $9,0x44($29)
40185		 sw    $14,0x40($29)
40186		 sw    $24,0x3C($29)
40187		 or    $4,$0,$14
40188		 jalr  $25
40189		 sw    $23,0x4C($21)    	 # Delay slot
40190		 lw    $24,0x3C($29)
40191		 lw    $14,0x40($29)
40192		 lw    $9,0x44($29)
40193		 lw    $15,m68k_ICount
40194		 seb   $10,$2
40195		 or   $2,$10,$9
40196		 and   $16,$0,$0        	 # Clear Carry
40197		 and   $17,$0,$0        	 # Clear Overflow
40198		 slt   $19,$2,$0        	 # Set Sign
40199		 sltiu $18,$2,1         	 # Set Zero
40200		 lw    $25,0x88($21)
40201		 sw    $15,m68k_ICount
40202		 sw    $9,0x44($29)
40203		 sw    $14,0x40($29)
40204		 sw    $24,0x3C($29)
40205		 or    $5,$0,$2
40206		 or    $4,$0,$14
40207		 jalr  $25
40208		 sw    $23,0x4C($21)    	 # Delay slot
40209		 lw    $24,0x3C($29)
40210		 lw    $14,0x40($29)
40211		 lw    $9,0x44($29)
40212		 lw    $15,m68k_ICount
40213		 addiu $15,$15,-14
40214		 bgez  $15,3f
40215		 lhu   $24,0x00($23)    	 # Delay slot
40216		 j     MainExit
40217	3:
40218		 sll   $7,$24,2         	 # Delay slot
40219		 addu  $7,$7,$30
40220		 lw    $7,0x00($7)
40221		 jr    $7
40222		 nop                    	 # Delay slot
40223
40224OP0_8128:				#:
40225		 addiu $23,$23,2
40226
40227		 andi  $8,$24,0x07
40228		 srl   $24,$24,7
40229		 andi  $24,$24,0x1C
40230		 addu  $24,$24,$21
40231		 lb    $9,0x00($24)
40232		 lh    $7,0x00($23)
40233		 sll   $8,$8,2
40234		 addu  $8,$8,$21
40235		 lw    $14,0x20($8)
40236		 addiu $23,$23,2
40237		 addu  $14,$14,$7
40238		 lw    $25,0x7C($21)
40239		 sw    $15,m68k_ICount
40240		 sw    $9,0x44($29)
40241		 sw    $14,0x40($29)
40242		 sw    $24,0x3C($29)
40243		 or    $4,$0,$14
40244		 jalr  $25
40245		 sw    $23,0x4C($21)    	 # Delay slot
40246		 lw    $24,0x3C($29)
40247		 lw    $14,0x40($29)
40248		 lw    $9,0x44($29)
40249		 lw    $15,m68k_ICount
40250		 seb   $10,$2
40251		 or   $2,$10,$9
40252		 and   $16,$0,$0        	 # Clear Carry
40253		 and   $17,$0,$0        	 # Clear Overflow
40254		 slt   $19,$2,$0        	 # Set Sign
40255		 sltiu $18,$2,1         	 # Set Zero
40256		 lw    $25,0x88($21)
40257		 sw    $15,m68k_ICount
40258		 sw    $9,0x44($29)
40259		 sw    $14,0x40($29)
40260		 sw    $24,0x3C($29)
40261		 or    $5,$0,$2
40262		 or    $4,$0,$14
40263		 jalr  $25
40264		 sw    $23,0x4C($21)    	 # Delay slot
40265		 lw    $24,0x3C($29)
40266		 lw    $14,0x40($29)
40267		 lw    $9,0x44($29)
40268		 lw    $15,m68k_ICount
40269		 addiu $15,$15,-16
40270		 bgez  $15,3f
40271		 lhu   $24,0x00($23)    	 # Delay slot
40272		 j     MainExit
40273	3:
40274		 sll   $7,$24,2         	 # Delay slot
40275		 addu  $7,$7,$30
40276		 lw    $7,0x00($7)
40277		 jr    $7
40278		 nop                    	 # Delay slot
40279
40280OP0_8130:				#:
40281		 addiu $23,$23,2
40282
40283		 andi  $8,$24,0x07
40284		 srl   $24,$24,7
40285		 andi  $24,$24,0x1C
40286		 addu  $24,$24,$21
40287		 lb    $9,0x00($24)
40288		 sll   $8,$8,2
40289		 addu  $8,$8,$21
40290		 lw    $14,0x20($8)
40291		 lhu   $7,0x00($23)
40292		 addiu $23,$23,2
40293		 seb   $6,$7
40294		 or    $25,$0,$7
40295		 srl   $7,$7,12
40296		 andi  $25,$25,0x0800
40297		 sll   $7,$7,2
40298		 addu  $7,$7,$21
40299		 bne   $25,$0,0f
40300		 lw    $25,0x00($7)      	 # Delay slot
40301		 seh   $25,$25
40302	0:
40303		 addu  $25,$14,$25
40304		 addu  $14,$25,$6
40305		 lw    $25,0x7C($21)
40306		 sw    $15,m68k_ICount
40307		 sw    $9,0x44($29)
40308		 sw    $14,0x40($29)
40309		 sw    $24,0x3C($29)
40310		 or    $4,$0,$14
40311		 jalr  $25
40312		 sw    $23,0x4C($21)    	 # Delay slot
40313		 lw    $24,0x3C($29)
40314		 lw    $14,0x40($29)
40315		 lw    $9,0x44($29)
40316		 lw    $15,m68k_ICount
40317		 seb   $10,$2
40318		 or   $2,$10,$9
40319		 and   $16,$0,$0        	 # Clear Carry
40320		 and   $17,$0,$0        	 # Clear Overflow
40321		 slt   $19,$2,$0        	 # Set Sign
40322		 sltiu $18,$2,1         	 # Set Zero
40323		 lw    $25,0x88($21)
40324		 sw    $15,m68k_ICount
40325		 sw    $9,0x44($29)
40326		 sw    $14,0x40($29)
40327		 sw    $24,0x3C($29)
40328		 or    $5,$0,$2
40329		 or    $4,$0,$14
40330		 jalr  $25
40331		 sw    $23,0x4C($21)    	 # Delay slot
40332		 lw    $24,0x3C($29)
40333		 lw    $14,0x40($29)
40334		 lw    $9,0x44($29)
40335		 lw    $15,m68k_ICount
40336		 addiu $15,$15,-18
40337		 bgez  $15,3f
40338		 lhu   $24,0x00($23)    	 # Delay slot
40339		 j     MainExit
40340	3:
40341		 sll   $7,$24,2         	 # Delay slot
40342		 addu  $7,$7,$30
40343		 lw    $7,0x00($7)
40344		 jr    $7
40345		 nop                    	 # Delay slot
40346
40347OP0_8138:				#:
40348		 addiu $23,$23,2
40349
40350		 srl   $24,$24,7
40351		 andi  $24,$24,0x1C
40352		 addu  $24,$24,$21
40353		 lb    $9,0x00($24)
40354		 lh    $14,0x00($23)
40355		 addiu $23,$23,2
40356		 lw    $25,0x7C($21)
40357		 sw    $15,m68k_ICount
40358		 sw    $9,0x44($29)
40359		 sw    $14,0x40($29)
40360		 sw    $24,0x3C($29)
40361		 or    $4,$0,$14
40362		 jalr  $25
40363		 sw    $23,0x4C($21)    	 # Delay slot
40364		 lw    $24,0x3C($29)
40365		 lw    $14,0x40($29)
40366		 lw    $9,0x44($29)
40367		 lw    $15,m68k_ICount
40368		 seb   $10,$2
40369		 or   $2,$10,$9
40370		 and   $16,$0,$0        	 # Clear Carry
40371		 and   $17,$0,$0        	 # Clear Overflow
40372		 slt   $19,$2,$0        	 # Set Sign
40373		 sltiu $18,$2,1         	 # Set Zero
40374		 lw    $25,0x88($21)
40375		 sw    $15,m68k_ICount
40376		 sw    $9,0x44($29)
40377		 sw    $14,0x40($29)
40378		 sw    $24,0x3C($29)
40379		 or    $5,$0,$2
40380		 or    $4,$0,$14
40381		 jalr  $25
40382		 sw    $23,0x4C($21)    	 # Delay slot
40383		 lw    $24,0x3C($29)
40384		 lw    $14,0x40($29)
40385		 lw    $9,0x44($29)
40386		 lw    $15,m68k_ICount
40387		 addiu $15,$15,-16
40388		 bgez  $15,3f
40389		 lhu   $24,0x00($23)    	 # Delay slot
40390		 j     MainExit
40391	3:
40392		 sll   $7,$24,2         	 # Delay slot
40393		 addu  $7,$7,$30
40394		 lw    $7,0x00($7)
40395		 jr    $7
40396		 nop                    	 # Delay slot
40397
40398OP0_8139:				#:
40399		 addiu $23,$23,2
40400
40401		 srl   $24,$24,7
40402		 andi  $24,$24,0x1C
40403		 addu  $24,$24,$21
40404		 lb    $9,0x00($24)
40405		 lhu   $14,0x00($23)
40406		 lhu   $25,0x02($23)
40407		 sll   $14,$14,16
40408		 or    $14,$14,$25
40409		 addiu $23,$23,4
40410		 lw    $25,0x7C($21)
40411		 sw    $15,m68k_ICount
40412		 sw    $9,0x44($29)
40413		 sw    $14,0x40($29)
40414		 sw    $24,0x3C($29)
40415		 or    $4,$0,$14
40416		 jalr  $25
40417		 sw    $23,0x4C($21)    	 # Delay slot
40418		 lw    $24,0x3C($29)
40419		 lw    $14,0x40($29)
40420		 lw    $9,0x44($29)
40421		 lw    $15,m68k_ICount
40422		 seb   $10,$2
40423		 or   $2,$10,$9
40424		 and   $16,$0,$0        	 # Clear Carry
40425		 and   $17,$0,$0        	 # Clear Overflow
40426		 slt   $19,$2,$0        	 # Set Sign
40427		 sltiu $18,$2,1         	 # Set Zero
40428		 lw    $25,0x88($21)
40429		 sw    $15,m68k_ICount
40430		 sw    $9,0x44($29)
40431		 sw    $14,0x40($29)
40432		 sw    $24,0x3C($29)
40433		 or    $5,$0,$2
40434		 or    $4,$0,$14
40435		 jalr  $25
40436		 sw    $23,0x4C($21)    	 # Delay slot
40437		 lw    $24,0x3C($29)
40438		 lw    $14,0x40($29)
40439		 lw    $9,0x44($29)
40440		 lw    $15,m68k_ICount
40441		 addiu $15,$15,-20
40442		 bgez  $15,3f
40443		 lhu   $24,0x00($23)    	 # Delay slot
40444		 j     MainExit
40445	3:
40446		 sll   $7,$24,2         	 # Delay slot
40447		 addu  $7,$7,$30
40448		 lw    $7,0x00($7)
40449		 jr    $7
40450		 nop                    	 # Delay slot
40451
40452OP0_8150:				#:
40453		 addiu $23,$23,2
40454
40455		 andi  $8,$24,0x07
40456		 srl   $24,$24,7
40457		 andi  $24,$24,0x1C
40458		 addu  $24,$24,$21
40459		 lh    $9,0x00($24)
40460		 sll   $8,$8,2
40461		 addu  $8,$8,$21
40462		 lw    $14,0x20($8)
40463		 lw    $25,0x80($21)
40464		 sw    $15,m68k_ICount
40465		 sw    $9,0x44($29)
40466		 sw    $14,0x40($29)
40467		 sw    $24,0x3C($29)
40468		 or    $4,$0,$14
40469		 jalr  $25
40470		 sw    $23,0x4C($21)    	 # Delay slot
40471		 lw    $24,0x3C($29)
40472		 lw    $14,0x40($29)
40473		 lw    $9,0x44($29)
40474		 lw    $15,m68k_ICount
40475		 seh   $10,$2
40476		 or   $2,$10,$9
40477		 and   $16,$0,$0        	 # Clear Carry
40478		 and   $17,$0,$0        	 # Clear Overflow
40479		 slt   $19,$2,$0        	 # Set Sign
40480		 sltiu $18,$2,1         	 # Set Zero
40481		 lw    $25,0x8C($21)
40482		 sw    $15,m68k_ICount
40483		 sw    $9,0x44($29)
40484		 sw    $14,0x40($29)
40485		 sw    $24,0x3C($29)
40486		 or    $5,$0,$2
40487		 or    $4,$0,$14
40488		 jalr  $25
40489		 sw    $23,0x4C($21)    	 # Delay slot
40490		 lw    $24,0x3C($29)
40491		 lw    $14,0x40($29)
40492		 lw    $9,0x44($29)
40493		 lw    $15,m68k_ICount
40494		 addiu $15,$15,-12
40495		 bgez  $15,3f
40496		 lhu   $24,0x00($23)    	 # Delay slot
40497		 j     MainExit
40498	3:
40499		 sll   $7,$24,2         	 # Delay slot
40500		 addu  $7,$7,$30
40501		 lw    $7,0x00($7)
40502		 jr    $7
40503		 nop                    	 # Delay slot
40504
40505OP0_8158:				#:
40506		 addiu $23,$23,2
40507
40508		 andi  $8,$24,0x07
40509		 srl   $24,$24,7
40510		 andi  $24,$24,0x1C
40511		 addu  $24,$24,$21
40512		 lh    $9,0x00($24)
40513		 sll   $8,$8,2
40514		 addu  $8,$8,$21
40515		 lw    $14,0x20($8)
40516		 addiu $25,$14,2
40517		 sw    $25,0x20($8)
40518		 lw    $25,0x80($21)
40519		 sw    $15,m68k_ICount
40520		 sw    $9,0x44($29)
40521		 sw    $14,0x40($29)
40522		 sw    $24,0x3C($29)
40523		 or    $4,$0,$14
40524		 jalr  $25
40525		 sw    $23,0x4C($21)    	 # Delay slot
40526		 lw    $24,0x3C($29)
40527		 lw    $14,0x40($29)
40528		 lw    $9,0x44($29)
40529		 lw    $15,m68k_ICount
40530		 seh   $10,$2
40531		 or   $2,$10,$9
40532		 and   $16,$0,$0        	 # Clear Carry
40533		 and   $17,$0,$0        	 # Clear Overflow
40534		 slt   $19,$2,$0        	 # Set Sign
40535		 sltiu $18,$2,1         	 # Set Zero
40536		 lw    $25,0x8C($21)
40537		 sw    $15,m68k_ICount
40538		 sw    $9,0x44($29)
40539		 sw    $14,0x40($29)
40540		 sw    $24,0x3C($29)
40541		 or    $5,$0,$2
40542		 or    $4,$0,$14
40543		 jalr  $25
40544		 sw    $23,0x4C($21)    	 # Delay slot
40545		 lw    $24,0x3C($29)
40546		 lw    $14,0x40($29)
40547		 lw    $9,0x44($29)
40548		 lw    $15,m68k_ICount
40549		 addiu $15,$15,-12
40550		 bgez  $15,3f
40551		 lhu   $24,0x00($23)    	 # Delay slot
40552		 j     MainExit
40553	3:
40554		 sll   $7,$24,2         	 # Delay slot
40555		 addu  $7,$7,$30
40556		 lw    $7,0x00($7)
40557		 jr    $7
40558		 nop                    	 # Delay slot
40559
40560OP0_8160:				#:
40561		 addiu $23,$23,2
40562
40563		 andi  $8,$24,0x07
40564		 srl   $24,$24,7
40565		 andi  $24,$24,0x1C
40566		 addu  $24,$24,$21
40567		 lh    $9,0x00($24)
40568		 sll   $8,$8,2
40569		 addu  $8,$8,$21
40570		 lw    $14,0x20($8)
40571		 addiu $14,$14,-2
40572		 sw    $14,0x20($8)
40573		 lw    $25,0x80($21)
40574		 sw    $15,m68k_ICount
40575		 sw    $9,0x44($29)
40576		 sw    $14,0x40($29)
40577		 sw    $24,0x3C($29)
40578		 or    $4,$0,$14
40579		 jalr  $25
40580		 sw    $23,0x4C($21)    	 # Delay slot
40581		 lw    $24,0x3C($29)
40582		 lw    $14,0x40($29)
40583		 lw    $9,0x44($29)
40584		 lw    $15,m68k_ICount
40585		 seh   $10,$2
40586		 or   $2,$10,$9
40587		 and   $16,$0,$0        	 # Clear Carry
40588		 and   $17,$0,$0        	 # Clear Overflow
40589		 slt   $19,$2,$0        	 # Set Sign
40590		 sltiu $18,$2,1         	 # Set Zero
40591		 lw    $25,0x8C($21)
40592		 sw    $15,m68k_ICount
40593		 sw    $9,0x44($29)
40594		 sw    $14,0x40($29)
40595		 sw    $24,0x3C($29)
40596		 or    $5,$0,$2
40597		 or    $4,$0,$14
40598		 jalr  $25
40599		 sw    $23,0x4C($21)    	 # Delay slot
40600		 lw    $24,0x3C($29)
40601		 lw    $14,0x40($29)
40602		 lw    $9,0x44($29)
40603		 lw    $15,m68k_ICount
40604		 addiu $15,$15,-14
40605		 bgez  $15,3f
40606		 lhu   $24,0x00($23)    	 # Delay slot
40607		 j     MainExit
40608	3:
40609		 sll   $7,$24,2         	 # Delay slot
40610		 addu  $7,$7,$30
40611		 lw    $7,0x00($7)
40612		 jr    $7
40613		 nop                    	 # Delay slot
40614
40615OP0_8168:				#:
40616		 addiu $23,$23,2
40617
40618		 andi  $8,$24,0x07
40619		 srl   $24,$24,7
40620		 andi  $24,$24,0x1C
40621		 addu  $24,$24,$21
40622		 lh    $9,0x00($24)
40623		 lh    $7,0x00($23)
40624		 sll   $8,$8,2
40625		 addu  $8,$8,$21
40626		 lw    $14,0x20($8)
40627		 addiu $23,$23,2
40628		 addu  $14,$14,$7
40629		 lw    $25,0x80($21)
40630		 sw    $15,m68k_ICount
40631		 sw    $9,0x44($29)
40632		 sw    $14,0x40($29)
40633		 sw    $24,0x3C($29)
40634		 or    $4,$0,$14
40635		 jalr  $25
40636		 sw    $23,0x4C($21)    	 # Delay slot
40637		 lw    $24,0x3C($29)
40638		 lw    $14,0x40($29)
40639		 lw    $9,0x44($29)
40640		 lw    $15,m68k_ICount
40641		 seh   $10,$2
40642		 or   $2,$10,$9
40643		 and   $16,$0,$0        	 # Clear Carry
40644		 and   $17,$0,$0        	 # Clear Overflow
40645		 slt   $19,$2,$0        	 # Set Sign
40646		 sltiu $18,$2,1         	 # Set Zero
40647		 lw    $25,0x8C($21)
40648		 sw    $15,m68k_ICount
40649		 sw    $9,0x44($29)
40650		 sw    $14,0x40($29)
40651		 sw    $24,0x3C($29)
40652		 or    $5,$0,$2
40653		 or    $4,$0,$14
40654		 jalr  $25
40655		 sw    $23,0x4C($21)    	 # Delay slot
40656		 lw    $24,0x3C($29)
40657		 lw    $14,0x40($29)
40658		 lw    $9,0x44($29)
40659		 lw    $15,m68k_ICount
40660		 addiu $15,$15,-16
40661		 bgez  $15,3f
40662		 lhu   $24,0x00($23)    	 # Delay slot
40663		 j     MainExit
40664	3:
40665		 sll   $7,$24,2         	 # Delay slot
40666		 addu  $7,$7,$30
40667		 lw    $7,0x00($7)
40668		 jr    $7
40669		 nop                    	 # Delay slot
40670
40671OP0_8170:				#:
40672		 addiu $23,$23,2
40673
40674		 andi  $8,$24,0x07
40675		 srl   $24,$24,7
40676		 andi  $24,$24,0x1C
40677		 addu  $24,$24,$21
40678		 lh    $9,0x00($24)
40679		 sll   $8,$8,2
40680		 addu  $8,$8,$21
40681		 lw    $14,0x20($8)
40682		 lhu   $7,0x00($23)
40683		 addiu $23,$23,2
40684		 seb   $6,$7
40685		 or    $25,$0,$7
40686		 srl   $7,$7,12
40687		 andi  $25,$25,0x0800
40688		 sll   $7,$7,2
40689		 addu  $7,$7,$21
40690		 bne   $25,$0,0f
40691		 lw    $25,0x00($7)      	 # Delay slot
40692		 seh   $25,$25
40693	0:
40694		 addu  $25,$14,$25
40695		 addu  $14,$25,$6
40696		 lw    $25,0x80($21)
40697		 sw    $15,m68k_ICount
40698		 sw    $9,0x44($29)
40699		 sw    $14,0x40($29)
40700		 sw    $24,0x3C($29)
40701		 or    $4,$0,$14
40702		 jalr  $25
40703		 sw    $23,0x4C($21)    	 # Delay slot
40704		 lw    $24,0x3C($29)
40705		 lw    $14,0x40($29)
40706		 lw    $9,0x44($29)
40707		 lw    $15,m68k_ICount
40708		 seh   $10,$2
40709		 or   $2,$10,$9
40710		 and   $16,$0,$0        	 # Clear Carry
40711		 and   $17,$0,$0        	 # Clear Overflow
40712		 slt   $19,$2,$0        	 # Set Sign
40713		 sltiu $18,$2,1         	 # Set Zero
40714		 lw    $25,0x8C($21)
40715		 sw    $15,m68k_ICount
40716		 sw    $9,0x44($29)
40717		 sw    $14,0x40($29)
40718		 sw    $24,0x3C($29)
40719		 or    $5,$0,$2
40720		 or    $4,$0,$14
40721		 jalr  $25
40722		 sw    $23,0x4C($21)    	 # Delay slot
40723		 lw    $24,0x3C($29)
40724		 lw    $14,0x40($29)
40725		 lw    $9,0x44($29)
40726		 lw    $15,m68k_ICount
40727		 addiu $15,$15,-18
40728		 bgez  $15,3f
40729		 lhu   $24,0x00($23)    	 # Delay slot
40730		 j     MainExit
40731	3:
40732		 sll   $7,$24,2         	 # Delay slot
40733		 addu  $7,$7,$30
40734		 lw    $7,0x00($7)
40735		 jr    $7
40736		 nop                    	 # Delay slot
40737
40738OP0_8178:				#:
40739		 addiu $23,$23,2
40740
40741		 srl   $24,$24,7
40742		 andi  $24,$24,0x1C
40743		 addu  $24,$24,$21
40744		 lh    $9,0x00($24)
40745		 lh    $14,0x00($23)
40746		 addiu $23,$23,2
40747		 lw    $25,0x80($21)
40748		 sw    $15,m68k_ICount
40749		 sw    $9,0x44($29)
40750		 sw    $14,0x40($29)
40751		 sw    $24,0x3C($29)
40752		 or    $4,$0,$14
40753		 jalr  $25
40754		 sw    $23,0x4C($21)    	 # Delay slot
40755		 lw    $24,0x3C($29)
40756		 lw    $14,0x40($29)
40757		 lw    $9,0x44($29)
40758		 lw    $15,m68k_ICount
40759		 seh   $10,$2
40760		 or   $2,$10,$9
40761		 and   $16,$0,$0        	 # Clear Carry
40762		 and   $17,$0,$0        	 # Clear Overflow
40763		 slt   $19,$2,$0        	 # Set Sign
40764		 sltiu $18,$2,1         	 # Set Zero
40765		 lw    $25,0x8C($21)
40766		 sw    $15,m68k_ICount
40767		 sw    $9,0x44($29)
40768		 sw    $14,0x40($29)
40769		 sw    $24,0x3C($29)
40770		 or    $5,$0,$2
40771		 or    $4,$0,$14
40772		 jalr  $25
40773		 sw    $23,0x4C($21)    	 # Delay slot
40774		 lw    $24,0x3C($29)
40775		 lw    $14,0x40($29)
40776		 lw    $9,0x44($29)
40777		 lw    $15,m68k_ICount
40778		 addiu $15,$15,-16
40779		 bgez  $15,3f
40780		 lhu   $24,0x00($23)    	 # Delay slot
40781		 j     MainExit
40782	3:
40783		 sll   $7,$24,2         	 # Delay slot
40784		 addu  $7,$7,$30
40785		 lw    $7,0x00($7)
40786		 jr    $7
40787		 nop                    	 # Delay slot
40788
40789OP0_8179:				#:
40790		 addiu $23,$23,2
40791
40792		 srl   $24,$24,7
40793		 andi  $24,$24,0x1C
40794		 addu  $24,$24,$21
40795		 lh    $9,0x00($24)
40796		 lhu   $14,0x00($23)
40797		 lhu   $25,0x02($23)
40798		 sll   $14,$14,16
40799		 or    $14,$14,$25
40800		 addiu $23,$23,4
40801		 lw    $25,0x80($21)
40802		 sw    $15,m68k_ICount
40803		 sw    $9,0x44($29)
40804		 sw    $14,0x40($29)
40805		 sw    $24,0x3C($29)
40806		 or    $4,$0,$14
40807		 jalr  $25
40808		 sw    $23,0x4C($21)    	 # Delay slot
40809		 lw    $24,0x3C($29)
40810		 lw    $14,0x40($29)
40811		 lw    $9,0x44($29)
40812		 lw    $15,m68k_ICount
40813		 seh   $10,$2
40814		 or   $2,$10,$9
40815		 and   $16,$0,$0        	 # Clear Carry
40816		 and   $17,$0,$0        	 # Clear Overflow
40817		 slt   $19,$2,$0        	 # Set Sign
40818		 sltiu $18,$2,1         	 # Set Zero
40819		 lw    $25,0x8C($21)
40820		 sw    $15,m68k_ICount
40821		 sw    $9,0x44($29)
40822		 sw    $14,0x40($29)
40823		 sw    $24,0x3C($29)
40824		 or    $5,$0,$2
40825		 or    $4,$0,$14
40826		 jalr  $25
40827		 sw    $23,0x4C($21)    	 # Delay slot
40828		 lw    $24,0x3C($29)
40829		 lw    $14,0x40($29)
40830		 lw    $9,0x44($29)
40831		 lw    $15,m68k_ICount
40832		 addiu $15,$15,-20
40833		 bgez  $15,3f
40834		 lhu   $24,0x00($23)    	 # Delay slot
40835		 j     MainExit
40836	3:
40837		 sll   $7,$24,2         	 # Delay slot
40838		 addu  $7,$7,$30
40839		 lw    $7,0x00($7)
40840		 jr    $7
40841		 nop                    	 # Delay slot
40842
40843OP0_8190:				#:
40844		 addiu $23,$23,2
40845
40846		 andi  $8,$24,0x07
40847		 srl   $24,$24,7
40848		 andi  $24,$24,0x1C
40849		 addu  $24,$24,$21
40850		 lw    $9,0x00($24)
40851		 sll   $8,$8,2
40852		 addu  $8,$8,$21
40853		 lw    $14,0x20($8)
40854		 lw    $25,0x84($21)
40855		 sw    $15,m68k_ICount
40856		 sw    $9,0x44($29)
40857		 sw    $14,0x40($29)
40858		 sw    $24,0x3C($29)
40859		 or    $4,$0,$14
40860		 jalr  $25
40861		 sw    $23,0x4C($21)    	 # Delay slot
40862		 lw    $24,0x3C($29)
40863		 lw    $14,0x40($29)
40864		 lw    $9,0x44($29)
40865		 lw    $15,m68k_ICount
40866		 or    $10,$0,$2
40867		 or   $2,$10,$9
40868		 and   $16,$0,$0        	 # Clear Carry
40869		 and   $17,$0,$0        	 # Clear Overflow
40870		 slt   $19,$2,$0        	 # Set Sign
40871		 sltiu $18,$2,1         	 # Set Zero
40872		 lw    $25,0x90($21)
40873		 sw    $15,m68k_ICount
40874		 sw    $9,0x44($29)
40875		 sw    $14,0x40($29)
40876		 sw    $24,0x3C($29)
40877		 or    $5,$0,$2
40878		 or    $4,$0,$14
40879		 jalr  $25
40880		 sw    $23,0x4C($21)    	 # Delay slot
40881		 lw    $24,0x3C($29)
40882		 lw    $14,0x40($29)
40883		 lw    $9,0x44($29)
40884		 lw    $15,m68k_ICount
40885		 addiu $15,$15,-20
40886		 bgez  $15,3f
40887		 lhu   $24,0x00($23)    	 # Delay slot
40888		 j     MainExit
40889	3:
40890		 sll   $7,$24,2         	 # Delay slot
40891		 addu  $7,$7,$30
40892		 lw    $7,0x00($7)
40893		 jr    $7
40894		 nop                    	 # Delay slot
40895
40896OP0_8198:				#:
40897		 addiu $23,$23,2
40898
40899		 andi  $8,$24,0x07
40900		 srl   $24,$24,7
40901		 andi  $24,$24,0x1C
40902		 addu  $24,$24,$21
40903		 lw    $9,0x00($24)
40904		 sll   $8,$8,2
40905		 addu  $8,$8,$21
40906		 lw    $14,0x20($8)
40907		 addiu $25,$14,4
40908		 sw    $25,0x20($8)
40909		 lw    $25,0x84($21)
40910		 sw    $15,m68k_ICount
40911		 sw    $9,0x44($29)
40912		 sw    $14,0x40($29)
40913		 sw    $24,0x3C($29)
40914		 or    $4,$0,$14
40915		 jalr  $25
40916		 sw    $23,0x4C($21)    	 # Delay slot
40917		 lw    $24,0x3C($29)
40918		 lw    $14,0x40($29)
40919		 lw    $9,0x44($29)
40920		 lw    $15,m68k_ICount
40921		 or    $10,$0,$2
40922		 or   $2,$10,$9
40923		 and   $16,$0,$0        	 # Clear Carry
40924		 and   $17,$0,$0        	 # Clear Overflow
40925		 slt   $19,$2,$0        	 # Set Sign
40926		 sltiu $18,$2,1         	 # Set Zero
40927		 lw    $25,0x90($21)
40928		 sw    $15,m68k_ICount
40929		 sw    $9,0x44($29)
40930		 sw    $14,0x40($29)
40931		 sw    $24,0x3C($29)
40932		 or    $5,$0,$2
40933		 or    $4,$0,$14
40934		 jalr  $25
40935		 sw    $23,0x4C($21)    	 # Delay slot
40936		 lw    $24,0x3C($29)
40937		 lw    $14,0x40($29)
40938		 lw    $9,0x44($29)
40939		 lw    $15,m68k_ICount
40940		 addiu $15,$15,-20
40941		 bgez  $15,3f
40942		 lhu   $24,0x00($23)    	 # Delay slot
40943		 j     MainExit
40944	3:
40945		 sll   $7,$24,2         	 # Delay slot
40946		 addu  $7,$7,$30
40947		 lw    $7,0x00($7)
40948		 jr    $7
40949		 nop                    	 # Delay slot
40950
40951OP0_81a0:				#:
40952		 addiu $23,$23,2
40953
40954		 andi  $8,$24,0x07
40955		 srl   $24,$24,7
40956		 andi  $24,$24,0x1C
40957		 addu  $24,$24,$21
40958		 lw    $9,0x00($24)
40959		 sll   $8,$8,2
40960		 addu  $8,$8,$21
40961		 lw    $14,0x20($8)
40962		 addiu $14,$14,-4
40963		 sw    $14,0x20($8)
40964		 lw    $25,0x84($21)
40965		 sw    $15,m68k_ICount
40966		 sw    $9,0x44($29)
40967		 sw    $14,0x40($29)
40968		 sw    $24,0x3C($29)
40969		 or    $4,$0,$14
40970		 jalr  $25
40971		 sw    $23,0x4C($21)    	 # Delay slot
40972		 lw    $24,0x3C($29)
40973		 lw    $14,0x40($29)
40974		 lw    $9,0x44($29)
40975		 lw    $15,m68k_ICount
40976		 or    $10,$0,$2
40977		 or   $2,$10,$9
40978		 and   $16,$0,$0        	 # Clear Carry
40979		 and   $17,$0,$0        	 # Clear Overflow
40980		 slt   $19,$2,$0        	 # Set Sign
40981		 sltiu $18,$2,1         	 # Set Zero
40982		 lw    $25,0x90($21)
40983		 sw    $15,m68k_ICount
40984		 sw    $9,0x44($29)
40985		 sw    $14,0x40($29)
40986		 sw    $24,0x3C($29)
40987		 or    $5,$0,$2
40988		 or    $4,$0,$14
40989		 jalr  $25
40990		 sw    $23,0x4C($21)    	 # Delay slot
40991		 lw    $24,0x3C($29)
40992		 lw    $14,0x40($29)
40993		 lw    $9,0x44($29)
40994		 lw    $15,m68k_ICount
40995		 addiu $15,$15,-22
40996		 bgez  $15,3f
40997		 lhu   $24,0x00($23)    	 # Delay slot
40998		 j     MainExit
40999	3:
41000		 sll   $7,$24,2         	 # Delay slot
41001		 addu  $7,$7,$30
41002		 lw    $7,0x00($7)
41003		 jr    $7
41004		 nop                    	 # Delay slot
41005
41006OP0_81a8:				#:
41007		 addiu $23,$23,2
41008
41009		 andi  $8,$24,0x07
41010		 srl   $24,$24,7
41011		 andi  $24,$24,0x1C
41012		 addu  $24,$24,$21
41013		 lw    $9,0x00($24)
41014		 lh    $7,0x00($23)
41015		 sll   $8,$8,2
41016		 addu  $8,$8,$21
41017		 lw    $14,0x20($8)
41018		 addiu $23,$23,2
41019		 addu  $14,$14,$7
41020		 lw    $25,0x84($21)
41021		 sw    $15,m68k_ICount
41022		 sw    $9,0x44($29)
41023		 sw    $14,0x40($29)
41024		 sw    $24,0x3C($29)
41025		 or    $4,$0,$14
41026		 jalr  $25
41027		 sw    $23,0x4C($21)    	 # Delay slot
41028		 lw    $24,0x3C($29)
41029		 lw    $14,0x40($29)
41030		 lw    $9,0x44($29)
41031		 lw    $15,m68k_ICount
41032		 or    $10,$0,$2
41033		 or   $2,$10,$9
41034		 and   $16,$0,$0        	 # Clear Carry
41035		 and   $17,$0,$0        	 # Clear Overflow
41036		 slt   $19,$2,$0        	 # Set Sign
41037		 sltiu $18,$2,1         	 # Set Zero
41038		 lw    $25,0x90($21)
41039		 sw    $15,m68k_ICount
41040		 sw    $9,0x44($29)
41041		 sw    $14,0x40($29)
41042		 sw    $24,0x3C($29)
41043		 or    $5,$0,$2
41044		 or    $4,$0,$14
41045		 jalr  $25
41046		 sw    $23,0x4C($21)    	 # Delay slot
41047		 lw    $24,0x3C($29)
41048		 lw    $14,0x40($29)
41049		 lw    $9,0x44($29)
41050		 lw    $15,m68k_ICount
41051		 addiu $15,$15,-24
41052		 bgez  $15,3f
41053		 lhu   $24,0x00($23)    	 # Delay slot
41054		 j     MainExit
41055	3:
41056		 sll   $7,$24,2         	 # Delay slot
41057		 addu  $7,$7,$30
41058		 lw    $7,0x00($7)
41059		 jr    $7
41060		 nop                    	 # Delay slot
41061
41062OP0_81b0:				#:
41063		 addiu $23,$23,2
41064
41065		 andi  $8,$24,0x07
41066		 srl   $24,$24,7
41067		 andi  $24,$24,0x1C
41068		 addu  $24,$24,$21
41069		 lw    $9,0x00($24)
41070		 sll   $8,$8,2
41071		 addu  $8,$8,$21
41072		 lw    $14,0x20($8)
41073		 lhu   $7,0x00($23)
41074		 addiu $23,$23,2
41075		 seb   $6,$7
41076		 or    $25,$0,$7
41077		 srl   $7,$7,12
41078		 andi  $25,$25,0x0800
41079		 sll   $7,$7,2
41080		 addu  $7,$7,$21
41081		 bne   $25,$0,0f
41082		 lw    $25,0x00($7)      	 # Delay slot
41083		 seh   $25,$25
41084	0:
41085		 addu  $25,$14,$25
41086		 addu  $14,$25,$6
41087		 lw    $25,0x84($21)
41088		 sw    $15,m68k_ICount
41089		 sw    $9,0x44($29)
41090		 sw    $14,0x40($29)
41091		 sw    $24,0x3C($29)
41092		 or    $4,$0,$14
41093		 jalr  $25
41094		 sw    $23,0x4C($21)    	 # Delay slot
41095		 lw    $24,0x3C($29)
41096		 lw    $14,0x40($29)
41097		 lw    $9,0x44($29)
41098		 lw    $15,m68k_ICount
41099		 or    $10,$0,$2
41100		 or   $2,$10,$9
41101		 and   $16,$0,$0        	 # Clear Carry
41102		 and   $17,$0,$0        	 # Clear Overflow
41103		 slt   $19,$2,$0        	 # Set Sign
41104		 sltiu $18,$2,1         	 # Set Zero
41105		 lw    $25,0x90($21)
41106		 sw    $15,m68k_ICount
41107		 sw    $9,0x44($29)
41108		 sw    $14,0x40($29)
41109		 sw    $24,0x3C($29)
41110		 or    $5,$0,$2
41111		 or    $4,$0,$14
41112		 jalr  $25
41113		 sw    $23,0x4C($21)    	 # Delay slot
41114		 lw    $24,0x3C($29)
41115		 lw    $14,0x40($29)
41116		 lw    $9,0x44($29)
41117		 lw    $15,m68k_ICount
41118		 addiu $15,$15,-26
41119		 bgez  $15,3f
41120		 lhu   $24,0x00($23)    	 # Delay slot
41121		 j     MainExit
41122	3:
41123		 sll   $7,$24,2         	 # Delay slot
41124		 addu  $7,$7,$30
41125		 lw    $7,0x00($7)
41126		 jr    $7
41127		 nop                    	 # Delay slot
41128
41129OP0_81b8:				#:
41130		 addiu $23,$23,2
41131
41132		 srl   $24,$24,7
41133		 andi  $24,$24,0x1C
41134		 addu  $24,$24,$21
41135		 lw    $9,0x00($24)
41136		 lh    $14,0x00($23)
41137		 addiu $23,$23,2
41138		 lw    $25,0x84($21)
41139		 sw    $15,m68k_ICount
41140		 sw    $9,0x44($29)
41141		 sw    $14,0x40($29)
41142		 sw    $24,0x3C($29)
41143		 or    $4,$0,$14
41144		 jalr  $25
41145		 sw    $23,0x4C($21)    	 # Delay slot
41146		 lw    $24,0x3C($29)
41147		 lw    $14,0x40($29)
41148		 lw    $9,0x44($29)
41149		 lw    $15,m68k_ICount
41150		 or    $10,$0,$2
41151		 or   $2,$10,$9
41152		 and   $16,$0,$0        	 # Clear Carry
41153		 and   $17,$0,$0        	 # Clear Overflow
41154		 slt   $19,$2,$0        	 # Set Sign
41155		 sltiu $18,$2,1         	 # Set Zero
41156		 lw    $25,0x90($21)
41157		 sw    $15,m68k_ICount
41158		 sw    $9,0x44($29)
41159		 sw    $14,0x40($29)
41160		 sw    $24,0x3C($29)
41161		 or    $5,$0,$2
41162		 or    $4,$0,$14
41163		 jalr  $25
41164		 sw    $23,0x4C($21)    	 # Delay slot
41165		 lw    $24,0x3C($29)
41166		 lw    $14,0x40($29)
41167		 lw    $9,0x44($29)
41168		 lw    $15,m68k_ICount
41169		 addiu $15,$15,-24
41170		 bgez  $15,3f
41171		 lhu   $24,0x00($23)    	 # Delay slot
41172		 j     MainExit
41173	3:
41174		 sll   $7,$24,2         	 # Delay slot
41175		 addu  $7,$7,$30
41176		 lw    $7,0x00($7)
41177		 jr    $7
41178		 nop                    	 # Delay slot
41179
41180OP0_81b9:				#:
41181		 addiu $23,$23,2
41182
41183		 srl   $24,$24,7
41184		 andi  $24,$24,0x1C
41185		 addu  $24,$24,$21
41186		 lw    $9,0x00($24)
41187		 lhu   $14,0x00($23)
41188		 lhu   $25,0x02($23)
41189		 sll   $14,$14,16
41190		 or    $14,$14,$25
41191		 addiu $23,$23,4
41192		 lw    $25,0x84($21)
41193		 sw    $15,m68k_ICount
41194		 sw    $9,0x44($29)
41195		 sw    $14,0x40($29)
41196		 sw    $24,0x3C($29)
41197		 or    $4,$0,$14
41198		 jalr  $25
41199		 sw    $23,0x4C($21)    	 # Delay slot
41200		 lw    $24,0x3C($29)
41201		 lw    $14,0x40($29)
41202		 lw    $9,0x44($29)
41203		 lw    $15,m68k_ICount
41204		 or    $10,$0,$2
41205		 or   $2,$10,$9
41206		 and   $16,$0,$0        	 # Clear Carry
41207		 and   $17,$0,$0        	 # Clear Overflow
41208		 slt   $19,$2,$0        	 # Set Sign
41209		 sltiu $18,$2,1         	 # Set Zero
41210		 lw    $25,0x90($21)
41211		 sw    $15,m68k_ICount
41212		 sw    $9,0x44($29)
41213		 sw    $14,0x40($29)
41214		 sw    $24,0x3C($29)
41215		 or    $5,$0,$2
41216		 or    $4,$0,$14
41217		 jalr  $25
41218		 sw    $23,0x4C($21)    	 # Delay slot
41219		 lw    $24,0x3C($29)
41220		 lw    $14,0x40($29)
41221		 lw    $9,0x44($29)
41222		 lw    $15,m68k_ICount
41223		 addiu $15,$15,-28
41224		 bgez  $15,3f
41225		 lhu   $24,0x00($23)    	 # Delay slot
41226		 j     MainExit
41227	3:
41228		 sll   $7,$24,2         	 # Delay slot
41229		 addu  $7,$7,$30
41230		 lw    $7,0x00($7)
41231		 jr    $7
41232		 nop                    	 # Delay slot
41233
41234OP0_9000:				#:
41235		 addiu $23,$23,2
41236
41237		 andi  $8,$24,0x07
41238		 srl   $24,$24,7
41239		 andi  $24,$24,0x1C
41240		 addu  $24,$24,$21
41241		 lb    $9,0x00($24)
41242		 sll   $8,$8,2
41243		 addu  $8,$8,$21
41244		 lb    $2,0x00($8)
41245		 subu  $10,$9,$2
41246		 sb    $10,0x00($24)
41247		 sltu  $16,$9,$2       	 # Set Carry
41248		 xor   $17,$9,$2
41249		 xor   $25,$10,$9
41250		 and   $17,$17,$25
41251		 srl   $17,$17,7
41252		 andi  $17,$17,0x01     	 # Set Overflow
41253		 seb  $25,$10
41254		 slt   $19,$25,$0        	 # Set Sign
41255		 sltiu $18,$25,1         	 # Set Zero
41256		 or    $20,$0,$16      	 # Copy Carry to X
41257		 addiu $15,$15,-4
41258		 bgez  $15,3f
41259		 lhu   $24,0x00($23)    	 # Delay slot
41260		 j     MainExit
41261	3:
41262		 sll   $7,$24,2         	 # Delay slot
41263		 addu  $7,$7,$30
41264		 lw    $7,0x00($7)
41265		 jr    $7
41266		 nop                    	 # Delay slot
41267
41268OP0_9010:				#:
41269		 addiu $23,$23,2
41270
41271		 andi  $8,$24,0x07
41272		 srl   $24,$24,7
41273		 andi  $24,$24,0x1C
41274		 addu  $24,$24,$21
41275		 lb    $9,0x00($24)
41276		 sll   $8,$8,2
41277		 addu  $8,$8,$21
41278		 lw    $14,0x20($8)
41279		 lw    $25,0x7C($21)
41280		 sw    $15,m68k_ICount
41281		 sw    $9,0x44($29)
41282		 sw    $24,0x40($29)
41283		 or    $4,$0,$14
41284		 jalr  $25
41285		 sw    $23,0x4C($21)    	 # Delay slot
41286		 lw    $24,0x40($29)
41287		 lw    $9,0x44($29)
41288		 lw    $15,m68k_ICount
41289		 seb   $2,$2
41290		 subu  $10,$9,$2
41291		 sb    $10,0x00($24)
41292		 sltu  $16,$9,$2       	 # Set Carry
41293		 xor   $17,$9,$2
41294		 xor   $25,$10,$9
41295		 and   $17,$17,$25
41296		 srl   $17,$17,7
41297		 andi  $17,$17,0x01     	 # Set Overflow
41298		 seb  $25,$10
41299		 slt   $19,$25,$0        	 # Set Sign
41300		 sltiu $18,$25,1         	 # Set Zero
41301		 or    $20,$0,$16      	 # Copy Carry to X
41302		 addiu $15,$15,-8
41303		 bgez  $15,3f
41304		 lhu   $24,0x00($23)    	 # Delay slot
41305		 j     MainExit
41306	3:
41307		 sll   $7,$24,2         	 # Delay slot
41308		 addu  $7,$7,$30
41309		 lw    $7,0x00($7)
41310		 jr    $7
41311		 nop                    	 # Delay slot
41312
41313OP0_9018:				#:
41314		 addiu $23,$23,2
41315
41316		 andi  $8,$24,0x07
41317		 srl   $24,$24,7
41318		 andi  $24,$24,0x1C
41319		 addu  $24,$24,$21
41320		 lb    $9,0x00($24)
41321		 sll   $8,$8,2
41322		 addu  $8,$8,$21
41323		 lw    $14,0x20($8)
41324		 addiu $25,$14,1
41325		 sw    $25,0x20($8)
41326		 lw    $25,0x7C($21)
41327		 sw    $15,m68k_ICount
41328		 sw    $9,0x44($29)
41329		 sw    $24,0x40($29)
41330		 or    $4,$0,$14
41331		 jalr  $25
41332		 sw    $23,0x4C($21)    	 # Delay slot
41333		 lw    $24,0x40($29)
41334		 lw    $9,0x44($29)
41335		 lw    $15,m68k_ICount
41336		 seb   $2,$2
41337		 subu  $10,$9,$2
41338		 sb    $10,0x00($24)
41339		 sltu  $16,$9,$2       	 # Set Carry
41340		 xor   $17,$9,$2
41341		 xor   $25,$10,$9
41342		 and   $17,$17,$25
41343		 srl   $17,$17,7
41344		 andi  $17,$17,0x01     	 # Set Overflow
41345		 seb  $25,$10
41346		 slt   $19,$25,$0        	 # Set Sign
41347		 sltiu $18,$25,1         	 # Set Zero
41348		 or    $20,$0,$16      	 # Copy Carry to X
41349		 addiu $15,$15,-8
41350		 bgez  $15,3f
41351		 lhu   $24,0x00($23)    	 # Delay slot
41352		 j     MainExit
41353	3:
41354		 sll   $7,$24,2         	 # Delay slot
41355		 addu  $7,$7,$30
41356		 lw    $7,0x00($7)
41357		 jr    $7
41358		 nop                    	 # Delay slot
41359
41360OP0_901f:				#:
41361		 addiu $23,$23,2
41362
41363		 srl   $24,$24,7
41364		 andi  $24,$24,0x1C
41365		 addu  $24,$24,$21
41366		 lb    $9,0x00($24)
41367		 lw    $14,0x3C($21)    	 # Get A7
41368		 addiu $25,$14,2
41369		 sw    $25,0x3C($21)
41370		 lw    $25,0x7C($21)
41371		 sw    $15,m68k_ICount
41372		 sw    $9,0x44($29)
41373		 sw    $24,0x40($29)
41374		 or    $4,$0,$14
41375		 jalr  $25
41376		 sw    $23,0x4C($21)    	 # Delay slot
41377		 lw    $24,0x40($29)
41378		 lw    $9,0x44($29)
41379		 lw    $15,m68k_ICount
41380		 seb   $2,$2
41381		 subu  $10,$9,$2
41382		 sb    $10,0x00($24)
41383		 sltu  $16,$9,$2       	 # Set Carry
41384		 xor   $17,$9,$2
41385		 xor   $25,$10,$9
41386		 and   $17,$17,$25
41387		 srl   $17,$17,7
41388		 andi  $17,$17,0x01     	 # Set Overflow
41389		 seb  $25,$10
41390		 slt   $19,$25,$0        	 # Set Sign
41391		 sltiu $18,$25,1         	 # Set Zero
41392		 or    $20,$0,$16      	 # Copy Carry to X
41393		 addiu $15,$15,-8
41394		 bgez  $15,3f
41395		 lhu   $24,0x00($23)    	 # Delay slot
41396		 j     MainExit
41397	3:
41398		 sll   $7,$24,2         	 # Delay slot
41399		 addu  $7,$7,$30
41400		 lw    $7,0x00($7)
41401		 jr    $7
41402		 nop                    	 # Delay slot
41403
41404OP0_9020:				#:
41405		 addiu $23,$23,2
41406
41407		 andi  $8,$24,0x07
41408		 srl   $24,$24,7
41409		 andi  $24,$24,0x1C
41410		 addu  $24,$24,$21
41411		 lb    $9,0x00($24)
41412		 sll   $8,$8,2
41413		 addu  $8,$8,$21
41414		 lw    $14,0x20($8)
41415		 addiu $14,$14,-1
41416		 sw    $14,0x20($8)
41417		 lw    $25,0x7C($21)
41418		 sw    $15,m68k_ICount
41419		 sw    $9,0x44($29)
41420		 sw    $24,0x40($29)
41421		 or    $4,$0,$14
41422		 jalr  $25
41423		 sw    $23,0x4C($21)    	 # Delay slot
41424		 lw    $24,0x40($29)
41425		 lw    $9,0x44($29)
41426		 lw    $15,m68k_ICount
41427		 seb   $2,$2
41428		 subu  $10,$9,$2
41429		 sb    $10,0x00($24)
41430		 sltu  $16,$9,$2       	 # Set Carry
41431		 xor   $17,$9,$2
41432		 xor   $25,$10,$9
41433		 and   $17,$17,$25
41434		 srl   $17,$17,7
41435		 andi  $17,$17,0x01     	 # Set Overflow
41436		 seb  $25,$10
41437		 slt   $19,$25,$0        	 # Set Sign
41438		 sltiu $18,$25,1         	 # Set Zero
41439		 or    $20,$0,$16      	 # Copy Carry to X
41440		 addiu $15,$15,-10
41441		 bgez  $15,3f
41442		 lhu   $24,0x00($23)    	 # Delay slot
41443		 j     MainExit
41444	3:
41445		 sll   $7,$24,2         	 # Delay slot
41446		 addu  $7,$7,$30
41447		 lw    $7,0x00($7)
41448		 jr    $7
41449		 nop                    	 # Delay slot
41450
41451OP0_9027:				#:
41452		 addiu $23,$23,2
41453
41454		 srl   $24,$24,7
41455		 andi  $24,$24,0x1C
41456		 addu  $24,$24,$21
41457		 lb    $9,0x00($24)
41458		 lw    $14,0x3C($21)    	 # Get A7
41459		 addiu $14,$14,-2
41460		 sw    $14,0x3C($21)
41461		 lw    $25,0x7C($21)
41462		 sw    $15,m68k_ICount
41463		 sw    $9,0x44($29)
41464		 sw    $24,0x40($29)
41465		 or    $4,$0,$14
41466		 jalr  $25
41467		 sw    $23,0x4C($21)    	 # Delay slot
41468		 lw    $24,0x40($29)
41469		 lw    $9,0x44($29)
41470		 lw    $15,m68k_ICount
41471		 seb   $2,$2
41472		 subu  $10,$9,$2
41473		 sb    $10,0x00($24)
41474		 sltu  $16,$9,$2       	 # Set Carry
41475		 xor   $17,$9,$2
41476		 xor   $25,$10,$9
41477		 and   $17,$17,$25
41478		 srl   $17,$17,7
41479		 andi  $17,$17,0x01     	 # Set Overflow
41480		 seb  $25,$10
41481		 slt   $19,$25,$0        	 # Set Sign
41482		 sltiu $18,$25,1         	 # Set Zero
41483		 or    $20,$0,$16      	 # Copy Carry to X
41484		 addiu $15,$15,-10
41485		 bgez  $15,3f
41486		 lhu   $24,0x00($23)    	 # Delay slot
41487		 j     MainExit
41488	3:
41489		 sll   $7,$24,2         	 # Delay slot
41490		 addu  $7,$7,$30
41491		 lw    $7,0x00($7)
41492		 jr    $7
41493		 nop                    	 # Delay slot
41494
41495OP0_9028:				#:
41496		 addiu $23,$23,2
41497
41498		 andi  $8,$24,0x07
41499		 srl   $24,$24,7
41500		 andi  $24,$24,0x1C
41501		 addu  $24,$24,$21
41502		 lb    $9,0x00($24)
41503		 lh    $7,0x00($23)
41504		 sll   $8,$8,2
41505		 addu  $8,$8,$21
41506		 lw    $14,0x20($8)
41507		 addiu $23,$23,2
41508		 addu  $14,$14,$7
41509		 lw    $25,0x7C($21)
41510		 sw    $15,m68k_ICount
41511		 sw    $9,0x44($29)
41512		 sw    $24,0x40($29)
41513		 or    $4,$0,$14
41514		 jalr  $25
41515		 sw    $23,0x4C($21)    	 # Delay slot
41516		 lw    $24,0x40($29)
41517		 lw    $9,0x44($29)
41518		 lw    $15,m68k_ICount
41519		 seb   $2,$2
41520		 subu  $10,$9,$2
41521		 sb    $10,0x00($24)
41522		 sltu  $16,$9,$2       	 # Set Carry
41523		 xor   $17,$9,$2
41524		 xor   $25,$10,$9
41525		 and   $17,$17,$25
41526		 srl   $17,$17,7
41527		 andi  $17,$17,0x01     	 # Set Overflow
41528		 seb  $25,$10
41529		 slt   $19,$25,$0        	 # Set Sign
41530		 sltiu $18,$25,1         	 # Set Zero
41531		 or    $20,$0,$16      	 # Copy Carry to X
41532		 addiu $15,$15,-12
41533		 bgez  $15,3f
41534		 lhu   $24,0x00($23)    	 # Delay slot
41535		 j     MainExit
41536	3:
41537		 sll   $7,$24,2         	 # Delay slot
41538		 addu  $7,$7,$30
41539		 lw    $7,0x00($7)
41540		 jr    $7
41541		 nop                    	 # Delay slot
41542
41543OP0_9030:				#:
41544		 addiu $23,$23,2
41545
41546		 andi  $8,$24,0x07
41547		 srl   $24,$24,7
41548		 andi  $24,$24,0x1C
41549		 addu  $24,$24,$21
41550		 lb    $9,0x00($24)
41551		 sll   $8,$8,2
41552		 addu  $8,$8,$21
41553		 lw    $14,0x20($8)
41554		 lhu   $7,0x00($23)
41555		 addiu $23,$23,2
41556		 seb   $6,$7
41557		 or    $25,$0,$7
41558		 srl   $7,$7,12
41559		 andi  $25,$25,0x0800
41560		 sll   $7,$7,2
41561		 addu  $7,$7,$21
41562		 bne   $25,$0,0f
41563		 lw    $25,0x00($7)      	 # Delay slot
41564		 seh   $25,$25
41565	0:
41566		 addu  $25,$14,$25
41567		 addu  $14,$25,$6
41568		 lw    $25,0x7C($21)
41569		 sw    $15,m68k_ICount
41570		 sw    $9,0x44($29)
41571		 sw    $24,0x40($29)
41572		 or    $4,$0,$14
41573		 jalr  $25
41574		 sw    $23,0x4C($21)    	 # Delay slot
41575		 lw    $24,0x40($29)
41576		 lw    $9,0x44($29)
41577		 lw    $15,m68k_ICount
41578		 seb   $2,$2
41579		 subu  $10,$9,$2
41580		 sb    $10,0x00($24)
41581		 sltu  $16,$9,$2       	 # Set Carry
41582		 xor   $17,$9,$2
41583		 xor   $25,$10,$9
41584		 and   $17,$17,$25
41585		 srl   $17,$17,7
41586		 andi  $17,$17,0x01     	 # Set Overflow
41587		 seb  $25,$10
41588		 slt   $19,$25,$0        	 # Set Sign
41589		 sltiu $18,$25,1         	 # Set Zero
41590		 or    $20,$0,$16      	 # Copy Carry to X
41591		 addiu $15,$15,-14
41592		 bgez  $15,3f
41593		 lhu   $24,0x00($23)    	 # Delay slot
41594		 j     MainExit
41595	3:
41596		 sll   $7,$24,2         	 # Delay slot
41597		 addu  $7,$7,$30
41598		 lw    $7,0x00($7)
41599		 jr    $7
41600		 nop                    	 # Delay slot
41601
41602OP0_9038:				#:
41603		 addiu $23,$23,2
41604
41605		 srl   $24,$24,7
41606		 andi  $24,$24,0x1C
41607		 addu  $24,$24,$21
41608		 lb    $9,0x00($24)
41609		 lh    $14,0x00($23)
41610		 addiu $23,$23,2
41611		 lw    $25,0x7C($21)
41612		 sw    $15,m68k_ICount
41613		 sw    $9,0x44($29)
41614		 sw    $24,0x40($29)
41615		 or    $4,$0,$14
41616		 jalr  $25
41617		 sw    $23,0x4C($21)    	 # Delay slot
41618		 lw    $24,0x40($29)
41619		 lw    $9,0x44($29)
41620		 lw    $15,m68k_ICount
41621		 seb   $2,$2
41622		 subu  $10,$9,$2
41623		 sb    $10,0x00($24)
41624		 sltu  $16,$9,$2       	 # Set Carry
41625		 xor   $17,$9,$2
41626		 xor   $25,$10,$9
41627		 and   $17,$17,$25
41628		 srl   $17,$17,7
41629		 andi  $17,$17,0x01     	 # Set Overflow
41630		 seb  $25,$10
41631		 slt   $19,$25,$0        	 # Set Sign
41632		 sltiu $18,$25,1         	 # Set Zero
41633		 or    $20,$0,$16      	 # Copy Carry to X
41634		 addiu $15,$15,-12
41635		 bgez  $15,3f
41636		 lhu   $24,0x00($23)    	 # Delay slot
41637		 j     MainExit
41638	3:
41639		 sll   $7,$24,2         	 # Delay slot
41640		 addu  $7,$7,$30
41641		 lw    $7,0x00($7)
41642		 jr    $7
41643		 nop                    	 # Delay slot
41644
41645OP0_9039:				#:
41646		 addiu $23,$23,2
41647
41648		 srl   $24,$24,7
41649		 andi  $24,$24,0x1C
41650		 addu  $24,$24,$21
41651		 lb    $9,0x00($24)
41652		 lhu   $14,0x00($23)
41653		 lhu   $25,0x02($23)
41654		 sll   $14,$14,16
41655		 or    $14,$14,$25
41656		 addiu $23,$23,4
41657		 lw    $25,0x7C($21)
41658		 sw    $15,m68k_ICount
41659		 sw    $9,0x44($29)
41660		 sw    $24,0x40($29)
41661		 or    $4,$0,$14
41662		 jalr  $25
41663		 sw    $23,0x4C($21)    	 # Delay slot
41664		 lw    $24,0x40($29)
41665		 lw    $9,0x44($29)
41666		 lw    $15,m68k_ICount
41667		 seb   $2,$2
41668		 subu  $10,$9,$2
41669		 sb    $10,0x00($24)
41670		 sltu  $16,$9,$2       	 # Set Carry
41671		 xor   $17,$9,$2
41672		 xor   $25,$10,$9
41673		 and   $17,$17,$25
41674		 srl   $17,$17,7
41675		 andi  $17,$17,0x01     	 # Set Overflow
41676		 seb  $25,$10
41677		 slt   $19,$25,$0        	 # Set Sign
41678		 sltiu $18,$25,1         	 # Set Zero
41679		 or    $20,$0,$16      	 # Copy Carry to X
41680		 addiu $15,$15,-16
41681		 bgez  $15,3f
41682		 lhu   $24,0x00($23)    	 # Delay slot
41683		 j     MainExit
41684	3:
41685		 sll   $7,$24,2         	 # Delay slot
41686		 addu  $7,$7,$30
41687		 lw    $7,0x00($7)
41688		 jr    $7
41689		 nop                    	 # Delay slot
41690
41691OP0_903a:				#:
41692		 addiu $23,$23,2
41693
41694		 srl   $24,$24,7
41695		 andi  $24,$24,0x1C
41696		 addu  $24,$24,$21
41697		 lb    $9,0x00($24)
41698		 lh    $7,0x00($23)
41699		 subu  $25,$23,$22
41700		 addu  $14,$25,$7       	 # Add Offset to PC
41701		 addiu $23,$23,2
41702		 lw    $25,0x98($21)
41703		 sw    $15,m68k_ICount
41704		 sw    $9,0x44($29)
41705		 sw    $24,0x40($29)
41706		 or    $4,$0,$14
41707		 jalr  $25
41708		 sw    $23,0x4C($21)    	 # Delay slot
41709		 lw    $24,0x40($29)
41710		 lw    $9,0x44($29)
41711		 lw    $15,m68k_ICount
41712		 seb   $2,$2
41713		 subu  $10,$9,$2
41714		 sb    $10,0x00($24)
41715		 sltu  $16,$9,$2       	 # Set Carry
41716		 xor   $17,$9,$2
41717		 xor   $25,$10,$9
41718		 and   $17,$17,$25
41719		 srl   $17,$17,7
41720		 andi  $17,$17,0x01     	 # Set Overflow
41721		 seb  $25,$10
41722		 slt   $19,$25,$0        	 # Set Sign
41723		 sltiu $18,$25,1         	 # Set Zero
41724		 or    $20,$0,$16      	 # Copy Carry to X
41725		 addiu $15,$15,-12
41726		 bgez  $15,3f
41727		 lhu   $24,0x00($23)    	 # Delay slot
41728		 j     MainExit
41729	3:
41730		 sll   $7,$24,2         	 # Delay slot
41731		 addu  $7,$7,$30
41732		 lw    $7,0x00($7)
41733		 jr    $7
41734		 nop                    	 # Delay slot
41735
41736OP0_903b:				#:
41737		 addiu $23,$23,2
41738
41739		 srl   $24,$24,7
41740		 andi  $24,$24,0x1C
41741		 addu  $24,$24,$21
41742		 lb    $9,0x00($24)
41743		 subu  $14,$23,$22       	 # Get PC
41744		 lhu   $7,0x00($23)
41745		 addiu $23,$23,2
41746		 seb   $6,$7
41747		 or    $25,$0,$7
41748		 srl   $7,$7,12
41749		 andi  $25,$25,0x0800
41750		 sll   $7,$7,2
41751		 addu  $7,$7,$21
41752		 bne   $25,$0,0f
41753		 lw    $25,0x00($7)      	 # Delay slot
41754		 seh   $25,$25
41755	0:
41756		 addu  $25,$14,$25
41757		 addu  $14,$25,$6
41758		 lw    $25,0x98($21)
41759		 sw    $15,m68k_ICount
41760		 sw    $9,0x44($29)
41761		 sw    $24,0x40($29)
41762		 or    $4,$0,$14
41763		 jalr  $25
41764		 sw    $23,0x4C($21)    	 # Delay slot
41765		 lw    $24,0x40($29)
41766		 lw    $9,0x44($29)
41767		 lw    $15,m68k_ICount
41768		 seb   $2,$2
41769		 subu  $10,$9,$2
41770		 sb    $10,0x00($24)
41771		 sltu  $16,$9,$2       	 # Set Carry
41772		 xor   $17,$9,$2
41773		 xor   $25,$10,$9
41774		 and   $17,$17,$25
41775		 srl   $17,$17,7
41776		 andi  $17,$17,0x01     	 # Set Overflow
41777		 seb  $25,$10
41778		 slt   $19,$25,$0        	 # Set Sign
41779		 sltiu $18,$25,1         	 # Set Zero
41780		 or    $20,$0,$16      	 # Copy Carry to X
41781		 addiu $15,$15,-14
41782		 bgez  $15,3f
41783		 lhu   $24,0x00($23)    	 # Delay slot
41784		 j     MainExit
41785	3:
41786		 sll   $7,$24,2         	 # Delay slot
41787		 addu  $7,$7,$30
41788		 lw    $7,0x00($7)
41789		 jr    $7
41790		 nop                    	 # Delay slot
41791
41792OP0_903c:				#:
41793		 addiu $23,$23,2
41794
41795		 srl   $24,$24,7
41796		 andi  $24,$24,0x1C
41797		 addu  $24,$24,$21
41798		 lb    $9,0x00($24)
41799		 lb    $2,0x00($23)
41800		 addiu $23,$23,2
41801		 subu  $10,$9,$2
41802		 sb    $10,0x00($24)
41803		 sltu  $16,$9,$2       	 # Set Carry
41804		 xor   $17,$9,$2
41805		 xor   $25,$10,$9
41806		 and   $17,$17,$25
41807		 srl   $17,$17,7
41808		 andi  $17,$17,0x01     	 # Set Overflow
41809		 seb  $25,$10
41810		 slt   $19,$25,$0        	 # Set Sign
41811		 sltiu $18,$25,1         	 # Set Zero
41812		 or    $20,$0,$16      	 # Copy Carry to X
41813		 addiu $15,$15,-4
41814		 bgez  $15,3f
41815		 lhu   $24,0x00($23)    	 # Delay slot
41816		 j     MainExit
41817	3:
41818		 sll   $7,$24,2         	 # Delay slot
41819		 addu  $7,$7,$30
41820		 lw    $7,0x00($7)
41821		 jr    $7
41822		 nop                    	 # Delay slot
41823
41824OP0_9040:				#:
41825		 addiu $23,$23,2
41826
41827		 andi  $8,$24,0x0f
41828		 srl   $24,$24,7
41829		 andi  $24,$24,0x1C
41830		 addu  $24,$24,$21
41831		 lh    $9,0x00($24)
41832		 sll   $8,$8,2
41833		 addu  $8,$8,$21
41834		 lh    $2,0x00($8)
41835		 subu  $10,$9,$2
41836		 sh    $10,0x00($24)
41837		 sltu  $16,$9,$2       	 # Set Carry
41838		 xor   $17,$9,$2
41839		 xor   $25,$10,$9
41840		 and   $17,$17,$25
41841		 srl   $17,$17,15
41842		 andi  $17,$17,0x01     	 # Set Overflow
41843		 seh  $25,$10
41844		 slt   $19,$25,$0        	 # Set Sign
41845		 sltiu $18,$25,1         	 # Set Zero
41846		 or    $20,$0,$16      	 # Copy Carry to X
41847		 addiu $15,$15,-4
41848		 bgez  $15,3f
41849		 lhu   $24,0x00($23)    	 # Delay slot
41850		 j     MainExit
41851	3:
41852		 sll   $7,$24,2         	 # Delay slot
41853		 addu  $7,$7,$30
41854		 lw    $7,0x00($7)
41855		 jr    $7
41856		 nop                    	 # Delay slot
41857
41858OP0_9050:				#:
41859		 addiu $23,$23,2
41860
41861		 andi  $8,$24,0x07
41862		 srl   $24,$24,7
41863		 andi  $24,$24,0x1C
41864		 addu  $24,$24,$21
41865		 lh    $9,0x00($24)
41866		 sll   $8,$8,2
41867		 addu  $8,$8,$21
41868		 lw    $14,0x20($8)
41869		 lw    $25,0x80($21)
41870		 sw    $15,m68k_ICount
41871		 sw    $9,0x44($29)
41872		 sw    $24,0x40($29)
41873		 or    $4,$0,$14
41874		 jalr  $25
41875		 sw    $23,0x4C($21)    	 # Delay slot
41876		 lw    $24,0x40($29)
41877		 lw    $9,0x44($29)
41878		 lw    $15,m68k_ICount
41879		 seh   $2,$2
41880		 subu  $10,$9,$2
41881		 sh    $10,0x00($24)
41882		 sltu  $16,$9,$2       	 # Set Carry
41883		 xor   $17,$9,$2
41884		 xor   $25,$10,$9
41885		 and   $17,$17,$25
41886		 srl   $17,$17,15
41887		 andi  $17,$17,0x01     	 # Set Overflow
41888		 seh  $25,$10
41889		 slt   $19,$25,$0        	 # Set Sign
41890		 sltiu $18,$25,1         	 # Set Zero
41891		 or    $20,$0,$16      	 # Copy Carry to X
41892		 addiu $15,$15,-8
41893		 bgez  $15,3f
41894		 lhu   $24,0x00($23)    	 # Delay slot
41895		 j     MainExit
41896	3:
41897		 sll   $7,$24,2         	 # Delay slot
41898		 addu  $7,$7,$30
41899		 lw    $7,0x00($7)
41900		 jr    $7
41901		 nop                    	 # Delay slot
41902
41903OP0_9058:				#:
41904		 addiu $23,$23,2
41905
41906		 andi  $8,$24,0x07
41907		 srl   $24,$24,7
41908		 andi  $24,$24,0x1C
41909		 addu  $24,$24,$21
41910		 lh    $9,0x00($24)
41911		 sll   $8,$8,2
41912		 addu  $8,$8,$21
41913		 lw    $14,0x20($8)
41914		 addiu $25,$14,2
41915		 sw    $25,0x20($8)
41916		 lw    $25,0x80($21)
41917		 sw    $15,m68k_ICount
41918		 sw    $9,0x44($29)
41919		 sw    $24,0x40($29)
41920		 or    $4,$0,$14
41921		 jalr  $25
41922		 sw    $23,0x4C($21)    	 # Delay slot
41923		 lw    $24,0x40($29)
41924		 lw    $9,0x44($29)
41925		 lw    $15,m68k_ICount
41926		 seh   $2,$2
41927		 subu  $10,$9,$2
41928		 sh    $10,0x00($24)
41929		 sltu  $16,$9,$2       	 # Set Carry
41930		 xor   $17,$9,$2
41931		 xor   $25,$10,$9
41932		 and   $17,$17,$25
41933		 srl   $17,$17,15
41934		 andi  $17,$17,0x01     	 # Set Overflow
41935		 seh  $25,$10
41936		 slt   $19,$25,$0        	 # Set Sign
41937		 sltiu $18,$25,1         	 # Set Zero
41938		 or    $20,$0,$16      	 # Copy Carry to X
41939		 addiu $15,$15,-8
41940		 bgez  $15,3f
41941		 lhu   $24,0x00($23)    	 # Delay slot
41942		 j     MainExit
41943	3:
41944		 sll   $7,$24,2         	 # Delay slot
41945		 addu  $7,$7,$30
41946		 lw    $7,0x00($7)
41947		 jr    $7
41948		 nop                    	 # Delay slot
41949
41950OP0_9060:				#:
41951		 addiu $23,$23,2
41952
41953		 andi  $8,$24,0x07
41954		 srl   $24,$24,7
41955		 andi  $24,$24,0x1C
41956		 addu  $24,$24,$21
41957		 lh    $9,0x00($24)
41958		 sll   $8,$8,2
41959		 addu  $8,$8,$21
41960		 lw    $14,0x20($8)
41961		 addiu $14,$14,-2
41962		 sw    $14,0x20($8)
41963		 lw    $25,0x80($21)
41964		 sw    $15,m68k_ICount
41965		 sw    $9,0x44($29)
41966		 sw    $24,0x40($29)
41967		 or    $4,$0,$14
41968		 jalr  $25
41969		 sw    $23,0x4C($21)    	 # Delay slot
41970		 lw    $24,0x40($29)
41971		 lw    $9,0x44($29)
41972		 lw    $15,m68k_ICount
41973		 seh   $2,$2
41974		 subu  $10,$9,$2
41975		 sh    $10,0x00($24)
41976		 sltu  $16,$9,$2       	 # Set Carry
41977		 xor   $17,$9,$2
41978		 xor   $25,$10,$9
41979		 and   $17,$17,$25
41980		 srl   $17,$17,15
41981		 andi  $17,$17,0x01     	 # Set Overflow
41982		 seh  $25,$10
41983		 slt   $19,$25,$0        	 # Set Sign
41984		 sltiu $18,$25,1         	 # Set Zero
41985		 or    $20,$0,$16      	 # Copy Carry to X
41986		 addiu $15,$15,-10
41987		 bgez  $15,3f
41988		 lhu   $24,0x00($23)    	 # Delay slot
41989		 j     MainExit
41990	3:
41991		 sll   $7,$24,2         	 # Delay slot
41992		 addu  $7,$7,$30
41993		 lw    $7,0x00($7)
41994		 jr    $7
41995		 nop                    	 # Delay slot
41996
41997OP0_9068:				#:
41998		 addiu $23,$23,2
41999
42000		 andi  $8,$24,0x07
42001		 srl   $24,$24,7
42002		 andi  $24,$24,0x1C
42003		 addu  $24,$24,$21
42004		 lh    $9,0x00($24)
42005		 lh    $7,0x00($23)
42006		 sll   $8,$8,2
42007		 addu  $8,$8,$21
42008		 lw    $14,0x20($8)
42009		 addiu $23,$23,2
42010		 addu  $14,$14,$7
42011		 lw    $25,0x80($21)
42012		 sw    $15,m68k_ICount
42013		 sw    $9,0x44($29)
42014		 sw    $24,0x40($29)
42015		 or    $4,$0,$14
42016		 jalr  $25
42017		 sw    $23,0x4C($21)    	 # Delay slot
42018		 lw    $24,0x40($29)
42019		 lw    $9,0x44($29)
42020		 lw    $15,m68k_ICount
42021		 seh   $2,$2
42022		 subu  $10,$9,$2
42023		 sh    $10,0x00($24)
42024		 sltu  $16,$9,$2       	 # Set Carry
42025		 xor   $17,$9,$2
42026		 xor   $25,$10,$9
42027		 and   $17,$17,$25
42028		 srl   $17,$17,15
42029		 andi  $17,$17,0x01     	 # Set Overflow
42030		 seh  $25,$10
42031		 slt   $19,$25,$0        	 # Set Sign
42032		 sltiu $18,$25,1         	 # Set Zero
42033		 or    $20,$0,$16      	 # Copy Carry to X
42034		 addiu $15,$15,-12
42035		 bgez  $15,3f
42036		 lhu   $24,0x00($23)    	 # Delay slot
42037		 j     MainExit
42038	3:
42039		 sll   $7,$24,2         	 # Delay slot
42040		 addu  $7,$7,$30
42041		 lw    $7,0x00($7)
42042		 jr    $7
42043		 nop                    	 # Delay slot
42044
42045OP0_9070:				#:
42046		 addiu $23,$23,2
42047
42048		 andi  $8,$24,0x07
42049		 srl   $24,$24,7
42050		 andi  $24,$24,0x1C
42051		 addu  $24,$24,$21
42052		 lh    $9,0x00($24)
42053		 sll   $8,$8,2
42054		 addu  $8,$8,$21
42055		 lw    $14,0x20($8)
42056		 lhu   $7,0x00($23)
42057		 addiu $23,$23,2
42058		 seb   $6,$7
42059		 or    $25,$0,$7
42060		 srl   $7,$7,12
42061		 andi  $25,$25,0x0800
42062		 sll   $7,$7,2
42063		 addu  $7,$7,$21
42064		 bne   $25,$0,0f
42065		 lw    $25,0x00($7)      	 # Delay slot
42066		 seh   $25,$25
42067	0:
42068		 addu  $25,$14,$25
42069		 addu  $14,$25,$6
42070		 lw    $25,0x80($21)
42071		 sw    $15,m68k_ICount
42072		 sw    $9,0x44($29)
42073		 sw    $24,0x40($29)
42074		 or    $4,$0,$14
42075		 jalr  $25
42076		 sw    $23,0x4C($21)    	 # Delay slot
42077		 lw    $24,0x40($29)
42078		 lw    $9,0x44($29)
42079		 lw    $15,m68k_ICount
42080		 seh   $2,$2
42081		 subu  $10,$9,$2
42082		 sh    $10,0x00($24)
42083		 sltu  $16,$9,$2       	 # Set Carry
42084		 xor   $17,$9,$2
42085		 xor   $25,$10,$9
42086		 and   $17,$17,$25
42087		 srl   $17,$17,15
42088		 andi  $17,$17,0x01     	 # Set Overflow
42089		 seh  $25,$10
42090		 slt   $19,$25,$0        	 # Set Sign
42091		 sltiu $18,$25,1         	 # Set Zero
42092		 or    $20,$0,$16      	 # Copy Carry to X
42093		 addiu $15,$15,-14
42094		 bgez  $15,3f
42095		 lhu   $24,0x00($23)    	 # Delay slot
42096		 j     MainExit
42097	3:
42098		 sll   $7,$24,2         	 # Delay slot
42099		 addu  $7,$7,$30
42100		 lw    $7,0x00($7)
42101		 jr    $7
42102		 nop                    	 # Delay slot
42103
42104OP0_9078:				#:
42105		 addiu $23,$23,2
42106
42107		 srl   $24,$24,7
42108		 andi  $24,$24,0x1C
42109		 addu  $24,$24,$21
42110		 lh    $9,0x00($24)
42111		 lh    $14,0x00($23)
42112		 addiu $23,$23,2
42113		 lw    $25,0x80($21)
42114		 sw    $15,m68k_ICount
42115		 sw    $9,0x44($29)
42116		 sw    $24,0x40($29)
42117		 or    $4,$0,$14
42118		 jalr  $25
42119		 sw    $23,0x4C($21)    	 # Delay slot
42120		 lw    $24,0x40($29)
42121		 lw    $9,0x44($29)
42122		 lw    $15,m68k_ICount
42123		 seh   $2,$2
42124		 subu  $10,$9,$2
42125		 sh    $10,0x00($24)
42126		 sltu  $16,$9,$2       	 # Set Carry
42127		 xor   $17,$9,$2
42128		 xor   $25,$10,$9
42129		 and   $17,$17,$25
42130		 srl   $17,$17,15
42131		 andi  $17,$17,0x01     	 # Set Overflow
42132		 seh  $25,$10
42133		 slt   $19,$25,$0        	 # Set Sign
42134		 sltiu $18,$25,1         	 # Set Zero
42135		 or    $20,$0,$16      	 # Copy Carry to X
42136		 addiu $15,$15,-12
42137		 bgez  $15,3f
42138		 lhu   $24,0x00($23)    	 # Delay slot
42139		 j     MainExit
42140	3:
42141		 sll   $7,$24,2         	 # Delay slot
42142		 addu  $7,$7,$30
42143		 lw    $7,0x00($7)
42144		 jr    $7
42145		 nop                    	 # Delay slot
42146
42147OP0_9079:				#:
42148		 addiu $23,$23,2
42149
42150		 srl   $24,$24,7
42151		 andi  $24,$24,0x1C
42152		 addu  $24,$24,$21
42153		 lh    $9,0x00($24)
42154		 lhu   $14,0x00($23)
42155		 lhu   $25,0x02($23)
42156		 sll   $14,$14,16
42157		 or    $14,$14,$25
42158		 addiu $23,$23,4
42159		 lw    $25,0x80($21)
42160		 sw    $15,m68k_ICount
42161		 sw    $9,0x44($29)
42162		 sw    $24,0x40($29)
42163		 or    $4,$0,$14
42164		 jalr  $25
42165		 sw    $23,0x4C($21)    	 # Delay slot
42166		 lw    $24,0x40($29)
42167		 lw    $9,0x44($29)
42168		 lw    $15,m68k_ICount
42169		 seh   $2,$2
42170		 subu  $10,$9,$2
42171		 sh    $10,0x00($24)
42172		 sltu  $16,$9,$2       	 # Set Carry
42173		 xor   $17,$9,$2
42174		 xor   $25,$10,$9
42175		 and   $17,$17,$25
42176		 srl   $17,$17,15
42177		 andi  $17,$17,0x01     	 # Set Overflow
42178		 seh  $25,$10
42179		 slt   $19,$25,$0        	 # Set Sign
42180		 sltiu $18,$25,1         	 # Set Zero
42181		 or    $20,$0,$16      	 # Copy Carry to X
42182		 addiu $15,$15,-16
42183		 bgez  $15,3f
42184		 lhu   $24,0x00($23)    	 # Delay slot
42185		 j     MainExit
42186	3:
42187		 sll   $7,$24,2         	 # Delay slot
42188		 addu  $7,$7,$30
42189		 lw    $7,0x00($7)
42190		 jr    $7
42191		 nop                    	 # Delay slot
42192
42193OP0_907a:				#:
42194		 addiu $23,$23,2
42195
42196		 srl   $24,$24,7
42197		 andi  $24,$24,0x1C
42198		 addu  $24,$24,$21
42199		 lh    $9,0x00($24)
42200		 lh    $7,0x00($23)
42201		 subu  $25,$23,$22
42202		 addu  $14,$25,$7       	 # Add Offset to PC
42203		 addiu $23,$23,2
42204		 lw    $25,0x9C($21)
42205		 sw    $15,m68k_ICount
42206		 sw    $9,0x44($29)
42207		 sw    $24,0x40($29)
42208		 or    $4,$0,$14
42209		 jalr  $25
42210		 sw    $23,0x4C($21)    	 # Delay slot
42211		 lw    $24,0x40($29)
42212		 lw    $9,0x44($29)
42213		 lw    $15,m68k_ICount
42214		 seh   $2,$2
42215		 subu  $10,$9,$2
42216		 sh    $10,0x00($24)
42217		 sltu  $16,$9,$2       	 # Set Carry
42218		 xor   $17,$9,$2
42219		 xor   $25,$10,$9
42220		 and   $17,$17,$25
42221		 srl   $17,$17,15
42222		 andi  $17,$17,0x01     	 # Set Overflow
42223		 seh  $25,$10
42224		 slt   $19,$25,$0        	 # Set Sign
42225		 sltiu $18,$25,1         	 # Set Zero
42226		 or    $20,$0,$16      	 # Copy Carry to X
42227		 addiu $15,$15,-12
42228		 bgez  $15,3f
42229		 lhu   $24,0x00($23)    	 # Delay slot
42230		 j     MainExit
42231	3:
42232		 sll   $7,$24,2         	 # Delay slot
42233		 addu  $7,$7,$30
42234		 lw    $7,0x00($7)
42235		 jr    $7
42236		 nop                    	 # Delay slot
42237
42238OP0_907b:				#:
42239		 addiu $23,$23,2
42240
42241		 srl   $24,$24,7
42242		 andi  $24,$24,0x1C
42243		 addu  $24,$24,$21
42244		 lh    $9,0x00($24)
42245		 subu  $14,$23,$22       	 # Get PC
42246		 lhu   $7,0x00($23)
42247		 addiu $23,$23,2
42248		 seb   $6,$7
42249		 or    $25,$0,$7
42250		 srl   $7,$7,12
42251		 andi  $25,$25,0x0800
42252		 sll   $7,$7,2
42253		 addu  $7,$7,$21
42254		 bne   $25,$0,0f
42255		 lw    $25,0x00($7)      	 # Delay slot
42256		 seh   $25,$25
42257	0:
42258		 addu  $25,$14,$25
42259		 addu  $14,$25,$6
42260		 lw    $25,0x9C($21)
42261		 sw    $15,m68k_ICount
42262		 sw    $9,0x44($29)
42263		 sw    $24,0x40($29)
42264		 or    $4,$0,$14
42265		 jalr  $25
42266		 sw    $23,0x4C($21)    	 # Delay slot
42267		 lw    $24,0x40($29)
42268		 lw    $9,0x44($29)
42269		 lw    $15,m68k_ICount
42270		 seh   $2,$2
42271		 subu  $10,$9,$2
42272		 sh    $10,0x00($24)
42273		 sltu  $16,$9,$2       	 # Set Carry
42274		 xor   $17,$9,$2
42275		 xor   $25,$10,$9
42276		 and   $17,$17,$25
42277		 srl   $17,$17,15
42278		 andi  $17,$17,0x01     	 # Set Overflow
42279		 seh  $25,$10
42280		 slt   $19,$25,$0        	 # Set Sign
42281		 sltiu $18,$25,1         	 # Set Zero
42282		 or    $20,$0,$16      	 # Copy Carry to X
42283		 addiu $15,$15,-14
42284		 bgez  $15,3f
42285		 lhu   $24,0x00($23)    	 # Delay slot
42286		 j     MainExit
42287	3:
42288		 sll   $7,$24,2         	 # Delay slot
42289		 addu  $7,$7,$30
42290		 lw    $7,0x00($7)
42291		 jr    $7
42292		 nop                    	 # Delay slot
42293
42294OP0_907c:				#:
42295		 addiu $23,$23,2
42296
42297		 srl   $24,$24,7
42298		 andi  $24,$24,0x1C
42299		 addu  $24,$24,$21
42300		 lh    $9,0x00($24)
42301		 lh    $2,0x00($23)
42302		 addiu $23,$23,2
42303		 subu  $10,$9,$2
42304		 sh    $10,0x00($24)
42305		 sltu  $16,$9,$2       	 # Set Carry
42306		 xor   $17,$9,$2
42307		 xor   $25,$10,$9
42308		 and   $17,$17,$25
42309		 srl   $17,$17,15
42310		 andi  $17,$17,0x01     	 # Set Overflow
42311		 seh  $25,$10
42312		 slt   $19,$25,$0        	 # Set Sign
42313		 sltiu $18,$25,1         	 # Set Zero
42314		 or    $20,$0,$16      	 # Copy Carry to X
42315		 addiu $15,$15,-4
42316		 bgez  $15,3f
42317		 lhu   $24,0x00($23)    	 # Delay slot
42318		 j     MainExit
42319	3:
42320		 sll   $7,$24,2         	 # Delay slot
42321		 addu  $7,$7,$30
42322		 lw    $7,0x00($7)
42323		 jr    $7
42324		 nop                    	 # Delay slot
42325
42326OP0_9080:				#:
42327		 addiu $23,$23,2
42328
42329		 andi  $8,$24,0x0f
42330		 srl   $24,$24,7
42331		 andi  $24,$24,0x1C
42332		 addu  $24,$24,$21
42333		 lw    $9,0x00($24)
42334		 sll   $8,$8,2
42335		 addu  $8,$8,$21
42336		 lw    $2,0x00($8)
42337		 subu  $10,$9,$2
42338		 sw    $10,0x00($24)
42339		 sltu  $16,$9,$2       	 # Set Carry
42340		 xor   $17,$9,$2
42341		 xor   $25,$10,$9
42342		 and   $17,$17,$25
42343		 srl   $17,$17,31        	 # Set Overflow
42344		 slt   $19,$10,$0        	 # Set Sign
42345		 sltiu $18,$10,1         	 # Set Zero
42346		 or    $20,$0,$16      	 # Copy Carry to X
42347		 addiu $15,$15,-8
42348		 bgez  $15,3f
42349		 lhu   $24,0x00($23)    	 # Delay slot
42350		 j     MainExit
42351	3:
42352		 sll   $7,$24,2         	 # Delay slot
42353		 addu  $7,$7,$30
42354		 lw    $7,0x00($7)
42355		 jr    $7
42356		 nop                    	 # Delay slot
42357
42358OP0_9090:				#:
42359		 addiu $23,$23,2
42360
42361		 andi  $8,$24,0x07
42362		 srl   $24,$24,7
42363		 andi  $24,$24,0x1C
42364		 addu  $24,$24,$21
42365		 lw    $9,0x00($24)
42366		 sll   $8,$8,2
42367		 addu  $8,$8,$21
42368		 lw    $14,0x20($8)
42369		 lw    $25,0x84($21)
42370		 sw    $15,m68k_ICount
42371		 sw    $9,0x44($29)
42372		 sw    $24,0x40($29)
42373		 or    $4,$0,$14
42374		 jalr  $25
42375		 sw    $23,0x4C($21)    	 # Delay slot
42376		 lw    $24,0x40($29)
42377		 lw    $9,0x44($29)
42378		 lw    $15,m68k_ICount
42379		 subu  $10,$9,$2
42380		 sw    $10,0x00($24)
42381		 sltu  $16,$9,$2       	 # Set Carry
42382		 xor   $17,$9,$2
42383		 xor   $25,$10,$9
42384		 and   $17,$17,$25
42385		 srl   $17,$17,31        	 # Set Overflow
42386		 slt   $19,$10,$0        	 # Set Sign
42387		 sltiu $18,$10,1         	 # Set Zero
42388		 or    $20,$0,$16      	 # Copy Carry to X
42389		 addiu $15,$15,-14
42390		 bgez  $15,3f
42391		 lhu   $24,0x00($23)    	 # Delay slot
42392		 j     MainExit
42393	3:
42394		 sll   $7,$24,2         	 # Delay slot
42395		 addu  $7,$7,$30
42396		 lw    $7,0x00($7)
42397		 jr    $7
42398		 nop                    	 # Delay slot
42399
42400OP0_9098:				#:
42401		 addiu $23,$23,2
42402
42403		 andi  $8,$24,0x07
42404		 srl   $24,$24,7
42405		 andi  $24,$24,0x1C
42406		 addu  $24,$24,$21
42407		 lw    $9,0x00($24)
42408		 sll   $8,$8,2
42409		 addu  $8,$8,$21
42410		 lw    $14,0x20($8)
42411		 addiu $25,$14,4
42412		 sw    $25,0x20($8)
42413		 lw    $25,0x84($21)
42414		 sw    $15,m68k_ICount
42415		 sw    $9,0x44($29)
42416		 sw    $24,0x40($29)
42417		 or    $4,$0,$14
42418		 jalr  $25
42419		 sw    $23,0x4C($21)    	 # Delay slot
42420		 lw    $24,0x40($29)
42421		 lw    $9,0x44($29)
42422		 lw    $15,m68k_ICount
42423		 subu  $10,$9,$2
42424		 sw    $10,0x00($24)
42425		 sltu  $16,$9,$2       	 # Set Carry
42426		 xor   $17,$9,$2
42427		 xor   $25,$10,$9
42428		 and   $17,$17,$25
42429		 srl   $17,$17,31        	 # Set Overflow
42430		 slt   $19,$10,$0        	 # Set Sign
42431		 sltiu $18,$10,1         	 # Set Zero
42432		 or    $20,$0,$16      	 # Copy Carry to X
42433		 addiu $15,$15,-14
42434		 bgez  $15,3f
42435		 lhu   $24,0x00($23)    	 # Delay slot
42436		 j     MainExit
42437	3:
42438		 sll   $7,$24,2         	 # Delay slot
42439		 addu  $7,$7,$30
42440		 lw    $7,0x00($7)
42441		 jr    $7
42442		 nop                    	 # Delay slot
42443
42444OP0_90a0:				#:
42445		 addiu $23,$23,2
42446
42447		 andi  $8,$24,0x07
42448		 srl   $24,$24,7
42449		 andi  $24,$24,0x1C
42450		 addu  $24,$24,$21
42451		 lw    $9,0x00($24)
42452		 sll   $8,$8,2
42453		 addu  $8,$8,$21
42454		 lw    $14,0x20($8)
42455		 addiu $14,$14,-4
42456		 sw    $14,0x20($8)
42457		 lw    $25,0x84($21)
42458		 sw    $15,m68k_ICount
42459		 sw    $9,0x44($29)
42460		 sw    $24,0x40($29)
42461		 or    $4,$0,$14
42462		 jalr  $25
42463		 sw    $23,0x4C($21)    	 # Delay slot
42464		 lw    $24,0x40($29)
42465		 lw    $9,0x44($29)
42466		 lw    $15,m68k_ICount
42467		 subu  $10,$9,$2
42468		 sw    $10,0x00($24)
42469		 sltu  $16,$9,$2       	 # Set Carry
42470		 xor   $17,$9,$2
42471		 xor   $25,$10,$9
42472		 and   $17,$17,$25
42473		 srl   $17,$17,31        	 # Set Overflow
42474		 slt   $19,$10,$0        	 # Set Sign
42475		 sltiu $18,$10,1         	 # Set Zero
42476		 or    $20,$0,$16      	 # Copy Carry to X
42477		 addiu $15,$15,-16
42478		 bgez  $15,3f
42479		 lhu   $24,0x00($23)    	 # Delay slot
42480		 j     MainExit
42481	3:
42482		 sll   $7,$24,2         	 # Delay slot
42483		 addu  $7,$7,$30
42484		 lw    $7,0x00($7)
42485		 jr    $7
42486		 nop                    	 # Delay slot
42487
42488OP0_90a8:				#:
42489		 addiu $23,$23,2
42490
42491		 andi  $8,$24,0x07
42492		 srl   $24,$24,7
42493		 andi  $24,$24,0x1C
42494		 addu  $24,$24,$21
42495		 lw    $9,0x00($24)
42496		 lh    $7,0x00($23)
42497		 sll   $8,$8,2
42498		 addu  $8,$8,$21
42499		 lw    $14,0x20($8)
42500		 addiu $23,$23,2
42501		 addu  $14,$14,$7
42502		 lw    $25,0x84($21)
42503		 sw    $15,m68k_ICount
42504		 sw    $9,0x44($29)
42505		 sw    $24,0x40($29)
42506		 or    $4,$0,$14
42507		 jalr  $25
42508		 sw    $23,0x4C($21)    	 # Delay slot
42509		 lw    $24,0x40($29)
42510		 lw    $9,0x44($29)
42511		 lw    $15,m68k_ICount
42512		 subu  $10,$9,$2
42513		 sw    $10,0x00($24)
42514		 sltu  $16,$9,$2       	 # Set Carry
42515		 xor   $17,$9,$2
42516		 xor   $25,$10,$9
42517		 and   $17,$17,$25
42518		 srl   $17,$17,31        	 # Set Overflow
42519		 slt   $19,$10,$0        	 # Set Sign
42520		 sltiu $18,$10,1         	 # Set Zero
42521		 or    $20,$0,$16      	 # Copy Carry to X
42522		 addiu $15,$15,-18
42523		 bgez  $15,3f
42524		 lhu   $24,0x00($23)    	 # Delay slot
42525		 j     MainExit
42526	3:
42527		 sll   $7,$24,2         	 # Delay slot
42528		 addu  $7,$7,$30
42529		 lw    $7,0x00($7)
42530		 jr    $7
42531		 nop                    	 # Delay slot
42532
42533OP0_90b0:				#:
42534		 addiu $23,$23,2
42535
42536		 andi  $8,$24,0x07
42537		 srl   $24,$24,7
42538		 andi  $24,$24,0x1C
42539		 addu  $24,$24,$21
42540		 lw    $9,0x00($24)
42541		 sll   $8,$8,2
42542		 addu  $8,$8,$21
42543		 lw    $14,0x20($8)
42544		 lhu   $7,0x00($23)
42545		 addiu $23,$23,2
42546		 seb   $6,$7
42547		 or    $25,$0,$7
42548		 srl   $7,$7,12
42549		 andi  $25,$25,0x0800
42550		 sll   $7,$7,2
42551		 addu  $7,$7,$21
42552		 bne   $25,$0,0f
42553		 lw    $25,0x00($7)      	 # Delay slot
42554		 seh   $25,$25
42555	0:
42556		 addu  $25,$14,$25
42557		 addu  $14,$25,$6
42558		 lw    $25,0x84($21)
42559		 sw    $15,m68k_ICount
42560		 sw    $9,0x44($29)
42561		 sw    $24,0x40($29)
42562		 or    $4,$0,$14
42563		 jalr  $25
42564		 sw    $23,0x4C($21)    	 # Delay slot
42565		 lw    $24,0x40($29)
42566		 lw    $9,0x44($29)
42567		 lw    $15,m68k_ICount
42568		 subu  $10,$9,$2
42569		 sw    $10,0x00($24)
42570		 sltu  $16,$9,$2       	 # Set Carry
42571		 xor   $17,$9,$2
42572		 xor   $25,$10,$9
42573		 and   $17,$17,$25
42574		 srl   $17,$17,31        	 # Set Overflow
42575		 slt   $19,$10,$0        	 # Set Sign
42576		 sltiu $18,$10,1         	 # Set Zero
42577		 or    $20,$0,$16      	 # Copy Carry to X
42578		 addiu $15,$15,-20
42579		 bgez  $15,3f
42580		 lhu   $24,0x00($23)    	 # Delay slot
42581		 j     MainExit
42582	3:
42583		 sll   $7,$24,2         	 # Delay slot
42584		 addu  $7,$7,$30
42585		 lw    $7,0x00($7)
42586		 jr    $7
42587		 nop                    	 # Delay slot
42588
42589OP0_90b8:				#:
42590		 addiu $23,$23,2
42591
42592		 srl   $24,$24,7
42593		 andi  $24,$24,0x1C
42594		 addu  $24,$24,$21
42595		 lw    $9,0x00($24)
42596		 lh    $14,0x00($23)
42597		 addiu $23,$23,2
42598		 lw    $25,0x84($21)
42599		 sw    $15,m68k_ICount
42600		 sw    $9,0x44($29)
42601		 sw    $24,0x40($29)
42602		 or    $4,$0,$14
42603		 jalr  $25
42604		 sw    $23,0x4C($21)    	 # Delay slot
42605		 lw    $24,0x40($29)
42606		 lw    $9,0x44($29)
42607		 lw    $15,m68k_ICount
42608		 subu  $10,$9,$2
42609		 sw    $10,0x00($24)
42610		 sltu  $16,$9,$2       	 # Set Carry
42611		 xor   $17,$9,$2
42612		 xor   $25,$10,$9
42613		 and   $17,$17,$25
42614		 srl   $17,$17,31        	 # Set Overflow
42615		 slt   $19,$10,$0        	 # Set Sign
42616		 sltiu $18,$10,1         	 # Set Zero
42617		 or    $20,$0,$16      	 # Copy Carry to X
42618		 addiu $15,$15,-18
42619		 bgez  $15,3f
42620		 lhu   $24,0x00($23)    	 # Delay slot
42621		 j     MainExit
42622	3:
42623		 sll   $7,$24,2         	 # Delay slot
42624		 addu  $7,$7,$30
42625		 lw    $7,0x00($7)
42626		 jr    $7
42627		 nop                    	 # Delay slot
42628
42629OP0_90b9:				#:
42630		 addiu $23,$23,2
42631
42632		 srl   $24,$24,7
42633		 andi  $24,$24,0x1C
42634		 addu  $24,$24,$21
42635		 lw    $9,0x00($24)
42636		 lhu   $14,0x00($23)
42637		 lhu   $25,0x02($23)
42638		 sll   $14,$14,16
42639		 or    $14,$14,$25
42640		 addiu $23,$23,4
42641		 lw    $25,0x84($21)
42642		 sw    $15,m68k_ICount
42643		 sw    $9,0x44($29)
42644		 sw    $24,0x40($29)
42645		 or    $4,$0,$14
42646		 jalr  $25
42647		 sw    $23,0x4C($21)    	 # Delay slot
42648		 lw    $24,0x40($29)
42649		 lw    $9,0x44($29)
42650		 lw    $15,m68k_ICount
42651		 subu  $10,$9,$2
42652		 sw    $10,0x00($24)
42653		 sltu  $16,$9,$2       	 # Set Carry
42654		 xor   $17,$9,$2
42655		 xor   $25,$10,$9
42656		 and   $17,$17,$25
42657		 srl   $17,$17,31        	 # Set Overflow
42658		 slt   $19,$10,$0        	 # Set Sign
42659		 sltiu $18,$10,1         	 # Set Zero
42660		 or    $20,$0,$16      	 # Copy Carry to X
42661		 addiu $15,$15,-22
42662		 bgez  $15,3f
42663		 lhu   $24,0x00($23)    	 # Delay slot
42664		 j     MainExit
42665	3:
42666		 sll   $7,$24,2         	 # Delay slot
42667		 addu  $7,$7,$30
42668		 lw    $7,0x00($7)
42669		 jr    $7
42670		 nop                    	 # Delay slot
42671
42672OP0_90ba:				#:
42673		 addiu $23,$23,2
42674
42675		 srl   $24,$24,7
42676		 andi  $24,$24,0x1C
42677		 addu  $24,$24,$21
42678		 lw    $9,0x00($24)
42679		 lh    $7,0x00($23)
42680		 subu  $25,$23,$22
42681		 addu  $14,$25,$7       	 # Add Offset to PC
42682		 addiu $23,$23,2
42683		 lw    $25,0xA0($21)
42684		 sw    $15,m68k_ICount
42685		 sw    $9,0x44($29)
42686		 sw    $24,0x40($29)
42687		 or    $4,$0,$14
42688		 jalr  $25
42689		 sw    $23,0x4C($21)    	 # Delay slot
42690		 lw    $24,0x40($29)
42691		 lw    $9,0x44($29)
42692		 lw    $15,m68k_ICount
42693		 subu  $10,$9,$2
42694		 sw    $10,0x00($24)
42695		 sltu  $16,$9,$2       	 # Set Carry
42696		 xor   $17,$9,$2
42697		 xor   $25,$10,$9
42698		 and   $17,$17,$25
42699		 srl   $17,$17,31        	 # Set Overflow
42700		 slt   $19,$10,$0        	 # Set Sign
42701		 sltiu $18,$10,1         	 # Set Zero
42702		 or    $20,$0,$16      	 # Copy Carry to X
42703		 addiu $15,$15,-18
42704		 bgez  $15,3f
42705		 lhu   $24,0x00($23)    	 # Delay slot
42706		 j     MainExit
42707	3:
42708		 sll   $7,$24,2         	 # Delay slot
42709		 addu  $7,$7,$30
42710		 lw    $7,0x00($7)
42711		 jr    $7
42712		 nop                    	 # Delay slot
42713
42714OP0_90bb:				#:
42715		 addiu $23,$23,2
42716
42717		 srl   $24,$24,7
42718		 andi  $24,$24,0x1C
42719		 addu  $24,$24,$21
42720		 lw    $9,0x00($24)
42721		 subu  $14,$23,$22       	 # Get PC
42722		 lhu   $7,0x00($23)
42723		 addiu $23,$23,2
42724		 seb   $6,$7
42725		 or    $25,$0,$7
42726		 srl   $7,$7,12
42727		 andi  $25,$25,0x0800
42728		 sll   $7,$7,2
42729		 addu  $7,$7,$21
42730		 bne   $25,$0,0f
42731		 lw    $25,0x00($7)      	 # Delay slot
42732		 seh   $25,$25
42733	0:
42734		 addu  $25,$14,$25
42735		 addu  $14,$25,$6
42736		 lw    $25,0xA0($21)
42737		 sw    $15,m68k_ICount
42738		 sw    $9,0x44($29)
42739		 sw    $24,0x40($29)
42740		 or    $4,$0,$14
42741		 jalr  $25
42742		 sw    $23,0x4C($21)    	 # Delay slot
42743		 lw    $24,0x40($29)
42744		 lw    $9,0x44($29)
42745		 lw    $15,m68k_ICount
42746		 subu  $10,$9,$2
42747		 sw    $10,0x00($24)
42748		 sltu  $16,$9,$2       	 # Set Carry
42749		 xor   $17,$9,$2
42750		 xor   $25,$10,$9
42751		 and   $17,$17,$25
42752		 srl   $17,$17,31        	 # Set Overflow
42753		 slt   $19,$10,$0        	 # Set Sign
42754		 sltiu $18,$10,1         	 # Set Zero
42755		 or    $20,$0,$16      	 # Copy Carry to X
42756		 addiu $15,$15,-20
42757		 bgez  $15,3f
42758		 lhu   $24,0x00($23)    	 # Delay slot
42759		 j     MainExit
42760	3:
42761		 sll   $7,$24,2         	 # Delay slot
42762		 addu  $7,$7,$30
42763		 lw    $7,0x00($7)
42764		 jr    $7
42765		 nop                    	 # Delay slot
42766
42767OP0_90bc:				#:
42768		 addiu $23,$23,2
42769
42770		 srl   $24,$24,7
42771		 andi  $24,$24,0x1C
42772		 addu  $24,$24,$21
42773		 lw    $9,0x00($24)
42774		 lhu   $2,0x00($23)
42775		 lhu   $25,0x02($23)
42776		 sll   $2,$2,16
42777		 or    $2,$2,$25
42778		 addiu $23,$23,4
42779		 subu  $10,$9,$2
42780		 sw    $10,0x00($24)
42781		 sltu  $16,$9,$2       	 # Set Carry
42782		 xor   $17,$9,$2
42783		 xor   $25,$10,$9
42784		 and   $17,$17,$25
42785		 srl   $17,$17,31        	 # Set Overflow
42786		 slt   $19,$10,$0        	 # Set Sign
42787		 sltiu $18,$10,1         	 # Set Zero
42788		 or    $20,$0,$16      	 # Copy Carry to X
42789		 addiu $15,$15,-6
42790		 bgez  $15,3f
42791		 lhu   $24,0x00($23)    	 # Delay slot
42792		 j     MainExit
42793	3:
42794		 sll   $7,$24,2         	 # Delay slot
42795		 addu  $7,$7,$30
42796		 lw    $7,0x00($7)
42797		 jr    $7
42798		 nop                    	 # Delay slot
42799
42800OP0_9110:				#:
42801		 addiu $23,$23,2
42802
42803		 andi  $8,$24,0x07
42804		 srl   $24,$24,7
42805		 andi  $24,$24,0x1C
42806		 addu  $24,$24,$21
42807		 lb    $9,0x00($24)
42808		 sll   $8,$8,2
42809		 addu  $8,$8,$21
42810		 lw    $14,0x20($8)
42811		 lw    $25,0x7C($21)
42812		 sw    $15,m68k_ICount
42813		 sw    $9,0x44($29)
42814		 sw    $14,0x40($29)
42815		 sw    $24,0x3C($29)
42816		 or    $4,$0,$14
42817		 jalr  $25
42818		 sw    $23,0x4C($21)    	 # Delay slot
42819		 lw    $24,0x3C($29)
42820		 lw    $14,0x40($29)
42821		 lw    $9,0x44($29)
42822		 lw    $15,m68k_ICount
42823		 seb   $10,$2
42824		 subu  $2,$10,$9
42825		 sltu  $16,$10,$9       	 # Set Carry
42826		 xor   $17,$10,$9
42827		 xor   $25,$2,$10
42828		 and   $17,$17,$25
42829		 srl   $17,$17,7
42830		 andi  $17,$17,0x01     	 # Set Overflow
42831		 seb  $25,$2
42832		 slt   $19,$25,$0        	 # Set Sign
42833		 sltiu $18,$25,1         	 # Set Zero
42834		 or    $20,$0,$16      	 # Copy Carry to X
42835		 lw    $25,0x88($21)
42836		 sw    $15,m68k_ICount
42837		 sw    $9,0x44($29)
42838		 sw    $14,0x40($29)
42839		 sw    $24,0x3C($29)
42840		 or    $5,$0,$2
42841		 or    $4,$0,$14
42842		 jalr  $25
42843		 sw    $23,0x4C($21)    	 # Delay slot
42844		 lw    $24,0x3C($29)
42845		 lw    $14,0x40($29)
42846		 lw    $9,0x44($29)
42847		 lw    $15,m68k_ICount
42848		 addiu $15,$15,-12
42849		 bgez  $15,3f
42850		 lhu   $24,0x00($23)    	 # Delay slot
42851		 j     MainExit
42852	3:
42853		 sll   $7,$24,2         	 # Delay slot
42854		 addu  $7,$7,$30
42855		 lw    $7,0x00($7)
42856		 jr    $7
42857		 nop                    	 # Delay slot
42858
42859OP0_9118:				#:
42860		 addiu $23,$23,2
42861
42862		 andi  $8,$24,0x07
42863		 srl   $24,$24,7
42864		 andi  $24,$24,0x1C
42865		 addu  $24,$24,$21
42866		 lb    $9,0x00($24)
42867		 sll   $8,$8,2
42868		 addu  $8,$8,$21
42869		 lw    $14,0x20($8)
42870		 addiu $25,$14,1
42871		 sw    $25,0x20($8)
42872		 lw    $25,0x7C($21)
42873		 sw    $15,m68k_ICount
42874		 sw    $9,0x44($29)
42875		 sw    $14,0x40($29)
42876		 sw    $24,0x3C($29)
42877		 or    $4,$0,$14
42878		 jalr  $25
42879		 sw    $23,0x4C($21)    	 # Delay slot
42880		 lw    $24,0x3C($29)
42881		 lw    $14,0x40($29)
42882		 lw    $9,0x44($29)
42883		 lw    $15,m68k_ICount
42884		 seb   $10,$2
42885		 subu  $2,$10,$9
42886		 sltu  $16,$10,$9       	 # Set Carry
42887		 xor   $17,$10,$9
42888		 xor   $25,$2,$10
42889		 and   $17,$17,$25
42890		 srl   $17,$17,7
42891		 andi  $17,$17,0x01     	 # Set Overflow
42892		 seb  $25,$2
42893		 slt   $19,$25,$0        	 # Set Sign
42894		 sltiu $18,$25,1         	 # Set Zero
42895		 or    $20,$0,$16      	 # Copy Carry to X
42896		 lw    $25,0x88($21)
42897		 sw    $15,m68k_ICount
42898		 sw    $9,0x44($29)
42899		 sw    $14,0x40($29)
42900		 sw    $24,0x3C($29)
42901		 or    $5,$0,$2
42902		 or    $4,$0,$14
42903		 jalr  $25
42904		 sw    $23,0x4C($21)    	 # Delay slot
42905		 lw    $24,0x3C($29)
42906		 lw    $14,0x40($29)
42907		 lw    $9,0x44($29)
42908		 lw    $15,m68k_ICount
42909		 addiu $15,$15,-12
42910		 bgez  $15,3f
42911		 lhu   $24,0x00($23)    	 # Delay slot
42912		 j     MainExit
42913	3:
42914		 sll   $7,$24,2         	 # Delay slot
42915		 addu  $7,$7,$30
42916		 lw    $7,0x00($7)
42917		 jr    $7
42918		 nop                    	 # Delay slot
42919
42920OP0_911f:				#:
42921		 addiu $23,$23,2
42922
42923		 srl   $24,$24,7
42924		 andi  $24,$24,0x1C
42925		 addu  $24,$24,$21
42926		 lb    $9,0x00($24)
42927		 lw    $14,0x3C($21)    	 # Get A7
42928		 addiu $25,$14,2
42929		 sw    $25,0x3C($21)
42930		 lw    $25,0x7C($21)
42931		 sw    $15,m68k_ICount
42932		 sw    $9,0x44($29)
42933		 sw    $14,0x40($29)
42934		 sw    $24,0x3C($29)
42935		 or    $4,$0,$14
42936		 jalr  $25
42937		 sw    $23,0x4C($21)    	 # Delay slot
42938		 lw    $24,0x3C($29)
42939		 lw    $14,0x40($29)
42940		 lw    $9,0x44($29)
42941		 lw    $15,m68k_ICount
42942		 seb   $10,$2
42943		 subu  $2,$10,$9
42944		 sltu  $16,$10,$9       	 # Set Carry
42945		 xor   $17,$10,$9
42946		 xor   $25,$2,$10
42947		 and   $17,$17,$25
42948		 srl   $17,$17,7
42949		 andi  $17,$17,0x01     	 # Set Overflow
42950		 seb  $25,$2
42951		 slt   $19,$25,$0        	 # Set Sign
42952		 sltiu $18,$25,1         	 # Set Zero
42953		 or    $20,$0,$16      	 # Copy Carry to X
42954		 lw    $25,0x88($21)
42955		 sw    $15,m68k_ICount
42956		 sw    $9,0x44($29)
42957		 sw    $14,0x40($29)
42958		 sw    $24,0x3C($29)
42959		 or    $5,$0,$2
42960		 or    $4,$0,$14
42961		 jalr  $25
42962		 sw    $23,0x4C($21)    	 # Delay slot
42963		 lw    $24,0x3C($29)
42964		 lw    $14,0x40($29)
42965		 lw    $9,0x44($29)
42966		 lw    $15,m68k_ICount
42967		 addiu $15,$15,-12
42968		 bgez  $15,3f
42969		 lhu   $24,0x00($23)    	 # Delay slot
42970		 j     MainExit
42971	3:
42972		 sll   $7,$24,2         	 # Delay slot
42973		 addu  $7,$7,$30
42974		 lw    $7,0x00($7)
42975		 jr    $7
42976		 nop                    	 # Delay slot
42977
42978OP0_9120:				#:
42979		 addiu $23,$23,2
42980
42981		 andi  $8,$24,0x07
42982		 srl   $24,$24,7
42983		 andi  $24,$24,0x1C
42984		 addu  $24,$24,$21
42985		 lb    $9,0x00($24)
42986		 sll   $8,$8,2
42987		 addu  $8,$8,$21
42988		 lw    $14,0x20($8)
42989		 addiu $14,$14,-1
42990		 sw    $14,0x20($8)
42991		 lw    $25,0x7C($21)
42992		 sw    $15,m68k_ICount
42993		 sw    $9,0x44($29)
42994		 sw    $14,0x40($29)
42995		 sw    $24,0x3C($29)
42996		 or    $4,$0,$14
42997		 jalr  $25
42998		 sw    $23,0x4C($21)    	 # Delay slot
42999		 lw    $24,0x3C($29)
43000		 lw    $14,0x40($29)
43001		 lw    $9,0x44($29)
43002		 lw    $15,m68k_ICount
43003		 seb   $10,$2
43004		 subu  $2,$10,$9
43005		 sltu  $16,$10,$9       	 # Set Carry
43006		 xor   $17,$10,$9
43007		 xor   $25,$2,$10
43008		 and   $17,$17,$25
43009		 srl   $17,$17,7
43010		 andi  $17,$17,0x01     	 # Set Overflow
43011		 seb  $25,$2
43012		 slt   $19,$25,$0        	 # Set Sign
43013		 sltiu $18,$25,1         	 # Set Zero
43014		 or    $20,$0,$16      	 # Copy Carry to X
43015		 lw    $25,0x88($21)
43016		 sw    $15,m68k_ICount
43017		 sw    $9,0x44($29)
43018		 sw    $14,0x40($29)
43019		 sw    $24,0x3C($29)
43020		 or    $5,$0,$2
43021		 or    $4,$0,$14
43022		 jalr  $25
43023		 sw    $23,0x4C($21)    	 # Delay slot
43024		 lw    $24,0x3C($29)
43025		 lw    $14,0x40($29)
43026		 lw    $9,0x44($29)
43027		 lw    $15,m68k_ICount
43028		 addiu $15,$15,-14
43029		 bgez  $15,3f
43030		 lhu   $24,0x00($23)    	 # Delay slot
43031		 j     MainExit
43032	3:
43033		 sll   $7,$24,2         	 # Delay slot
43034		 addu  $7,$7,$30
43035		 lw    $7,0x00($7)
43036		 jr    $7
43037		 nop                    	 # Delay slot
43038
43039OP0_9127:				#:
43040		 addiu $23,$23,2
43041
43042		 srl   $24,$24,7
43043		 andi  $24,$24,0x1C
43044		 addu  $24,$24,$21
43045		 lb    $9,0x00($24)
43046		 lw    $14,0x3C($21)    	 # Get A7
43047		 addiu $14,$14,-2
43048		 sw    $14,0x3C($21)
43049		 lw    $25,0x7C($21)
43050		 sw    $15,m68k_ICount
43051		 sw    $9,0x44($29)
43052		 sw    $14,0x40($29)
43053		 sw    $24,0x3C($29)
43054		 or    $4,$0,$14
43055		 jalr  $25
43056		 sw    $23,0x4C($21)    	 # Delay slot
43057		 lw    $24,0x3C($29)
43058		 lw    $14,0x40($29)
43059		 lw    $9,0x44($29)
43060		 lw    $15,m68k_ICount
43061		 seb   $10,$2
43062		 subu  $2,$10,$9
43063		 sltu  $16,$10,$9       	 # Set Carry
43064		 xor   $17,$10,$9
43065		 xor   $25,$2,$10
43066		 and   $17,$17,$25
43067		 srl   $17,$17,7
43068		 andi  $17,$17,0x01     	 # Set Overflow
43069		 seb  $25,$2
43070		 slt   $19,$25,$0        	 # Set Sign
43071		 sltiu $18,$25,1         	 # Set Zero
43072		 or    $20,$0,$16      	 # Copy Carry to X
43073		 lw    $25,0x88($21)
43074		 sw    $15,m68k_ICount
43075		 sw    $9,0x44($29)
43076		 sw    $14,0x40($29)
43077		 sw    $24,0x3C($29)
43078		 or    $5,$0,$2
43079		 or    $4,$0,$14
43080		 jalr  $25
43081		 sw    $23,0x4C($21)    	 # Delay slot
43082		 lw    $24,0x3C($29)
43083		 lw    $14,0x40($29)
43084		 lw    $9,0x44($29)
43085		 lw    $15,m68k_ICount
43086		 addiu $15,$15,-14
43087		 bgez  $15,3f
43088		 lhu   $24,0x00($23)    	 # Delay slot
43089		 j     MainExit
43090	3:
43091		 sll   $7,$24,2         	 # Delay slot
43092		 addu  $7,$7,$30
43093		 lw    $7,0x00($7)
43094		 jr    $7
43095		 nop                    	 # Delay slot
43096
43097OP0_9128:				#:
43098		 addiu $23,$23,2
43099
43100		 andi  $8,$24,0x07
43101		 srl   $24,$24,7
43102		 andi  $24,$24,0x1C
43103		 addu  $24,$24,$21
43104		 lb    $9,0x00($24)
43105		 lh    $7,0x00($23)
43106		 sll   $8,$8,2
43107		 addu  $8,$8,$21
43108		 lw    $14,0x20($8)
43109		 addiu $23,$23,2
43110		 addu  $14,$14,$7
43111		 lw    $25,0x7C($21)
43112		 sw    $15,m68k_ICount
43113		 sw    $9,0x44($29)
43114		 sw    $14,0x40($29)
43115		 sw    $24,0x3C($29)
43116		 or    $4,$0,$14
43117		 jalr  $25
43118		 sw    $23,0x4C($21)    	 # Delay slot
43119		 lw    $24,0x3C($29)
43120		 lw    $14,0x40($29)
43121		 lw    $9,0x44($29)
43122		 lw    $15,m68k_ICount
43123		 seb   $10,$2
43124		 subu  $2,$10,$9
43125		 sltu  $16,$10,$9       	 # Set Carry
43126		 xor   $17,$10,$9
43127		 xor   $25,$2,$10
43128		 and   $17,$17,$25
43129		 srl   $17,$17,7
43130		 andi  $17,$17,0x01     	 # Set Overflow
43131		 seb  $25,$2
43132		 slt   $19,$25,$0        	 # Set Sign
43133		 sltiu $18,$25,1         	 # Set Zero
43134		 or    $20,$0,$16      	 # Copy Carry to X
43135		 lw    $25,0x88($21)
43136		 sw    $15,m68k_ICount
43137		 sw    $9,0x44($29)
43138		 sw    $14,0x40($29)
43139		 sw    $24,0x3C($29)
43140		 or    $5,$0,$2
43141		 or    $4,$0,$14
43142		 jalr  $25
43143		 sw    $23,0x4C($21)    	 # Delay slot
43144		 lw    $24,0x3C($29)
43145		 lw    $14,0x40($29)
43146		 lw    $9,0x44($29)
43147		 lw    $15,m68k_ICount
43148		 addiu $15,$15,-16
43149		 bgez  $15,3f
43150		 lhu   $24,0x00($23)    	 # Delay slot
43151		 j     MainExit
43152	3:
43153		 sll   $7,$24,2         	 # Delay slot
43154		 addu  $7,$7,$30
43155		 lw    $7,0x00($7)
43156		 jr    $7
43157		 nop                    	 # Delay slot
43158
43159OP0_9130:				#:
43160		 addiu $23,$23,2
43161
43162		 andi  $8,$24,0x07
43163		 srl   $24,$24,7
43164		 andi  $24,$24,0x1C
43165		 addu  $24,$24,$21
43166		 lb    $9,0x00($24)
43167		 sll   $8,$8,2
43168		 addu  $8,$8,$21
43169		 lw    $14,0x20($8)
43170		 lhu   $7,0x00($23)
43171		 addiu $23,$23,2
43172		 seb   $6,$7
43173		 or    $25,$0,$7
43174		 srl   $7,$7,12
43175		 andi  $25,$25,0x0800
43176		 sll   $7,$7,2
43177		 addu  $7,$7,$21
43178		 bne   $25,$0,0f
43179		 lw    $25,0x00($7)      	 # Delay slot
43180		 seh   $25,$25
43181	0:
43182		 addu  $25,$14,$25
43183		 addu  $14,$25,$6
43184		 lw    $25,0x7C($21)
43185		 sw    $15,m68k_ICount
43186		 sw    $9,0x44($29)
43187		 sw    $14,0x40($29)
43188		 sw    $24,0x3C($29)
43189		 or    $4,$0,$14
43190		 jalr  $25
43191		 sw    $23,0x4C($21)    	 # Delay slot
43192		 lw    $24,0x3C($29)
43193		 lw    $14,0x40($29)
43194		 lw    $9,0x44($29)
43195		 lw    $15,m68k_ICount
43196		 seb   $10,$2
43197		 subu  $2,$10,$9
43198		 sltu  $16,$10,$9       	 # Set Carry
43199		 xor   $17,$10,$9
43200		 xor   $25,$2,$10
43201		 and   $17,$17,$25
43202		 srl   $17,$17,7
43203		 andi  $17,$17,0x01     	 # Set Overflow
43204		 seb  $25,$2
43205		 slt   $19,$25,$0        	 # Set Sign
43206		 sltiu $18,$25,1         	 # Set Zero
43207		 or    $20,$0,$16      	 # Copy Carry to X
43208		 lw    $25,0x88($21)
43209		 sw    $15,m68k_ICount
43210		 sw    $9,0x44($29)
43211		 sw    $14,0x40($29)
43212		 sw    $24,0x3C($29)
43213		 or    $5,$0,$2
43214		 or    $4,$0,$14
43215		 jalr  $25
43216		 sw    $23,0x4C($21)    	 # Delay slot
43217		 lw    $24,0x3C($29)
43218		 lw    $14,0x40($29)
43219		 lw    $9,0x44($29)
43220		 lw    $15,m68k_ICount
43221		 addiu $15,$15,-18
43222		 bgez  $15,3f
43223		 lhu   $24,0x00($23)    	 # Delay slot
43224		 j     MainExit
43225	3:
43226		 sll   $7,$24,2         	 # Delay slot
43227		 addu  $7,$7,$30
43228		 lw    $7,0x00($7)
43229		 jr    $7
43230		 nop                    	 # Delay slot
43231
43232OP0_9138:				#:
43233		 addiu $23,$23,2
43234
43235		 srl   $24,$24,7
43236		 andi  $24,$24,0x1C
43237		 addu  $24,$24,$21
43238		 lb    $9,0x00($24)
43239		 lh    $14,0x00($23)
43240		 addiu $23,$23,2
43241		 lw    $25,0x7C($21)
43242		 sw    $15,m68k_ICount
43243		 sw    $9,0x44($29)
43244		 sw    $14,0x40($29)
43245		 sw    $24,0x3C($29)
43246		 or    $4,$0,$14
43247		 jalr  $25
43248		 sw    $23,0x4C($21)    	 # Delay slot
43249		 lw    $24,0x3C($29)
43250		 lw    $14,0x40($29)
43251		 lw    $9,0x44($29)
43252		 lw    $15,m68k_ICount
43253		 seb   $10,$2
43254		 subu  $2,$10,$9
43255		 sltu  $16,$10,$9       	 # Set Carry
43256		 xor   $17,$10,$9
43257		 xor   $25,$2,$10
43258		 and   $17,$17,$25
43259		 srl   $17,$17,7
43260		 andi  $17,$17,0x01     	 # Set Overflow
43261		 seb  $25,$2
43262		 slt   $19,$25,$0        	 # Set Sign
43263		 sltiu $18,$25,1         	 # Set Zero
43264		 or    $20,$0,$16      	 # Copy Carry to X
43265		 lw    $25,0x88($21)
43266		 sw    $15,m68k_ICount
43267		 sw    $9,0x44($29)
43268		 sw    $14,0x40($29)
43269		 sw    $24,0x3C($29)
43270		 or    $5,$0,$2
43271		 or    $4,$0,$14
43272		 jalr  $25
43273		 sw    $23,0x4C($21)    	 # Delay slot
43274		 lw    $24,0x3C($29)
43275		 lw    $14,0x40($29)
43276		 lw    $9,0x44($29)
43277		 lw    $15,m68k_ICount
43278		 addiu $15,$15,-16
43279		 bgez  $15,3f
43280		 lhu   $24,0x00($23)    	 # Delay slot
43281		 j     MainExit
43282	3:
43283		 sll   $7,$24,2         	 # Delay slot
43284		 addu  $7,$7,$30
43285		 lw    $7,0x00($7)
43286		 jr    $7
43287		 nop                    	 # Delay slot
43288
43289OP0_9139:				#:
43290		 addiu $23,$23,2
43291
43292		 srl   $24,$24,7
43293		 andi  $24,$24,0x1C
43294		 addu  $24,$24,$21
43295		 lb    $9,0x00($24)
43296		 lhu   $14,0x00($23)
43297		 lhu   $25,0x02($23)
43298		 sll   $14,$14,16
43299		 or    $14,$14,$25
43300		 addiu $23,$23,4
43301		 lw    $25,0x7C($21)
43302		 sw    $15,m68k_ICount
43303		 sw    $9,0x44($29)
43304		 sw    $14,0x40($29)
43305		 sw    $24,0x3C($29)
43306		 or    $4,$0,$14
43307		 jalr  $25
43308		 sw    $23,0x4C($21)    	 # Delay slot
43309		 lw    $24,0x3C($29)
43310		 lw    $14,0x40($29)
43311		 lw    $9,0x44($29)
43312		 lw    $15,m68k_ICount
43313		 seb   $10,$2
43314		 subu  $2,$10,$9
43315		 sltu  $16,$10,$9       	 # Set Carry
43316		 xor   $17,$10,$9
43317		 xor   $25,$2,$10
43318		 and   $17,$17,$25
43319		 srl   $17,$17,7
43320		 andi  $17,$17,0x01     	 # Set Overflow
43321		 seb  $25,$2
43322		 slt   $19,$25,$0        	 # Set Sign
43323		 sltiu $18,$25,1         	 # Set Zero
43324		 or    $20,$0,$16      	 # Copy Carry to X
43325		 lw    $25,0x88($21)
43326		 sw    $15,m68k_ICount
43327		 sw    $9,0x44($29)
43328		 sw    $14,0x40($29)
43329		 sw    $24,0x3C($29)
43330		 or    $5,$0,$2
43331		 or    $4,$0,$14
43332		 jalr  $25
43333		 sw    $23,0x4C($21)    	 # Delay slot
43334		 lw    $24,0x3C($29)
43335		 lw    $14,0x40($29)
43336		 lw    $9,0x44($29)
43337		 lw    $15,m68k_ICount
43338		 addiu $15,$15,-20
43339		 bgez  $15,3f
43340		 lhu   $24,0x00($23)    	 # Delay slot
43341		 j     MainExit
43342	3:
43343		 sll   $7,$24,2         	 # Delay slot
43344		 addu  $7,$7,$30
43345		 lw    $7,0x00($7)
43346		 jr    $7
43347		 nop                    	 # Delay slot
43348
43349OP0_9150:				#:
43350		 addiu $23,$23,2
43351
43352		 andi  $8,$24,0x07
43353		 srl   $24,$24,7
43354		 andi  $24,$24,0x1C
43355		 addu  $24,$24,$21
43356		 lh    $9,0x00($24)
43357		 sll   $8,$8,2
43358		 addu  $8,$8,$21
43359		 lw    $14,0x20($8)
43360		 lw    $25,0x80($21)
43361		 sw    $15,m68k_ICount
43362		 sw    $9,0x44($29)
43363		 sw    $14,0x40($29)
43364		 sw    $24,0x3C($29)
43365		 or    $4,$0,$14
43366		 jalr  $25
43367		 sw    $23,0x4C($21)    	 # Delay slot
43368		 lw    $24,0x3C($29)
43369		 lw    $14,0x40($29)
43370		 lw    $9,0x44($29)
43371		 lw    $15,m68k_ICount
43372		 seh   $10,$2
43373		 subu  $2,$10,$9
43374		 sltu  $16,$10,$9       	 # Set Carry
43375		 xor   $17,$10,$9
43376		 xor   $25,$2,$10
43377		 and   $17,$17,$25
43378		 srl   $17,$17,15
43379		 andi  $17,$17,0x01     	 # Set Overflow
43380		 seh  $25,$2
43381		 slt   $19,$25,$0        	 # Set Sign
43382		 sltiu $18,$25,1         	 # Set Zero
43383		 or    $20,$0,$16      	 # Copy Carry to X
43384		 lw    $25,0x8C($21)
43385		 sw    $15,m68k_ICount
43386		 sw    $9,0x44($29)
43387		 sw    $14,0x40($29)
43388		 sw    $24,0x3C($29)
43389		 or    $5,$0,$2
43390		 or    $4,$0,$14
43391		 jalr  $25
43392		 sw    $23,0x4C($21)    	 # Delay slot
43393		 lw    $24,0x3C($29)
43394		 lw    $14,0x40($29)
43395		 lw    $9,0x44($29)
43396		 lw    $15,m68k_ICount
43397		 addiu $15,$15,-12
43398		 bgez  $15,3f
43399		 lhu   $24,0x00($23)    	 # Delay slot
43400		 j     MainExit
43401	3:
43402		 sll   $7,$24,2         	 # Delay slot
43403		 addu  $7,$7,$30
43404		 lw    $7,0x00($7)
43405		 jr    $7
43406		 nop                    	 # Delay slot
43407
43408OP0_9158:				#:
43409		 addiu $23,$23,2
43410
43411		 andi  $8,$24,0x07
43412		 srl   $24,$24,7
43413		 andi  $24,$24,0x1C
43414		 addu  $24,$24,$21
43415		 lh    $9,0x00($24)
43416		 sll   $8,$8,2
43417		 addu  $8,$8,$21
43418		 lw    $14,0x20($8)
43419		 addiu $25,$14,2
43420		 sw    $25,0x20($8)
43421		 lw    $25,0x80($21)
43422		 sw    $15,m68k_ICount
43423		 sw    $9,0x44($29)
43424		 sw    $14,0x40($29)
43425		 sw    $24,0x3C($29)
43426		 or    $4,$0,$14
43427		 jalr  $25
43428		 sw    $23,0x4C($21)    	 # Delay slot
43429		 lw    $24,0x3C($29)
43430		 lw    $14,0x40($29)
43431		 lw    $9,0x44($29)
43432		 lw    $15,m68k_ICount
43433		 seh   $10,$2
43434		 subu  $2,$10,$9
43435		 sltu  $16,$10,$9       	 # Set Carry
43436		 xor   $17,$10,$9
43437		 xor   $25,$2,$10
43438		 and   $17,$17,$25
43439		 srl   $17,$17,15
43440		 andi  $17,$17,0x01     	 # Set Overflow
43441		 seh  $25,$2
43442		 slt   $19,$25,$0        	 # Set Sign
43443		 sltiu $18,$25,1         	 # Set Zero
43444		 or    $20,$0,$16      	 # Copy Carry to X
43445		 lw    $25,0x8C($21)
43446		 sw    $15,m68k_ICount
43447		 sw    $9,0x44($29)
43448		 sw    $14,0x40($29)
43449		 sw    $24,0x3C($29)
43450		 or    $5,$0,$2
43451		 or    $4,$0,$14
43452		 jalr  $25
43453		 sw    $23,0x4C($21)    	 # Delay slot
43454		 lw    $24,0x3C($29)
43455		 lw    $14,0x40($29)
43456		 lw    $9,0x44($29)
43457		 lw    $15,m68k_ICount
43458		 addiu $15,$15,-12
43459		 bgez  $15,3f
43460		 lhu   $24,0x00($23)    	 # Delay slot
43461		 j     MainExit
43462	3:
43463		 sll   $7,$24,2         	 # Delay slot
43464		 addu  $7,$7,$30
43465		 lw    $7,0x00($7)
43466		 jr    $7
43467		 nop                    	 # Delay slot
43468
43469OP0_9160:				#:
43470		 addiu $23,$23,2
43471
43472		 andi  $8,$24,0x07
43473		 srl   $24,$24,7
43474		 andi  $24,$24,0x1C
43475		 addu  $24,$24,$21
43476		 lh    $9,0x00($24)
43477		 sll   $8,$8,2
43478		 addu  $8,$8,$21
43479		 lw    $14,0x20($8)
43480		 addiu $14,$14,-2
43481		 sw    $14,0x20($8)
43482		 lw    $25,0x80($21)
43483		 sw    $15,m68k_ICount
43484		 sw    $9,0x44($29)
43485		 sw    $14,0x40($29)
43486		 sw    $24,0x3C($29)
43487		 or    $4,$0,$14
43488		 jalr  $25
43489		 sw    $23,0x4C($21)    	 # Delay slot
43490		 lw    $24,0x3C($29)
43491		 lw    $14,0x40($29)
43492		 lw    $9,0x44($29)
43493		 lw    $15,m68k_ICount
43494		 seh   $10,$2
43495		 subu  $2,$10,$9
43496		 sltu  $16,$10,$9       	 # Set Carry
43497		 xor   $17,$10,$9
43498		 xor   $25,$2,$10
43499		 and   $17,$17,$25
43500		 srl   $17,$17,15
43501		 andi  $17,$17,0x01     	 # Set Overflow
43502		 seh  $25,$2
43503		 slt   $19,$25,$0        	 # Set Sign
43504		 sltiu $18,$25,1         	 # Set Zero
43505		 or    $20,$0,$16      	 # Copy Carry to X
43506		 lw    $25,0x8C($21)
43507		 sw    $15,m68k_ICount
43508		 sw    $9,0x44($29)
43509		 sw    $14,0x40($29)
43510		 sw    $24,0x3C($29)
43511		 or    $5,$0,$2
43512		 or    $4,$0,$14
43513		 jalr  $25
43514		 sw    $23,0x4C($21)    	 # Delay slot
43515		 lw    $24,0x3C($29)
43516		 lw    $14,0x40($29)
43517		 lw    $9,0x44($29)
43518		 lw    $15,m68k_ICount
43519		 addiu $15,$15,-14
43520		 bgez  $15,3f
43521		 lhu   $24,0x00($23)    	 # Delay slot
43522		 j     MainExit
43523	3:
43524		 sll   $7,$24,2         	 # Delay slot
43525		 addu  $7,$7,$30
43526		 lw    $7,0x00($7)
43527		 jr    $7
43528		 nop                    	 # Delay slot
43529
43530OP0_9168:				#:
43531		 addiu $23,$23,2
43532
43533		 andi  $8,$24,0x07
43534		 srl   $24,$24,7
43535		 andi  $24,$24,0x1C
43536		 addu  $24,$24,$21
43537		 lh    $9,0x00($24)
43538		 lh    $7,0x00($23)
43539		 sll   $8,$8,2
43540		 addu  $8,$8,$21
43541		 lw    $14,0x20($8)
43542		 addiu $23,$23,2
43543		 addu  $14,$14,$7
43544		 lw    $25,0x80($21)
43545		 sw    $15,m68k_ICount
43546		 sw    $9,0x44($29)
43547		 sw    $14,0x40($29)
43548		 sw    $24,0x3C($29)
43549		 or    $4,$0,$14
43550		 jalr  $25
43551		 sw    $23,0x4C($21)    	 # Delay slot
43552		 lw    $24,0x3C($29)
43553		 lw    $14,0x40($29)
43554		 lw    $9,0x44($29)
43555		 lw    $15,m68k_ICount
43556		 seh   $10,$2
43557		 subu  $2,$10,$9
43558		 sltu  $16,$10,$9       	 # Set Carry
43559		 xor   $17,$10,$9
43560		 xor   $25,$2,$10
43561		 and   $17,$17,$25
43562		 srl   $17,$17,15
43563		 andi  $17,$17,0x01     	 # Set Overflow
43564		 seh  $25,$2
43565		 slt   $19,$25,$0        	 # Set Sign
43566		 sltiu $18,$25,1         	 # Set Zero
43567		 or    $20,$0,$16      	 # Copy Carry to X
43568		 lw    $25,0x8C($21)
43569		 sw    $15,m68k_ICount
43570		 sw    $9,0x44($29)
43571		 sw    $14,0x40($29)
43572		 sw    $24,0x3C($29)
43573		 or    $5,$0,$2
43574		 or    $4,$0,$14
43575		 jalr  $25
43576		 sw    $23,0x4C($21)    	 # Delay slot
43577		 lw    $24,0x3C($29)
43578		 lw    $14,0x40($29)
43579		 lw    $9,0x44($29)
43580		 lw    $15,m68k_ICount
43581		 addiu $15,$15,-16
43582		 bgez  $15,3f
43583		 lhu   $24,0x00($23)    	 # Delay slot
43584		 j     MainExit
43585	3:
43586		 sll   $7,$24,2         	 # Delay slot
43587		 addu  $7,$7,$30
43588		 lw    $7,0x00($7)
43589		 jr    $7
43590		 nop                    	 # Delay slot
43591
43592OP0_9170:				#:
43593		 addiu $23,$23,2
43594
43595		 andi  $8,$24,0x07
43596		 srl   $24,$24,7
43597		 andi  $24,$24,0x1C
43598		 addu  $24,$24,$21
43599		 lh    $9,0x00($24)
43600		 sll   $8,$8,2
43601		 addu  $8,$8,$21
43602		 lw    $14,0x20($8)
43603		 lhu   $7,0x00($23)
43604		 addiu $23,$23,2
43605		 seb   $6,$7
43606		 or    $25,$0,$7
43607		 srl   $7,$7,12
43608		 andi  $25,$25,0x0800
43609		 sll   $7,$7,2
43610		 addu  $7,$7,$21
43611		 bne   $25,$0,0f
43612		 lw    $25,0x00($7)      	 # Delay slot
43613		 seh   $25,$25
43614	0:
43615		 addu  $25,$14,$25
43616		 addu  $14,$25,$6
43617		 lw    $25,0x80($21)
43618		 sw    $15,m68k_ICount
43619		 sw    $9,0x44($29)
43620		 sw    $14,0x40($29)
43621		 sw    $24,0x3C($29)
43622		 or    $4,$0,$14
43623		 jalr  $25
43624		 sw    $23,0x4C($21)    	 # Delay slot
43625		 lw    $24,0x3C($29)
43626		 lw    $14,0x40($29)
43627		 lw    $9,0x44($29)
43628		 lw    $15,m68k_ICount
43629		 seh   $10,$2
43630		 subu  $2,$10,$9
43631		 sltu  $16,$10,$9       	 # Set Carry
43632		 xor   $17,$10,$9
43633		 xor   $25,$2,$10
43634		 and   $17,$17,$25
43635		 srl   $17,$17,15
43636		 andi  $17,$17,0x01     	 # Set Overflow
43637		 seh  $25,$2
43638		 slt   $19,$25,$0        	 # Set Sign
43639		 sltiu $18,$25,1         	 # Set Zero
43640		 or    $20,$0,$16      	 # Copy Carry to X
43641		 lw    $25,0x8C($21)
43642		 sw    $15,m68k_ICount
43643		 sw    $9,0x44($29)
43644		 sw    $14,0x40($29)
43645		 sw    $24,0x3C($29)
43646		 or    $5,$0,$2
43647		 or    $4,$0,$14
43648		 jalr  $25
43649		 sw    $23,0x4C($21)    	 # Delay slot
43650		 lw    $24,0x3C($29)
43651		 lw    $14,0x40($29)
43652		 lw    $9,0x44($29)
43653		 lw    $15,m68k_ICount
43654		 addiu $15,$15,-18
43655		 bgez  $15,3f
43656		 lhu   $24,0x00($23)    	 # Delay slot
43657		 j     MainExit
43658	3:
43659		 sll   $7,$24,2         	 # Delay slot
43660		 addu  $7,$7,$30
43661		 lw    $7,0x00($7)
43662		 jr    $7
43663		 nop                    	 # Delay slot
43664
43665OP0_9178:				#:
43666		 addiu $23,$23,2
43667
43668		 srl   $24,$24,7
43669		 andi  $24,$24,0x1C
43670		 addu  $24,$24,$21
43671		 lh    $9,0x00($24)
43672		 lh    $14,0x00($23)
43673		 addiu $23,$23,2
43674		 lw    $25,0x80($21)
43675		 sw    $15,m68k_ICount
43676		 sw    $9,0x44($29)
43677		 sw    $14,0x40($29)
43678		 sw    $24,0x3C($29)
43679		 or    $4,$0,$14
43680		 jalr  $25
43681		 sw    $23,0x4C($21)    	 # Delay slot
43682		 lw    $24,0x3C($29)
43683		 lw    $14,0x40($29)
43684		 lw    $9,0x44($29)
43685		 lw    $15,m68k_ICount
43686		 seh   $10,$2
43687		 subu  $2,$10,$9
43688		 sltu  $16,$10,$9       	 # Set Carry
43689		 xor   $17,$10,$9
43690		 xor   $25,$2,$10
43691		 and   $17,$17,$25
43692		 srl   $17,$17,15
43693		 andi  $17,$17,0x01     	 # Set Overflow
43694		 seh  $25,$2
43695		 slt   $19,$25,$0        	 # Set Sign
43696		 sltiu $18,$25,1         	 # Set Zero
43697		 or    $20,$0,$16      	 # Copy Carry to X
43698		 lw    $25,0x8C($21)
43699		 sw    $15,m68k_ICount
43700		 sw    $9,0x44($29)
43701		 sw    $14,0x40($29)
43702		 sw    $24,0x3C($29)
43703		 or    $5,$0,$2
43704		 or    $4,$0,$14
43705		 jalr  $25
43706		 sw    $23,0x4C($21)    	 # Delay slot
43707		 lw    $24,0x3C($29)
43708		 lw    $14,0x40($29)
43709		 lw    $9,0x44($29)
43710		 lw    $15,m68k_ICount
43711		 addiu $15,$15,-16
43712		 bgez  $15,3f
43713		 lhu   $24,0x00($23)    	 # Delay slot
43714		 j     MainExit
43715	3:
43716		 sll   $7,$24,2         	 # Delay slot
43717		 addu  $7,$7,$30
43718		 lw    $7,0x00($7)
43719		 jr    $7
43720		 nop                    	 # Delay slot
43721
43722OP0_9179:				#:
43723		 addiu $23,$23,2
43724
43725		 srl   $24,$24,7
43726		 andi  $24,$24,0x1C
43727		 addu  $24,$24,$21
43728		 lh    $9,0x00($24)
43729		 lhu   $14,0x00($23)
43730		 lhu   $25,0x02($23)
43731		 sll   $14,$14,16
43732		 or    $14,$14,$25
43733		 addiu $23,$23,4
43734		 lw    $25,0x80($21)
43735		 sw    $15,m68k_ICount
43736		 sw    $9,0x44($29)
43737		 sw    $14,0x40($29)
43738		 sw    $24,0x3C($29)
43739		 or    $4,$0,$14
43740		 jalr  $25
43741		 sw    $23,0x4C($21)    	 # Delay slot
43742		 lw    $24,0x3C($29)
43743		 lw    $14,0x40($29)
43744		 lw    $9,0x44($29)
43745		 lw    $15,m68k_ICount
43746		 seh   $10,$2
43747		 subu  $2,$10,$9
43748		 sltu  $16,$10,$9       	 # Set Carry
43749		 xor   $17,$10,$9
43750		 xor   $25,$2,$10
43751		 and   $17,$17,$25
43752		 srl   $17,$17,15
43753		 andi  $17,$17,0x01     	 # Set Overflow
43754		 seh  $25,$2
43755		 slt   $19,$25,$0        	 # Set Sign
43756		 sltiu $18,$25,1         	 # Set Zero
43757		 or    $20,$0,$16      	 # Copy Carry to X
43758		 lw    $25,0x8C($21)
43759		 sw    $15,m68k_ICount
43760		 sw    $9,0x44($29)
43761		 sw    $14,0x40($29)
43762		 sw    $24,0x3C($29)
43763		 or    $5,$0,$2
43764		 or    $4,$0,$14
43765		 jalr  $25
43766		 sw    $23,0x4C($21)    	 # Delay slot
43767		 lw    $24,0x3C($29)
43768		 lw    $14,0x40($29)
43769		 lw    $9,0x44($29)
43770		 lw    $15,m68k_ICount
43771		 addiu $15,$15,-20
43772		 bgez  $15,3f
43773		 lhu   $24,0x00($23)    	 # Delay slot
43774		 j     MainExit
43775	3:
43776		 sll   $7,$24,2         	 # Delay slot
43777		 addu  $7,$7,$30
43778		 lw    $7,0x00($7)
43779		 jr    $7
43780		 nop                    	 # Delay slot
43781
43782OP0_9190:				#:
43783		 addiu $23,$23,2
43784
43785		 andi  $8,$24,0x07
43786		 srl   $24,$24,7
43787		 andi  $24,$24,0x1C
43788		 addu  $24,$24,$21
43789		 lw    $9,0x00($24)
43790		 sll   $8,$8,2
43791		 addu  $8,$8,$21
43792		 lw    $14,0x20($8)
43793		 lw    $25,0x84($21)
43794		 sw    $15,m68k_ICount
43795		 sw    $9,0x44($29)
43796		 sw    $14,0x40($29)
43797		 sw    $24,0x3C($29)
43798		 or    $4,$0,$14
43799		 jalr  $25
43800		 sw    $23,0x4C($21)    	 # Delay slot
43801		 lw    $24,0x3C($29)
43802		 lw    $14,0x40($29)
43803		 lw    $9,0x44($29)
43804		 lw    $15,m68k_ICount
43805		 or    $10,$0,$2
43806		 subu  $2,$10,$9
43807		 sltu  $16,$10,$9       	 # Set Carry
43808		 xor   $17,$10,$9
43809		 xor   $25,$2,$10
43810		 and   $17,$17,$25
43811		 srl   $17,$17,31        	 # Set Overflow
43812		 slt   $19,$2,$0        	 # Set Sign
43813		 sltiu $18,$2,1         	 # Set Zero
43814		 or    $20,$0,$16      	 # Copy Carry to X
43815		 lw    $25,0x90($21)
43816		 sw    $15,m68k_ICount
43817		 sw    $9,0x44($29)
43818		 sw    $14,0x40($29)
43819		 sw    $24,0x3C($29)
43820		 or    $5,$0,$2
43821		 or    $4,$0,$14
43822		 jalr  $25
43823		 sw    $23,0x4C($21)    	 # Delay slot
43824		 lw    $24,0x3C($29)
43825		 lw    $14,0x40($29)
43826		 lw    $9,0x44($29)
43827		 lw    $15,m68k_ICount
43828		 addiu $15,$15,-20
43829		 bgez  $15,3f
43830		 lhu   $24,0x00($23)    	 # Delay slot
43831		 j     MainExit
43832	3:
43833		 sll   $7,$24,2         	 # Delay slot
43834		 addu  $7,$7,$30
43835		 lw    $7,0x00($7)
43836		 jr    $7
43837		 nop                    	 # Delay slot
43838
43839OP0_9198:				#:
43840		 addiu $23,$23,2
43841
43842		 andi  $8,$24,0x07
43843		 srl   $24,$24,7
43844		 andi  $24,$24,0x1C
43845		 addu  $24,$24,$21
43846		 lw    $9,0x00($24)
43847		 sll   $8,$8,2
43848		 addu  $8,$8,$21
43849		 lw    $14,0x20($8)
43850		 addiu $25,$14,4
43851		 sw    $25,0x20($8)
43852		 lw    $25,0x84($21)
43853		 sw    $15,m68k_ICount
43854		 sw    $9,0x44($29)
43855		 sw    $14,0x40($29)
43856		 sw    $24,0x3C($29)
43857		 or    $4,$0,$14
43858		 jalr  $25
43859		 sw    $23,0x4C($21)    	 # Delay slot
43860		 lw    $24,0x3C($29)
43861		 lw    $14,0x40($29)
43862		 lw    $9,0x44($29)
43863		 lw    $15,m68k_ICount
43864		 or    $10,$0,$2
43865		 subu  $2,$10,$9
43866		 sltu  $16,$10,$9       	 # Set Carry
43867		 xor   $17,$10,$9
43868		 xor   $25,$2,$10
43869		 and   $17,$17,$25
43870		 srl   $17,$17,31        	 # Set Overflow
43871		 slt   $19,$2,$0        	 # Set Sign
43872		 sltiu $18,$2,1         	 # Set Zero
43873		 or    $20,$0,$16      	 # Copy Carry to X
43874		 lw    $25,0x90($21)
43875		 sw    $15,m68k_ICount
43876		 sw    $9,0x44($29)
43877		 sw    $14,0x40($29)
43878		 sw    $24,0x3C($29)
43879		 or    $5,$0,$2
43880		 or    $4,$0,$14
43881		 jalr  $25
43882		 sw    $23,0x4C($21)    	 # Delay slot
43883		 lw    $24,0x3C($29)
43884		 lw    $14,0x40($29)
43885		 lw    $9,0x44($29)
43886		 lw    $15,m68k_ICount
43887		 addiu $15,$15,-20
43888		 bgez  $15,3f
43889		 lhu   $24,0x00($23)    	 # Delay slot
43890		 j     MainExit
43891	3:
43892		 sll   $7,$24,2         	 # Delay slot
43893		 addu  $7,$7,$30
43894		 lw    $7,0x00($7)
43895		 jr    $7
43896		 nop                    	 # Delay slot
43897
43898OP0_91a0:				#:
43899		 addiu $23,$23,2
43900
43901		 andi  $8,$24,0x07
43902		 srl   $24,$24,7
43903		 andi  $24,$24,0x1C
43904		 addu  $24,$24,$21
43905		 lw    $9,0x00($24)
43906		 sll   $8,$8,2
43907		 addu  $8,$8,$21
43908		 lw    $14,0x20($8)
43909		 addiu $14,$14,-4
43910		 sw    $14,0x20($8)
43911		 lw    $25,0x84($21)
43912		 sw    $15,m68k_ICount
43913		 sw    $9,0x44($29)
43914		 sw    $14,0x40($29)
43915		 sw    $24,0x3C($29)
43916		 or    $4,$0,$14
43917		 jalr  $25
43918		 sw    $23,0x4C($21)    	 # Delay slot
43919		 lw    $24,0x3C($29)
43920		 lw    $14,0x40($29)
43921		 lw    $9,0x44($29)
43922		 lw    $15,m68k_ICount
43923		 or    $10,$0,$2
43924		 subu  $2,$10,$9
43925		 sltu  $16,$10,$9       	 # Set Carry
43926		 xor   $17,$10,$9
43927		 xor   $25,$2,$10
43928		 and   $17,$17,$25
43929		 srl   $17,$17,31        	 # Set Overflow
43930		 slt   $19,$2,$0        	 # Set Sign
43931		 sltiu $18,$2,1         	 # Set Zero
43932		 or    $20,$0,$16      	 # Copy Carry to X
43933		 lw    $25,0x90($21)
43934		 sw    $15,m68k_ICount
43935		 sw    $9,0x44($29)
43936		 sw    $14,0x40($29)
43937		 sw    $24,0x3C($29)
43938		 or    $5,$0,$2
43939		 or    $4,$0,$14
43940		 jalr  $25
43941		 sw    $23,0x4C($21)    	 # Delay slot
43942		 lw    $24,0x3C($29)
43943		 lw    $14,0x40($29)
43944		 lw    $9,0x44($29)
43945		 lw    $15,m68k_ICount
43946		 addiu $15,$15,-22
43947		 bgez  $15,3f
43948		 lhu   $24,0x00($23)    	 # Delay slot
43949		 j     MainExit
43950	3:
43951		 sll   $7,$24,2         	 # Delay slot
43952		 addu  $7,$7,$30
43953		 lw    $7,0x00($7)
43954		 jr    $7
43955		 nop                    	 # Delay slot
43956
43957OP0_91a8:				#:
43958		 addiu $23,$23,2
43959
43960		 andi  $8,$24,0x07
43961		 srl   $24,$24,7
43962		 andi  $24,$24,0x1C
43963		 addu  $24,$24,$21
43964		 lw    $9,0x00($24)
43965		 lh    $7,0x00($23)
43966		 sll   $8,$8,2
43967		 addu  $8,$8,$21
43968		 lw    $14,0x20($8)
43969		 addiu $23,$23,2
43970		 addu  $14,$14,$7
43971		 lw    $25,0x84($21)
43972		 sw    $15,m68k_ICount
43973		 sw    $9,0x44($29)
43974		 sw    $14,0x40($29)
43975		 sw    $24,0x3C($29)
43976		 or    $4,$0,$14
43977		 jalr  $25
43978		 sw    $23,0x4C($21)    	 # Delay slot
43979		 lw    $24,0x3C($29)
43980		 lw    $14,0x40($29)
43981		 lw    $9,0x44($29)
43982		 lw    $15,m68k_ICount
43983		 or    $10,$0,$2
43984		 subu  $2,$10,$9
43985		 sltu  $16,$10,$9       	 # Set Carry
43986		 xor   $17,$10,$9
43987		 xor   $25,$2,$10
43988		 and   $17,$17,$25
43989		 srl   $17,$17,31        	 # Set Overflow
43990		 slt   $19,$2,$0        	 # Set Sign
43991		 sltiu $18,$2,1         	 # Set Zero
43992		 or    $20,$0,$16      	 # Copy Carry to X
43993		 lw    $25,0x90($21)
43994		 sw    $15,m68k_ICount
43995		 sw    $9,0x44($29)
43996		 sw    $14,0x40($29)
43997		 sw    $24,0x3C($29)
43998		 or    $5,$0,$2
43999		 or    $4,$0,$14
44000		 jalr  $25
44001		 sw    $23,0x4C($21)    	 # Delay slot
44002		 lw    $24,0x3C($29)
44003		 lw    $14,0x40($29)
44004		 lw    $9,0x44($29)
44005		 lw    $15,m68k_ICount
44006		 addiu $15,$15,-24
44007		 bgez  $15,3f
44008		 lhu   $24,0x00($23)    	 # Delay slot
44009		 j     MainExit
44010	3:
44011		 sll   $7,$24,2         	 # Delay slot
44012		 addu  $7,$7,$30
44013		 lw    $7,0x00($7)
44014		 jr    $7
44015		 nop                    	 # Delay slot
44016
44017OP0_91b0:				#:
44018		 addiu $23,$23,2
44019
44020		 andi  $8,$24,0x07
44021		 srl   $24,$24,7
44022		 andi  $24,$24,0x1C
44023		 addu  $24,$24,$21
44024		 lw    $9,0x00($24)
44025		 sll   $8,$8,2
44026		 addu  $8,$8,$21
44027		 lw    $14,0x20($8)
44028		 lhu   $7,0x00($23)
44029		 addiu $23,$23,2
44030		 seb   $6,$7
44031		 or    $25,$0,$7
44032		 srl   $7,$7,12
44033		 andi  $25,$25,0x0800
44034		 sll   $7,$7,2
44035		 addu  $7,$7,$21
44036		 bne   $25,$0,0f
44037		 lw    $25,0x00($7)      	 # Delay slot
44038		 seh   $25,$25
44039	0:
44040		 addu  $25,$14,$25
44041		 addu  $14,$25,$6
44042		 lw    $25,0x84($21)
44043		 sw    $15,m68k_ICount
44044		 sw    $9,0x44($29)
44045		 sw    $14,0x40($29)
44046		 sw    $24,0x3C($29)
44047		 or    $4,$0,$14
44048		 jalr  $25
44049		 sw    $23,0x4C($21)    	 # Delay slot
44050		 lw    $24,0x3C($29)
44051		 lw    $14,0x40($29)
44052		 lw    $9,0x44($29)
44053		 lw    $15,m68k_ICount
44054		 or    $10,$0,$2
44055		 subu  $2,$10,$9
44056		 sltu  $16,$10,$9       	 # Set Carry
44057		 xor   $17,$10,$9
44058		 xor   $25,$2,$10
44059		 and   $17,$17,$25
44060		 srl   $17,$17,31        	 # Set Overflow
44061		 slt   $19,$2,$0        	 # Set Sign
44062		 sltiu $18,$2,1         	 # Set Zero
44063		 or    $20,$0,$16      	 # Copy Carry to X
44064		 lw    $25,0x90($21)
44065		 sw    $15,m68k_ICount
44066		 sw    $9,0x44($29)
44067		 sw    $14,0x40($29)
44068		 sw    $24,0x3C($29)
44069		 or    $5,$0,$2
44070		 or    $4,$0,$14
44071		 jalr  $25
44072		 sw    $23,0x4C($21)    	 # Delay slot
44073		 lw    $24,0x3C($29)
44074		 lw    $14,0x40($29)
44075		 lw    $9,0x44($29)
44076		 lw    $15,m68k_ICount
44077		 addiu $15,$15,-26
44078		 bgez  $15,3f
44079		 lhu   $24,0x00($23)    	 # Delay slot
44080		 j     MainExit
44081	3:
44082		 sll   $7,$24,2         	 # Delay slot
44083		 addu  $7,$7,$30
44084		 lw    $7,0x00($7)
44085		 jr    $7
44086		 nop                    	 # Delay slot
44087
44088OP0_91b8:				#:
44089		 addiu $23,$23,2
44090
44091		 srl   $24,$24,7
44092		 andi  $24,$24,0x1C
44093		 addu  $24,$24,$21
44094		 lw    $9,0x00($24)
44095		 lh    $14,0x00($23)
44096		 addiu $23,$23,2
44097		 lw    $25,0x84($21)
44098		 sw    $15,m68k_ICount
44099		 sw    $9,0x44($29)
44100		 sw    $14,0x40($29)
44101		 sw    $24,0x3C($29)
44102		 or    $4,$0,$14
44103		 jalr  $25
44104		 sw    $23,0x4C($21)    	 # Delay slot
44105		 lw    $24,0x3C($29)
44106		 lw    $14,0x40($29)
44107		 lw    $9,0x44($29)
44108		 lw    $15,m68k_ICount
44109		 or    $10,$0,$2
44110		 subu  $2,$10,$9
44111		 sltu  $16,$10,$9       	 # Set Carry
44112		 xor   $17,$10,$9
44113		 xor   $25,$2,$10
44114		 and   $17,$17,$25
44115		 srl   $17,$17,31        	 # Set Overflow
44116		 slt   $19,$2,$0        	 # Set Sign
44117		 sltiu $18,$2,1         	 # Set Zero
44118		 or    $20,$0,$16      	 # Copy Carry to X
44119		 lw    $25,0x90($21)
44120		 sw    $15,m68k_ICount
44121		 sw    $9,0x44($29)
44122		 sw    $14,0x40($29)
44123		 sw    $24,0x3C($29)
44124		 or    $5,$0,$2
44125		 or    $4,$0,$14
44126		 jalr  $25
44127		 sw    $23,0x4C($21)    	 # Delay slot
44128		 lw    $24,0x3C($29)
44129		 lw    $14,0x40($29)
44130		 lw    $9,0x44($29)
44131		 lw    $15,m68k_ICount
44132		 addiu $15,$15,-24
44133		 bgez  $15,3f
44134		 lhu   $24,0x00($23)    	 # Delay slot
44135		 j     MainExit
44136	3:
44137		 sll   $7,$24,2         	 # Delay slot
44138		 addu  $7,$7,$30
44139		 lw    $7,0x00($7)
44140		 jr    $7
44141		 nop                    	 # Delay slot
44142
44143OP0_91b9:				#:
44144		 addiu $23,$23,2
44145
44146		 srl   $24,$24,7
44147		 andi  $24,$24,0x1C
44148		 addu  $24,$24,$21
44149		 lw    $9,0x00($24)
44150		 lhu   $14,0x00($23)
44151		 lhu   $25,0x02($23)
44152		 sll   $14,$14,16
44153		 or    $14,$14,$25
44154		 addiu $23,$23,4
44155		 lw    $25,0x84($21)
44156		 sw    $15,m68k_ICount
44157		 sw    $9,0x44($29)
44158		 sw    $14,0x40($29)
44159		 sw    $24,0x3C($29)
44160		 or    $4,$0,$14
44161		 jalr  $25
44162		 sw    $23,0x4C($21)    	 # Delay slot
44163		 lw    $24,0x3C($29)
44164		 lw    $14,0x40($29)
44165		 lw    $9,0x44($29)
44166		 lw    $15,m68k_ICount
44167		 or    $10,$0,$2
44168		 subu  $2,$10,$9
44169		 sltu  $16,$10,$9       	 # Set Carry
44170		 xor   $17,$10,$9
44171		 xor   $25,$2,$10
44172		 and   $17,$17,$25
44173		 srl   $17,$17,31        	 # Set Overflow
44174		 slt   $19,$2,$0        	 # Set Sign
44175		 sltiu $18,$2,1         	 # Set Zero
44176		 or    $20,$0,$16      	 # Copy Carry to X
44177		 lw    $25,0x90($21)
44178		 sw    $15,m68k_ICount
44179		 sw    $9,0x44($29)
44180		 sw    $14,0x40($29)
44181		 sw    $24,0x3C($29)
44182		 or    $5,$0,$2
44183		 or    $4,$0,$14
44184		 jalr  $25
44185		 sw    $23,0x4C($21)    	 # Delay slot
44186		 lw    $24,0x3C($29)
44187		 lw    $14,0x40($29)
44188		 lw    $9,0x44($29)
44189		 lw    $15,m68k_ICount
44190		 addiu $15,$15,-28
44191		 bgez  $15,3f
44192		 lhu   $24,0x00($23)    	 # Delay slot
44193		 j     MainExit
44194	3:
44195		 sll   $7,$24,2         	 # Delay slot
44196		 addu  $7,$7,$30
44197		 lw    $7,0x00($7)
44198		 jr    $7
44199		 nop                    	 # Delay slot
44200
44201OP0_90c0:				#:
44202		 addiu $23,$23,2
44203
44204		 andi  $8,$24,0x0f
44205		 srl   $24,$24,7
44206		 andi  $24,$24,0x1C
44207		 addu  $24,$24,$21
44208		 lw    $9,0x20($24)
44209		 sll   $8,$8,2
44210		 addu  $8,$8,$21
44211		 lh    $2,0x00($8)
44212		 subu  $10,$9,$2
44213		 sw    $10,0x20($24)
44214		 addiu $15,$15,-4
44215		 bgez  $15,3f
44216		 lhu   $24,0x00($23)    	 # Delay slot
44217		 j     MainExit
44218	3:
44219		 sll   $7,$24,2         	 # Delay slot
44220		 addu  $7,$7,$30
44221		 lw    $7,0x00($7)
44222		 jr    $7
44223		 nop                    	 # Delay slot
44224
44225OP0_90d0:				#:
44226		 addiu $23,$23,2
44227
44228		 andi  $8,$24,0x07
44229		 srl   $24,$24,7
44230		 andi  $24,$24,0x1C
44231		 addu  $24,$24,$21
44232		 lw    $9,0x20($24)
44233		 sll   $8,$8,2
44234		 addu  $8,$8,$21
44235		 lw    $14,0x20($8)
44236		 lw    $25,0x80($21)
44237		 sw    $15,m68k_ICount
44238		 sw    $9,0x44($29)
44239		 sw    $24,0x40($29)
44240		 or    $4,$0,$14
44241		 jalr  $25
44242		 sw    $23,0x4C($21)    	 # Delay slot
44243		 lw    $24,0x40($29)
44244		 lw    $9,0x44($29)
44245		 lw    $15,m68k_ICount
44246		 seh   $2,$2
44247		 subu  $10,$9,$2
44248		 sw    $10,0x20($24)
44249		 addiu $15,$15,-8
44250		 bgez  $15,3f
44251		 lhu   $24,0x00($23)    	 # Delay slot
44252		 j     MainExit
44253	3:
44254		 sll   $7,$24,2         	 # Delay slot
44255		 addu  $7,$7,$30
44256		 lw    $7,0x00($7)
44257		 jr    $7
44258		 nop                    	 # Delay slot
44259
44260OP0_90d8:				#:
44261		 addiu $23,$23,2
44262
44263		 andi  $8,$24,0x07
44264		 srl   $24,$24,7
44265		 andi  $24,$24,0x1C
44266		 addu  $24,$24,$21
44267		 lw    $9,0x20($24)
44268		 sll   $8,$8,2
44269		 addu  $8,$8,$21
44270		 lw    $14,0x20($8)
44271		 addiu $25,$14,2
44272		 sw    $25,0x20($8)
44273		 lw    $25,0x80($21)
44274		 sw    $15,m68k_ICount
44275		 sw    $9,0x44($29)
44276		 sw    $24,0x40($29)
44277		 or    $4,$0,$14
44278		 jalr  $25
44279		 sw    $23,0x4C($21)    	 # Delay slot
44280		 lw    $24,0x40($29)
44281		 lw    $9,0x44($29)
44282		 lw    $15,m68k_ICount
44283		 seh   $2,$2
44284		 subu  $10,$9,$2
44285		 sw    $10,0x20($24)
44286		 addiu $15,$15,-8
44287		 bgez  $15,3f
44288		 lhu   $24,0x00($23)    	 # Delay slot
44289		 j     MainExit
44290	3:
44291		 sll   $7,$24,2         	 # Delay slot
44292		 addu  $7,$7,$30
44293		 lw    $7,0x00($7)
44294		 jr    $7
44295		 nop                    	 # Delay slot
44296
44297OP0_90e0:				#:
44298		 addiu $23,$23,2
44299
44300		 andi  $8,$24,0x07
44301		 srl   $24,$24,7
44302		 andi  $24,$24,0x1C
44303		 addu  $24,$24,$21
44304		 lw    $9,0x20($24)
44305		 sll   $8,$8,2
44306		 addu  $8,$8,$21
44307		 lw    $14,0x20($8)
44308		 addiu $14,$14,-2
44309		 sw    $14,0x20($8)
44310		 lw    $25,0x80($21)
44311		 sw    $15,m68k_ICount
44312		 sw    $9,0x44($29)
44313		 sw    $24,0x40($29)
44314		 or    $4,$0,$14
44315		 jalr  $25
44316		 sw    $23,0x4C($21)    	 # Delay slot
44317		 lw    $24,0x40($29)
44318		 lw    $9,0x44($29)
44319		 lw    $15,m68k_ICount
44320		 seh   $2,$2
44321		 subu  $10,$9,$2
44322		 sw    $10,0x20($24)
44323		 addiu $15,$15,-10
44324		 bgez  $15,3f
44325		 lhu   $24,0x00($23)    	 # Delay slot
44326		 j     MainExit
44327	3:
44328		 sll   $7,$24,2         	 # Delay slot
44329		 addu  $7,$7,$30
44330		 lw    $7,0x00($7)
44331		 jr    $7
44332		 nop                    	 # Delay slot
44333
44334OP0_90e8:				#:
44335		 addiu $23,$23,2
44336
44337		 andi  $8,$24,0x07
44338		 srl   $24,$24,7
44339		 andi  $24,$24,0x1C
44340		 addu  $24,$24,$21
44341		 lw    $9,0x20($24)
44342		 lh    $7,0x00($23)
44343		 sll   $8,$8,2
44344		 addu  $8,$8,$21
44345		 lw    $14,0x20($8)
44346		 addiu $23,$23,2
44347		 addu  $14,$14,$7
44348		 lw    $25,0x80($21)
44349		 sw    $15,m68k_ICount
44350		 sw    $9,0x44($29)
44351		 sw    $24,0x40($29)
44352		 or    $4,$0,$14
44353		 jalr  $25
44354		 sw    $23,0x4C($21)    	 # Delay slot
44355		 lw    $24,0x40($29)
44356		 lw    $9,0x44($29)
44357		 lw    $15,m68k_ICount
44358		 seh   $2,$2
44359		 subu  $10,$9,$2
44360		 sw    $10,0x20($24)
44361		 addiu $15,$15,-12
44362		 bgez  $15,3f
44363		 lhu   $24,0x00($23)    	 # Delay slot
44364		 j     MainExit
44365	3:
44366		 sll   $7,$24,2         	 # Delay slot
44367		 addu  $7,$7,$30
44368		 lw    $7,0x00($7)
44369		 jr    $7
44370		 nop                    	 # Delay slot
44371
44372OP0_90f0:				#:
44373		 addiu $23,$23,2
44374
44375		 andi  $8,$24,0x07
44376		 srl   $24,$24,7
44377		 andi  $24,$24,0x1C
44378		 addu  $24,$24,$21
44379		 lw    $9,0x20($24)
44380		 sll   $8,$8,2
44381		 addu  $8,$8,$21
44382		 lw    $14,0x20($8)
44383		 lhu   $7,0x00($23)
44384		 addiu $23,$23,2
44385		 seb   $6,$7
44386		 or    $25,$0,$7
44387		 srl   $7,$7,12
44388		 andi  $25,$25,0x0800
44389		 sll   $7,$7,2
44390		 addu  $7,$7,$21
44391		 bne   $25,$0,0f
44392		 lw    $25,0x00($7)      	 # Delay slot
44393		 seh   $25,$25
44394	0:
44395		 addu  $25,$14,$25
44396		 addu  $14,$25,$6
44397		 lw    $25,0x80($21)
44398		 sw    $15,m68k_ICount
44399		 sw    $9,0x44($29)
44400		 sw    $24,0x40($29)
44401		 or    $4,$0,$14
44402		 jalr  $25
44403		 sw    $23,0x4C($21)    	 # Delay slot
44404		 lw    $24,0x40($29)
44405		 lw    $9,0x44($29)
44406		 lw    $15,m68k_ICount
44407		 seh   $2,$2
44408		 subu  $10,$9,$2
44409		 sw    $10,0x20($24)
44410		 addiu $15,$15,-14
44411		 bgez  $15,3f
44412		 lhu   $24,0x00($23)    	 # Delay slot
44413		 j     MainExit
44414	3:
44415		 sll   $7,$24,2         	 # Delay slot
44416		 addu  $7,$7,$30
44417		 lw    $7,0x00($7)
44418		 jr    $7
44419		 nop                    	 # Delay slot
44420
44421OP0_90f8:				#:
44422		 addiu $23,$23,2
44423
44424		 srl   $24,$24,7
44425		 andi  $24,$24,0x1C
44426		 addu  $24,$24,$21
44427		 lw    $9,0x20($24)
44428		 lh    $14,0x00($23)
44429		 addiu $23,$23,2
44430		 lw    $25,0x80($21)
44431		 sw    $15,m68k_ICount
44432		 sw    $9,0x44($29)
44433		 sw    $24,0x40($29)
44434		 or    $4,$0,$14
44435		 jalr  $25
44436		 sw    $23,0x4C($21)    	 # Delay slot
44437		 lw    $24,0x40($29)
44438		 lw    $9,0x44($29)
44439		 lw    $15,m68k_ICount
44440		 seh   $2,$2
44441		 subu  $10,$9,$2
44442		 sw    $10,0x20($24)
44443		 addiu $15,$15,-12
44444		 bgez  $15,3f
44445		 lhu   $24,0x00($23)    	 # Delay slot
44446		 j     MainExit
44447	3:
44448		 sll   $7,$24,2         	 # Delay slot
44449		 addu  $7,$7,$30
44450		 lw    $7,0x00($7)
44451		 jr    $7
44452		 nop                    	 # Delay slot
44453
44454OP0_90f9:				#:
44455		 addiu $23,$23,2
44456
44457		 srl   $24,$24,7
44458		 andi  $24,$24,0x1C
44459		 addu  $24,$24,$21
44460		 lw    $9,0x20($24)
44461		 lhu   $14,0x00($23)
44462		 lhu   $25,0x02($23)
44463		 sll   $14,$14,16
44464		 or    $14,$14,$25
44465		 addiu $23,$23,4
44466		 lw    $25,0x80($21)
44467		 sw    $15,m68k_ICount
44468		 sw    $9,0x44($29)
44469		 sw    $24,0x40($29)
44470		 or    $4,$0,$14
44471		 jalr  $25
44472		 sw    $23,0x4C($21)    	 # Delay slot
44473		 lw    $24,0x40($29)
44474		 lw    $9,0x44($29)
44475		 lw    $15,m68k_ICount
44476		 seh   $2,$2
44477		 subu  $10,$9,$2
44478		 sw    $10,0x20($24)
44479		 addiu $15,$15,-16
44480		 bgez  $15,3f
44481		 lhu   $24,0x00($23)    	 # Delay slot
44482		 j     MainExit
44483	3:
44484		 sll   $7,$24,2         	 # Delay slot
44485		 addu  $7,$7,$30
44486		 lw    $7,0x00($7)
44487		 jr    $7
44488		 nop                    	 # Delay slot
44489
44490OP0_90fa:				#:
44491		 addiu $23,$23,2
44492
44493		 srl   $24,$24,7
44494		 andi  $24,$24,0x1C
44495		 addu  $24,$24,$21
44496		 lw    $9,0x20($24)
44497		 lh    $7,0x00($23)
44498		 subu  $25,$23,$22
44499		 addu  $14,$25,$7       	 # Add Offset to PC
44500		 addiu $23,$23,2
44501		 lw    $25,0x9C($21)
44502		 sw    $15,m68k_ICount
44503		 sw    $9,0x44($29)
44504		 sw    $24,0x40($29)
44505		 or    $4,$0,$14
44506		 jalr  $25
44507		 sw    $23,0x4C($21)    	 # Delay slot
44508		 lw    $24,0x40($29)
44509		 lw    $9,0x44($29)
44510		 lw    $15,m68k_ICount
44511		 seh   $2,$2
44512		 subu  $10,$9,$2
44513		 sw    $10,0x20($24)
44514		 addiu $15,$15,-12
44515		 bgez  $15,3f
44516		 lhu   $24,0x00($23)    	 # Delay slot
44517		 j     MainExit
44518	3:
44519		 sll   $7,$24,2         	 # Delay slot
44520		 addu  $7,$7,$30
44521		 lw    $7,0x00($7)
44522		 jr    $7
44523		 nop                    	 # Delay slot
44524
44525OP0_90fb:				#:
44526		 addiu $23,$23,2
44527
44528		 srl   $24,$24,7
44529		 andi  $24,$24,0x1C
44530		 addu  $24,$24,$21
44531		 lw    $9,0x20($24)
44532		 subu  $14,$23,$22       	 # Get PC
44533		 lhu   $7,0x00($23)
44534		 addiu $23,$23,2
44535		 seb   $6,$7
44536		 or    $25,$0,$7
44537		 srl   $7,$7,12
44538		 andi  $25,$25,0x0800
44539		 sll   $7,$7,2
44540		 addu  $7,$7,$21
44541		 bne   $25,$0,0f
44542		 lw    $25,0x00($7)      	 # Delay slot
44543		 seh   $25,$25
44544	0:
44545		 addu  $25,$14,$25
44546		 addu  $14,$25,$6
44547		 lw    $25,0x9C($21)
44548		 sw    $15,m68k_ICount
44549		 sw    $9,0x44($29)
44550		 sw    $24,0x40($29)
44551		 or    $4,$0,$14
44552		 jalr  $25
44553		 sw    $23,0x4C($21)    	 # Delay slot
44554		 lw    $24,0x40($29)
44555		 lw    $9,0x44($29)
44556		 lw    $15,m68k_ICount
44557		 seh   $2,$2
44558		 subu  $10,$9,$2
44559		 sw    $10,0x20($24)
44560		 addiu $15,$15,-14
44561		 bgez  $15,3f
44562		 lhu   $24,0x00($23)    	 # Delay slot
44563		 j     MainExit
44564	3:
44565		 sll   $7,$24,2         	 # Delay slot
44566		 addu  $7,$7,$30
44567		 lw    $7,0x00($7)
44568		 jr    $7
44569		 nop                    	 # Delay slot
44570
44571OP0_90fc:				#:
44572		 addiu $23,$23,2
44573
44574		 srl   $24,$24,7
44575		 andi  $24,$24,0x1C
44576		 addu  $24,$24,$21
44577		 lw    $9,0x20($24)
44578		 lh    $2,0x00($23)
44579		 addiu $23,$23,2
44580		 subu  $10,$9,$2
44581		 sw    $10,0x20($24)
44582		 addiu $15,$15,-4
44583		 bgez  $15,3f
44584		 lhu   $24,0x00($23)    	 # Delay slot
44585		 j     MainExit
44586	3:
44587		 sll   $7,$24,2         	 # Delay slot
44588		 addu  $7,$7,$30
44589		 lw    $7,0x00($7)
44590		 jr    $7
44591		 nop                    	 # Delay slot
44592
44593OP0_91c0:				#:
44594		 addiu $23,$23,2
44595
44596		 andi  $8,$24,0x0f
44597		 srl   $24,$24,7
44598		 andi  $24,$24,0x1C
44599		 addu  $24,$24,$21
44600		 lw    $9,0x20($24)
44601		 sll   $8,$8,2
44602		 addu  $8,$8,$21
44603		 lw    $2,0x00($8)
44604		 subu  $10,$9,$2
44605		 sw    $10,0x20($24)
44606		 addiu $15,$15,-8
44607		 bgez  $15,3f
44608		 lhu   $24,0x00($23)    	 # Delay slot
44609		 j     MainExit
44610	3:
44611		 sll   $7,$24,2         	 # Delay slot
44612		 addu  $7,$7,$30
44613		 lw    $7,0x00($7)
44614		 jr    $7
44615		 nop                    	 # Delay slot
44616
44617OP0_91d0:				#:
44618		 addiu $23,$23,2
44619
44620		 andi  $8,$24,0x07
44621		 srl   $24,$24,7
44622		 andi  $24,$24,0x1C
44623		 addu  $24,$24,$21
44624		 lw    $9,0x20($24)
44625		 sll   $8,$8,2
44626		 addu  $8,$8,$21
44627		 lw    $14,0x20($8)
44628		 lw    $25,0x84($21)
44629		 sw    $15,m68k_ICount
44630		 sw    $9,0x44($29)
44631		 sw    $24,0x40($29)
44632		 or    $4,$0,$14
44633		 jalr  $25
44634		 sw    $23,0x4C($21)    	 # Delay slot
44635		 lw    $24,0x40($29)
44636		 lw    $9,0x44($29)
44637		 lw    $15,m68k_ICount
44638		 subu  $10,$9,$2
44639		 sw    $10,0x20($24)
44640		 addiu $15,$15,-14
44641		 bgez  $15,3f
44642		 lhu   $24,0x00($23)    	 # Delay slot
44643		 j     MainExit
44644	3:
44645		 sll   $7,$24,2         	 # Delay slot
44646		 addu  $7,$7,$30
44647		 lw    $7,0x00($7)
44648		 jr    $7
44649		 nop                    	 # Delay slot
44650
44651OP0_91d8:				#:
44652		 addiu $23,$23,2
44653
44654		 andi  $8,$24,0x07
44655		 srl   $24,$24,7
44656		 andi  $24,$24,0x1C
44657		 addu  $24,$24,$21
44658		 lw    $9,0x20($24)
44659		 sll   $8,$8,2
44660		 addu  $8,$8,$21
44661		 lw    $14,0x20($8)
44662		 addiu $25,$14,4
44663		 sw    $25,0x20($8)
44664		 lw    $25,0x84($21)
44665		 sw    $15,m68k_ICount
44666		 sw    $9,0x44($29)
44667		 sw    $24,0x40($29)
44668		 or    $4,$0,$14
44669		 jalr  $25
44670		 sw    $23,0x4C($21)    	 # Delay slot
44671		 lw    $24,0x40($29)
44672		 lw    $9,0x44($29)
44673		 lw    $15,m68k_ICount
44674		 subu  $10,$9,$2
44675		 sw    $10,0x20($24)
44676		 addiu $15,$15,-14
44677		 bgez  $15,3f
44678		 lhu   $24,0x00($23)    	 # Delay slot
44679		 j     MainExit
44680	3:
44681		 sll   $7,$24,2         	 # Delay slot
44682		 addu  $7,$7,$30
44683		 lw    $7,0x00($7)
44684		 jr    $7
44685		 nop                    	 # Delay slot
44686
44687OP0_91e0:				#:
44688		 addiu $23,$23,2
44689
44690		 andi  $8,$24,0x07
44691		 srl   $24,$24,7
44692		 andi  $24,$24,0x1C
44693		 addu  $24,$24,$21
44694		 lw    $9,0x20($24)
44695		 sll   $8,$8,2
44696		 addu  $8,$8,$21
44697		 lw    $14,0x20($8)
44698		 addiu $14,$14,-4
44699		 sw    $14,0x20($8)
44700		 lw    $25,0x84($21)
44701		 sw    $15,m68k_ICount
44702		 sw    $9,0x44($29)
44703		 sw    $24,0x40($29)
44704		 or    $4,$0,$14
44705		 jalr  $25
44706		 sw    $23,0x4C($21)    	 # Delay slot
44707		 lw    $24,0x40($29)
44708		 lw    $9,0x44($29)
44709		 lw    $15,m68k_ICount
44710		 subu  $10,$9,$2
44711		 sw    $10,0x20($24)
44712		 addiu $15,$15,-16
44713		 bgez  $15,3f
44714		 lhu   $24,0x00($23)    	 # Delay slot
44715		 j     MainExit
44716	3:
44717		 sll   $7,$24,2         	 # Delay slot
44718		 addu  $7,$7,$30
44719		 lw    $7,0x00($7)
44720		 jr    $7
44721		 nop                    	 # Delay slot
44722
44723OP0_91e8:				#:
44724		 addiu $23,$23,2
44725
44726		 andi  $8,$24,0x07
44727		 srl   $24,$24,7
44728		 andi  $24,$24,0x1C
44729		 addu  $24,$24,$21
44730		 lw    $9,0x20($24)
44731		 lh    $7,0x00($23)
44732		 sll   $8,$8,2
44733		 addu  $8,$8,$21
44734		 lw    $14,0x20($8)
44735		 addiu $23,$23,2
44736		 addu  $14,$14,$7
44737		 lw    $25,0x84($21)
44738		 sw    $15,m68k_ICount
44739		 sw    $9,0x44($29)
44740		 sw    $24,0x40($29)
44741		 or    $4,$0,$14
44742		 jalr  $25
44743		 sw    $23,0x4C($21)    	 # Delay slot
44744		 lw    $24,0x40($29)
44745		 lw    $9,0x44($29)
44746		 lw    $15,m68k_ICount
44747		 subu  $10,$9,$2
44748		 sw    $10,0x20($24)
44749		 addiu $15,$15,-18
44750		 bgez  $15,3f
44751		 lhu   $24,0x00($23)    	 # Delay slot
44752		 j     MainExit
44753	3:
44754		 sll   $7,$24,2         	 # Delay slot
44755		 addu  $7,$7,$30
44756		 lw    $7,0x00($7)
44757		 jr    $7
44758		 nop                    	 # Delay slot
44759
44760OP0_91f0:				#:
44761		 addiu $23,$23,2
44762
44763		 andi  $8,$24,0x07
44764		 srl   $24,$24,7
44765		 andi  $24,$24,0x1C
44766		 addu  $24,$24,$21
44767		 lw    $9,0x20($24)
44768		 sll   $8,$8,2
44769		 addu  $8,$8,$21
44770		 lw    $14,0x20($8)
44771		 lhu   $7,0x00($23)
44772		 addiu $23,$23,2
44773		 seb   $6,$7
44774		 or    $25,$0,$7
44775		 srl   $7,$7,12
44776		 andi  $25,$25,0x0800
44777		 sll   $7,$7,2
44778		 addu  $7,$7,$21
44779		 bne   $25,$0,0f
44780		 lw    $25,0x00($7)      	 # Delay slot
44781		 seh   $25,$25
44782	0:
44783		 addu  $25,$14,$25
44784		 addu  $14,$25,$6
44785		 lw    $25,0x84($21)
44786		 sw    $15,m68k_ICount
44787		 sw    $9,0x44($29)
44788		 sw    $24,0x40($29)
44789		 or    $4,$0,$14
44790		 jalr  $25
44791		 sw    $23,0x4C($21)    	 # Delay slot
44792		 lw    $24,0x40($29)
44793		 lw    $9,0x44($29)
44794		 lw    $15,m68k_ICount
44795		 subu  $10,$9,$2
44796		 sw    $10,0x20($24)
44797		 addiu $15,$15,-20
44798		 bgez  $15,3f
44799		 lhu   $24,0x00($23)    	 # Delay slot
44800		 j     MainExit
44801	3:
44802		 sll   $7,$24,2         	 # Delay slot
44803		 addu  $7,$7,$30
44804		 lw    $7,0x00($7)
44805		 jr    $7
44806		 nop                    	 # Delay slot
44807
44808OP0_91f8:				#:
44809		 addiu $23,$23,2
44810
44811		 srl   $24,$24,7
44812		 andi  $24,$24,0x1C
44813		 addu  $24,$24,$21
44814		 lw    $9,0x20($24)
44815		 lh    $14,0x00($23)
44816		 addiu $23,$23,2
44817		 lw    $25,0x84($21)
44818		 sw    $15,m68k_ICount
44819		 sw    $9,0x44($29)
44820		 sw    $24,0x40($29)
44821		 or    $4,$0,$14
44822		 jalr  $25
44823		 sw    $23,0x4C($21)    	 # Delay slot
44824		 lw    $24,0x40($29)
44825		 lw    $9,0x44($29)
44826		 lw    $15,m68k_ICount
44827		 subu  $10,$9,$2
44828		 sw    $10,0x20($24)
44829		 addiu $15,$15,-18
44830		 bgez  $15,3f
44831		 lhu   $24,0x00($23)    	 # Delay slot
44832		 j     MainExit
44833	3:
44834		 sll   $7,$24,2         	 # Delay slot
44835		 addu  $7,$7,$30
44836		 lw    $7,0x00($7)
44837		 jr    $7
44838		 nop                    	 # Delay slot
44839
44840OP0_91f9:				#:
44841		 addiu $23,$23,2
44842
44843		 srl   $24,$24,7
44844		 andi  $24,$24,0x1C
44845		 addu  $24,$24,$21
44846		 lw    $9,0x20($24)
44847		 lhu   $14,0x00($23)
44848		 lhu   $25,0x02($23)
44849		 sll   $14,$14,16
44850		 or    $14,$14,$25
44851		 addiu $23,$23,4
44852		 lw    $25,0x84($21)
44853		 sw    $15,m68k_ICount
44854		 sw    $9,0x44($29)
44855		 sw    $24,0x40($29)
44856		 or    $4,$0,$14
44857		 jalr  $25
44858		 sw    $23,0x4C($21)    	 # Delay slot
44859		 lw    $24,0x40($29)
44860		 lw    $9,0x44($29)
44861		 lw    $15,m68k_ICount
44862		 subu  $10,$9,$2
44863		 sw    $10,0x20($24)
44864		 addiu $15,$15,-22
44865		 bgez  $15,3f
44866		 lhu   $24,0x00($23)    	 # Delay slot
44867		 j     MainExit
44868	3:
44869		 sll   $7,$24,2         	 # Delay slot
44870		 addu  $7,$7,$30
44871		 lw    $7,0x00($7)
44872		 jr    $7
44873		 nop                    	 # Delay slot
44874
44875OP0_91fa:				#:
44876		 addiu $23,$23,2
44877
44878		 srl   $24,$24,7
44879		 andi  $24,$24,0x1C
44880		 addu  $24,$24,$21
44881		 lw    $9,0x20($24)
44882		 lh    $7,0x00($23)
44883		 subu  $25,$23,$22
44884		 addu  $14,$25,$7       	 # Add Offset to PC
44885		 addiu $23,$23,2
44886		 lw    $25,0xA0($21)
44887		 sw    $15,m68k_ICount
44888		 sw    $9,0x44($29)
44889		 sw    $24,0x40($29)
44890		 or    $4,$0,$14
44891		 jalr  $25
44892		 sw    $23,0x4C($21)    	 # Delay slot
44893		 lw    $24,0x40($29)
44894		 lw    $9,0x44($29)
44895		 lw    $15,m68k_ICount
44896		 subu  $10,$9,$2
44897		 sw    $10,0x20($24)
44898		 addiu $15,$15,-18
44899		 bgez  $15,3f
44900		 lhu   $24,0x00($23)    	 # Delay slot
44901		 j     MainExit
44902	3:
44903		 sll   $7,$24,2         	 # Delay slot
44904		 addu  $7,$7,$30
44905		 lw    $7,0x00($7)
44906		 jr    $7
44907		 nop                    	 # Delay slot
44908
44909OP0_91fb:				#:
44910		 addiu $23,$23,2
44911
44912		 srl   $24,$24,7
44913		 andi  $24,$24,0x1C
44914		 addu  $24,$24,$21
44915		 lw    $9,0x20($24)
44916		 subu  $14,$23,$22       	 # Get PC
44917		 lhu   $7,0x00($23)
44918		 addiu $23,$23,2
44919		 seb   $6,$7
44920		 or    $25,$0,$7
44921		 srl   $7,$7,12
44922		 andi  $25,$25,0x0800
44923		 sll   $7,$7,2
44924		 addu  $7,$7,$21
44925		 bne   $25,$0,0f
44926		 lw    $25,0x00($7)      	 # Delay slot
44927		 seh   $25,$25
44928	0:
44929		 addu  $25,$14,$25
44930		 addu  $14,$25,$6
44931		 lw    $25,0xA0($21)
44932		 sw    $15,m68k_ICount
44933		 sw    $9,0x44($29)
44934		 sw    $24,0x40($29)
44935		 or    $4,$0,$14
44936		 jalr  $25
44937		 sw    $23,0x4C($21)    	 # Delay slot
44938		 lw    $24,0x40($29)
44939		 lw    $9,0x44($29)
44940		 lw    $15,m68k_ICount
44941		 subu  $10,$9,$2
44942		 sw    $10,0x20($24)
44943		 addiu $15,$15,-20
44944		 bgez  $15,3f
44945		 lhu   $24,0x00($23)    	 # Delay slot
44946		 j     MainExit
44947	3:
44948		 sll   $7,$24,2         	 # Delay slot
44949		 addu  $7,$7,$30
44950		 lw    $7,0x00($7)
44951		 jr    $7
44952		 nop                    	 # Delay slot
44953
44954OP0_91fc:				#:
44955		 addiu $23,$23,2
44956
44957		 srl   $24,$24,7
44958		 andi  $24,$24,0x1C
44959		 addu  $24,$24,$21
44960		 lw    $9,0x20($24)
44961		 lhu   $2,0x00($23)
44962		 lhu   $25,0x02($23)
44963		 sll   $2,$2,16
44964		 or    $2,$2,$25
44965		 addiu $23,$23,4
44966		 subu  $10,$9,$2
44967		 sw    $10,0x20($24)
44968		 addiu $15,$15,-6
44969		 bgez  $15,3f
44970		 lhu   $24,0x00($23)    	 # Delay slot
44971		 j     MainExit
44972	3:
44973		 sll   $7,$24,2         	 # Delay slot
44974		 addu  $7,$7,$30
44975		 lw    $7,0x00($7)
44976		 jr    $7
44977		 nop                    	 # Delay slot
44978
44979OP0_b000:				#:
44980		 addiu $23,$23,2
44981
44982		 andi  $8,$24,0x0f
44983		 srl   $24,$24,7
44984		 andi  $24,$24,0x1C
44985		 addu  $24,$24,$21
44986		 lb    $9,0x00($24)
44987		 sll   $8,$8,2
44988		 addu  $8,$8,$21
44989		 lb    $2,0x00($8)
44990		 subu  $10,$9,$2
44991		 sltu  $16,$9,$2       	 # Set Carry
44992		 xor   $17,$9,$2
44993		 xor   $25,$10,$9
44994		 and   $17,$17,$25
44995		 srl   $17,$17,7
44996		 andi  $17,$17,0x01     	 # Set Overflow
44997		 seb  $25,$10
44998		 slt   $19,$25,$0        	 # Set Sign
44999		 sltiu $18,$25,1         	 # Set Zero
45000		 addiu $15,$15,-4
45001		 bgez  $15,3f
45002		 lhu   $24,0x00($23)    	 # Delay slot
45003		 j     MainExit
45004	3:
45005		 sll   $7,$24,2         	 # Delay slot
45006		 addu  $7,$7,$30
45007		 lw    $7,0x00($7)
45008		 jr    $7
45009		 nop                    	 # Delay slot
45010
45011OP0_b010:				#:
45012		 addiu $23,$23,2
45013
45014		 andi  $8,$24,0x07
45015		 srl   $24,$24,7
45016		 andi  $24,$24,0x1C
45017		 addu  $24,$24,$21
45018		 lb    $9,0x00($24)
45019		 sll   $8,$8,2
45020		 addu  $8,$8,$21
45021		 lw    $14,0x20($8)
45022		 lw    $25,0x7C($21)
45023		 sw    $15,m68k_ICount
45024		 sw    $9,0x44($29)
45025		 sw    $24,0x40($29)
45026		 or    $4,$0,$14
45027		 jalr  $25
45028		 sw    $23,0x4C($21)    	 # Delay slot
45029		 lw    $24,0x40($29)
45030		 lw    $9,0x44($29)
45031		 lw    $15,m68k_ICount
45032		 seb   $2,$2
45033		 subu  $10,$9,$2
45034		 sltu  $16,$9,$2       	 # Set Carry
45035		 xor   $17,$9,$2
45036		 xor   $25,$10,$9
45037		 and   $17,$17,$25
45038		 srl   $17,$17,7
45039		 andi  $17,$17,0x01     	 # Set Overflow
45040		 seb  $25,$10
45041		 slt   $19,$25,$0        	 # Set Sign
45042		 sltiu $18,$25,1         	 # Set Zero
45043		 addiu $15,$15,-8
45044		 bgez  $15,3f
45045		 lhu   $24,0x00($23)    	 # Delay slot
45046		 j     MainExit
45047	3:
45048		 sll   $7,$24,2         	 # Delay slot
45049		 addu  $7,$7,$30
45050		 lw    $7,0x00($7)
45051		 jr    $7
45052		 nop                    	 # Delay slot
45053
45054OP0_b018:				#:
45055		 addiu $23,$23,2
45056
45057		 andi  $8,$24,0x07
45058		 srl   $24,$24,7
45059		 andi  $24,$24,0x1C
45060		 addu  $24,$24,$21
45061		 lb    $9,0x00($24)
45062		 sll   $8,$8,2
45063		 addu  $8,$8,$21
45064		 lw    $14,0x20($8)
45065		 addiu $25,$14,1
45066		 sw    $25,0x20($8)
45067		 lw    $25,0x7C($21)
45068		 sw    $15,m68k_ICount
45069		 sw    $9,0x44($29)
45070		 sw    $24,0x40($29)
45071		 or    $4,$0,$14
45072		 jalr  $25
45073		 sw    $23,0x4C($21)    	 # Delay slot
45074		 lw    $24,0x40($29)
45075		 lw    $9,0x44($29)
45076		 lw    $15,m68k_ICount
45077		 seb   $2,$2
45078		 subu  $10,$9,$2
45079		 sltu  $16,$9,$2       	 # Set Carry
45080		 xor   $17,$9,$2
45081		 xor   $25,$10,$9
45082		 and   $17,$17,$25
45083		 srl   $17,$17,7
45084		 andi  $17,$17,0x01     	 # Set Overflow
45085		 seb  $25,$10
45086		 slt   $19,$25,$0        	 # Set Sign
45087		 sltiu $18,$25,1         	 # Set Zero
45088		 addiu $15,$15,-8
45089		 bgez  $15,3f
45090		 lhu   $24,0x00($23)    	 # Delay slot
45091		 j     MainExit
45092	3:
45093		 sll   $7,$24,2         	 # Delay slot
45094		 addu  $7,$7,$30
45095		 lw    $7,0x00($7)
45096		 jr    $7
45097		 nop                    	 # Delay slot
45098
45099OP0_b01f:				#:
45100		 addiu $23,$23,2
45101
45102		 srl   $24,$24,7
45103		 andi  $24,$24,0x1C
45104		 addu  $24,$24,$21
45105		 lb    $9,0x00($24)
45106		 lw    $14,0x3C($21)    	 # Get A7
45107		 addiu $25,$14,2
45108		 sw    $25,0x3C($21)
45109		 lw    $25,0x7C($21)
45110		 sw    $15,m68k_ICount
45111		 sw    $9,0x44($29)
45112		 sw    $24,0x40($29)
45113		 or    $4,$0,$14
45114		 jalr  $25
45115		 sw    $23,0x4C($21)    	 # Delay slot
45116		 lw    $24,0x40($29)
45117		 lw    $9,0x44($29)
45118		 lw    $15,m68k_ICount
45119		 seb   $2,$2
45120		 subu  $10,$9,$2
45121		 sltu  $16,$9,$2       	 # Set Carry
45122		 xor   $17,$9,$2
45123		 xor   $25,$10,$9
45124		 and   $17,$17,$25
45125		 srl   $17,$17,7
45126		 andi  $17,$17,0x01     	 # Set Overflow
45127		 seb  $25,$10
45128		 slt   $19,$25,$0        	 # Set Sign
45129		 sltiu $18,$25,1         	 # Set Zero
45130		 addiu $15,$15,-8
45131		 bgez  $15,3f
45132		 lhu   $24,0x00($23)    	 # Delay slot
45133		 j     MainExit
45134	3:
45135		 sll   $7,$24,2         	 # Delay slot
45136		 addu  $7,$7,$30
45137		 lw    $7,0x00($7)
45138		 jr    $7
45139		 nop                    	 # Delay slot
45140
45141OP0_b020:				#:
45142		 addiu $23,$23,2
45143
45144		 andi  $8,$24,0x07
45145		 srl   $24,$24,7
45146		 andi  $24,$24,0x1C
45147		 addu  $24,$24,$21
45148		 lb    $9,0x00($24)
45149		 sll   $8,$8,2
45150		 addu  $8,$8,$21
45151		 lw    $14,0x20($8)
45152		 addiu $14,$14,-1
45153		 sw    $14,0x20($8)
45154		 lw    $25,0x7C($21)
45155		 sw    $15,m68k_ICount
45156		 sw    $9,0x44($29)
45157		 sw    $24,0x40($29)
45158		 or    $4,$0,$14
45159		 jalr  $25
45160		 sw    $23,0x4C($21)    	 # Delay slot
45161		 lw    $24,0x40($29)
45162		 lw    $9,0x44($29)
45163		 lw    $15,m68k_ICount
45164		 seb   $2,$2
45165		 subu  $10,$9,$2
45166		 sltu  $16,$9,$2       	 # Set Carry
45167		 xor   $17,$9,$2
45168		 xor   $25,$10,$9
45169		 and   $17,$17,$25
45170		 srl   $17,$17,7
45171		 andi  $17,$17,0x01     	 # Set Overflow
45172		 seb  $25,$10
45173		 slt   $19,$25,$0        	 # Set Sign
45174		 sltiu $18,$25,1         	 # Set Zero
45175		 addiu $15,$15,-10
45176		 bgez  $15,3f
45177		 lhu   $24,0x00($23)    	 # Delay slot
45178		 j     MainExit
45179	3:
45180		 sll   $7,$24,2         	 # Delay slot
45181		 addu  $7,$7,$30
45182		 lw    $7,0x00($7)
45183		 jr    $7
45184		 nop                    	 # Delay slot
45185
45186OP0_b027:				#:
45187		 addiu $23,$23,2
45188
45189		 srl   $24,$24,7
45190		 andi  $24,$24,0x1C
45191		 addu  $24,$24,$21
45192		 lb    $9,0x00($24)
45193		 lw    $14,0x3C($21)    	 # Get A7
45194		 addiu $14,$14,-2
45195		 sw    $14,0x3C($21)
45196		 lw    $25,0x7C($21)
45197		 sw    $15,m68k_ICount
45198		 sw    $9,0x44($29)
45199		 sw    $24,0x40($29)
45200		 or    $4,$0,$14
45201		 jalr  $25
45202		 sw    $23,0x4C($21)    	 # Delay slot
45203		 lw    $24,0x40($29)
45204		 lw    $9,0x44($29)
45205		 lw    $15,m68k_ICount
45206		 seb   $2,$2
45207		 subu  $10,$9,$2
45208		 sltu  $16,$9,$2       	 # Set Carry
45209		 xor   $17,$9,$2
45210		 xor   $25,$10,$9
45211		 and   $17,$17,$25
45212		 srl   $17,$17,7
45213		 andi  $17,$17,0x01     	 # Set Overflow
45214		 seb  $25,$10
45215		 slt   $19,$25,$0        	 # Set Sign
45216		 sltiu $18,$25,1         	 # Set Zero
45217		 addiu $15,$15,-10
45218		 bgez  $15,3f
45219		 lhu   $24,0x00($23)    	 # Delay slot
45220		 j     MainExit
45221	3:
45222		 sll   $7,$24,2         	 # Delay slot
45223		 addu  $7,$7,$30
45224		 lw    $7,0x00($7)
45225		 jr    $7
45226		 nop                    	 # Delay slot
45227
45228OP0_b028:				#:
45229		 addiu $23,$23,2
45230
45231		 andi  $8,$24,0x07
45232		 srl   $24,$24,7
45233		 andi  $24,$24,0x1C
45234		 addu  $24,$24,$21
45235		 lb    $9,0x00($24)
45236		 lh    $7,0x00($23)
45237		 sll   $8,$8,2
45238		 addu  $8,$8,$21
45239		 lw    $14,0x20($8)
45240		 addiu $23,$23,2
45241		 addu  $14,$14,$7
45242		 lw    $25,0x7C($21)
45243		 sw    $15,m68k_ICount
45244		 sw    $9,0x44($29)
45245		 sw    $24,0x40($29)
45246		 or    $4,$0,$14
45247		 jalr  $25
45248		 sw    $23,0x4C($21)    	 # Delay slot
45249		 lw    $24,0x40($29)
45250		 lw    $9,0x44($29)
45251		 lw    $15,m68k_ICount
45252		 seb   $2,$2
45253		 subu  $10,$9,$2
45254		 sltu  $16,$9,$2       	 # Set Carry
45255		 xor   $17,$9,$2
45256		 xor   $25,$10,$9
45257		 and   $17,$17,$25
45258		 srl   $17,$17,7
45259		 andi  $17,$17,0x01     	 # Set Overflow
45260		 seb  $25,$10
45261		 slt   $19,$25,$0        	 # Set Sign
45262		 sltiu $18,$25,1         	 # Set Zero
45263		 addiu $15,$15,-12
45264		 bgez  $15,3f
45265		 lhu   $24,0x00($23)    	 # Delay slot
45266		 j     MainExit
45267	3:
45268		 sll   $7,$24,2         	 # Delay slot
45269		 addu  $7,$7,$30
45270		 lw    $7,0x00($7)
45271		 jr    $7
45272		 nop                    	 # Delay slot
45273
45274OP0_b030:				#:
45275		 addiu $23,$23,2
45276
45277		 andi  $8,$24,0x07
45278		 srl   $24,$24,7
45279		 andi  $24,$24,0x1C
45280		 addu  $24,$24,$21
45281		 lb    $9,0x00($24)
45282		 sll   $8,$8,2
45283		 addu  $8,$8,$21
45284		 lw    $14,0x20($8)
45285		 lhu   $7,0x00($23)
45286		 addiu $23,$23,2
45287		 seb   $6,$7
45288		 or    $25,$0,$7
45289		 srl   $7,$7,12
45290		 andi  $25,$25,0x0800
45291		 sll   $7,$7,2
45292		 addu  $7,$7,$21
45293		 bne   $25,$0,0f
45294		 lw    $25,0x00($7)      	 # Delay slot
45295		 seh   $25,$25
45296	0:
45297		 addu  $25,$14,$25
45298		 addu  $14,$25,$6
45299		 lw    $25,0x7C($21)
45300		 sw    $15,m68k_ICount
45301		 sw    $9,0x44($29)
45302		 sw    $24,0x40($29)
45303		 or    $4,$0,$14
45304		 jalr  $25
45305		 sw    $23,0x4C($21)    	 # Delay slot
45306		 lw    $24,0x40($29)
45307		 lw    $9,0x44($29)
45308		 lw    $15,m68k_ICount
45309		 seb   $2,$2
45310		 subu  $10,$9,$2
45311		 sltu  $16,$9,$2       	 # Set Carry
45312		 xor   $17,$9,$2
45313		 xor   $25,$10,$9
45314		 and   $17,$17,$25
45315		 srl   $17,$17,7
45316		 andi  $17,$17,0x01     	 # Set Overflow
45317		 seb  $25,$10
45318		 slt   $19,$25,$0        	 # Set Sign
45319		 sltiu $18,$25,1         	 # Set Zero
45320		 addiu $15,$15,-14
45321		 bgez  $15,3f
45322		 lhu   $24,0x00($23)    	 # Delay slot
45323		 j     MainExit
45324	3:
45325		 sll   $7,$24,2         	 # Delay slot
45326		 addu  $7,$7,$30
45327		 lw    $7,0x00($7)
45328		 jr    $7
45329		 nop                    	 # Delay slot
45330
45331OP0_b038:				#:
45332		 addiu $23,$23,2
45333
45334		 srl   $24,$24,7
45335		 andi  $24,$24,0x1C
45336		 addu  $24,$24,$21
45337		 lb    $9,0x00($24)
45338		 lh    $14,0x00($23)
45339		 addiu $23,$23,2
45340		 lw    $25,0x7C($21)
45341		 sw    $15,m68k_ICount
45342		 sw    $9,0x44($29)
45343		 sw    $24,0x40($29)
45344		 or    $4,$0,$14
45345		 jalr  $25
45346		 sw    $23,0x4C($21)    	 # Delay slot
45347		 lw    $24,0x40($29)
45348		 lw    $9,0x44($29)
45349		 lw    $15,m68k_ICount
45350		 seb   $2,$2
45351		 subu  $10,$9,$2
45352		 sltu  $16,$9,$2       	 # Set Carry
45353		 xor   $17,$9,$2
45354		 xor   $25,$10,$9
45355		 and   $17,$17,$25
45356		 srl   $17,$17,7
45357		 andi  $17,$17,0x01     	 # Set Overflow
45358		 seb  $25,$10
45359		 slt   $19,$25,$0        	 # Set Sign
45360		 sltiu $18,$25,1         	 # Set Zero
45361		 addiu $15,$15,-12
45362		 bgez  $15,3f
45363		 lhu   $24,0x00($23)    	 # Delay slot
45364		 j     MainExit
45365	3:
45366		 sll   $7,$24,2         	 # Delay slot
45367		 addu  $7,$7,$30
45368		 lw    $7,0x00($7)
45369		 jr    $7
45370		 nop                    	 # Delay slot
45371
45372OP0_b039:				#:
45373		 addiu $23,$23,2
45374
45375		 srl   $24,$24,7
45376		 andi  $24,$24,0x1C
45377		 addu  $24,$24,$21
45378		 lb    $9,0x00($24)
45379		 lhu   $14,0x00($23)
45380		 lhu   $25,0x02($23)
45381		 sll   $14,$14,16
45382		 or    $14,$14,$25
45383		 addiu $23,$23,4
45384		 lw    $25,0x7C($21)
45385		 sw    $15,m68k_ICount
45386		 sw    $9,0x44($29)
45387		 sw    $24,0x40($29)
45388		 or    $4,$0,$14
45389		 jalr  $25
45390		 sw    $23,0x4C($21)    	 # Delay slot
45391		 lw    $24,0x40($29)
45392		 lw    $9,0x44($29)
45393		 lw    $15,m68k_ICount
45394		 seb   $2,$2
45395		 subu  $10,$9,$2
45396		 sltu  $16,$9,$2       	 # Set Carry
45397		 xor   $17,$9,$2
45398		 xor   $25,$10,$9
45399		 and   $17,$17,$25
45400		 srl   $17,$17,7
45401		 andi  $17,$17,0x01     	 # Set Overflow
45402		 seb  $25,$10
45403		 slt   $19,$25,$0        	 # Set Sign
45404		 sltiu $18,$25,1         	 # Set Zero
45405		 addiu $15,$15,-16
45406		 bgez  $15,3f
45407		 lhu   $24,0x00($23)    	 # Delay slot
45408		 j     MainExit
45409	3:
45410		 sll   $7,$24,2         	 # Delay slot
45411		 addu  $7,$7,$30
45412		 lw    $7,0x00($7)
45413		 jr    $7
45414		 nop                    	 # Delay slot
45415
45416OP0_b03a:				#:
45417		 addiu $23,$23,2
45418
45419		 srl   $24,$24,7
45420		 andi  $24,$24,0x1C
45421		 addu  $24,$24,$21
45422		 lb    $9,0x00($24)
45423		 lh    $7,0x00($23)
45424		 subu  $25,$23,$22
45425		 addu  $14,$25,$7       	 # Add Offset to PC
45426		 addiu $23,$23,2
45427		 lw    $25,0x98($21)
45428		 sw    $15,m68k_ICount
45429		 sw    $9,0x44($29)
45430		 sw    $24,0x40($29)
45431		 or    $4,$0,$14
45432		 jalr  $25
45433		 sw    $23,0x4C($21)    	 # Delay slot
45434		 lw    $24,0x40($29)
45435		 lw    $9,0x44($29)
45436		 lw    $15,m68k_ICount
45437		 seb   $2,$2
45438		 subu  $10,$9,$2
45439		 sltu  $16,$9,$2       	 # Set Carry
45440		 xor   $17,$9,$2
45441		 xor   $25,$10,$9
45442		 and   $17,$17,$25
45443		 srl   $17,$17,7
45444		 andi  $17,$17,0x01     	 # Set Overflow
45445		 seb  $25,$10
45446		 slt   $19,$25,$0        	 # Set Sign
45447		 sltiu $18,$25,1         	 # Set Zero
45448		 addiu $15,$15,-12
45449		 bgez  $15,3f
45450		 lhu   $24,0x00($23)    	 # Delay slot
45451		 j     MainExit
45452	3:
45453		 sll   $7,$24,2         	 # Delay slot
45454		 addu  $7,$7,$30
45455		 lw    $7,0x00($7)
45456		 jr    $7
45457		 nop                    	 # Delay slot
45458
45459OP0_b03b:				#:
45460		 addiu $23,$23,2
45461
45462		 srl   $24,$24,7
45463		 andi  $24,$24,0x1C
45464		 addu  $24,$24,$21
45465		 lb    $9,0x00($24)
45466		 subu  $14,$23,$22       	 # Get PC
45467		 lhu   $7,0x00($23)
45468		 addiu $23,$23,2
45469		 seb   $6,$7
45470		 or    $25,$0,$7
45471		 srl   $7,$7,12
45472		 andi  $25,$25,0x0800
45473		 sll   $7,$7,2
45474		 addu  $7,$7,$21
45475		 bne   $25,$0,0f
45476		 lw    $25,0x00($7)      	 # Delay slot
45477		 seh   $25,$25
45478	0:
45479		 addu  $25,$14,$25
45480		 addu  $14,$25,$6
45481		 lw    $25,0x98($21)
45482		 sw    $15,m68k_ICount
45483		 sw    $9,0x44($29)
45484		 sw    $24,0x40($29)
45485		 or    $4,$0,$14
45486		 jalr  $25
45487		 sw    $23,0x4C($21)    	 # Delay slot
45488		 lw    $24,0x40($29)
45489		 lw    $9,0x44($29)
45490		 lw    $15,m68k_ICount
45491		 seb   $2,$2
45492		 subu  $10,$9,$2
45493		 sltu  $16,$9,$2       	 # Set Carry
45494		 xor   $17,$9,$2
45495		 xor   $25,$10,$9
45496		 and   $17,$17,$25
45497		 srl   $17,$17,7
45498		 andi  $17,$17,0x01     	 # Set Overflow
45499		 seb  $25,$10
45500		 slt   $19,$25,$0        	 # Set Sign
45501		 sltiu $18,$25,1         	 # Set Zero
45502		 addiu $15,$15,-14
45503		 bgez  $15,3f
45504		 lhu   $24,0x00($23)    	 # Delay slot
45505		 j     MainExit
45506	3:
45507		 sll   $7,$24,2         	 # Delay slot
45508		 addu  $7,$7,$30
45509		 lw    $7,0x00($7)
45510		 jr    $7
45511		 nop                    	 # Delay slot
45512
45513OP0_b03c:				#:
45514		 addiu $23,$23,2
45515
45516		 srl   $24,$24,7
45517		 andi  $24,$24,0x1C
45518		 addu  $24,$24,$21
45519		 lb    $9,0x00($24)
45520		 lb    $2,0x00($23)
45521		 addiu $23,$23,2
45522		 subu  $10,$9,$2
45523		 sltu  $16,$9,$2       	 # Set Carry
45524		 xor   $17,$9,$2
45525		 xor   $25,$10,$9
45526		 and   $17,$17,$25
45527		 srl   $17,$17,7
45528		 andi  $17,$17,0x01     	 # Set Overflow
45529		 seb  $25,$10
45530		 slt   $19,$25,$0        	 # Set Sign
45531		 sltiu $18,$25,1         	 # Set Zero
45532		 addiu $15,$15,-4
45533		 bgez  $15,3f
45534		 lhu   $24,0x00($23)    	 # Delay slot
45535		 j     MainExit
45536	3:
45537		 sll   $7,$24,2         	 # Delay slot
45538		 addu  $7,$7,$30
45539		 lw    $7,0x00($7)
45540		 jr    $7
45541		 nop                    	 # Delay slot
45542
45543OP0_b040:				#:
45544		 addiu $23,$23,2
45545
45546		 andi  $8,$24,0x0f
45547		 srl   $24,$24,7
45548		 andi  $24,$24,0x1C
45549		 addu  $24,$24,$21
45550		 lh    $9,0x00($24)
45551		 sll   $8,$8,2
45552		 addu  $8,$8,$21
45553		 lh    $2,0x00($8)
45554		 subu  $10,$9,$2
45555		 sltu  $16,$9,$2       	 # Set Carry
45556		 xor   $17,$9,$2
45557		 xor   $25,$10,$9
45558		 and   $17,$17,$25
45559		 srl   $17,$17,15
45560		 andi  $17,$17,0x01     	 # Set Overflow
45561		 seh  $25,$10
45562		 slt   $19,$25,$0        	 # Set Sign
45563		 sltiu $18,$25,1         	 # Set Zero
45564		 addiu $15,$15,-4
45565		 bgez  $15,3f
45566		 lhu   $24,0x00($23)    	 # Delay slot
45567		 j     MainExit
45568	3:
45569		 sll   $7,$24,2         	 # Delay slot
45570		 addu  $7,$7,$30
45571		 lw    $7,0x00($7)
45572		 jr    $7
45573		 nop                    	 # Delay slot
45574
45575OP0_b050:				#:
45576		 addiu $23,$23,2
45577
45578		 andi  $8,$24,0x07
45579		 srl   $24,$24,7
45580		 andi  $24,$24,0x1C
45581		 addu  $24,$24,$21
45582		 lh    $9,0x00($24)
45583		 sll   $8,$8,2
45584		 addu  $8,$8,$21
45585		 lw    $14,0x20($8)
45586		 lw    $25,0x80($21)
45587		 sw    $15,m68k_ICount
45588		 sw    $9,0x44($29)
45589		 sw    $24,0x40($29)
45590		 or    $4,$0,$14
45591		 jalr  $25
45592		 sw    $23,0x4C($21)    	 # Delay slot
45593		 lw    $24,0x40($29)
45594		 lw    $9,0x44($29)
45595		 lw    $15,m68k_ICount
45596		 seh   $2,$2
45597		 subu  $10,$9,$2
45598		 sltu  $16,$9,$2       	 # Set Carry
45599		 xor   $17,$9,$2
45600		 xor   $25,$10,$9
45601		 and   $17,$17,$25
45602		 srl   $17,$17,15
45603		 andi  $17,$17,0x01     	 # Set Overflow
45604		 seh  $25,$10
45605		 slt   $19,$25,$0        	 # Set Sign
45606		 sltiu $18,$25,1         	 # Set Zero
45607		 addiu $15,$15,-8
45608		 bgez  $15,3f
45609		 lhu   $24,0x00($23)    	 # Delay slot
45610		 j     MainExit
45611	3:
45612		 sll   $7,$24,2         	 # Delay slot
45613		 addu  $7,$7,$30
45614		 lw    $7,0x00($7)
45615		 jr    $7
45616		 nop                    	 # Delay slot
45617
45618OP0_b058:				#:
45619		 addiu $23,$23,2
45620
45621		 andi  $8,$24,0x07
45622		 srl   $24,$24,7
45623		 andi  $24,$24,0x1C
45624		 addu  $24,$24,$21
45625		 lh    $9,0x00($24)
45626		 sll   $8,$8,2
45627		 addu  $8,$8,$21
45628		 lw    $14,0x20($8)
45629		 addiu $25,$14,2
45630		 sw    $25,0x20($8)
45631		 lw    $25,0x80($21)
45632		 sw    $15,m68k_ICount
45633		 sw    $9,0x44($29)
45634		 sw    $24,0x40($29)
45635		 or    $4,$0,$14
45636		 jalr  $25
45637		 sw    $23,0x4C($21)    	 # Delay slot
45638		 lw    $24,0x40($29)
45639		 lw    $9,0x44($29)
45640		 lw    $15,m68k_ICount
45641		 seh   $2,$2
45642		 subu  $10,$9,$2
45643		 sltu  $16,$9,$2       	 # Set Carry
45644		 xor   $17,$9,$2
45645		 xor   $25,$10,$9
45646		 and   $17,$17,$25
45647		 srl   $17,$17,15
45648		 andi  $17,$17,0x01     	 # Set Overflow
45649		 seh  $25,$10
45650		 slt   $19,$25,$0        	 # Set Sign
45651		 sltiu $18,$25,1         	 # Set Zero
45652		 addiu $15,$15,-8
45653		 bgez  $15,3f
45654		 lhu   $24,0x00($23)    	 # Delay slot
45655		 j     MainExit
45656	3:
45657		 sll   $7,$24,2         	 # Delay slot
45658		 addu  $7,$7,$30
45659		 lw    $7,0x00($7)
45660		 jr    $7
45661		 nop                    	 # Delay slot
45662
45663OP0_b060:				#:
45664		 addiu $23,$23,2
45665
45666		 andi  $8,$24,0x07
45667		 srl   $24,$24,7
45668		 andi  $24,$24,0x1C
45669		 addu  $24,$24,$21
45670		 lh    $9,0x00($24)
45671		 sll   $8,$8,2
45672		 addu  $8,$8,$21
45673		 lw    $14,0x20($8)
45674		 addiu $14,$14,-2
45675		 sw    $14,0x20($8)
45676		 lw    $25,0x80($21)
45677		 sw    $15,m68k_ICount
45678		 sw    $9,0x44($29)
45679		 sw    $24,0x40($29)
45680		 or    $4,$0,$14
45681		 jalr  $25
45682		 sw    $23,0x4C($21)    	 # Delay slot
45683		 lw    $24,0x40($29)
45684		 lw    $9,0x44($29)
45685		 lw    $15,m68k_ICount
45686		 seh   $2,$2
45687		 subu  $10,$9,$2
45688		 sltu  $16,$9,$2       	 # Set Carry
45689		 xor   $17,$9,$2
45690		 xor   $25,$10,$9
45691		 and   $17,$17,$25
45692		 srl   $17,$17,15
45693		 andi  $17,$17,0x01     	 # Set Overflow
45694		 seh  $25,$10
45695		 slt   $19,$25,$0        	 # Set Sign
45696		 sltiu $18,$25,1         	 # Set Zero
45697		 addiu $15,$15,-10
45698		 bgez  $15,3f
45699		 lhu   $24,0x00($23)    	 # Delay slot
45700		 j     MainExit
45701	3:
45702		 sll   $7,$24,2         	 # Delay slot
45703		 addu  $7,$7,$30
45704		 lw    $7,0x00($7)
45705		 jr    $7
45706		 nop                    	 # Delay slot
45707
45708OP0_b068:				#:
45709		 addiu $23,$23,2
45710
45711		 andi  $8,$24,0x07
45712		 srl   $24,$24,7
45713		 andi  $24,$24,0x1C
45714		 addu  $24,$24,$21
45715		 lh    $9,0x00($24)
45716		 lh    $7,0x00($23)
45717		 sll   $8,$8,2
45718		 addu  $8,$8,$21
45719		 lw    $14,0x20($8)
45720		 addiu $23,$23,2
45721		 addu  $14,$14,$7
45722		 lw    $25,0x80($21)
45723		 sw    $15,m68k_ICount
45724		 sw    $9,0x44($29)
45725		 sw    $24,0x40($29)
45726		 or    $4,$0,$14
45727		 jalr  $25
45728		 sw    $23,0x4C($21)    	 # Delay slot
45729		 lw    $24,0x40($29)
45730		 lw    $9,0x44($29)
45731		 lw    $15,m68k_ICount
45732		 seh   $2,$2
45733		 subu  $10,$9,$2
45734		 sltu  $16,$9,$2       	 # Set Carry
45735		 xor   $17,$9,$2
45736		 xor   $25,$10,$9
45737		 and   $17,$17,$25
45738		 srl   $17,$17,15
45739		 andi  $17,$17,0x01     	 # Set Overflow
45740		 seh  $25,$10
45741		 slt   $19,$25,$0        	 # Set Sign
45742		 sltiu $18,$25,1         	 # Set Zero
45743		 addiu $15,$15,-12
45744		 bgez  $15,3f
45745		 lhu   $24,0x00($23)    	 # Delay slot
45746		 j     MainExit
45747	3:
45748		 sll   $7,$24,2         	 # Delay slot
45749		 addu  $7,$7,$30
45750		 lw    $7,0x00($7)
45751		 jr    $7
45752		 nop                    	 # Delay slot
45753
45754OP0_b070:				#:
45755		 addiu $23,$23,2
45756
45757		 andi  $8,$24,0x07
45758		 srl   $24,$24,7
45759		 andi  $24,$24,0x1C
45760		 addu  $24,$24,$21
45761		 lh    $9,0x00($24)
45762		 sll   $8,$8,2
45763		 addu  $8,$8,$21
45764		 lw    $14,0x20($8)
45765		 lhu   $7,0x00($23)
45766		 addiu $23,$23,2
45767		 seb   $6,$7
45768		 or    $25,$0,$7
45769		 srl   $7,$7,12
45770		 andi  $25,$25,0x0800
45771		 sll   $7,$7,2
45772		 addu  $7,$7,$21
45773		 bne   $25,$0,0f
45774		 lw    $25,0x00($7)      	 # Delay slot
45775		 seh   $25,$25
45776	0:
45777		 addu  $25,$14,$25
45778		 addu  $14,$25,$6
45779		 lw    $25,0x80($21)
45780		 sw    $15,m68k_ICount
45781		 sw    $9,0x44($29)
45782		 sw    $24,0x40($29)
45783		 or    $4,$0,$14
45784		 jalr  $25
45785		 sw    $23,0x4C($21)    	 # Delay slot
45786		 lw    $24,0x40($29)
45787		 lw    $9,0x44($29)
45788		 lw    $15,m68k_ICount
45789		 seh   $2,$2
45790		 subu  $10,$9,$2
45791		 sltu  $16,$9,$2       	 # Set Carry
45792		 xor   $17,$9,$2
45793		 xor   $25,$10,$9
45794		 and   $17,$17,$25
45795		 srl   $17,$17,15
45796		 andi  $17,$17,0x01     	 # Set Overflow
45797		 seh  $25,$10
45798		 slt   $19,$25,$0        	 # Set Sign
45799		 sltiu $18,$25,1         	 # Set Zero
45800		 addiu $15,$15,-14
45801		 bgez  $15,3f
45802		 lhu   $24,0x00($23)    	 # Delay slot
45803		 j     MainExit
45804	3:
45805		 sll   $7,$24,2         	 # Delay slot
45806		 addu  $7,$7,$30
45807		 lw    $7,0x00($7)
45808		 jr    $7
45809		 nop                    	 # Delay slot
45810
45811OP0_b078:				#:
45812		 addiu $23,$23,2
45813
45814		 srl   $24,$24,7
45815		 andi  $24,$24,0x1C
45816		 addu  $24,$24,$21
45817		 lh    $9,0x00($24)
45818		 lh    $14,0x00($23)
45819		 addiu $23,$23,2
45820		 lw    $25,0x80($21)
45821		 sw    $15,m68k_ICount
45822		 sw    $9,0x44($29)
45823		 sw    $24,0x40($29)
45824		 or    $4,$0,$14
45825		 jalr  $25
45826		 sw    $23,0x4C($21)    	 # Delay slot
45827		 lw    $24,0x40($29)
45828		 lw    $9,0x44($29)
45829		 lw    $15,m68k_ICount
45830		 seh   $2,$2
45831		 subu  $10,$9,$2
45832		 sltu  $16,$9,$2       	 # Set Carry
45833		 xor   $17,$9,$2
45834		 xor   $25,$10,$9
45835		 and   $17,$17,$25
45836		 srl   $17,$17,15
45837		 andi  $17,$17,0x01     	 # Set Overflow
45838		 seh  $25,$10
45839		 slt   $19,$25,$0        	 # Set Sign
45840		 sltiu $18,$25,1         	 # Set Zero
45841		 addiu $15,$15,-12
45842		 bgez  $15,3f
45843		 lhu   $24,0x00($23)    	 # Delay slot
45844		 j     MainExit
45845	3:
45846		 sll   $7,$24,2         	 # Delay slot
45847		 addu  $7,$7,$30
45848		 lw    $7,0x00($7)
45849		 jr    $7
45850		 nop                    	 # Delay slot
45851
45852OP0_b079:				#:
45853		 addiu $23,$23,2
45854
45855		 srl   $24,$24,7
45856		 andi  $24,$24,0x1C
45857		 addu  $24,$24,$21
45858		 lh    $9,0x00($24)
45859		 lhu   $14,0x00($23)
45860		 lhu   $25,0x02($23)
45861		 sll   $14,$14,16
45862		 or    $14,$14,$25
45863		 addiu $23,$23,4
45864		 lw    $25,0x80($21)
45865		 sw    $15,m68k_ICount
45866		 sw    $9,0x44($29)
45867		 sw    $24,0x40($29)
45868		 or    $4,$0,$14
45869		 jalr  $25
45870		 sw    $23,0x4C($21)    	 # Delay slot
45871		 lw    $24,0x40($29)
45872		 lw    $9,0x44($29)
45873		 lw    $15,m68k_ICount
45874		 seh   $2,$2
45875		 subu  $10,$9,$2
45876		 sltu  $16,$9,$2       	 # Set Carry
45877		 xor   $17,$9,$2
45878		 xor   $25,$10,$9
45879		 and   $17,$17,$25
45880		 srl   $17,$17,15
45881		 andi  $17,$17,0x01     	 # Set Overflow
45882		 seh  $25,$10
45883		 slt   $19,$25,$0        	 # Set Sign
45884		 sltiu $18,$25,1         	 # Set Zero
45885		 addiu $15,$15,-16
45886		 bgez  $15,3f
45887		 lhu   $24,0x00($23)    	 # Delay slot
45888		 j     MainExit
45889	3:
45890		 sll   $7,$24,2         	 # Delay slot
45891		 addu  $7,$7,$30
45892		 lw    $7,0x00($7)
45893		 jr    $7
45894		 nop                    	 # Delay slot
45895
45896OP0_b07a:				#:
45897		 addiu $23,$23,2
45898
45899		 srl   $24,$24,7
45900		 andi  $24,$24,0x1C
45901		 addu  $24,$24,$21
45902		 lh    $9,0x00($24)
45903		 lh    $7,0x00($23)
45904		 subu  $25,$23,$22
45905		 addu  $14,$25,$7       	 # Add Offset to PC
45906		 addiu $23,$23,2
45907		 lw    $25,0x9C($21)
45908		 sw    $15,m68k_ICount
45909		 sw    $9,0x44($29)
45910		 sw    $24,0x40($29)
45911		 or    $4,$0,$14
45912		 jalr  $25
45913		 sw    $23,0x4C($21)    	 # Delay slot
45914		 lw    $24,0x40($29)
45915		 lw    $9,0x44($29)
45916		 lw    $15,m68k_ICount
45917		 seh   $2,$2
45918		 subu  $10,$9,$2
45919		 sltu  $16,$9,$2       	 # Set Carry
45920		 xor   $17,$9,$2
45921		 xor   $25,$10,$9
45922		 and   $17,$17,$25
45923		 srl   $17,$17,15
45924		 andi  $17,$17,0x01     	 # Set Overflow
45925		 seh  $25,$10
45926		 slt   $19,$25,$0        	 # Set Sign
45927		 sltiu $18,$25,1         	 # Set Zero
45928		 addiu $15,$15,-12
45929		 bgez  $15,3f
45930		 lhu   $24,0x00($23)    	 # Delay slot
45931		 j     MainExit
45932	3:
45933		 sll   $7,$24,2         	 # Delay slot
45934		 addu  $7,$7,$30
45935		 lw    $7,0x00($7)
45936		 jr    $7
45937		 nop                    	 # Delay slot
45938
45939OP0_b07b:				#:
45940		 addiu $23,$23,2
45941
45942		 srl   $24,$24,7
45943		 andi  $24,$24,0x1C
45944		 addu  $24,$24,$21
45945		 lh    $9,0x00($24)
45946		 subu  $14,$23,$22       	 # Get PC
45947		 lhu   $7,0x00($23)
45948		 addiu $23,$23,2
45949		 seb   $6,$7
45950		 or    $25,$0,$7
45951		 srl   $7,$7,12
45952		 andi  $25,$25,0x0800
45953		 sll   $7,$7,2
45954		 addu  $7,$7,$21
45955		 bne   $25,$0,0f
45956		 lw    $25,0x00($7)      	 # Delay slot
45957		 seh   $25,$25
45958	0:
45959		 addu  $25,$14,$25
45960		 addu  $14,$25,$6
45961		 lw    $25,0x9C($21)
45962		 sw    $15,m68k_ICount
45963		 sw    $9,0x44($29)
45964		 sw    $24,0x40($29)
45965		 or    $4,$0,$14
45966		 jalr  $25
45967		 sw    $23,0x4C($21)    	 # Delay slot
45968		 lw    $24,0x40($29)
45969		 lw    $9,0x44($29)
45970		 lw    $15,m68k_ICount
45971		 seh   $2,$2
45972		 subu  $10,$9,$2
45973		 sltu  $16,$9,$2       	 # Set Carry
45974		 xor   $17,$9,$2
45975		 xor   $25,$10,$9
45976		 and   $17,$17,$25
45977		 srl   $17,$17,15
45978		 andi  $17,$17,0x01     	 # Set Overflow
45979		 seh  $25,$10
45980		 slt   $19,$25,$0        	 # Set Sign
45981		 sltiu $18,$25,1         	 # Set Zero
45982		 addiu $15,$15,-14
45983		 bgez  $15,3f
45984		 lhu   $24,0x00($23)    	 # Delay slot
45985		 j     MainExit
45986	3:
45987		 sll   $7,$24,2         	 # Delay slot
45988		 addu  $7,$7,$30
45989		 lw    $7,0x00($7)
45990		 jr    $7
45991		 nop                    	 # Delay slot
45992
45993OP0_b07c:				#:
45994		 addiu $23,$23,2
45995
45996		 srl   $24,$24,7
45997		 andi  $24,$24,0x1C
45998		 addu  $24,$24,$21
45999		 lh    $9,0x00($24)
46000		 lh    $2,0x00($23)
46001		 addiu $23,$23,2
46002		 subu  $10,$9,$2
46003		 sltu  $16,$9,$2       	 # Set Carry
46004		 xor   $17,$9,$2
46005		 xor   $25,$10,$9
46006		 and   $17,$17,$25
46007		 srl   $17,$17,15
46008		 andi  $17,$17,0x01     	 # Set Overflow
46009		 seh  $25,$10
46010		 slt   $19,$25,$0        	 # Set Sign
46011		 sltiu $18,$25,1         	 # Set Zero
46012		 addiu $15,$15,-4
46013		 bgez  $15,3f
46014		 lhu   $24,0x00($23)    	 # Delay slot
46015		 j     MainExit
46016	3:
46017		 sll   $7,$24,2         	 # Delay slot
46018		 addu  $7,$7,$30
46019		 lw    $7,0x00($7)
46020		 jr    $7
46021		 nop                    	 # Delay slot
46022
46023OP0_b080:				#:
46024		 addiu $23,$23,2
46025
46026		 andi  $8,$24,0x0f
46027		 srl   $24,$24,7
46028		 andi  $24,$24,0x1C
46029		 addu  $24,$24,$21
46030		 lw    $9,0x00($24)
46031		 sll   $8,$8,2
46032		 addu  $8,$8,$21
46033		 lw    $2,0x00($8)
46034		 subu  $10,$9,$2
46035		 sltu  $16,$9,$2       	 # Set Carry
46036		 xor   $17,$9,$2
46037		 xor   $25,$10,$9
46038		 and   $17,$17,$25
46039		 srl   $17,$17,31        	 # Set Overflow
46040		 slt   $19,$10,$0        	 # Set Sign
46041		 sltiu $18,$10,1         	 # Set Zero
46042		 addiu $15,$15,-8
46043		 bgez  $15,3f
46044		 lhu   $24,0x00($23)    	 # Delay slot
46045		 j     MainExit
46046	3:
46047		 sll   $7,$24,2         	 # Delay slot
46048		 addu  $7,$7,$30
46049		 lw    $7,0x00($7)
46050		 jr    $7
46051		 nop                    	 # Delay slot
46052
46053OP0_b090:				#:
46054		 addiu $23,$23,2
46055
46056		 andi  $8,$24,0x07
46057		 srl   $24,$24,7
46058		 andi  $24,$24,0x1C
46059		 addu  $24,$24,$21
46060		 lw    $9,0x00($24)
46061		 sll   $8,$8,2
46062		 addu  $8,$8,$21
46063		 lw    $14,0x20($8)
46064		 lw    $25,0x84($21)
46065		 sw    $15,m68k_ICount
46066		 sw    $9,0x44($29)
46067		 sw    $24,0x40($29)
46068		 or    $4,$0,$14
46069		 jalr  $25
46070		 sw    $23,0x4C($21)    	 # Delay slot
46071		 lw    $24,0x40($29)
46072		 lw    $9,0x44($29)
46073		 lw    $15,m68k_ICount
46074		 subu  $10,$9,$2
46075		 sltu  $16,$9,$2       	 # Set Carry
46076		 xor   $17,$9,$2
46077		 xor   $25,$10,$9
46078		 and   $17,$17,$25
46079		 srl   $17,$17,31        	 # Set Overflow
46080		 slt   $19,$10,$0        	 # Set Sign
46081		 sltiu $18,$10,1         	 # Set Zero
46082		 addiu $15,$15,-14
46083		 bgez  $15,3f
46084		 lhu   $24,0x00($23)    	 # Delay slot
46085		 j     MainExit
46086	3:
46087		 sll   $7,$24,2         	 # Delay slot
46088		 addu  $7,$7,$30
46089		 lw    $7,0x00($7)
46090		 jr    $7
46091		 nop                    	 # Delay slot
46092
46093OP0_b098:				#:
46094		 addiu $23,$23,2
46095
46096		 andi  $8,$24,0x07
46097		 srl   $24,$24,7
46098		 andi  $24,$24,0x1C
46099		 addu  $24,$24,$21
46100		 lw    $9,0x00($24)
46101		 sll   $8,$8,2
46102		 addu  $8,$8,$21
46103		 lw    $14,0x20($8)
46104		 addiu $25,$14,4
46105		 sw    $25,0x20($8)
46106		 lw    $25,0x84($21)
46107		 sw    $15,m68k_ICount
46108		 sw    $9,0x44($29)
46109		 sw    $24,0x40($29)
46110		 or    $4,$0,$14
46111		 jalr  $25
46112		 sw    $23,0x4C($21)    	 # Delay slot
46113		 lw    $24,0x40($29)
46114		 lw    $9,0x44($29)
46115		 lw    $15,m68k_ICount
46116		 subu  $10,$9,$2
46117		 sltu  $16,$9,$2       	 # Set Carry
46118		 xor   $17,$9,$2
46119		 xor   $25,$10,$9
46120		 and   $17,$17,$25
46121		 srl   $17,$17,31        	 # Set Overflow
46122		 slt   $19,$10,$0        	 # Set Sign
46123		 sltiu $18,$10,1         	 # Set Zero
46124		 addiu $15,$15,-14
46125		 bgez  $15,3f
46126		 lhu   $24,0x00($23)    	 # Delay slot
46127		 j     MainExit
46128	3:
46129		 sll   $7,$24,2         	 # Delay slot
46130		 addu  $7,$7,$30
46131		 lw    $7,0x00($7)
46132		 jr    $7
46133		 nop                    	 # Delay slot
46134
46135OP0_b0a0:				#:
46136		 addiu $23,$23,2
46137
46138		 andi  $8,$24,0x07
46139		 srl   $24,$24,7
46140		 andi  $24,$24,0x1C
46141		 addu  $24,$24,$21
46142		 lw    $9,0x00($24)
46143		 sll   $8,$8,2
46144		 addu  $8,$8,$21
46145		 lw    $14,0x20($8)
46146		 addiu $14,$14,-4
46147		 sw    $14,0x20($8)
46148		 lw    $25,0x84($21)
46149		 sw    $15,m68k_ICount
46150		 sw    $9,0x44($29)
46151		 sw    $24,0x40($29)
46152		 or    $4,$0,$14
46153		 jalr  $25
46154		 sw    $23,0x4C($21)    	 # Delay slot
46155		 lw    $24,0x40($29)
46156		 lw    $9,0x44($29)
46157		 lw    $15,m68k_ICount
46158		 subu  $10,$9,$2
46159		 sltu  $16,$9,$2       	 # Set Carry
46160		 xor   $17,$9,$2
46161		 xor   $25,$10,$9
46162		 and   $17,$17,$25
46163		 srl   $17,$17,31        	 # Set Overflow
46164		 slt   $19,$10,$0        	 # Set Sign
46165		 sltiu $18,$10,1         	 # Set Zero
46166		 addiu $15,$15,-16
46167		 bgez  $15,3f
46168		 lhu   $24,0x00($23)    	 # Delay slot
46169		 j     MainExit
46170	3:
46171		 sll   $7,$24,2         	 # Delay slot
46172		 addu  $7,$7,$30
46173		 lw    $7,0x00($7)
46174		 jr    $7
46175		 nop                    	 # Delay slot
46176
46177OP0_b0a8:				#:
46178		 addiu $23,$23,2
46179
46180		 andi  $8,$24,0x07
46181		 srl   $24,$24,7
46182		 andi  $24,$24,0x1C
46183		 addu  $24,$24,$21
46184		 lw    $9,0x00($24)
46185		 lh    $7,0x00($23)
46186		 sll   $8,$8,2
46187		 addu  $8,$8,$21
46188		 lw    $14,0x20($8)
46189		 addiu $23,$23,2
46190		 addu  $14,$14,$7
46191		 lw    $25,0x84($21)
46192		 sw    $15,m68k_ICount
46193		 sw    $9,0x44($29)
46194		 sw    $24,0x40($29)
46195		 or    $4,$0,$14
46196		 jalr  $25
46197		 sw    $23,0x4C($21)    	 # Delay slot
46198		 lw    $24,0x40($29)
46199		 lw    $9,0x44($29)
46200		 lw    $15,m68k_ICount
46201		 subu  $10,$9,$2
46202		 sltu  $16,$9,$2       	 # Set Carry
46203		 xor   $17,$9,$2
46204		 xor   $25,$10,$9
46205		 and   $17,$17,$25
46206		 srl   $17,$17,31        	 # Set Overflow
46207		 slt   $19,$10,$0        	 # Set Sign
46208		 sltiu $18,$10,1         	 # Set Zero
46209		 addiu $15,$15,-18
46210		 bgez  $15,3f
46211		 lhu   $24,0x00($23)    	 # Delay slot
46212		 j     MainExit
46213	3:
46214		 sll   $7,$24,2         	 # Delay slot
46215		 addu  $7,$7,$30
46216		 lw    $7,0x00($7)
46217		 jr    $7
46218		 nop                    	 # Delay slot
46219
46220OP0_b0b0:				#:
46221		 addiu $23,$23,2
46222
46223		 andi  $8,$24,0x07
46224		 srl   $24,$24,7
46225		 andi  $24,$24,0x1C
46226		 addu  $24,$24,$21
46227		 lw    $9,0x00($24)
46228		 sll   $8,$8,2
46229		 addu  $8,$8,$21
46230		 lw    $14,0x20($8)
46231		 lhu   $7,0x00($23)
46232		 addiu $23,$23,2
46233		 seb   $6,$7
46234		 or    $25,$0,$7
46235		 srl   $7,$7,12
46236		 andi  $25,$25,0x0800
46237		 sll   $7,$7,2
46238		 addu  $7,$7,$21
46239		 bne   $25,$0,0f
46240		 lw    $25,0x00($7)      	 # Delay slot
46241		 seh   $25,$25
46242	0:
46243		 addu  $25,$14,$25
46244		 addu  $14,$25,$6
46245		 lw    $25,0x84($21)
46246		 sw    $15,m68k_ICount
46247		 sw    $9,0x44($29)
46248		 sw    $24,0x40($29)
46249		 or    $4,$0,$14
46250		 jalr  $25
46251		 sw    $23,0x4C($21)    	 # Delay slot
46252		 lw    $24,0x40($29)
46253		 lw    $9,0x44($29)
46254		 lw    $15,m68k_ICount
46255		 subu  $10,$9,$2
46256		 sltu  $16,$9,$2       	 # Set Carry
46257		 xor   $17,$9,$2
46258		 xor   $25,$10,$9
46259		 and   $17,$17,$25
46260		 srl   $17,$17,31        	 # Set Overflow
46261		 slt   $19,$10,$0        	 # Set Sign
46262		 sltiu $18,$10,1         	 # Set Zero
46263		 addiu $15,$15,-20
46264		 bgez  $15,3f
46265		 lhu   $24,0x00($23)    	 # Delay slot
46266		 j     MainExit
46267	3:
46268		 sll   $7,$24,2         	 # Delay slot
46269		 addu  $7,$7,$30
46270		 lw    $7,0x00($7)
46271		 jr    $7
46272		 nop                    	 # Delay slot
46273
46274OP0_b0b8:				#:
46275		 addiu $23,$23,2
46276
46277		 srl   $24,$24,7
46278		 andi  $24,$24,0x1C
46279		 addu  $24,$24,$21
46280		 lw    $9,0x00($24)
46281		 lh    $14,0x00($23)
46282		 addiu $23,$23,2
46283		 lw    $25,0x84($21)
46284		 sw    $15,m68k_ICount
46285		 sw    $9,0x44($29)
46286		 sw    $24,0x40($29)
46287		 or    $4,$0,$14
46288		 jalr  $25
46289		 sw    $23,0x4C($21)    	 # Delay slot
46290		 lw    $24,0x40($29)
46291		 lw    $9,0x44($29)
46292		 lw    $15,m68k_ICount
46293		 subu  $10,$9,$2
46294		 sltu  $16,$9,$2       	 # Set Carry
46295		 xor   $17,$9,$2
46296		 xor   $25,$10,$9
46297		 and   $17,$17,$25
46298		 srl   $17,$17,31        	 # Set Overflow
46299		 slt   $19,$10,$0        	 # Set Sign
46300		 sltiu $18,$10,1         	 # Set Zero
46301		 addiu $15,$15,-18
46302		 bgez  $15,3f
46303		 lhu   $24,0x00($23)    	 # Delay slot
46304		 j     MainExit
46305	3:
46306		 sll   $7,$24,2         	 # Delay slot
46307		 addu  $7,$7,$30
46308		 lw    $7,0x00($7)
46309		 jr    $7
46310		 nop                    	 # Delay slot
46311
46312OP0_b0b9:				#:
46313		 addiu $23,$23,2
46314
46315		 srl   $24,$24,7
46316		 andi  $24,$24,0x1C
46317		 addu  $24,$24,$21
46318		 lw    $9,0x00($24)
46319		 lhu   $14,0x00($23)
46320		 lhu   $25,0x02($23)
46321		 sll   $14,$14,16
46322		 or    $14,$14,$25
46323		 addiu $23,$23,4
46324		 lw    $25,0x84($21)
46325		 sw    $15,m68k_ICount
46326		 sw    $9,0x44($29)
46327		 sw    $24,0x40($29)
46328		 or    $4,$0,$14
46329		 jalr  $25
46330		 sw    $23,0x4C($21)    	 # Delay slot
46331		 lw    $24,0x40($29)
46332		 lw    $9,0x44($29)
46333		 lw    $15,m68k_ICount
46334		 subu  $10,$9,$2
46335		 sltu  $16,$9,$2       	 # Set Carry
46336		 xor   $17,$9,$2
46337		 xor   $25,$10,$9
46338		 and   $17,$17,$25
46339		 srl   $17,$17,31        	 # Set Overflow
46340		 slt   $19,$10,$0        	 # Set Sign
46341		 sltiu $18,$10,1         	 # Set Zero
46342		 addiu $15,$15,-22
46343		 bgez  $15,3f
46344		 lhu   $24,0x00($23)    	 # Delay slot
46345		 j     MainExit
46346	3:
46347		 sll   $7,$24,2         	 # Delay slot
46348		 addu  $7,$7,$30
46349		 lw    $7,0x00($7)
46350		 jr    $7
46351		 nop                    	 # Delay slot
46352
46353OP0_b0ba:				#:
46354		 addiu $23,$23,2
46355
46356		 srl   $24,$24,7
46357		 andi  $24,$24,0x1C
46358		 addu  $24,$24,$21
46359		 lw    $9,0x00($24)
46360		 lh    $7,0x00($23)
46361		 subu  $25,$23,$22
46362		 addu  $14,$25,$7       	 # Add Offset to PC
46363		 addiu $23,$23,2
46364		 lw    $25,0xA0($21)
46365		 sw    $15,m68k_ICount
46366		 sw    $9,0x44($29)
46367		 sw    $24,0x40($29)
46368		 or    $4,$0,$14
46369		 jalr  $25
46370		 sw    $23,0x4C($21)    	 # Delay slot
46371		 lw    $24,0x40($29)
46372		 lw    $9,0x44($29)
46373		 lw    $15,m68k_ICount
46374		 subu  $10,$9,$2
46375		 sltu  $16,$9,$2       	 # Set Carry
46376		 xor   $17,$9,$2
46377		 xor   $25,$10,$9
46378		 and   $17,$17,$25
46379		 srl   $17,$17,31        	 # Set Overflow
46380		 slt   $19,$10,$0        	 # Set Sign
46381		 sltiu $18,$10,1         	 # Set Zero
46382		 addiu $15,$15,-18
46383		 bgez  $15,3f
46384		 lhu   $24,0x00($23)    	 # Delay slot
46385		 j     MainExit
46386	3:
46387		 sll   $7,$24,2         	 # Delay slot
46388		 addu  $7,$7,$30
46389		 lw    $7,0x00($7)
46390		 jr    $7
46391		 nop                    	 # Delay slot
46392
46393OP0_b0bb:				#:
46394		 addiu $23,$23,2
46395
46396		 srl   $24,$24,7
46397		 andi  $24,$24,0x1C
46398		 addu  $24,$24,$21
46399		 lw    $9,0x00($24)
46400		 subu  $14,$23,$22       	 # Get PC
46401		 lhu   $7,0x00($23)
46402		 addiu $23,$23,2
46403		 seb   $6,$7
46404		 or    $25,$0,$7
46405		 srl   $7,$7,12
46406		 andi  $25,$25,0x0800
46407		 sll   $7,$7,2
46408		 addu  $7,$7,$21
46409		 bne   $25,$0,0f
46410		 lw    $25,0x00($7)      	 # Delay slot
46411		 seh   $25,$25
46412	0:
46413		 addu  $25,$14,$25
46414		 addu  $14,$25,$6
46415		 lw    $25,0xA0($21)
46416		 sw    $15,m68k_ICount
46417		 sw    $9,0x44($29)
46418		 sw    $24,0x40($29)
46419		 or    $4,$0,$14
46420		 jalr  $25
46421		 sw    $23,0x4C($21)    	 # Delay slot
46422		 lw    $24,0x40($29)
46423		 lw    $9,0x44($29)
46424		 lw    $15,m68k_ICount
46425		 subu  $10,$9,$2
46426		 sltu  $16,$9,$2       	 # Set Carry
46427		 xor   $17,$9,$2
46428		 xor   $25,$10,$9
46429		 and   $17,$17,$25
46430		 srl   $17,$17,31        	 # Set Overflow
46431		 slt   $19,$10,$0        	 # Set Sign
46432		 sltiu $18,$10,1         	 # Set Zero
46433		 addiu $15,$15,-20
46434		 bgez  $15,3f
46435		 lhu   $24,0x00($23)    	 # Delay slot
46436		 j     MainExit
46437	3:
46438		 sll   $7,$24,2         	 # Delay slot
46439		 addu  $7,$7,$30
46440		 lw    $7,0x00($7)
46441		 jr    $7
46442		 nop                    	 # Delay slot
46443
46444OP0_b0bc:				#:
46445		 addiu $23,$23,2
46446
46447		 srl   $24,$24,7
46448		 andi  $24,$24,0x1C
46449		 addu  $24,$24,$21
46450		 lw    $9,0x00($24)
46451		 lhu   $2,0x00($23)
46452		 lhu   $25,0x02($23)
46453		 sll   $2,$2,16
46454		 or    $2,$2,$25
46455		 addiu $23,$23,4
46456		 subu  $10,$9,$2
46457		 sltu  $16,$9,$2       	 # Set Carry
46458		 xor   $17,$9,$2
46459		 xor   $25,$10,$9
46460		 and   $17,$17,$25
46461		 srl   $17,$17,31        	 # Set Overflow
46462		 slt   $19,$10,$0        	 # Set Sign
46463		 sltiu $18,$10,1         	 # Set Zero
46464		 addiu $15,$15,-6
46465		 bgez  $15,3f
46466		 lhu   $24,0x00($23)    	 # Delay slot
46467		 j     MainExit
46468	3:
46469		 sll   $7,$24,2         	 # Delay slot
46470		 addu  $7,$7,$30
46471		 lw    $7,0x00($7)
46472		 jr    $7
46473		 nop                    	 # Delay slot
46474
46475OP0_b0c0:				#:
46476		 addiu $23,$23,2
46477
46478		 andi  $8,$24,0x0f
46479		 srl   $24,$24,7
46480		 andi  $24,$24,0x1C
46481		 addu  $24,$24,$21
46482		 lw    $9,0x20($24)
46483		 sll   $8,$8,2
46484		 addu  $8,$8,$21
46485		 lh    $2,0x00($8)
46486		 subu  $10,$9,$2
46487		 sltu  $16,$9,$2       	 # Set Carry
46488		 xor   $17,$9,$2
46489		 xor   $25,$10,$9
46490		 and   $17,$17,$25
46491		 srl   $17,$17,31        	 # Set Overflow
46492		 slt   $19,$10,$0        	 # Set Sign
46493		 sltiu $18,$10,1         	 # Set Zero
46494		 addiu $15,$15,-4
46495		 bgez  $15,3f
46496		 lhu   $24,0x00($23)    	 # Delay slot
46497		 j     MainExit
46498	3:
46499		 sll   $7,$24,2         	 # Delay slot
46500		 addu  $7,$7,$30
46501		 lw    $7,0x00($7)
46502		 jr    $7
46503		 nop                    	 # Delay slot
46504
46505OP0_b0d0:				#:
46506		 addiu $23,$23,2
46507
46508		 andi  $8,$24,0x07
46509		 srl   $24,$24,7
46510		 andi  $24,$24,0x1C
46511		 addu  $24,$24,$21
46512		 lw    $9,0x20($24)
46513		 sll   $8,$8,2
46514		 addu  $8,$8,$21
46515		 lw    $14,0x20($8)
46516		 lw    $25,0x80($21)
46517		 sw    $15,m68k_ICount
46518		 sw    $9,0x44($29)
46519		 sw    $24,0x40($29)
46520		 or    $4,$0,$14
46521		 jalr  $25
46522		 sw    $23,0x4C($21)    	 # Delay slot
46523		 lw    $24,0x40($29)
46524		 lw    $9,0x44($29)
46525		 lw    $15,m68k_ICount
46526		 seh   $2,$2
46527		 subu  $10,$9,$2
46528		 sltu  $16,$9,$2       	 # Set Carry
46529		 xor   $17,$9,$2
46530		 xor   $25,$10,$9
46531		 and   $17,$17,$25
46532		 srl   $17,$17,31        	 # Set Overflow
46533		 slt   $19,$10,$0        	 # Set Sign
46534		 sltiu $18,$10,1         	 # Set Zero
46535		 addiu $15,$15,-8
46536		 bgez  $15,3f
46537		 lhu   $24,0x00($23)    	 # Delay slot
46538		 j     MainExit
46539	3:
46540		 sll   $7,$24,2         	 # Delay slot
46541		 addu  $7,$7,$30
46542		 lw    $7,0x00($7)
46543		 jr    $7
46544		 nop                    	 # Delay slot
46545
46546OP0_b0d8:				#:
46547		 addiu $23,$23,2
46548
46549		 andi  $8,$24,0x07
46550		 srl   $24,$24,7
46551		 andi  $24,$24,0x1C
46552		 addu  $24,$24,$21
46553		 lw    $9,0x20($24)
46554		 sll   $8,$8,2
46555		 addu  $8,$8,$21
46556		 lw    $14,0x20($8)
46557		 addiu $25,$14,2
46558		 sw    $25,0x20($8)
46559		 lw    $25,0x80($21)
46560		 sw    $15,m68k_ICount
46561		 sw    $9,0x44($29)
46562		 sw    $24,0x40($29)
46563		 or    $4,$0,$14
46564		 jalr  $25
46565		 sw    $23,0x4C($21)    	 # Delay slot
46566		 lw    $24,0x40($29)
46567		 lw    $9,0x44($29)
46568		 lw    $15,m68k_ICount
46569		 seh   $2,$2
46570		 subu  $10,$9,$2
46571		 sltu  $16,$9,$2       	 # Set Carry
46572		 xor   $17,$9,$2
46573		 xor   $25,$10,$9
46574		 and   $17,$17,$25
46575		 srl   $17,$17,31        	 # Set Overflow
46576		 slt   $19,$10,$0        	 # Set Sign
46577		 sltiu $18,$10,1         	 # Set Zero
46578		 addiu $15,$15,-8
46579		 bgez  $15,3f
46580		 lhu   $24,0x00($23)    	 # Delay slot
46581		 j     MainExit
46582	3:
46583		 sll   $7,$24,2         	 # Delay slot
46584		 addu  $7,$7,$30
46585		 lw    $7,0x00($7)
46586		 jr    $7
46587		 nop                    	 # Delay slot
46588
46589OP0_b0e0:				#:
46590		 addiu $23,$23,2
46591
46592		 andi  $8,$24,0x07
46593		 srl   $24,$24,7
46594		 andi  $24,$24,0x1C
46595		 addu  $24,$24,$21
46596		 lw    $9,0x20($24)
46597		 sll   $8,$8,2
46598		 addu  $8,$8,$21
46599		 lw    $14,0x20($8)
46600		 addiu $14,$14,-2
46601		 sw    $14,0x20($8)
46602		 lw    $25,0x80($21)
46603		 sw    $15,m68k_ICount
46604		 sw    $9,0x44($29)
46605		 sw    $24,0x40($29)
46606		 or    $4,$0,$14
46607		 jalr  $25
46608		 sw    $23,0x4C($21)    	 # Delay slot
46609		 lw    $24,0x40($29)
46610		 lw    $9,0x44($29)
46611		 lw    $15,m68k_ICount
46612		 seh   $2,$2
46613		 subu  $10,$9,$2
46614		 sltu  $16,$9,$2       	 # Set Carry
46615		 xor   $17,$9,$2
46616		 xor   $25,$10,$9
46617		 and   $17,$17,$25
46618		 srl   $17,$17,31        	 # Set Overflow
46619		 slt   $19,$10,$0        	 # Set Sign
46620		 sltiu $18,$10,1         	 # Set Zero
46621		 addiu $15,$15,-10
46622		 bgez  $15,3f
46623		 lhu   $24,0x00($23)    	 # Delay slot
46624		 j     MainExit
46625	3:
46626		 sll   $7,$24,2         	 # Delay slot
46627		 addu  $7,$7,$30
46628		 lw    $7,0x00($7)
46629		 jr    $7
46630		 nop                    	 # Delay slot
46631
46632OP0_b0e8:				#:
46633		 addiu $23,$23,2
46634
46635		 andi  $8,$24,0x07
46636		 srl   $24,$24,7
46637		 andi  $24,$24,0x1C
46638		 addu  $24,$24,$21
46639		 lw    $9,0x20($24)
46640		 lh    $7,0x00($23)
46641		 sll   $8,$8,2
46642		 addu  $8,$8,$21
46643		 lw    $14,0x20($8)
46644		 addiu $23,$23,2
46645		 addu  $14,$14,$7
46646		 lw    $25,0x80($21)
46647		 sw    $15,m68k_ICount
46648		 sw    $9,0x44($29)
46649		 sw    $24,0x40($29)
46650		 or    $4,$0,$14
46651		 jalr  $25
46652		 sw    $23,0x4C($21)    	 # Delay slot
46653		 lw    $24,0x40($29)
46654		 lw    $9,0x44($29)
46655		 lw    $15,m68k_ICount
46656		 seh   $2,$2
46657		 subu  $10,$9,$2
46658		 sltu  $16,$9,$2       	 # Set Carry
46659		 xor   $17,$9,$2
46660		 xor   $25,$10,$9
46661		 and   $17,$17,$25
46662		 srl   $17,$17,31        	 # Set Overflow
46663		 slt   $19,$10,$0        	 # Set Sign
46664		 sltiu $18,$10,1         	 # Set Zero
46665		 addiu $15,$15,-12
46666		 bgez  $15,3f
46667		 lhu   $24,0x00($23)    	 # Delay slot
46668		 j     MainExit
46669	3:
46670		 sll   $7,$24,2         	 # Delay slot
46671		 addu  $7,$7,$30
46672		 lw    $7,0x00($7)
46673		 jr    $7
46674		 nop                    	 # Delay slot
46675
46676OP0_b0f0:				#:
46677		 addiu $23,$23,2
46678
46679		 andi  $8,$24,0x07
46680		 srl   $24,$24,7
46681		 andi  $24,$24,0x1C
46682		 addu  $24,$24,$21
46683		 lw    $9,0x20($24)
46684		 sll   $8,$8,2
46685		 addu  $8,$8,$21
46686		 lw    $14,0x20($8)
46687		 lhu   $7,0x00($23)
46688		 addiu $23,$23,2
46689		 seb   $6,$7
46690		 or    $25,$0,$7
46691		 srl   $7,$7,12
46692		 andi  $25,$25,0x0800
46693		 sll   $7,$7,2
46694		 addu  $7,$7,$21
46695		 bne   $25,$0,0f
46696		 lw    $25,0x00($7)      	 # Delay slot
46697		 seh   $25,$25
46698	0:
46699		 addu  $25,$14,$25
46700		 addu  $14,$25,$6
46701		 lw    $25,0x80($21)
46702		 sw    $15,m68k_ICount
46703		 sw    $9,0x44($29)
46704		 sw    $24,0x40($29)
46705		 or    $4,$0,$14
46706		 jalr  $25
46707		 sw    $23,0x4C($21)    	 # Delay slot
46708		 lw    $24,0x40($29)
46709		 lw    $9,0x44($29)
46710		 lw    $15,m68k_ICount
46711		 seh   $2,$2
46712		 subu  $10,$9,$2
46713		 sltu  $16,$9,$2       	 # Set Carry
46714		 xor   $17,$9,$2
46715		 xor   $25,$10,$9
46716		 and   $17,$17,$25
46717		 srl   $17,$17,31        	 # Set Overflow
46718		 slt   $19,$10,$0        	 # Set Sign
46719		 sltiu $18,$10,1         	 # Set Zero
46720		 addiu $15,$15,-14
46721		 bgez  $15,3f
46722		 lhu   $24,0x00($23)    	 # Delay slot
46723		 j     MainExit
46724	3:
46725		 sll   $7,$24,2         	 # Delay slot
46726		 addu  $7,$7,$30
46727		 lw    $7,0x00($7)
46728		 jr    $7
46729		 nop                    	 # Delay slot
46730
46731OP0_b0f8:				#:
46732		 addiu $23,$23,2
46733
46734		 srl   $24,$24,7
46735		 andi  $24,$24,0x1C
46736		 addu  $24,$24,$21
46737		 lw    $9,0x20($24)
46738		 lh    $14,0x00($23)
46739		 addiu $23,$23,2
46740		 lw    $25,0x80($21)
46741		 sw    $15,m68k_ICount
46742		 sw    $9,0x44($29)
46743		 sw    $24,0x40($29)
46744		 or    $4,$0,$14
46745		 jalr  $25
46746		 sw    $23,0x4C($21)    	 # Delay slot
46747		 lw    $24,0x40($29)
46748		 lw    $9,0x44($29)
46749		 lw    $15,m68k_ICount
46750		 seh   $2,$2
46751		 subu  $10,$9,$2
46752		 sltu  $16,$9,$2       	 # Set Carry
46753		 xor   $17,$9,$2
46754		 xor   $25,$10,$9
46755		 and   $17,$17,$25
46756		 srl   $17,$17,31        	 # Set Overflow
46757		 slt   $19,$10,$0        	 # Set Sign
46758		 sltiu $18,$10,1         	 # Set Zero
46759		 addiu $15,$15,-12
46760		 bgez  $15,3f
46761		 lhu   $24,0x00($23)    	 # Delay slot
46762		 j     MainExit
46763	3:
46764		 sll   $7,$24,2         	 # Delay slot
46765		 addu  $7,$7,$30
46766		 lw    $7,0x00($7)
46767		 jr    $7
46768		 nop                    	 # Delay slot
46769
46770OP0_b0f9:				#:
46771		 addiu $23,$23,2
46772
46773		 srl   $24,$24,7
46774		 andi  $24,$24,0x1C
46775		 addu  $24,$24,$21
46776		 lw    $9,0x20($24)
46777		 lhu   $14,0x00($23)
46778		 lhu   $25,0x02($23)
46779		 sll   $14,$14,16
46780		 or    $14,$14,$25
46781		 addiu $23,$23,4
46782		 lw    $25,0x80($21)
46783		 sw    $15,m68k_ICount
46784		 sw    $9,0x44($29)
46785		 sw    $24,0x40($29)
46786		 or    $4,$0,$14
46787		 jalr  $25
46788		 sw    $23,0x4C($21)    	 # Delay slot
46789		 lw    $24,0x40($29)
46790		 lw    $9,0x44($29)
46791		 lw    $15,m68k_ICount
46792		 seh   $2,$2
46793		 subu  $10,$9,$2
46794		 sltu  $16,$9,$2       	 # Set Carry
46795		 xor   $17,$9,$2
46796		 xor   $25,$10,$9
46797		 and   $17,$17,$25
46798		 srl   $17,$17,31        	 # Set Overflow
46799		 slt   $19,$10,$0        	 # Set Sign
46800		 sltiu $18,$10,1         	 # Set Zero
46801		 addiu $15,$15,-16
46802		 bgez  $15,3f
46803		 lhu   $24,0x00($23)    	 # Delay slot
46804		 j     MainExit
46805	3:
46806		 sll   $7,$24,2         	 # Delay slot
46807		 addu  $7,$7,$30
46808		 lw    $7,0x00($7)
46809		 jr    $7
46810		 nop                    	 # Delay slot
46811
46812OP0_b0fa:				#:
46813		 addiu $23,$23,2
46814
46815		 srl   $24,$24,7
46816		 andi  $24,$24,0x1C
46817		 addu  $24,$24,$21
46818		 lw    $9,0x20($24)
46819		 lh    $7,0x00($23)
46820		 subu  $25,$23,$22
46821		 addu  $14,$25,$7       	 # Add Offset to PC
46822		 addiu $23,$23,2
46823		 lw    $25,0x9C($21)
46824		 sw    $15,m68k_ICount
46825		 sw    $9,0x44($29)
46826		 sw    $24,0x40($29)
46827		 or    $4,$0,$14
46828		 jalr  $25
46829		 sw    $23,0x4C($21)    	 # Delay slot
46830		 lw    $24,0x40($29)
46831		 lw    $9,0x44($29)
46832		 lw    $15,m68k_ICount
46833		 seh   $2,$2
46834		 subu  $10,$9,$2
46835		 sltu  $16,$9,$2       	 # Set Carry
46836		 xor   $17,$9,$2
46837		 xor   $25,$10,$9
46838		 and   $17,$17,$25
46839		 srl   $17,$17,31        	 # Set Overflow
46840		 slt   $19,$10,$0        	 # Set Sign
46841		 sltiu $18,$10,1         	 # Set Zero
46842		 addiu $15,$15,-12
46843		 bgez  $15,3f
46844		 lhu   $24,0x00($23)    	 # Delay slot
46845		 j     MainExit
46846	3:
46847		 sll   $7,$24,2         	 # Delay slot
46848		 addu  $7,$7,$30
46849		 lw    $7,0x00($7)
46850		 jr    $7
46851		 nop                    	 # Delay slot
46852
46853OP0_b0fb:				#:
46854		 addiu $23,$23,2
46855
46856		 srl   $24,$24,7
46857		 andi  $24,$24,0x1C
46858		 addu  $24,$24,$21
46859		 lw    $9,0x20($24)
46860		 subu  $14,$23,$22       	 # Get PC
46861		 lhu   $7,0x00($23)
46862		 addiu $23,$23,2
46863		 seb   $6,$7
46864		 or    $25,$0,$7
46865		 srl   $7,$7,12
46866		 andi  $25,$25,0x0800
46867		 sll   $7,$7,2
46868		 addu  $7,$7,$21
46869		 bne   $25,$0,0f
46870		 lw    $25,0x00($7)      	 # Delay slot
46871		 seh   $25,$25
46872	0:
46873		 addu  $25,$14,$25
46874		 addu  $14,$25,$6
46875		 lw    $25,0x9C($21)
46876		 sw    $15,m68k_ICount
46877		 sw    $9,0x44($29)
46878		 sw    $24,0x40($29)
46879		 or    $4,$0,$14
46880		 jalr  $25
46881		 sw    $23,0x4C($21)    	 # Delay slot
46882		 lw    $24,0x40($29)
46883		 lw    $9,0x44($29)
46884		 lw    $15,m68k_ICount
46885		 seh   $2,$2
46886		 subu  $10,$9,$2
46887		 sltu  $16,$9,$2       	 # Set Carry
46888		 xor   $17,$9,$2
46889		 xor   $25,$10,$9
46890		 and   $17,$17,$25
46891		 srl   $17,$17,31        	 # Set Overflow
46892		 slt   $19,$10,$0        	 # Set Sign
46893		 sltiu $18,$10,1         	 # Set Zero
46894		 addiu $15,$15,-14
46895		 bgez  $15,3f
46896		 lhu   $24,0x00($23)    	 # Delay slot
46897		 j     MainExit
46898	3:
46899		 sll   $7,$24,2         	 # Delay slot
46900		 addu  $7,$7,$30
46901		 lw    $7,0x00($7)
46902		 jr    $7
46903		 nop                    	 # Delay slot
46904
46905OP0_b0fc:				#:
46906		 addiu $23,$23,2
46907
46908		 srl   $24,$24,7
46909		 andi  $24,$24,0x1C
46910		 addu  $24,$24,$21
46911		 lw    $9,0x20($24)
46912		 lh    $2,0x00($23)
46913		 addiu $23,$23,2
46914		 subu  $10,$9,$2
46915		 sltu  $16,$9,$2       	 # Set Carry
46916		 xor   $17,$9,$2
46917		 xor   $25,$10,$9
46918		 and   $17,$17,$25
46919		 srl   $17,$17,31        	 # Set Overflow
46920		 slt   $19,$10,$0        	 # Set Sign
46921		 sltiu $18,$10,1         	 # Set Zero
46922		 addiu $15,$15,-4
46923		 bgez  $15,3f
46924		 lhu   $24,0x00($23)    	 # Delay slot
46925		 j     MainExit
46926	3:
46927		 sll   $7,$24,2         	 # Delay slot
46928		 addu  $7,$7,$30
46929		 lw    $7,0x00($7)
46930		 jr    $7
46931		 nop                    	 # Delay slot
46932
46933OP0_b1c0:				#:
46934		 addiu $23,$23,2
46935
46936		 andi  $8,$24,0x0f
46937		 srl   $24,$24,7
46938		 andi  $24,$24,0x1C
46939		 addu  $24,$24,$21
46940		 lw    $9,0x20($24)
46941		 sll   $8,$8,2
46942		 addu  $8,$8,$21
46943		 lw    $2,0x00($8)
46944		 subu  $10,$9,$2
46945		 sltu  $16,$9,$2       	 # Set Carry
46946		 xor   $17,$9,$2
46947		 xor   $25,$10,$9
46948		 and   $17,$17,$25
46949		 srl   $17,$17,31        	 # Set Overflow
46950		 slt   $19,$10,$0        	 # Set Sign
46951		 sltiu $18,$10,1         	 # Set Zero
46952		 addiu $15,$15,-8
46953		 bgez  $15,3f
46954		 lhu   $24,0x00($23)    	 # Delay slot
46955		 j     MainExit
46956	3:
46957		 sll   $7,$24,2         	 # Delay slot
46958		 addu  $7,$7,$30
46959		 lw    $7,0x00($7)
46960		 jr    $7
46961		 nop                    	 # Delay slot
46962
46963OP0_b1d0:				#:
46964		 addiu $23,$23,2
46965
46966		 andi  $8,$24,0x07
46967		 srl   $24,$24,7
46968		 andi  $24,$24,0x1C
46969		 addu  $24,$24,$21
46970		 lw    $9,0x20($24)
46971		 sll   $8,$8,2
46972		 addu  $8,$8,$21
46973		 lw    $14,0x20($8)
46974		 lw    $25,0x84($21)
46975		 sw    $15,m68k_ICount
46976		 sw    $9,0x44($29)
46977		 sw    $24,0x40($29)
46978		 or    $4,$0,$14
46979		 jalr  $25
46980		 sw    $23,0x4C($21)    	 # Delay slot
46981		 lw    $24,0x40($29)
46982		 lw    $9,0x44($29)
46983		 lw    $15,m68k_ICount
46984		 subu  $10,$9,$2
46985		 sltu  $16,$9,$2       	 # Set Carry
46986		 xor   $17,$9,$2
46987		 xor   $25,$10,$9
46988		 and   $17,$17,$25
46989		 srl   $17,$17,31        	 # Set Overflow
46990		 slt   $19,$10,$0        	 # Set Sign
46991		 sltiu $18,$10,1         	 # Set Zero
46992		 addiu $15,$15,-14
46993		 bgez  $15,3f
46994		 lhu   $24,0x00($23)    	 # Delay slot
46995		 j     MainExit
46996	3:
46997		 sll   $7,$24,2         	 # Delay slot
46998		 addu  $7,$7,$30
46999		 lw    $7,0x00($7)
47000		 jr    $7
47001		 nop                    	 # Delay slot
47002
47003OP0_b1d8:				#:
47004		 addiu $23,$23,2
47005
47006		 andi  $8,$24,0x07
47007		 srl   $24,$24,7
47008		 andi  $24,$24,0x1C
47009		 addu  $24,$24,$21
47010		 lw    $9,0x20($24)
47011		 sll   $8,$8,2
47012		 addu  $8,$8,$21
47013		 lw    $14,0x20($8)
47014		 addiu $25,$14,4
47015		 sw    $25,0x20($8)
47016		 lw    $25,0x84($21)
47017		 sw    $15,m68k_ICount
47018		 sw    $9,0x44($29)
47019		 sw    $24,0x40($29)
47020		 or    $4,$0,$14
47021		 jalr  $25
47022		 sw    $23,0x4C($21)    	 # Delay slot
47023		 lw    $24,0x40($29)
47024		 lw    $9,0x44($29)
47025		 lw    $15,m68k_ICount
47026		 subu  $10,$9,$2
47027		 sltu  $16,$9,$2       	 # Set Carry
47028		 xor   $17,$9,$2
47029		 xor   $25,$10,$9
47030		 and   $17,$17,$25
47031		 srl   $17,$17,31        	 # Set Overflow
47032		 slt   $19,$10,$0        	 # Set Sign
47033		 sltiu $18,$10,1         	 # Set Zero
47034		 addiu $15,$15,-14
47035		 bgez  $15,3f
47036		 lhu   $24,0x00($23)    	 # Delay slot
47037		 j     MainExit
47038	3:
47039		 sll   $7,$24,2         	 # Delay slot
47040		 addu  $7,$7,$30
47041		 lw    $7,0x00($7)
47042		 jr    $7
47043		 nop                    	 # Delay slot
47044
47045OP0_b1e0:				#:
47046		 addiu $23,$23,2
47047
47048		 andi  $8,$24,0x07
47049		 srl   $24,$24,7
47050		 andi  $24,$24,0x1C
47051		 addu  $24,$24,$21
47052		 lw    $9,0x20($24)
47053		 sll   $8,$8,2
47054		 addu  $8,$8,$21
47055		 lw    $14,0x20($8)
47056		 addiu $14,$14,-4
47057		 sw    $14,0x20($8)
47058		 lw    $25,0x84($21)
47059		 sw    $15,m68k_ICount
47060		 sw    $9,0x44($29)
47061		 sw    $24,0x40($29)
47062		 or    $4,$0,$14
47063		 jalr  $25
47064		 sw    $23,0x4C($21)    	 # Delay slot
47065		 lw    $24,0x40($29)
47066		 lw    $9,0x44($29)
47067		 lw    $15,m68k_ICount
47068		 subu  $10,$9,$2
47069		 sltu  $16,$9,$2       	 # Set Carry
47070		 xor   $17,$9,$2
47071		 xor   $25,$10,$9
47072		 and   $17,$17,$25
47073		 srl   $17,$17,31        	 # Set Overflow
47074		 slt   $19,$10,$0        	 # Set Sign
47075		 sltiu $18,$10,1         	 # Set Zero
47076		 addiu $15,$15,-16
47077		 bgez  $15,3f
47078		 lhu   $24,0x00($23)    	 # Delay slot
47079		 j     MainExit
47080	3:
47081		 sll   $7,$24,2         	 # Delay slot
47082		 addu  $7,$7,$30
47083		 lw    $7,0x00($7)
47084		 jr    $7
47085		 nop                    	 # Delay slot
47086
47087OP0_b1e8:				#:
47088		 addiu $23,$23,2
47089
47090		 andi  $8,$24,0x07
47091		 srl   $24,$24,7
47092		 andi  $24,$24,0x1C
47093		 addu  $24,$24,$21
47094		 lw    $9,0x20($24)
47095		 lh    $7,0x00($23)
47096		 sll   $8,$8,2
47097		 addu  $8,$8,$21
47098		 lw    $14,0x20($8)
47099		 addiu $23,$23,2
47100		 addu  $14,$14,$7
47101		 lw    $25,0x84($21)
47102		 sw    $15,m68k_ICount
47103		 sw    $9,0x44($29)
47104		 sw    $24,0x40($29)
47105		 or    $4,$0,$14
47106		 jalr  $25
47107		 sw    $23,0x4C($21)    	 # Delay slot
47108		 lw    $24,0x40($29)
47109		 lw    $9,0x44($29)
47110		 lw    $15,m68k_ICount
47111		 subu  $10,$9,$2
47112		 sltu  $16,$9,$2       	 # Set Carry
47113		 xor   $17,$9,$2
47114		 xor   $25,$10,$9
47115		 and   $17,$17,$25
47116		 srl   $17,$17,31        	 # Set Overflow
47117		 slt   $19,$10,$0        	 # Set Sign
47118		 sltiu $18,$10,1         	 # Set Zero
47119		 addiu $15,$15,-18
47120		 bgez  $15,3f
47121		 lhu   $24,0x00($23)    	 # Delay slot
47122		 j     MainExit
47123	3:
47124		 sll   $7,$24,2         	 # Delay slot
47125		 addu  $7,$7,$30
47126		 lw    $7,0x00($7)
47127		 jr    $7
47128		 nop                    	 # Delay slot
47129
47130OP0_b1f0:				#:
47131		 addiu $23,$23,2
47132
47133		 andi  $8,$24,0x07
47134		 srl   $24,$24,7
47135		 andi  $24,$24,0x1C
47136		 addu  $24,$24,$21
47137		 lw    $9,0x20($24)
47138		 sll   $8,$8,2
47139		 addu  $8,$8,$21
47140		 lw    $14,0x20($8)
47141		 lhu   $7,0x00($23)
47142		 addiu $23,$23,2
47143		 seb   $6,$7
47144		 or    $25,$0,$7
47145		 srl   $7,$7,12
47146		 andi  $25,$25,0x0800
47147		 sll   $7,$7,2
47148		 addu  $7,$7,$21
47149		 bne   $25,$0,0f
47150		 lw    $25,0x00($7)      	 # Delay slot
47151		 seh   $25,$25
47152	0:
47153		 addu  $25,$14,$25
47154		 addu  $14,$25,$6
47155		 lw    $25,0x84($21)
47156		 sw    $15,m68k_ICount
47157		 sw    $9,0x44($29)
47158		 sw    $24,0x40($29)
47159		 or    $4,$0,$14
47160		 jalr  $25
47161		 sw    $23,0x4C($21)    	 # Delay slot
47162		 lw    $24,0x40($29)
47163		 lw    $9,0x44($29)
47164		 lw    $15,m68k_ICount
47165		 subu  $10,$9,$2
47166		 sltu  $16,$9,$2       	 # Set Carry
47167		 xor   $17,$9,$2
47168		 xor   $25,$10,$9
47169		 and   $17,$17,$25
47170		 srl   $17,$17,31        	 # Set Overflow
47171		 slt   $19,$10,$0        	 # Set Sign
47172		 sltiu $18,$10,1         	 # Set Zero
47173		 addiu $15,$15,-20
47174		 bgez  $15,3f
47175		 lhu   $24,0x00($23)    	 # Delay slot
47176		 j     MainExit
47177	3:
47178		 sll   $7,$24,2         	 # Delay slot
47179		 addu  $7,$7,$30
47180		 lw    $7,0x00($7)
47181		 jr    $7
47182		 nop                    	 # Delay slot
47183
47184OP0_b1f8:				#:
47185		 addiu $23,$23,2
47186
47187		 srl   $24,$24,7
47188		 andi  $24,$24,0x1C
47189		 addu  $24,$24,$21
47190		 lw    $9,0x20($24)
47191		 lh    $14,0x00($23)
47192		 addiu $23,$23,2
47193		 lw    $25,0x84($21)
47194		 sw    $15,m68k_ICount
47195		 sw    $9,0x44($29)
47196		 sw    $24,0x40($29)
47197		 or    $4,$0,$14
47198		 jalr  $25
47199		 sw    $23,0x4C($21)    	 # Delay slot
47200		 lw    $24,0x40($29)
47201		 lw    $9,0x44($29)
47202		 lw    $15,m68k_ICount
47203		 subu  $10,$9,$2
47204		 sltu  $16,$9,$2       	 # Set Carry
47205		 xor   $17,$9,$2
47206		 xor   $25,$10,$9
47207		 and   $17,$17,$25
47208		 srl   $17,$17,31        	 # Set Overflow
47209		 slt   $19,$10,$0        	 # Set Sign
47210		 sltiu $18,$10,1         	 # Set Zero
47211		 addiu $15,$15,-18
47212		 bgez  $15,3f
47213		 lhu   $24,0x00($23)    	 # Delay slot
47214		 j     MainExit
47215	3:
47216		 sll   $7,$24,2         	 # Delay slot
47217		 addu  $7,$7,$30
47218		 lw    $7,0x00($7)
47219		 jr    $7
47220		 nop                    	 # Delay slot
47221
47222OP0_b1f9:				#:
47223		 addiu $23,$23,2
47224
47225		 srl   $24,$24,7
47226		 andi  $24,$24,0x1C
47227		 addu  $24,$24,$21
47228		 lw    $9,0x20($24)
47229		 lhu   $14,0x00($23)
47230		 lhu   $25,0x02($23)
47231		 sll   $14,$14,16
47232		 or    $14,$14,$25
47233		 addiu $23,$23,4
47234		 lw    $25,0x84($21)
47235		 sw    $15,m68k_ICount
47236		 sw    $9,0x44($29)
47237		 sw    $24,0x40($29)
47238		 or    $4,$0,$14
47239		 jalr  $25
47240		 sw    $23,0x4C($21)    	 # Delay slot
47241		 lw    $24,0x40($29)
47242		 lw    $9,0x44($29)
47243		 lw    $15,m68k_ICount
47244		 subu  $10,$9,$2
47245		 sltu  $16,$9,$2       	 # Set Carry
47246		 xor   $17,$9,$2
47247		 xor   $25,$10,$9
47248		 and   $17,$17,$25
47249		 srl   $17,$17,31        	 # Set Overflow
47250		 slt   $19,$10,$0        	 # Set Sign
47251		 sltiu $18,$10,1         	 # Set Zero
47252		 addiu $15,$15,-22
47253		 bgez  $15,3f
47254		 lhu   $24,0x00($23)    	 # Delay slot
47255		 j     MainExit
47256	3:
47257		 sll   $7,$24,2         	 # Delay slot
47258		 addu  $7,$7,$30
47259		 lw    $7,0x00($7)
47260		 jr    $7
47261		 nop                    	 # Delay slot
47262
47263OP0_b1fa:				#:
47264		 addiu $23,$23,2
47265
47266		 srl   $24,$24,7
47267		 andi  $24,$24,0x1C
47268		 addu  $24,$24,$21
47269		 lw    $9,0x20($24)
47270		 lh    $7,0x00($23)
47271		 subu  $25,$23,$22
47272		 addu  $14,$25,$7       	 # Add Offset to PC
47273		 addiu $23,$23,2
47274		 lw    $25,0xA0($21)
47275		 sw    $15,m68k_ICount
47276		 sw    $9,0x44($29)
47277		 sw    $24,0x40($29)
47278		 or    $4,$0,$14
47279		 jalr  $25
47280		 sw    $23,0x4C($21)    	 # Delay slot
47281		 lw    $24,0x40($29)
47282		 lw    $9,0x44($29)
47283		 lw    $15,m68k_ICount
47284		 subu  $10,$9,$2
47285		 sltu  $16,$9,$2       	 # Set Carry
47286		 xor   $17,$9,$2
47287		 xor   $25,$10,$9
47288		 and   $17,$17,$25
47289		 srl   $17,$17,31        	 # Set Overflow
47290		 slt   $19,$10,$0        	 # Set Sign
47291		 sltiu $18,$10,1         	 # Set Zero
47292		 addiu $15,$15,-18
47293		 bgez  $15,3f
47294		 lhu   $24,0x00($23)    	 # Delay slot
47295		 j     MainExit
47296	3:
47297		 sll   $7,$24,2         	 # Delay slot
47298		 addu  $7,$7,$30
47299		 lw    $7,0x00($7)
47300		 jr    $7
47301		 nop                    	 # Delay slot
47302
47303OP0_b1fb:				#:
47304		 addiu $23,$23,2
47305
47306		 srl   $24,$24,7
47307		 andi  $24,$24,0x1C
47308		 addu  $24,$24,$21
47309		 lw    $9,0x20($24)
47310		 subu  $14,$23,$22       	 # Get PC
47311		 lhu   $7,0x00($23)
47312		 addiu $23,$23,2
47313		 seb   $6,$7
47314		 or    $25,$0,$7
47315		 srl   $7,$7,12
47316		 andi  $25,$25,0x0800
47317		 sll   $7,$7,2
47318		 addu  $7,$7,$21
47319		 bne   $25,$0,0f
47320		 lw    $25,0x00($7)      	 # Delay slot
47321		 seh   $25,$25
47322	0:
47323		 addu  $25,$14,$25
47324		 addu  $14,$25,$6
47325		 lw    $25,0xA0($21)
47326		 sw    $15,m68k_ICount
47327		 sw    $9,0x44($29)
47328		 sw    $24,0x40($29)
47329		 or    $4,$0,$14
47330		 jalr  $25
47331		 sw    $23,0x4C($21)    	 # Delay slot
47332		 lw    $24,0x40($29)
47333		 lw    $9,0x44($29)
47334		 lw    $15,m68k_ICount
47335		 subu  $10,$9,$2
47336		 sltu  $16,$9,$2       	 # Set Carry
47337		 xor   $17,$9,$2
47338		 xor   $25,$10,$9
47339		 and   $17,$17,$25
47340		 srl   $17,$17,31        	 # Set Overflow
47341		 slt   $19,$10,$0        	 # Set Sign
47342		 sltiu $18,$10,1         	 # Set Zero
47343		 addiu $15,$15,-20
47344		 bgez  $15,3f
47345		 lhu   $24,0x00($23)    	 # Delay slot
47346		 j     MainExit
47347	3:
47348		 sll   $7,$24,2         	 # Delay slot
47349		 addu  $7,$7,$30
47350		 lw    $7,0x00($7)
47351		 jr    $7
47352		 nop                    	 # Delay slot
47353
47354OP0_b1fc:				#:
47355		 addiu $23,$23,2
47356
47357		 srl   $24,$24,7
47358		 andi  $24,$24,0x1C
47359		 addu  $24,$24,$21
47360		 lw    $9,0x20($24)
47361		 lhu   $2,0x00($23)
47362		 lhu   $25,0x02($23)
47363		 sll   $2,$2,16
47364		 or    $2,$2,$25
47365		 addiu $23,$23,4
47366		 subu  $10,$9,$2
47367		 sltu  $16,$9,$2       	 # Set Carry
47368		 xor   $17,$9,$2
47369		 xor   $25,$10,$9
47370		 and   $17,$17,$25
47371		 srl   $17,$17,31        	 # Set Overflow
47372		 slt   $19,$10,$0        	 # Set Sign
47373		 sltiu $18,$10,1         	 # Set Zero
47374		 addiu $15,$15,-6
47375		 bgez  $15,3f
47376		 lhu   $24,0x00($23)    	 # Delay slot
47377		 j     MainExit
47378	3:
47379		 sll   $7,$24,2         	 # Delay slot
47380		 addu  $7,$7,$30
47381		 lw    $7,0x00($7)
47382		 jr    $7
47383		 nop                    	 # Delay slot
47384
47385OP0_d0c0:				#:
47386		 addiu $23,$23,2
47387
47388		 andi  $8,$24,0x0f
47389		 srl   $24,$24,7
47390		 andi  $24,$24,0x1C
47391		 addu  $24,$24,$21
47392		 lw    $9,0x20($24)
47393		 sll   $8,$8,2
47394		 addu  $8,$8,$21
47395		 lh    $2,0x00($8)
47396		 addu  $10,$9,$2
47397		 sw    $10,0x20($24)
47398		 addiu $15,$15,-4
47399		 bgez  $15,3f
47400		 lhu   $24,0x00($23)    	 # Delay slot
47401		 j     MainExit
47402	3:
47403		 sll   $7,$24,2         	 # Delay slot
47404		 addu  $7,$7,$30
47405		 lw    $7,0x00($7)
47406		 jr    $7
47407		 nop                    	 # Delay slot
47408
47409OP0_d0d0:				#:
47410		 addiu $23,$23,2
47411
47412		 andi  $8,$24,0x07
47413		 srl   $24,$24,7
47414		 andi  $24,$24,0x1C
47415		 addu  $24,$24,$21
47416		 lw    $9,0x20($24)
47417		 sll   $8,$8,2
47418		 addu  $8,$8,$21
47419		 lw    $14,0x20($8)
47420		 lw    $25,0x80($21)
47421		 sw    $15,m68k_ICount
47422		 sw    $9,0x44($29)
47423		 sw    $24,0x40($29)
47424		 or    $4,$0,$14
47425		 jalr  $25
47426		 sw    $23,0x4C($21)    	 # Delay slot
47427		 lw    $24,0x40($29)
47428		 lw    $9,0x44($29)
47429		 lw    $15,m68k_ICount
47430		 seh   $2,$2
47431		 addu  $10,$9,$2
47432		 sw    $10,0x20($24)
47433		 addiu $15,$15,-8
47434		 bgez  $15,3f
47435		 lhu   $24,0x00($23)    	 # Delay slot
47436		 j     MainExit
47437	3:
47438		 sll   $7,$24,2         	 # Delay slot
47439		 addu  $7,$7,$30
47440		 lw    $7,0x00($7)
47441		 jr    $7
47442		 nop                    	 # Delay slot
47443
47444OP0_d0d8:				#:
47445		 addiu $23,$23,2
47446
47447		 andi  $8,$24,0x07
47448		 srl   $24,$24,7
47449		 andi  $24,$24,0x1C
47450		 addu  $24,$24,$21
47451		 lw    $9,0x20($24)
47452		 sll   $8,$8,2
47453		 addu  $8,$8,$21
47454		 lw    $14,0x20($8)
47455		 addiu $25,$14,2
47456		 sw    $25,0x20($8)
47457		 lw    $25,0x80($21)
47458		 sw    $15,m68k_ICount
47459		 sw    $9,0x44($29)
47460		 sw    $24,0x40($29)
47461		 or    $4,$0,$14
47462		 jalr  $25
47463		 sw    $23,0x4C($21)    	 # Delay slot
47464		 lw    $24,0x40($29)
47465		 lw    $9,0x44($29)
47466		 lw    $15,m68k_ICount
47467		 seh   $2,$2
47468		 addu  $10,$9,$2
47469		 sw    $10,0x20($24)
47470		 addiu $15,$15,-8
47471		 bgez  $15,3f
47472		 lhu   $24,0x00($23)    	 # Delay slot
47473		 j     MainExit
47474	3:
47475		 sll   $7,$24,2         	 # Delay slot
47476		 addu  $7,$7,$30
47477		 lw    $7,0x00($7)
47478		 jr    $7
47479		 nop                    	 # Delay slot
47480
47481OP0_d0e0:				#:
47482		 addiu $23,$23,2
47483
47484		 andi  $8,$24,0x07
47485		 srl   $24,$24,7
47486		 andi  $24,$24,0x1C
47487		 addu  $24,$24,$21
47488		 lw    $9,0x20($24)
47489		 sll   $8,$8,2
47490		 addu  $8,$8,$21
47491		 lw    $14,0x20($8)
47492		 addiu $14,$14,-2
47493		 sw    $14,0x20($8)
47494		 lw    $25,0x80($21)
47495		 sw    $15,m68k_ICount
47496		 sw    $9,0x44($29)
47497		 sw    $24,0x40($29)
47498		 or    $4,$0,$14
47499		 jalr  $25
47500		 sw    $23,0x4C($21)    	 # Delay slot
47501		 lw    $24,0x40($29)
47502		 lw    $9,0x44($29)
47503		 lw    $15,m68k_ICount
47504		 seh   $2,$2
47505		 addu  $10,$9,$2
47506		 sw    $10,0x20($24)
47507		 addiu $15,$15,-10
47508		 bgez  $15,3f
47509		 lhu   $24,0x00($23)    	 # Delay slot
47510		 j     MainExit
47511	3:
47512		 sll   $7,$24,2         	 # Delay slot
47513		 addu  $7,$7,$30
47514		 lw    $7,0x00($7)
47515		 jr    $7
47516		 nop                    	 # Delay slot
47517
47518OP0_d0e8:				#:
47519		 addiu $23,$23,2
47520
47521		 andi  $8,$24,0x07
47522		 srl   $24,$24,7
47523		 andi  $24,$24,0x1C
47524		 addu  $24,$24,$21
47525		 lw    $9,0x20($24)
47526		 lh    $7,0x00($23)
47527		 sll   $8,$8,2
47528		 addu  $8,$8,$21
47529		 lw    $14,0x20($8)
47530		 addiu $23,$23,2
47531		 addu  $14,$14,$7
47532		 lw    $25,0x80($21)
47533		 sw    $15,m68k_ICount
47534		 sw    $9,0x44($29)
47535		 sw    $24,0x40($29)
47536		 or    $4,$0,$14
47537		 jalr  $25
47538		 sw    $23,0x4C($21)    	 # Delay slot
47539		 lw    $24,0x40($29)
47540		 lw    $9,0x44($29)
47541		 lw    $15,m68k_ICount
47542		 seh   $2,$2
47543		 addu  $10,$9,$2
47544		 sw    $10,0x20($24)
47545		 addiu $15,$15,-12
47546		 bgez  $15,3f
47547		 lhu   $24,0x00($23)    	 # Delay slot
47548		 j     MainExit
47549	3:
47550		 sll   $7,$24,2         	 # Delay slot
47551		 addu  $7,$7,$30
47552		 lw    $7,0x00($7)
47553		 jr    $7
47554		 nop                    	 # Delay slot
47555
47556OP0_d0f0:				#:
47557		 addiu $23,$23,2
47558
47559		 andi  $8,$24,0x07
47560		 srl   $24,$24,7
47561		 andi  $24,$24,0x1C
47562		 addu  $24,$24,$21
47563		 lw    $9,0x20($24)
47564		 sll   $8,$8,2
47565		 addu  $8,$8,$21
47566		 lw    $14,0x20($8)
47567		 lhu   $7,0x00($23)
47568		 addiu $23,$23,2
47569		 seb   $6,$7
47570		 or    $25,$0,$7
47571		 srl   $7,$7,12
47572		 andi  $25,$25,0x0800
47573		 sll   $7,$7,2
47574		 addu  $7,$7,$21
47575		 bne   $25,$0,0f
47576		 lw    $25,0x00($7)      	 # Delay slot
47577		 seh   $25,$25
47578	0:
47579		 addu  $25,$14,$25
47580		 addu  $14,$25,$6
47581		 lw    $25,0x80($21)
47582		 sw    $15,m68k_ICount
47583		 sw    $9,0x44($29)
47584		 sw    $24,0x40($29)
47585		 or    $4,$0,$14
47586		 jalr  $25
47587		 sw    $23,0x4C($21)    	 # Delay slot
47588		 lw    $24,0x40($29)
47589		 lw    $9,0x44($29)
47590		 lw    $15,m68k_ICount
47591		 seh   $2,$2
47592		 addu  $10,$9,$2
47593		 sw    $10,0x20($24)
47594		 addiu $15,$15,-14
47595		 bgez  $15,3f
47596		 lhu   $24,0x00($23)    	 # Delay slot
47597		 j     MainExit
47598	3:
47599		 sll   $7,$24,2         	 # Delay slot
47600		 addu  $7,$7,$30
47601		 lw    $7,0x00($7)
47602		 jr    $7
47603		 nop                    	 # Delay slot
47604
47605OP0_d0f8:				#:
47606		 addiu $23,$23,2
47607
47608		 srl   $24,$24,7
47609		 andi  $24,$24,0x1C
47610		 addu  $24,$24,$21
47611		 lw    $9,0x20($24)
47612		 lh    $14,0x00($23)
47613		 addiu $23,$23,2
47614		 lw    $25,0x80($21)
47615		 sw    $15,m68k_ICount
47616		 sw    $9,0x44($29)
47617		 sw    $24,0x40($29)
47618		 or    $4,$0,$14
47619		 jalr  $25
47620		 sw    $23,0x4C($21)    	 # Delay slot
47621		 lw    $24,0x40($29)
47622		 lw    $9,0x44($29)
47623		 lw    $15,m68k_ICount
47624		 seh   $2,$2
47625		 addu  $10,$9,$2
47626		 sw    $10,0x20($24)
47627		 addiu $15,$15,-12
47628		 bgez  $15,3f
47629		 lhu   $24,0x00($23)    	 # Delay slot
47630		 j     MainExit
47631	3:
47632		 sll   $7,$24,2         	 # Delay slot
47633		 addu  $7,$7,$30
47634		 lw    $7,0x00($7)
47635		 jr    $7
47636		 nop                    	 # Delay slot
47637
47638OP0_d0f9:				#:
47639		 addiu $23,$23,2
47640
47641		 srl   $24,$24,7
47642		 andi  $24,$24,0x1C
47643		 addu  $24,$24,$21
47644		 lw    $9,0x20($24)
47645		 lhu   $14,0x00($23)
47646		 lhu   $25,0x02($23)
47647		 sll   $14,$14,16
47648		 or    $14,$14,$25
47649		 addiu $23,$23,4
47650		 lw    $25,0x80($21)
47651		 sw    $15,m68k_ICount
47652		 sw    $9,0x44($29)
47653		 sw    $24,0x40($29)
47654		 or    $4,$0,$14
47655		 jalr  $25
47656		 sw    $23,0x4C($21)    	 # Delay slot
47657		 lw    $24,0x40($29)
47658		 lw    $9,0x44($29)
47659		 lw    $15,m68k_ICount
47660		 seh   $2,$2
47661		 addu  $10,$9,$2
47662		 sw    $10,0x20($24)
47663		 addiu $15,$15,-16
47664		 bgez  $15,3f
47665		 lhu   $24,0x00($23)    	 # Delay slot
47666		 j     MainExit
47667	3:
47668		 sll   $7,$24,2         	 # Delay slot
47669		 addu  $7,$7,$30
47670		 lw    $7,0x00($7)
47671		 jr    $7
47672		 nop                    	 # Delay slot
47673
47674OP0_d0fa:				#:
47675		 addiu $23,$23,2
47676
47677		 srl   $24,$24,7
47678		 andi  $24,$24,0x1C
47679		 addu  $24,$24,$21
47680		 lw    $9,0x20($24)
47681		 lh    $7,0x00($23)
47682		 subu  $25,$23,$22
47683		 addu  $14,$25,$7       	 # Add Offset to PC
47684		 addiu $23,$23,2
47685		 lw    $25,0x9C($21)
47686		 sw    $15,m68k_ICount
47687		 sw    $9,0x44($29)
47688		 sw    $24,0x40($29)
47689		 or    $4,$0,$14
47690		 jalr  $25
47691		 sw    $23,0x4C($21)    	 # Delay slot
47692		 lw    $24,0x40($29)
47693		 lw    $9,0x44($29)
47694		 lw    $15,m68k_ICount
47695		 seh   $2,$2
47696		 addu  $10,$9,$2
47697		 sw    $10,0x20($24)
47698		 addiu $15,$15,-12
47699		 bgez  $15,3f
47700		 lhu   $24,0x00($23)    	 # Delay slot
47701		 j     MainExit
47702	3:
47703		 sll   $7,$24,2         	 # Delay slot
47704		 addu  $7,$7,$30
47705		 lw    $7,0x00($7)
47706		 jr    $7
47707		 nop                    	 # Delay slot
47708
47709OP0_d0fb:				#:
47710		 addiu $23,$23,2
47711
47712		 srl   $24,$24,7
47713		 andi  $24,$24,0x1C
47714		 addu  $24,$24,$21
47715		 lw    $9,0x20($24)
47716		 subu  $14,$23,$22       	 # Get PC
47717		 lhu   $7,0x00($23)
47718		 addiu $23,$23,2
47719		 seb   $6,$7
47720		 or    $25,$0,$7
47721		 srl   $7,$7,12
47722		 andi  $25,$25,0x0800
47723		 sll   $7,$7,2
47724		 addu  $7,$7,$21
47725		 bne   $25,$0,0f
47726		 lw    $25,0x00($7)      	 # Delay slot
47727		 seh   $25,$25
47728	0:
47729		 addu  $25,$14,$25
47730		 addu  $14,$25,$6
47731		 lw    $25,0x9C($21)
47732		 sw    $15,m68k_ICount
47733		 sw    $9,0x44($29)
47734		 sw    $24,0x40($29)
47735		 or    $4,$0,$14
47736		 jalr  $25
47737		 sw    $23,0x4C($21)    	 # Delay slot
47738		 lw    $24,0x40($29)
47739		 lw    $9,0x44($29)
47740		 lw    $15,m68k_ICount
47741		 seh   $2,$2
47742		 addu  $10,$9,$2
47743		 sw    $10,0x20($24)
47744		 addiu $15,$15,-14
47745		 bgez  $15,3f
47746		 lhu   $24,0x00($23)    	 # Delay slot
47747		 j     MainExit
47748	3:
47749		 sll   $7,$24,2         	 # Delay slot
47750		 addu  $7,$7,$30
47751		 lw    $7,0x00($7)
47752		 jr    $7
47753		 nop                    	 # Delay slot
47754
47755OP0_d0fc:				#:
47756		 addiu $23,$23,2
47757
47758		 srl   $24,$24,7
47759		 andi  $24,$24,0x1C
47760		 addu  $24,$24,$21
47761		 lw    $9,0x20($24)
47762		 lh    $2,0x00($23)
47763		 addiu $23,$23,2
47764		 addu  $10,$9,$2
47765		 sw    $10,0x20($24)
47766		 addiu $15,$15,-4
47767		 bgez  $15,3f
47768		 lhu   $24,0x00($23)    	 # Delay slot
47769		 j     MainExit
47770	3:
47771		 sll   $7,$24,2         	 # Delay slot
47772		 addu  $7,$7,$30
47773		 lw    $7,0x00($7)
47774		 jr    $7
47775		 nop                    	 # Delay slot
47776
47777OP0_d1c0:				#:
47778		 addiu $23,$23,2
47779
47780		 andi  $8,$24,0x0f
47781		 srl   $24,$24,7
47782		 andi  $24,$24,0x1C
47783		 addu  $24,$24,$21
47784		 lw    $9,0x20($24)
47785		 sll   $8,$8,2
47786		 addu  $8,$8,$21
47787		 lw    $2,0x00($8)
47788		 addu  $10,$9,$2
47789		 sw    $10,0x20($24)
47790		 addiu $15,$15,-8
47791		 bgez  $15,3f
47792		 lhu   $24,0x00($23)    	 # Delay slot
47793		 j     MainExit
47794	3:
47795		 sll   $7,$24,2         	 # Delay slot
47796		 addu  $7,$7,$30
47797		 lw    $7,0x00($7)
47798		 jr    $7
47799		 nop                    	 # Delay slot
47800
47801OP0_d1d0:				#:
47802		 addiu $23,$23,2
47803
47804		 andi  $8,$24,0x07
47805		 srl   $24,$24,7
47806		 andi  $24,$24,0x1C
47807		 addu  $24,$24,$21
47808		 lw    $9,0x20($24)
47809		 sll   $8,$8,2
47810		 addu  $8,$8,$21
47811		 lw    $14,0x20($8)
47812		 lw    $25,0x84($21)
47813		 sw    $15,m68k_ICount
47814		 sw    $9,0x44($29)
47815		 sw    $24,0x40($29)
47816		 or    $4,$0,$14
47817		 jalr  $25
47818		 sw    $23,0x4C($21)    	 # Delay slot
47819		 lw    $24,0x40($29)
47820		 lw    $9,0x44($29)
47821		 lw    $15,m68k_ICount
47822		 addu  $10,$9,$2
47823		 sw    $10,0x20($24)
47824		 addiu $15,$15,-14
47825		 bgez  $15,3f
47826		 lhu   $24,0x00($23)    	 # Delay slot
47827		 j     MainExit
47828	3:
47829		 sll   $7,$24,2         	 # Delay slot
47830		 addu  $7,$7,$30
47831		 lw    $7,0x00($7)
47832		 jr    $7
47833		 nop                    	 # Delay slot
47834
47835OP0_d1d8:				#:
47836		 addiu $23,$23,2
47837
47838		 andi  $8,$24,0x07
47839		 srl   $24,$24,7
47840		 andi  $24,$24,0x1C
47841		 addu  $24,$24,$21
47842		 lw    $9,0x20($24)
47843		 sll   $8,$8,2
47844		 addu  $8,$8,$21
47845		 lw    $14,0x20($8)
47846		 addiu $25,$14,4
47847		 sw    $25,0x20($8)
47848		 lw    $25,0x84($21)
47849		 sw    $15,m68k_ICount
47850		 sw    $9,0x44($29)
47851		 sw    $24,0x40($29)
47852		 or    $4,$0,$14
47853		 jalr  $25
47854		 sw    $23,0x4C($21)    	 # Delay slot
47855		 lw    $24,0x40($29)
47856		 lw    $9,0x44($29)
47857		 lw    $15,m68k_ICount
47858		 addu  $10,$9,$2
47859		 sw    $10,0x20($24)
47860		 addiu $15,$15,-14
47861		 bgez  $15,3f
47862		 lhu   $24,0x00($23)    	 # Delay slot
47863		 j     MainExit
47864	3:
47865		 sll   $7,$24,2         	 # Delay slot
47866		 addu  $7,$7,$30
47867		 lw    $7,0x00($7)
47868		 jr    $7
47869		 nop                    	 # Delay slot
47870
47871OP0_d1e0:				#:
47872		 addiu $23,$23,2
47873
47874		 andi  $8,$24,0x07
47875		 srl   $24,$24,7
47876		 andi  $24,$24,0x1C
47877		 addu  $24,$24,$21
47878		 lw    $9,0x20($24)
47879		 sll   $8,$8,2
47880		 addu  $8,$8,$21
47881		 lw    $14,0x20($8)
47882		 addiu $14,$14,-4
47883		 sw    $14,0x20($8)
47884		 lw    $25,0x84($21)
47885		 sw    $15,m68k_ICount
47886		 sw    $9,0x44($29)
47887		 sw    $24,0x40($29)
47888		 or    $4,$0,$14
47889		 jalr  $25
47890		 sw    $23,0x4C($21)    	 # Delay slot
47891		 lw    $24,0x40($29)
47892		 lw    $9,0x44($29)
47893		 lw    $15,m68k_ICount
47894		 addu  $10,$9,$2
47895		 sw    $10,0x20($24)
47896		 addiu $15,$15,-16
47897		 bgez  $15,3f
47898		 lhu   $24,0x00($23)    	 # Delay slot
47899		 j     MainExit
47900	3:
47901		 sll   $7,$24,2         	 # Delay slot
47902		 addu  $7,$7,$30
47903		 lw    $7,0x00($7)
47904		 jr    $7
47905		 nop                    	 # Delay slot
47906
47907OP0_d1e8:				#:
47908		 addiu $23,$23,2
47909
47910		 andi  $8,$24,0x07
47911		 srl   $24,$24,7
47912		 andi  $24,$24,0x1C
47913		 addu  $24,$24,$21
47914		 lw    $9,0x20($24)
47915		 lh    $7,0x00($23)
47916		 sll   $8,$8,2
47917		 addu  $8,$8,$21
47918		 lw    $14,0x20($8)
47919		 addiu $23,$23,2
47920		 addu  $14,$14,$7
47921		 lw    $25,0x84($21)
47922		 sw    $15,m68k_ICount
47923		 sw    $9,0x44($29)
47924		 sw    $24,0x40($29)
47925		 or    $4,$0,$14
47926		 jalr  $25
47927		 sw    $23,0x4C($21)    	 # Delay slot
47928		 lw    $24,0x40($29)
47929		 lw    $9,0x44($29)
47930		 lw    $15,m68k_ICount
47931		 addu  $10,$9,$2
47932		 sw    $10,0x20($24)
47933		 addiu $15,$15,-18
47934		 bgez  $15,3f
47935		 lhu   $24,0x00($23)    	 # Delay slot
47936		 j     MainExit
47937	3:
47938		 sll   $7,$24,2         	 # Delay slot
47939		 addu  $7,$7,$30
47940		 lw    $7,0x00($7)
47941		 jr    $7
47942		 nop                    	 # Delay slot
47943
47944OP0_d1f0:				#:
47945		 addiu $23,$23,2
47946
47947		 andi  $8,$24,0x07
47948		 srl   $24,$24,7
47949		 andi  $24,$24,0x1C
47950		 addu  $24,$24,$21
47951		 lw    $9,0x20($24)
47952		 sll   $8,$8,2
47953		 addu  $8,$8,$21
47954		 lw    $14,0x20($8)
47955		 lhu   $7,0x00($23)
47956		 addiu $23,$23,2
47957		 seb   $6,$7
47958		 or    $25,$0,$7
47959		 srl   $7,$7,12
47960		 andi  $25,$25,0x0800
47961		 sll   $7,$7,2
47962		 addu  $7,$7,$21
47963		 bne   $25,$0,0f
47964		 lw    $25,0x00($7)      	 # Delay slot
47965		 seh   $25,$25
47966	0:
47967		 addu  $25,$14,$25
47968		 addu  $14,$25,$6
47969		 lw    $25,0x84($21)
47970		 sw    $15,m68k_ICount
47971		 sw    $9,0x44($29)
47972		 sw    $24,0x40($29)
47973		 or    $4,$0,$14
47974		 jalr  $25
47975		 sw    $23,0x4C($21)    	 # Delay slot
47976		 lw    $24,0x40($29)
47977		 lw    $9,0x44($29)
47978		 lw    $15,m68k_ICount
47979		 addu  $10,$9,$2
47980		 sw    $10,0x20($24)
47981		 addiu $15,$15,-20
47982		 bgez  $15,3f
47983		 lhu   $24,0x00($23)    	 # Delay slot
47984		 j     MainExit
47985	3:
47986		 sll   $7,$24,2         	 # Delay slot
47987		 addu  $7,$7,$30
47988		 lw    $7,0x00($7)
47989		 jr    $7
47990		 nop                    	 # Delay slot
47991
47992OP0_d1f8:				#:
47993		 addiu $23,$23,2
47994
47995		 srl   $24,$24,7
47996		 andi  $24,$24,0x1C
47997		 addu  $24,$24,$21
47998		 lw    $9,0x20($24)
47999		 lh    $14,0x00($23)
48000		 addiu $23,$23,2
48001		 lw    $25,0x84($21)
48002		 sw    $15,m68k_ICount
48003		 sw    $9,0x44($29)
48004		 sw    $24,0x40($29)
48005		 or    $4,$0,$14
48006		 jalr  $25
48007		 sw    $23,0x4C($21)    	 # Delay slot
48008		 lw    $24,0x40($29)
48009		 lw    $9,0x44($29)
48010		 lw    $15,m68k_ICount
48011		 addu  $10,$9,$2
48012		 sw    $10,0x20($24)
48013		 addiu $15,$15,-18
48014		 bgez  $15,3f
48015		 lhu   $24,0x00($23)    	 # Delay slot
48016		 j     MainExit
48017	3:
48018		 sll   $7,$24,2         	 # Delay slot
48019		 addu  $7,$7,$30
48020		 lw    $7,0x00($7)
48021		 jr    $7
48022		 nop                    	 # Delay slot
48023
48024OP0_d1f9:				#:
48025		 addiu $23,$23,2
48026
48027		 srl   $24,$24,7
48028		 andi  $24,$24,0x1C
48029		 addu  $24,$24,$21
48030		 lw    $9,0x20($24)
48031		 lhu   $14,0x00($23)
48032		 lhu   $25,0x02($23)
48033		 sll   $14,$14,16
48034		 or    $14,$14,$25
48035		 addiu $23,$23,4
48036		 lw    $25,0x84($21)
48037		 sw    $15,m68k_ICount
48038		 sw    $9,0x44($29)
48039		 sw    $24,0x40($29)
48040		 or    $4,$0,$14
48041		 jalr  $25
48042		 sw    $23,0x4C($21)    	 # Delay slot
48043		 lw    $24,0x40($29)
48044		 lw    $9,0x44($29)
48045		 lw    $15,m68k_ICount
48046		 addu  $10,$9,$2
48047		 sw    $10,0x20($24)
48048		 addiu $15,$15,-22
48049		 bgez  $15,3f
48050		 lhu   $24,0x00($23)    	 # Delay slot
48051		 j     MainExit
48052	3:
48053		 sll   $7,$24,2         	 # Delay slot
48054		 addu  $7,$7,$30
48055		 lw    $7,0x00($7)
48056		 jr    $7
48057		 nop                    	 # Delay slot
48058
48059OP0_d1fa:				#:
48060		 addiu $23,$23,2
48061
48062		 srl   $24,$24,7
48063		 andi  $24,$24,0x1C
48064		 addu  $24,$24,$21
48065		 lw    $9,0x20($24)
48066		 lh    $7,0x00($23)
48067		 subu  $25,$23,$22
48068		 addu  $14,$25,$7       	 # Add Offset to PC
48069		 addiu $23,$23,2
48070		 lw    $25,0xA0($21)
48071		 sw    $15,m68k_ICount
48072		 sw    $9,0x44($29)
48073		 sw    $24,0x40($29)
48074		 or    $4,$0,$14
48075		 jalr  $25
48076		 sw    $23,0x4C($21)    	 # Delay slot
48077		 lw    $24,0x40($29)
48078		 lw    $9,0x44($29)
48079		 lw    $15,m68k_ICount
48080		 addu  $10,$9,$2
48081		 sw    $10,0x20($24)
48082		 addiu $15,$15,-18
48083		 bgez  $15,3f
48084		 lhu   $24,0x00($23)    	 # Delay slot
48085		 j     MainExit
48086	3:
48087		 sll   $7,$24,2         	 # Delay slot
48088		 addu  $7,$7,$30
48089		 lw    $7,0x00($7)
48090		 jr    $7
48091		 nop                    	 # Delay slot
48092
48093OP0_d1fb:				#:
48094		 addiu $23,$23,2
48095
48096		 srl   $24,$24,7
48097		 andi  $24,$24,0x1C
48098		 addu  $24,$24,$21
48099		 lw    $9,0x20($24)
48100		 subu  $14,$23,$22       	 # Get PC
48101		 lhu   $7,0x00($23)
48102		 addiu $23,$23,2
48103		 seb   $6,$7
48104		 or    $25,$0,$7
48105		 srl   $7,$7,12
48106		 andi  $25,$25,0x0800
48107		 sll   $7,$7,2
48108		 addu  $7,$7,$21
48109		 bne   $25,$0,0f
48110		 lw    $25,0x00($7)      	 # Delay slot
48111		 seh   $25,$25
48112	0:
48113		 addu  $25,$14,$25
48114		 addu  $14,$25,$6
48115		 lw    $25,0xA0($21)
48116		 sw    $15,m68k_ICount
48117		 sw    $9,0x44($29)
48118		 sw    $24,0x40($29)
48119		 or    $4,$0,$14
48120		 jalr  $25
48121		 sw    $23,0x4C($21)    	 # Delay slot
48122		 lw    $24,0x40($29)
48123		 lw    $9,0x44($29)
48124		 lw    $15,m68k_ICount
48125		 addu  $10,$9,$2
48126		 sw    $10,0x20($24)
48127		 addiu $15,$15,-20
48128		 bgez  $15,3f
48129		 lhu   $24,0x00($23)    	 # Delay slot
48130		 j     MainExit
48131	3:
48132		 sll   $7,$24,2         	 # Delay slot
48133		 addu  $7,$7,$30
48134		 lw    $7,0x00($7)
48135		 jr    $7
48136		 nop                    	 # Delay slot
48137
48138OP0_d1fc:				#:
48139		 addiu $23,$23,2
48140
48141		 srl   $24,$24,7
48142		 andi  $24,$24,0x1C
48143		 addu  $24,$24,$21
48144		 lw    $9,0x20($24)
48145		 lhu   $2,0x00($23)
48146		 lhu   $25,0x02($23)
48147		 sll   $2,$2,16
48148		 or    $2,$2,$25
48149		 addiu $23,$23,4
48150		 addu  $10,$9,$2
48151		 sw    $10,0x20($24)
48152		 addiu $15,$15,-6
48153		 bgez  $15,3f
48154		 lhu   $24,0x00($23)    	 # Delay slot
48155		 j     MainExit
48156	3:
48157		 sll   $7,$24,2         	 # Delay slot
48158		 addu  $7,$7,$30
48159		 lw    $7,0x00($7)
48160		 jr    $7
48161		 nop                    	 # Delay slot
48162
48163OP0_b100:				#:
48164		 addiu $23,$23,2
48165
48166		 andi  $8,$24,0x07
48167		 srl   $24,$24,7
48168		 andi  $24,$24,0x1C
48169		 addu  $24,$24,$21
48170		 lb    $9,0x00($24)
48171		 sll   $8,$8,2
48172		 addu  $8,$8,$21
48173		 lb    $10,0x00($8)
48174		 xor   $2,$10,$9
48175		 and   $16,$0,$0        	 # Clear Carry
48176		 and   $17,$0,$0        	 # Clear Overflow
48177		 slt   $19,$2,$0        	 # Set Sign
48178		 sltiu $18,$2,1         	 # Set Zero
48179		 sb    $2,0x00($8)
48180		 addiu $15,$15,-8
48181		 bgez  $15,3f
48182		 lhu   $24,0x00($23)    	 # Delay slot
48183		 j     MainExit
48184	3:
48185		 sll   $7,$24,2         	 # Delay slot
48186		 addu  $7,$7,$30
48187		 lw    $7,0x00($7)
48188		 jr    $7
48189		 nop                    	 # Delay slot
48190
48191OP0_b110:				#:
48192		 addiu $23,$23,2
48193
48194		 andi  $8,$24,0x07
48195		 srl   $24,$24,7
48196		 andi  $24,$24,0x1C
48197		 addu  $24,$24,$21
48198		 lb    $9,0x00($24)
48199		 sll   $8,$8,2
48200		 addu  $8,$8,$21
48201		 lw    $14,0x20($8)
48202		 lw    $25,0x7C($21)
48203		 sw    $15,m68k_ICount
48204		 sw    $9,0x44($29)
48205		 sw    $14,0x40($29)
48206		 sw    $24,0x3C($29)
48207		 or    $4,$0,$14
48208		 jalr  $25
48209		 sw    $23,0x4C($21)    	 # Delay slot
48210		 lw    $24,0x3C($29)
48211		 lw    $14,0x40($29)
48212		 lw    $9,0x44($29)
48213		 lw    $15,m68k_ICount
48214		 seb   $10,$2
48215		 xor   $2,$10,$9
48216		 and   $16,$0,$0        	 # Clear Carry
48217		 and   $17,$0,$0        	 # Clear Overflow
48218		 slt   $19,$2,$0        	 # Set Sign
48219		 sltiu $18,$2,1         	 # Set Zero
48220		 lw    $25,0x88($21)
48221		 sw    $15,m68k_ICount
48222		 sw    $9,0x44($29)
48223		 sw    $14,0x40($29)
48224		 sw    $24,0x3C($29)
48225		 or    $5,$0,$2
48226		 or    $4,$0,$14
48227		 jalr  $25
48228		 sw    $23,0x4C($21)    	 # Delay slot
48229		 lw    $24,0x3C($29)
48230		 lw    $14,0x40($29)
48231		 lw    $9,0x44($29)
48232		 lw    $15,m68k_ICount
48233		 addiu $15,$15,-12
48234		 bgez  $15,3f
48235		 lhu   $24,0x00($23)    	 # Delay slot
48236		 j     MainExit
48237	3:
48238		 sll   $7,$24,2         	 # Delay slot
48239		 addu  $7,$7,$30
48240		 lw    $7,0x00($7)
48241		 jr    $7
48242		 nop                    	 # Delay slot
48243
48244OP0_b118:				#:
48245		 addiu $23,$23,2
48246
48247		 andi  $8,$24,0x07
48248		 srl   $24,$24,7
48249		 andi  $24,$24,0x1C
48250		 addu  $24,$24,$21
48251		 lb    $9,0x00($24)
48252		 sll   $8,$8,2
48253		 addu  $8,$8,$21
48254		 lw    $14,0x20($8)
48255		 addiu $25,$14,1
48256		 sw    $25,0x20($8)
48257		 lw    $25,0x7C($21)
48258		 sw    $15,m68k_ICount
48259		 sw    $9,0x44($29)
48260		 sw    $14,0x40($29)
48261		 sw    $24,0x3C($29)
48262		 or    $4,$0,$14
48263		 jalr  $25
48264		 sw    $23,0x4C($21)    	 # Delay slot
48265		 lw    $24,0x3C($29)
48266		 lw    $14,0x40($29)
48267		 lw    $9,0x44($29)
48268		 lw    $15,m68k_ICount
48269		 seb   $10,$2
48270		 xor   $2,$10,$9
48271		 and   $16,$0,$0        	 # Clear Carry
48272		 and   $17,$0,$0        	 # Clear Overflow
48273		 slt   $19,$2,$0        	 # Set Sign
48274		 sltiu $18,$2,1         	 # Set Zero
48275		 lw    $25,0x88($21)
48276		 sw    $15,m68k_ICount
48277		 sw    $9,0x44($29)
48278		 sw    $14,0x40($29)
48279		 sw    $24,0x3C($29)
48280		 or    $5,$0,$2
48281		 or    $4,$0,$14
48282		 jalr  $25
48283		 sw    $23,0x4C($21)    	 # Delay slot
48284		 lw    $24,0x3C($29)
48285		 lw    $14,0x40($29)
48286		 lw    $9,0x44($29)
48287		 lw    $15,m68k_ICount
48288		 addiu $15,$15,-12
48289		 bgez  $15,3f
48290		 lhu   $24,0x00($23)    	 # Delay slot
48291		 j     MainExit
48292	3:
48293		 sll   $7,$24,2         	 # Delay slot
48294		 addu  $7,$7,$30
48295		 lw    $7,0x00($7)
48296		 jr    $7
48297		 nop                    	 # Delay slot
48298
48299OP0_b11f:				#:
48300		 addiu $23,$23,2
48301
48302		 srl   $24,$24,7
48303		 andi  $24,$24,0x1C
48304		 addu  $24,$24,$21
48305		 lb    $9,0x00($24)
48306		 lw    $14,0x3C($21)    	 # Get A7
48307		 addiu $25,$14,2
48308		 sw    $25,0x3C($21)
48309		 lw    $25,0x7C($21)
48310		 sw    $15,m68k_ICount
48311		 sw    $9,0x44($29)
48312		 sw    $14,0x40($29)
48313		 sw    $24,0x3C($29)
48314		 or    $4,$0,$14
48315		 jalr  $25
48316		 sw    $23,0x4C($21)    	 # Delay slot
48317		 lw    $24,0x3C($29)
48318		 lw    $14,0x40($29)
48319		 lw    $9,0x44($29)
48320		 lw    $15,m68k_ICount
48321		 seb   $10,$2
48322		 xor   $2,$10,$9
48323		 and   $16,$0,$0        	 # Clear Carry
48324		 and   $17,$0,$0        	 # Clear Overflow
48325		 slt   $19,$2,$0        	 # Set Sign
48326		 sltiu $18,$2,1         	 # Set Zero
48327		 lw    $25,0x88($21)
48328		 sw    $15,m68k_ICount
48329		 sw    $9,0x44($29)
48330		 sw    $14,0x40($29)
48331		 sw    $24,0x3C($29)
48332		 or    $5,$0,$2
48333		 or    $4,$0,$14
48334		 jalr  $25
48335		 sw    $23,0x4C($21)    	 # Delay slot
48336		 lw    $24,0x3C($29)
48337		 lw    $14,0x40($29)
48338		 lw    $9,0x44($29)
48339		 lw    $15,m68k_ICount
48340		 addiu $15,$15,-12
48341		 bgez  $15,3f
48342		 lhu   $24,0x00($23)    	 # Delay slot
48343		 j     MainExit
48344	3:
48345		 sll   $7,$24,2         	 # Delay slot
48346		 addu  $7,$7,$30
48347		 lw    $7,0x00($7)
48348		 jr    $7
48349		 nop                    	 # Delay slot
48350
48351OP0_b120:				#:
48352		 addiu $23,$23,2
48353
48354		 andi  $8,$24,0x07
48355		 srl   $24,$24,7
48356		 andi  $24,$24,0x1C
48357		 addu  $24,$24,$21
48358		 lb    $9,0x00($24)
48359		 sll   $8,$8,2
48360		 addu  $8,$8,$21
48361		 lw    $14,0x20($8)
48362		 addiu $14,$14,-1
48363		 sw    $14,0x20($8)
48364		 lw    $25,0x7C($21)
48365		 sw    $15,m68k_ICount
48366		 sw    $9,0x44($29)
48367		 sw    $14,0x40($29)
48368		 sw    $24,0x3C($29)
48369		 or    $4,$0,$14
48370		 jalr  $25
48371		 sw    $23,0x4C($21)    	 # Delay slot
48372		 lw    $24,0x3C($29)
48373		 lw    $14,0x40($29)
48374		 lw    $9,0x44($29)
48375		 lw    $15,m68k_ICount
48376		 seb   $10,$2
48377		 xor   $2,$10,$9
48378		 and   $16,$0,$0        	 # Clear Carry
48379		 and   $17,$0,$0        	 # Clear Overflow
48380		 slt   $19,$2,$0        	 # Set Sign
48381		 sltiu $18,$2,1         	 # Set Zero
48382		 lw    $25,0x88($21)
48383		 sw    $15,m68k_ICount
48384		 sw    $9,0x44($29)
48385		 sw    $14,0x40($29)
48386		 sw    $24,0x3C($29)
48387		 or    $5,$0,$2
48388		 or    $4,$0,$14
48389		 jalr  $25
48390		 sw    $23,0x4C($21)    	 # Delay slot
48391		 lw    $24,0x3C($29)
48392		 lw    $14,0x40($29)
48393		 lw    $9,0x44($29)
48394		 lw    $15,m68k_ICount
48395		 addiu $15,$15,-14
48396		 bgez  $15,3f
48397		 lhu   $24,0x00($23)    	 # Delay slot
48398		 j     MainExit
48399	3:
48400		 sll   $7,$24,2         	 # Delay slot
48401		 addu  $7,$7,$30
48402		 lw    $7,0x00($7)
48403		 jr    $7
48404		 nop                    	 # Delay slot
48405
48406OP0_b127:				#:
48407		 addiu $23,$23,2
48408
48409		 srl   $24,$24,7
48410		 andi  $24,$24,0x1C
48411		 addu  $24,$24,$21
48412		 lb    $9,0x00($24)
48413		 lw    $14,0x3C($21)    	 # Get A7
48414		 addiu $14,$14,-2
48415		 sw    $14,0x3C($21)
48416		 lw    $25,0x7C($21)
48417		 sw    $15,m68k_ICount
48418		 sw    $9,0x44($29)
48419		 sw    $14,0x40($29)
48420		 sw    $24,0x3C($29)
48421		 or    $4,$0,$14
48422		 jalr  $25
48423		 sw    $23,0x4C($21)    	 # Delay slot
48424		 lw    $24,0x3C($29)
48425		 lw    $14,0x40($29)
48426		 lw    $9,0x44($29)
48427		 lw    $15,m68k_ICount
48428		 seb   $10,$2
48429		 xor   $2,$10,$9
48430		 and   $16,$0,$0        	 # Clear Carry
48431		 and   $17,$0,$0        	 # Clear Overflow
48432		 slt   $19,$2,$0        	 # Set Sign
48433		 sltiu $18,$2,1         	 # Set Zero
48434		 lw    $25,0x88($21)
48435		 sw    $15,m68k_ICount
48436		 sw    $9,0x44($29)
48437		 sw    $14,0x40($29)
48438		 sw    $24,0x3C($29)
48439		 or    $5,$0,$2
48440		 or    $4,$0,$14
48441		 jalr  $25
48442		 sw    $23,0x4C($21)    	 # Delay slot
48443		 lw    $24,0x3C($29)
48444		 lw    $14,0x40($29)
48445		 lw    $9,0x44($29)
48446		 lw    $15,m68k_ICount
48447		 addiu $15,$15,-14
48448		 bgez  $15,3f
48449		 lhu   $24,0x00($23)    	 # Delay slot
48450		 j     MainExit
48451	3:
48452		 sll   $7,$24,2         	 # Delay slot
48453		 addu  $7,$7,$30
48454		 lw    $7,0x00($7)
48455		 jr    $7
48456		 nop                    	 # Delay slot
48457
48458OP0_b128:				#:
48459		 addiu $23,$23,2
48460
48461		 andi  $8,$24,0x07
48462		 srl   $24,$24,7
48463		 andi  $24,$24,0x1C
48464		 addu  $24,$24,$21
48465		 lb    $9,0x00($24)
48466		 lh    $7,0x00($23)
48467		 sll   $8,$8,2
48468		 addu  $8,$8,$21
48469		 lw    $14,0x20($8)
48470		 addiu $23,$23,2
48471		 addu  $14,$14,$7
48472		 lw    $25,0x7C($21)
48473		 sw    $15,m68k_ICount
48474		 sw    $9,0x44($29)
48475		 sw    $14,0x40($29)
48476		 sw    $24,0x3C($29)
48477		 or    $4,$0,$14
48478		 jalr  $25
48479		 sw    $23,0x4C($21)    	 # Delay slot
48480		 lw    $24,0x3C($29)
48481		 lw    $14,0x40($29)
48482		 lw    $9,0x44($29)
48483		 lw    $15,m68k_ICount
48484		 seb   $10,$2
48485		 xor   $2,$10,$9
48486		 and   $16,$0,$0        	 # Clear Carry
48487		 and   $17,$0,$0        	 # Clear Overflow
48488		 slt   $19,$2,$0        	 # Set Sign
48489		 sltiu $18,$2,1         	 # Set Zero
48490		 lw    $25,0x88($21)
48491		 sw    $15,m68k_ICount
48492		 sw    $9,0x44($29)
48493		 sw    $14,0x40($29)
48494		 sw    $24,0x3C($29)
48495		 or    $5,$0,$2
48496		 or    $4,$0,$14
48497		 jalr  $25
48498		 sw    $23,0x4C($21)    	 # Delay slot
48499		 lw    $24,0x3C($29)
48500		 lw    $14,0x40($29)
48501		 lw    $9,0x44($29)
48502		 lw    $15,m68k_ICount
48503		 addiu $15,$15,-16
48504		 bgez  $15,3f
48505		 lhu   $24,0x00($23)    	 # Delay slot
48506		 j     MainExit
48507	3:
48508		 sll   $7,$24,2         	 # Delay slot
48509		 addu  $7,$7,$30
48510		 lw    $7,0x00($7)
48511		 jr    $7
48512		 nop                    	 # Delay slot
48513
48514OP0_b130:				#:
48515		 addiu $23,$23,2
48516
48517		 andi  $8,$24,0x07
48518		 srl   $24,$24,7
48519		 andi  $24,$24,0x1C
48520		 addu  $24,$24,$21
48521		 lb    $9,0x00($24)
48522		 sll   $8,$8,2
48523		 addu  $8,$8,$21
48524		 lw    $14,0x20($8)
48525		 lhu   $7,0x00($23)
48526		 addiu $23,$23,2
48527		 seb   $6,$7
48528		 or    $25,$0,$7
48529		 srl   $7,$7,12
48530		 andi  $25,$25,0x0800
48531		 sll   $7,$7,2
48532		 addu  $7,$7,$21
48533		 bne   $25,$0,0f
48534		 lw    $25,0x00($7)      	 # Delay slot
48535		 seh   $25,$25
48536	0:
48537		 addu  $25,$14,$25
48538		 addu  $14,$25,$6
48539		 lw    $25,0x7C($21)
48540		 sw    $15,m68k_ICount
48541		 sw    $9,0x44($29)
48542		 sw    $14,0x40($29)
48543		 sw    $24,0x3C($29)
48544		 or    $4,$0,$14
48545		 jalr  $25
48546		 sw    $23,0x4C($21)    	 # Delay slot
48547		 lw    $24,0x3C($29)
48548		 lw    $14,0x40($29)
48549		 lw    $9,0x44($29)
48550		 lw    $15,m68k_ICount
48551		 seb   $10,$2
48552		 xor   $2,$10,$9
48553		 and   $16,$0,$0        	 # Clear Carry
48554		 and   $17,$0,$0        	 # Clear Overflow
48555		 slt   $19,$2,$0        	 # Set Sign
48556		 sltiu $18,$2,1         	 # Set Zero
48557		 lw    $25,0x88($21)
48558		 sw    $15,m68k_ICount
48559		 sw    $9,0x44($29)
48560		 sw    $14,0x40($29)
48561		 sw    $24,0x3C($29)
48562		 or    $5,$0,$2
48563		 or    $4,$0,$14
48564		 jalr  $25
48565		 sw    $23,0x4C($21)    	 # Delay slot
48566		 lw    $24,0x3C($29)
48567		 lw    $14,0x40($29)
48568		 lw    $9,0x44($29)
48569		 lw    $15,m68k_ICount
48570		 addiu $15,$15,-18
48571		 bgez  $15,3f
48572		 lhu   $24,0x00($23)    	 # Delay slot
48573		 j     MainExit
48574	3:
48575		 sll   $7,$24,2         	 # Delay slot
48576		 addu  $7,$7,$30
48577		 lw    $7,0x00($7)
48578		 jr    $7
48579		 nop                    	 # Delay slot
48580
48581OP0_b138:				#:
48582		 addiu $23,$23,2
48583
48584		 srl   $24,$24,7
48585		 andi  $24,$24,0x1C
48586		 addu  $24,$24,$21
48587		 lb    $9,0x00($24)
48588		 lh    $14,0x00($23)
48589		 addiu $23,$23,2
48590		 lw    $25,0x7C($21)
48591		 sw    $15,m68k_ICount
48592		 sw    $9,0x44($29)
48593		 sw    $14,0x40($29)
48594		 sw    $24,0x3C($29)
48595		 or    $4,$0,$14
48596		 jalr  $25
48597		 sw    $23,0x4C($21)    	 # Delay slot
48598		 lw    $24,0x3C($29)
48599		 lw    $14,0x40($29)
48600		 lw    $9,0x44($29)
48601		 lw    $15,m68k_ICount
48602		 seb   $10,$2
48603		 xor   $2,$10,$9
48604		 and   $16,$0,$0        	 # Clear Carry
48605		 and   $17,$0,$0        	 # Clear Overflow
48606		 slt   $19,$2,$0        	 # Set Sign
48607		 sltiu $18,$2,1         	 # Set Zero
48608		 lw    $25,0x88($21)
48609		 sw    $15,m68k_ICount
48610		 sw    $9,0x44($29)
48611		 sw    $14,0x40($29)
48612		 sw    $24,0x3C($29)
48613		 or    $5,$0,$2
48614		 or    $4,$0,$14
48615		 jalr  $25
48616		 sw    $23,0x4C($21)    	 # Delay slot
48617		 lw    $24,0x3C($29)
48618		 lw    $14,0x40($29)
48619		 lw    $9,0x44($29)
48620		 lw    $15,m68k_ICount
48621		 addiu $15,$15,-16
48622		 bgez  $15,3f
48623		 lhu   $24,0x00($23)    	 # Delay slot
48624		 j     MainExit
48625	3:
48626		 sll   $7,$24,2         	 # Delay slot
48627		 addu  $7,$7,$30
48628		 lw    $7,0x00($7)
48629		 jr    $7
48630		 nop                    	 # Delay slot
48631
48632OP0_b139:				#:
48633		 addiu $23,$23,2
48634
48635		 srl   $24,$24,7
48636		 andi  $24,$24,0x1C
48637		 addu  $24,$24,$21
48638		 lb    $9,0x00($24)
48639		 lhu   $14,0x00($23)
48640		 lhu   $25,0x02($23)
48641		 sll   $14,$14,16
48642		 or    $14,$14,$25
48643		 addiu $23,$23,4
48644		 lw    $25,0x7C($21)
48645		 sw    $15,m68k_ICount
48646		 sw    $9,0x44($29)
48647		 sw    $14,0x40($29)
48648		 sw    $24,0x3C($29)
48649		 or    $4,$0,$14
48650		 jalr  $25
48651		 sw    $23,0x4C($21)    	 # Delay slot
48652		 lw    $24,0x3C($29)
48653		 lw    $14,0x40($29)
48654		 lw    $9,0x44($29)
48655		 lw    $15,m68k_ICount
48656		 seb   $10,$2
48657		 xor   $2,$10,$9
48658		 and   $16,$0,$0        	 # Clear Carry
48659		 and   $17,$0,$0        	 # Clear Overflow
48660		 slt   $19,$2,$0        	 # Set Sign
48661		 sltiu $18,$2,1         	 # Set Zero
48662		 lw    $25,0x88($21)
48663		 sw    $15,m68k_ICount
48664		 sw    $9,0x44($29)
48665		 sw    $14,0x40($29)
48666		 sw    $24,0x3C($29)
48667		 or    $5,$0,$2
48668		 or    $4,$0,$14
48669		 jalr  $25
48670		 sw    $23,0x4C($21)    	 # Delay slot
48671		 lw    $24,0x3C($29)
48672		 lw    $14,0x40($29)
48673		 lw    $9,0x44($29)
48674		 lw    $15,m68k_ICount
48675		 addiu $15,$15,-20
48676		 bgez  $15,3f
48677		 lhu   $24,0x00($23)    	 # Delay slot
48678		 j     MainExit
48679	3:
48680		 sll   $7,$24,2         	 # Delay slot
48681		 addu  $7,$7,$30
48682		 lw    $7,0x00($7)
48683		 jr    $7
48684		 nop                    	 # Delay slot
48685
48686OP0_b140:				#:
48687		 addiu $23,$23,2
48688
48689		 andi  $8,$24,0x07
48690		 srl   $24,$24,7
48691		 andi  $24,$24,0x1C
48692		 addu  $24,$24,$21
48693		 lh    $9,0x00($24)
48694		 sll   $8,$8,2
48695		 addu  $8,$8,$21
48696		 lh    $10,0x00($8)
48697		 xor   $2,$10,$9
48698		 and   $16,$0,$0        	 # Clear Carry
48699		 and   $17,$0,$0        	 # Clear Overflow
48700		 slt   $19,$2,$0        	 # Set Sign
48701		 sltiu $18,$2,1         	 # Set Zero
48702		 sh    $2,0x00($8)
48703		 addiu $15,$15,-8
48704		 bgez  $15,3f
48705		 lhu   $24,0x00($23)    	 # Delay slot
48706		 j     MainExit
48707	3:
48708		 sll   $7,$24,2         	 # Delay slot
48709		 addu  $7,$7,$30
48710		 lw    $7,0x00($7)
48711		 jr    $7
48712		 nop                    	 # Delay slot
48713
48714OP0_b150:				#:
48715		 addiu $23,$23,2
48716
48717		 andi  $8,$24,0x07
48718		 srl   $24,$24,7
48719		 andi  $24,$24,0x1C
48720		 addu  $24,$24,$21
48721		 lh    $9,0x00($24)
48722		 sll   $8,$8,2
48723		 addu  $8,$8,$21
48724		 lw    $14,0x20($8)
48725		 lw    $25,0x80($21)
48726		 sw    $15,m68k_ICount
48727		 sw    $9,0x44($29)
48728		 sw    $14,0x40($29)
48729		 sw    $24,0x3C($29)
48730		 or    $4,$0,$14
48731		 jalr  $25
48732		 sw    $23,0x4C($21)    	 # Delay slot
48733		 lw    $24,0x3C($29)
48734		 lw    $14,0x40($29)
48735		 lw    $9,0x44($29)
48736		 lw    $15,m68k_ICount
48737		 seh   $10,$2
48738		 xor   $2,$10,$9
48739		 and   $16,$0,$0        	 # Clear Carry
48740		 and   $17,$0,$0        	 # Clear Overflow
48741		 slt   $19,$2,$0        	 # Set Sign
48742		 sltiu $18,$2,1         	 # Set Zero
48743		 lw    $25,0x8C($21)
48744		 sw    $15,m68k_ICount
48745		 sw    $9,0x44($29)
48746		 sw    $14,0x40($29)
48747		 sw    $24,0x3C($29)
48748		 or    $5,$0,$2
48749		 or    $4,$0,$14
48750		 jalr  $25
48751		 sw    $23,0x4C($21)    	 # Delay slot
48752		 lw    $24,0x3C($29)
48753		 lw    $14,0x40($29)
48754		 lw    $9,0x44($29)
48755		 lw    $15,m68k_ICount
48756		 addiu $15,$15,-12
48757		 bgez  $15,3f
48758		 lhu   $24,0x00($23)    	 # Delay slot
48759		 j     MainExit
48760	3:
48761		 sll   $7,$24,2         	 # Delay slot
48762		 addu  $7,$7,$30
48763		 lw    $7,0x00($7)
48764		 jr    $7
48765		 nop                    	 # Delay slot
48766
48767OP0_b158:				#:
48768		 addiu $23,$23,2
48769
48770		 andi  $8,$24,0x07
48771		 srl   $24,$24,7
48772		 andi  $24,$24,0x1C
48773		 addu  $24,$24,$21
48774		 lh    $9,0x00($24)
48775		 sll   $8,$8,2
48776		 addu  $8,$8,$21
48777		 lw    $14,0x20($8)
48778		 addiu $25,$14,2
48779		 sw    $25,0x20($8)
48780		 lw    $25,0x80($21)
48781		 sw    $15,m68k_ICount
48782		 sw    $9,0x44($29)
48783		 sw    $14,0x40($29)
48784		 sw    $24,0x3C($29)
48785		 or    $4,$0,$14
48786		 jalr  $25
48787		 sw    $23,0x4C($21)    	 # Delay slot
48788		 lw    $24,0x3C($29)
48789		 lw    $14,0x40($29)
48790		 lw    $9,0x44($29)
48791		 lw    $15,m68k_ICount
48792		 seh   $10,$2
48793		 xor   $2,$10,$9
48794		 and   $16,$0,$0        	 # Clear Carry
48795		 and   $17,$0,$0        	 # Clear Overflow
48796		 slt   $19,$2,$0        	 # Set Sign
48797		 sltiu $18,$2,1         	 # Set Zero
48798		 lw    $25,0x8C($21)
48799		 sw    $15,m68k_ICount
48800		 sw    $9,0x44($29)
48801		 sw    $14,0x40($29)
48802		 sw    $24,0x3C($29)
48803		 or    $5,$0,$2
48804		 or    $4,$0,$14
48805		 jalr  $25
48806		 sw    $23,0x4C($21)    	 # Delay slot
48807		 lw    $24,0x3C($29)
48808		 lw    $14,0x40($29)
48809		 lw    $9,0x44($29)
48810		 lw    $15,m68k_ICount
48811		 addiu $15,$15,-12
48812		 bgez  $15,3f
48813		 lhu   $24,0x00($23)    	 # Delay slot
48814		 j     MainExit
48815	3:
48816		 sll   $7,$24,2         	 # Delay slot
48817		 addu  $7,$7,$30
48818		 lw    $7,0x00($7)
48819		 jr    $7
48820		 nop                    	 # Delay slot
48821
48822OP0_b160:				#:
48823		 addiu $23,$23,2
48824
48825		 andi  $8,$24,0x07
48826		 srl   $24,$24,7
48827		 andi  $24,$24,0x1C
48828		 addu  $24,$24,$21
48829		 lh    $9,0x00($24)
48830		 sll   $8,$8,2
48831		 addu  $8,$8,$21
48832		 lw    $14,0x20($8)
48833		 addiu $14,$14,-2
48834		 sw    $14,0x20($8)
48835		 lw    $25,0x80($21)
48836		 sw    $15,m68k_ICount
48837		 sw    $9,0x44($29)
48838		 sw    $14,0x40($29)
48839		 sw    $24,0x3C($29)
48840		 or    $4,$0,$14
48841		 jalr  $25
48842		 sw    $23,0x4C($21)    	 # Delay slot
48843		 lw    $24,0x3C($29)
48844		 lw    $14,0x40($29)
48845		 lw    $9,0x44($29)
48846		 lw    $15,m68k_ICount
48847		 seh   $10,$2
48848		 xor   $2,$10,$9
48849		 and   $16,$0,$0        	 # Clear Carry
48850		 and   $17,$0,$0        	 # Clear Overflow
48851		 slt   $19,$2,$0        	 # Set Sign
48852		 sltiu $18,$2,1         	 # Set Zero
48853		 lw    $25,0x8C($21)
48854		 sw    $15,m68k_ICount
48855		 sw    $9,0x44($29)
48856		 sw    $14,0x40($29)
48857		 sw    $24,0x3C($29)
48858		 or    $5,$0,$2
48859		 or    $4,$0,$14
48860		 jalr  $25
48861		 sw    $23,0x4C($21)    	 # Delay slot
48862		 lw    $24,0x3C($29)
48863		 lw    $14,0x40($29)
48864		 lw    $9,0x44($29)
48865		 lw    $15,m68k_ICount
48866		 addiu $15,$15,-14
48867		 bgez  $15,3f
48868		 lhu   $24,0x00($23)    	 # Delay slot
48869		 j     MainExit
48870	3:
48871		 sll   $7,$24,2         	 # Delay slot
48872		 addu  $7,$7,$30
48873		 lw    $7,0x00($7)
48874		 jr    $7
48875		 nop                    	 # Delay slot
48876
48877OP0_b168:				#:
48878		 addiu $23,$23,2
48879
48880		 andi  $8,$24,0x07
48881		 srl   $24,$24,7
48882		 andi  $24,$24,0x1C
48883		 addu  $24,$24,$21
48884		 lh    $9,0x00($24)
48885		 lh    $7,0x00($23)
48886		 sll   $8,$8,2
48887		 addu  $8,$8,$21
48888		 lw    $14,0x20($8)
48889		 addiu $23,$23,2
48890		 addu  $14,$14,$7
48891		 lw    $25,0x80($21)
48892		 sw    $15,m68k_ICount
48893		 sw    $9,0x44($29)
48894		 sw    $14,0x40($29)
48895		 sw    $24,0x3C($29)
48896		 or    $4,$0,$14
48897		 jalr  $25
48898		 sw    $23,0x4C($21)    	 # Delay slot
48899		 lw    $24,0x3C($29)
48900		 lw    $14,0x40($29)
48901		 lw    $9,0x44($29)
48902		 lw    $15,m68k_ICount
48903		 seh   $10,$2
48904		 xor   $2,$10,$9
48905		 and   $16,$0,$0        	 # Clear Carry
48906		 and   $17,$0,$0        	 # Clear Overflow
48907		 slt   $19,$2,$0        	 # Set Sign
48908		 sltiu $18,$2,1         	 # Set Zero
48909		 lw    $25,0x8C($21)
48910		 sw    $15,m68k_ICount
48911		 sw    $9,0x44($29)
48912		 sw    $14,0x40($29)
48913		 sw    $24,0x3C($29)
48914		 or    $5,$0,$2
48915		 or    $4,$0,$14
48916		 jalr  $25
48917		 sw    $23,0x4C($21)    	 # Delay slot
48918		 lw    $24,0x3C($29)
48919		 lw    $14,0x40($29)
48920		 lw    $9,0x44($29)
48921		 lw    $15,m68k_ICount
48922		 addiu $15,$15,-16
48923		 bgez  $15,3f
48924		 lhu   $24,0x00($23)    	 # Delay slot
48925		 j     MainExit
48926	3:
48927		 sll   $7,$24,2         	 # Delay slot
48928		 addu  $7,$7,$30
48929		 lw    $7,0x00($7)
48930		 jr    $7
48931		 nop                    	 # Delay slot
48932
48933OP0_b170:				#:
48934		 addiu $23,$23,2
48935
48936		 andi  $8,$24,0x07
48937		 srl   $24,$24,7
48938		 andi  $24,$24,0x1C
48939		 addu  $24,$24,$21
48940		 lh    $9,0x00($24)
48941		 sll   $8,$8,2
48942		 addu  $8,$8,$21
48943		 lw    $14,0x20($8)
48944		 lhu   $7,0x00($23)
48945		 addiu $23,$23,2
48946		 seb   $6,$7
48947		 or    $25,$0,$7
48948		 srl   $7,$7,12
48949		 andi  $25,$25,0x0800
48950		 sll   $7,$7,2
48951		 addu  $7,$7,$21
48952		 bne   $25,$0,0f
48953		 lw    $25,0x00($7)      	 # Delay slot
48954		 seh   $25,$25
48955	0:
48956		 addu  $25,$14,$25
48957		 addu  $14,$25,$6
48958		 lw    $25,0x80($21)
48959		 sw    $15,m68k_ICount
48960		 sw    $9,0x44($29)
48961		 sw    $14,0x40($29)
48962		 sw    $24,0x3C($29)
48963		 or    $4,$0,$14
48964		 jalr  $25
48965		 sw    $23,0x4C($21)    	 # Delay slot
48966		 lw    $24,0x3C($29)
48967		 lw    $14,0x40($29)
48968		 lw    $9,0x44($29)
48969		 lw    $15,m68k_ICount
48970		 seh   $10,$2
48971		 xor   $2,$10,$9
48972		 and   $16,$0,$0        	 # Clear Carry
48973		 and   $17,$0,$0        	 # Clear Overflow
48974		 slt   $19,$2,$0        	 # Set Sign
48975		 sltiu $18,$2,1         	 # Set Zero
48976		 lw    $25,0x8C($21)
48977		 sw    $15,m68k_ICount
48978		 sw    $9,0x44($29)
48979		 sw    $14,0x40($29)
48980		 sw    $24,0x3C($29)
48981		 or    $5,$0,$2
48982		 or    $4,$0,$14
48983		 jalr  $25
48984		 sw    $23,0x4C($21)    	 # Delay slot
48985		 lw    $24,0x3C($29)
48986		 lw    $14,0x40($29)
48987		 lw    $9,0x44($29)
48988		 lw    $15,m68k_ICount
48989		 addiu $15,$15,-18
48990		 bgez  $15,3f
48991		 lhu   $24,0x00($23)    	 # Delay slot
48992		 j     MainExit
48993	3:
48994		 sll   $7,$24,2         	 # Delay slot
48995		 addu  $7,$7,$30
48996		 lw    $7,0x00($7)
48997		 jr    $7
48998		 nop                    	 # Delay slot
48999
49000OP0_b178:				#:
49001		 addiu $23,$23,2
49002
49003		 srl   $24,$24,7
49004		 andi  $24,$24,0x1C
49005		 addu  $24,$24,$21
49006		 lh    $9,0x00($24)
49007		 lh    $14,0x00($23)
49008		 addiu $23,$23,2
49009		 lw    $25,0x80($21)
49010		 sw    $15,m68k_ICount
49011		 sw    $9,0x44($29)
49012		 sw    $14,0x40($29)
49013		 sw    $24,0x3C($29)
49014		 or    $4,$0,$14
49015		 jalr  $25
49016		 sw    $23,0x4C($21)    	 # Delay slot
49017		 lw    $24,0x3C($29)
49018		 lw    $14,0x40($29)
49019		 lw    $9,0x44($29)
49020		 lw    $15,m68k_ICount
49021		 seh   $10,$2
49022		 xor   $2,$10,$9
49023		 and   $16,$0,$0        	 # Clear Carry
49024		 and   $17,$0,$0        	 # Clear Overflow
49025		 slt   $19,$2,$0        	 # Set Sign
49026		 sltiu $18,$2,1         	 # Set Zero
49027		 lw    $25,0x8C($21)
49028		 sw    $15,m68k_ICount
49029		 sw    $9,0x44($29)
49030		 sw    $14,0x40($29)
49031		 sw    $24,0x3C($29)
49032		 or    $5,$0,$2
49033		 or    $4,$0,$14
49034		 jalr  $25
49035		 sw    $23,0x4C($21)    	 # Delay slot
49036		 lw    $24,0x3C($29)
49037		 lw    $14,0x40($29)
49038		 lw    $9,0x44($29)
49039		 lw    $15,m68k_ICount
49040		 addiu $15,$15,-16
49041		 bgez  $15,3f
49042		 lhu   $24,0x00($23)    	 # Delay slot
49043		 j     MainExit
49044	3:
49045		 sll   $7,$24,2         	 # Delay slot
49046		 addu  $7,$7,$30
49047		 lw    $7,0x00($7)
49048		 jr    $7
49049		 nop                    	 # Delay slot
49050
49051OP0_b179:				#:
49052		 addiu $23,$23,2
49053
49054		 srl   $24,$24,7
49055		 andi  $24,$24,0x1C
49056		 addu  $24,$24,$21
49057		 lh    $9,0x00($24)
49058		 lhu   $14,0x00($23)
49059		 lhu   $25,0x02($23)
49060		 sll   $14,$14,16
49061		 or    $14,$14,$25
49062		 addiu $23,$23,4
49063		 lw    $25,0x80($21)
49064		 sw    $15,m68k_ICount
49065		 sw    $9,0x44($29)
49066		 sw    $14,0x40($29)
49067		 sw    $24,0x3C($29)
49068		 or    $4,$0,$14
49069		 jalr  $25
49070		 sw    $23,0x4C($21)    	 # Delay slot
49071		 lw    $24,0x3C($29)
49072		 lw    $14,0x40($29)
49073		 lw    $9,0x44($29)
49074		 lw    $15,m68k_ICount
49075		 seh   $10,$2
49076		 xor   $2,$10,$9
49077		 and   $16,$0,$0        	 # Clear Carry
49078		 and   $17,$0,$0        	 # Clear Overflow
49079		 slt   $19,$2,$0        	 # Set Sign
49080		 sltiu $18,$2,1         	 # Set Zero
49081		 lw    $25,0x8C($21)
49082		 sw    $15,m68k_ICount
49083		 sw    $9,0x44($29)
49084		 sw    $14,0x40($29)
49085		 sw    $24,0x3C($29)
49086		 or    $5,$0,$2
49087		 or    $4,$0,$14
49088		 jalr  $25
49089		 sw    $23,0x4C($21)    	 # Delay slot
49090		 lw    $24,0x3C($29)
49091		 lw    $14,0x40($29)
49092		 lw    $9,0x44($29)
49093		 lw    $15,m68k_ICount
49094		 addiu $15,$15,-20
49095		 bgez  $15,3f
49096		 lhu   $24,0x00($23)    	 # Delay slot
49097		 j     MainExit
49098	3:
49099		 sll   $7,$24,2         	 # Delay slot
49100		 addu  $7,$7,$30
49101		 lw    $7,0x00($7)
49102		 jr    $7
49103		 nop                    	 # Delay slot
49104
49105OP0_b180:				#:
49106		 addiu $23,$23,2
49107
49108		 andi  $8,$24,0x07
49109		 srl   $24,$24,7
49110		 andi  $24,$24,0x1C
49111		 addu  $24,$24,$21
49112		 lw    $9,0x00($24)
49113		 sll   $8,$8,2
49114		 addu  $8,$8,$21
49115		 lw    $10,0x00($8)
49116		 xor   $2,$10,$9
49117		 and   $16,$0,$0        	 # Clear Carry
49118		 and   $17,$0,$0        	 # Clear Overflow
49119		 slt   $19,$2,$0        	 # Set Sign
49120		 sltiu $18,$2,1         	 # Set Zero
49121		 sw    $2,0x00($8)
49122		 addiu $15,$15,-12
49123		 bgez  $15,3f
49124		 lhu   $24,0x00($23)    	 # Delay slot
49125		 j     MainExit
49126	3:
49127		 sll   $7,$24,2         	 # Delay slot
49128		 addu  $7,$7,$30
49129		 lw    $7,0x00($7)
49130		 jr    $7
49131		 nop                    	 # Delay slot
49132
49133OP0_b190:				#:
49134		 addiu $23,$23,2
49135
49136		 andi  $8,$24,0x07
49137		 srl   $24,$24,7
49138		 andi  $24,$24,0x1C
49139		 addu  $24,$24,$21
49140		 lw    $9,0x00($24)
49141		 sll   $8,$8,2
49142		 addu  $8,$8,$21
49143		 lw    $14,0x20($8)
49144		 lw    $25,0x84($21)
49145		 sw    $15,m68k_ICount
49146		 sw    $9,0x44($29)
49147		 sw    $14,0x40($29)
49148		 sw    $24,0x3C($29)
49149		 or    $4,$0,$14
49150		 jalr  $25
49151		 sw    $23,0x4C($21)    	 # Delay slot
49152		 lw    $24,0x3C($29)
49153		 lw    $14,0x40($29)
49154		 lw    $9,0x44($29)
49155		 lw    $15,m68k_ICount
49156		 or    $10,$0,$2
49157		 xor   $2,$10,$9
49158		 and   $16,$0,$0        	 # Clear Carry
49159		 and   $17,$0,$0        	 # Clear Overflow
49160		 slt   $19,$2,$0        	 # Set Sign
49161		 sltiu $18,$2,1         	 # Set Zero
49162		 lw    $25,0x90($21)
49163		 sw    $15,m68k_ICount
49164		 sw    $9,0x44($29)
49165		 sw    $14,0x40($29)
49166		 sw    $24,0x3C($29)
49167		 or    $5,$0,$2
49168		 or    $4,$0,$14
49169		 jalr  $25
49170		 sw    $23,0x4C($21)    	 # Delay slot
49171		 lw    $24,0x3C($29)
49172		 lw    $14,0x40($29)
49173		 lw    $9,0x44($29)
49174		 lw    $15,m68k_ICount
49175		 addiu $15,$15,-20
49176		 bgez  $15,3f
49177		 lhu   $24,0x00($23)    	 # Delay slot
49178		 j     MainExit
49179	3:
49180		 sll   $7,$24,2         	 # Delay slot
49181		 addu  $7,$7,$30
49182		 lw    $7,0x00($7)
49183		 jr    $7
49184		 nop                    	 # Delay slot
49185
49186OP0_b198:				#:
49187		 addiu $23,$23,2
49188
49189		 andi  $8,$24,0x07
49190		 srl   $24,$24,7
49191		 andi  $24,$24,0x1C
49192		 addu  $24,$24,$21
49193		 lw    $9,0x00($24)
49194		 sll   $8,$8,2
49195		 addu  $8,$8,$21
49196		 lw    $14,0x20($8)
49197		 addiu $25,$14,4
49198		 sw    $25,0x20($8)
49199		 lw    $25,0x84($21)
49200		 sw    $15,m68k_ICount
49201		 sw    $9,0x44($29)
49202		 sw    $14,0x40($29)
49203		 sw    $24,0x3C($29)
49204		 or    $4,$0,$14
49205		 jalr  $25
49206		 sw    $23,0x4C($21)    	 # Delay slot
49207		 lw    $24,0x3C($29)
49208		 lw    $14,0x40($29)
49209		 lw    $9,0x44($29)
49210		 lw    $15,m68k_ICount
49211		 or    $10,$0,$2
49212		 xor   $2,$10,$9
49213		 and   $16,$0,$0        	 # Clear Carry
49214		 and   $17,$0,$0        	 # Clear Overflow
49215		 slt   $19,$2,$0        	 # Set Sign
49216		 sltiu $18,$2,1         	 # Set Zero
49217		 lw    $25,0x90($21)
49218		 sw    $15,m68k_ICount
49219		 sw    $9,0x44($29)
49220		 sw    $14,0x40($29)
49221		 sw    $24,0x3C($29)
49222		 or    $5,$0,$2
49223		 or    $4,$0,$14
49224		 jalr  $25
49225		 sw    $23,0x4C($21)    	 # Delay slot
49226		 lw    $24,0x3C($29)
49227		 lw    $14,0x40($29)
49228		 lw    $9,0x44($29)
49229		 lw    $15,m68k_ICount
49230		 addiu $15,$15,-20
49231		 bgez  $15,3f
49232		 lhu   $24,0x00($23)    	 # Delay slot
49233		 j     MainExit
49234	3:
49235		 sll   $7,$24,2         	 # Delay slot
49236		 addu  $7,$7,$30
49237		 lw    $7,0x00($7)
49238		 jr    $7
49239		 nop                    	 # Delay slot
49240
49241OP0_b1a0:				#:
49242		 addiu $23,$23,2
49243
49244		 andi  $8,$24,0x07
49245		 srl   $24,$24,7
49246		 andi  $24,$24,0x1C
49247		 addu  $24,$24,$21
49248		 lw    $9,0x00($24)
49249		 sll   $8,$8,2
49250		 addu  $8,$8,$21
49251		 lw    $14,0x20($8)
49252		 addiu $14,$14,-4
49253		 sw    $14,0x20($8)
49254		 lw    $25,0x84($21)
49255		 sw    $15,m68k_ICount
49256		 sw    $9,0x44($29)
49257		 sw    $14,0x40($29)
49258		 sw    $24,0x3C($29)
49259		 or    $4,$0,$14
49260		 jalr  $25
49261		 sw    $23,0x4C($21)    	 # Delay slot
49262		 lw    $24,0x3C($29)
49263		 lw    $14,0x40($29)
49264		 lw    $9,0x44($29)
49265		 lw    $15,m68k_ICount
49266		 or    $10,$0,$2
49267		 xor   $2,$10,$9
49268		 and   $16,$0,$0        	 # Clear Carry
49269		 and   $17,$0,$0        	 # Clear Overflow
49270		 slt   $19,$2,$0        	 # Set Sign
49271		 sltiu $18,$2,1         	 # Set Zero
49272		 lw    $25,0x90($21)
49273		 sw    $15,m68k_ICount
49274		 sw    $9,0x44($29)
49275		 sw    $14,0x40($29)
49276		 sw    $24,0x3C($29)
49277		 or    $5,$0,$2
49278		 or    $4,$0,$14
49279		 jalr  $25
49280		 sw    $23,0x4C($21)    	 # Delay slot
49281		 lw    $24,0x3C($29)
49282		 lw    $14,0x40($29)
49283		 lw    $9,0x44($29)
49284		 lw    $15,m68k_ICount
49285		 addiu $15,$15,-22
49286		 bgez  $15,3f
49287		 lhu   $24,0x00($23)    	 # Delay slot
49288		 j     MainExit
49289	3:
49290		 sll   $7,$24,2         	 # Delay slot
49291		 addu  $7,$7,$30
49292		 lw    $7,0x00($7)
49293		 jr    $7
49294		 nop                    	 # Delay slot
49295
49296OP0_b1a8:				#:
49297		 addiu $23,$23,2
49298
49299		 andi  $8,$24,0x07
49300		 srl   $24,$24,7
49301		 andi  $24,$24,0x1C
49302		 addu  $24,$24,$21
49303		 lw    $9,0x00($24)
49304		 lh    $7,0x00($23)
49305		 sll   $8,$8,2
49306		 addu  $8,$8,$21
49307		 lw    $14,0x20($8)
49308		 addiu $23,$23,2
49309		 addu  $14,$14,$7
49310		 lw    $25,0x84($21)
49311		 sw    $15,m68k_ICount
49312		 sw    $9,0x44($29)
49313		 sw    $14,0x40($29)
49314		 sw    $24,0x3C($29)
49315		 or    $4,$0,$14
49316		 jalr  $25
49317		 sw    $23,0x4C($21)    	 # Delay slot
49318		 lw    $24,0x3C($29)
49319		 lw    $14,0x40($29)
49320		 lw    $9,0x44($29)
49321		 lw    $15,m68k_ICount
49322		 or    $10,$0,$2
49323		 xor   $2,$10,$9
49324		 and   $16,$0,$0        	 # Clear Carry
49325		 and   $17,$0,$0        	 # Clear Overflow
49326		 slt   $19,$2,$0        	 # Set Sign
49327		 sltiu $18,$2,1         	 # Set Zero
49328		 lw    $25,0x90($21)
49329		 sw    $15,m68k_ICount
49330		 sw    $9,0x44($29)
49331		 sw    $14,0x40($29)
49332		 sw    $24,0x3C($29)
49333		 or    $5,$0,$2
49334		 or    $4,$0,$14
49335		 jalr  $25
49336		 sw    $23,0x4C($21)    	 # Delay slot
49337		 lw    $24,0x3C($29)
49338		 lw    $14,0x40($29)
49339		 lw    $9,0x44($29)
49340		 lw    $15,m68k_ICount
49341		 addiu $15,$15,-24
49342		 bgez  $15,3f
49343		 lhu   $24,0x00($23)    	 # Delay slot
49344		 j     MainExit
49345	3:
49346		 sll   $7,$24,2         	 # Delay slot
49347		 addu  $7,$7,$30
49348		 lw    $7,0x00($7)
49349		 jr    $7
49350		 nop                    	 # Delay slot
49351
49352OP0_b1b0:				#:
49353		 addiu $23,$23,2
49354
49355		 andi  $8,$24,0x07
49356		 srl   $24,$24,7
49357		 andi  $24,$24,0x1C
49358		 addu  $24,$24,$21
49359		 lw    $9,0x00($24)
49360		 sll   $8,$8,2
49361		 addu  $8,$8,$21
49362		 lw    $14,0x20($8)
49363		 lhu   $7,0x00($23)
49364		 addiu $23,$23,2
49365		 seb   $6,$7
49366		 or    $25,$0,$7
49367		 srl   $7,$7,12
49368		 andi  $25,$25,0x0800
49369		 sll   $7,$7,2
49370		 addu  $7,$7,$21
49371		 bne   $25,$0,0f
49372		 lw    $25,0x00($7)      	 # Delay slot
49373		 seh   $25,$25
49374	0:
49375		 addu  $25,$14,$25
49376		 addu  $14,$25,$6
49377		 lw    $25,0x84($21)
49378		 sw    $15,m68k_ICount
49379		 sw    $9,0x44($29)
49380		 sw    $14,0x40($29)
49381		 sw    $24,0x3C($29)
49382		 or    $4,$0,$14
49383		 jalr  $25
49384		 sw    $23,0x4C($21)    	 # Delay slot
49385		 lw    $24,0x3C($29)
49386		 lw    $14,0x40($29)
49387		 lw    $9,0x44($29)
49388		 lw    $15,m68k_ICount
49389		 or    $10,$0,$2
49390		 xor   $2,$10,$9
49391		 and   $16,$0,$0        	 # Clear Carry
49392		 and   $17,$0,$0        	 # Clear Overflow
49393		 slt   $19,$2,$0        	 # Set Sign
49394		 sltiu $18,$2,1         	 # Set Zero
49395		 lw    $25,0x90($21)
49396		 sw    $15,m68k_ICount
49397		 sw    $9,0x44($29)
49398		 sw    $14,0x40($29)
49399		 sw    $24,0x3C($29)
49400		 or    $5,$0,$2
49401		 or    $4,$0,$14
49402		 jalr  $25
49403		 sw    $23,0x4C($21)    	 # Delay slot
49404		 lw    $24,0x3C($29)
49405		 lw    $14,0x40($29)
49406		 lw    $9,0x44($29)
49407		 lw    $15,m68k_ICount
49408		 addiu $15,$15,-26
49409		 bgez  $15,3f
49410		 lhu   $24,0x00($23)    	 # Delay slot
49411		 j     MainExit
49412	3:
49413		 sll   $7,$24,2         	 # Delay slot
49414		 addu  $7,$7,$30
49415		 lw    $7,0x00($7)
49416		 jr    $7
49417		 nop                    	 # Delay slot
49418
49419OP0_b1b8:				#:
49420		 addiu $23,$23,2
49421
49422		 srl   $24,$24,7
49423		 andi  $24,$24,0x1C
49424		 addu  $24,$24,$21
49425		 lw    $9,0x00($24)
49426		 lh    $14,0x00($23)
49427		 addiu $23,$23,2
49428		 lw    $25,0x84($21)
49429		 sw    $15,m68k_ICount
49430		 sw    $9,0x44($29)
49431		 sw    $14,0x40($29)
49432		 sw    $24,0x3C($29)
49433		 or    $4,$0,$14
49434		 jalr  $25
49435		 sw    $23,0x4C($21)    	 # Delay slot
49436		 lw    $24,0x3C($29)
49437		 lw    $14,0x40($29)
49438		 lw    $9,0x44($29)
49439		 lw    $15,m68k_ICount
49440		 or    $10,$0,$2
49441		 xor   $2,$10,$9
49442		 and   $16,$0,$0        	 # Clear Carry
49443		 and   $17,$0,$0        	 # Clear Overflow
49444		 slt   $19,$2,$0        	 # Set Sign
49445		 sltiu $18,$2,1         	 # Set Zero
49446		 lw    $25,0x90($21)
49447		 sw    $15,m68k_ICount
49448		 sw    $9,0x44($29)
49449		 sw    $14,0x40($29)
49450		 sw    $24,0x3C($29)
49451		 or    $5,$0,$2
49452		 or    $4,$0,$14
49453		 jalr  $25
49454		 sw    $23,0x4C($21)    	 # Delay slot
49455		 lw    $24,0x3C($29)
49456		 lw    $14,0x40($29)
49457		 lw    $9,0x44($29)
49458		 lw    $15,m68k_ICount
49459		 addiu $15,$15,-24
49460		 bgez  $15,3f
49461		 lhu   $24,0x00($23)    	 # Delay slot
49462		 j     MainExit
49463	3:
49464		 sll   $7,$24,2         	 # Delay slot
49465		 addu  $7,$7,$30
49466		 lw    $7,0x00($7)
49467		 jr    $7
49468		 nop                    	 # Delay slot
49469
49470OP0_b1b9:				#:
49471		 addiu $23,$23,2
49472
49473		 srl   $24,$24,7
49474		 andi  $24,$24,0x1C
49475		 addu  $24,$24,$21
49476		 lw    $9,0x00($24)
49477		 lhu   $14,0x00($23)
49478		 lhu   $25,0x02($23)
49479		 sll   $14,$14,16
49480		 or    $14,$14,$25
49481		 addiu $23,$23,4
49482		 lw    $25,0x84($21)
49483		 sw    $15,m68k_ICount
49484		 sw    $9,0x44($29)
49485		 sw    $14,0x40($29)
49486		 sw    $24,0x3C($29)
49487		 or    $4,$0,$14
49488		 jalr  $25
49489		 sw    $23,0x4C($21)    	 # Delay slot
49490		 lw    $24,0x3C($29)
49491		 lw    $14,0x40($29)
49492		 lw    $9,0x44($29)
49493		 lw    $15,m68k_ICount
49494		 or    $10,$0,$2
49495		 xor   $2,$10,$9
49496		 and   $16,$0,$0        	 # Clear Carry
49497		 and   $17,$0,$0        	 # Clear Overflow
49498		 slt   $19,$2,$0        	 # Set Sign
49499		 sltiu $18,$2,1         	 # Set Zero
49500		 lw    $25,0x90($21)
49501		 sw    $15,m68k_ICount
49502		 sw    $9,0x44($29)
49503		 sw    $14,0x40($29)
49504		 sw    $24,0x3C($29)
49505		 or    $5,$0,$2
49506		 or    $4,$0,$14
49507		 jalr  $25
49508		 sw    $23,0x4C($21)    	 # Delay slot
49509		 lw    $24,0x3C($29)
49510		 lw    $14,0x40($29)
49511		 lw    $9,0x44($29)
49512		 lw    $15,m68k_ICount
49513		 addiu $15,$15,-28
49514		 bgez  $15,3f
49515		 lhu   $24,0x00($23)    	 # Delay slot
49516		 j     MainExit
49517	3:
49518		 sll   $7,$24,2         	 # Delay slot
49519		 addu  $7,$7,$30
49520		 lw    $7,0x00($7)
49521		 jr    $7
49522		 nop                    	 # Delay slot
49523
49524OP0_c000:				#:
49525		 addiu $23,$23,2
49526
49527		 andi  $8,$24,0x07
49528		 srl   $24,$24,7
49529		 andi  $24,$24,0x1C
49530		 addu  $24,$24,$21
49531		 lb    $9,0x00($24)
49532		 sll   $8,$8,2
49533		 addu  $8,$8,$21
49534		 lb    $2,0x00($8)
49535		 and   $10,$9,$2
49536		 sb    $10,0x00($24)
49537		 and   $16,$0,$0        	 # Clear Carry
49538		 and   $17,$0,$0        	 # Clear Overflow
49539		 slt   $19,$10,$0        	 # Set Sign
49540		 sltiu $18,$10,1         	 # Set Zero
49541		 addiu $15,$15,-4
49542		 bgez  $15,3f
49543		 lhu   $24,0x00($23)    	 # Delay slot
49544		 j     MainExit
49545	3:
49546		 sll   $7,$24,2         	 # Delay slot
49547		 addu  $7,$7,$30
49548		 lw    $7,0x00($7)
49549		 jr    $7
49550		 nop                    	 # Delay slot
49551
49552OP0_c010:				#:
49553		 addiu $23,$23,2
49554
49555		 andi  $8,$24,0x07
49556		 srl   $24,$24,7
49557		 andi  $24,$24,0x1C
49558		 addu  $24,$24,$21
49559		 lb    $9,0x00($24)
49560		 sll   $8,$8,2
49561		 addu  $8,$8,$21
49562		 lw    $14,0x20($8)
49563		 lw    $25,0x7C($21)
49564		 sw    $15,m68k_ICount
49565		 sw    $9,0x44($29)
49566		 sw    $24,0x40($29)
49567		 or    $4,$0,$14
49568		 jalr  $25
49569		 sw    $23,0x4C($21)    	 # Delay slot
49570		 lw    $24,0x40($29)
49571		 lw    $9,0x44($29)
49572		 lw    $15,m68k_ICount
49573		 seb   $2,$2
49574		 and   $10,$9,$2
49575		 sb    $10,0x00($24)
49576		 and   $16,$0,$0        	 # Clear Carry
49577		 and   $17,$0,$0        	 # Clear Overflow
49578		 slt   $19,$10,$0        	 # Set Sign
49579		 sltiu $18,$10,1         	 # Set Zero
49580		 addiu $15,$15,-8
49581		 bgez  $15,3f
49582		 lhu   $24,0x00($23)    	 # Delay slot
49583		 j     MainExit
49584	3:
49585		 sll   $7,$24,2         	 # Delay slot
49586		 addu  $7,$7,$30
49587		 lw    $7,0x00($7)
49588		 jr    $7
49589		 nop                    	 # Delay slot
49590
49591OP0_c018:				#:
49592		 addiu $23,$23,2
49593
49594		 andi  $8,$24,0x07
49595		 srl   $24,$24,7
49596		 andi  $24,$24,0x1C
49597		 addu  $24,$24,$21
49598		 lb    $9,0x00($24)
49599		 sll   $8,$8,2
49600		 addu  $8,$8,$21
49601		 lw    $14,0x20($8)
49602		 addiu $25,$14,1
49603		 sw    $25,0x20($8)
49604		 lw    $25,0x7C($21)
49605		 sw    $15,m68k_ICount
49606		 sw    $9,0x44($29)
49607		 sw    $24,0x40($29)
49608		 or    $4,$0,$14
49609		 jalr  $25
49610		 sw    $23,0x4C($21)    	 # Delay slot
49611		 lw    $24,0x40($29)
49612		 lw    $9,0x44($29)
49613		 lw    $15,m68k_ICount
49614		 seb   $2,$2
49615		 and   $10,$9,$2
49616		 sb    $10,0x00($24)
49617		 and   $16,$0,$0        	 # Clear Carry
49618		 and   $17,$0,$0        	 # Clear Overflow
49619		 slt   $19,$10,$0        	 # Set Sign
49620		 sltiu $18,$10,1         	 # Set Zero
49621		 addiu $15,$15,-8
49622		 bgez  $15,3f
49623		 lhu   $24,0x00($23)    	 # Delay slot
49624		 j     MainExit
49625	3:
49626		 sll   $7,$24,2         	 # Delay slot
49627		 addu  $7,$7,$30
49628		 lw    $7,0x00($7)
49629		 jr    $7
49630		 nop                    	 # Delay slot
49631
49632OP0_c01f:				#:
49633		 addiu $23,$23,2
49634
49635		 srl   $24,$24,7
49636		 andi  $24,$24,0x1C
49637		 addu  $24,$24,$21
49638		 lb    $9,0x00($24)
49639		 lw    $14,0x3C($21)    	 # Get A7
49640		 addiu $25,$14,2
49641		 sw    $25,0x3C($21)
49642		 lw    $25,0x7C($21)
49643		 sw    $15,m68k_ICount
49644		 sw    $9,0x44($29)
49645		 sw    $24,0x40($29)
49646		 or    $4,$0,$14
49647		 jalr  $25
49648		 sw    $23,0x4C($21)    	 # Delay slot
49649		 lw    $24,0x40($29)
49650		 lw    $9,0x44($29)
49651		 lw    $15,m68k_ICount
49652		 seb   $2,$2
49653		 and   $10,$9,$2
49654		 sb    $10,0x00($24)
49655		 and   $16,$0,$0        	 # Clear Carry
49656		 and   $17,$0,$0        	 # Clear Overflow
49657		 slt   $19,$10,$0        	 # Set Sign
49658		 sltiu $18,$10,1         	 # Set Zero
49659		 addiu $15,$15,-8
49660		 bgez  $15,3f
49661		 lhu   $24,0x00($23)    	 # Delay slot
49662		 j     MainExit
49663	3:
49664		 sll   $7,$24,2         	 # Delay slot
49665		 addu  $7,$7,$30
49666		 lw    $7,0x00($7)
49667		 jr    $7
49668		 nop                    	 # Delay slot
49669
49670OP0_c020:				#:
49671		 addiu $23,$23,2
49672
49673		 andi  $8,$24,0x07
49674		 srl   $24,$24,7
49675		 andi  $24,$24,0x1C
49676		 addu  $24,$24,$21
49677		 lb    $9,0x00($24)
49678		 sll   $8,$8,2
49679		 addu  $8,$8,$21
49680		 lw    $14,0x20($8)
49681		 addiu $14,$14,-1
49682		 sw    $14,0x20($8)
49683		 lw    $25,0x7C($21)
49684		 sw    $15,m68k_ICount
49685		 sw    $9,0x44($29)
49686		 sw    $24,0x40($29)
49687		 or    $4,$0,$14
49688		 jalr  $25
49689		 sw    $23,0x4C($21)    	 # Delay slot
49690		 lw    $24,0x40($29)
49691		 lw    $9,0x44($29)
49692		 lw    $15,m68k_ICount
49693		 seb   $2,$2
49694		 and   $10,$9,$2
49695		 sb    $10,0x00($24)
49696		 and   $16,$0,$0        	 # Clear Carry
49697		 and   $17,$0,$0        	 # Clear Overflow
49698		 slt   $19,$10,$0        	 # Set Sign
49699		 sltiu $18,$10,1         	 # Set Zero
49700		 addiu $15,$15,-10
49701		 bgez  $15,3f
49702		 lhu   $24,0x00($23)    	 # Delay slot
49703		 j     MainExit
49704	3:
49705		 sll   $7,$24,2         	 # Delay slot
49706		 addu  $7,$7,$30
49707		 lw    $7,0x00($7)
49708		 jr    $7
49709		 nop                    	 # Delay slot
49710
49711OP0_c027:				#:
49712		 addiu $23,$23,2
49713
49714		 srl   $24,$24,7
49715		 andi  $24,$24,0x1C
49716		 addu  $24,$24,$21
49717		 lb    $9,0x00($24)
49718		 lw    $14,0x3C($21)    	 # Get A7
49719		 addiu $14,$14,-2
49720		 sw    $14,0x3C($21)
49721		 lw    $25,0x7C($21)
49722		 sw    $15,m68k_ICount
49723		 sw    $9,0x44($29)
49724		 sw    $24,0x40($29)
49725		 or    $4,$0,$14
49726		 jalr  $25
49727		 sw    $23,0x4C($21)    	 # Delay slot
49728		 lw    $24,0x40($29)
49729		 lw    $9,0x44($29)
49730		 lw    $15,m68k_ICount
49731		 seb   $2,$2
49732		 and   $10,$9,$2
49733		 sb    $10,0x00($24)
49734		 and   $16,$0,$0        	 # Clear Carry
49735		 and   $17,$0,$0        	 # Clear Overflow
49736		 slt   $19,$10,$0        	 # Set Sign
49737		 sltiu $18,$10,1         	 # Set Zero
49738		 addiu $15,$15,-10
49739		 bgez  $15,3f
49740		 lhu   $24,0x00($23)    	 # Delay slot
49741		 j     MainExit
49742	3:
49743		 sll   $7,$24,2         	 # Delay slot
49744		 addu  $7,$7,$30
49745		 lw    $7,0x00($7)
49746		 jr    $7
49747		 nop                    	 # Delay slot
49748
49749OP0_c028:				#:
49750		 addiu $23,$23,2
49751
49752		 andi  $8,$24,0x07
49753		 srl   $24,$24,7
49754		 andi  $24,$24,0x1C
49755		 addu  $24,$24,$21
49756		 lb    $9,0x00($24)
49757		 lh    $7,0x00($23)
49758		 sll   $8,$8,2
49759		 addu  $8,$8,$21
49760		 lw    $14,0x20($8)
49761		 addiu $23,$23,2
49762		 addu  $14,$14,$7
49763		 lw    $25,0x7C($21)
49764		 sw    $15,m68k_ICount
49765		 sw    $9,0x44($29)
49766		 sw    $24,0x40($29)
49767		 or    $4,$0,$14
49768		 jalr  $25
49769		 sw    $23,0x4C($21)    	 # Delay slot
49770		 lw    $24,0x40($29)
49771		 lw    $9,0x44($29)
49772		 lw    $15,m68k_ICount
49773		 seb   $2,$2
49774		 and   $10,$9,$2
49775		 sb    $10,0x00($24)
49776		 and   $16,$0,$0        	 # Clear Carry
49777		 and   $17,$0,$0        	 # Clear Overflow
49778		 slt   $19,$10,$0        	 # Set Sign
49779		 sltiu $18,$10,1         	 # Set Zero
49780		 addiu $15,$15,-12
49781		 bgez  $15,3f
49782		 lhu   $24,0x00($23)    	 # Delay slot
49783		 j     MainExit
49784	3:
49785		 sll   $7,$24,2         	 # Delay slot
49786		 addu  $7,$7,$30
49787		 lw    $7,0x00($7)
49788		 jr    $7
49789		 nop                    	 # Delay slot
49790
49791OP0_c030:				#:
49792		 addiu $23,$23,2
49793
49794		 andi  $8,$24,0x07
49795		 srl   $24,$24,7
49796		 andi  $24,$24,0x1C
49797		 addu  $24,$24,$21
49798		 lb    $9,0x00($24)
49799		 sll   $8,$8,2
49800		 addu  $8,$8,$21
49801		 lw    $14,0x20($8)
49802		 lhu   $7,0x00($23)
49803		 addiu $23,$23,2
49804		 seb   $6,$7
49805		 or    $25,$0,$7
49806		 srl   $7,$7,12
49807		 andi  $25,$25,0x0800
49808		 sll   $7,$7,2
49809		 addu  $7,$7,$21
49810		 bne   $25,$0,0f
49811		 lw    $25,0x00($7)      	 # Delay slot
49812		 seh   $25,$25
49813	0:
49814		 addu  $25,$14,$25
49815		 addu  $14,$25,$6
49816		 lw    $25,0x7C($21)
49817		 sw    $15,m68k_ICount
49818		 sw    $9,0x44($29)
49819		 sw    $24,0x40($29)
49820		 or    $4,$0,$14
49821		 jalr  $25
49822		 sw    $23,0x4C($21)    	 # Delay slot
49823		 lw    $24,0x40($29)
49824		 lw    $9,0x44($29)
49825		 lw    $15,m68k_ICount
49826		 seb   $2,$2
49827		 and   $10,$9,$2
49828		 sb    $10,0x00($24)
49829		 and   $16,$0,$0        	 # Clear Carry
49830		 and   $17,$0,$0        	 # Clear Overflow
49831		 slt   $19,$10,$0        	 # Set Sign
49832		 sltiu $18,$10,1         	 # Set Zero
49833		 addiu $15,$15,-14
49834		 bgez  $15,3f
49835		 lhu   $24,0x00($23)    	 # Delay slot
49836		 j     MainExit
49837	3:
49838		 sll   $7,$24,2         	 # Delay slot
49839		 addu  $7,$7,$30
49840		 lw    $7,0x00($7)
49841		 jr    $7
49842		 nop                    	 # Delay slot
49843
49844OP0_c038:				#:
49845		 addiu $23,$23,2
49846
49847		 srl   $24,$24,7
49848		 andi  $24,$24,0x1C
49849		 addu  $24,$24,$21
49850		 lb    $9,0x00($24)
49851		 lh    $14,0x00($23)
49852		 addiu $23,$23,2
49853		 lw    $25,0x7C($21)
49854		 sw    $15,m68k_ICount
49855		 sw    $9,0x44($29)
49856		 sw    $24,0x40($29)
49857		 or    $4,$0,$14
49858		 jalr  $25
49859		 sw    $23,0x4C($21)    	 # Delay slot
49860		 lw    $24,0x40($29)
49861		 lw    $9,0x44($29)
49862		 lw    $15,m68k_ICount
49863		 seb   $2,$2
49864		 and   $10,$9,$2
49865		 sb    $10,0x00($24)
49866		 and   $16,$0,$0        	 # Clear Carry
49867		 and   $17,$0,$0        	 # Clear Overflow
49868		 slt   $19,$10,$0        	 # Set Sign
49869		 sltiu $18,$10,1         	 # Set Zero
49870		 addiu $15,$15,-12
49871		 bgez  $15,3f
49872		 lhu   $24,0x00($23)    	 # Delay slot
49873		 j     MainExit
49874	3:
49875		 sll   $7,$24,2         	 # Delay slot
49876		 addu  $7,$7,$30
49877		 lw    $7,0x00($7)
49878		 jr    $7
49879		 nop                    	 # Delay slot
49880
49881OP0_c039:				#:
49882		 addiu $23,$23,2
49883
49884		 srl   $24,$24,7
49885		 andi  $24,$24,0x1C
49886		 addu  $24,$24,$21
49887		 lb    $9,0x00($24)
49888		 lhu   $14,0x00($23)
49889		 lhu   $25,0x02($23)
49890		 sll   $14,$14,16
49891		 or    $14,$14,$25
49892		 addiu $23,$23,4
49893		 lw    $25,0x7C($21)
49894		 sw    $15,m68k_ICount
49895		 sw    $9,0x44($29)
49896		 sw    $24,0x40($29)
49897		 or    $4,$0,$14
49898		 jalr  $25
49899		 sw    $23,0x4C($21)    	 # Delay slot
49900		 lw    $24,0x40($29)
49901		 lw    $9,0x44($29)
49902		 lw    $15,m68k_ICount
49903		 seb   $2,$2
49904		 and   $10,$9,$2
49905		 sb    $10,0x00($24)
49906		 and   $16,$0,$0        	 # Clear Carry
49907		 and   $17,$0,$0        	 # Clear Overflow
49908		 slt   $19,$10,$0        	 # Set Sign
49909		 sltiu $18,$10,1         	 # Set Zero
49910		 addiu $15,$15,-16
49911		 bgez  $15,3f
49912		 lhu   $24,0x00($23)    	 # Delay slot
49913		 j     MainExit
49914	3:
49915		 sll   $7,$24,2         	 # Delay slot
49916		 addu  $7,$7,$30
49917		 lw    $7,0x00($7)
49918		 jr    $7
49919		 nop                    	 # Delay slot
49920
49921OP0_c03a:				#:
49922		 addiu $23,$23,2
49923
49924		 srl   $24,$24,7
49925		 andi  $24,$24,0x1C
49926		 addu  $24,$24,$21
49927		 lb    $9,0x00($24)
49928		 lh    $7,0x00($23)
49929		 subu  $25,$23,$22
49930		 addu  $14,$25,$7       	 # Add Offset to PC
49931		 addiu $23,$23,2
49932		 lw    $25,0x98($21)
49933		 sw    $15,m68k_ICount
49934		 sw    $9,0x44($29)
49935		 sw    $24,0x40($29)
49936		 or    $4,$0,$14
49937		 jalr  $25
49938		 sw    $23,0x4C($21)    	 # Delay slot
49939		 lw    $24,0x40($29)
49940		 lw    $9,0x44($29)
49941		 lw    $15,m68k_ICount
49942		 seb   $2,$2
49943		 and   $10,$9,$2
49944		 sb    $10,0x00($24)
49945		 and   $16,$0,$0        	 # Clear Carry
49946		 and   $17,$0,$0        	 # Clear Overflow
49947		 slt   $19,$10,$0        	 # Set Sign
49948		 sltiu $18,$10,1         	 # Set Zero
49949		 addiu $15,$15,-12
49950		 bgez  $15,3f
49951		 lhu   $24,0x00($23)    	 # Delay slot
49952		 j     MainExit
49953	3:
49954		 sll   $7,$24,2         	 # Delay slot
49955		 addu  $7,$7,$30
49956		 lw    $7,0x00($7)
49957		 jr    $7
49958		 nop                    	 # Delay slot
49959
49960OP0_c03b:				#:
49961		 addiu $23,$23,2
49962
49963		 srl   $24,$24,7
49964		 andi  $24,$24,0x1C
49965		 addu  $24,$24,$21
49966		 lb    $9,0x00($24)
49967		 subu  $14,$23,$22       	 # Get PC
49968		 lhu   $7,0x00($23)
49969		 addiu $23,$23,2
49970		 seb   $6,$7
49971		 or    $25,$0,$7
49972		 srl   $7,$7,12
49973		 andi  $25,$25,0x0800
49974		 sll   $7,$7,2
49975		 addu  $7,$7,$21
49976		 bne   $25,$0,0f
49977		 lw    $25,0x00($7)      	 # Delay slot
49978		 seh   $25,$25
49979	0:
49980		 addu  $25,$14,$25
49981		 addu  $14,$25,$6
49982		 lw    $25,0x98($21)
49983		 sw    $15,m68k_ICount
49984		 sw    $9,0x44($29)
49985		 sw    $24,0x40($29)
49986		 or    $4,$0,$14
49987		 jalr  $25
49988		 sw    $23,0x4C($21)    	 # Delay slot
49989		 lw    $24,0x40($29)
49990		 lw    $9,0x44($29)
49991		 lw    $15,m68k_ICount
49992		 seb   $2,$2
49993		 and   $10,$9,$2
49994		 sb    $10,0x00($24)
49995		 and   $16,$0,$0        	 # Clear Carry
49996		 and   $17,$0,$0        	 # Clear Overflow
49997		 slt   $19,$10,$0        	 # Set Sign
49998		 sltiu $18,$10,1         	 # Set Zero
49999		 addiu $15,$15,-14
50000		 bgez  $15,3f
50001		 lhu   $24,0x00($23)    	 # Delay slot
50002		 j     MainExit
50003	3:
50004		 sll   $7,$24,2         	 # Delay slot
50005		 addu  $7,$7,$30
50006		 lw    $7,0x00($7)
50007		 jr    $7
50008		 nop                    	 # Delay slot
50009
50010OP0_c03c:				#:
50011		 addiu $23,$23,2
50012
50013		 srl   $24,$24,7
50014		 andi  $24,$24,0x1C
50015		 addu  $24,$24,$21
50016		 lb    $9,0x00($24)
50017		 lb    $2,0x00($23)
50018		 addiu $23,$23,2
50019		 and   $10,$9,$2
50020		 sb    $10,0x00($24)
50021		 and   $16,$0,$0        	 # Clear Carry
50022		 and   $17,$0,$0        	 # Clear Overflow
50023		 slt   $19,$10,$0        	 # Set Sign
50024		 sltiu $18,$10,1         	 # Set Zero
50025		 addiu $15,$15,-4
50026		 bgez  $15,3f
50027		 lhu   $24,0x00($23)    	 # Delay slot
50028		 j     MainExit
50029	3:
50030		 sll   $7,$24,2         	 # Delay slot
50031		 addu  $7,$7,$30
50032		 lw    $7,0x00($7)
50033		 jr    $7
50034		 nop                    	 # Delay slot
50035
50036OP0_c040:				#:
50037		 addiu $23,$23,2
50038
50039		 andi  $8,$24,0x07
50040		 srl   $24,$24,7
50041		 andi  $24,$24,0x1C
50042		 addu  $24,$24,$21
50043		 lh    $9,0x00($24)
50044		 sll   $8,$8,2
50045		 addu  $8,$8,$21
50046		 lh    $2,0x00($8)
50047		 and   $10,$9,$2
50048		 sh    $10,0x00($24)
50049		 and   $16,$0,$0        	 # Clear Carry
50050		 and   $17,$0,$0        	 # Clear Overflow
50051		 slt   $19,$10,$0        	 # Set Sign
50052		 sltiu $18,$10,1         	 # Set Zero
50053		 addiu $15,$15,-4
50054		 bgez  $15,3f
50055		 lhu   $24,0x00($23)    	 # Delay slot
50056		 j     MainExit
50057	3:
50058		 sll   $7,$24,2         	 # Delay slot
50059		 addu  $7,$7,$30
50060		 lw    $7,0x00($7)
50061		 jr    $7
50062		 nop                    	 # Delay slot
50063
50064OP0_c050:				#:
50065		 addiu $23,$23,2
50066
50067		 andi  $8,$24,0x07
50068		 srl   $24,$24,7
50069		 andi  $24,$24,0x1C
50070		 addu  $24,$24,$21
50071		 lh    $9,0x00($24)
50072		 sll   $8,$8,2
50073		 addu  $8,$8,$21
50074		 lw    $14,0x20($8)
50075		 lw    $25,0x80($21)
50076		 sw    $15,m68k_ICount
50077		 sw    $9,0x44($29)
50078		 sw    $24,0x40($29)
50079		 or    $4,$0,$14
50080		 jalr  $25
50081		 sw    $23,0x4C($21)    	 # Delay slot
50082		 lw    $24,0x40($29)
50083		 lw    $9,0x44($29)
50084		 lw    $15,m68k_ICount
50085		 seh   $2,$2
50086		 and   $10,$9,$2
50087		 sh    $10,0x00($24)
50088		 and   $16,$0,$0        	 # Clear Carry
50089		 and   $17,$0,$0        	 # Clear Overflow
50090		 slt   $19,$10,$0        	 # Set Sign
50091		 sltiu $18,$10,1         	 # Set Zero
50092		 addiu $15,$15,-8
50093		 bgez  $15,3f
50094		 lhu   $24,0x00($23)    	 # Delay slot
50095		 j     MainExit
50096	3:
50097		 sll   $7,$24,2         	 # Delay slot
50098		 addu  $7,$7,$30
50099		 lw    $7,0x00($7)
50100		 jr    $7
50101		 nop                    	 # Delay slot
50102
50103OP0_c058:				#:
50104		 addiu $23,$23,2
50105
50106		 andi  $8,$24,0x07
50107		 srl   $24,$24,7
50108		 andi  $24,$24,0x1C
50109		 addu  $24,$24,$21
50110		 lh    $9,0x00($24)
50111		 sll   $8,$8,2
50112		 addu  $8,$8,$21
50113		 lw    $14,0x20($8)
50114		 addiu $25,$14,2
50115		 sw    $25,0x20($8)
50116		 lw    $25,0x80($21)
50117		 sw    $15,m68k_ICount
50118		 sw    $9,0x44($29)
50119		 sw    $24,0x40($29)
50120		 or    $4,$0,$14
50121		 jalr  $25
50122		 sw    $23,0x4C($21)    	 # Delay slot
50123		 lw    $24,0x40($29)
50124		 lw    $9,0x44($29)
50125		 lw    $15,m68k_ICount
50126		 seh   $2,$2
50127		 and   $10,$9,$2
50128		 sh    $10,0x00($24)
50129		 and   $16,$0,$0        	 # Clear Carry
50130		 and   $17,$0,$0        	 # Clear Overflow
50131		 slt   $19,$10,$0        	 # Set Sign
50132		 sltiu $18,$10,1         	 # Set Zero
50133		 addiu $15,$15,-8
50134		 bgez  $15,3f
50135		 lhu   $24,0x00($23)    	 # Delay slot
50136		 j     MainExit
50137	3:
50138		 sll   $7,$24,2         	 # Delay slot
50139		 addu  $7,$7,$30
50140		 lw    $7,0x00($7)
50141		 jr    $7
50142		 nop                    	 # Delay slot
50143
50144OP0_c060:				#:
50145		 addiu $23,$23,2
50146
50147		 andi  $8,$24,0x07
50148		 srl   $24,$24,7
50149		 andi  $24,$24,0x1C
50150		 addu  $24,$24,$21
50151		 lh    $9,0x00($24)
50152		 sll   $8,$8,2
50153		 addu  $8,$8,$21
50154		 lw    $14,0x20($8)
50155		 addiu $14,$14,-2
50156		 sw    $14,0x20($8)
50157		 lw    $25,0x80($21)
50158		 sw    $15,m68k_ICount
50159		 sw    $9,0x44($29)
50160		 sw    $24,0x40($29)
50161		 or    $4,$0,$14
50162		 jalr  $25
50163		 sw    $23,0x4C($21)    	 # Delay slot
50164		 lw    $24,0x40($29)
50165		 lw    $9,0x44($29)
50166		 lw    $15,m68k_ICount
50167		 seh   $2,$2
50168		 and   $10,$9,$2
50169		 sh    $10,0x00($24)
50170		 and   $16,$0,$0        	 # Clear Carry
50171		 and   $17,$0,$0        	 # Clear Overflow
50172		 slt   $19,$10,$0        	 # Set Sign
50173		 sltiu $18,$10,1         	 # Set Zero
50174		 addiu $15,$15,-10
50175		 bgez  $15,3f
50176		 lhu   $24,0x00($23)    	 # Delay slot
50177		 j     MainExit
50178	3:
50179		 sll   $7,$24,2         	 # Delay slot
50180		 addu  $7,$7,$30
50181		 lw    $7,0x00($7)
50182		 jr    $7
50183		 nop                    	 # Delay slot
50184
50185OP0_c068:				#:
50186		 addiu $23,$23,2
50187
50188		 andi  $8,$24,0x07
50189		 srl   $24,$24,7
50190		 andi  $24,$24,0x1C
50191		 addu  $24,$24,$21
50192		 lh    $9,0x00($24)
50193		 lh    $7,0x00($23)
50194		 sll   $8,$8,2
50195		 addu  $8,$8,$21
50196		 lw    $14,0x20($8)
50197		 addiu $23,$23,2
50198		 addu  $14,$14,$7
50199		 lw    $25,0x80($21)
50200		 sw    $15,m68k_ICount
50201		 sw    $9,0x44($29)
50202		 sw    $24,0x40($29)
50203		 or    $4,$0,$14
50204		 jalr  $25
50205		 sw    $23,0x4C($21)    	 # Delay slot
50206		 lw    $24,0x40($29)
50207		 lw    $9,0x44($29)
50208		 lw    $15,m68k_ICount
50209		 seh   $2,$2
50210		 and   $10,$9,$2
50211		 sh    $10,0x00($24)
50212		 and   $16,$0,$0        	 # Clear Carry
50213		 and   $17,$0,$0        	 # Clear Overflow
50214		 slt   $19,$10,$0        	 # Set Sign
50215		 sltiu $18,$10,1         	 # Set Zero
50216		 addiu $15,$15,-12
50217		 bgez  $15,3f
50218		 lhu   $24,0x00($23)    	 # Delay slot
50219		 j     MainExit
50220	3:
50221		 sll   $7,$24,2         	 # Delay slot
50222		 addu  $7,$7,$30
50223		 lw    $7,0x00($7)
50224		 jr    $7
50225		 nop                    	 # Delay slot
50226
50227OP0_c070:				#:
50228		 addiu $23,$23,2
50229
50230		 andi  $8,$24,0x07
50231		 srl   $24,$24,7
50232		 andi  $24,$24,0x1C
50233		 addu  $24,$24,$21
50234		 lh    $9,0x00($24)
50235		 sll   $8,$8,2
50236		 addu  $8,$8,$21
50237		 lw    $14,0x20($8)
50238		 lhu   $7,0x00($23)
50239		 addiu $23,$23,2
50240		 seb   $6,$7
50241		 or    $25,$0,$7
50242		 srl   $7,$7,12
50243		 andi  $25,$25,0x0800
50244		 sll   $7,$7,2
50245		 addu  $7,$7,$21
50246		 bne   $25,$0,0f
50247		 lw    $25,0x00($7)      	 # Delay slot
50248		 seh   $25,$25
50249	0:
50250		 addu  $25,$14,$25
50251		 addu  $14,$25,$6
50252		 lw    $25,0x80($21)
50253		 sw    $15,m68k_ICount
50254		 sw    $9,0x44($29)
50255		 sw    $24,0x40($29)
50256		 or    $4,$0,$14
50257		 jalr  $25
50258		 sw    $23,0x4C($21)    	 # Delay slot
50259		 lw    $24,0x40($29)
50260		 lw    $9,0x44($29)
50261		 lw    $15,m68k_ICount
50262		 seh   $2,$2
50263		 and   $10,$9,$2
50264		 sh    $10,0x00($24)
50265		 and   $16,$0,$0        	 # Clear Carry
50266		 and   $17,$0,$0        	 # Clear Overflow
50267		 slt   $19,$10,$0        	 # Set Sign
50268		 sltiu $18,$10,1         	 # Set Zero
50269		 addiu $15,$15,-14
50270		 bgez  $15,3f
50271		 lhu   $24,0x00($23)    	 # Delay slot
50272		 j     MainExit
50273	3:
50274		 sll   $7,$24,2         	 # Delay slot
50275		 addu  $7,$7,$30
50276		 lw    $7,0x00($7)
50277		 jr    $7
50278		 nop                    	 # Delay slot
50279
50280OP0_c078:				#:
50281		 addiu $23,$23,2
50282
50283		 srl   $24,$24,7
50284		 andi  $24,$24,0x1C
50285		 addu  $24,$24,$21
50286		 lh    $9,0x00($24)
50287		 lh    $14,0x00($23)
50288		 addiu $23,$23,2
50289		 lw    $25,0x80($21)
50290		 sw    $15,m68k_ICount
50291		 sw    $9,0x44($29)
50292		 sw    $24,0x40($29)
50293		 or    $4,$0,$14
50294		 jalr  $25
50295		 sw    $23,0x4C($21)    	 # Delay slot
50296		 lw    $24,0x40($29)
50297		 lw    $9,0x44($29)
50298		 lw    $15,m68k_ICount
50299		 seh   $2,$2
50300		 and   $10,$9,$2
50301		 sh    $10,0x00($24)
50302		 and   $16,$0,$0        	 # Clear Carry
50303		 and   $17,$0,$0        	 # Clear Overflow
50304		 slt   $19,$10,$0        	 # Set Sign
50305		 sltiu $18,$10,1         	 # Set Zero
50306		 addiu $15,$15,-12
50307		 bgez  $15,3f
50308		 lhu   $24,0x00($23)    	 # Delay slot
50309		 j     MainExit
50310	3:
50311		 sll   $7,$24,2         	 # Delay slot
50312		 addu  $7,$7,$30
50313		 lw    $7,0x00($7)
50314		 jr    $7
50315		 nop                    	 # Delay slot
50316
50317OP0_c079:				#:
50318		 addiu $23,$23,2
50319
50320		 srl   $24,$24,7
50321		 andi  $24,$24,0x1C
50322		 addu  $24,$24,$21
50323		 lh    $9,0x00($24)
50324		 lhu   $14,0x00($23)
50325		 lhu   $25,0x02($23)
50326		 sll   $14,$14,16
50327		 or    $14,$14,$25
50328		 addiu $23,$23,4
50329		 lw    $25,0x80($21)
50330		 sw    $15,m68k_ICount
50331		 sw    $9,0x44($29)
50332		 sw    $24,0x40($29)
50333		 or    $4,$0,$14
50334		 jalr  $25
50335		 sw    $23,0x4C($21)    	 # Delay slot
50336		 lw    $24,0x40($29)
50337		 lw    $9,0x44($29)
50338		 lw    $15,m68k_ICount
50339		 seh   $2,$2
50340		 and   $10,$9,$2
50341		 sh    $10,0x00($24)
50342		 and   $16,$0,$0        	 # Clear Carry
50343		 and   $17,$0,$0        	 # Clear Overflow
50344		 slt   $19,$10,$0        	 # Set Sign
50345		 sltiu $18,$10,1         	 # Set Zero
50346		 addiu $15,$15,-16
50347		 bgez  $15,3f
50348		 lhu   $24,0x00($23)    	 # Delay slot
50349		 j     MainExit
50350	3:
50351		 sll   $7,$24,2         	 # Delay slot
50352		 addu  $7,$7,$30
50353		 lw    $7,0x00($7)
50354		 jr    $7
50355		 nop                    	 # Delay slot
50356
50357OP0_c07a:				#:
50358		 addiu $23,$23,2
50359
50360		 srl   $24,$24,7
50361		 andi  $24,$24,0x1C
50362		 addu  $24,$24,$21
50363		 lh    $9,0x00($24)
50364		 lh    $7,0x00($23)
50365		 subu  $25,$23,$22
50366		 addu  $14,$25,$7       	 # Add Offset to PC
50367		 addiu $23,$23,2
50368		 lw    $25,0x9C($21)
50369		 sw    $15,m68k_ICount
50370		 sw    $9,0x44($29)
50371		 sw    $24,0x40($29)
50372		 or    $4,$0,$14
50373		 jalr  $25
50374		 sw    $23,0x4C($21)    	 # Delay slot
50375		 lw    $24,0x40($29)
50376		 lw    $9,0x44($29)
50377		 lw    $15,m68k_ICount
50378		 seh   $2,$2
50379		 and   $10,$9,$2
50380		 sh    $10,0x00($24)
50381		 and   $16,$0,$0        	 # Clear Carry
50382		 and   $17,$0,$0        	 # Clear Overflow
50383		 slt   $19,$10,$0        	 # Set Sign
50384		 sltiu $18,$10,1         	 # Set Zero
50385		 addiu $15,$15,-12
50386		 bgez  $15,3f
50387		 lhu   $24,0x00($23)    	 # Delay slot
50388		 j     MainExit
50389	3:
50390		 sll   $7,$24,2         	 # Delay slot
50391		 addu  $7,$7,$30
50392		 lw    $7,0x00($7)
50393		 jr    $7
50394		 nop                    	 # Delay slot
50395
50396OP0_c07b:				#:
50397		 addiu $23,$23,2
50398
50399		 srl   $24,$24,7
50400		 andi  $24,$24,0x1C
50401		 addu  $24,$24,$21
50402		 lh    $9,0x00($24)
50403		 subu  $14,$23,$22       	 # Get PC
50404		 lhu   $7,0x00($23)
50405		 addiu $23,$23,2
50406		 seb   $6,$7
50407		 or    $25,$0,$7
50408		 srl   $7,$7,12
50409		 andi  $25,$25,0x0800
50410		 sll   $7,$7,2
50411		 addu  $7,$7,$21
50412		 bne   $25,$0,0f
50413		 lw    $25,0x00($7)      	 # Delay slot
50414		 seh   $25,$25
50415	0:
50416		 addu  $25,$14,$25
50417		 addu  $14,$25,$6
50418		 lw    $25,0x9C($21)
50419		 sw    $15,m68k_ICount
50420		 sw    $9,0x44($29)
50421		 sw    $24,0x40($29)
50422		 or    $4,$0,$14
50423		 jalr  $25
50424		 sw    $23,0x4C($21)    	 # Delay slot
50425		 lw    $24,0x40($29)
50426		 lw    $9,0x44($29)
50427		 lw    $15,m68k_ICount
50428		 seh   $2,$2
50429		 and   $10,$9,$2
50430		 sh    $10,0x00($24)
50431		 and   $16,$0,$0        	 # Clear Carry
50432		 and   $17,$0,$0        	 # Clear Overflow
50433		 slt   $19,$10,$0        	 # Set Sign
50434		 sltiu $18,$10,1         	 # Set Zero
50435		 addiu $15,$15,-14
50436		 bgez  $15,3f
50437		 lhu   $24,0x00($23)    	 # Delay slot
50438		 j     MainExit
50439	3:
50440		 sll   $7,$24,2         	 # Delay slot
50441		 addu  $7,$7,$30
50442		 lw    $7,0x00($7)
50443		 jr    $7
50444		 nop                    	 # Delay slot
50445
50446OP0_c07c:				#:
50447		 addiu $23,$23,2
50448
50449		 srl   $24,$24,7
50450		 andi  $24,$24,0x1C
50451		 addu  $24,$24,$21
50452		 lh    $9,0x00($24)
50453		 lh    $2,0x00($23)
50454		 addiu $23,$23,2
50455		 and   $10,$9,$2
50456		 sh    $10,0x00($24)
50457		 and   $16,$0,$0        	 # Clear Carry
50458		 and   $17,$0,$0        	 # Clear Overflow
50459		 slt   $19,$10,$0        	 # Set Sign
50460		 sltiu $18,$10,1         	 # Set Zero
50461		 addiu $15,$15,-4
50462		 bgez  $15,3f
50463		 lhu   $24,0x00($23)    	 # Delay slot
50464		 j     MainExit
50465	3:
50466		 sll   $7,$24,2         	 # Delay slot
50467		 addu  $7,$7,$30
50468		 lw    $7,0x00($7)
50469		 jr    $7
50470		 nop                    	 # Delay slot
50471
50472OP0_c080:				#:
50473		 addiu $23,$23,2
50474
50475		 andi  $8,$24,0x07
50476		 srl   $24,$24,7
50477		 andi  $24,$24,0x1C
50478		 addu  $24,$24,$21
50479		 lw    $9,0x00($24)
50480		 sll   $8,$8,2
50481		 addu  $8,$8,$21
50482		 lw    $2,0x00($8)
50483		 and   $10,$9,$2
50484		 sw    $10,0x00($24)
50485		 and   $16,$0,$0        	 # Clear Carry
50486		 and   $17,$0,$0        	 # Clear Overflow
50487		 slt   $19,$10,$0        	 # Set Sign
50488		 sltiu $18,$10,1         	 # Set Zero
50489		 addiu $15,$15,-8
50490		 bgez  $15,3f
50491		 lhu   $24,0x00($23)    	 # Delay slot
50492		 j     MainExit
50493	3:
50494		 sll   $7,$24,2         	 # Delay slot
50495		 addu  $7,$7,$30
50496		 lw    $7,0x00($7)
50497		 jr    $7
50498		 nop                    	 # Delay slot
50499
50500OP0_c090:				#:
50501		 addiu $23,$23,2
50502
50503		 andi  $8,$24,0x07
50504		 srl   $24,$24,7
50505		 andi  $24,$24,0x1C
50506		 addu  $24,$24,$21
50507		 lw    $9,0x00($24)
50508		 sll   $8,$8,2
50509		 addu  $8,$8,$21
50510		 lw    $14,0x20($8)
50511		 lw    $25,0x84($21)
50512		 sw    $15,m68k_ICount
50513		 sw    $9,0x44($29)
50514		 sw    $24,0x40($29)
50515		 or    $4,$0,$14
50516		 jalr  $25
50517		 sw    $23,0x4C($21)    	 # Delay slot
50518		 lw    $24,0x40($29)
50519		 lw    $9,0x44($29)
50520		 lw    $15,m68k_ICount
50521		 and   $10,$9,$2
50522		 sw    $10,0x00($24)
50523		 and   $16,$0,$0        	 # Clear Carry
50524		 and   $17,$0,$0        	 # Clear Overflow
50525		 slt   $19,$10,$0        	 # Set Sign
50526		 sltiu $18,$10,1         	 # Set Zero
50527		 addiu $15,$15,-14
50528		 bgez  $15,3f
50529		 lhu   $24,0x00($23)    	 # Delay slot
50530		 j     MainExit
50531	3:
50532		 sll   $7,$24,2         	 # Delay slot
50533		 addu  $7,$7,$30
50534		 lw    $7,0x00($7)
50535		 jr    $7
50536		 nop                    	 # Delay slot
50537
50538OP0_c098:				#:
50539		 addiu $23,$23,2
50540
50541		 andi  $8,$24,0x07
50542		 srl   $24,$24,7
50543		 andi  $24,$24,0x1C
50544		 addu  $24,$24,$21
50545		 lw    $9,0x00($24)
50546		 sll   $8,$8,2
50547		 addu  $8,$8,$21
50548		 lw    $14,0x20($8)
50549		 addiu $25,$14,4
50550		 sw    $25,0x20($8)
50551		 lw    $25,0x84($21)
50552		 sw    $15,m68k_ICount
50553		 sw    $9,0x44($29)
50554		 sw    $24,0x40($29)
50555		 or    $4,$0,$14
50556		 jalr  $25
50557		 sw    $23,0x4C($21)    	 # Delay slot
50558		 lw    $24,0x40($29)
50559		 lw    $9,0x44($29)
50560		 lw    $15,m68k_ICount
50561		 and   $10,$9,$2
50562		 sw    $10,0x00($24)
50563		 and   $16,$0,$0        	 # Clear Carry
50564		 and   $17,$0,$0        	 # Clear Overflow
50565		 slt   $19,$10,$0        	 # Set Sign
50566		 sltiu $18,$10,1         	 # Set Zero
50567		 addiu $15,$15,-14
50568		 bgez  $15,3f
50569		 lhu   $24,0x00($23)    	 # Delay slot
50570		 j     MainExit
50571	3:
50572		 sll   $7,$24,2         	 # Delay slot
50573		 addu  $7,$7,$30
50574		 lw    $7,0x00($7)
50575		 jr    $7
50576		 nop                    	 # Delay slot
50577
50578OP0_c0a0:				#:
50579		 addiu $23,$23,2
50580
50581		 andi  $8,$24,0x07
50582		 srl   $24,$24,7
50583		 andi  $24,$24,0x1C
50584		 addu  $24,$24,$21
50585		 lw    $9,0x00($24)
50586		 sll   $8,$8,2
50587		 addu  $8,$8,$21
50588		 lw    $14,0x20($8)
50589		 addiu $14,$14,-4
50590		 sw    $14,0x20($8)
50591		 lw    $25,0x84($21)
50592		 sw    $15,m68k_ICount
50593		 sw    $9,0x44($29)
50594		 sw    $24,0x40($29)
50595		 or    $4,$0,$14
50596		 jalr  $25
50597		 sw    $23,0x4C($21)    	 # Delay slot
50598		 lw    $24,0x40($29)
50599		 lw    $9,0x44($29)
50600		 lw    $15,m68k_ICount
50601		 and   $10,$9,$2
50602		 sw    $10,0x00($24)
50603		 and   $16,$0,$0        	 # Clear Carry
50604		 and   $17,$0,$0        	 # Clear Overflow
50605		 slt   $19,$10,$0        	 # Set Sign
50606		 sltiu $18,$10,1         	 # Set Zero
50607		 addiu $15,$15,-16
50608		 bgez  $15,3f
50609		 lhu   $24,0x00($23)    	 # Delay slot
50610		 j     MainExit
50611	3:
50612		 sll   $7,$24,2         	 # Delay slot
50613		 addu  $7,$7,$30
50614		 lw    $7,0x00($7)
50615		 jr    $7
50616		 nop                    	 # Delay slot
50617
50618OP0_c0a8:				#:
50619		 addiu $23,$23,2
50620
50621		 andi  $8,$24,0x07
50622		 srl   $24,$24,7
50623		 andi  $24,$24,0x1C
50624		 addu  $24,$24,$21
50625		 lw    $9,0x00($24)
50626		 lh    $7,0x00($23)
50627		 sll   $8,$8,2
50628		 addu  $8,$8,$21
50629		 lw    $14,0x20($8)
50630		 addiu $23,$23,2
50631		 addu  $14,$14,$7
50632		 lw    $25,0x84($21)
50633		 sw    $15,m68k_ICount
50634		 sw    $9,0x44($29)
50635		 sw    $24,0x40($29)
50636		 or    $4,$0,$14
50637		 jalr  $25
50638		 sw    $23,0x4C($21)    	 # Delay slot
50639		 lw    $24,0x40($29)
50640		 lw    $9,0x44($29)
50641		 lw    $15,m68k_ICount
50642		 and   $10,$9,$2
50643		 sw    $10,0x00($24)
50644		 and   $16,$0,$0        	 # Clear Carry
50645		 and   $17,$0,$0        	 # Clear Overflow
50646		 slt   $19,$10,$0        	 # Set Sign
50647		 sltiu $18,$10,1         	 # Set Zero
50648		 addiu $15,$15,-18
50649		 bgez  $15,3f
50650		 lhu   $24,0x00($23)    	 # Delay slot
50651		 j     MainExit
50652	3:
50653		 sll   $7,$24,2         	 # Delay slot
50654		 addu  $7,$7,$30
50655		 lw    $7,0x00($7)
50656		 jr    $7
50657		 nop                    	 # Delay slot
50658
50659OP0_c0b0:				#:
50660		 addiu $23,$23,2
50661
50662		 andi  $8,$24,0x07
50663		 srl   $24,$24,7
50664		 andi  $24,$24,0x1C
50665		 addu  $24,$24,$21
50666		 lw    $9,0x00($24)
50667		 sll   $8,$8,2
50668		 addu  $8,$8,$21
50669		 lw    $14,0x20($8)
50670		 lhu   $7,0x00($23)
50671		 addiu $23,$23,2
50672		 seb   $6,$7
50673		 or    $25,$0,$7
50674		 srl   $7,$7,12
50675		 andi  $25,$25,0x0800
50676		 sll   $7,$7,2
50677		 addu  $7,$7,$21
50678		 bne   $25,$0,0f
50679		 lw    $25,0x00($7)      	 # Delay slot
50680		 seh   $25,$25
50681	0:
50682		 addu  $25,$14,$25
50683		 addu  $14,$25,$6
50684		 lw    $25,0x84($21)
50685		 sw    $15,m68k_ICount
50686		 sw    $9,0x44($29)
50687		 sw    $24,0x40($29)
50688		 or    $4,$0,$14
50689		 jalr  $25
50690		 sw    $23,0x4C($21)    	 # Delay slot
50691		 lw    $24,0x40($29)
50692		 lw    $9,0x44($29)
50693		 lw    $15,m68k_ICount
50694		 and   $10,$9,$2
50695		 sw    $10,0x00($24)
50696		 and   $16,$0,$0        	 # Clear Carry
50697		 and   $17,$0,$0        	 # Clear Overflow
50698		 slt   $19,$10,$0        	 # Set Sign
50699		 sltiu $18,$10,1         	 # Set Zero
50700		 addiu $15,$15,-20
50701		 bgez  $15,3f
50702		 lhu   $24,0x00($23)    	 # Delay slot
50703		 j     MainExit
50704	3:
50705		 sll   $7,$24,2         	 # Delay slot
50706		 addu  $7,$7,$30
50707		 lw    $7,0x00($7)
50708		 jr    $7
50709		 nop                    	 # Delay slot
50710
50711OP0_c0b8:				#:
50712		 addiu $23,$23,2
50713
50714		 srl   $24,$24,7
50715		 andi  $24,$24,0x1C
50716		 addu  $24,$24,$21
50717		 lw    $9,0x00($24)
50718		 lh    $14,0x00($23)
50719		 addiu $23,$23,2
50720		 lw    $25,0x84($21)
50721		 sw    $15,m68k_ICount
50722		 sw    $9,0x44($29)
50723		 sw    $24,0x40($29)
50724		 or    $4,$0,$14
50725		 jalr  $25
50726		 sw    $23,0x4C($21)    	 # Delay slot
50727		 lw    $24,0x40($29)
50728		 lw    $9,0x44($29)
50729		 lw    $15,m68k_ICount
50730		 and   $10,$9,$2
50731		 sw    $10,0x00($24)
50732		 and   $16,$0,$0        	 # Clear Carry
50733		 and   $17,$0,$0        	 # Clear Overflow
50734		 slt   $19,$10,$0        	 # Set Sign
50735		 sltiu $18,$10,1         	 # Set Zero
50736		 addiu $15,$15,-18
50737		 bgez  $15,3f
50738		 lhu   $24,0x00($23)    	 # Delay slot
50739		 j     MainExit
50740	3:
50741		 sll   $7,$24,2         	 # Delay slot
50742		 addu  $7,$7,$30
50743		 lw    $7,0x00($7)
50744		 jr    $7
50745		 nop                    	 # Delay slot
50746
50747OP0_c0b9:				#:
50748		 addiu $23,$23,2
50749
50750		 srl   $24,$24,7
50751		 andi  $24,$24,0x1C
50752		 addu  $24,$24,$21
50753		 lw    $9,0x00($24)
50754		 lhu   $14,0x00($23)
50755		 lhu   $25,0x02($23)
50756		 sll   $14,$14,16
50757		 or    $14,$14,$25
50758		 addiu $23,$23,4
50759		 lw    $25,0x84($21)
50760		 sw    $15,m68k_ICount
50761		 sw    $9,0x44($29)
50762		 sw    $24,0x40($29)
50763		 or    $4,$0,$14
50764		 jalr  $25
50765		 sw    $23,0x4C($21)    	 # Delay slot
50766		 lw    $24,0x40($29)
50767		 lw    $9,0x44($29)
50768		 lw    $15,m68k_ICount
50769		 and   $10,$9,$2
50770		 sw    $10,0x00($24)
50771		 and   $16,$0,$0        	 # Clear Carry
50772		 and   $17,$0,$0        	 # Clear Overflow
50773		 slt   $19,$10,$0        	 # Set Sign
50774		 sltiu $18,$10,1         	 # Set Zero
50775		 addiu $15,$15,-22
50776		 bgez  $15,3f
50777		 lhu   $24,0x00($23)    	 # Delay slot
50778		 j     MainExit
50779	3:
50780		 sll   $7,$24,2         	 # Delay slot
50781		 addu  $7,$7,$30
50782		 lw    $7,0x00($7)
50783		 jr    $7
50784		 nop                    	 # Delay slot
50785
50786OP0_c0ba:				#:
50787		 addiu $23,$23,2
50788
50789		 srl   $24,$24,7
50790		 andi  $24,$24,0x1C
50791		 addu  $24,$24,$21
50792		 lw    $9,0x00($24)
50793		 lh    $7,0x00($23)
50794		 subu  $25,$23,$22
50795		 addu  $14,$25,$7       	 # Add Offset to PC
50796		 addiu $23,$23,2
50797		 lw    $25,0xA0($21)
50798		 sw    $15,m68k_ICount
50799		 sw    $9,0x44($29)
50800		 sw    $24,0x40($29)
50801		 or    $4,$0,$14
50802		 jalr  $25
50803		 sw    $23,0x4C($21)    	 # Delay slot
50804		 lw    $24,0x40($29)
50805		 lw    $9,0x44($29)
50806		 lw    $15,m68k_ICount
50807		 and   $10,$9,$2
50808		 sw    $10,0x00($24)
50809		 and   $16,$0,$0        	 # Clear Carry
50810		 and   $17,$0,$0        	 # Clear Overflow
50811		 slt   $19,$10,$0        	 # Set Sign
50812		 sltiu $18,$10,1         	 # Set Zero
50813		 addiu $15,$15,-18
50814		 bgez  $15,3f
50815		 lhu   $24,0x00($23)    	 # Delay slot
50816		 j     MainExit
50817	3:
50818		 sll   $7,$24,2         	 # Delay slot
50819		 addu  $7,$7,$30
50820		 lw    $7,0x00($7)
50821		 jr    $7
50822		 nop                    	 # Delay slot
50823
50824OP0_c0bb:				#:
50825		 addiu $23,$23,2
50826
50827		 srl   $24,$24,7
50828		 andi  $24,$24,0x1C
50829		 addu  $24,$24,$21
50830		 lw    $9,0x00($24)
50831		 subu  $14,$23,$22       	 # Get PC
50832		 lhu   $7,0x00($23)
50833		 addiu $23,$23,2
50834		 seb   $6,$7
50835		 or    $25,$0,$7
50836		 srl   $7,$7,12
50837		 andi  $25,$25,0x0800
50838		 sll   $7,$7,2
50839		 addu  $7,$7,$21
50840		 bne   $25,$0,0f
50841		 lw    $25,0x00($7)      	 # Delay slot
50842		 seh   $25,$25
50843	0:
50844		 addu  $25,$14,$25
50845		 addu  $14,$25,$6
50846		 lw    $25,0xA0($21)
50847		 sw    $15,m68k_ICount
50848		 sw    $9,0x44($29)
50849		 sw    $24,0x40($29)
50850		 or    $4,$0,$14
50851		 jalr  $25
50852		 sw    $23,0x4C($21)    	 # Delay slot
50853		 lw    $24,0x40($29)
50854		 lw    $9,0x44($29)
50855		 lw    $15,m68k_ICount
50856		 and   $10,$9,$2
50857		 sw    $10,0x00($24)
50858		 and   $16,$0,$0        	 # Clear Carry
50859		 and   $17,$0,$0        	 # Clear Overflow
50860		 slt   $19,$10,$0        	 # Set Sign
50861		 sltiu $18,$10,1         	 # Set Zero
50862		 addiu $15,$15,-20
50863		 bgez  $15,3f
50864		 lhu   $24,0x00($23)    	 # Delay slot
50865		 j     MainExit
50866	3:
50867		 sll   $7,$24,2         	 # Delay slot
50868		 addu  $7,$7,$30
50869		 lw    $7,0x00($7)
50870		 jr    $7
50871		 nop                    	 # Delay slot
50872
50873OP0_c0bc:				#:
50874		 addiu $23,$23,2
50875
50876		 srl   $24,$24,7
50877		 andi  $24,$24,0x1C
50878		 addu  $24,$24,$21
50879		 lw    $9,0x00($24)
50880		 lhu   $2,0x00($23)
50881		 lhu   $25,0x02($23)
50882		 sll   $2,$2,16
50883		 or    $2,$2,$25
50884		 addiu $23,$23,4
50885		 and   $10,$9,$2
50886		 sw    $10,0x00($24)
50887		 and   $16,$0,$0        	 # Clear Carry
50888		 and   $17,$0,$0        	 # Clear Overflow
50889		 slt   $19,$10,$0        	 # Set Sign
50890		 sltiu $18,$10,1         	 # Set Zero
50891		 addiu $15,$15,-6
50892		 bgez  $15,3f
50893		 lhu   $24,0x00($23)    	 # Delay slot
50894		 j     MainExit
50895	3:
50896		 sll   $7,$24,2         	 # Delay slot
50897		 addu  $7,$7,$30
50898		 lw    $7,0x00($7)
50899		 jr    $7
50900		 nop                    	 # Delay slot
50901
50902OP0_c110:				#:
50903		 addiu $23,$23,2
50904
50905		 andi  $8,$24,0x07
50906		 srl   $24,$24,7
50907		 andi  $24,$24,0x1C
50908		 addu  $24,$24,$21
50909		 lb    $9,0x00($24)
50910		 sll   $8,$8,2
50911		 addu  $8,$8,$21
50912		 lw    $14,0x20($8)
50913		 lw    $25,0x7C($21)
50914		 sw    $15,m68k_ICount
50915		 sw    $9,0x44($29)
50916		 sw    $14,0x40($29)
50917		 sw    $24,0x3C($29)
50918		 or    $4,$0,$14
50919		 jalr  $25
50920		 sw    $23,0x4C($21)    	 # Delay slot
50921		 lw    $24,0x3C($29)
50922		 lw    $14,0x40($29)
50923		 lw    $9,0x44($29)
50924		 lw    $15,m68k_ICount
50925		 seb   $10,$2
50926		 and   $2,$10,$9
50927		 and   $16,$0,$0        	 # Clear Carry
50928		 and   $17,$0,$0        	 # Clear Overflow
50929		 slt   $19,$2,$0        	 # Set Sign
50930		 sltiu $18,$2,1         	 # Set Zero
50931		 lw    $25,0x88($21)
50932		 sw    $15,m68k_ICount
50933		 sw    $9,0x44($29)
50934		 sw    $14,0x40($29)
50935		 sw    $24,0x3C($29)
50936		 or    $5,$0,$2
50937		 or    $4,$0,$14
50938		 jalr  $25
50939		 sw    $23,0x4C($21)    	 # Delay slot
50940		 lw    $24,0x3C($29)
50941		 lw    $14,0x40($29)
50942		 lw    $9,0x44($29)
50943		 lw    $15,m68k_ICount
50944		 addiu $15,$15,-12
50945		 bgez  $15,3f
50946		 lhu   $24,0x00($23)    	 # Delay slot
50947		 j     MainExit
50948	3:
50949		 sll   $7,$24,2         	 # Delay slot
50950		 addu  $7,$7,$30
50951		 lw    $7,0x00($7)
50952		 jr    $7
50953		 nop                    	 # Delay slot
50954
50955OP0_c118:				#:
50956		 addiu $23,$23,2
50957
50958		 andi  $8,$24,0x07
50959		 srl   $24,$24,7
50960		 andi  $24,$24,0x1C
50961		 addu  $24,$24,$21
50962		 lb    $9,0x00($24)
50963		 sll   $8,$8,2
50964		 addu  $8,$8,$21
50965		 lw    $14,0x20($8)
50966		 addiu $25,$14,1
50967		 sw    $25,0x20($8)
50968		 lw    $25,0x7C($21)
50969		 sw    $15,m68k_ICount
50970		 sw    $9,0x44($29)
50971		 sw    $14,0x40($29)
50972		 sw    $24,0x3C($29)
50973		 or    $4,$0,$14
50974		 jalr  $25
50975		 sw    $23,0x4C($21)    	 # Delay slot
50976		 lw    $24,0x3C($29)
50977		 lw    $14,0x40($29)
50978		 lw    $9,0x44($29)
50979		 lw    $15,m68k_ICount
50980		 seb   $10,$2
50981		 and   $2,$10,$9
50982		 and   $16,$0,$0        	 # Clear Carry
50983		 and   $17,$0,$0        	 # Clear Overflow
50984		 slt   $19,$2,$0        	 # Set Sign
50985		 sltiu $18,$2,1         	 # Set Zero
50986		 lw    $25,0x88($21)
50987		 sw    $15,m68k_ICount
50988		 sw    $9,0x44($29)
50989		 sw    $14,0x40($29)
50990		 sw    $24,0x3C($29)
50991		 or    $5,$0,$2
50992		 or    $4,$0,$14
50993		 jalr  $25
50994		 sw    $23,0x4C($21)    	 # Delay slot
50995		 lw    $24,0x3C($29)
50996		 lw    $14,0x40($29)
50997		 lw    $9,0x44($29)
50998		 lw    $15,m68k_ICount
50999		 addiu $15,$15,-12
51000		 bgez  $15,3f
51001		 lhu   $24,0x00($23)    	 # Delay slot
51002		 j     MainExit
51003	3:
51004		 sll   $7,$24,2         	 # Delay slot
51005		 addu  $7,$7,$30
51006		 lw    $7,0x00($7)
51007		 jr    $7
51008		 nop                    	 # Delay slot
51009
51010OP0_c11f:				#:
51011		 addiu $23,$23,2
51012
51013		 srl   $24,$24,7
51014		 andi  $24,$24,0x1C
51015		 addu  $24,$24,$21
51016		 lb    $9,0x00($24)
51017		 lw    $14,0x3C($21)    	 # Get A7
51018		 addiu $25,$14,2
51019		 sw    $25,0x3C($21)
51020		 lw    $25,0x7C($21)
51021		 sw    $15,m68k_ICount
51022		 sw    $9,0x44($29)
51023		 sw    $14,0x40($29)
51024		 sw    $24,0x3C($29)
51025		 or    $4,$0,$14
51026		 jalr  $25
51027		 sw    $23,0x4C($21)    	 # Delay slot
51028		 lw    $24,0x3C($29)
51029		 lw    $14,0x40($29)
51030		 lw    $9,0x44($29)
51031		 lw    $15,m68k_ICount
51032		 seb   $10,$2
51033		 and   $2,$10,$9
51034		 and   $16,$0,$0        	 # Clear Carry
51035		 and   $17,$0,$0        	 # Clear Overflow
51036		 slt   $19,$2,$0        	 # Set Sign
51037		 sltiu $18,$2,1         	 # Set Zero
51038		 lw    $25,0x88($21)
51039		 sw    $15,m68k_ICount
51040		 sw    $9,0x44($29)
51041		 sw    $14,0x40($29)
51042		 sw    $24,0x3C($29)
51043		 or    $5,$0,$2
51044		 or    $4,$0,$14
51045		 jalr  $25
51046		 sw    $23,0x4C($21)    	 # Delay slot
51047		 lw    $24,0x3C($29)
51048		 lw    $14,0x40($29)
51049		 lw    $9,0x44($29)
51050		 lw    $15,m68k_ICount
51051		 addiu $15,$15,-12
51052		 bgez  $15,3f
51053		 lhu   $24,0x00($23)    	 # Delay slot
51054		 j     MainExit
51055	3:
51056		 sll   $7,$24,2         	 # Delay slot
51057		 addu  $7,$7,$30
51058		 lw    $7,0x00($7)
51059		 jr    $7
51060		 nop                    	 # Delay slot
51061
51062OP0_c120:				#:
51063		 addiu $23,$23,2
51064
51065		 andi  $8,$24,0x07
51066		 srl   $24,$24,7
51067		 andi  $24,$24,0x1C
51068		 addu  $24,$24,$21
51069		 lb    $9,0x00($24)
51070		 sll   $8,$8,2
51071		 addu  $8,$8,$21
51072		 lw    $14,0x20($8)
51073		 addiu $14,$14,-1
51074		 sw    $14,0x20($8)
51075		 lw    $25,0x7C($21)
51076		 sw    $15,m68k_ICount
51077		 sw    $9,0x44($29)
51078		 sw    $14,0x40($29)
51079		 sw    $24,0x3C($29)
51080		 or    $4,$0,$14
51081		 jalr  $25
51082		 sw    $23,0x4C($21)    	 # Delay slot
51083		 lw    $24,0x3C($29)
51084		 lw    $14,0x40($29)
51085		 lw    $9,0x44($29)
51086		 lw    $15,m68k_ICount
51087		 seb   $10,$2
51088		 and   $2,$10,$9
51089		 and   $16,$0,$0        	 # Clear Carry
51090		 and   $17,$0,$0        	 # Clear Overflow
51091		 slt   $19,$2,$0        	 # Set Sign
51092		 sltiu $18,$2,1         	 # Set Zero
51093		 lw    $25,0x88($21)
51094		 sw    $15,m68k_ICount
51095		 sw    $9,0x44($29)
51096		 sw    $14,0x40($29)
51097		 sw    $24,0x3C($29)
51098		 or    $5,$0,$2
51099		 or    $4,$0,$14
51100		 jalr  $25
51101		 sw    $23,0x4C($21)    	 # Delay slot
51102		 lw    $24,0x3C($29)
51103		 lw    $14,0x40($29)
51104		 lw    $9,0x44($29)
51105		 lw    $15,m68k_ICount
51106		 addiu $15,$15,-14
51107		 bgez  $15,3f
51108		 lhu   $24,0x00($23)    	 # Delay slot
51109		 j     MainExit
51110	3:
51111		 sll   $7,$24,2         	 # Delay slot
51112		 addu  $7,$7,$30
51113		 lw    $7,0x00($7)
51114		 jr    $7
51115		 nop                    	 # Delay slot
51116
51117OP0_c127:				#:
51118		 addiu $23,$23,2
51119
51120		 srl   $24,$24,7
51121		 andi  $24,$24,0x1C
51122		 addu  $24,$24,$21
51123		 lb    $9,0x00($24)
51124		 lw    $14,0x3C($21)    	 # Get A7
51125		 addiu $14,$14,-2
51126		 sw    $14,0x3C($21)
51127		 lw    $25,0x7C($21)
51128		 sw    $15,m68k_ICount
51129		 sw    $9,0x44($29)
51130		 sw    $14,0x40($29)
51131		 sw    $24,0x3C($29)
51132		 or    $4,$0,$14
51133		 jalr  $25
51134		 sw    $23,0x4C($21)    	 # Delay slot
51135		 lw    $24,0x3C($29)
51136		 lw    $14,0x40($29)
51137		 lw    $9,0x44($29)
51138		 lw    $15,m68k_ICount
51139		 seb   $10,$2
51140		 and   $2,$10,$9
51141		 and   $16,$0,$0        	 # Clear Carry
51142		 and   $17,$0,$0        	 # Clear Overflow
51143		 slt   $19,$2,$0        	 # Set Sign
51144		 sltiu $18,$2,1         	 # Set Zero
51145		 lw    $25,0x88($21)
51146		 sw    $15,m68k_ICount
51147		 sw    $9,0x44($29)
51148		 sw    $14,0x40($29)
51149		 sw    $24,0x3C($29)
51150		 or    $5,$0,$2
51151		 or    $4,$0,$14
51152		 jalr  $25
51153		 sw    $23,0x4C($21)    	 # Delay slot
51154		 lw    $24,0x3C($29)
51155		 lw    $14,0x40($29)
51156		 lw    $9,0x44($29)
51157		 lw    $15,m68k_ICount
51158		 addiu $15,$15,-14
51159		 bgez  $15,3f
51160		 lhu   $24,0x00($23)    	 # Delay slot
51161		 j     MainExit
51162	3:
51163		 sll   $7,$24,2         	 # Delay slot
51164		 addu  $7,$7,$30
51165		 lw    $7,0x00($7)
51166		 jr    $7
51167		 nop                    	 # Delay slot
51168
51169OP0_c128:				#:
51170		 addiu $23,$23,2
51171
51172		 andi  $8,$24,0x07
51173		 srl   $24,$24,7
51174		 andi  $24,$24,0x1C
51175		 addu  $24,$24,$21
51176		 lb    $9,0x00($24)
51177		 lh    $7,0x00($23)
51178		 sll   $8,$8,2
51179		 addu  $8,$8,$21
51180		 lw    $14,0x20($8)
51181		 addiu $23,$23,2
51182		 addu  $14,$14,$7
51183		 lw    $25,0x7C($21)
51184		 sw    $15,m68k_ICount
51185		 sw    $9,0x44($29)
51186		 sw    $14,0x40($29)
51187		 sw    $24,0x3C($29)
51188		 or    $4,$0,$14
51189		 jalr  $25
51190		 sw    $23,0x4C($21)    	 # Delay slot
51191		 lw    $24,0x3C($29)
51192		 lw    $14,0x40($29)
51193		 lw    $9,0x44($29)
51194		 lw    $15,m68k_ICount
51195		 seb   $10,$2
51196		 and   $2,$10,$9
51197		 and   $16,$0,$0        	 # Clear Carry
51198		 and   $17,$0,$0        	 # Clear Overflow
51199		 slt   $19,$2,$0        	 # Set Sign
51200		 sltiu $18,$2,1         	 # Set Zero
51201		 lw    $25,0x88($21)
51202		 sw    $15,m68k_ICount
51203		 sw    $9,0x44($29)
51204		 sw    $14,0x40($29)
51205		 sw    $24,0x3C($29)
51206		 or    $5,$0,$2
51207		 or    $4,$0,$14
51208		 jalr  $25
51209		 sw    $23,0x4C($21)    	 # Delay slot
51210		 lw    $24,0x3C($29)
51211		 lw    $14,0x40($29)
51212		 lw    $9,0x44($29)
51213		 lw    $15,m68k_ICount
51214		 addiu $15,$15,-16
51215		 bgez  $15,3f
51216		 lhu   $24,0x00($23)    	 # Delay slot
51217		 j     MainExit
51218	3:
51219		 sll   $7,$24,2         	 # Delay slot
51220		 addu  $7,$7,$30
51221		 lw    $7,0x00($7)
51222		 jr    $7
51223		 nop                    	 # Delay slot
51224
51225OP0_c130:				#:
51226		 addiu $23,$23,2
51227
51228		 andi  $8,$24,0x07
51229		 srl   $24,$24,7
51230		 andi  $24,$24,0x1C
51231		 addu  $24,$24,$21
51232		 lb    $9,0x00($24)
51233		 sll   $8,$8,2
51234		 addu  $8,$8,$21
51235		 lw    $14,0x20($8)
51236		 lhu   $7,0x00($23)
51237		 addiu $23,$23,2
51238		 seb   $6,$7
51239		 or    $25,$0,$7
51240		 srl   $7,$7,12
51241		 andi  $25,$25,0x0800
51242		 sll   $7,$7,2
51243		 addu  $7,$7,$21
51244		 bne   $25,$0,0f
51245		 lw    $25,0x00($7)      	 # Delay slot
51246		 seh   $25,$25
51247	0:
51248		 addu  $25,$14,$25
51249		 addu  $14,$25,$6
51250		 lw    $25,0x7C($21)
51251		 sw    $15,m68k_ICount
51252		 sw    $9,0x44($29)
51253		 sw    $14,0x40($29)
51254		 sw    $24,0x3C($29)
51255		 or    $4,$0,$14
51256		 jalr  $25
51257		 sw    $23,0x4C($21)    	 # Delay slot
51258		 lw    $24,0x3C($29)
51259		 lw    $14,0x40($29)
51260		 lw    $9,0x44($29)
51261		 lw    $15,m68k_ICount
51262		 seb   $10,$2
51263		 and   $2,$10,$9
51264		 and   $16,$0,$0        	 # Clear Carry
51265		 and   $17,$0,$0        	 # Clear Overflow
51266		 slt   $19,$2,$0        	 # Set Sign
51267		 sltiu $18,$2,1         	 # Set Zero
51268		 lw    $25,0x88($21)
51269		 sw    $15,m68k_ICount
51270		 sw    $9,0x44($29)
51271		 sw    $14,0x40($29)
51272		 sw    $24,0x3C($29)
51273		 or    $5,$0,$2
51274		 or    $4,$0,$14
51275		 jalr  $25
51276		 sw    $23,0x4C($21)    	 # Delay slot
51277		 lw    $24,0x3C($29)
51278		 lw    $14,0x40($29)
51279		 lw    $9,0x44($29)
51280		 lw    $15,m68k_ICount
51281		 addiu $15,$15,-18
51282		 bgez  $15,3f
51283		 lhu   $24,0x00($23)    	 # Delay slot
51284		 j     MainExit
51285	3:
51286		 sll   $7,$24,2         	 # Delay slot
51287		 addu  $7,$7,$30
51288		 lw    $7,0x00($7)
51289		 jr    $7
51290		 nop                    	 # Delay slot
51291
51292OP0_c138:				#:
51293		 addiu $23,$23,2
51294
51295		 srl   $24,$24,7
51296		 andi  $24,$24,0x1C
51297		 addu  $24,$24,$21
51298		 lb    $9,0x00($24)
51299		 lh    $14,0x00($23)
51300		 addiu $23,$23,2
51301		 lw    $25,0x7C($21)
51302		 sw    $15,m68k_ICount
51303		 sw    $9,0x44($29)
51304		 sw    $14,0x40($29)
51305		 sw    $24,0x3C($29)
51306		 or    $4,$0,$14
51307		 jalr  $25
51308		 sw    $23,0x4C($21)    	 # Delay slot
51309		 lw    $24,0x3C($29)
51310		 lw    $14,0x40($29)
51311		 lw    $9,0x44($29)
51312		 lw    $15,m68k_ICount
51313		 seb   $10,$2
51314		 and   $2,$10,$9
51315		 and   $16,$0,$0        	 # Clear Carry
51316		 and   $17,$0,$0        	 # Clear Overflow
51317		 slt   $19,$2,$0        	 # Set Sign
51318		 sltiu $18,$2,1         	 # Set Zero
51319		 lw    $25,0x88($21)
51320		 sw    $15,m68k_ICount
51321		 sw    $9,0x44($29)
51322		 sw    $14,0x40($29)
51323		 sw    $24,0x3C($29)
51324		 or    $5,$0,$2
51325		 or    $4,$0,$14
51326		 jalr  $25
51327		 sw    $23,0x4C($21)    	 # Delay slot
51328		 lw    $24,0x3C($29)
51329		 lw    $14,0x40($29)
51330		 lw    $9,0x44($29)
51331		 lw    $15,m68k_ICount
51332		 addiu $15,$15,-16
51333		 bgez  $15,3f
51334		 lhu   $24,0x00($23)    	 # Delay slot
51335		 j     MainExit
51336	3:
51337		 sll   $7,$24,2         	 # Delay slot
51338		 addu  $7,$7,$30
51339		 lw    $7,0x00($7)
51340		 jr    $7
51341		 nop                    	 # Delay slot
51342
51343OP0_c139:				#:
51344		 addiu $23,$23,2
51345
51346		 srl   $24,$24,7
51347		 andi  $24,$24,0x1C
51348		 addu  $24,$24,$21
51349		 lb    $9,0x00($24)
51350		 lhu   $14,0x00($23)
51351		 lhu   $25,0x02($23)
51352		 sll   $14,$14,16
51353		 or    $14,$14,$25
51354		 addiu $23,$23,4
51355		 lw    $25,0x7C($21)
51356		 sw    $15,m68k_ICount
51357		 sw    $9,0x44($29)
51358		 sw    $14,0x40($29)
51359		 sw    $24,0x3C($29)
51360		 or    $4,$0,$14
51361		 jalr  $25
51362		 sw    $23,0x4C($21)    	 # Delay slot
51363		 lw    $24,0x3C($29)
51364		 lw    $14,0x40($29)
51365		 lw    $9,0x44($29)
51366		 lw    $15,m68k_ICount
51367		 seb   $10,$2
51368		 and   $2,$10,$9
51369		 and   $16,$0,$0        	 # Clear Carry
51370		 and   $17,$0,$0        	 # Clear Overflow
51371		 slt   $19,$2,$0        	 # Set Sign
51372		 sltiu $18,$2,1         	 # Set Zero
51373		 lw    $25,0x88($21)
51374		 sw    $15,m68k_ICount
51375		 sw    $9,0x44($29)
51376		 sw    $14,0x40($29)
51377		 sw    $24,0x3C($29)
51378		 or    $5,$0,$2
51379		 or    $4,$0,$14
51380		 jalr  $25
51381		 sw    $23,0x4C($21)    	 # Delay slot
51382		 lw    $24,0x3C($29)
51383		 lw    $14,0x40($29)
51384		 lw    $9,0x44($29)
51385		 lw    $15,m68k_ICount
51386		 addiu $15,$15,-20
51387		 bgez  $15,3f
51388		 lhu   $24,0x00($23)    	 # Delay slot
51389		 j     MainExit
51390	3:
51391		 sll   $7,$24,2         	 # Delay slot
51392		 addu  $7,$7,$30
51393		 lw    $7,0x00($7)
51394		 jr    $7
51395		 nop                    	 # Delay slot
51396
51397OP0_c150:				#:
51398		 addiu $23,$23,2
51399
51400		 andi  $8,$24,0x07
51401		 srl   $24,$24,7
51402		 andi  $24,$24,0x1C
51403		 addu  $24,$24,$21
51404		 lh    $9,0x00($24)
51405		 sll   $8,$8,2
51406		 addu  $8,$8,$21
51407		 lw    $14,0x20($8)
51408		 lw    $25,0x80($21)
51409		 sw    $15,m68k_ICount
51410		 sw    $9,0x44($29)
51411		 sw    $14,0x40($29)
51412		 sw    $24,0x3C($29)
51413		 or    $4,$0,$14
51414		 jalr  $25
51415		 sw    $23,0x4C($21)    	 # Delay slot
51416		 lw    $24,0x3C($29)
51417		 lw    $14,0x40($29)
51418		 lw    $9,0x44($29)
51419		 lw    $15,m68k_ICount
51420		 seh   $10,$2
51421		 and   $2,$10,$9
51422		 and   $16,$0,$0        	 # Clear Carry
51423		 and   $17,$0,$0        	 # Clear Overflow
51424		 slt   $19,$2,$0        	 # Set Sign
51425		 sltiu $18,$2,1         	 # Set Zero
51426		 lw    $25,0x8C($21)
51427		 sw    $15,m68k_ICount
51428		 sw    $9,0x44($29)
51429		 sw    $14,0x40($29)
51430		 sw    $24,0x3C($29)
51431		 or    $5,$0,$2
51432		 or    $4,$0,$14
51433		 jalr  $25
51434		 sw    $23,0x4C($21)    	 # Delay slot
51435		 lw    $24,0x3C($29)
51436		 lw    $14,0x40($29)
51437		 lw    $9,0x44($29)
51438		 lw    $15,m68k_ICount
51439		 addiu $15,$15,-12
51440		 bgez  $15,3f
51441		 lhu   $24,0x00($23)    	 # Delay slot
51442		 j     MainExit
51443	3:
51444		 sll   $7,$24,2         	 # Delay slot
51445		 addu  $7,$7,$30
51446		 lw    $7,0x00($7)
51447		 jr    $7
51448		 nop                    	 # Delay slot
51449
51450OP0_c158:				#:
51451		 addiu $23,$23,2
51452
51453		 andi  $8,$24,0x07
51454		 srl   $24,$24,7
51455		 andi  $24,$24,0x1C
51456		 addu  $24,$24,$21
51457		 lh    $9,0x00($24)
51458		 sll   $8,$8,2
51459		 addu  $8,$8,$21
51460		 lw    $14,0x20($8)
51461		 addiu $25,$14,2
51462		 sw    $25,0x20($8)
51463		 lw    $25,0x80($21)
51464		 sw    $15,m68k_ICount
51465		 sw    $9,0x44($29)
51466		 sw    $14,0x40($29)
51467		 sw    $24,0x3C($29)
51468		 or    $4,$0,$14
51469		 jalr  $25
51470		 sw    $23,0x4C($21)    	 # Delay slot
51471		 lw    $24,0x3C($29)
51472		 lw    $14,0x40($29)
51473		 lw    $9,0x44($29)
51474		 lw    $15,m68k_ICount
51475		 seh   $10,$2
51476		 and   $2,$10,$9
51477		 and   $16,$0,$0        	 # Clear Carry
51478		 and   $17,$0,$0        	 # Clear Overflow
51479		 slt   $19,$2,$0        	 # Set Sign
51480		 sltiu $18,$2,1         	 # Set Zero
51481		 lw    $25,0x8C($21)
51482		 sw    $15,m68k_ICount
51483		 sw    $9,0x44($29)
51484		 sw    $14,0x40($29)
51485		 sw    $24,0x3C($29)
51486		 or    $5,$0,$2
51487		 or    $4,$0,$14
51488		 jalr  $25
51489		 sw    $23,0x4C($21)    	 # Delay slot
51490		 lw    $24,0x3C($29)
51491		 lw    $14,0x40($29)
51492		 lw    $9,0x44($29)
51493		 lw    $15,m68k_ICount
51494		 addiu $15,$15,-12
51495		 bgez  $15,3f
51496		 lhu   $24,0x00($23)    	 # Delay slot
51497		 j     MainExit
51498	3:
51499		 sll   $7,$24,2         	 # Delay slot
51500		 addu  $7,$7,$30
51501		 lw    $7,0x00($7)
51502		 jr    $7
51503		 nop                    	 # Delay slot
51504
51505OP0_c160:				#:
51506		 addiu $23,$23,2
51507
51508		 andi  $8,$24,0x07
51509		 srl   $24,$24,7
51510		 andi  $24,$24,0x1C
51511		 addu  $24,$24,$21
51512		 lh    $9,0x00($24)
51513		 sll   $8,$8,2
51514		 addu  $8,$8,$21
51515		 lw    $14,0x20($8)
51516		 addiu $14,$14,-2
51517		 sw    $14,0x20($8)
51518		 lw    $25,0x80($21)
51519		 sw    $15,m68k_ICount
51520		 sw    $9,0x44($29)
51521		 sw    $14,0x40($29)
51522		 sw    $24,0x3C($29)
51523		 or    $4,$0,$14
51524		 jalr  $25
51525		 sw    $23,0x4C($21)    	 # Delay slot
51526		 lw    $24,0x3C($29)
51527		 lw    $14,0x40($29)
51528		 lw    $9,0x44($29)
51529		 lw    $15,m68k_ICount
51530		 seh   $10,$2
51531		 and   $2,$10,$9
51532		 and   $16,$0,$0        	 # Clear Carry
51533		 and   $17,$0,$0        	 # Clear Overflow
51534		 slt   $19,$2,$0        	 # Set Sign
51535		 sltiu $18,$2,1         	 # Set Zero
51536		 lw    $25,0x8C($21)
51537		 sw    $15,m68k_ICount
51538		 sw    $9,0x44($29)
51539		 sw    $14,0x40($29)
51540		 sw    $24,0x3C($29)
51541		 or    $5,$0,$2
51542		 or    $4,$0,$14
51543		 jalr  $25
51544		 sw    $23,0x4C($21)    	 # Delay slot
51545		 lw    $24,0x3C($29)
51546		 lw    $14,0x40($29)
51547		 lw    $9,0x44($29)
51548		 lw    $15,m68k_ICount
51549		 addiu $15,$15,-14
51550		 bgez  $15,3f
51551		 lhu   $24,0x00($23)    	 # Delay slot
51552		 j     MainExit
51553	3:
51554		 sll   $7,$24,2         	 # Delay slot
51555		 addu  $7,$7,$30
51556		 lw    $7,0x00($7)
51557		 jr    $7
51558		 nop                    	 # Delay slot
51559
51560OP0_c168:				#:
51561		 addiu $23,$23,2
51562
51563		 andi  $8,$24,0x07
51564		 srl   $24,$24,7
51565		 andi  $24,$24,0x1C
51566		 addu  $24,$24,$21
51567		 lh    $9,0x00($24)
51568		 lh    $7,0x00($23)
51569		 sll   $8,$8,2
51570		 addu  $8,$8,$21
51571		 lw    $14,0x20($8)
51572		 addiu $23,$23,2
51573		 addu  $14,$14,$7
51574		 lw    $25,0x80($21)
51575		 sw    $15,m68k_ICount
51576		 sw    $9,0x44($29)
51577		 sw    $14,0x40($29)
51578		 sw    $24,0x3C($29)
51579		 or    $4,$0,$14
51580		 jalr  $25
51581		 sw    $23,0x4C($21)    	 # Delay slot
51582		 lw    $24,0x3C($29)
51583		 lw    $14,0x40($29)
51584		 lw    $9,0x44($29)
51585		 lw    $15,m68k_ICount
51586		 seh   $10,$2
51587		 and   $2,$10,$9
51588		 and   $16,$0,$0        	 # Clear Carry
51589		 and   $17,$0,$0        	 # Clear Overflow
51590		 slt   $19,$2,$0        	 # Set Sign
51591		 sltiu $18,$2,1         	 # Set Zero
51592		 lw    $25,0x8C($21)
51593		 sw    $15,m68k_ICount
51594		 sw    $9,0x44($29)
51595		 sw    $14,0x40($29)
51596		 sw    $24,0x3C($29)
51597		 or    $5,$0,$2
51598		 or    $4,$0,$14
51599		 jalr  $25
51600		 sw    $23,0x4C($21)    	 # Delay slot
51601		 lw    $24,0x3C($29)
51602		 lw    $14,0x40($29)
51603		 lw    $9,0x44($29)
51604		 lw    $15,m68k_ICount
51605		 addiu $15,$15,-16
51606		 bgez  $15,3f
51607		 lhu   $24,0x00($23)    	 # Delay slot
51608		 j     MainExit
51609	3:
51610		 sll   $7,$24,2         	 # Delay slot
51611		 addu  $7,$7,$30
51612		 lw    $7,0x00($7)
51613		 jr    $7
51614		 nop                    	 # Delay slot
51615
51616OP0_c170:				#:
51617		 addiu $23,$23,2
51618
51619		 andi  $8,$24,0x07
51620		 srl   $24,$24,7
51621		 andi  $24,$24,0x1C
51622		 addu  $24,$24,$21
51623		 lh    $9,0x00($24)
51624		 sll   $8,$8,2
51625		 addu  $8,$8,$21
51626		 lw    $14,0x20($8)
51627		 lhu   $7,0x00($23)
51628		 addiu $23,$23,2
51629		 seb   $6,$7
51630		 or    $25,$0,$7
51631		 srl   $7,$7,12
51632		 andi  $25,$25,0x0800
51633		 sll   $7,$7,2
51634		 addu  $7,$7,$21
51635		 bne   $25,$0,0f
51636		 lw    $25,0x00($7)      	 # Delay slot
51637		 seh   $25,$25
51638	0:
51639		 addu  $25,$14,$25
51640		 addu  $14,$25,$6
51641		 lw    $25,0x80($21)
51642		 sw    $15,m68k_ICount
51643		 sw    $9,0x44($29)
51644		 sw    $14,0x40($29)
51645		 sw    $24,0x3C($29)
51646		 or    $4,$0,$14
51647		 jalr  $25
51648		 sw    $23,0x4C($21)    	 # Delay slot
51649		 lw    $24,0x3C($29)
51650		 lw    $14,0x40($29)
51651		 lw    $9,0x44($29)
51652		 lw    $15,m68k_ICount
51653		 seh   $10,$2
51654		 and   $2,$10,$9
51655		 and   $16,$0,$0        	 # Clear Carry
51656		 and   $17,$0,$0        	 # Clear Overflow
51657		 slt   $19,$2,$0        	 # Set Sign
51658		 sltiu $18,$2,1         	 # Set Zero
51659		 lw    $25,0x8C($21)
51660		 sw    $15,m68k_ICount
51661		 sw    $9,0x44($29)
51662		 sw    $14,0x40($29)
51663		 sw    $24,0x3C($29)
51664		 or    $5,$0,$2
51665		 or    $4,$0,$14
51666		 jalr  $25
51667		 sw    $23,0x4C($21)    	 # Delay slot
51668		 lw    $24,0x3C($29)
51669		 lw    $14,0x40($29)
51670		 lw    $9,0x44($29)
51671		 lw    $15,m68k_ICount
51672		 addiu $15,$15,-18
51673		 bgez  $15,3f
51674		 lhu   $24,0x00($23)    	 # Delay slot
51675		 j     MainExit
51676	3:
51677		 sll   $7,$24,2         	 # Delay slot
51678		 addu  $7,$7,$30
51679		 lw    $7,0x00($7)
51680		 jr    $7
51681		 nop                    	 # Delay slot
51682
51683OP0_c178:				#:
51684		 addiu $23,$23,2
51685
51686		 srl   $24,$24,7
51687		 andi  $24,$24,0x1C
51688		 addu  $24,$24,$21
51689		 lh    $9,0x00($24)
51690		 lh    $14,0x00($23)
51691		 addiu $23,$23,2
51692		 lw    $25,0x80($21)
51693		 sw    $15,m68k_ICount
51694		 sw    $9,0x44($29)
51695		 sw    $14,0x40($29)
51696		 sw    $24,0x3C($29)
51697		 or    $4,$0,$14
51698		 jalr  $25
51699		 sw    $23,0x4C($21)    	 # Delay slot
51700		 lw    $24,0x3C($29)
51701		 lw    $14,0x40($29)
51702		 lw    $9,0x44($29)
51703		 lw    $15,m68k_ICount
51704		 seh   $10,$2
51705		 and   $2,$10,$9
51706		 and   $16,$0,$0        	 # Clear Carry
51707		 and   $17,$0,$0        	 # Clear Overflow
51708		 slt   $19,$2,$0        	 # Set Sign
51709		 sltiu $18,$2,1         	 # Set Zero
51710		 lw    $25,0x8C($21)
51711		 sw    $15,m68k_ICount
51712		 sw    $9,0x44($29)
51713		 sw    $14,0x40($29)
51714		 sw    $24,0x3C($29)
51715		 or    $5,$0,$2
51716		 or    $4,$0,$14
51717		 jalr  $25
51718		 sw    $23,0x4C($21)    	 # Delay slot
51719		 lw    $24,0x3C($29)
51720		 lw    $14,0x40($29)
51721		 lw    $9,0x44($29)
51722		 lw    $15,m68k_ICount
51723		 addiu $15,$15,-16
51724		 bgez  $15,3f
51725		 lhu   $24,0x00($23)    	 # Delay slot
51726		 j     MainExit
51727	3:
51728		 sll   $7,$24,2         	 # Delay slot
51729		 addu  $7,$7,$30
51730		 lw    $7,0x00($7)
51731		 jr    $7
51732		 nop                    	 # Delay slot
51733
51734OP0_c179:				#:
51735		 addiu $23,$23,2
51736
51737		 srl   $24,$24,7
51738		 andi  $24,$24,0x1C
51739		 addu  $24,$24,$21
51740		 lh    $9,0x00($24)
51741		 lhu   $14,0x00($23)
51742		 lhu   $25,0x02($23)
51743		 sll   $14,$14,16
51744		 or    $14,$14,$25
51745		 addiu $23,$23,4
51746		 lw    $25,0x80($21)
51747		 sw    $15,m68k_ICount
51748		 sw    $9,0x44($29)
51749		 sw    $14,0x40($29)
51750		 sw    $24,0x3C($29)
51751		 or    $4,$0,$14
51752		 jalr  $25
51753		 sw    $23,0x4C($21)    	 # Delay slot
51754		 lw    $24,0x3C($29)
51755		 lw    $14,0x40($29)
51756		 lw    $9,0x44($29)
51757		 lw    $15,m68k_ICount
51758		 seh   $10,$2
51759		 and   $2,$10,$9
51760		 and   $16,$0,$0        	 # Clear Carry
51761		 and   $17,$0,$0        	 # Clear Overflow
51762		 slt   $19,$2,$0        	 # Set Sign
51763		 sltiu $18,$2,1         	 # Set Zero
51764		 lw    $25,0x8C($21)
51765		 sw    $15,m68k_ICount
51766		 sw    $9,0x44($29)
51767		 sw    $14,0x40($29)
51768		 sw    $24,0x3C($29)
51769		 or    $5,$0,$2
51770		 or    $4,$0,$14
51771		 jalr  $25
51772		 sw    $23,0x4C($21)    	 # Delay slot
51773		 lw    $24,0x3C($29)
51774		 lw    $14,0x40($29)
51775		 lw    $9,0x44($29)
51776		 lw    $15,m68k_ICount
51777		 addiu $15,$15,-20
51778		 bgez  $15,3f
51779		 lhu   $24,0x00($23)    	 # Delay slot
51780		 j     MainExit
51781	3:
51782		 sll   $7,$24,2         	 # Delay slot
51783		 addu  $7,$7,$30
51784		 lw    $7,0x00($7)
51785		 jr    $7
51786		 nop                    	 # Delay slot
51787
51788OP0_c190:				#:
51789		 addiu $23,$23,2
51790
51791		 andi  $8,$24,0x07
51792		 srl   $24,$24,7
51793		 andi  $24,$24,0x1C
51794		 addu  $24,$24,$21
51795		 lw    $9,0x00($24)
51796		 sll   $8,$8,2
51797		 addu  $8,$8,$21
51798		 lw    $14,0x20($8)
51799		 lw    $25,0x84($21)
51800		 sw    $15,m68k_ICount
51801		 sw    $9,0x44($29)
51802		 sw    $14,0x40($29)
51803		 sw    $24,0x3C($29)
51804		 or    $4,$0,$14
51805		 jalr  $25
51806		 sw    $23,0x4C($21)    	 # Delay slot
51807		 lw    $24,0x3C($29)
51808		 lw    $14,0x40($29)
51809		 lw    $9,0x44($29)
51810		 lw    $15,m68k_ICount
51811		 or    $10,$0,$2
51812		 and   $2,$10,$9
51813		 and   $16,$0,$0        	 # Clear Carry
51814		 and   $17,$0,$0        	 # Clear Overflow
51815		 slt   $19,$2,$0        	 # Set Sign
51816		 sltiu $18,$2,1         	 # Set Zero
51817		 lw    $25,0x90($21)
51818		 sw    $15,m68k_ICount
51819		 sw    $9,0x44($29)
51820		 sw    $14,0x40($29)
51821		 sw    $24,0x3C($29)
51822		 or    $5,$0,$2
51823		 or    $4,$0,$14
51824		 jalr  $25
51825		 sw    $23,0x4C($21)    	 # Delay slot
51826		 lw    $24,0x3C($29)
51827		 lw    $14,0x40($29)
51828		 lw    $9,0x44($29)
51829		 lw    $15,m68k_ICount
51830		 addiu $15,$15,-20
51831		 bgez  $15,3f
51832		 lhu   $24,0x00($23)    	 # Delay slot
51833		 j     MainExit
51834	3:
51835		 sll   $7,$24,2         	 # Delay slot
51836		 addu  $7,$7,$30
51837		 lw    $7,0x00($7)
51838		 jr    $7
51839		 nop                    	 # Delay slot
51840
51841OP0_c198:				#:
51842		 addiu $23,$23,2
51843
51844		 andi  $8,$24,0x07
51845		 srl   $24,$24,7
51846		 andi  $24,$24,0x1C
51847		 addu  $24,$24,$21
51848		 lw    $9,0x00($24)
51849		 sll   $8,$8,2
51850		 addu  $8,$8,$21
51851		 lw    $14,0x20($8)
51852		 addiu $25,$14,4
51853		 sw    $25,0x20($8)
51854		 lw    $25,0x84($21)
51855		 sw    $15,m68k_ICount
51856		 sw    $9,0x44($29)
51857		 sw    $14,0x40($29)
51858		 sw    $24,0x3C($29)
51859		 or    $4,$0,$14
51860		 jalr  $25
51861		 sw    $23,0x4C($21)    	 # Delay slot
51862		 lw    $24,0x3C($29)
51863		 lw    $14,0x40($29)
51864		 lw    $9,0x44($29)
51865		 lw    $15,m68k_ICount
51866		 or    $10,$0,$2
51867		 and   $2,$10,$9
51868		 and   $16,$0,$0        	 # Clear Carry
51869		 and   $17,$0,$0        	 # Clear Overflow
51870		 slt   $19,$2,$0        	 # Set Sign
51871		 sltiu $18,$2,1         	 # Set Zero
51872		 lw    $25,0x90($21)
51873		 sw    $15,m68k_ICount
51874		 sw    $9,0x44($29)
51875		 sw    $14,0x40($29)
51876		 sw    $24,0x3C($29)
51877		 or    $5,$0,$2
51878		 or    $4,$0,$14
51879		 jalr  $25
51880		 sw    $23,0x4C($21)    	 # Delay slot
51881		 lw    $24,0x3C($29)
51882		 lw    $14,0x40($29)
51883		 lw    $9,0x44($29)
51884		 lw    $15,m68k_ICount
51885		 addiu $15,$15,-20
51886		 bgez  $15,3f
51887		 lhu   $24,0x00($23)    	 # Delay slot
51888		 j     MainExit
51889	3:
51890		 sll   $7,$24,2         	 # Delay slot
51891		 addu  $7,$7,$30
51892		 lw    $7,0x00($7)
51893		 jr    $7
51894		 nop                    	 # Delay slot
51895
51896OP0_c1a0:				#:
51897		 addiu $23,$23,2
51898
51899		 andi  $8,$24,0x07
51900		 srl   $24,$24,7
51901		 andi  $24,$24,0x1C
51902		 addu  $24,$24,$21
51903		 lw    $9,0x00($24)
51904		 sll   $8,$8,2
51905		 addu  $8,$8,$21
51906		 lw    $14,0x20($8)
51907		 addiu $14,$14,-4
51908		 sw    $14,0x20($8)
51909		 lw    $25,0x84($21)
51910		 sw    $15,m68k_ICount
51911		 sw    $9,0x44($29)
51912		 sw    $14,0x40($29)
51913		 sw    $24,0x3C($29)
51914		 or    $4,$0,$14
51915		 jalr  $25
51916		 sw    $23,0x4C($21)    	 # Delay slot
51917		 lw    $24,0x3C($29)
51918		 lw    $14,0x40($29)
51919		 lw    $9,0x44($29)
51920		 lw    $15,m68k_ICount
51921		 or    $10,$0,$2
51922		 and   $2,$10,$9
51923		 and   $16,$0,$0        	 # Clear Carry
51924		 and   $17,$0,$0        	 # Clear Overflow
51925		 slt   $19,$2,$0        	 # Set Sign
51926		 sltiu $18,$2,1         	 # Set Zero
51927		 lw    $25,0x90($21)
51928		 sw    $15,m68k_ICount
51929		 sw    $9,0x44($29)
51930		 sw    $14,0x40($29)
51931		 sw    $24,0x3C($29)
51932		 or    $5,$0,$2
51933		 or    $4,$0,$14
51934		 jalr  $25
51935		 sw    $23,0x4C($21)    	 # Delay slot
51936		 lw    $24,0x3C($29)
51937		 lw    $14,0x40($29)
51938		 lw    $9,0x44($29)
51939		 lw    $15,m68k_ICount
51940		 addiu $15,$15,-22
51941		 bgez  $15,3f
51942		 lhu   $24,0x00($23)    	 # Delay slot
51943		 j     MainExit
51944	3:
51945		 sll   $7,$24,2         	 # Delay slot
51946		 addu  $7,$7,$30
51947		 lw    $7,0x00($7)
51948		 jr    $7
51949		 nop                    	 # Delay slot
51950
51951OP0_c1a8:				#:
51952		 addiu $23,$23,2
51953
51954		 andi  $8,$24,0x07
51955		 srl   $24,$24,7
51956		 andi  $24,$24,0x1C
51957		 addu  $24,$24,$21
51958		 lw    $9,0x00($24)
51959		 lh    $7,0x00($23)
51960		 sll   $8,$8,2
51961		 addu  $8,$8,$21
51962		 lw    $14,0x20($8)
51963		 addiu $23,$23,2
51964		 addu  $14,$14,$7
51965		 lw    $25,0x84($21)
51966		 sw    $15,m68k_ICount
51967		 sw    $9,0x44($29)
51968		 sw    $14,0x40($29)
51969		 sw    $24,0x3C($29)
51970		 or    $4,$0,$14
51971		 jalr  $25
51972		 sw    $23,0x4C($21)    	 # Delay slot
51973		 lw    $24,0x3C($29)
51974		 lw    $14,0x40($29)
51975		 lw    $9,0x44($29)
51976		 lw    $15,m68k_ICount
51977		 or    $10,$0,$2
51978		 and   $2,$10,$9
51979		 and   $16,$0,$0        	 # Clear Carry
51980		 and   $17,$0,$0        	 # Clear Overflow
51981		 slt   $19,$2,$0        	 # Set Sign
51982		 sltiu $18,$2,1         	 # Set Zero
51983		 lw    $25,0x90($21)
51984		 sw    $15,m68k_ICount
51985		 sw    $9,0x44($29)
51986		 sw    $14,0x40($29)
51987		 sw    $24,0x3C($29)
51988		 or    $5,$0,$2
51989		 or    $4,$0,$14
51990		 jalr  $25
51991		 sw    $23,0x4C($21)    	 # Delay slot
51992		 lw    $24,0x3C($29)
51993		 lw    $14,0x40($29)
51994		 lw    $9,0x44($29)
51995		 lw    $15,m68k_ICount
51996		 addiu $15,$15,-24
51997		 bgez  $15,3f
51998		 lhu   $24,0x00($23)    	 # Delay slot
51999		 j     MainExit
52000	3:
52001		 sll   $7,$24,2         	 # Delay slot
52002		 addu  $7,$7,$30
52003		 lw    $7,0x00($7)
52004		 jr    $7
52005		 nop                    	 # Delay slot
52006
52007OP0_c1b0:				#:
52008		 addiu $23,$23,2
52009
52010		 andi  $8,$24,0x07
52011		 srl   $24,$24,7
52012		 andi  $24,$24,0x1C
52013		 addu  $24,$24,$21
52014		 lw    $9,0x00($24)
52015		 sll   $8,$8,2
52016		 addu  $8,$8,$21
52017		 lw    $14,0x20($8)
52018		 lhu   $7,0x00($23)
52019		 addiu $23,$23,2
52020		 seb   $6,$7
52021		 or    $25,$0,$7
52022		 srl   $7,$7,12
52023		 andi  $25,$25,0x0800
52024		 sll   $7,$7,2
52025		 addu  $7,$7,$21
52026		 bne   $25,$0,0f
52027		 lw    $25,0x00($7)      	 # Delay slot
52028		 seh   $25,$25
52029	0:
52030		 addu  $25,$14,$25
52031		 addu  $14,$25,$6
52032		 lw    $25,0x84($21)
52033		 sw    $15,m68k_ICount
52034		 sw    $9,0x44($29)
52035		 sw    $14,0x40($29)
52036		 sw    $24,0x3C($29)
52037		 or    $4,$0,$14
52038		 jalr  $25
52039		 sw    $23,0x4C($21)    	 # Delay slot
52040		 lw    $24,0x3C($29)
52041		 lw    $14,0x40($29)
52042		 lw    $9,0x44($29)
52043		 lw    $15,m68k_ICount
52044		 or    $10,$0,$2
52045		 and   $2,$10,$9
52046		 and   $16,$0,$0        	 # Clear Carry
52047		 and   $17,$0,$0        	 # Clear Overflow
52048		 slt   $19,$2,$0        	 # Set Sign
52049		 sltiu $18,$2,1         	 # Set Zero
52050		 lw    $25,0x90($21)
52051		 sw    $15,m68k_ICount
52052		 sw    $9,0x44($29)
52053		 sw    $14,0x40($29)
52054		 sw    $24,0x3C($29)
52055		 or    $5,$0,$2
52056		 or    $4,$0,$14
52057		 jalr  $25
52058		 sw    $23,0x4C($21)    	 # Delay slot
52059		 lw    $24,0x3C($29)
52060		 lw    $14,0x40($29)
52061		 lw    $9,0x44($29)
52062		 lw    $15,m68k_ICount
52063		 addiu $15,$15,-26
52064		 bgez  $15,3f
52065		 lhu   $24,0x00($23)    	 # Delay slot
52066		 j     MainExit
52067	3:
52068		 sll   $7,$24,2         	 # Delay slot
52069		 addu  $7,$7,$30
52070		 lw    $7,0x00($7)
52071		 jr    $7
52072		 nop                    	 # Delay slot
52073
52074OP0_c1b8:				#:
52075		 addiu $23,$23,2
52076
52077		 srl   $24,$24,7
52078		 andi  $24,$24,0x1C
52079		 addu  $24,$24,$21
52080		 lw    $9,0x00($24)
52081		 lh    $14,0x00($23)
52082		 addiu $23,$23,2
52083		 lw    $25,0x84($21)
52084		 sw    $15,m68k_ICount
52085		 sw    $9,0x44($29)
52086		 sw    $14,0x40($29)
52087		 sw    $24,0x3C($29)
52088		 or    $4,$0,$14
52089		 jalr  $25
52090		 sw    $23,0x4C($21)    	 # Delay slot
52091		 lw    $24,0x3C($29)
52092		 lw    $14,0x40($29)
52093		 lw    $9,0x44($29)
52094		 lw    $15,m68k_ICount
52095		 or    $10,$0,$2
52096		 and   $2,$10,$9
52097		 and   $16,$0,$0        	 # Clear Carry
52098		 and   $17,$0,$0        	 # Clear Overflow
52099		 slt   $19,$2,$0        	 # Set Sign
52100		 sltiu $18,$2,1         	 # Set Zero
52101		 lw    $25,0x90($21)
52102		 sw    $15,m68k_ICount
52103		 sw    $9,0x44($29)
52104		 sw    $14,0x40($29)
52105		 sw    $24,0x3C($29)
52106		 or    $5,$0,$2
52107		 or    $4,$0,$14
52108		 jalr  $25
52109		 sw    $23,0x4C($21)    	 # Delay slot
52110		 lw    $24,0x3C($29)
52111		 lw    $14,0x40($29)
52112		 lw    $9,0x44($29)
52113		 lw    $15,m68k_ICount
52114		 addiu $15,$15,-24
52115		 bgez  $15,3f
52116		 lhu   $24,0x00($23)    	 # Delay slot
52117		 j     MainExit
52118	3:
52119		 sll   $7,$24,2         	 # Delay slot
52120		 addu  $7,$7,$30
52121		 lw    $7,0x00($7)
52122		 jr    $7
52123		 nop                    	 # Delay slot
52124
52125OP0_c1b9:				#:
52126		 addiu $23,$23,2
52127
52128		 srl   $24,$24,7
52129		 andi  $24,$24,0x1C
52130		 addu  $24,$24,$21
52131		 lw    $9,0x00($24)
52132		 lhu   $14,0x00($23)
52133		 lhu   $25,0x02($23)
52134		 sll   $14,$14,16
52135		 or    $14,$14,$25
52136		 addiu $23,$23,4
52137		 lw    $25,0x84($21)
52138		 sw    $15,m68k_ICount
52139		 sw    $9,0x44($29)
52140		 sw    $14,0x40($29)
52141		 sw    $24,0x3C($29)
52142		 or    $4,$0,$14
52143		 jalr  $25
52144		 sw    $23,0x4C($21)    	 # Delay slot
52145		 lw    $24,0x3C($29)
52146		 lw    $14,0x40($29)
52147		 lw    $9,0x44($29)
52148		 lw    $15,m68k_ICount
52149		 or    $10,$0,$2
52150		 and   $2,$10,$9
52151		 and   $16,$0,$0        	 # Clear Carry
52152		 and   $17,$0,$0        	 # Clear Overflow
52153		 slt   $19,$2,$0        	 # Set Sign
52154		 sltiu $18,$2,1         	 # Set Zero
52155		 lw    $25,0x90($21)
52156		 sw    $15,m68k_ICount
52157		 sw    $9,0x44($29)
52158		 sw    $14,0x40($29)
52159		 sw    $24,0x3C($29)
52160		 or    $5,$0,$2
52161		 or    $4,$0,$14
52162		 jalr  $25
52163		 sw    $23,0x4C($21)    	 # Delay slot
52164		 lw    $24,0x3C($29)
52165		 lw    $14,0x40($29)
52166		 lw    $9,0x44($29)
52167		 lw    $15,m68k_ICount
52168		 addiu $15,$15,-28
52169		 bgez  $15,3f
52170		 lhu   $24,0x00($23)    	 # Delay slot
52171		 j     MainExit
52172	3:
52173		 sll   $7,$24,2         	 # Delay slot
52174		 addu  $7,$7,$30
52175		 lw    $7,0x00($7)
52176		 jr    $7
52177		 nop                    	 # Delay slot
52178
52179OP0_d000:				#:
52180		 addiu $23,$23,2
52181
52182		 andi  $8,$24,0x07
52183		 srl   $24,$24,7
52184		 andi  $24,$24,0x1C
52185		 addu  $24,$24,$21
52186		 lb    $9,0x00($24)
52187		 sll   $8,$8,2
52188		 addu  $8,$8,$21
52189		 lb    $2,0x00($8)
52190		 addu  $10,$9,$2
52191		 sb    $10,0x00($24)
52192		 sltu  $16,$10,$2       	 # Set Carry
52193		 xor   $17,$9,$2
52194		 nor   $17,$0,$17
52195		 xor   $25,$10,$9
52196		 and   $17,$17,$25
52197		 srl   $17,$17,7
52198		 andi  $17,$17,0x01     	 # Set Overflow
52199		 seb  $25,$10
52200		 slt   $19,$25,$0        	 # Set Sign
52201		 sltiu $18,$25,1         	 # Set Zero
52202		 or    $20,$0,$16      	 # Copy Carry to X
52203		 addiu $15,$15,-4
52204		 bgez  $15,3f
52205		 lhu   $24,0x00($23)    	 # Delay slot
52206		 j     MainExit
52207	3:
52208		 sll   $7,$24,2         	 # Delay slot
52209		 addu  $7,$7,$30
52210		 lw    $7,0x00($7)
52211		 jr    $7
52212		 nop                    	 # Delay slot
52213
52214OP0_d010:				#:
52215		 addiu $23,$23,2
52216
52217		 andi  $8,$24,0x07
52218		 srl   $24,$24,7
52219		 andi  $24,$24,0x1C
52220		 addu  $24,$24,$21
52221		 lb    $9,0x00($24)
52222		 sll   $8,$8,2
52223		 addu  $8,$8,$21
52224		 lw    $14,0x20($8)
52225		 lw    $25,0x7C($21)
52226		 sw    $15,m68k_ICount
52227		 sw    $9,0x44($29)
52228		 sw    $24,0x40($29)
52229		 or    $4,$0,$14
52230		 jalr  $25
52231		 sw    $23,0x4C($21)    	 # Delay slot
52232		 lw    $24,0x40($29)
52233		 lw    $9,0x44($29)
52234		 lw    $15,m68k_ICount
52235		 seb   $2,$2
52236		 addu  $10,$9,$2
52237		 sb    $10,0x00($24)
52238		 sltu  $16,$10,$2       	 # Set Carry
52239		 xor   $17,$9,$2
52240		 nor   $17,$0,$17
52241		 xor   $25,$10,$9
52242		 and   $17,$17,$25
52243		 srl   $17,$17,7
52244		 andi  $17,$17,0x01     	 # Set Overflow
52245		 seb  $25,$10
52246		 slt   $19,$25,$0        	 # Set Sign
52247		 sltiu $18,$25,1         	 # Set Zero
52248		 or    $20,$0,$16      	 # Copy Carry to X
52249		 addiu $15,$15,-8
52250		 bgez  $15,3f
52251		 lhu   $24,0x00($23)    	 # Delay slot
52252		 j     MainExit
52253	3:
52254		 sll   $7,$24,2         	 # Delay slot
52255		 addu  $7,$7,$30
52256		 lw    $7,0x00($7)
52257		 jr    $7
52258		 nop                    	 # Delay slot
52259
52260OP0_d018:				#:
52261		 addiu $23,$23,2
52262
52263		 andi  $8,$24,0x07
52264		 srl   $24,$24,7
52265		 andi  $24,$24,0x1C
52266		 addu  $24,$24,$21
52267		 lb    $9,0x00($24)
52268		 sll   $8,$8,2
52269		 addu  $8,$8,$21
52270		 lw    $14,0x20($8)
52271		 addiu $25,$14,1
52272		 sw    $25,0x20($8)
52273		 lw    $25,0x7C($21)
52274		 sw    $15,m68k_ICount
52275		 sw    $9,0x44($29)
52276		 sw    $24,0x40($29)
52277		 or    $4,$0,$14
52278		 jalr  $25
52279		 sw    $23,0x4C($21)    	 # Delay slot
52280		 lw    $24,0x40($29)
52281		 lw    $9,0x44($29)
52282		 lw    $15,m68k_ICount
52283		 seb   $2,$2
52284		 addu  $10,$9,$2
52285		 sb    $10,0x00($24)
52286		 sltu  $16,$10,$2       	 # Set Carry
52287		 xor   $17,$9,$2
52288		 nor   $17,$0,$17
52289		 xor   $25,$10,$9
52290		 and   $17,$17,$25
52291		 srl   $17,$17,7
52292		 andi  $17,$17,0x01     	 # Set Overflow
52293		 seb  $25,$10
52294		 slt   $19,$25,$0        	 # Set Sign
52295		 sltiu $18,$25,1         	 # Set Zero
52296		 or    $20,$0,$16      	 # Copy Carry to X
52297		 addiu $15,$15,-8
52298		 bgez  $15,3f
52299		 lhu   $24,0x00($23)    	 # Delay slot
52300		 j     MainExit
52301	3:
52302		 sll   $7,$24,2         	 # Delay slot
52303		 addu  $7,$7,$30
52304		 lw    $7,0x00($7)
52305		 jr    $7
52306		 nop                    	 # Delay slot
52307
52308OP0_d01f:				#:
52309		 addiu $23,$23,2
52310
52311		 srl   $24,$24,7
52312		 andi  $24,$24,0x1C
52313		 addu  $24,$24,$21
52314		 lb    $9,0x00($24)
52315		 lw    $14,0x3C($21)    	 # Get A7
52316		 addiu $25,$14,2
52317		 sw    $25,0x3C($21)
52318		 lw    $25,0x7C($21)
52319		 sw    $15,m68k_ICount
52320		 sw    $9,0x44($29)
52321		 sw    $24,0x40($29)
52322		 or    $4,$0,$14
52323		 jalr  $25
52324		 sw    $23,0x4C($21)    	 # Delay slot
52325		 lw    $24,0x40($29)
52326		 lw    $9,0x44($29)
52327		 lw    $15,m68k_ICount
52328		 seb   $2,$2
52329		 addu  $10,$9,$2
52330		 sb    $10,0x00($24)
52331		 sltu  $16,$10,$2       	 # Set Carry
52332		 xor   $17,$9,$2
52333		 nor   $17,$0,$17
52334		 xor   $25,$10,$9
52335		 and   $17,$17,$25
52336		 srl   $17,$17,7
52337		 andi  $17,$17,0x01     	 # Set Overflow
52338		 seb  $25,$10
52339		 slt   $19,$25,$0        	 # Set Sign
52340		 sltiu $18,$25,1         	 # Set Zero
52341		 or    $20,$0,$16      	 # Copy Carry to X
52342		 addiu $15,$15,-8
52343		 bgez  $15,3f
52344		 lhu   $24,0x00($23)    	 # Delay slot
52345		 j     MainExit
52346	3:
52347		 sll   $7,$24,2         	 # Delay slot
52348		 addu  $7,$7,$30
52349		 lw    $7,0x00($7)
52350		 jr    $7
52351		 nop                    	 # Delay slot
52352
52353OP0_d020:				#:
52354		 addiu $23,$23,2
52355
52356		 andi  $8,$24,0x07
52357		 srl   $24,$24,7
52358		 andi  $24,$24,0x1C
52359		 addu  $24,$24,$21
52360		 lb    $9,0x00($24)
52361		 sll   $8,$8,2
52362		 addu  $8,$8,$21
52363		 lw    $14,0x20($8)
52364		 addiu $14,$14,-1
52365		 sw    $14,0x20($8)
52366		 lw    $25,0x7C($21)
52367		 sw    $15,m68k_ICount
52368		 sw    $9,0x44($29)
52369		 sw    $24,0x40($29)
52370		 or    $4,$0,$14
52371		 jalr  $25
52372		 sw    $23,0x4C($21)    	 # Delay slot
52373		 lw    $24,0x40($29)
52374		 lw    $9,0x44($29)
52375		 lw    $15,m68k_ICount
52376		 seb   $2,$2
52377		 addu  $10,$9,$2
52378		 sb    $10,0x00($24)
52379		 sltu  $16,$10,$2       	 # Set Carry
52380		 xor   $17,$9,$2
52381		 nor   $17,$0,$17
52382		 xor   $25,$10,$9
52383		 and   $17,$17,$25
52384		 srl   $17,$17,7
52385		 andi  $17,$17,0x01     	 # Set Overflow
52386		 seb  $25,$10
52387		 slt   $19,$25,$0        	 # Set Sign
52388		 sltiu $18,$25,1         	 # Set Zero
52389		 or    $20,$0,$16      	 # Copy Carry to X
52390		 addiu $15,$15,-10
52391		 bgez  $15,3f
52392		 lhu   $24,0x00($23)    	 # Delay slot
52393		 j     MainExit
52394	3:
52395		 sll   $7,$24,2         	 # Delay slot
52396		 addu  $7,$7,$30
52397		 lw    $7,0x00($7)
52398		 jr    $7
52399		 nop                    	 # Delay slot
52400
52401OP0_d027:				#:
52402		 addiu $23,$23,2
52403
52404		 srl   $24,$24,7
52405		 andi  $24,$24,0x1C
52406		 addu  $24,$24,$21
52407		 lb    $9,0x00($24)
52408		 lw    $14,0x3C($21)    	 # Get A7
52409		 addiu $14,$14,-2
52410		 sw    $14,0x3C($21)
52411		 lw    $25,0x7C($21)
52412		 sw    $15,m68k_ICount
52413		 sw    $9,0x44($29)
52414		 sw    $24,0x40($29)
52415		 or    $4,$0,$14
52416		 jalr  $25
52417		 sw    $23,0x4C($21)    	 # Delay slot
52418		 lw    $24,0x40($29)
52419		 lw    $9,0x44($29)
52420		 lw    $15,m68k_ICount
52421		 seb   $2,$2
52422		 addu  $10,$9,$2
52423		 sb    $10,0x00($24)
52424		 sltu  $16,$10,$2       	 # Set Carry
52425		 xor   $17,$9,$2
52426		 nor   $17,$0,$17
52427		 xor   $25,$10,$9
52428		 and   $17,$17,$25
52429		 srl   $17,$17,7
52430		 andi  $17,$17,0x01     	 # Set Overflow
52431		 seb  $25,$10
52432		 slt   $19,$25,$0        	 # Set Sign
52433		 sltiu $18,$25,1         	 # Set Zero
52434		 or    $20,$0,$16      	 # Copy Carry to X
52435		 addiu $15,$15,-10
52436		 bgez  $15,3f
52437		 lhu   $24,0x00($23)    	 # Delay slot
52438		 j     MainExit
52439	3:
52440		 sll   $7,$24,2         	 # Delay slot
52441		 addu  $7,$7,$30
52442		 lw    $7,0x00($7)
52443		 jr    $7
52444		 nop                    	 # Delay slot
52445
52446OP0_d028:				#:
52447		 addiu $23,$23,2
52448
52449		 andi  $8,$24,0x07
52450		 srl   $24,$24,7
52451		 andi  $24,$24,0x1C
52452		 addu  $24,$24,$21
52453		 lb    $9,0x00($24)
52454		 lh    $7,0x00($23)
52455		 sll   $8,$8,2
52456		 addu  $8,$8,$21
52457		 lw    $14,0x20($8)
52458		 addiu $23,$23,2
52459		 addu  $14,$14,$7
52460		 lw    $25,0x7C($21)
52461		 sw    $15,m68k_ICount
52462		 sw    $9,0x44($29)
52463		 sw    $24,0x40($29)
52464		 or    $4,$0,$14
52465		 jalr  $25
52466		 sw    $23,0x4C($21)    	 # Delay slot
52467		 lw    $24,0x40($29)
52468		 lw    $9,0x44($29)
52469		 lw    $15,m68k_ICount
52470		 seb   $2,$2
52471		 addu  $10,$9,$2
52472		 sb    $10,0x00($24)
52473		 sltu  $16,$10,$2       	 # Set Carry
52474		 xor   $17,$9,$2
52475		 nor   $17,$0,$17
52476		 xor   $25,$10,$9
52477		 and   $17,$17,$25
52478		 srl   $17,$17,7
52479		 andi  $17,$17,0x01     	 # Set Overflow
52480		 seb  $25,$10
52481		 slt   $19,$25,$0        	 # Set Sign
52482		 sltiu $18,$25,1         	 # Set Zero
52483		 or    $20,$0,$16      	 # Copy Carry to X
52484		 addiu $15,$15,-12
52485		 bgez  $15,3f
52486		 lhu   $24,0x00($23)    	 # Delay slot
52487		 j     MainExit
52488	3:
52489		 sll   $7,$24,2         	 # Delay slot
52490		 addu  $7,$7,$30
52491		 lw    $7,0x00($7)
52492		 jr    $7
52493		 nop                    	 # Delay slot
52494
52495OP0_d030:				#:
52496		 addiu $23,$23,2
52497
52498		 andi  $8,$24,0x07
52499		 srl   $24,$24,7
52500		 andi  $24,$24,0x1C
52501		 addu  $24,$24,$21
52502		 lb    $9,0x00($24)
52503		 sll   $8,$8,2
52504		 addu  $8,$8,$21
52505		 lw    $14,0x20($8)
52506		 lhu   $7,0x00($23)
52507		 addiu $23,$23,2
52508		 seb   $6,$7
52509		 or    $25,$0,$7
52510		 srl   $7,$7,12
52511		 andi  $25,$25,0x0800
52512		 sll   $7,$7,2
52513		 addu  $7,$7,$21
52514		 bne   $25,$0,0f
52515		 lw    $25,0x00($7)      	 # Delay slot
52516		 seh   $25,$25
52517	0:
52518		 addu  $25,$14,$25
52519		 addu  $14,$25,$6
52520		 lw    $25,0x7C($21)
52521		 sw    $15,m68k_ICount
52522		 sw    $9,0x44($29)
52523		 sw    $24,0x40($29)
52524		 or    $4,$0,$14
52525		 jalr  $25
52526		 sw    $23,0x4C($21)    	 # Delay slot
52527		 lw    $24,0x40($29)
52528		 lw    $9,0x44($29)
52529		 lw    $15,m68k_ICount
52530		 seb   $2,$2
52531		 addu  $10,$9,$2
52532		 sb    $10,0x00($24)
52533		 sltu  $16,$10,$2       	 # Set Carry
52534		 xor   $17,$9,$2
52535		 nor   $17,$0,$17
52536		 xor   $25,$10,$9
52537		 and   $17,$17,$25
52538		 srl   $17,$17,7
52539		 andi  $17,$17,0x01     	 # Set Overflow
52540		 seb  $25,$10
52541		 slt   $19,$25,$0        	 # Set Sign
52542		 sltiu $18,$25,1         	 # Set Zero
52543		 or    $20,$0,$16      	 # Copy Carry to X
52544		 addiu $15,$15,-14
52545		 bgez  $15,3f
52546		 lhu   $24,0x00($23)    	 # Delay slot
52547		 j     MainExit
52548	3:
52549		 sll   $7,$24,2         	 # Delay slot
52550		 addu  $7,$7,$30
52551		 lw    $7,0x00($7)
52552		 jr    $7
52553		 nop                    	 # Delay slot
52554
52555OP0_d038:				#:
52556		 addiu $23,$23,2
52557
52558		 srl   $24,$24,7
52559		 andi  $24,$24,0x1C
52560		 addu  $24,$24,$21
52561		 lb    $9,0x00($24)
52562		 lh    $14,0x00($23)
52563		 addiu $23,$23,2
52564		 lw    $25,0x7C($21)
52565		 sw    $15,m68k_ICount
52566		 sw    $9,0x44($29)
52567		 sw    $24,0x40($29)
52568		 or    $4,$0,$14
52569		 jalr  $25
52570		 sw    $23,0x4C($21)    	 # Delay slot
52571		 lw    $24,0x40($29)
52572		 lw    $9,0x44($29)
52573		 lw    $15,m68k_ICount
52574		 seb   $2,$2
52575		 addu  $10,$9,$2
52576		 sb    $10,0x00($24)
52577		 sltu  $16,$10,$2       	 # Set Carry
52578		 xor   $17,$9,$2
52579		 nor   $17,$0,$17
52580		 xor   $25,$10,$9
52581		 and   $17,$17,$25
52582		 srl   $17,$17,7
52583		 andi  $17,$17,0x01     	 # Set Overflow
52584		 seb  $25,$10
52585		 slt   $19,$25,$0        	 # Set Sign
52586		 sltiu $18,$25,1         	 # Set Zero
52587		 or    $20,$0,$16      	 # Copy Carry to X
52588		 addiu $15,$15,-12
52589		 bgez  $15,3f
52590		 lhu   $24,0x00($23)    	 # Delay slot
52591		 j     MainExit
52592	3:
52593		 sll   $7,$24,2         	 # Delay slot
52594		 addu  $7,$7,$30
52595		 lw    $7,0x00($7)
52596		 jr    $7
52597		 nop                    	 # Delay slot
52598
52599OP0_d039:				#:
52600		 addiu $23,$23,2
52601
52602		 srl   $24,$24,7
52603		 andi  $24,$24,0x1C
52604		 addu  $24,$24,$21
52605		 lb    $9,0x00($24)
52606		 lhu   $14,0x00($23)
52607		 lhu   $25,0x02($23)
52608		 sll   $14,$14,16
52609		 or    $14,$14,$25
52610		 addiu $23,$23,4
52611		 lw    $25,0x7C($21)
52612		 sw    $15,m68k_ICount
52613		 sw    $9,0x44($29)
52614		 sw    $24,0x40($29)
52615		 or    $4,$0,$14
52616		 jalr  $25
52617		 sw    $23,0x4C($21)    	 # Delay slot
52618		 lw    $24,0x40($29)
52619		 lw    $9,0x44($29)
52620		 lw    $15,m68k_ICount
52621		 seb   $2,$2
52622		 addu  $10,$9,$2
52623		 sb    $10,0x00($24)
52624		 sltu  $16,$10,$2       	 # Set Carry
52625		 xor   $17,$9,$2
52626		 nor   $17,$0,$17
52627		 xor   $25,$10,$9
52628		 and   $17,$17,$25
52629		 srl   $17,$17,7
52630		 andi  $17,$17,0x01     	 # Set Overflow
52631		 seb  $25,$10
52632		 slt   $19,$25,$0        	 # Set Sign
52633		 sltiu $18,$25,1         	 # Set Zero
52634		 or    $20,$0,$16      	 # Copy Carry to X
52635		 addiu $15,$15,-16
52636		 bgez  $15,3f
52637		 lhu   $24,0x00($23)    	 # Delay slot
52638		 j     MainExit
52639	3:
52640		 sll   $7,$24,2         	 # Delay slot
52641		 addu  $7,$7,$30
52642		 lw    $7,0x00($7)
52643		 jr    $7
52644		 nop                    	 # Delay slot
52645
52646OP0_d03a:				#:
52647		 addiu $23,$23,2
52648
52649		 srl   $24,$24,7
52650		 andi  $24,$24,0x1C
52651		 addu  $24,$24,$21
52652		 lb    $9,0x00($24)
52653		 lh    $7,0x00($23)
52654		 subu  $25,$23,$22
52655		 addu  $14,$25,$7       	 # Add Offset to PC
52656		 addiu $23,$23,2
52657		 lw    $25,0x98($21)
52658		 sw    $15,m68k_ICount
52659		 sw    $9,0x44($29)
52660		 sw    $24,0x40($29)
52661		 or    $4,$0,$14
52662		 jalr  $25
52663		 sw    $23,0x4C($21)    	 # Delay slot
52664		 lw    $24,0x40($29)
52665		 lw    $9,0x44($29)
52666		 lw    $15,m68k_ICount
52667		 seb   $2,$2
52668		 addu  $10,$9,$2
52669		 sb    $10,0x00($24)
52670		 sltu  $16,$10,$2       	 # Set Carry
52671		 xor   $17,$9,$2
52672		 nor   $17,$0,$17
52673		 xor   $25,$10,$9
52674		 and   $17,$17,$25
52675		 srl   $17,$17,7
52676		 andi  $17,$17,0x01     	 # Set Overflow
52677		 seb  $25,$10
52678		 slt   $19,$25,$0        	 # Set Sign
52679		 sltiu $18,$25,1         	 # Set Zero
52680		 or    $20,$0,$16      	 # Copy Carry to X
52681		 addiu $15,$15,-12
52682		 bgez  $15,3f
52683		 lhu   $24,0x00($23)    	 # Delay slot
52684		 j     MainExit
52685	3:
52686		 sll   $7,$24,2         	 # Delay slot
52687		 addu  $7,$7,$30
52688		 lw    $7,0x00($7)
52689		 jr    $7
52690		 nop                    	 # Delay slot
52691
52692OP0_d03b:				#:
52693		 addiu $23,$23,2
52694
52695		 srl   $24,$24,7
52696		 andi  $24,$24,0x1C
52697		 addu  $24,$24,$21
52698		 lb    $9,0x00($24)
52699		 subu  $14,$23,$22       	 # Get PC
52700		 lhu   $7,0x00($23)
52701		 addiu $23,$23,2
52702		 seb   $6,$7
52703		 or    $25,$0,$7
52704		 srl   $7,$7,12
52705		 andi  $25,$25,0x0800
52706		 sll   $7,$7,2
52707		 addu  $7,$7,$21
52708		 bne   $25,$0,0f
52709		 lw    $25,0x00($7)      	 # Delay slot
52710		 seh   $25,$25
52711	0:
52712		 addu  $25,$14,$25
52713		 addu  $14,$25,$6
52714		 lw    $25,0x98($21)
52715		 sw    $15,m68k_ICount
52716		 sw    $9,0x44($29)
52717		 sw    $24,0x40($29)
52718		 or    $4,$0,$14
52719		 jalr  $25
52720		 sw    $23,0x4C($21)    	 # Delay slot
52721		 lw    $24,0x40($29)
52722		 lw    $9,0x44($29)
52723		 lw    $15,m68k_ICount
52724		 seb   $2,$2
52725		 addu  $10,$9,$2
52726		 sb    $10,0x00($24)
52727		 sltu  $16,$10,$2       	 # Set Carry
52728		 xor   $17,$9,$2
52729		 nor   $17,$0,$17
52730		 xor   $25,$10,$9
52731		 and   $17,$17,$25
52732		 srl   $17,$17,7
52733		 andi  $17,$17,0x01     	 # Set Overflow
52734		 seb  $25,$10
52735		 slt   $19,$25,$0        	 # Set Sign
52736		 sltiu $18,$25,1         	 # Set Zero
52737		 or    $20,$0,$16      	 # Copy Carry to X
52738		 addiu $15,$15,-14
52739		 bgez  $15,3f
52740		 lhu   $24,0x00($23)    	 # Delay slot
52741		 j     MainExit
52742	3:
52743		 sll   $7,$24,2         	 # Delay slot
52744		 addu  $7,$7,$30
52745		 lw    $7,0x00($7)
52746		 jr    $7
52747		 nop                    	 # Delay slot
52748
52749OP0_d03c:				#:
52750		 addiu $23,$23,2
52751
52752		 srl   $24,$24,7
52753		 andi  $24,$24,0x1C
52754		 addu  $24,$24,$21
52755		 lb    $9,0x00($24)
52756		 lb    $2,0x00($23)
52757		 addiu $23,$23,2
52758		 addu  $10,$9,$2
52759		 sb    $10,0x00($24)
52760		 sltu  $16,$10,$2       	 # Set Carry
52761		 xor   $17,$9,$2
52762		 nor   $17,$0,$17
52763		 xor   $25,$10,$9
52764		 and   $17,$17,$25
52765		 srl   $17,$17,7
52766		 andi  $17,$17,0x01     	 # Set Overflow
52767		 seb  $25,$10
52768		 slt   $19,$25,$0        	 # Set Sign
52769		 sltiu $18,$25,1         	 # Set Zero
52770		 or    $20,$0,$16      	 # Copy Carry to X
52771		 addiu $15,$15,-4
52772		 bgez  $15,3f
52773		 lhu   $24,0x00($23)    	 # Delay slot
52774		 j     MainExit
52775	3:
52776		 sll   $7,$24,2         	 # Delay slot
52777		 addu  $7,$7,$30
52778		 lw    $7,0x00($7)
52779		 jr    $7
52780		 nop                    	 # Delay slot
52781
52782OP0_d040:				#:
52783		 addiu $23,$23,2
52784
52785		 andi  $8,$24,0x0f
52786		 srl   $24,$24,7
52787		 andi  $24,$24,0x1C
52788		 addu  $24,$24,$21
52789		 lh    $9,0x00($24)
52790		 sll   $8,$8,2
52791		 addu  $8,$8,$21
52792		 lh    $2,0x00($8)
52793		 addu  $10,$9,$2
52794		 sh    $10,0x00($24)
52795		 sltu  $16,$10,$2       	 # Set Carry
52796		 xor   $17,$9,$2
52797		 nor   $17,$0,$17
52798		 xor   $25,$10,$9
52799		 and   $17,$17,$25
52800		 srl   $17,$17,15
52801		 andi  $17,$17,0x01     	 # Set Overflow
52802		 seh  $25,$10
52803		 slt   $19,$25,$0        	 # Set Sign
52804		 sltiu $18,$25,1         	 # Set Zero
52805		 or    $20,$0,$16      	 # Copy Carry to X
52806		 addiu $15,$15,-4
52807		 bgez  $15,3f
52808		 lhu   $24,0x00($23)    	 # Delay slot
52809		 j     MainExit
52810	3:
52811		 sll   $7,$24,2         	 # Delay slot
52812		 addu  $7,$7,$30
52813		 lw    $7,0x00($7)
52814		 jr    $7
52815		 nop                    	 # Delay slot
52816
52817OP0_d050:				#:
52818		 addiu $23,$23,2
52819
52820		 andi  $8,$24,0x07
52821		 srl   $24,$24,7
52822		 andi  $24,$24,0x1C
52823		 addu  $24,$24,$21
52824		 lh    $9,0x00($24)
52825		 sll   $8,$8,2
52826		 addu  $8,$8,$21
52827		 lw    $14,0x20($8)
52828		 lw    $25,0x80($21)
52829		 sw    $15,m68k_ICount
52830		 sw    $9,0x44($29)
52831		 sw    $24,0x40($29)
52832		 or    $4,$0,$14
52833		 jalr  $25
52834		 sw    $23,0x4C($21)    	 # Delay slot
52835		 lw    $24,0x40($29)
52836		 lw    $9,0x44($29)
52837		 lw    $15,m68k_ICount
52838		 seh   $2,$2
52839		 addu  $10,$9,$2
52840		 sh    $10,0x00($24)
52841		 sltu  $16,$10,$2       	 # Set Carry
52842		 xor   $17,$9,$2
52843		 nor   $17,$0,$17
52844		 xor   $25,$10,$9
52845		 and   $17,$17,$25
52846		 srl   $17,$17,15
52847		 andi  $17,$17,0x01     	 # Set Overflow
52848		 seh  $25,$10
52849		 slt   $19,$25,$0        	 # Set Sign
52850		 sltiu $18,$25,1         	 # Set Zero
52851		 or    $20,$0,$16      	 # Copy Carry to X
52852		 addiu $15,$15,-8
52853		 bgez  $15,3f
52854		 lhu   $24,0x00($23)    	 # Delay slot
52855		 j     MainExit
52856	3:
52857		 sll   $7,$24,2         	 # Delay slot
52858		 addu  $7,$7,$30
52859		 lw    $7,0x00($7)
52860		 jr    $7
52861		 nop                    	 # Delay slot
52862
52863OP0_d058:				#:
52864		 addiu $23,$23,2
52865
52866		 andi  $8,$24,0x07
52867		 srl   $24,$24,7
52868		 andi  $24,$24,0x1C
52869		 addu  $24,$24,$21
52870		 lh    $9,0x00($24)
52871		 sll   $8,$8,2
52872		 addu  $8,$8,$21
52873		 lw    $14,0x20($8)
52874		 addiu $25,$14,2
52875		 sw    $25,0x20($8)
52876		 lw    $25,0x80($21)
52877		 sw    $15,m68k_ICount
52878		 sw    $9,0x44($29)
52879		 sw    $24,0x40($29)
52880		 or    $4,$0,$14
52881		 jalr  $25
52882		 sw    $23,0x4C($21)    	 # Delay slot
52883		 lw    $24,0x40($29)
52884		 lw    $9,0x44($29)
52885		 lw    $15,m68k_ICount
52886		 seh   $2,$2
52887		 addu  $10,$9,$2
52888		 sh    $10,0x00($24)
52889		 sltu  $16,$10,$2       	 # Set Carry
52890		 xor   $17,$9,$2
52891		 nor   $17,$0,$17
52892		 xor   $25,$10,$9
52893		 and   $17,$17,$25
52894		 srl   $17,$17,15
52895		 andi  $17,$17,0x01     	 # Set Overflow
52896		 seh  $25,$10
52897		 slt   $19,$25,$0        	 # Set Sign
52898		 sltiu $18,$25,1         	 # Set Zero
52899		 or    $20,$0,$16      	 # Copy Carry to X
52900		 addiu $15,$15,-8
52901		 bgez  $15,3f
52902		 lhu   $24,0x00($23)    	 # Delay slot
52903		 j     MainExit
52904	3:
52905		 sll   $7,$24,2         	 # Delay slot
52906		 addu  $7,$7,$30
52907		 lw    $7,0x00($7)
52908		 jr    $7
52909		 nop                    	 # Delay slot
52910
52911OP0_d060:				#:
52912		 addiu $23,$23,2
52913
52914		 andi  $8,$24,0x07
52915		 srl   $24,$24,7
52916		 andi  $24,$24,0x1C
52917		 addu  $24,$24,$21
52918		 lh    $9,0x00($24)
52919		 sll   $8,$8,2
52920		 addu  $8,$8,$21
52921		 lw    $14,0x20($8)
52922		 addiu $14,$14,-2
52923		 sw    $14,0x20($8)
52924		 lw    $25,0x80($21)
52925		 sw    $15,m68k_ICount
52926		 sw    $9,0x44($29)
52927		 sw    $24,0x40($29)
52928		 or    $4,$0,$14
52929		 jalr  $25
52930		 sw    $23,0x4C($21)    	 # Delay slot
52931		 lw    $24,0x40($29)
52932		 lw    $9,0x44($29)
52933		 lw    $15,m68k_ICount
52934		 seh   $2,$2
52935		 addu  $10,$9,$2
52936		 sh    $10,0x00($24)
52937		 sltu  $16,$10,$2       	 # Set Carry
52938		 xor   $17,$9,$2
52939		 nor   $17,$0,$17
52940		 xor   $25,$10,$9
52941		 and   $17,$17,$25
52942		 srl   $17,$17,15
52943		 andi  $17,$17,0x01     	 # Set Overflow
52944		 seh  $25,$10
52945		 slt   $19,$25,$0        	 # Set Sign
52946		 sltiu $18,$25,1         	 # Set Zero
52947		 or    $20,$0,$16      	 # Copy Carry to X
52948		 addiu $15,$15,-10
52949		 bgez  $15,3f
52950		 lhu   $24,0x00($23)    	 # Delay slot
52951		 j     MainExit
52952	3:
52953		 sll   $7,$24,2         	 # Delay slot
52954		 addu  $7,$7,$30
52955		 lw    $7,0x00($7)
52956		 jr    $7
52957		 nop                    	 # Delay slot
52958
52959OP0_d068:				#:
52960		 addiu $23,$23,2
52961
52962		 andi  $8,$24,0x07
52963		 srl   $24,$24,7
52964		 andi  $24,$24,0x1C
52965		 addu  $24,$24,$21
52966		 lh    $9,0x00($24)
52967		 lh    $7,0x00($23)
52968		 sll   $8,$8,2
52969		 addu  $8,$8,$21
52970		 lw    $14,0x20($8)
52971		 addiu $23,$23,2
52972		 addu  $14,$14,$7
52973		 lw    $25,0x80($21)
52974		 sw    $15,m68k_ICount
52975		 sw    $9,0x44($29)
52976		 sw    $24,0x40($29)
52977		 or    $4,$0,$14
52978		 jalr  $25
52979		 sw    $23,0x4C($21)    	 # Delay slot
52980		 lw    $24,0x40($29)
52981		 lw    $9,0x44($29)
52982		 lw    $15,m68k_ICount
52983		 seh   $2,$2
52984		 addu  $10,$9,$2
52985		 sh    $10,0x00($24)
52986		 sltu  $16,$10,$2       	 # Set Carry
52987		 xor   $17,$9,$2
52988		 nor   $17,$0,$17
52989		 xor   $25,$10,$9
52990		 and   $17,$17,$25
52991		 srl   $17,$17,15
52992		 andi  $17,$17,0x01     	 # Set Overflow
52993		 seh  $25,$10
52994		 slt   $19,$25,$0        	 # Set Sign
52995		 sltiu $18,$25,1         	 # Set Zero
52996		 or    $20,$0,$16      	 # Copy Carry to X
52997		 addiu $15,$15,-12
52998		 bgez  $15,3f
52999		 lhu   $24,0x00($23)    	 # Delay slot
53000		 j     MainExit
53001	3:
53002		 sll   $7,$24,2         	 # Delay slot
53003		 addu  $7,$7,$30
53004		 lw    $7,0x00($7)
53005		 jr    $7
53006		 nop                    	 # Delay slot
53007
53008OP0_d070:				#:
53009		 addiu $23,$23,2
53010
53011		 andi  $8,$24,0x07
53012		 srl   $24,$24,7
53013		 andi  $24,$24,0x1C
53014		 addu  $24,$24,$21
53015		 lh    $9,0x00($24)
53016		 sll   $8,$8,2
53017		 addu  $8,$8,$21
53018		 lw    $14,0x20($8)
53019		 lhu   $7,0x00($23)
53020		 addiu $23,$23,2
53021		 seb   $6,$7
53022		 or    $25,$0,$7
53023		 srl   $7,$7,12
53024		 andi  $25,$25,0x0800
53025		 sll   $7,$7,2
53026		 addu  $7,$7,$21
53027		 bne   $25,$0,0f
53028		 lw    $25,0x00($7)      	 # Delay slot
53029		 seh   $25,$25
53030	0:
53031		 addu  $25,$14,$25
53032		 addu  $14,$25,$6
53033		 lw    $25,0x80($21)
53034		 sw    $15,m68k_ICount
53035		 sw    $9,0x44($29)
53036		 sw    $24,0x40($29)
53037		 or    $4,$0,$14
53038		 jalr  $25
53039		 sw    $23,0x4C($21)    	 # Delay slot
53040		 lw    $24,0x40($29)
53041		 lw    $9,0x44($29)
53042		 lw    $15,m68k_ICount
53043		 seh   $2,$2
53044		 addu  $10,$9,$2
53045		 sh    $10,0x00($24)
53046		 sltu  $16,$10,$2       	 # Set Carry
53047		 xor   $17,$9,$2
53048		 nor   $17,$0,$17
53049		 xor   $25,$10,$9
53050		 and   $17,$17,$25
53051		 srl   $17,$17,15
53052		 andi  $17,$17,0x01     	 # Set Overflow
53053		 seh  $25,$10
53054		 slt   $19,$25,$0        	 # Set Sign
53055		 sltiu $18,$25,1         	 # Set Zero
53056		 or    $20,$0,$16      	 # Copy Carry to X
53057		 addiu $15,$15,-14
53058		 bgez  $15,3f
53059		 lhu   $24,0x00($23)    	 # Delay slot
53060		 j     MainExit
53061	3:
53062		 sll   $7,$24,2         	 # Delay slot
53063		 addu  $7,$7,$30
53064		 lw    $7,0x00($7)
53065		 jr    $7
53066		 nop                    	 # Delay slot
53067
53068OP0_d078:				#:
53069		 addiu $23,$23,2
53070
53071		 srl   $24,$24,7
53072		 andi  $24,$24,0x1C
53073		 addu  $24,$24,$21
53074		 lh    $9,0x00($24)
53075		 lh    $14,0x00($23)
53076		 addiu $23,$23,2
53077		 lw    $25,0x80($21)
53078		 sw    $15,m68k_ICount
53079		 sw    $9,0x44($29)
53080		 sw    $24,0x40($29)
53081		 or    $4,$0,$14
53082		 jalr  $25
53083		 sw    $23,0x4C($21)    	 # Delay slot
53084		 lw    $24,0x40($29)
53085		 lw    $9,0x44($29)
53086		 lw    $15,m68k_ICount
53087		 seh   $2,$2
53088		 addu  $10,$9,$2
53089		 sh    $10,0x00($24)
53090		 sltu  $16,$10,$2       	 # Set Carry
53091		 xor   $17,$9,$2
53092		 nor   $17,$0,$17
53093		 xor   $25,$10,$9
53094		 and   $17,$17,$25
53095		 srl   $17,$17,15
53096		 andi  $17,$17,0x01     	 # Set Overflow
53097		 seh  $25,$10
53098		 slt   $19,$25,$0        	 # Set Sign
53099		 sltiu $18,$25,1         	 # Set Zero
53100		 or    $20,$0,$16      	 # Copy Carry to X
53101		 addiu $15,$15,-12
53102		 bgez  $15,3f
53103		 lhu   $24,0x00($23)    	 # Delay slot
53104		 j     MainExit
53105	3:
53106		 sll   $7,$24,2         	 # Delay slot
53107		 addu  $7,$7,$30
53108		 lw    $7,0x00($7)
53109		 jr    $7
53110		 nop                    	 # Delay slot
53111
53112OP0_d079:				#:
53113		 addiu $23,$23,2
53114
53115		 srl   $24,$24,7
53116		 andi  $24,$24,0x1C
53117		 addu  $24,$24,$21
53118		 lh    $9,0x00($24)
53119		 lhu   $14,0x00($23)
53120		 lhu   $25,0x02($23)
53121		 sll   $14,$14,16
53122		 or    $14,$14,$25
53123		 addiu $23,$23,4
53124		 lw    $25,0x80($21)
53125		 sw    $15,m68k_ICount
53126		 sw    $9,0x44($29)
53127		 sw    $24,0x40($29)
53128		 or    $4,$0,$14
53129		 jalr  $25
53130		 sw    $23,0x4C($21)    	 # Delay slot
53131		 lw    $24,0x40($29)
53132		 lw    $9,0x44($29)
53133		 lw    $15,m68k_ICount
53134		 seh   $2,$2
53135		 addu  $10,$9,$2
53136		 sh    $10,0x00($24)
53137		 sltu  $16,$10,$2       	 # Set Carry
53138		 xor   $17,$9,$2
53139		 nor   $17,$0,$17
53140		 xor   $25,$10,$9
53141		 and   $17,$17,$25
53142		 srl   $17,$17,15
53143		 andi  $17,$17,0x01     	 # Set Overflow
53144		 seh  $25,$10
53145		 slt   $19,$25,$0        	 # Set Sign
53146		 sltiu $18,$25,1         	 # Set Zero
53147		 or    $20,$0,$16      	 # Copy Carry to X
53148		 addiu $15,$15,-16
53149		 bgez  $15,3f
53150		 lhu   $24,0x00($23)    	 # Delay slot
53151		 j     MainExit
53152	3:
53153		 sll   $7,$24,2         	 # Delay slot
53154		 addu  $7,$7,$30
53155		 lw    $7,0x00($7)
53156		 jr    $7
53157		 nop                    	 # Delay slot
53158
53159OP0_d07a:				#:
53160		 addiu $23,$23,2
53161
53162		 srl   $24,$24,7
53163		 andi  $24,$24,0x1C
53164		 addu  $24,$24,$21
53165		 lh    $9,0x00($24)
53166		 lh    $7,0x00($23)
53167		 subu  $25,$23,$22
53168		 addu  $14,$25,$7       	 # Add Offset to PC
53169		 addiu $23,$23,2
53170		 lw    $25,0x9C($21)
53171		 sw    $15,m68k_ICount
53172		 sw    $9,0x44($29)
53173		 sw    $24,0x40($29)
53174		 or    $4,$0,$14
53175		 jalr  $25
53176		 sw    $23,0x4C($21)    	 # Delay slot
53177		 lw    $24,0x40($29)
53178		 lw    $9,0x44($29)
53179		 lw    $15,m68k_ICount
53180		 seh   $2,$2
53181		 addu  $10,$9,$2
53182		 sh    $10,0x00($24)
53183		 sltu  $16,$10,$2       	 # Set Carry
53184		 xor   $17,$9,$2
53185		 nor   $17,$0,$17
53186		 xor   $25,$10,$9
53187		 and   $17,$17,$25
53188		 srl   $17,$17,15
53189		 andi  $17,$17,0x01     	 # Set Overflow
53190		 seh  $25,$10
53191		 slt   $19,$25,$0        	 # Set Sign
53192		 sltiu $18,$25,1         	 # Set Zero
53193		 or    $20,$0,$16      	 # Copy Carry to X
53194		 addiu $15,$15,-12
53195		 bgez  $15,3f
53196		 lhu   $24,0x00($23)    	 # Delay slot
53197		 j     MainExit
53198	3:
53199		 sll   $7,$24,2         	 # Delay slot
53200		 addu  $7,$7,$30
53201		 lw    $7,0x00($7)
53202		 jr    $7
53203		 nop                    	 # Delay slot
53204
53205OP0_d07b:				#:
53206		 addiu $23,$23,2
53207
53208		 srl   $24,$24,7
53209		 andi  $24,$24,0x1C
53210		 addu  $24,$24,$21
53211		 lh    $9,0x00($24)
53212		 subu  $14,$23,$22       	 # Get PC
53213		 lhu   $7,0x00($23)
53214		 addiu $23,$23,2
53215		 seb   $6,$7
53216		 or    $25,$0,$7
53217		 srl   $7,$7,12
53218		 andi  $25,$25,0x0800
53219		 sll   $7,$7,2
53220		 addu  $7,$7,$21
53221		 bne   $25,$0,0f
53222		 lw    $25,0x00($7)      	 # Delay slot
53223		 seh   $25,$25
53224	0:
53225		 addu  $25,$14,$25
53226		 addu  $14,$25,$6
53227		 lw    $25,0x9C($21)
53228		 sw    $15,m68k_ICount
53229		 sw    $9,0x44($29)
53230		 sw    $24,0x40($29)
53231		 or    $4,$0,$14
53232		 jalr  $25
53233		 sw    $23,0x4C($21)    	 # Delay slot
53234		 lw    $24,0x40($29)
53235		 lw    $9,0x44($29)
53236		 lw    $15,m68k_ICount
53237		 seh   $2,$2
53238		 addu  $10,$9,$2
53239		 sh    $10,0x00($24)
53240		 sltu  $16,$10,$2       	 # Set Carry
53241		 xor   $17,$9,$2
53242		 nor   $17,$0,$17
53243		 xor   $25,$10,$9
53244		 and   $17,$17,$25
53245		 srl   $17,$17,15
53246		 andi  $17,$17,0x01     	 # Set Overflow
53247		 seh  $25,$10
53248		 slt   $19,$25,$0        	 # Set Sign
53249		 sltiu $18,$25,1         	 # Set Zero
53250		 or    $20,$0,$16      	 # Copy Carry to X
53251		 addiu $15,$15,-14
53252		 bgez  $15,3f
53253		 lhu   $24,0x00($23)    	 # Delay slot
53254		 j     MainExit
53255	3:
53256		 sll   $7,$24,2         	 # Delay slot
53257		 addu  $7,$7,$30
53258		 lw    $7,0x00($7)
53259		 jr    $7
53260		 nop                    	 # Delay slot
53261
53262OP0_d07c:				#:
53263		 addiu $23,$23,2
53264
53265		 srl   $24,$24,7
53266		 andi  $24,$24,0x1C
53267		 addu  $24,$24,$21
53268		 lh    $9,0x00($24)
53269		 lh    $2,0x00($23)
53270		 addiu $23,$23,2
53271		 addu  $10,$9,$2
53272		 sh    $10,0x00($24)
53273		 sltu  $16,$10,$2       	 # Set Carry
53274		 xor   $17,$9,$2
53275		 nor   $17,$0,$17
53276		 xor   $25,$10,$9
53277		 and   $17,$17,$25
53278		 srl   $17,$17,15
53279		 andi  $17,$17,0x01     	 # Set Overflow
53280		 seh  $25,$10
53281		 slt   $19,$25,$0        	 # Set Sign
53282		 sltiu $18,$25,1         	 # Set Zero
53283		 or    $20,$0,$16      	 # Copy Carry to X
53284		 addiu $15,$15,-4
53285		 bgez  $15,3f
53286		 lhu   $24,0x00($23)    	 # Delay slot
53287		 j     MainExit
53288	3:
53289		 sll   $7,$24,2         	 # Delay slot
53290		 addu  $7,$7,$30
53291		 lw    $7,0x00($7)
53292		 jr    $7
53293		 nop                    	 # Delay slot
53294
53295OP0_d080:				#:
53296		 addiu $23,$23,2
53297
53298		 andi  $8,$24,0x0f
53299		 srl   $24,$24,7
53300		 andi  $24,$24,0x1C
53301		 addu  $24,$24,$21
53302		 lw    $9,0x00($24)
53303		 sll   $8,$8,2
53304		 addu  $8,$8,$21
53305		 lw    $2,0x00($8)
53306		 addu  $10,$9,$2
53307		 sw    $10,0x00($24)
53308		 sltu  $16,$10,$2       	 # Set Carry
53309		 xor   $17,$9,$2
53310		 nor   $17,$0,$17
53311		 xor   $25,$10,$9
53312		 and   $17,$17,$25
53313		 srl   $17,$17,31        	 # Set Overflow
53314		 slt   $19,$10,$0        	 # Set Sign
53315		 sltiu $18,$10,1         	 # Set Zero
53316		 or    $20,$0,$16      	 # Copy Carry to X
53317		 addiu $15,$15,-8
53318		 bgez  $15,3f
53319		 lhu   $24,0x00($23)    	 # Delay slot
53320		 j     MainExit
53321	3:
53322		 sll   $7,$24,2         	 # Delay slot
53323		 addu  $7,$7,$30
53324		 lw    $7,0x00($7)
53325		 jr    $7
53326		 nop                    	 # Delay slot
53327
53328OP0_d090:				#:
53329		 addiu $23,$23,2
53330
53331		 andi  $8,$24,0x07
53332		 srl   $24,$24,7
53333		 andi  $24,$24,0x1C
53334		 addu  $24,$24,$21
53335		 lw    $9,0x00($24)
53336		 sll   $8,$8,2
53337		 addu  $8,$8,$21
53338		 lw    $14,0x20($8)
53339		 lw    $25,0x84($21)
53340		 sw    $15,m68k_ICount
53341		 sw    $9,0x44($29)
53342		 sw    $24,0x40($29)
53343		 or    $4,$0,$14
53344		 jalr  $25
53345		 sw    $23,0x4C($21)    	 # Delay slot
53346		 lw    $24,0x40($29)
53347		 lw    $9,0x44($29)
53348		 lw    $15,m68k_ICount
53349		 addu  $10,$9,$2
53350		 sw    $10,0x00($24)
53351		 sltu  $16,$10,$2       	 # Set Carry
53352		 xor   $17,$9,$2
53353		 nor   $17,$0,$17
53354		 xor   $25,$10,$9
53355		 and   $17,$17,$25
53356		 srl   $17,$17,31        	 # Set Overflow
53357		 slt   $19,$10,$0        	 # Set Sign
53358		 sltiu $18,$10,1         	 # Set Zero
53359		 or    $20,$0,$16      	 # Copy Carry to X
53360		 addiu $15,$15,-14
53361		 bgez  $15,3f
53362		 lhu   $24,0x00($23)    	 # Delay slot
53363		 j     MainExit
53364	3:
53365		 sll   $7,$24,2         	 # Delay slot
53366		 addu  $7,$7,$30
53367		 lw    $7,0x00($7)
53368		 jr    $7
53369		 nop                    	 # Delay slot
53370
53371OP0_d098:				#:
53372		 addiu $23,$23,2
53373
53374		 andi  $8,$24,0x07
53375		 srl   $24,$24,7
53376		 andi  $24,$24,0x1C
53377		 addu  $24,$24,$21
53378		 lw    $9,0x00($24)
53379		 sll   $8,$8,2
53380		 addu  $8,$8,$21
53381		 lw    $14,0x20($8)
53382		 addiu $25,$14,4
53383		 sw    $25,0x20($8)
53384		 lw    $25,0x84($21)
53385		 sw    $15,m68k_ICount
53386		 sw    $9,0x44($29)
53387		 sw    $24,0x40($29)
53388		 or    $4,$0,$14
53389		 jalr  $25
53390		 sw    $23,0x4C($21)    	 # Delay slot
53391		 lw    $24,0x40($29)
53392		 lw    $9,0x44($29)
53393		 lw    $15,m68k_ICount
53394		 addu  $10,$9,$2
53395		 sw    $10,0x00($24)
53396		 sltu  $16,$10,$2       	 # Set Carry
53397		 xor   $17,$9,$2
53398		 nor   $17,$0,$17
53399		 xor   $25,$10,$9
53400		 and   $17,$17,$25
53401		 srl   $17,$17,31        	 # Set Overflow
53402		 slt   $19,$10,$0        	 # Set Sign
53403		 sltiu $18,$10,1         	 # Set Zero
53404		 or    $20,$0,$16      	 # Copy Carry to X
53405		 addiu $15,$15,-14
53406		 bgez  $15,3f
53407		 lhu   $24,0x00($23)    	 # Delay slot
53408		 j     MainExit
53409	3:
53410		 sll   $7,$24,2         	 # Delay slot
53411		 addu  $7,$7,$30
53412		 lw    $7,0x00($7)
53413		 jr    $7
53414		 nop                    	 # Delay slot
53415
53416OP0_d0a0:				#:
53417		 addiu $23,$23,2
53418
53419		 andi  $8,$24,0x07
53420		 srl   $24,$24,7
53421		 andi  $24,$24,0x1C
53422		 addu  $24,$24,$21
53423		 lw    $9,0x00($24)
53424		 sll   $8,$8,2
53425		 addu  $8,$8,$21
53426		 lw    $14,0x20($8)
53427		 addiu $14,$14,-4
53428		 sw    $14,0x20($8)
53429		 lw    $25,0x84($21)
53430		 sw    $15,m68k_ICount
53431		 sw    $9,0x44($29)
53432		 sw    $24,0x40($29)
53433		 or    $4,$0,$14
53434		 jalr  $25
53435		 sw    $23,0x4C($21)    	 # Delay slot
53436		 lw    $24,0x40($29)
53437		 lw    $9,0x44($29)
53438		 lw    $15,m68k_ICount
53439		 addu  $10,$9,$2
53440		 sw    $10,0x00($24)
53441		 sltu  $16,$10,$2       	 # Set Carry
53442		 xor   $17,$9,$2
53443		 nor   $17,$0,$17
53444		 xor   $25,$10,$9
53445		 and   $17,$17,$25
53446		 srl   $17,$17,31        	 # Set Overflow
53447		 slt   $19,$10,$0        	 # Set Sign
53448		 sltiu $18,$10,1         	 # Set Zero
53449		 or    $20,$0,$16      	 # Copy Carry to X
53450		 addiu $15,$15,-16
53451		 bgez  $15,3f
53452		 lhu   $24,0x00($23)    	 # Delay slot
53453		 j     MainExit
53454	3:
53455		 sll   $7,$24,2         	 # Delay slot
53456		 addu  $7,$7,$30
53457		 lw    $7,0x00($7)
53458		 jr    $7
53459		 nop                    	 # Delay slot
53460
53461OP0_d0a8:				#:
53462		 addiu $23,$23,2
53463
53464		 andi  $8,$24,0x07
53465		 srl   $24,$24,7
53466		 andi  $24,$24,0x1C
53467		 addu  $24,$24,$21
53468		 lw    $9,0x00($24)
53469		 lh    $7,0x00($23)
53470		 sll   $8,$8,2
53471		 addu  $8,$8,$21
53472		 lw    $14,0x20($8)
53473		 addiu $23,$23,2
53474		 addu  $14,$14,$7
53475		 lw    $25,0x84($21)
53476		 sw    $15,m68k_ICount
53477		 sw    $9,0x44($29)
53478		 sw    $24,0x40($29)
53479		 or    $4,$0,$14
53480		 jalr  $25
53481		 sw    $23,0x4C($21)    	 # Delay slot
53482		 lw    $24,0x40($29)
53483		 lw    $9,0x44($29)
53484		 lw    $15,m68k_ICount
53485		 addu  $10,$9,$2
53486		 sw    $10,0x00($24)
53487		 sltu  $16,$10,$2       	 # Set Carry
53488		 xor   $17,$9,$2
53489		 nor   $17,$0,$17
53490		 xor   $25,$10,$9
53491		 and   $17,$17,$25
53492		 srl   $17,$17,31        	 # Set Overflow
53493		 slt   $19,$10,$0        	 # Set Sign
53494		 sltiu $18,$10,1         	 # Set Zero
53495		 or    $20,$0,$16      	 # Copy Carry to X
53496		 addiu $15,$15,-18
53497		 bgez  $15,3f
53498		 lhu   $24,0x00($23)    	 # Delay slot
53499		 j     MainExit
53500	3:
53501		 sll   $7,$24,2         	 # Delay slot
53502		 addu  $7,$7,$30
53503		 lw    $7,0x00($7)
53504		 jr    $7
53505		 nop                    	 # Delay slot
53506
53507OP0_d0b0:				#:
53508		 addiu $23,$23,2
53509
53510		 andi  $8,$24,0x07
53511		 srl   $24,$24,7
53512		 andi  $24,$24,0x1C
53513		 addu  $24,$24,$21
53514		 lw    $9,0x00($24)
53515		 sll   $8,$8,2
53516		 addu  $8,$8,$21
53517		 lw    $14,0x20($8)
53518		 lhu   $7,0x00($23)
53519		 addiu $23,$23,2
53520		 seb   $6,$7
53521		 or    $25,$0,$7
53522		 srl   $7,$7,12
53523		 andi  $25,$25,0x0800
53524		 sll   $7,$7,2
53525		 addu  $7,$7,$21
53526		 bne   $25,$0,0f
53527		 lw    $25,0x00($7)      	 # Delay slot
53528		 seh   $25,$25
53529	0:
53530		 addu  $25,$14,$25
53531		 addu  $14,$25,$6
53532		 lw    $25,0x84($21)
53533		 sw    $15,m68k_ICount
53534		 sw    $9,0x44($29)
53535		 sw    $24,0x40($29)
53536		 or    $4,$0,$14
53537		 jalr  $25
53538		 sw    $23,0x4C($21)    	 # Delay slot
53539		 lw    $24,0x40($29)
53540		 lw    $9,0x44($29)
53541		 lw    $15,m68k_ICount
53542		 addu  $10,$9,$2
53543		 sw    $10,0x00($24)
53544		 sltu  $16,$10,$2       	 # Set Carry
53545		 xor   $17,$9,$2
53546		 nor   $17,$0,$17
53547		 xor   $25,$10,$9
53548		 and   $17,$17,$25
53549		 srl   $17,$17,31        	 # Set Overflow
53550		 slt   $19,$10,$0        	 # Set Sign
53551		 sltiu $18,$10,1         	 # Set Zero
53552		 or    $20,$0,$16      	 # Copy Carry to X
53553		 addiu $15,$15,-20
53554		 bgez  $15,3f
53555		 lhu   $24,0x00($23)    	 # Delay slot
53556		 j     MainExit
53557	3:
53558		 sll   $7,$24,2         	 # Delay slot
53559		 addu  $7,$7,$30
53560		 lw    $7,0x00($7)
53561		 jr    $7
53562		 nop                    	 # Delay slot
53563
53564OP0_d0b8:				#:
53565		 addiu $23,$23,2
53566
53567		 srl   $24,$24,7
53568		 andi  $24,$24,0x1C
53569		 addu  $24,$24,$21
53570		 lw    $9,0x00($24)
53571		 lh    $14,0x00($23)
53572		 addiu $23,$23,2
53573		 lw    $25,0x84($21)
53574		 sw    $15,m68k_ICount
53575		 sw    $9,0x44($29)
53576		 sw    $24,0x40($29)
53577		 or    $4,$0,$14
53578		 jalr  $25
53579		 sw    $23,0x4C($21)    	 # Delay slot
53580		 lw    $24,0x40($29)
53581		 lw    $9,0x44($29)
53582		 lw    $15,m68k_ICount
53583		 addu  $10,$9,$2
53584		 sw    $10,0x00($24)
53585		 sltu  $16,$10,$2       	 # Set Carry
53586		 xor   $17,$9,$2
53587		 nor   $17,$0,$17
53588		 xor   $25,$10,$9
53589		 and   $17,$17,$25
53590		 srl   $17,$17,31        	 # Set Overflow
53591		 slt   $19,$10,$0        	 # Set Sign
53592		 sltiu $18,$10,1         	 # Set Zero
53593		 or    $20,$0,$16      	 # Copy Carry to X
53594		 addiu $15,$15,-18
53595		 bgez  $15,3f
53596		 lhu   $24,0x00($23)    	 # Delay slot
53597		 j     MainExit
53598	3:
53599		 sll   $7,$24,2         	 # Delay slot
53600		 addu  $7,$7,$30
53601		 lw    $7,0x00($7)
53602		 jr    $7
53603		 nop                    	 # Delay slot
53604
53605OP0_d0b9:				#:
53606		 addiu $23,$23,2
53607
53608		 srl   $24,$24,7
53609		 andi  $24,$24,0x1C
53610		 addu  $24,$24,$21
53611		 lw    $9,0x00($24)
53612		 lhu   $14,0x00($23)
53613		 lhu   $25,0x02($23)
53614		 sll   $14,$14,16
53615		 or    $14,$14,$25
53616		 addiu $23,$23,4
53617		 lw    $25,0x84($21)
53618		 sw    $15,m68k_ICount
53619		 sw    $9,0x44($29)
53620		 sw    $24,0x40($29)
53621		 or    $4,$0,$14
53622		 jalr  $25
53623		 sw    $23,0x4C($21)    	 # Delay slot
53624		 lw    $24,0x40($29)
53625		 lw    $9,0x44($29)
53626		 lw    $15,m68k_ICount
53627		 addu  $10,$9,$2
53628		 sw    $10,0x00($24)
53629		 sltu  $16,$10,$2       	 # Set Carry
53630		 xor   $17,$9,$2
53631		 nor   $17,$0,$17
53632		 xor   $25,$10,$9
53633		 and   $17,$17,$25
53634		 srl   $17,$17,31        	 # Set Overflow
53635		 slt   $19,$10,$0        	 # Set Sign
53636		 sltiu $18,$10,1         	 # Set Zero
53637		 or    $20,$0,$16      	 # Copy Carry to X
53638		 addiu $15,$15,-22
53639		 bgez  $15,3f
53640		 lhu   $24,0x00($23)    	 # Delay slot
53641		 j     MainExit
53642	3:
53643		 sll   $7,$24,2         	 # Delay slot
53644		 addu  $7,$7,$30
53645		 lw    $7,0x00($7)
53646		 jr    $7
53647		 nop                    	 # Delay slot
53648
53649OP0_d0ba:				#:
53650		 addiu $23,$23,2
53651
53652		 srl   $24,$24,7
53653		 andi  $24,$24,0x1C
53654		 addu  $24,$24,$21
53655		 lw    $9,0x00($24)
53656		 lh    $7,0x00($23)
53657		 subu  $25,$23,$22
53658		 addu  $14,$25,$7       	 # Add Offset to PC
53659		 addiu $23,$23,2
53660		 lw    $25,0xA0($21)
53661		 sw    $15,m68k_ICount
53662		 sw    $9,0x44($29)
53663		 sw    $24,0x40($29)
53664		 or    $4,$0,$14
53665		 jalr  $25
53666		 sw    $23,0x4C($21)    	 # Delay slot
53667		 lw    $24,0x40($29)
53668		 lw    $9,0x44($29)
53669		 lw    $15,m68k_ICount
53670		 addu  $10,$9,$2
53671		 sw    $10,0x00($24)
53672		 sltu  $16,$10,$2       	 # Set Carry
53673		 xor   $17,$9,$2
53674		 nor   $17,$0,$17
53675		 xor   $25,$10,$9
53676		 and   $17,$17,$25
53677		 srl   $17,$17,31        	 # Set Overflow
53678		 slt   $19,$10,$0        	 # Set Sign
53679		 sltiu $18,$10,1         	 # Set Zero
53680		 or    $20,$0,$16      	 # Copy Carry to X
53681		 addiu $15,$15,-18
53682		 bgez  $15,3f
53683		 lhu   $24,0x00($23)    	 # Delay slot
53684		 j     MainExit
53685	3:
53686		 sll   $7,$24,2         	 # Delay slot
53687		 addu  $7,$7,$30
53688		 lw    $7,0x00($7)
53689		 jr    $7
53690		 nop                    	 # Delay slot
53691
53692OP0_d0bb:				#:
53693		 addiu $23,$23,2
53694
53695		 srl   $24,$24,7
53696		 andi  $24,$24,0x1C
53697		 addu  $24,$24,$21
53698		 lw    $9,0x00($24)
53699		 subu  $14,$23,$22       	 # Get PC
53700		 lhu   $7,0x00($23)
53701		 addiu $23,$23,2
53702		 seb   $6,$7
53703		 or    $25,$0,$7
53704		 srl   $7,$7,12
53705		 andi  $25,$25,0x0800
53706		 sll   $7,$7,2
53707		 addu  $7,$7,$21
53708		 bne   $25,$0,0f
53709		 lw    $25,0x00($7)      	 # Delay slot
53710		 seh   $25,$25
53711	0:
53712		 addu  $25,$14,$25
53713		 addu  $14,$25,$6
53714		 lw    $25,0xA0($21)
53715		 sw    $15,m68k_ICount
53716		 sw    $9,0x44($29)
53717		 sw    $24,0x40($29)
53718		 or    $4,$0,$14
53719		 jalr  $25
53720		 sw    $23,0x4C($21)    	 # Delay slot
53721		 lw    $24,0x40($29)
53722		 lw    $9,0x44($29)
53723		 lw    $15,m68k_ICount
53724		 addu  $10,$9,$2
53725		 sw    $10,0x00($24)
53726		 sltu  $16,$10,$2       	 # Set Carry
53727		 xor   $17,$9,$2
53728		 nor   $17,$0,$17
53729		 xor   $25,$10,$9
53730		 and   $17,$17,$25
53731		 srl   $17,$17,31        	 # Set Overflow
53732		 slt   $19,$10,$0        	 # Set Sign
53733		 sltiu $18,$10,1         	 # Set Zero
53734		 or    $20,$0,$16      	 # Copy Carry to X
53735		 addiu $15,$15,-20
53736		 bgez  $15,3f
53737		 lhu   $24,0x00($23)    	 # Delay slot
53738		 j     MainExit
53739	3:
53740		 sll   $7,$24,2         	 # Delay slot
53741		 addu  $7,$7,$30
53742		 lw    $7,0x00($7)
53743		 jr    $7
53744		 nop                    	 # Delay slot
53745
53746OP0_d0bc:				#:
53747		 addiu $23,$23,2
53748
53749		 srl   $24,$24,7
53750		 andi  $24,$24,0x1C
53751		 addu  $24,$24,$21
53752		 lw    $9,0x00($24)
53753		 lhu   $2,0x00($23)
53754		 lhu   $25,0x02($23)
53755		 sll   $2,$2,16
53756		 or    $2,$2,$25
53757		 addiu $23,$23,4
53758		 addu  $10,$9,$2
53759		 sw    $10,0x00($24)
53760		 sltu  $16,$10,$2       	 # Set Carry
53761		 xor   $17,$9,$2
53762		 nor   $17,$0,$17
53763		 xor   $25,$10,$9
53764		 and   $17,$17,$25
53765		 srl   $17,$17,31        	 # Set Overflow
53766		 slt   $19,$10,$0        	 # Set Sign
53767		 sltiu $18,$10,1         	 # Set Zero
53768		 or    $20,$0,$16      	 # Copy Carry to X
53769		 addiu $15,$15,-6
53770		 bgez  $15,3f
53771		 lhu   $24,0x00($23)    	 # Delay slot
53772		 j     MainExit
53773	3:
53774		 sll   $7,$24,2         	 # Delay slot
53775		 addu  $7,$7,$30
53776		 lw    $7,0x00($7)
53777		 jr    $7
53778		 nop                    	 # Delay slot
53779
53780OP0_d110:				#:
53781		 addiu $23,$23,2
53782
53783		 andi  $8,$24,0x07
53784		 srl   $24,$24,7
53785		 andi  $24,$24,0x1C
53786		 addu  $24,$24,$21
53787		 lb    $9,0x00($24)
53788		 sll   $8,$8,2
53789		 addu  $8,$8,$21
53790		 lw    $14,0x20($8)
53791		 lw    $25,0x7C($21)
53792		 sw    $15,m68k_ICount
53793		 sw    $9,0x44($29)
53794		 sw    $14,0x40($29)
53795		 sw    $24,0x3C($29)
53796		 or    $4,$0,$14
53797		 jalr  $25
53798		 sw    $23,0x4C($21)    	 # Delay slot
53799		 lw    $24,0x3C($29)
53800		 lw    $14,0x40($29)
53801		 lw    $9,0x44($29)
53802		 lw    $15,m68k_ICount
53803		 seb   $10,$2
53804		 addu  $2,$10,$9
53805		 sltu  $16,$2,$9       	 # Set Carry
53806		 xor   $17,$10,$9
53807		 nor   $17,$0,$17
53808		 xor   $25,$2,$10
53809		 and   $17,$17,$25
53810		 srl   $17,$17,7
53811		 andi  $17,$17,0x01     	 # Set Overflow
53812		 seb  $25,$2
53813		 slt   $19,$25,$0        	 # Set Sign
53814		 sltiu $18,$25,1         	 # Set Zero
53815		 or    $20,$0,$16      	 # Copy Carry to X
53816		 lw    $25,0x88($21)
53817		 sw    $15,m68k_ICount
53818		 sw    $9,0x44($29)
53819		 sw    $14,0x40($29)
53820		 sw    $24,0x3C($29)
53821		 or    $5,$0,$2
53822		 or    $4,$0,$14
53823		 jalr  $25
53824		 sw    $23,0x4C($21)    	 # Delay slot
53825		 lw    $24,0x3C($29)
53826		 lw    $14,0x40($29)
53827		 lw    $9,0x44($29)
53828		 lw    $15,m68k_ICount
53829		 addiu $15,$15,-12
53830		 bgez  $15,3f
53831		 lhu   $24,0x00($23)    	 # Delay slot
53832		 j     MainExit
53833	3:
53834		 sll   $7,$24,2         	 # Delay slot
53835		 addu  $7,$7,$30
53836		 lw    $7,0x00($7)
53837		 jr    $7
53838		 nop                    	 # Delay slot
53839
53840OP0_d118:				#:
53841		 addiu $23,$23,2
53842
53843		 andi  $8,$24,0x07
53844		 srl   $24,$24,7
53845		 andi  $24,$24,0x1C
53846		 addu  $24,$24,$21
53847		 lb    $9,0x00($24)
53848		 sll   $8,$8,2
53849		 addu  $8,$8,$21
53850		 lw    $14,0x20($8)
53851		 addiu $25,$14,1
53852		 sw    $25,0x20($8)
53853		 lw    $25,0x7C($21)
53854		 sw    $15,m68k_ICount
53855		 sw    $9,0x44($29)
53856		 sw    $14,0x40($29)
53857		 sw    $24,0x3C($29)
53858		 or    $4,$0,$14
53859		 jalr  $25
53860		 sw    $23,0x4C($21)    	 # Delay slot
53861		 lw    $24,0x3C($29)
53862		 lw    $14,0x40($29)
53863		 lw    $9,0x44($29)
53864		 lw    $15,m68k_ICount
53865		 seb   $10,$2
53866		 addu  $2,$10,$9
53867		 sltu  $16,$2,$9       	 # Set Carry
53868		 xor   $17,$10,$9
53869		 nor   $17,$0,$17
53870		 xor   $25,$2,$10
53871		 and   $17,$17,$25
53872		 srl   $17,$17,7
53873		 andi  $17,$17,0x01     	 # Set Overflow
53874		 seb  $25,$2
53875		 slt   $19,$25,$0        	 # Set Sign
53876		 sltiu $18,$25,1         	 # Set Zero
53877		 or    $20,$0,$16      	 # Copy Carry to X
53878		 lw    $25,0x88($21)
53879		 sw    $15,m68k_ICount
53880		 sw    $9,0x44($29)
53881		 sw    $14,0x40($29)
53882		 sw    $24,0x3C($29)
53883		 or    $5,$0,$2
53884		 or    $4,$0,$14
53885		 jalr  $25
53886		 sw    $23,0x4C($21)    	 # Delay slot
53887		 lw    $24,0x3C($29)
53888		 lw    $14,0x40($29)
53889		 lw    $9,0x44($29)
53890		 lw    $15,m68k_ICount
53891		 addiu $15,$15,-12
53892		 bgez  $15,3f
53893		 lhu   $24,0x00($23)    	 # Delay slot
53894		 j     MainExit
53895	3:
53896		 sll   $7,$24,2         	 # Delay slot
53897		 addu  $7,$7,$30
53898		 lw    $7,0x00($7)
53899		 jr    $7
53900		 nop                    	 # Delay slot
53901
53902OP0_d11f:				#:
53903		 addiu $23,$23,2
53904
53905		 srl   $24,$24,7
53906		 andi  $24,$24,0x1C
53907		 addu  $24,$24,$21
53908		 lb    $9,0x00($24)
53909		 lw    $14,0x3C($21)    	 # Get A7
53910		 addiu $25,$14,2
53911		 sw    $25,0x3C($21)
53912		 lw    $25,0x7C($21)
53913		 sw    $15,m68k_ICount
53914		 sw    $9,0x44($29)
53915		 sw    $14,0x40($29)
53916		 sw    $24,0x3C($29)
53917		 or    $4,$0,$14
53918		 jalr  $25
53919		 sw    $23,0x4C($21)    	 # Delay slot
53920		 lw    $24,0x3C($29)
53921		 lw    $14,0x40($29)
53922		 lw    $9,0x44($29)
53923		 lw    $15,m68k_ICount
53924		 seb   $10,$2
53925		 addu  $2,$10,$9
53926		 sltu  $16,$2,$9       	 # Set Carry
53927		 xor   $17,$10,$9
53928		 nor   $17,$0,$17
53929		 xor   $25,$2,$10
53930		 and   $17,$17,$25
53931		 srl   $17,$17,7
53932		 andi  $17,$17,0x01     	 # Set Overflow
53933		 seb  $25,$2
53934		 slt   $19,$25,$0        	 # Set Sign
53935		 sltiu $18,$25,1         	 # Set Zero
53936		 or    $20,$0,$16      	 # Copy Carry to X
53937		 lw    $25,0x88($21)
53938		 sw    $15,m68k_ICount
53939		 sw    $9,0x44($29)
53940		 sw    $14,0x40($29)
53941		 sw    $24,0x3C($29)
53942		 or    $5,$0,$2
53943		 or    $4,$0,$14
53944		 jalr  $25
53945		 sw    $23,0x4C($21)    	 # Delay slot
53946		 lw    $24,0x3C($29)
53947		 lw    $14,0x40($29)
53948		 lw    $9,0x44($29)
53949		 lw    $15,m68k_ICount
53950		 addiu $15,$15,-12
53951		 bgez  $15,3f
53952		 lhu   $24,0x00($23)    	 # Delay slot
53953		 j     MainExit
53954	3:
53955		 sll   $7,$24,2         	 # Delay slot
53956		 addu  $7,$7,$30
53957		 lw    $7,0x00($7)
53958		 jr    $7
53959		 nop                    	 # Delay slot
53960
53961OP0_d120:				#:
53962		 addiu $23,$23,2
53963
53964		 andi  $8,$24,0x07
53965		 srl   $24,$24,7
53966		 andi  $24,$24,0x1C
53967		 addu  $24,$24,$21
53968		 lb    $9,0x00($24)
53969		 sll   $8,$8,2
53970		 addu  $8,$8,$21
53971		 lw    $14,0x20($8)
53972		 addiu $14,$14,-1
53973		 sw    $14,0x20($8)
53974		 lw    $25,0x7C($21)
53975		 sw    $15,m68k_ICount
53976		 sw    $9,0x44($29)
53977		 sw    $14,0x40($29)
53978		 sw    $24,0x3C($29)
53979		 or    $4,$0,$14
53980		 jalr  $25
53981		 sw    $23,0x4C($21)    	 # Delay slot
53982		 lw    $24,0x3C($29)
53983		 lw    $14,0x40($29)
53984		 lw    $9,0x44($29)
53985		 lw    $15,m68k_ICount
53986		 seb   $10,$2
53987		 addu  $2,$10,$9
53988		 sltu  $16,$2,$9       	 # Set Carry
53989		 xor   $17,$10,$9
53990		 nor   $17,$0,$17
53991		 xor   $25,$2,$10
53992		 and   $17,$17,$25
53993		 srl   $17,$17,7
53994		 andi  $17,$17,0x01     	 # Set Overflow
53995		 seb  $25,$2
53996		 slt   $19,$25,$0        	 # Set Sign
53997		 sltiu $18,$25,1         	 # Set Zero
53998		 or    $20,$0,$16      	 # Copy Carry to X
53999		 lw    $25,0x88($21)
54000		 sw    $15,m68k_ICount
54001		 sw    $9,0x44($29)
54002		 sw    $14,0x40($29)
54003		 sw    $24,0x3C($29)
54004		 or    $5,$0,$2
54005		 or    $4,$0,$14
54006		 jalr  $25
54007		 sw    $23,0x4C($21)    	 # Delay slot
54008		 lw    $24,0x3C($29)
54009		 lw    $14,0x40($29)
54010		 lw    $9,0x44($29)
54011		 lw    $15,m68k_ICount
54012		 addiu $15,$15,-14
54013		 bgez  $15,3f
54014		 lhu   $24,0x00($23)    	 # Delay slot
54015		 j     MainExit
54016	3:
54017		 sll   $7,$24,2         	 # Delay slot
54018		 addu  $7,$7,$30
54019		 lw    $7,0x00($7)
54020		 jr    $7
54021		 nop                    	 # Delay slot
54022
54023OP0_d127:				#:
54024		 addiu $23,$23,2
54025
54026		 srl   $24,$24,7
54027		 andi  $24,$24,0x1C
54028		 addu  $24,$24,$21
54029		 lb    $9,0x00($24)
54030		 lw    $14,0x3C($21)    	 # Get A7
54031		 addiu $14,$14,-2
54032		 sw    $14,0x3C($21)
54033		 lw    $25,0x7C($21)
54034		 sw    $15,m68k_ICount
54035		 sw    $9,0x44($29)
54036		 sw    $14,0x40($29)
54037		 sw    $24,0x3C($29)
54038		 or    $4,$0,$14
54039		 jalr  $25
54040		 sw    $23,0x4C($21)    	 # Delay slot
54041		 lw    $24,0x3C($29)
54042		 lw    $14,0x40($29)
54043		 lw    $9,0x44($29)
54044		 lw    $15,m68k_ICount
54045		 seb   $10,$2
54046		 addu  $2,$10,$9
54047		 sltu  $16,$2,$9       	 # Set Carry
54048		 xor   $17,$10,$9
54049		 nor   $17,$0,$17
54050		 xor   $25,$2,$10
54051		 and   $17,$17,$25
54052		 srl   $17,$17,7
54053		 andi  $17,$17,0x01     	 # Set Overflow
54054		 seb  $25,$2
54055		 slt   $19,$25,$0        	 # Set Sign
54056		 sltiu $18,$25,1         	 # Set Zero
54057		 or    $20,$0,$16      	 # Copy Carry to X
54058		 lw    $25,0x88($21)
54059		 sw    $15,m68k_ICount
54060		 sw    $9,0x44($29)
54061		 sw    $14,0x40($29)
54062		 sw    $24,0x3C($29)
54063		 or    $5,$0,$2
54064		 or    $4,$0,$14
54065		 jalr  $25
54066		 sw    $23,0x4C($21)    	 # Delay slot
54067		 lw    $24,0x3C($29)
54068		 lw    $14,0x40($29)
54069		 lw    $9,0x44($29)
54070		 lw    $15,m68k_ICount
54071		 addiu $15,$15,-14
54072		 bgez  $15,3f
54073		 lhu   $24,0x00($23)    	 # Delay slot
54074		 j     MainExit
54075	3:
54076		 sll   $7,$24,2         	 # Delay slot
54077		 addu  $7,$7,$30
54078		 lw    $7,0x00($7)
54079		 jr    $7
54080		 nop                    	 # Delay slot
54081
54082OP0_d128:				#:
54083		 addiu $23,$23,2
54084
54085		 andi  $8,$24,0x07
54086		 srl   $24,$24,7
54087		 andi  $24,$24,0x1C
54088		 addu  $24,$24,$21
54089		 lb    $9,0x00($24)
54090		 lh    $7,0x00($23)
54091		 sll   $8,$8,2
54092		 addu  $8,$8,$21
54093		 lw    $14,0x20($8)
54094		 addiu $23,$23,2
54095		 addu  $14,$14,$7
54096		 lw    $25,0x7C($21)
54097		 sw    $15,m68k_ICount
54098		 sw    $9,0x44($29)
54099		 sw    $14,0x40($29)
54100		 sw    $24,0x3C($29)
54101		 or    $4,$0,$14
54102		 jalr  $25
54103		 sw    $23,0x4C($21)    	 # Delay slot
54104		 lw    $24,0x3C($29)
54105		 lw    $14,0x40($29)
54106		 lw    $9,0x44($29)
54107		 lw    $15,m68k_ICount
54108		 seb   $10,$2
54109		 addu  $2,$10,$9
54110		 sltu  $16,$2,$9       	 # Set Carry
54111		 xor   $17,$10,$9
54112		 nor   $17,$0,$17
54113		 xor   $25,$2,$10
54114		 and   $17,$17,$25
54115		 srl   $17,$17,7
54116		 andi  $17,$17,0x01     	 # Set Overflow
54117		 seb  $25,$2
54118		 slt   $19,$25,$0        	 # Set Sign
54119		 sltiu $18,$25,1         	 # Set Zero
54120		 or    $20,$0,$16      	 # Copy Carry to X
54121		 lw    $25,0x88($21)
54122		 sw    $15,m68k_ICount
54123		 sw    $9,0x44($29)
54124		 sw    $14,0x40($29)
54125		 sw    $24,0x3C($29)
54126		 or    $5,$0,$2
54127		 or    $4,$0,$14
54128		 jalr  $25
54129		 sw    $23,0x4C($21)    	 # Delay slot
54130		 lw    $24,0x3C($29)
54131		 lw    $14,0x40($29)
54132		 lw    $9,0x44($29)
54133		 lw    $15,m68k_ICount
54134		 addiu $15,$15,-16
54135		 bgez  $15,3f
54136		 lhu   $24,0x00($23)    	 # Delay slot
54137		 j     MainExit
54138	3:
54139		 sll   $7,$24,2         	 # Delay slot
54140		 addu  $7,$7,$30
54141		 lw    $7,0x00($7)
54142		 jr    $7
54143		 nop                    	 # Delay slot
54144
54145OP0_d130:				#:
54146		 addiu $23,$23,2
54147
54148		 andi  $8,$24,0x07
54149		 srl   $24,$24,7
54150		 andi  $24,$24,0x1C
54151		 addu  $24,$24,$21
54152		 lb    $9,0x00($24)
54153		 sll   $8,$8,2
54154		 addu  $8,$8,$21
54155		 lw    $14,0x20($8)
54156		 lhu   $7,0x00($23)
54157		 addiu $23,$23,2
54158		 seb   $6,$7
54159		 or    $25,$0,$7
54160		 srl   $7,$7,12
54161		 andi  $25,$25,0x0800
54162		 sll   $7,$7,2
54163		 addu  $7,$7,$21
54164		 bne   $25,$0,0f
54165		 lw    $25,0x00($7)      	 # Delay slot
54166		 seh   $25,$25
54167	0:
54168		 addu  $25,$14,$25
54169		 addu  $14,$25,$6
54170		 lw    $25,0x7C($21)
54171		 sw    $15,m68k_ICount
54172		 sw    $9,0x44($29)
54173		 sw    $14,0x40($29)
54174		 sw    $24,0x3C($29)
54175		 or    $4,$0,$14
54176		 jalr  $25
54177		 sw    $23,0x4C($21)    	 # Delay slot
54178		 lw    $24,0x3C($29)
54179		 lw    $14,0x40($29)
54180		 lw    $9,0x44($29)
54181		 lw    $15,m68k_ICount
54182		 seb   $10,$2
54183		 addu  $2,$10,$9
54184		 sltu  $16,$2,$9       	 # Set Carry
54185		 xor   $17,$10,$9
54186		 nor   $17,$0,$17
54187		 xor   $25,$2,$10
54188		 and   $17,$17,$25
54189		 srl   $17,$17,7
54190		 andi  $17,$17,0x01     	 # Set Overflow
54191		 seb  $25,$2
54192		 slt   $19,$25,$0        	 # Set Sign
54193		 sltiu $18,$25,1         	 # Set Zero
54194		 or    $20,$0,$16      	 # Copy Carry to X
54195		 lw    $25,0x88($21)
54196		 sw    $15,m68k_ICount
54197		 sw    $9,0x44($29)
54198		 sw    $14,0x40($29)
54199		 sw    $24,0x3C($29)
54200		 or    $5,$0,$2
54201		 or    $4,$0,$14
54202		 jalr  $25
54203		 sw    $23,0x4C($21)    	 # Delay slot
54204		 lw    $24,0x3C($29)
54205		 lw    $14,0x40($29)
54206		 lw    $9,0x44($29)
54207		 lw    $15,m68k_ICount
54208		 addiu $15,$15,-18
54209		 bgez  $15,3f
54210		 lhu   $24,0x00($23)    	 # Delay slot
54211		 j     MainExit
54212	3:
54213		 sll   $7,$24,2         	 # Delay slot
54214		 addu  $7,$7,$30
54215		 lw    $7,0x00($7)
54216		 jr    $7
54217		 nop                    	 # Delay slot
54218
54219OP0_d138:				#:
54220		 addiu $23,$23,2
54221
54222		 srl   $24,$24,7
54223		 andi  $24,$24,0x1C
54224		 addu  $24,$24,$21
54225		 lb    $9,0x00($24)
54226		 lh    $14,0x00($23)
54227		 addiu $23,$23,2
54228		 lw    $25,0x7C($21)
54229		 sw    $15,m68k_ICount
54230		 sw    $9,0x44($29)
54231		 sw    $14,0x40($29)
54232		 sw    $24,0x3C($29)
54233		 or    $4,$0,$14
54234		 jalr  $25
54235		 sw    $23,0x4C($21)    	 # Delay slot
54236		 lw    $24,0x3C($29)
54237		 lw    $14,0x40($29)
54238		 lw    $9,0x44($29)
54239		 lw    $15,m68k_ICount
54240		 seb   $10,$2
54241		 addu  $2,$10,$9
54242		 sltu  $16,$2,$9       	 # Set Carry
54243		 xor   $17,$10,$9
54244		 nor   $17,$0,$17
54245		 xor   $25,$2,$10
54246		 and   $17,$17,$25
54247		 srl   $17,$17,7
54248		 andi  $17,$17,0x01     	 # Set Overflow
54249		 seb  $25,$2
54250		 slt   $19,$25,$0        	 # Set Sign
54251		 sltiu $18,$25,1         	 # Set Zero
54252		 or    $20,$0,$16      	 # Copy Carry to X
54253		 lw    $25,0x88($21)
54254		 sw    $15,m68k_ICount
54255		 sw    $9,0x44($29)
54256		 sw    $14,0x40($29)
54257		 sw    $24,0x3C($29)
54258		 or    $5,$0,$2
54259		 or    $4,$0,$14
54260		 jalr  $25
54261		 sw    $23,0x4C($21)    	 # Delay slot
54262		 lw    $24,0x3C($29)
54263		 lw    $14,0x40($29)
54264		 lw    $9,0x44($29)
54265		 lw    $15,m68k_ICount
54266		 addiu $15,$15,-16
54267		 bgez  $15,3f
54268		 lhu   $24,0x00($23)    	 # Delay slot
54269		 j     MainExit
54270	3:
54271		 sll   $7,$24,2         	 # Delay slot
54272		 addu  $7,$7,$30
54273		 lw    $7,0x00($7)
54274		 jr    $7
54275		 nop                    	 # Delay slot
54276
54277OP0_d139:				#:
54278		 addiu $23,$23,2
54279
54280		 srl   $24,$24,7
54281		 andi  $24,$24,0x1C
54282		 addu  $24,$24,$21
54283		 lb    $9,0x00($24)
54284		 lhu   $14,0x00($23)
54285		 lhu   $25,0x02($23)
54286		 sll   $14,$14,16
54287		 or    $14,$14,$25
54288		 addiu $23,$23,4
54289		 lw    $25,0x7C($21)
54290		 sw    $15,m68k_ICount
54291		 sw    $9,0x44($29)
54292		 sw    $14,0x40($29)
54293		 sw    $24,0x3C($29)
54294		 or    $4,$0,$14
54295		 jalr  $25
54296		 sw    $23,0x4C($21)    	 # Delay slot
54297		 lw    $24,0x3C($29)
54298		 lw    $14,0x40($29)
54299		 lw    $9,0x44($29)
54300		 lw    $15,m68k_ICount
54301		 seb   $10,$2
54302		 addu  $2,$10,$9
54303		 sltu  $16,$2,$9       	 # Set Carry
54304		 xor   $17,$10,$9
54305		 nor   $17,$0,$17
54306		 xor   $25,$2,$10
54307		 and   $17,$17,$25
54308		 srl   $17,$17,7
54309		 andi  $17,$17,0x01     	 # Set Overflow
54310		 seb  $25,$2
54311		 slt   $19,$25,$0        	 # Set Sign
54312		 sltiu $18,$25,1         	 # Set Zero
54313		 or    $20,$0,$16      	 # Copy Carry to X
54314		 lw    $25,0x88($21)
54315		 sw    $15,m68k_ICount
54316		 sw    $9,0x44($29)
54317		 sw    $14,0x40($29)
54318		 sw    $24,0x3C($29)
54319		 or    $5,$0,$2
54320		 or    $4,$0,$14
54321		 jalr  $25
54322		 sw    $23,0x4C($21)    	 # Delay slot
54323		 lw    $24,0x3C($29)
54324		 lw    $14,0x40($29)
54325		 lw    $9,0x44($29)
54326		 lw    $15,m68k_ICount
54327		 addiu $15,$15,-20
54328		 bgez  $15,3f
54329		 lhu   $24,0x00($23)    	 # Delay slot
54330		 j     MainExit
54331	3:
54332		 sll   $7,$24,2         	 # Delay slot
54333		 addu  $7,$7,$30
54334		 lw    $7,0x00($7)
54335		 jr    $7
54336		 nop                    	 # Delay slot
54337
54338OP0_d150:				#:
54339		 addiu $23,$23,2
54340
54341		 andi  $8,$24,0x07
54342		 srl   $24,$24,7
54343		 andi  $24,$24,0x1C
54344		 addu  $24,$24,$21
54345		 lh    $9,0x00($24)
54346		 sll   $8,$8,2
54347		 addu  $8,$8,$21
54348		 lw    $14,0x20($8)
54349		 lw    $25,0x80($21)
54350		 sw    $15,m68k_ICount
54351		 sw    $9,0x44($29)
54352		 sw    $14,0x40($29)
54353		 sw    $24,0x3C($29)
54354		 or    $4,$0,$14
54355		 jalr  $25
54356		 sw    $23,0x4C($21)    	 # Delay slot
54357		 lw    $24,0x3C($29)
54358		 lw    $14,0x40($29)
54359		 lw    $9,0x44($29)
54360		 lw    $15,m68k_ICount
54361		 seh   $10,$2
54362		 addu  $2,$10,$9
54363		 sltu  $16,$2,$9       	 # Set Carry
54364		 xor   $17,$10,$9
54365		 nor   $17,$0,$17
54366		 xor   $25,$2,$10
54367		 and   $17,$17,$25
54368		 srl   $17,$17,15
54369		 andi  $17,$17,0x01     	 # Set Overflow
54370		 seh  $25,$2
54371		 slt   $19,$25,$0        	 # Set Sign
54372		 sltiu $18,$25,1         	 # Set Zero
54373		 or    $20,$0,$16      	 # Copy Carry to X
54374		 lw    $25,0x8C($21)
54375		 sw    $15,m68k_ICount
54376		 sw    $9,0x44($29)
54377		 sw    $14,0x40($29)
54378		 sw    $24,0x3C($29)
54379		 or    $5,$0,$2
54380		 or    $4,$0,$14
54381		 jalr  $25
54382		 sw    $23,0x4C($21)    	 # Delay slot
54383		 lw    $24,0x3C($29)
54384		 lw    $14,0x40($29)
54385		 lw    $9,0x44($29)
54386		 lw    $15,m68k_ICount
54387		 addiu $15,$15,-12
54388		 bgez  $15,3f
54389		 lhu   $24,0x00($23)    	 # Delay slot
54390		 j     MainExit
54391	3:
54392		 sll   $7,$24,2         	 # Delay slot
54393		 addu  $7,$7,$30
54394		 lw    $7,0x00($7)
54395		 jr    $7
54396		 nop                    	 # Delay slot
54397
54398OP0_d158:				#:
54399		 addiu $23,$23,2
54400
54401		 andi  $8,$24,0x07
54402		 srl   $24,$24,7
54403		 andi  $24,$24,0x1C
54404		 addu  $24,$24,$21
54405		 lh    $9,0x00($24)
54406		 sll   $8,$8,2
54407		 addu  $8,$8,$21
54408		 lw    $14,0x20($8)
54409		 addiu $25,$14,2
54410		 sw    $25,0x20($8)
54411		 lw    $25,0x80($21)
54412		 sw    $15,m68k_ICount
54413		 sw    $9,0x44($29)
54414		 sw    $14,0x40($29)
54415		 sw    $24,0x3C($29)
54416		 or    $4,$0,$14
54417		 jalr  $25
54418		 sw    $23,0x4C($21)    	 # Delay slot
54419		 lw    $24,0x3C($29)
54420		 lw    $14,0x40($29)
54421		 lw    $9,0x44($29)
54422		 lw    $15,m68k_ICount
54423		 seh   $10,$2
54424		 addu  $2,$10,$9
54425		 sltu  $16,$2,$9       	 # Set Carry
54426		 xor   $17,$10,$9
54427		 nor   $17,$0,$17
54428		 xor   $25,$2,$10
54429		 and   $17,$17,$25
54430		 srl   $17,$17,15
54431		 andi  $17,$17,0x01     	 # Set Overflow
54432		 seh  $25,$2
54433		 slt   $19,$25,$0        	 # Set Sign
54434		 sltiu $18,$25,1         	 # Set Zero
54435		 or    $20,$0,$16      	 # Copy Carry to X
54436		 lw    $25,0x8C($21)
54437		 sw    $15,m68k_ICount
54438		 sw    $9,0x44($29)
54439		 sw    $14,0x40($29)
54440		 sw    $24,0x3C($29)
54441		 or    $5,$0,$2
54442		 or    $4,$0,$14
54443		 jalr  $25
54444		 sw    $23,0x4C($21)    	 # Delay slot
54445		 lw    $24,0x3C($29)
54446		 lw    $14,0x40($29)
54447		 lw    $9,0x44($29)
54448		 lw    $15,m68k_ICount
54449		 addiu $15,$15,-12
54450		 bgez  $15,3f
54451		 lhu   $24,0x00($23)    	 # Delay slot
54452		 j     MainExit
54453	3:
54454		 sll   $7,$24,2         	 # Delay slot
54455		 addu  $7,$7,$30
54456		 lw    $7,0x00($7)
54457		 jr    $7
54458		 nop                    	 # Delay slot
54459
54460OP0_d160:				#:
54461		 addiu $23,$23,2
54462
54463		 andi  $8,$24,0x07
54464		 srl   $24,$24,7
54465		 andi  $24,$24,0x1C
54466		 addu  $24,$24,$21
54467		 lh    $9,0x00($24)
54468		 sll   $8,$8,2
54469		 addu  $8,$8,$21
54470		 lw    $14,0x20($8)
54471		 addiu $14,$14,-2
54472		 sw    $14,0x20($8)
54473		 lw    $25,0x80($21)
54474		 sw    $15,m68k_ICount
54475		 sw    $9,0x44($29)
54476		 sw    $14,0x40($29)
54477		 sw    $24,0x3C($29)
54478		 or    $4,$0,$14
54479		 jalr  $25
54480		 sw    $23,0x4C($21)    	 # Delay slot
54481		 lw    $24,0x3C($29)
54482		 lw    $14,0x40($29)
54483		 lw    $9,0x44($29)
54484		 lw    $15,m68k_ICount
54485		 seh   $10,$2
54486		 addu  $2,$10,$9
54487		 sltu  $16,$2,$9       	 # Set Carry
54488		 xor   $17,$10,$9
54489		 nor   $17,$0,$17
54490		 xor   $25,$2,$10
54491		 and   $17,$17,$25
54492		 srl   $17,$17,15
54493		 andi  $17,$17,0x01     	 # Set Overflow
54494		 seh  $25,$2
54495		 slt   $19,$25,$0        	 # Set Sign
54496		 sltiu $18,$25,1         	 # Set Zero
54497		 or    $20,$0,$16      	 # Copy Carry to X
54498		 lw    $25,0x8C($21)
54499		 sw    $15,m68k_ICount
54500		 sw    $9,0x44($29)
54501		 sw    $14,0x40($29)
54502		 sw    $24,0x3C($29)
54503		 or    $5,$0,$2
54504		 or    $4,$0,$14
54505		 jalr  $25
54506		 sw    $23,0x4C($21)    	 # Delay slot
54507		 lw    $24,0x3C($29)
54508		 lw    $14,0x40($29)
54509		 lw    $9,0x44($29)
54510		 lw    $15,m68k_ICount
54511		 addiu $15,$15,-14
54512		 bgez  $15,3f
54513		 lhu   $24,0x00($23)    	 # Delay slot
54514		 j     MainExit
54515	3:
54516		 sll   $7,$24,2         	 # Delay slot
54517		 addu  $7,$7,$30
54518		 lw    $7,0x00($7)
54519		 jr    $7
54520		 nop                    	 # Delay slot
54521
54522OP0_d168:				#:
54523		 addiu $23,$23,2
54524
54525		 andi  $8,$24,0x07
54526		 srl   $24,$24,7
54527		 andi  $24,$24,0x1C
54528		 addu  $24,$24,$21
54529		 lh    $9,0x00($24)
54530		 lh    $7,0x00($23)
54531		 sll   $8,$8,2
54532		 addu  $8,$8,$21
54533		 lw    $14,0x20($8)
54534		 addiu $23,$23,2
54535		 addu  $14,$14,$7
54536		 lw    $25,0x80($21)
54537		 sw    $15,m68k_ICount
54538		 sw    $9,0x44($29)
54539		 sw    $14,0x40($29)
54540		 sw    $24,0x3C($29)
54541		 or    $4,$0,$14
54542		 jalr  $25
54543		 sw    $23,0x4C($21)    	 # Delay slot
54544		 lw    $24,0x3C($29)
54545		 lw    $14,0x40($29)
54546		 lw    $9,0x44($29)
54547		 lw    $15,m68k_ICount
54548		 seh   $10,$2
54549		 addu  $2,$10,$9
54550		 sltu  $16,$2,$9       	 # Set Carry
54551		 xor   $17,$10,$9
54552		 nor   $17,$0,$17
54553		 xor   $25,$2,$10
54554		 and   $17,$17,$25
54555		 srl   $17,$17,15
54556		 andi  $17,$17,0x01     	 # Set Overflow
54557		 seh  $25,$2
54558		 slt   $19,$25,$0        	 # Set Sign
54559		 sltiu $18,$25,1         	 # Set Zero
54560		 or    $20,$0,$16      	 # Copy Carry to X
54561		 lw    $25,0x8C($21)
54562		 sw    $15,m68k_ICount
54563		 sw    $9,0x44($29)
54564		 sw    $14,0x40($29)
54565		 sw    $24,0x3C($29)
54566		 or    $5,$0,$2
54567		 or    $4,$0,$14
54568		 jalr  $25
54569		 sw    $23,0x4C($21)    	 # Delay slot
54570		 lw    $24,0x3C($29)
54571		 lw    $14,0x40($29)
54572		 lw    $9,0x44($29)
54573		 lw    $15,m68k_ICount
54574		 addiu $15,$15,-16
54575		 bgez  $15,3f
54576		 lhu   $24,0x00($23)    	 # Delay slot
54577		 j     MainExit
54578	3:
54579		 sll   $7,$24,2         	 # Delay slot
54580		 addu  $7,$7,$30
54581		 lw    $7,0x00($7)
54582		 jr    $7
54583		 nop                    	 # Delay slot
54584
54585OP0_d170:				#:
54586		 addiu $23,$23,2
54587
54588		 andi  $8,$24,0x07
54589		 srl   $24,$24,7
54590		 andi  $24,$24,0x1C
54591		 addu  $24,$24,$21
54592		 lh    $9,0x00($24)
54593		 sll   $8,$8,2
54594		 addu  $8,$8,$21
54595		 lw    $14,0x20($8)
54596		 lhu   $7,0x00($23)
54597		 addiu $23,$23,2
54598		 seb   $6,$7
54599		 or    $25,$0,$7
54600		 srl   $7,$7,12
54601		 andi  $25,$25,0x0800
54602		 sll   $7,$7,2
54603		 addu  $7,$7,$21
54604		 bne   $25,$0,0f
54605		 lw    $25,0x00($7)      	 # Delay slot
54606		 seh   $25,$25
54607	0:
54608		 addu  $25,$14,$25
54609		 addu  $14,$25,$6
54610		 lw    $25,0x80($21)
54611		 sw    $15,m68k_ICount
54612		 sw    $9,0x44($29)
54613		 sw    $14,0x40($29)
54614		 sw    $24,0x3C($29)
54615		 or    $4,$0,$14
54616		 jalr  $25
54617		 sw    $23,0x4C($21)    	 # Delay slot
54618		 lw    $24,0x3C($29)
54619		 lw    $14,0x40($29)
54620		 lw    $9,0x44($29)
54621		 lw    $15,m68k_ICount
54622		 seh   $10,$2
54623		 addu  $2,$10,$9
54624		 sltu  $16,$2,$9       	 # Set Carry
54625		 xor   $17,$10,$9
54626		 nor   $17,$0,$17
54627		 xor   $25,$2,$10
54628		 and   $17,$17,$25
54629		 srl   $17,$17,15
54630		 andi  $17,$17,0x01     	 # Set Overflow
54631		 seh  $25,$2
54632		 slt   $19,$25,$0        	 # Set Sign
54633		 sltiu $18,$25,1         	 # Set Zero
54634		 or    $20,$0,$16      	 # Copy Carry to X
54635		 lw    $25,0x8C($21)
54636		 sw    $15,m68k_ICount
54637		 sw    $9,0x44($29)
54638		 sw    $14,0x40($29)
54639		 sw    $24,0x3C($29)
54640		 or    $5,$0,$2
54641		 or    $4,$0,$14
54642		 jalr  $25
54643		 sw    $23,0x4C($21)    	 # Delay slot
54644		 lw    $24,0x3C($29)
54645		 lw    $14,0x40($29)
54646		 lw    $9,0x44($29)
54647		 lw    $15,m68k_ICount
54648		 addiu $15,$15,-18
54649		 bgez  $15,3f
54650		 lhu   $24,0x00($23)    	 # Delay slot
54651		 j     MainExit
54652	3:
54653		 sll   $7,$24,2         	 # Delay slot
54654		 addu  $7,$7,$30
54655		 lw    $7,0x00($7)
54656		 jr    $7
54657		 nop                    	 # Delay slot
54658
54659OP0_d178:				#:
54660		 addiu $23,$23,2
54661
54662		 srl   $24,$24,7
54663		 andi  $24,$24,0x1C
54664		 addu  $24,$24,$21
54665		 lh    $9,0x00($24)
54666		 lh    $14,0x00($23)
54667		 addiu $23,$23,2
54668		 lw    $25,0x80($21)
54669		 sw    $15,m68k_ICount
54670		 sw    $9,0x44($29)
54671		 sw    $14,0x40($29)
54672		 sw    $24,0x3C($29)
54673		 or    $4,$0,$14
54674		 jalr  $25
54675		 sw    $23,0x4C($21)    	 # Delay slot
54676		 lw    $24,0x3C($29)
54677		 lw    $14,0x40($29)
54678		 lw    $9,0x44($29)
54679		 lw    $15,m68k_ICount
54680		 seh   $10,$2
54681		 addu  $2,$10,$9
54682		 sltu  $16,$2,$9       	 # Set Carry
54683		 xor   $17,$10,$9
54684		 nor   $17,$0,$17
54685		 xor   $25,$2,$10
54686		 and   $17,$17,$25
54687		 srl   $17,$17,15
54688		 andi  $17,$17,0x01     	 # Set Overflow
54689		 seh  $25,$2
54690		 slt   $19,$25,$0        	 # Set Sign
54691		 sltiu $18,$25,1         	 # Set Zero
54692		 or    $20,$0,$16      	 # Copy Carry to X
54693		 lw    $25,0x8C($21)
54694		 sw    $15,m68k_ICount
54695		 sw    $9,0x44($29)
54696		 sw    $14,0x40($29)
54697		 sw    $24,0x3C($29)
54698		 or    $5,$0,$2
54699		 or    $4,$0,$14
54700		 jalr  $25
54701		 sw    $23,0x4C($21)    	 # Delay slot
54702		 lw    $24,0x3C($29)
54703		 lw    $14,0x40($29)
54704		 lw    $9,0x44($29)
54705		 lw    $15,m68k_ICount
54706		 addiu $15,$15,-16
54707		 bgez  $15,3f
54708		 lhu   $24,0x00($23)    	 # Delay slot
54709		 j     MainExit
54710	3:
54711		 sll   $7,$24,2         	 # Delay slot
54712		 addu  $7,$7,$30
54713		 lw    $7,0x00($7)
54714		 jr    $7
54715		 nop                    	 # Delay slot
54716
54717OP0_d179:				#:
54718		 addiu $23,$23,2
54719
54720		 srl   $24,$24,7
54721		 andi  $24,$24,0x1C
54722		 addu  $24,$24,$21
54723		 lh    $9,0x00($24)
54724		 lhu   $14,0x00($23)
54725		 lhu   $25,0x02($23)
54726		 sll   $14,$14,16
54727		 or    $14,$14,$25
54728		 addiu $23,$23,4
54729		 lw    $25,0x80($21)
54730		 sw    $15,m68k_ICount
54731		 sw    $9,0x44($29)
54732		 sw    $14,0x40($29)
54733		 sw    $24,0x3C($29)
54734		 or    $4,$0,$14
54735		 jalr  $25
54736		 sw    $23,0x4C($21)    	 # Delay slot
54737		 lw    $24,0x3C($29)
54738		 lw    $14,0x40($29)
54739		 lw    $9,0x44($29)
54740		 lw    $15,m68k_ICount
54741		 seh   $10,$2
54742		 addu  $2,$10,$9
54743		 sltu  $16,$2,$9       	 # Set Carry
54744		 xor   $17,$10,$9
54745		 nor   $17,$0,$17
54746		 xor   $25,$2,$10
54747		 and   $17,$17,$25
54748		 srl   $17,$17,15
54749		 andi  $17,$17,0x01     	 # Set Overflow
54750		 seh  $25,$2
54751		 slt   $19,$25,$0        	 # Set Sign
54752		 sltiu $18,$25,1         	 # Set Zero
54753		 or    $20,$0,$16      	 # Copy Carry to X
54754		 lw    $25,0x8C($21)
54755		 sw    $15,m68k_ICount
54756		 sw    $9,0x44($29)
54757		 sw    $14,0x40($29)
54758		 sw    $24,0x3C($29)
54759		 or    $5,$0,$2
54760		 or    $4,$0,$14
54761		 jalr  $25
54762		 sw    $23,0x4C($21)    	 # Delay slot
54763		 lw    $24,0x3C($29)
54764		 lw    $14,0x40($29)
54765		 lw    $9,0x44($29)
54766		 lw    $15,m68k_ICount
54767		 addiu $15,$15,-20
54768		 bgez  $15,3f
54769		 lhu   $24,0x00($23)    	 # Delay slot
54770		 j     MainExit
54771	3:
54772		 sll   $7,$24,2         	 # Delay slot
54773		 addu  $7,$7,$30
54774		 lw    $7,0x00($7)
54775		 jr    $7
54776		 nop                    	 # Delay slot
54777
54778OP0_d190:				#:
54779		 addiu $23,$23,2
54780
54781		 andi  $8,$24,0x07
54782		 srl   $24,$24,7
54783		 andi  $24,$24,0x1C
54784		 addu  $24,$24,$21
54785		 lw    $9,0x00($24)
54786		 sll   $8,$8,2
54787		 addu  $8,$8,$21
54788		 lw    $14,0x20($8)
54789		 lw    $25,0x84($21)
54790		 sw    $15,m68k_ICount
54791		 sw    $9,0x44($29)
54792		 sw    $14,0x40($29)
54793		 sw    $24,0x3C($29)
54794		 or    $4,$0,$14
54795		 jalr  $25
54796		 sw    $23,0x4C($21)    	 # Delay slot
54797		 lw    $24,0x3C($29)
54798		 lw    $14,0x40($29)
54799		 lw    $9,0x44($29)
54800		 lw    $15,m68k_ICount
54801		 or    $10,$0,$2
54802		 addu  $2,$10,$9
54803		 sltu  $16,$2,$9       	 # Set Carry
54804		 xor   $17,$10,$9
54805		 nor   $17,$0,$17
54806		 xor   $25,$2,$10
54807		 and   $17,$17,$25
54808		 srl   $17,$17,31        	 # Set Overflow
54809		 slt   $19,$2,$0        	 # Set Sign
54810		 sltiu $18,$2,1         	 # Set Zero
54811		 or    $20,$0,$16      	 # Copy Carry to X
54812		 lw    $25,0x90($21)
54813		 sw    $15,m68k_ICount
54814		 sw    $9,0x44($29)
54815		 sw    $14,0x40($29)
54816		 sw    $24,0x3C($29)
54817		 or    $5,$0,$2
54818		 or    $4,$0,$14
54819		 jalr  $25
54820		 sw    $23,0x4C($21)    	 # Delay slot
54821		 lw    $24,0x3C($29)
54822		 lw    $14,0x40($29)
54823		 lw    $9,0x44($29)
54824		 lw    $15,m68k_ICount
54825		 addiu $15,$15,-20
54826		 bgez  $15,3f
54827		 lhu   $24,0x00($23)    	 # Delay slot
54828		 j     MainExit
54829	3:
54830		 sll   $7,$24,2         	 # Delay slot
54831		 addu  $7,$7,$30
54832		 lw    $7,0x00($7)
54833		 jr    $7
54834		 nop                    	 # Delay slot
54835
54836OP0_d198:				#:
54837		 addiu $23,$23,2
54838
54839		 andi  $8,$24,0x07
54840		 srl   $24,$24,7
54841		 andi  $24,$24,0x1C
54842		 addu  $24,$24,$21
54843		 lw    $9,0x00($24)
54844		 sll   $8,$8,2
54845		 addu  $8,$8,$21
54846		 lw    $14,0x20($8)
54847		 addiu $25,$14,4
54848		 sw    $25,0x20($8)
54849		 lw    $25,0x84($21)
54850		 sw    $15,m68k_ICount
54851		 sw    $9,0x44($29)
54852		 sw    $14,0x40($29)
54853		 sw    $24,0x3C($29)
54854		 or    $4,$0,$14
54855		 jalr  $25
54856		 sw    $23,0x4C($21)    	 # Delay slot
54857		 lw    $24,0x3C($29)
54858		 lw    $14,0x40($29)
54859		 lw    $9,0x44($29)
54860		 lw    $15,m68k_ICount
54861		 or    $10,$0,$2
54862		 addu  $2,$10,$9
54863		 sltu  $16,$2,$9       	 # Set Carry
54864		 xor   $17,$10,$9
54865		 nor   $17,$0,$17
54866		 xor   $25,$2,$10
54867		 and   $17,$17,$25
54868		 srl   $17,$17,31        	 # Set Overflow
54869		 slt   $19,$2,$0        	 # Set Sign
54870		 sltiu $18,$2,1         	 # Set Zero
54871		 or    $20,$0,$16      	 # Copy Carry to X
54872		 lw    $25,0x90($21)
54873		 sw    $15,m68k_ICount
54874		 sw    $9,0x44($29)
54875		 sw    $14,0x40($29)
54876		 sw    $24,0x3C($29)
54877		 or    $5,$0,$2
54878		 or    $4,$0,$14
54879		 jalr  $25
54880		 sw    $23,0x4C($21)    	 # Delay slot
54881		 lw    $24,0x3C($29)
54882		 lw    $14,0x40($29)
54883		 lw    $9,0x44($29)
54884		 lw    $15,m68k_ICount
54885		 addiu $15,$15,-20
54886		 bgez  $15,3f
54887		 lhu   $24,0x00($23)    	 # Delay slot
54888		 j     MainExit
54889	3:
54890		 sll   $7,$24,2         	 # Delay slot
54891		 addu  $7,$7,$30
54892		 lw    $7,0x00($7)
54893		 jr    $7
54894		 nop                    	 # Delay slot
54895
54896OP0_d1a0:				#:
54897		 addiu $23,$23,2
54898
54899		 andi  $8,$24,0x07
54900		 srl   $24,$24,7
54901		 andi  $24,$24,0x1C
54902		 addu  $24,$24,$21
54903		 lw    $9,0x00($24)
54904		 sll   $8,$8,2
54905		 addu  $8,$8,$21
54906		 lw    $14,0x20($8)
54907		 addiu $14,$14,-4
54908		 sw    $14,0x20($8)
54909		 lw    $25,0x84($21)
54910		 sw    $15,m68k_ICount
54911		 sw    $9,0x44($29)
54912		 sw    $14,0x40($29)
54913		 sw    $24,0x3C($29)
54914		 or    $4,$0,$14
54915		 jalr  $25
54916		 sw    $23,0x4C($21)    	 # Delay slot
54917		 lw    $24,0x3C($29)
54918		 lw    $14,0x40($29)
54919		 lw    $9,0x44($29)
54920		 lw    $15,m68k_ICount
54921		 or    $10,$0,$2
54922		 addu  $2,$10,$9
54923		 sltu  $16,$2,$9       	 # Set Carry
54924		 xor   $17,$10,$9
54925		 nor   $17,$0,$17
54926		 xor   $25,$2,$10
54927		 and   $17,$17,$25
54928		 srl   $17,$17,31        	 # Set Overflow
54929		 slt   $19,$2,$0        	 # Set Sign
54930		 sltiu $18,$2,1         	 # Set Zero
54931		 or    $20,$0,$16      	 # Copy Carry to X
54932		 lw    $25,0x90($21)
54933		 sw    $15,m68k_ICount
54934		 sw    $9,0x44($29)
54935		 sw    $14,0x40($29)
54936		 sw    $24,0x3C($29)
54937		 or    $5,$0,$2
54938		 or    $4,$0,$14
54939		 jalr  $25
54940		 sw    $23,0x4C($21)    	 # Delay slot
54941		 lw    $24,0x3C($29)
54942		 lw    $14,0x40($29)
54943		 lw    $9,0x44($29)
54944		 lw    $15,m68k_ICount
54945		 addiu $15,$15,-22
54946		 bgez  $15,3f
54947		 lhu   $24,0x00($23)    	 # Delay slot
54948		 j     MainExit
54949	3:
54950		 sll   $7,$24,2         	 # Delay slot
54951		 addu  $7,$7,$30
54952		 lw    $7,0x00($7)
54953		 jr    $7
54954		 nop                    	 # Delay slot
54955
54956OP0_d1a8:				#:
54957		 addiu $23,$23,2
54958
54959		 andi  $8,$24,0x07
54960		 srl   $24,$24,7
54961		 andi  $24,$24,0x1C
54962		 addu  $24,$24,$21
54963		 lw    $9,0x00($24)
54964		 lh    $7,0x00($23)
54965		 sll   $8,$8,2
54966		 addu  $8,$8,$21
54967		 lw    $14,0x20($8)
54968		 addiu $23,$23,2
54969		 addu  $14,$14,$7
54970		 lw    $25,0x84($21)
54971		 sw    $15,m68k_ICount
54972		 sw    $9,0x44($29)
54973		 sw    $14,0x40($29)
54974		 sw    $24,0x3C($29)
54975		 or    $4,$0,$14
54976		 jalr  $25
54977		 sw    $23,0x4C($21)    	 # Delay slot
54978		 lw    $24,0x3C($29)
54979		 lw    $14,0x40($29)
54980		 lw    $9,0x44($29)
54981		 lw    $15,m68k_ICount
54982		 or    $10,$0,$2
54983		 addu  $2,$10,$9
54984		 sltu  $16,$2,$9       	 # Set Carry
54985		 xor   $17,$10,$9
54986		 nor   $17,$0,$17
54987		 xor   $25,$2,$10
54988		 and   $17,$17,$25
54989		 srl   $17,$17,31        	 # Set Overflow
54990		 slt   $19,$2,$0        	 # Set Sign
54991		 sltiu $18,$2,1         	 # Set Zero
54992		 or    $20,$0,$16      	 # Copy Carry to X
54993		 lw    $25,0x90($21)
54994		 sw    $15,m68k_ICount
54995		 sw    $9,0x44($29)
54996		 sw    $14,0x40($29)
54997		 sw    $24,0x3C($29)
54998		 or    $5,$0,$2
54999		 or    $4,$0,$14
55000		 jalr  $25
55001		 sw    $23,0x4C($21)    	 # Delay slot
55002		 lw    $24,0x3C($29)
55003		 lw    $14,0x40($29)
55004		 lw    $9,0x44($29)
55005		 lw    $15,m68k_ICount
55006		 addiu $15,$15,-24
55007		 bgez  $15,3f
55008		 lhu   $24,0x00($23)    	 # Delay slot
55009		 j     MainExit
55010	3:
55011		 sll   $7,$24,2         	 # Delay slot
55012		 addu  $7,$7,$30
55013		 lw    $7,0x00($7)
55014		 jr    $7
55015		 nop                    	 # Delay slot
55016
55017OP0_d1b0:				#:
55018		 addiu $23,$23,2
55019
55020		 andi  $8,$24,0x07
55021		 srl   $24,$24,7
55022		 andi  $24,$24,0x1C
55023		 addu  $24,$24,$21
55024		 lw    $9,0x00($24)
55025		 sll   $8,$8,2
55026		 addu  $8,$8,$21
55027		 lw    $14,0x20($8)
55028		 lhu   $7,0x00($23)
55029		 addiu $23,$23,2
55030		 seb   $6,$7
55031		 or    $25,$0,$7
55032		 srl   $7,$7,12
55033		 andi  $25,$25,0x0800
55034		 sll   $7,$7,2
55035		 addu  $7,$7,$21
55036		 bne   $25,$0,0f
55037		 lw    $25,0x00($7)      	 # Delay slot
55038		 seh   $25,$25
55039	0:
55040		 addu  $25,$14,$25
55041		 addu  $14,$25,$6
55042		 lw    $25,0x84($21)
55043		 sw    $15,m68k_ICount
55044		 sw    $9,0x44($29)
55045		 sw    $14,0x40($29)
55046		 sw    $24,0x3C($29)
55047		 or    $4,$0,$14
55048		 jalr  $25
55049		 sw    $23,0x4C($21)    	 # Delay slot
55050		 lw    $24,0x3C($29)
55051		 lw    $14,0x40($29)
55052		 lw    $9,0x44($29)
55053		 lw    $15,m68k_ICount
55054		 or    $10,$0,$2
55055		 addu  $2,$10,$9
55056		 sltu  $16,$2,$9       	 # Set Carry
55057		 xor   $17,$10,$9
55058		 nor   $17,$0,$17
55059		 xor   $25,$2,$10
55060		 and   $17,$17,$25
55061		 srl   $17,$17,31        	 # Set Overflow
55062		 slt   $19,$2,$0        	 # Set Sign
55063		 sltiu $18,$2,1         	 # Set Zero
55064		 or    $20,$0,$16      	 # Copy Carry to X
55065		 lw    $25,0x90($21)
55066		 sw    $15,m68k_ICount
55067		 sw    $9,0x44($29)
55068		 sw    $14,0x40($29)
55069		 sw    $24,0x3C($29)
55070		 or    $5,$0,$2
55071		 or    $4,$0,$14
55072		 jalr  $25
55073		 sw    $23,0x4C($21)    	 # Delay slot
55074		 lw    $24,0x3C($29)
55075		 lw    $14,0x40($29)
55076		 lw    $9,0x44($29)
55077		 lw    $15,m68k_ICount
55078		 addiu $15,$15,-26
55079		 bgez  $15,3f
55080		 lhu   $24,0x00($23)    	 # Delay slot
55081		 j     MainExit
55082	3:
55083		 sll   $7,$24,2         	 # Delay slot
55084		 addu  $7,$7,$30
55085		 lw    $7,0x00($7)
55086		 jr    $7
55087		 nop                    	 # Delay slot
55088
55089OP0_d1b8:				#:
55090		 addiu $23,$23,2
55091
55092		 srl   $24,$24,7
55093		 andi  $24,$24,0x1C
55094		 addu  $24,$24,$21
55095		 lw    $9,0x00($24)
55096		 lh    $14,0x00($23)
55097		 addiu $23,$23,2
55098		 lw    $25,0x84($21)
55099		 sw    $15,m68k_ICount
55100		 sw    $9,0x44($29)
55101		 sw    $14,0x40($29)
55102		 sw    $24,0x3C($29)
55103		 or    $4,$0,$14
55104		 jalr  $25
55105		 sw    $23,0x4C($21)    	 # Delay slot
55106		 lw    $24,0x3C($29)
55107		 lw    $14,0x40($29)
55108		 lw    $9,0x44($29)
55109		 lw    $15,m68k_ICount
55110		 or    $10,$0,$2
55111		 addu  $2,$10,$9
55112		 sltu  $16,$2,$9       	 # Set Carry
55113		 xor   $17,$10,$9
55114		 nor   $17,$0,$17
55115		 xor   $25,$2,$10
55116		 and   $17,$17,$25
55117		 srl   $17,$17,31        	 # Set Overflow
55118		 slt   $19,$2,$0        	 # Set Sign
55119		 sltiu $18,$2,1         	 # Set Zero
55120		 or    $20,$0,$16      	 # Copy Carry to X
55121		 lw    $25,0x90($21)
55122		 sw    $15,m68k_ICount
55123		 sw    $9,0x44($29)
55124		 sw    $14,0x40($29)
55125		 sw    $24,0x3C($29)
55126		 or    $5,$0,$2
55127		 or    $4,$0,$14
55128		 jalr  $25
55129		 sw    $23,0x4C($21)    	 # Delay slot
55130		 lw    $24,0x3C($29)
55131		 lw    $14,0x40($29)
55132		 lw    $9,0x44($29)
55133		 lw    $15,m68k_ICount
55134		 addiu $15,$15,-24
55135		 bgez  $15,3f
55136		 lhu   $24,0x00($23)    	 # Delay slot
55137		 j     MainExit
55138	3:
55139		 sll   $7,$24,2         	 # Delay slot
55140		 addu  $7,$7,$30
55141		 lw    $7,0x00($7)
55142		 jr    $7
55143		 nop                    	 # Delay slot
55144
55145OP0_d1b9:				#:
55146		 addiu $23,$23,2
55147
55148		 srl   $24,$24,7
55149		 andi  $24,$24,0x1C
55150		 addu  $24,$24,$21
55151		 lw    $9,0x00($24)
55152		 lhu   $14,0x00($23)
55153		 lhu   $25,0x02($23)
55154		 sll   $14,$14,16
55155		 or    $14,$14,$25
55156		 addiu $23,$23,4
55157		 lw    $25,0x84($21)
55158		 sw    $15,m68k_ICount
55159		 sw    $9,0x44($29)
55160		 sw    $14,0x40($29)
55161		 sw    $24,0x3C($29)
55162		 or    $4,$0,$14
55163		 jalr  $25
55164		 sw    $23,0x4C($21)    	 # Delay slot
55165		 lw    $24,0x3C($29)
55166		 lw    $14,0x40($29)
55167		 lw    $9,0x44($29)
55168		 lw    $15,m68k_ICount
55169		 or    $10,$0,$2
55170		 addu  $2,$10,$9
55171		 sltu  $16,$2,$9       	 # Set Carry
55172		 xor   $17,$10,$9
55173		 nor   $17,$0,$17
55174		 xor   $25,$2,$10
55175		 and   $17,$17,$25
55176		 srl   $17,$17,31        	 # Set Overflow
55177		 slt   $19,$2,$0        	 # Set Sign
55178		 sltiu $18,$2,1         	 # Set Zero
55179		 or    $20,$0,$16      	 # Copy Carry to X
55180		 lw    $25,0x90($21)
55181		 sw    $15,m68k_ICount
55182		 sw    $9,0x44($29)
55183		 sw    $14,0x40($29)
55184		 sw    $24,0x3C($29)
55185		 or    $5,$0,$2
55186		 or    $4,$0,$14
55187		 jalr  $25
55188		 sw    $23,0x4C($21)    	 # Delay slot
55189		 lw    $24,0x3C($29)
55190		 lw    $14,0x40($29)
55191		 lw    $9,0x44($29)
55192		 lw    $15,m68k_ICount
55193		 addiu $15,$15,-28
55194		 bgez  $15,3f
55195		 lhu   $24,0x00($23)    	 # Delay slot
55196		 j     MainExit
55197	3:
55198		 sll   $7,$24,2         	 # Delay slot
55199		 addu  $7,$7,$30
55200		 lw    $7,0x00($7)
55201		 jr    $7
55202		 nop                    	 # Delay slot
55203
55204OP0_9100:				#:
55205		 addiu $23,$23,2
55206
55207		 andi  $8,$24,0x07
55208
55209		 srl   $24,$24,7
55210
55211		 andi  $24,$24,0x1C
55212
55213		 sll   $8,$8,2
55214		 addu  $8,$8,$21
55215		 lb    $8,0x00($8)
55216		 addu   $24,$24,$21
55217
55218		 lb    $9,0x00($24)
55219
55220		 subu  $2,$9,$8
55221		 subu  $2,$2,$20
55222		 addu  $25,$8,$20
55223		 sltu  $16,$9,$25       	 # Set Carry
55224		 xor   $17,$9,$8
55225		 xor   $25,$2,$9
55226		 and   $17,$17,$25
55227		 srl   $17,$17,7
55228		 andi  $17,$17,0x01     	 # Set Overflow
55229		 seb  $25,$2
55230		 slt   $19,$25,$0        	 # Set Sign
55231		 sltiu $25,$25,1
55232		 and   $18,$18,$25      	 # Set Zero
55233		 or    $20,$0,$16      	 # Copy Carry to X
55234		 sb    $2,0x00($24)
55235
55236		 addiu $15,$15,-4
55237		 bgez  $15,3f
55238		 lhu   $24,0x00($23)    	 # Delay slot
55239		 j     MainExit
55240	3:
55241		 sll   $7,$24,2         	 # Delay slot
55242		 addu  $7,$7,$30
55243		 lw    $7,0x00($7)
55244		 jr    $7
55245		 nop                    	 # Delay slot
55246
55247OP0_9108:				#:
55248		 addiu $23,$23,2
55249
55250		 andi  $8,$24,0x07
55251
55252		 srl   $24,$24,7
55253
55254		 andi  $24,$24,0x1C
55255
55256		 sll   $8,$8,2
55257		 addu  $8,$8,$21
55258		 lw    $14,0x20($8)
55259		 addiu $14,$14,-1
55260		 sw    $14,0x20($8)
55261		 lw    $25,0x7C($21)
55262		 sw    $15,m68k_ICount
55263		 sw    $24,0x44($29)
55264		 or    $4,$0,$14
55265		 jalr  $25
55266		 sw    $23,0x4C($21)    	 # Delay slot
55267		 lw    $24,0x44($29)
55268		 lw    $15,m68k_ICount
55269		 seb   $8,$2
55270		 addu  $24,$24,$21
55271		 lw    $14,0x20($24)
55272		 addiu $14,$14,-1
55273		 sw    $14,0x20($24)
55274		 lw    $25,0x7C($21)
55275		 sw    $15,m68k_ICount
55276		 sw    $8,0x44($29)
55277		 sw    $14,0x40($29)
55278		 or    $4,$0,$14
55279		 jalr  $25
55280		 sw    $23,0x4C($21)    	 # Delay slot
55281		 lw    $14,0x40($29)
55282		 lw    $8,0x44($29)
55283		 lw    $15,m68k_ICount
55284		 seb   $9,$2
55285		 subu  $2,$9,$8
55286		 subu  $2,$2,$20
55287		 addu  $25,$8,$20
55288		 sltu  $16,$9,$25       	 # Set Carry
55289		 xor   $17,$9,$8
55290		 xor   $25,$2,$9
55291		 and   $17,$17,$25
55292		 srl   $17,$17,7
55293		 andi  $17,$17,0x01     	 # Set Overflow
55294		 seb  $25,$2
55295		 slt   $19,$25,$0        	 # Set Sign
55296		 sltiu $25,$25,1
55297		 and   $18,$18,$25      	 # Set Zero
55298		 or    $20,$0,$16      	 # Copy Carry to X
55299		 lw    $25,0x88($21)
55300		 sw    $15,m68k_ICount
55301		 or    $5,$0,$2
55302		 or    $4,$0,$14
55303		 jalr  $25
55304		 sw    $23,0x4C($21)    	 # Delay slot
55305		 lw    $15,m68k_ICount
55306		 addiu $15,$15,-18
55307		 bgez  $15,3f
55308		 lhu   $24,0x00($23)    	 # Delay slot
55309		 j     MainExit
55310	3:
55311		 sll   $7,$24,2         	 # Delay slot
55312		 addu  $7,$7,$30
55313		 lw    $7,0x00($7)
55314		 jr    $7
55315		 nop                    	 # Delay slot
55316
55317OP0_910f:				#:
55318		 addiu $23,$23,2
55319
55320		 andi  $8,$24,0x07
55321
55322		 srl   $24,$24,7
55323
55324		 andi  $24,$24,0x1C
55325
55326		 lw    $14,0x3C($21)    	 # Get A7
55327		 addiu $14,$14,-2
55328		 sw    $14,0x3C($21)
55329		 lw    $25,0x7C($21)
55330		 sw    $15,m68k_ICount
55331		 sw    $24,0x44($29)
55332		 or    $4,$0,$14
55333		 jalr  $25
55334		 sw    $23,0x4C($21)    	 # Delay slot
55335		 lw    $24,0x44($29)
55336		 lw    $15,m68k_ICount
55337		 seb   $8,$2
55338		 addu  $24,$24,$21
55339		 lw    $14,0x20($24)
55340		 addiu $14,$14,-1
55341		 sw    $14,0x20($24)
55342		 lw    $25,0x7C($21)
55343		 sw    $15,m68k_ICount
55344		 sw    $8,0x44($29)
55345		 sw    $14,0x40($29)
55346		 or    $4,$0,$14
55347		 jalr  $25
55348		 sw    $23,0x4C($21)    	 # Delay slot
55349		 lw    $14,0x40($29)
55350		 lw    $8,0x44($29)
55351		 lw    $15,m68k_ICount
55352		 seb   $9,$2
55353		 subu  $2,$9,$8
55354		 subu  $2,$2,$20
55355		 addu  $25,$8,$20
55356		 sltu  $16,$9,$25       	 # Set Carry
55357		 xor   $17,$9,$8
55358		 xor   $25,$2,$9
55359		 and   $17,$17,$25
55360		 srl   $17,$17,7
55361		 andi  $17,$17,0x01     	 # Set Overflow
55362		 seb  $25,$2
55363		 slt   $19,$25,$0        	 # Set Sign
55364		 sltiu $25,$25,1
55365		 and   $18,$18,$25      	 # Set Zero
55366		 or    $20,$0,$16      	 # Copy Carry to X
55367		 lw    $25,0x88($21)
55368		 sw    $15,m68k_ICount
55369		 or    $5,$0,$2
55370		 or    $4,$0,$14
55371		 jalr  $25
55372		 sw    $23,0x4C($21)    	 # Delay slot
55373		 lw    $15,m68k_ICount
55374		 addiu $15,$15,-18
55375		 bgez  $15,3f
55376		 lhu   $24,0x00($23)    	 # Delay slot
55377		 j     MainExit
55378	3:
55379		 sll   $7,$24,2         	 # Delay slot
55380		 addu  $7,$7,$30
55381		 lw    $7,0x00($7)
55382		 jr    $7
55383		 nop                    	 # Delay slot
55384
55385OP0_9140:				#:
55386		 addiu $23,$23,2
55387
55388		 andi  $8,$24,0x07
55389
55390		 srl   $24,$24,7
55391
55392		 andi  $24,$24,0x1C
55393
55394		 sll   $8,$8,2
55395		 addu  $8,$8,$21
55396		 lh    $8,0x00($8)
55397		 addu   $24,$24,$21
55398
55399		 lh    $9,0x00($24)
55400
55401		 subu  $2,$9,$8
55402		 subu  $2,$2,$20
55403		 addu  $25,$8,$20
55404		 sltu  $16,$9,$25       	 # Set Carry
55405		 xor   $17,$9,$8
55406		 xor   $25,$2,$9
55407		 and   $17,$17,$25
55408		 srl   $17,$17,15
55409		 andi  $17,$17,0x01     	 # Set Overflow
55410		 seh  $25,$2
55411		 slt   $19,$25,$0        	 # Set Sign
55412		 sltiu $25,$25,1
55413		 and   $18,$18,$25      	 # Set Zero
55414		 or    $20,$0,$16      	 # Copy Carry to X
55415		 sh    $2,0x00($24)
55416
55417		 addiu $15,$15,-4
55418		 bgez  $15,3f
55419		 lhu   $24,0x00($23)    	 # Delay slot
55420		 j     MainExit
55421	3:
55422		 sll   $7,$24,2         	 # Delay slot
55423		 addu  $7,$7,$30
55424		 lw    $7,0x00($7)
55425		 jr    $7
55426		 nop                    	 # Delay slot
55427
55428OP0_9148:				#:
55429		 addiu $23,$23,2
55430
55431		 andi  $8,$24,0x07
55432
55433		 srl   $24,$24,7
55434
55435		 andi  $24,$24,0x1C
55436
55437		 sll   $8,$8,2
55438		 addu  $8,$8,$21
55439		 lw    $14,0x20($8)
55440		 addiu $14,$14,-2
55441		 sw    $14,0x20($8)
55442		 lw    $25,0x80($21)
55443		 sw    $15,m68k_ICount
55444		 sw    $24,0x44($29)
55445		 or    $4,$0,$14
55446		 jalr  $25
55447		 sw    $23,0x4C($21)    	 # Delay slot
55448		 lw    $24,0x44($29)
55449		 lw    $15,m68k_ICount
55450		 seh   $8,$2
55451		 addu  $24,$24,$21
55452		 lw    $14,0x20($24)
55453		 addiu $14,$14,-2
55454		 sw    $14,0x20($24)
55455		 lw    $25,0x80($21)
55456		 sw    $15,m68k_ICount
55457		 sw    $8,0x44($29)
55458		 sw    $14,0x40($29)
55459		 or    $4,$0,$14
55460		 jalr  $25
55461		 sw    $23,0x4C($21)    	 # Delay slot
55462		 lw    $14,0x40($29)
55463		 lw    $8,0x44($29)
55464		 lw    $15,m68k_ICount
55465		 seh   $9,$2
55466		 subu  $2,$9,$8
55467		 subu  $2,$2,$20
55468		 addu  $25,$8,$20
55469		 sltu  $16,$9,$25       	 # Set Carry
55470		 xor   $17,$9,$8
55471		 xor   $25,$2,$9
55472		 and   $17,$17,$25
55473		 srl   $17,$17,15
55474		 andi  $17,$17,0x01     	 # Set Overflow
55475		 seh  $25,$2
55476		 slt   $19,$25,$0        	 # Set Sign
55477		 sltiu $25,$25,1
55478		 and   $18,$18,$25      	 # Set Zero
55479		 or    $20,$0,$16      	 # Copy Carry to X
55480		 lw    $25,0x8C($21)
55481		 sw    $15,m68k_ICount
55482		 or    $5,$0,$2
55483		 or    $4,$0,$14
55484		 jalr  $25
55485		 sw    $23,0x4C($21)    	 # Delay slot
55486		 lw    $15,m68k_ICount
55487		 addiu $15,$15,-18
55488		 bgez  $15,3f
55489		 lhu   $24,0x00($23)    	 # Delay slot
55490		 j     MainExit
55491	3:
55492		 sll   $7,$24,2         	 # Delay slot
55493		 addu  $7,$7,$30
55494		 lw    $7,0x00($7)
55495		 jr    $7
55496		 nop                    	 # Delay slot
55497
55498OP0_9180:				#:
55499		 addiu $23,$23,2
55500
55501		 andi  $8,$24,0x07
55502
55503		 srl   $24,$24,7
55504
55505		 andi  $24,$24,0x1C
55506
55507		 sll   $8,$8,2
55508		 addu  $8,$8,$21
55509		 lw    $8,0x00($8)
55510		 addu   $24,$24,$21
55511
55512		 lw    $9,0x00($24)
55513
55514		 subu  $2,$9,$8
55515		 subu  $2,$2,$20
55516		 addu  $25,$8,$20
55517		 sltu  $16,$9,$25       	 # Set Carry
55518		 xor   $17,$9,$8
55519		 xor   $25,$2,$9
55520		 and   $17,$17,$25
55521		 srl   $17,$17,31        	 # Set Overflow
55522		 slt   $19,$2,$0        	 # Set Sign
55523		 sltiu $25,$2,1
55524		 and   $18,$18,$25      	 # Set Zero
55525		 or    $20,$0,$16      	 # Copy Carry to X
55526		 sw    $2,0x00($24)
55527
55528		 addiu $15,$15,-8
55529		 bgez  $15,3f
55530		 lhu   $24,0x00($23)    	 # Delay slot
55531		 j     MainExit
55532	3:
55533		 sll   $7,$24,2         	 # Delay slot
55534		 addu  $7,$7,$30
55535		 lw    $7,0x00($7)
55536		 jr    $7
55537		 nop                    	 # Delay slot
55538
55539OP0_9188:				#:
55540		 addiu $23,$23,2
55541
55542		 andi  $8,$24,0x07
55543
55544		 srl   $24,$24,7
55545
55546		 andi  $24,$24,0x1C
55547
55548		 sll   $8,$8,2
55549		 addu  $8,$8,$21
55550		 lw    $14,0x20($8)
55551		 addiu $14,$14,-4
55552		 sw    $14,0x20($8)
55553		 lw    $25,0x84($21)
55554		 sw    $15,m68k_ICount
55555		 sw    $24,0x44($29)
55556		 or    $4,$0,$14
55557		 jalr  $25
55558		 sw    $23,0x4C($21)    	 # Delay slot
55559		 lw    $24,0x44($29)
55560		 lw    $15,m68k_ICount
55561		 or    $8,$0,$2
55562		 addu  $24,$24,$21
55563		 lw    $14,0x20($24)
55564		 addiu $14,$14,-4
55565		 sw    $14,0x20($24)
55566		 lw    $25,0x84($21)
55567		 sw    $15,m68k_ICount
55568		 sw    $8,0x44($29)
55569		 sw    $14,0x40($29)
55570		 or    $4,$0,$14
55571		 jalr  $25
55572		 sw    $23,0x4C($21)    	 # Delay slot
55573		 lw    $14,0x40($29)
55574		 lw    $8,0x44($29)
55575		 lw    $15,m68k_ICount
55576		 or    $9,$0,$2
55577		 subu  $2,$9,$8
55578		 subu  $2,$2,$20
55579		 addu  $25,$8,$20
55580		 sltu  $16,$9,$25       	 # Set Carry
55581		 xor   $17,$9,$8
55582		 xor   $25,$2,$9
55583		 and   $17,$17,$25
55584		 srl   $17,$17,31        	 # Set Overflow
55585		 slt   $19,$2,$0        	 # Set Sign
55586		 sltiu $25,$2,1
55587		 and   $18,$18,$25      	 # Set Zero
55588		 or    $20,$0,$16      	 # Copy Carry to X
55589		 lw    $25,0x90($21)
55590		 sw    $15,m68k_ICount
55591		 or    $5,$0,$2
55592		 or    $4,$0,$14
55593		 jalr  $25
55594		 sw    $23,0x4C($21)    	 # Delay slot
55595		 lw    $15,m68k_ICount
55596		 addiu $15,$15,-30
55597		 bgez  $15,3f
55598		 lhu   $24,0x00($23)    	 # Delay slot
55599		 j     MainExit
55600	3:
55601		 sll   $7,$24,2         	 # Delay slot
55602		 addu  $7,$7,$30
55603		 lw    $7,0x00($7)
55604		 jr    $7
55605		 nop                    	 # Delay slot
55606
55607OP0_9f08:				#:
55608		 addiu $23,$23,2
55609
55610		 andi  $8,$24,0x07
55611
55612		 srl   $24,$24,7
55613
55614		 andi  $24,$24,0x1C
55615
55616		 sll   $8,$8,2
55617		 addu  $8,$8,$21
55618		 lw    $14,0x20($8)
55619		 addiu $14,$14,-1
55620		 sw    $14,0x20($8)
55621		 lw    $25,0x7C($21)
55622		 sw    $15,m68k_ICount
55623		 sw    $24,0x44($29)
55624		 or    $4,$0,$14
55625		 jalr  $25
55626		 sw    $23,0x4C($21)    	 # Delay slot
55627		 lw    $24,0x44($29)
55628		 lw    $15,m68k_ICount
55629		 seb   $8,$2
55630		 lw    $14,0x3C($21)    	 # Get A7
55631		 addiu $14,$14,-2
55632		 sw    $14,0x3C($21)
55633		 lw    $25,0x7C($21)
55634		 sw    $15,m68k_ICount
55635		 sw    $8,0x44($29)
55636		 sw    $14,0x40($29)
55637		 or    $4,$0,$14
55638		 jalr  $25
55639		 sw    $23,0x4C($21)    	 # Delay slot
55640		 lw    $14,0x40($29)
55641		 lw    $8,0x44($29)
55642		 lw    $15,m68k_ICount
55643		 seb   $9,$2
55644		 subu  $2,$9,$8
55645		 subu  $2,$2,$20
55646		 addu  $25,$8,$20
55647		 sltu  $16,$9,$25       	 # Set Carry
55648		 xor   $17,$9,$8
55649		 xor   $25,$2,$9
55650		 and   $17,$17,$25
55651		 srl   $17,$17,7
55652		 andi  $17,$17,0x01     	 # Set Overflow
55653		 seb  $25,$2
55654		 slt   $19,$25,$0        	 # Set Sign
55655		 sltiu $25,$25,1
55656		 and   $18,$18,$25      	 # Set Zero
55657		 or    $20,$0,$16      	 # Copy Carry to X
55658		 lw    $25,0x88($21)
55659		 sw    $15,m68k_ICount
55660		 or    $5,$0,$2
55661		 or    $4,$0,$14
55662		 jalr  $25
55663		 sw    $23,0x4C($21)    	 # Delay slot
55664		 lw    $15,m68k_ICount
55665		 addiu $15,$15,-18
55666		 bgez  $15,3f
55667		 lhu   $24,0x00($23)    	 # Delay slot
55668		 j     MainExit
55669	3:
55670		 sll   $7,$24,2         	 # Delay slot
55671		 addu  $7,$7,$30
55672		 lw    $7,0x00($7)
55673		 jr    $7
55674		 nop                    	 # Delay slot
55675
55676OP0_9f0f:				#:
55677		 addiu $23,$23,2
55678
55679		 andi  $8,$24,0x07
55680
55681		 srl   $24,$24,7
55682
55683		 andi  $24,$24,0x1C
55684
55685		 lw    $14,0x3C($21)    	 # Get A7
55686		 addiu $14,$14,-2
55687		 sw    $14,0x3C($21)
55688		 lw    $25,0x7C($21)
55689		 sw    $15,m68k_ICount
55690		 sw    $24,0x44($29)
55691		 or    $4,$0,$14
55692		 jalr  $25
55693		 sw    $23,0x4C($21)    	 # Delay slot
55694		 lw    $24,0x44($29)
55695		 lw    $15,m68k_ICount
55696		 seb   $8,$2
55697		 lw    $14,0x3C($21)    	 # Get A7
55698		 addiu $14,$14,-2
55699		 sw    $14,0x3C($21)
55700		 lw    $25,0x7C($21)
55701		 sw    $15,m68k_ICount
55702		 sw    $8,0x44($29)
55703		 sw    $14,0x40($29)
55704		 or    $4,$0,$14
55705		 jalr  $25
55706		 sw    $23,0x4C($21)    	 # Delay slot
55707		 lw    $14,0x40($29)
55708		 lw    $8,0x44($29)
55709		 lw    $15,m68k_ICount
55710		 seb   $9,$2
55711		 subu  $2,$9,$8
55712		 subu  $2,$2,$20
55713		 addu  $25,$8,$20
55714		 sltu  $16,$9,$25       	 # Set Carry
55715		 xor   $17,$9,$8
55716		 xor   $25,$2,$9
55717		 and   $17,$17,$25
55718		 srl   $17,$17,7
55719		 andi  $17,$17,0x01     	 # Set Overflow
55720		 seb  $25,$2
55721		 slt   $19,$25,$0        	 # Set Sign
55722		 sltiu $25,$25,1
55723		 and   $18,$18,$25      	 # Set Zero
55724		 or    $20,$0,$16      	 # Copy Carry to X
55725		 lw    $25,0x88($21)
55726		 sw    $15,m68k_ICount
55727		 or    $5,$0,$2
55728		 or    $4,$0,$14
55729		 jalr  $25
55730		 sw    $23,0x4C($21)    	 # Delay slot
55731		 lw    $15,m68k_ICount
55732		 addiu $15,$15,-18
55733		 bgez  $15,3f
55734		 lhu   $24,0x00($23)    	 # Delay slot
55735		 j     MainExit
55736	3:
55737		 sll   $7,$24,2         	 # Delay slot
55738		 addu  $7,$7,$30
55739		 lw    $7,0x00($7)
55740		 jr    $7
55741		 nop                    	 # Delay slot
55742
55743OP0_d100:				#:
55744		 addiu $23,$23,2
55745
55746		 andi  $8,$24,0x07
55747
55748		 srl   $24,$24,7
55749
55750		 andi  $24,$24,0x1C
55751
55752		 sll   $8,$8,2
55753		 addu  $8,$8,$21
55754		 lb    $8,0x00($8)
55755		 addu   $24,$24,$21
55756
55757		 lb    $9,0x00($24)
55758
55759		 addu  $2,$9,$8
55760		 addu  $2,$2,$20
55761		 addu  $25,$8,$20
55762		 sltu  $16,$2,$25       	 # Set Carry
55763		 xor   $17,$9,$8
55764		 nor   $17,$0,$17
55765		 xor   $25,$2,$9
55766		 and   $17,$17,$25
55767		 srl   $17,$17,7
55768		 andi  $17,$17,0x01     	 # Set Overflow
55769		 seb  $25,$2
55770		 slt   $19,$25,$0        	 # Set Sign
55771		 sltiu $25,$25,1
55772		 and   $18,$18,$25      	 # Set Zero
55773		 or    $20,$0,$16      	 # Copy Carry to X
55774		 sb    $2,0x00($24)
55775
55776		 addiu $15,$15,-4
55777		 bgez  $15,3f
55778		 lhu   $24,0x00($23)    	 # Delay slot
55779		 j     MainExit
55780	3:
55781		 sll   $7,$24,2         	 # Delay slot
55782		 addu  $7,$7,$30
55783		 lw    $7,0x00($7)
55784		 jr    $7
55785		 nop                    	 # Delay slot
55786
55787OP0_d108:				#:
55788		 addiu $23,$23,2
55789
55790		 andi  $8,$24,0x07
55791
55792		 srl   $24,$24,7
55793
55794		 andi  $24,$24,0x1C
55795
55796		 sll   $8,$8,2
55797		 addu  $8,$8,$21
55798		 lw    $14,0x20($8)
55799		 addiu $14,$14,-1
55800		 sw    $14,0x20($8)
55801		 lw    $25,0x7C($21)
55802		 sw    $15,m68k_ICount
55803		 sw    $24,0x44($29)
55804		 or    $4,$0,$14
55805		 jalr  $25
55806		 sw    $23,0x4C($21)    	 # Delay slot
55807		 lw    $24,0x44($29)
55808		 lw    $15,m68k_ICount
55809		 seb   $8,$2
55810		 addu  $24,$24,$21
55811		 lw    $14,0x20($24)
55812		 addiu $14,$14,-1
55813		 sw    $14,0x20($24)
55814		 lw    $25,0x7C($21)
55815		 sw    $15,m68k_ICount
55816		 sw    $8,0x44($29)
55817		 sw    $14,0x40($29)
55818		 or    $4,$0,$14
55819		 jalr  $25
55820		 sw    $23,0x4C($21)    	 # Delay slot
55821		 lw    $14,0x40($29)
55822		 lw    $8,0x44($29)
55823		 lw    $15,m68k_ICount
55824		 seb   $9,$2
55825		 addu  $2,$9,$8
55826		 addu  $2,$2,$20
55827		 addu  $25,$8,$20
55828		 sltu  $16,$2,$25       	 # Set Carry
55829		 xor   $17,$9,$8
55830		 nor   $17,$0,$17
55831		 xor   $25,$2,$9
55832		 and   $17,$17,$25
55833		 srl   $17,$17,7
55834		 andi  $17,$17,0x01     	 # Set Overflow
55835		 seb  $25,$2
55836		 slt   $19,$25,$0        	 # Set Sign
55837		 sltiu $25,$25,1
55838		 and   $18,$18,$25      	 # Set Zero
55839		 or    $20,$0,$16      	 # Copy Carry to X
55840		 lw    $25,0x88($21)
55841		 sw    $15,m68k_ICount
55842		 or    $5,$0,$2
55843		 or    $4,$0,$14
55844		 jalr  $25
55845		 sw    $23,0x4C($21)    	 # Delay slot
55846		 lw    $15,m68k_ICount
55847		 addiu $15,$15,-18
55848		 bgez  $15,3f
55849		 lhu   $24,0x00($23)    	 # Delay slot
55850		 j     MainExit
55851	3:
55852		 sll   $7,$24,2         	 # Delay slot
55853		 addu  $7,$7,$30
55854		 lw    $7,0x00($7)
55855		 jr    $7
55856		 nop                    	 # Delay slot
55857
55858OP0_d10f:				#:
55859		 addiu $23,$23,2
55860
55861		 andi  $8,$24,0x07
55862
55863		 srl   $24,$24,7
55864
55865		 andi  $24,$24,0x1C
55866
55867		 lw    $14,0x3C($21)    	 # Get A7
55868		 addiu $14,$14,-2
55869		 sw    $14,0x3C($21)
55870		 lw    $25,0x7C($21)
55871		 sw    $15,m68k_ICount
55872		 sw    $24,0x44($29)
55873		 or    $4,$0,$14
55874		 jalr  $25
55875		 sw    $23,0x4C($21)    	 # Delay slot
55876		 lw    $24,0x44($29)
55877		 lw    $15,m68k_ICount
55878		 seb   $8,$2
55879		 addu  $24,$24,$21
55880		 lw    $14,0x20($24)
55881		 addiu $14,$14,-1
55882		 sw    $14,0x20($24)
55883		 lw    $25,0x7C($21)
55884		 sw    $15,m68k_ICount
55885		 sw    $8,0x44($29)
55886		 sw    $14,0x40($29)
55887		 or    $4,$0,$14
55888		 jalr  $25
55889		 sw    $23,0x4C($21)    	 # Delay slot
55890		 lw    $14,0x40($29)
55891		 lw    $8,0x44($29)
55892		 lw    $15,m68k_ICount
55893		 seb   $9,$2
55894		 addu  $2,$9,$8
55895		 addu  $2,$2,$20
55896		 addu  $25,$8,$20
55897		 sltu  $16,$2,$25       	 # Set Carry
55898		 xor   $17,$9,$8
55899		 nor   $17,$0,$17
55900		 xor   $25,$2,$9
55901		 and   $17,$17,$25
55902		 srl   $17,$17,7
55903		 andi  $17,$17,0x01     	 # Set Overflow
55904		 seb  $25,$2
55905		 slt   $19,$25,$0        	 # Set Sign
55906		 sltiu $25,$25,1
55907		 and   $18,$18,$25      	 # Set Zero
55908		 or    $20,$0,$16      	 # Copy Carry to X
55909		 lw    $25,0x88($21)
55910		 sw    $15,m68k_ICount
55911		 or    $5,$0,$2
55912		 or    $4,$0,$14
55913		 jalr  $25
55914		 sw    $23,0x4C($21)    	 # Delay slot
55915		 lw    $15,m68k_ICount
55916		 addiu $15,$15,-18
55917		 bgez  $15,3f
55918		 lhu   $24,0x00($23)    	 # Delay slot
55919		 j     MainExit
55920	3:
55921		 sll   $7,$24,2         	 # Delay slot
55922		 addu  $7,$7,$30
55923		 lw    $7,0x00($7)
55924		 jr    $7
55925		 nop                    	 # Delay slot
55926
55927OP0_d140:				#:
55928		 addiu $23,$23,2
55929
55930		 andi  $8,$24,0x07
55931
55932		 srl   $24,$24,7
55933
55934		 andi  $24,$24,0x1C
55935
55936		 sll   $8,$8,2
55937		 addu  $8,$8,$21
55938		 lh    $8,0x00($8)
55939		 addu   $24,$24,$21
55940
55941		 lh    $9,0x00($24)
55942
55943		 addu  $2,$9,$8
55944		 addu  $2,$2,$20
55945		 addu  $25,$8,$20
55946		 sltu  $16,$2,$25       	 # Set Carry
55947		 xor   $17,$9,$8
55948		 nor   $17,$0,$17
55949		 xor   $25,$2,$9
55950		 and   $17,$17,$25
55951		 srl   $17,$17,15
55952		 andi  $17,$17,0x01     	 # Set Overflow
55953		 seh  $25,$2
55954		 slt   $19,$25,$0        	 # Set Sign
55955		 sltiu $25,$25,1
55956		 and   $18,$18,$25      	 # Set Zero
55957		 or    $20,$0,$16      	 # Copy Carry to X
55958		 sh    $2,0x00($24)
55959
55960		 addiu $15,$15,-4
55961		 bgez  $15,3f
55962		 lhu   $24,0x00($23)    	 # Delay slot
55963		 j     MainExit
55964	3:
55965		 sll   $7,$24,2         	 # Delay slot
55966		 addu  $7,$7,$30
55967		 lw    $7,0x00($7)
55968		 jr    $7
55969		 nop                    	 # Delay slot
55970
55971OP0_d148:				#:
55972		 addiu $23,$23,2
55973
55974		 andi  $8,$24,0x07
55975
55976		 srl   $24,$24,7
55977
55978		 andi  $24,$24,0x1C
55979
55980		 sll   $8,$8,2
55981		 addu  $8,$8,$21
55982		 lw    $14,0x20($8)
55983		 addiu $14,$14,-2
55984		 sw    $14,0x20($8)
55985		 lw    $25,0x80($21)
55986		 sw    $15,m68k_ICount
55987		 sw    $24,0x44($29)
55988		 or    $4,$0,$14
55989		 jalr  $25
55990		 sw    $23,0x4C($21)    	 # Delay slot
55991		 lw    $24,0x44($29)
55992		 lw    $15,m68k_ICount
55993		 seh   $8,$2
55994		 addu  $24,$24,$21
55995		 lw    $14,0x20($24)
55996		 addiu $14,$14,-2
55997		 sw    $14,0x20($24)
55998		 lw    $25,0x80($21)
55999		 sw    $15,m68k_ICount
56000		 sw    $8,0x44($29)
56001		 sw    $14,0x40($29)
56002		 or    $4,$0,$14
56003		 jalr  $25
56004		 sw    $23,0x4C($21)    	 # Delay slot
56005		 lw    $14,0x40($29)
56006		 lw    $8,0x44($29)
56007		 lw    $15,m68k_ICount
56008		 seh   $9,$2
56009		 addu  $2,$9,$8
56010		 addu  $2,$2,$20
56011		 addu  $25,$8,$20
56012		 sltu  $16,$2,$25       	 # Set Carry
56013		 xor   $17,$9,$8
56014		 nor   $17,$0,$17
56015		 xor   $25,$2,$9
56016		 and   $17,$17,$25
56017		 srl   $17,$17,15
56018		 andi  $17,$17,0x01     	 # Set Overflow
56019		 seh  $25,$2
56020		 slt   $19,$25,$0        	 # Set Sign
56021		 sltiu $25,$25,1
56022		 and   $18,$18,$25      	 # Set Zero
56023		 or    $20,$0,$16      	 # Copy Carry to X
56024		 lw    $25,0x8C($21)
56025		 sw    $15,m68k_ICount
56026		 or    $5,$0,$2
56027		 or    $4,$0,$14
56028		 jalr  $25
56029		 sw    $23,0x4C($21)    	 # Delay slot
56030		 lw    $15,m68k_ICount
56031		 addiu $15,$15,-18
56032		 bgez  $15,3f
56033		 lhu   $24,0x00($23)    	 # Delay slot
56034		 j     MainExit
56035	3:
56036		 sll   $7,$24,2         	 # Delay slot
56037		 addu  $7,$7,$30
56038		 lw    $7,0x00($7)
56039		 jr    $7
56040		 nop                    	 # Delay slot
56041
56042OP0_d180:				#:
56043		 addiu $23,$23,2
56044
56045		 andi  $8,$24,0x07
56046
56047		 srl   $24,$24,7
56048
56049		 andi  $24,$24,0x1C
56050
56051		 sll   $8,$8,2
56052		 addu  $8,$8,$21
56053		 lw    $8,0x00($8)
56054		 addu   $24,$24,$21
56055
56056		 lw    $9,0x00($24)
56057
56058		 addu  $2,$9,$8
56059		 addu  $2,$2,$20
56060		 addu  $25,$8,$20
56061		 sltu  $16,$2,$25       	 # Set Carry
56062		 xor   $17,$9,$8
56063		 nor   $17,$0,$17
56064		 xor   $25,$2,$9
56065		 and   $17,$17,$25
56066		 srl   $17,$17,31        	 # Set Overflow
56067		 slt   $19,$2,$0        	 # Set Sign
56068		 sltiu $25,$2,1
56069		 and   $18,$18,$25      	 # Set Zero
56070		 or    $20,$0,$16      	 # Copy Carry to X
56071		 sw    $2,0x00($24)
56072
56073		 addiu $15,$15,-8
56074		 bgez  $15,3f
56075		 lhu   $24,0x00($23)    	 # Delay slot
56076		 j     MainExit
56077	3:
56078		 sll   $7,$24,2         	 # Delay slot
56079		 addu  $7,$7,$30
56080		 lw    $7,0x00($7)
56081		 jr    $7
56082		 nop                    	 # Delay slot
56083
56084OP0_d188:				#:
56085		 addiu $23,$23,2
56086
56087		 andi  $8,$24,0x07
56088
56089		 srl   $24,$24,7
56090
56091		 andi  $24,$24,0x1C
56092
56093		 sll   $8,$8,2
56094		 addu  $8,$8,$21
56095		 lw    $14,0x20($8)
56096		 addiu $14,$14,-4
56097		 sw    $14,0x20($8)
56098		 lw    $25,0x84($21)
56099		 sw    $15,m68k_ICount
56100		 sw    $24,0x44($29)
56101		 or    $4,$0,$14
56102		 jalr  $25
56103		 sw    $23,0x4C($21)    	 # Delay slot
56104		 lw    $24,0x44($29)
56105		 lw    $15,m68k_ICount
56106		 or    $8,$0,$2
56107		 addu  $24,$24,$21
56108		 lw    $14,0x20($24)
56109		 addiu $14,$14,-4
56110		 sw    $14,0x20($24)
56111		 lw    $25,0x84($21)
56112		 sw    $15,m68k_ICount
56113		 sw    $8,0x44($29)
56114		 sw    $14,0x40($29)
56115		 or    $4,$0,$14
56116		 jalr  $25
56117		 sw    $23,0x4C($21)    	 # Delay slot
56118		 lw    $14,0x40($29)
56119		 lw    $8,0x44($29)
56120		 lw    $15,m68k_ICount
56121		 or    $9,$0,$2
56122		 addu  $2,$9,$8
56123		 addu  $2,$2,$20
56124		 addu  $25,$8,$20
56125		 sltu  $16,$2,$25       	 # Set Carry
56126		 xor   $17,$9,$8
56127		 nor   $17,$0,$17
56128		 xor   $25,$2,$9
56129		 and   $17,$17,$25
56130		 srl   $17,$17,31        	 # Set Overflow
56131		 slt   $19,$2,$0        	 # Set Sign
56132		 sltiu $25,$2,1
56133		 and   $18,$18,$25      	 # Set Zero
56134		 or    $20,$0,$16      	 # Copy Carry to X
56135		 lw    $25,0x90($21)
56136		 sw    $15,m68k_ICount
56137		 or    $5,$0,$2
56138		 or    $4,$0,$14
56139		 jalr  $25
56140		 sw    $23,0x4C($21)    	 # Delay slot
56141		 lw    $15,m68k_ICount
56142		 addiu $15,$15,-30
56143		 bgez  $15,3f
56144		 lhu   $24,0x00($23)    	 # Delay slot
56145		 j     MainExit
56146	3:
56147		 sll   $7,$24,2         	 # Delay slot
56148		 addu  $7,$7,$30
56149		 lw    $7,0x00($7)
56150		 jr    $7
56151		 nop                    	 # Delay slot
56152
56153OP0_df08:				#:
56154		 addiu $23,$23,2
56155
56156		 andi  $8,$24,0x07
56157
56158		 srl   $24,$24,7
56159
56160		 andi  $24,$24,0x1C
56161
56162		 sll   $8,$8,2
56163		 addu  $8,$8,$21
56164		 lw    $14,0x20($8)
56165		 addiu $14,$14,-1
56166		 sw    $14,0x20($8)
56167		 lw    $25,0x7C($21)
56168		 sw    $15,m68k_ICount
56169		 sw    $24,0x44($29)
56170		 or    $4,$0,$14
56171		 jalr  $25
56172		 sw    $23,0x4C($21)    	 # Delay slot
56173		 lw    $24,0x44($29)
56174		 lw    $15,m68k_ICount
56175		 seb   $8,$2
56176		 lw    $14,0x3C($21)    	 # Get A7
56177		 addiu $14,$14,-2
56178		 sw    $14,0x3C($21)
56179		 lw    $25,0x7C($21)
56180		 sw    $15,m68k_ICount
56181		 sw    $8,0x44($29)
56182		 sw    $14,0x40($29)
56183		 or    $4,$0,$14
56184		 jalr  $25
56185		 sw    $23,0x4C($21)    	 # Delay slot
56186		 lw    $14,0x40($29)
56187		 lw    $8,0x44($29)
56188		 lw    $15,m68k_ICount
56189		 seb   $9,$2
56190		 addu  $2,$9,$8
56191		 addu  $2,$2,$20
56192		 addu  $25,$8,$20
56193		 sltu  $16,$2,$25       	 # Set Carry
56194		 xor   $17,$9,$8
56195		 nor   $17,$0,$17
56196		 xor   $25,$2,$9
56197		 and   $17,$17,$25
56198		 srl   $17,$17,7
56199		 andi  $17,$17,0x01     	 # Set Overflow
56200		 seb  $25,$2
56201		 slt   $19,$25,$0        	 # Set Sign
56202		 sltiu $25,$25,1
56203		 and   $18,$18,$25      	 # Set Zero
56204		 or    $20,$0,$16      	 # Copy Carry to X
56205		 lw    $25,0x88($21)
56206		 sw    $15,m68k_ICount
56207		 or    $5,$0,$2
56208		 or    $4,$0,$14
56209		 jalr  $25
56210		 sw    $23,0x4C($21)    	 # Delay slot
56211		 lw    $15,m68k_ICount
56212		 addiu $15,$15,-18
56213		 bgez  $15,3f
56214		 lhu   $24,0x00($23)    	 # Delay slot
56215		 j     MainExit
56216	3:
56217		 sll   $7,$24,2         	 # Delay slot
56218		 addu  $7,$7,$30
56219		 lw    $7,0x00($7)
56220		 jr    $7
56221		 nop                    	 # Delay slot
56222
56223OP0_df0f:				#:
56224		 addiu $23,$23,2
56225
56226		 andi  $8,$24,0x07
56227
56228		 srl   $24,$24,7
56229
56230		 andi  $24,$24,0x1C
56231
56232		 lw    $14,0x3C($21)    	 # Get A7
56233		 addiu $14,$14,-2
56234		 sw    $14,0x3C($21)
56235		 lw    $25,0x7C($21)
56236		 sw    $15,m68k_ICount
56237		 sw    $24,0x44($29)
56238		 or    $4,$0,$14
56239		 jalr  $25
56240		 sw    $23,0x4C($21)    	 # Delay slot
56241		 lw    $24,0x44($29)
56242		 lw    $15,m68k_ICount
56243		 seb   $8,$2
56244		 lw    $14,0x3C($21)    	 # Get A7
56245		 addiu $14,$14,-2
56246		 sw    $14,0x3C($21)
56247		 lw    $25,0x7C($21)
56248		 sw    $15,m68k_ICount
56249		 sw    $8,0x44($29)
56250		 sw    $14,0x40($29)
56251		 or    $4,$0,$14
56252		 jalr  $25
56253		 sw    $23,0x4C($21)    	 # Delay slot
56254		 lw    $14,0x40($29)
56255		 lw    $8,0x44($29)
56256		 lw    $15,m68k_ICount
56257		 seb   $9,$2
56258		 addu  $2,$9,$8
56259		 addu  $2,$2,$20
56260		 addu  $25,$8,$20
56261		 sltu  $16,$2,$25       	 # Set Carry
56262		 xor   $17,$9,$8
56263		 nor   $17,$0,$17
56264		 xor   $25,$2,$9
56265		 and   $17,$17,$25
56266		 srl   $17,$17,7
56267		 andi  $17,$17,0x01     	 # Set Overflow
56268		 seb  $25,$2
56269		 slt   $19,$25,$0        	 # Set Sign
56270		 sltiu $25,$25,1
56271		 and   $18,$18,$25      	 # Set Zero
56272		 or    $20,$0,$16      	 # Copy Carry to X
56273		 lw    $25,0x88($21)
56274		 sw    $15,m68k_ICount
56275		 or    $5,$0,$2
56276		 or    $4,$0,$14
56277		 jalr  $25
56278		 sw    $23,0x4C($21)    	 # Delay slot
56279		 lw    $15,m68k_ICount
56280		 addiu $15,$15,-18
56281		 bgez  $15,3f
56282		 lhu   $24,0x00($23)    	 # Delay slot
56283		 j     MainExit
56284	3:
56285		 sll   $7,$24,2         	 # Delay slot
56286		 addu  $7,$7,$30
56287		 lw    $7,0x00($7)
56288		 jr    $7
56289		 nop                    	 # Delay slot
56290
56291OP0_80c0:				#:
56292
56293		 addiu $23,$23,2
56294
56295		 addiu $15,$15,-133
56296		 andi  $8,$24,0x07
56297		 srl   $24,$24,7
56298		 andi  $24,$24,0x1C
56299		 sll   $8,$8,2
56300		 addu  $8,$8,$21
56301		 lhu   $2,0x00($8)
56302		 beq   $2,$0,9f         	 # do div by zero trap
56303		 nop                    	 # Delay slot
56304		 addu  $24,$24,$21
56305		 lw    $8,0x00($24)
56306		 divu  $0,$8,$2
56307		 mflo  $9
56308		 srl   $8,$9,16
56309		 bne   $8,$0,8f
56310		 mfhi  $3               	 # Delay slot
56311		 sll   $3,$3,16
56312		 or    $2,$9,$3
56313		 sw    $2,0x00($24)
56314		 and   $16,$0,$0        	 # Clear Carry
56315		 and   $17,$0,$0        	 # Clear Overflow
56316		 srl   $19,$9,15         	 # Set Sign
56317		 sltiu $18,$9,1         	 # Set Zero
56318	7:
56319		 bgez  $15,3f
56320		 lhu   $24,0x00($23)    	 # Delay slot
56321		 j     MainExit
56322	3:
56323		 sll   $7,$24,2         	 # Delay slot
56324		 addu  $7,$7,$30
56325		 lw    $7,0x00($7)
56326		 jr    $7
56327		 nop                    	 # Delay slot
56328
56329	8:
56330		 bgez  $0,7b
56331		 ori   $17,$0,1         	 # Selay slot - V flag
56332	9:		 # Do divide by zero trap
56333		 addiu $15,$15,95
56334		 jal   Exception
56335		 ori   $2,$0,5          	 # Delay slot
56336
56337		 bgez  $0,7b
56338		 nop                    	 # Delay slot
56339OP0_80d0:				#:
56340
56341		 addiu $23,$23,2
56342
56343		 addiu $15,$15,-137
56344		 andi  $8,$24,0x07
56345		 srl   $24,$24,7
56346		 andi  $24,$24,0x1C
56347		 sll   $8,$8,2
56348		 addu  $8,$8,$21
56349		 lw    $14,0x20($8)
56350		 lw    $25,0x80($21)
56351		 sw    $15,m68k_ICount
56352		 sw    $14,0x44($29)
56353		 sw    $24,0x40($29)
56354		 or    $4,$0,$14
56355		 jalr  $25
56356		 sw    $23,0x4C($21)    	 # Delay slot
56357		 lw    $24,0x40($29)
56358		 lw    $14,0x44($29)
56359		 lw    $15,m68k_ICount
56360		 beq   $2,$0,9f         	 # do div by zero trap
56361		 nop                    	 # Delay slot
56362		 addu  $24,$24,$21
56363		 lw    $8,0x00($24)
56364		 divu  $0,$8,$2
56365		 mflo  $9
56366		 srl   $8,$9,16
56367		 bne   $8,$0,8f
56368		 mfhi  $3               	 # Delay slot
56369		 sll   $3,$3,16
56370		 or    $2,$9,$3
56371		 sw    $2,0x00($24)
56372		 and   $16,$0,$0        	 # Clear Carry
56373		 and   $17,$0,$0        	 # Clear Overflow
56374		 srl   $19,$9,15         	 # Set Sign
56375		 sltiu $18,$9,1         	 # Set Zero
56376	7:
56377		 bgez  $15,3f
56378		 lhu   $24,0x00($23)    	 # Delay slot
56379		 j     MainExit
56380	3:
56381		 sll   $7,$24,2         	 # Delay slot
56382		 addu  $7,$7,$30
56383		 lw    $7,0x00($7)
56384		 jr    $7
56385		 nop                    	 # Delay slot
56386
56387	8:
56388		 bgez  $0,7b
56389		 ori   $17,$0,1         	 # Selay slot - V flag
56390	9:		 # Do divide by zero trap
56391		 addiu $15,$15,95
56392		 jal   Exception
56393		 ori   $2,$0,5          	 # Delay slot
56394
56395		 bgez  $0,7b
56396		 nop                    	 # Delay slot
56397OP0_80d8:				#:
56398
56399		 addiu $23,$23,2
56400
56401		 addiu $15,$15,-137
56402		 andi  $8,$24,0x07
56403		 srl   $24,$24,7
56404		 andi  $24,$24,0x1C
56405		 sll   $8,$8,2
56406		 addu  $8,$8,$21
56407		 lw    $14,0x20($8)
56408		 addiu $25,$14,2
56409		 sw    $25,0x20($8)
56410		 lw    $25,0x80($21)
56411		 sw    $15,m68k_ICount
56412		 sw    $14,0x44($29)
56413		 sw    $24,0x40($29)
56414		 or    $4,$0,$14
56415		 jalr  $25
56416		 sw    $23,0x4C($21)    	 # Delay slot
56417		 lw    $24,0x40($29)
56418		 lw    $14,0x44($29)
56419		 lw    $15,m68k_ICount
56420		 beq   $2,$0,9f         	 # do div by zero trap
56421		 nop                    	 # Delay slot
56422		 addu  $24,$24,$21
56423		 lw    $8,0x00($24)
56424		 divu  $0,$8,$2
56425		 mflo  $9
56426		 srl   $8,$9,16
56427		 bne   $8,$0,8f
56428		 mfhi  $3               	 # Delay slot
56429		 sll   $3,$3,16
56430		 or    $2,$9,$3
56431		 sw    $2,0x00($24)
56432		 and   $16,$0,$0        	 # Clear Carry
56433		 and   $17,$0,$0        	 # Clear Overflow
56434		 srl   $19,$9,15         	 # Set Sign
56435		 sltiu $18,$9,1         	 # Set Zero
56436	7:
56437		 bgez  $15,3f
56438		 lhu   $24,0x00($23)    	 # Delay slot
56439		 j     MainExit
56440	3:
56441		 sll   $7,$24,2         	 # Delay slot
56442		 addu  $7,$7,$30
56443		 lw    $7,0x00($7)
56444		 jr    $7
56445		 nop                    	 # Delay slot
56446
56447	8:
56448		 bgez  $0,7b
56449		 ori   $17,$0,1         	 # Selay slot - V flag
56450	9:		 # Do divide by zero trap
56451		 addiu $15,$15,95
56452		 jal   Exception
56453		 ori   $2,$0,5          	 # Delay slot
56454
56455		 bgez  $0,7b
56456		 nop                    	 # Delay slot
56457OP0_80e0:				#:
56458
56459		 addiu $23,$23,2
56460
56461		 addiu $15,$15,-139
56462		 andi  $8,$24,0x07
56463		 srl   $24,$24,7
56464		 andi  $24,$24,0x1C
56465		 sll   $8,$8,2
56466		 addu  $8,$8,$21
56467		 lw    $14,0x20($8)
56468		 addiu $14,$14,-2
56469		 sw    $14,0x20($8)
56470		 lw    $25,0x80($21)
56471		 sw    $15,m68k_ICount
56472		 sw    $14,0x44($29)
56473		 sw    $24,0x40($29)
56474		 or    $4,$0,$14
56475		 jalr  $25
56476		 sw    $23,0x4C($21)    	 # Delay slot
56477		 lw    $24,0x40($29)
56478		 lw    $14,0x44($29)
56479		 lw    $15,m68k_ICount
56480		 beq   $2,$0,9f         	 # do div by zero trap
56481		 nop                    	 # Delay slot
56482		 addu  $24,$24,$21
56483		 lw    $8,0x00($24)
56484		 divu  $0,$8,$2
56485		 mflo  $9
56486		 srl   $8,$9,16
56487		 bne   $8,$0,8f
56488		 mfhi  $3               	 # Delay slot
56489		 sll   $3,$3,16
56490		 or    $2,$9,$3
56491		 sw    $2,0x00($24)
56492		 and   $16,$0,$0        	 # Clear Carry
56493		 and   $17,$0,$0        	 # Clear Overflow
56494		 srl   $19,$9,15         	 # Set Sign
56495		 sltiu $18,$9,1         	 # Set Zero
56496	7:
56497		 bgez  $15,3f
56498		 lhu   $24,0x00($23)    	 # Delay slot
56499		 j     MainExit
56500	3:
56501		 sll   $7,$24,2         	 # Delay slot
56502		 addu  $7,$7,$30
56503		 lw    $7,0x00($7)
56504		 jr    $7
56505		 nop                    	 # Delay slot
56506
56507	8:
56508		 bgez  $0,7b
56509		 ori   $17,$0,1         	 # Selay slot - V flag
56510	9:		 # Do divide by zero trap
56511		 addiu $15,$15,95
56512		 jal   Exception
56513		 ori   $2,$0,5          	 # Delay slot
56514
56515		 bgez  $0,7b
56516		 nop                    	 # Delay slot
56517OP0_80e8:				#:
56518
56519		 addiu $23,$23,2
56520
56521		 addiu $15,$15,-141
56522		 andi  $8,$24,0x07
56523		 srl   $24,$24,7
56524		 andi  $24,$24,0x1C
56525		 lh    $7,0x00($23)
56526		 sll   $8,$8,2
56527		 addu  $8,$8,$21
56528		 lw    $14,0x20($8)
56529		 addiu $23,$23,2
56530		 addu  $14,$14,$7
56531		 lw    $25,0x80($21)
56532		 sw    $15,m68k_ICount
56533		 sw    $14,0x44($29)
56534		 sw    $24,0x40($29)
56535		 or    $4,$0,$14
56536		 jalr  $25
56537		 sw    $23,0x4C($21)    	 # Delay slot
56538		 lw    $24,0x40($29)
56539		 lw    $14,0x44($29)
56540		 lw    $15,m68k_ICount
56541		 beq   $2,$0,9f         	 # do div by zero trap
56542		 nop                    	 # Delay slot
56543		 addu  $24,$24,$21
56544		 lw    $8,0x00($24)
56545		 divu  $0,$8,$2
56546		 mflo  $9
56547		 srl   $8,$9,16
56548		 bne   $8,$0,8f
56549		 mfhi  $3               	 # Delay slot
56550		 sll   $3,$3,16
56551		 or    $2,$9,$3
56552		 sw    $2,0x00($24)
56553		 and   $16,$0,$0        	 # Clear Carry
56554		 and   $17,$0,$0        	 # Clear Overflow
56555		 srl   $19,$9,15         	 # Set Sign
56556		 sltiu $18,$9,1         	 # Set Zero
56557	7:
56558		 bgez  $15,3f
56559		 lhu   $24,0x00($23)    	 # Delay slot
56560		 j     MainExit
56561	3:
56562		 sll   $7,$24,2         	 # Delay slot
56563		 addu  $7,$7,$30
56564		 lw    $7,0x00($7)
56565		 jr    $7
56566		 nop                    	 # Delay slot
56567
56568	8:
56569		 bgez  $0,7b
56570		 ori   $17,$0,1         	 # Selay slot - V flag
56571	9:		 # Do divide by zero trap
56572		 addiu $15,$15,95
56573		 jal   Exception
56574		 ori   $2,$0,5          	 # Delay slot
56575
56576		 bgez  $0,7b
56577		 nop                    	 # Delay slot
56578OP0_80f0:				#:
56579
56580		 addiu $23,$23,2
56581
56582		 addiu $15,$15,-145
56583		 andi  $8,$24,0x07
56584		 srl   $24,$24,7
56585		 andi  $24,$24,0x1C
56586		 sll   $8,$8,2
56587		 addu  $8,$8,$21
56588		 lw    $14,0x20($8)
56589		 lhu   $7,0x00($23)
56590		 addiu $23,$23,2
56591		 seb   $6,$7
56592		 or    $25,$0,$7
56593		 srl   $7,$7,12
56594		 andi  $25,$25,0x0800
56595		 sll   $7,$7,2
56596		 addu  $7,$7,$21
56597		 bne   $25,$0,0f
56598		 lw    $25,0x00($7)      	 # Delay slot
56599		 seh   $25,$25
56600	0:
56601		 addu  $25,$14,$25
56602		 addu  $14,$25,$6
56603		 lw    $25,0x80($21)
56604		 sw    $15,m68k_ICount
56605		 sw    $14,0x44($29)
56606		 sw    $24,0x40($29)
56607		 or    $4,$0,$14
56608		 jalr  $25
56609		 sw    $23,0x4C($21)    	 # Delay slot
56610		 lw    $24,0x40($29)
56611		 lw    $14,0x44($29)
56612		 lw    $15,m68k_ICount
56613		 beq   $2,$0,9f         	 # do div by zero trap
56614		 nop                    	 # Delay slot
56615		 addu  $24,$24,$21
56616		 lw    $8,0x00($24)
56617		 divu  $0,$8,$2
56618		 mflo  $9
56619		 srl   $8,$9,16
56620		 bne   $8,$0,8f
56621		 mfhi  $3               	 # Delay slot
56622		 sll   $3,$3,16
56623		 or    $2,$9,$3
56624		 sw    $2,0x00($24)
56625		 and   $16,$0,$0        	 # Clear Carry
56626		 and   $17,$0,$0        	 # Clear Overflow
56627		 srl   $19,$9,15         	 # Set Sign
56628		 sltiu $18,$9,1         	 # Set Zero
56629	7:
56630		 bgez  $15,3f
56631		 lhu   $24,0x00($23)    	 # Delay slot
56632		 j     MainExit
56633	3:
56634		 sll   $7,$24,2         	 # Delay slot
56635		 addu  $7,$7,$30
56636		 lw    $7,0x00($7)
56637		 jr    $7
56638		 nop                    	 # Delay slot
56639
56640	8:
56641		 bgez  $0,7b
56642		 ori   $17,$0,1         	 # Selay slot - V flag
56643	9:		 # Do divide by zero trap
56644		 addiu $15,$15,95
56645		 jal   Exception
56646		 ori   $2,$0,5          	 # Delay slot
56647
56648		 bgez  $0,7b
56649		 nop                    	 # Delay slot
56650OP0_80f8:				#:
56651
56652		 addiu $23,$23,2
56653
56654		 addiu $15,$15,-141
56655		 srl   $24,$24,7
56656		 andi  $24,$24,0x1C
56657		 lh    $14,0x00($23)
56658		 addiu $23,$23,2
56659		 lw    $25,0x80($21)
56660		 sw    $15,m68k_ICount
56661		 sw    $14,0x44($29)
56662		 sw    $24,0x40($29)
56663		 or    $4,$0,$14
56664		 jalr  $25
56665		 sw    $23,0x4C($21)    	 # Delay slot
56666		 lw    $24,0x40($29)
56667		 lw    $14,0x44($29)
56668		 lw    $15,m68k_ICount
56669		 beq   $2,$0,9f         	 # do div by zero trap
56670		 nop                    	 # Delay slot
56671		 addu  $24,$24,$21
56672		 lw    $8,0x00($24)
56673		 divu  $0,$8,$2
56674		 mflo  $9
56675		 srl   $8,$9,16
56676		 bne   $8,$0,8f
56677		 mfhi  $3               	 # Delay slot
56678		 sll   $3,$3,16
56679		 or    $2,$9,$3
56680		 sw    $2,0x00($24)
56681		 and   $16,$0,$0        	 # Clear Carry
56682		 and   $17,$0,$0        	 # Clear Overflow
56683		 srl   $19,$9,15         	 # Set Sign
56684		 sltiu $18,$9,1         	 # Set Zero
56685	7:
56686		 bgez  $15,3f
56687		 lhu   $24,0x00($23)    	 # Delay slot
56688		 j     MainExit
56689	3:
56690		 sll   $7,$24,2         	 # Delay slot
56691		 addu  $7,$7,$30
56692		 lw    $7,0x00($7)
56693		 jr    $7
56694		 nop                    	 # Delay slot
56695
56696	8:
56697		 bgez  $0,7b
56698		 ori   $17,$0,1         	 # Selay slot - V flag
56699	9:		 # Do divide by zero trap
56700		 addiu $15,$15,95
56701		 jal   Exception
56702		 ori   $2,$0,5          	 # Delay slot
56703
56704		 bgez  $0,7b
56705		 nop                    	 # Delay slot
56706OP0_80f9:				#:
56707
56708		 addiu $23,$23,2
56709
56710		 addiu $15,$15,-145
56711		 srl   $24,$24,7
56712		 andi  $24,$24,0x1C
56713		 lhu   $14,0x00($23)
56714		 lhu   $25,0x02($23)
56715		 sll   $14,$14,16
56716		 or    $14,$14,$25
56717		 addiu $23,$23,4
56718		 lw    $25,0x80($21)
56719		 sw    $15,m68k_ICount
56720		 sw    $14,0x44($29)
56721		 sw    $24,0x40($29)
56722		 or    $4,$0,$14
56723		 jalr  $25
56724		 sw    $23,0x4C($21)    	 # Delay slot
56725		 lw    $24,0x40($29)
56726		 lw    $14,0x44($29)
56727		 lw    $15,m68k_ICount
56728		 beq   $2,$0,9f         	 # do div by zero trap
56729		 nop                    	 # Delay slot
56730		 addu  $24,$24,$21
56731		 lw    $8,0x00($24)
56732		 divu  $0,$8,$2
56733		 mflo  $9
56734		 srl   $8,$9,16
56735		 bne   $8,$0,8f
56736		 mfhi  $3               	 # Delay slot
56737		 sll   $3,$3,16
56738		 or    $2,$9,$3
56739		 sw    $2,0x00($24)
56740		 and   $16,$0,$0        	 # Clear Carry
56741		 and   $17,$0,$0        	 # Clear Overflow
56742		 srl   $19,$9,15         	 # Set Sign
56743		 sltiu $18,$9,1         	 # Set Zero
56744	7:
56745		 bgez  $15,3f
56746		 lhu   $24,0x00($23)    	 # Delay slot
56747		 j     MainExit
56748	3:
56749		 sll   $7,$24,2         	 # Delay slot
56750		 addu  $7,$7,$30
56751		 lw    $7,0x00($7)
56752		 jr    $7
56753		 nop                    	 # Delay slot
56754
56755	8:
56756		 bgez  $0,7b
56757		 ori   $17,$0,1         	 # Selay slot - V flag
56758	9:		 # Do divide by zero trap
56759		 addiu $15,$15,95
56760		 jal   Exception
56761		 ori   $2,$0,5          	 # Delay slot
56762
56763		 bgez  $0,7b
56764		 nop                    	 # Delay slot
56765OP0_80fa:				#:
56766
56767		 addiu $23,$23,2
56768
56769		 addiu $15,$15,-141
56770		 srl   $24,$24,7
56771		 andi  $24,$24,0x1C
56772		 lh    $7,0x00($23)
56773		 subu  $25,$23,$22
56774		 addu  $14,$25,$7       	 # Add Offset to PC
56775		 addiu $23,$23,2
56776		 lw    $25,0x9C($21)
56777		 sw    $15,m68k_ICount
56778		 sw    $14,0x44($29)
56779		 sw    $24,0x40($29)
56780		 or    $4,$0,$14
56781		 jalr  $25
56782		 sw    $23,0x4C($21)    	 # Delay slot
56783		 lw    $24,0x40($29)
56784		 lw    $14,0x44($29)
56785		 lw    $15,m68k_ICount
56786		 beq   $2,$0,9f         	 # do div by zero trap
56787		 nop                    	 # Delay slot
56788		 addu  $24,$24,$21
56789		 lw    $8,0x00($24)
56790		 divu  $0,$8,$2
56791		 mflo  $9
56792		 srl   $8,$9,16
56793		 bne   $8,$0,8f
56794		 mfhi  $3               	 # Delay slot
56795		 sll   $3,$3,16
56796		 or    $2,$9,$3
56797		 sw    $2,0x00($24)
56798		 and   $16,$0,$0        	 # Clear Carry
56799		 and   $17,$0,$0        	 # Clear Overflow
56800		 srl   $19,$9,15         	 # Set Sign
56801		 sltiu $18,$9,1         	 # Set Zero
56802	7:
56803		 bgez  $15,3f
56804		 lhu   $24,0x00($23)    	 # Delay slot
56805		 j     MainExit
56806	3:
56807		 sll   $7,$24,2         	 # Delay slot
56808		 addu  $7,$7,$30
56809		 lw    $7,0x00($7)
56810		 jr    $7
56811		 nop                    	 # Delay slot
56812
56813	8:
56814		 bgez  $0,7b
56815		 ori   $17,$0,1         	 # Selay slot - V flag
56816	9:		 # Do divide by zero trap
56817		 addiu $15,$15,95
56818		 jal   Exception
56819		 ori   $2,$0,5          	 # Delay slot
56820
56821		 bgez  $0,7b
56822		 nop                    	 # Delay slot
56823OP0_80fb:				#:
56824
56825		 addiu $23,$23,2
56826
56827		 addiu $15,$15,-143
56828		 srl   $24,$24,7
56829		 andi  $24,$24,0x1C
56830		 subu  $14,$23,$22       	 # Get PC
56831		 lhu   $7,0x00($23)
56832		 addiu $23,$23,2
56833		 seb   $6,$7
56834		 or    $25,$0,$7
56835		 srl   $7,$7,12
56836		 andi  $25,$25,0x0800
56837		 sll   $7,$7,2
56838		 addu  $7,$7,$21
56839		 bne   $25,$0,0f
56840		 lw    $25,0x00($7)      	 # Delay slot
56841		 seh   $25,$25
56842	0:
56843		 addu  $25,$14,$25
56844		 addu  $14,$25,$6
56845		 lw    $25,0x9C($21)
56846		 sw    $15,m68k_ICount
56847		 sw    $14,0x44($29)
56848		 sw    $24,0x40($29)
56849		 or    $4,$0,$14
56850		 jalr  $25
56851		 sw    $23,0x4C($21)    	 # Delay slot
56852		 lw    $24,0x40($29)
56853		 lw    $14,0x44($29)
56854		 lw    $15,m68k_ICount
56855		 beq   $2,$0,9f         	 # do div by zero trap
56856		 nop                    	 # Delay slot
56857		 addu  $24,$24,$21
56858		 lw    $8,0x00($24)
56859		 divu  $0,$8,$2
56860		 mflo  $9
56861		 srl   $8,$9,16
56862		 bne   $8,$0,8f
56863		 mfhi  $3               	 # Delay slot
56864		 sll   $3,$3,16
56865		 or    $2,$9,$3
56866		 sw    $2,0x00($24)
56867		 and   $16,$0,$0        	 # Clear Carry
56868		 and   $17,$0,$0        	 # Clear Overflow
56869		 srl   $19,$9,15         	 # Set Sign
56870		 sltiu $18,$9,1         	 # Set Zero
56871	7:
56872		 bgez  $15,3f
56873		 lhu   $24,0x00($23)    	 # Delay slot
56874		 j     MainExit
56875	3:
56876		 sll   $7,$24,2         	 # Delay slot
56877		 addu  $7,$7,$30
56878		 lw    $7,0x00($7)
56879		 jr    $7
56880		 nop                    	 # Delay slot
56881
56882	8:
56883		 bgez  $0,7b
56884		 ori   $17,$0,1         	 # Selay slot - V flag
56885	9:		 # Do divide by zero trap
56886		 addiu $15,$15,95
56887		 jal   Exception
56888		 ori   $2,$0,5          	 # Delay slot
56889
56890		 bgez  $0,7b
56891		 nop                    	 # Delay slot
56892OP0_80fc:				#:
56893
56894		 addiu $23,$23,2
56895
56896		 addiu $15,$15,-137
56897		 srl   $24,$24,7
56898		 andi  $24,$24,0x1C
56899		 lhu   $2,0x00($23)
56900		 addiu $23,$23,2
56901		 beq   $2,$0,9f         	 # do div by zero trap
56902		 nop                    	 # Delay slot
56903		 addu  $24,$24,$21
56904		 lw    $8,0x00($24)
56905		 divu  $0,$8,$2
56906		 mflo  $9
56907		 srl   $8,$9,16
56908		 bne   $8,$0,8f
56909		 mfhi  $3               	 # Delay slot
56910		 sll   $3,$3,16
56911		 or    $2,$9,$3
56912		 sw    $2,0x00($24)
56913		 and   $16,$0,$0        	 # Clear Carry
56914		 and   $17,$0,$0        	 # Clear Overflow
56915		 srl   $19,$9,15         	 # Set Sign
56916		 sltiu $18,$9,1         	 # Set Zero
56917	7:
56918		 bgez  $15,3f
56919		 lhu   $24,0x00($23)    	 # Delay slot
56920		 j     MainExit
56921	3:
56922		 sll   $7,$24,2         	 # Delay slot
56923		 addu  $7,$7,$30
56924		 lw    $7,0x00($7)
56925		 jr    $7
56926		 nop                    	 # Delay slot
56927
56928	8:
56929		 bgez  $0,7b
56930		 ori   $17,$0,1         	 # Selay slot - V flag
56931	9:		 # Do divide by zero trap
56932		 addiu $15,$15,95
56933		 jal   Exception
56934		 ori   $2,$0,5          	 # Delay slot
56935
56936		 bgez  $0,7b
56937		 nop                    	 # Delay slot
56938OP0_81c0:				#:
56939
56940		 addiu $23,$23,2
56941
56942		 addiu $15,$15,-150
56943		 andi  $8,$24,0x07
56944		 srl   $24,$24,7
56945		 andi  $24,$24,0x1C
56946		 sll   $8,$8,2
56947		 addu  $8,$8,$21
56948		 lh    $2,0x00($8)
56949		 beq   $2,$0,9f         	 # do div by zero trap
56950		 nop                    	 # Delay slot
56951		 addu  $24,$24,$21
56952		 lw    $8,0x00($24)
56953		 div   $0,$8,$2
56954		 mflo  $9
56955		 sll   $8,$9,16
56956		 sra   $8,$8,16
56957		 bne   $8,$9,8f
56958		 andi  $9,$9,0xffff     	 # Delay slot
56959		 mfhi  $3
56960		 sll   $3,$3,16
56961		 or    $2,$9,$3
56962		 sw    $2,0x00($24)
56963		 and   $16,$0,$0        	 # Clear Carry
56964		 and   $17,$0,$0        	 # Clear Overflow
56965		 srl   $19,$9,15         	 # Set Sign
56966		 sltiu $18,$9,1         	 # Set Zero
56967	7:
56968		 bgez  $15,3f
56969		 lhu   $24,0x00($23)    	 # Delay slot
56970		 j     MainExit
56971	3:
56972		 sll   $7,$24,2         	 # Delay slot
56973		 addu  $7,$7,$30
56974		 lw    $7,0x00($7)
56975		 jr    $7
56976		 nop                    	 # Delay slot
56977
56978	8:
56979		 bgez  $0,7b
56980		 ori   $17,$0,1         	 # Selay slot - V flag
56981	9:		 # Do divide by zero trap
56982		 addiu $15,$15,112
56983		 jal   Exception
56984		 ori   $2,$0,5          	 # Delay slot
56985
56986		 bgez  $0,7b
56987		 nop                    	 # Delay slot
56988OP0_81d0:				#:
56989
56990		 addiu $23,$23,2
56991
56992		 addiu $15,$15,-154
56993		 andi  $8,$24,0x07
56994		 srl   $24,$24,7
56995		 andi  $24,$24,0x1C
56996		 sll   $8,$8,2
56997		 addu  $8,$8,$21
56998		 lw    $14,0x20($8)
56999		 lw    $25,0x80($21)
57000		 sw    $15,m68k_ICount
57001		 sw    $14,0x44($29)
57002		 sw    $24,0x40($29)
57003		 or    $4,$0,$14
57004		 jalr  $25
57005		 sw    $23,0x4C($21)    	 # Delay slot
57006		 lw    $24,0x40($29)
57007		 lw    $14,0x44($29)
57008		 lw    $15,m68k_ICount
57009		 seh   $2,$2
57010		 beq   $2,$0,9f         	 # do div by zero trap
57011		 nop                    	 # Delay slot
57012		 addu  $24,$24,$21
57013		 lw    $8,0x00($24)
57014		 div   $0,$8,$2
57015		 mflo  $9
57016		 sll   $8,$9,16
57017		 sra   $8,$8,16
57018		 bne   $8,$9,8f
57019		 andi  $9,$9,0xffff     	 # Delay slot
57020		 mfhi  $3
57021		 sll   $3,$3,16
57022		 or    $2,$9,$3
57023		 sw    $2,0x00($24)
57024		 and   $16,$0,$0        	 # Clear Carry
57025		 and   $17,$0,$0        	 # Clear Overflow
57026		 srl   $19,$9,15         	 # Set Sign
57027		 sltiu $18,$9,1         	 # Set Zero
57028	7:
57029		 bgez  $15,3f
57030		 lhu   $24,0x00($23)    	 # Delay slot
57031		 j     MainExit
57032	3:
57033		 sll   $7,$24,2         	 # Delay slot
57034		 addu  $7,$7,$30
57035		 lw    $7,0x00($7)
57036		 jr    $7
57037		 nop                    	 # Delay slot
57038
57039	8:
57040		 bgez  $0,7b
57041		 ori   $17,$0,1         	 # Selay slot - V flag
57042	9:		 # Do divide by zero trap
57043		 addiu $15,$15,112
57044		 jal   Exception
57045		 ori   $2,$0,5          	 # Delay slot
57046
57047		 bgez  $0,7b
57048		 nop                    	 # Delay slot
57049OP0_81d8:				#:
57050
57051		 addiu $23,$23,2
57052
57053		 addiu $15,$15,-154
57054		 andi  $8,$24,0x07
57055		 srl   $24,$24,7
57056		 andi  $24,$24,0x1C
57057		 sll   $8,$8,2
57058		 addu  $8,$8,$21
57059		 lw    $14,0x20($8)
57060		 addiu $25,$14,2
57061		 sw    $25,0x20($8)
57062		 lw    $25,0x80($21)
57063		 sw    $15,m68k_ICount
57064		 sw    $14,0x44($29)
57065		 sw    $24,0x40($29)
57066		 or    $4,$0,$14
57067		 jalr  $25
57068		 sw    $23,0x4C($21)    	 # Delay slot
57069		 lw    $24,0x40($29)
57070		 lw    $14,0x44($29)
57071		 lw    $15,m68k_ICount
57072		 seh   $2,$2
57073		 beq   $2,$0,9f         	 # do div by zero trap
57074		 nop                    	 # Delay slot
57075		 addu  $24,$24,$21
57076		 lw    $8,0x00($24)
57077		 div   $0,$8,$2
57078		 mflo  $9
57079		 sll   $8,$9,16
57080		 sra   $8,$8,16
57081		 bne   $8,$9,8f
57082		 andi  $9,$9,0xffff     	 # Delay slot
57083		 mfhi  $3
57084		 sll   $3,$3,16
57085		 or    $2,$9,$3
57086		 sw    $2,0x00($24)
57087		 and   $16,$0,$0        	 # Clear Carry
57088		 and   $17,$0,$0        	 # Clear Overflow
57089		 srl   $19,$9,15         	 # Set Sign
57090		 sltiu $18,$9,1         	 # Set Zero
57091	7:
57092		 bgez  $15,3f
57093		 lhu   $24,0x00($23)    	 # Delay slot
57094		 j     MainExit
57095	3:
57096		 sll   $7,$24,2         	 # Delay slot
57097		 addu  $7,$7,$30
57098		 lw    $7,0x00($7)
57099		 jr    $7
57100		 nop                    	 # Delay slot
57101
57102	8:
57103		 bgez  $0,7b
57104		 ori   $17,$0,1         	 # Selay slot - V flag
57105	9:		 # Do divide by zero trap
57106		 addiu $15,$15,112
57107		 jal   Exception
57108		 ori   $2,$0,5          	 # Delay slot
57109
57110		 bgez  $0,7b
57111		 nop                    	 # Delay slot
57112OP0_81e0:				#:
57113
57114		 addiu $23,$23,2
57115
57116		 addiu $15,$15,-156
57117		 andi  $8,$24,0x07
57118		 srl   $24,$24,7
57119		 andi  $24,$24,0x1C
57120		 sll   $8,$8,2
57121		 addu  $8,$8,$21
57122		 lw    $14,0x20($8)
57123		 addiu $14,$14,-2
57124		 sw    $14,0x20($8)
57125		 lw    $25,0x80($21)
57126		 sw    $15,m68k_ICount
57127		 sw    $14,0x44($29)
57128		 sw    $24,0x40($29)
57129		 or    $4,$0,$14
57130		 jalr  $25
57131		 sw    $23,0x4C($21)    	 # Delay slot
57132		 lw    $24,0x40($29)
57133		 lw    $14,0x44($29)
57134		 lw    $15,m68k_ICount
57135		 seh   $2,$2
57136		 beq   $2,$0,9f         	 # do div by zero trap
57137		 nop                    	 # Delay slot
57138		 addu  $24,$24,$21
57139		 lw    $8,0x00($24)
57140		 div   $0,$8,$2
57141		 mflo  $9
57142		 sll   $8,$9,16
57143		 sra   $8,$8,16
57144		 bne   $8,$9,8f
57145		 andi  $9,$9,0xffff     	 # Delay slot
57146		 mfhi  $3
57147		 sll   $3,$3,16
57148		 or    $2,$9,$3
57149		 sw    $2,0x00($24)
57150		 and   $16,$0,$0        	 # Clear Carry
57151		 and   $17,$0,$0        	 # Clear Overflow
57152		 srl   $19,$9,15         	 # Set Sign
57153		 sltiu $18,$9,1         	 # Set Zero
57154	7:
57155		 bgez  $15,3f
57156		 lhu   $24,0x00($23)    	 # Delay slot
57157		 j     MainExit
57158	3:
57159		 sll   $7,$24,2         	 # Delay slot
57160		 addu  $7,$7,$30
57161		 lw    $7,0x00($7)
57162		 jr    $7
57163		 nop                    	 # Delay slot
57164
57165	8:
57166		 bgez  $0,7b
57167		 ori   $17,$0,1         	 # Selay slot - V flag
57168	9:		 # Do divide by zero trap
57169		 addiu $15,$15,112
57170		 jal   Exception
57171		 ori   $2,$0,5          	 # Delay slot
57172
57173		 bgez  $0,7b
57174		 nop                    	 # Delay slot
57175OP0_81e8:				#:
57176
57177		 addiu $23,$23,2
57178
57179		 addiu $15,$15,-158
57180		 andi  $8,$24,0x07
57181		 srl   $24,$24,7
57182		 andi  $24,$24,0x1C
57183		 lh    $7,0x00($23)
57184		 sll   $8,$8,2
57185		 addu  $8,$8,$21
57186		 lw    $14,0x20($8)
57187		 addiu $23,$23,2
57188		 addu  $14,$14,$7
57189		 lw    $25,0x80($21)
57190		 sw    $15,m68k_ICount
57191		 sw    $14,0x44($29)
57192		 sw    $24,0x40($29)
57193		 or    $4,$0,$14
57194		 jalr  $25
57195		 sw    $23,0x4C($21)    	 # Delay slot
57196		 lw    $24,0x40($29)
57197		 lw    $14,0x44($29)
57198		 lw    $15,m68k_ICount
57199		 seh   $2,$2
57200		 beq   $2,$0,9f         	 # do div by zero trap
57201		 nop                    	 # Delay slot
57202		 addu  $24,$24,$21
57203		 lw    $8,0x00($24)
57204		 div   $0,$8,$2
57205		 mflo  $9
57206		 sll   $8,$9,16
57207		 sra   $8,$8,16
57208		 bne   $8,$9,8f
57209		 andi  $9,$9,0xffff     	 # Delay slot
57210		 mfhi  $3
57211		 sll   $3,$3,16
57212		 or    $2,$9,$3
57213		 sw    $2,0x00($24)
57214		 and   $16,$0,$0        	 # Clear Carry
57215		 and   $17,$0,$0        	 # Clear Overflow
57216		 srl   $19,$9,15         	 # Set Sign
57217		 sltiu $18,$9,1         	 # Set Zero
57218	7:
57219		 bgez  $15,3f
57220		 lhu   $24,0x00($23)    	 # Delay slot
57221		 j     MainExit
57222	3:
57223		 sll   $7,$24,2         	 # Delay slot
57224		 addu  $7,$7,$30
57225		 lw    $7,0x00($7)
57226		 jr    $7
57227		 nop                    	 # Delay slot
57228
57229	8:
57230		 bgez  $0,7b
57231		 ori   $17,$0,1         	 # Selay slot - V flag
57232	9:		 # Do divide by zero trap
57233		 addiu $15,$15,112
57234		 jal   Exception
57235		 ori   $2,$0,5          	 # Delay slot
57236
57237		 bgez  $0,7b
57238		 nop                    	 # Delay slot
57239OP0_81f0:				#:
57240
57241		 addiu $23,$23,2
57242
57243		 addiu $15,$15,-162
57244		 andi  $8,$24,0x07
57245		 srl   $24,$24,7
57246		 andi  $24,$24,0x1C
57247		 sll   $8,$8,2
57248		 addu  $8,$8,$21
57249		 lw    $14,0x20($8)
57250		 lhu   $7,0x00($23)
57251		 addiu $23,$23,2
57252		 seb   $6,$7
57253		 or    $25,$0,$7
57254		 srl   $7,$7,12
57255		 andi  $25,$25,0x0800
57256		 sll   $7,$7,2
57257		 addu  $7,$7,$21
57258		 bne   $25,$0,0f
57259		 lw    $25,0x00($7)      	 # Delay slot
57260		 seh   $25,$25
57261	0:
57262		 addu  $25,$14,$25
57263		 addu  $14,$25,$6
57264		 lw    $25,0x80($21)
57265		 sw    $15,m68k_ICount
57266		 sw    $14,0x44($29)
57267		 sw    $24,0x40($29)
57268		 or    $4,$0,$14
57269		 jalr  $25
57270		 sw    $23,0x4C($21)    	 # Delay slot
57271		 lw    $24,0x40($29)
57272		 lw    $14,0x44($29)
57273		 lw    $15,m68k_ICount
57274		 seh   $2,$2
57275		 beq   $2,$0,9f         	 # do div by zero trap
57276		 nop                    	 # Delay slot
57277		 addu  $24,$24,$21
57278		 lw    $8,0x00($24)
57279		 div   $0,$8,$2
57280		 mflo  $9
57281		 sll   $8,$9,16
57282		 sra   $8,$8,16
57283		 bne   $8,$9,8f
57284		 andi  $9,$9,0xffff     	 # Delay slot
57285		 mfhi  $3
57286		 sll   $3,$3,16
57287		 or    $2,$9,$3
57288		 sw    $2,0x00($24)
57289		 and   $16,$0,$0        	 # Clear Carry
57290		 and   $17,$0,$0        	 # Clear Overflow
57291		 srl   $19,$9,15         	 # Set Sign
57292		 sltiu $18,$9,1         	 # Set Zero
57293	7:
57294		 bgez  $15,3f
57295		 lhu   $24,0x00($23)    	 # Delay slot
57296		 j     MainExit
57297	3:
57298		 sll   $7,$24,2         	 # Delay slot
57299		 addu  $7,$7,$30
57300		 lw    $7,0x00($7)
57301		 jr    $7
57302		 nop                    	 # Delay slot
57303
57304	8:
57305		 bgez  $0,7b
57306		 ori   $17,$0,1         	 # Selay slot - V flag
57307	9:		 # Do divide by zero trap
57308		 addiu $15,$15,112
57309		 jal   Exception
57310		 ori   $2,$0,5          	 # Delay slot
57311
57312		 bgez  $0,7b
57313		 nop                    	 # Delay slot
57314OP0_81f8:				#:
57315
57316		 addiu $23,$23,2
57317
57318		 addiu $15,$15,-158
57319		 srl   $24,$24,7
57320		 andi  $24,$24,0x1C
57321		 lh    $14,0x00($23)
57322		 addiu $23,$23,2
57323		 lw    $25,0x80($21)
57324		 sw    $15,m68k_ICount
57325		 sw    $14,0x44($29)
57326		 sw    $24,0x40($29)
57327		 or    $4,$0,$14
57328		 jalr  $25
57329		 sw    $23,0x4C($21)    	 # Delay slot
57330		 lw    $24,0x40($29)
57331		 lw    $14,0x44($29)
57332		 lw    $15,m68k_ICount
57333		 seh   $2,$2
57334		 beq   $2,$0,9f         	 # do div by zero trap
57335		 nop                    	 # Delay slot
57336		 addu  $24,$24,$21
57337		 lw    $8,0x00($24)
57338		 div   $0,$8,$2
57339		 mflo  $9
57340		 sll   $8,$9,16
57341		 sra   $8,$8,16
57342		 bne   $8,$9,8f
57343		 andi  $9,$9,0xffff     	 # Delay slot
57344		 mfhi  $3
57345		 sll   $3,$3,16
57346		 or    $2,$9,$3
57347		 sw    $2,0x00($24)
57348		 and   $16,$0,$0        	 # Clear Carry
57349		 and   $17,$0,$0        	 # Clear Overflow
57350		 srl   $19,$9,15         	 # Set Sign
57351		 sltiu $18,$9,1         	 # Set Zero
57352	7:
57353		 bgez  $15,3f
57354		 lhu   $24,0x00($23)    	 # Delay slot
57355		 j     MainExit
57356	3:
57357		 sll   $7,$24,2         	 # Delay slot
57358		 addu  $7,$7,$30
57359		 lw    $7,0x00($7)
57360		 jr    $7
57361		 nop                    	 # Delay slot
57362
57363	8:
57364		 bgez  $0,7b
57365		 ori   $17,$0,1         	 # Selay slot - V flag
57366	9:		 # Do divide by zero trap
57367		 addiu $15,$15,112
57368		 jal   Exception
57369		 ori   $2,$0,5          	 # Delay slot
57370
57371		 bgez  $0,7b
57372		 nop                    	 # Delay slot
57373OP0_81f9:				#:
57374
57375		 addiu $23,$23,2
57376
57377		 addiu $15,$15,-162
57378		 srl   $24,$24,7
57379		 andi  $24,$24,0x1C
57380		 lhu   $14,0x00($23)
57381		 lhu   $25,0x02($23)
57382		 sll   $14,$14,16
57383		 or    $14,$14,$25
57384		 addiu $23,$23,4
57385		 lw    $25,0x80($21)
57386		 sw    $15,m68k_ICount
57387		 sw    $14,0x44($29)
57388		 sw    $24,0x40($29)
57389		 or    $4,$0,$14
57390		 jalr  $25
57391		 sw    $23,0x4C($21)    	 # Delay slot
57392		 lw    $24,0x40($29)
57393		 lw    $14,0x44($29)
57394		 lw    $15,m68k_ICount
57395		 seh   $2,$2
57396		 beq   $2,$0,9f         	 # do div by zero trap
57397		 nop                    	 # Delay slot
57398		 addu  $24,$24,$21
57399		 lw    $8,0x00($24)
57400		 div   $0,$8,$2
57401		 mflo  $9
57402		 sll   $8,$9,16
57403		 sra   $8,$8,16
57404		 bne   $8,$9,8f
57405		 andi  $9,$9,0xffff     	 # Delay slot
57406		 mfhi  $3
57407		 sll   $3,$3,16
57408		 or    $2,$9,$3
57409		 sw    $2,0x00($24)
57410		 and   $16,$0,$0        	 # Clear Carry
57411		 and   $17,$0,$0        	 # Clear Overflow
57412		 srl   $19,$9,15         	 # Set Sign
57413		 sltiu $18,$9,1         	 # Set Zero
57414	7:
57415		 bgez  $15,3f
57416		 lhu   $24,0x00($23)    	 # Delay slot
57417		 j     MainExit
57418	3:
57419		 sll   $7,$24,2         	 # Delay slot
57420		 addu  $7,$7,$30
57421		 lw    $7,0x00($7)
57422		 jr    $7
57423		 nop                    	 # Delay slot
57424
57425	8:
57426		 bgez  $0,7b
57427		 ori   $17,$0,1         	 # Selay slot - V flag
57428	9:		 # Do divide by zero trap
57429		 addiu $15,$15,112
57430		 jal   Exception
57431		 ori   $2,$0,5          	 # Delay slot
57432
57433		 bgez  $0,7b
57434		 nop                    	 # Delay slot
57435OP0_81fa:				#:
57436
57437		 addiu $23,$23,2
57438
57439		 addiu $15,$15,-158
57440		 srl   $24,$24,7
57441		 andi  $24,$24,0x1C
57442		 lh    $7,0x00($23)
57443		 subu  $25,$23,$22
57444		 addu  $14,$25,$7       	 # Add Offset to PC
57445		 addiu $23,$23,2
57446		 lw    $25,0x9C($21)
57447		 sw    $15,m68k_ICount
57448		 sw    $14,0x44($29)
57449		 sw    $24,0x40($29)
57450		 or    $4,$0,$14
57451		 jalr  $25
57452		 sw    $23,0x4C($21)    	 # Delay slot
57453		 lw    $24,0x40($29)
57454		 lw    $14,0x44($29)
57455		 lw    $15,m68k_ICount
57456		 seh   $2,$2
57457		 beq   $2,$0,9f         	 # do div by zero trap
57458		 nop                    	 # Delay slot
57459		 addu  $24,$24,$21
57460		 lw    $8,0x00($24)
57461		 div   $0,$8,$2
57462		 mflo  $9
57463		 sll   $8,$9,16
57464		 sra   $8,$8,16
57465		 bne   $8,$9,8f
57466		 andi  $9,$9,0xffff     	 # Delay slot
57467		 mfhi  $3
57468		 sll   $3,$3,16
57469		 or    $2,$9,$3
57470		 sw    $2,0x00($24)
57471		 and   $16,$0,$0        	 # Clear Carry
57472		 and   $17,$0,$0        	 # Clear Overflow
57473		 srl   $19,$9,15         	 # Set Sign
57474		 sltiu $18,$9,1         	 # Set Zero
57475	7:
57476		 bgez  $15,3f
57477		 lhu   $24,0x00($23)    	 # Delay slot
57478		 j     MainExit
57479	3:
57480		 sll   $7,$24,2         	 # Delay slot
57481		 addu  $7,$7,$30
57482		 lw    $7,0x00($7)
57483		 jr    $7
57484		 nop                    	 # Delay slot
57485
57486	8:
57487		 bgez  $0,7b
57488		 ori   $17,$0,1         	 # Selay slot - V flag
57489	9:		 # Do divide by zero trap
57490		 addiu $15,$15,112
57491		 jal   Exception
57492		 ori   $2,$0,5          	 # Delay slot
57493
57494		 bgez  $0,7b
57495		 nop                    	 # Delay slot
57496OP0_81fb:				#:
57497
57498		 addiu $23,$23,2
57499
57500		 addiu $15,$15,-160
57501		 srl   $24,$24,7
57502		 andi  $24,$24,0x1C
57503		 subu  $14,$23,$22       	 # Get PC
57504		 lhu   $7,0x00($23)
57505		 addiu $23,$23,2
57506		 seb   $6,$7
57507		 or    $25,$0,$7
57508		 srl   $7,$7,12
57509		 andi  $25,$25,0x0800
57510		 sll   $7,$7,2
57511		 addu  $7,$7,$21
57512		 bne   $25,$0,0f
57513		 lw    $25,0x00($7)      	 # Delay slot
57514		 seh   $25,$25
57515	0:
57516		 addu  $25,$14,$25
57517		 addu  $14,$25,$6
57518		 lw    $25,0x9C($21)
57519		 sw    $15,m68k_ICount
57520		 sw    $14,0x44($29)
57521		 sw    $24,0x40($29)
57522		 or    $4,$0,$14
57523		 jalr  $25
57524		 sw    $23,0x4C($21)    	 # Delay slot
57525		 lw    $24,0x40($29)
57526		 lw    $14,0x44($29)
57527		 lw    $15,m68k_ICount
57528		 seh   $2,$2
57529		 beq   $2,$0,9f         	 # do div by zero trap
57530		 nop                    	 # Delay slot
57531		 addu  $24,$24,$21
57532		 lw    $8,0x00($24)
57533		 div   $0,$8,$2
57534		 mflo  $9
57535		 sll   $8,$9,16
57536		 sra   $8,$8,16
57537		 bne   $8,$9,8f
57538		 andi  $9,$9,0xffff     	 # Delay slot
57539		 mfhi  $3
57540		 sll   $3,$3,16
57541		 or    $2,$9,$3
57542		 sw    $2,0x00($24)
57543		 and   $16,$0,$0        	 # Clear Carry
57544		 and   $17,$0,$0        	 # Clear Overflow
57545		 srl   $19,$9,15         	 # Set Sign
57546		 sltiu $18,$9,1         	 # Set Zero
57547	7:
57548		 bgez  $15,3f
57549		 lhu   $24,0x00($23)    	 # Delay slot
57550		 j     MainExit
57551	3:
57552		 sll   $7,$24,2         	 # Delay slot
57553		 addu  $7,$7,$30
57554		 lw    $7,0x00($7)
57555		 jr    $7
57556		 nop                    	 # Delay slot
57557
57558	8:
57559		 bgez  $0,7b
57560		 ori   $17,$0,1         	 # Selay slot - V flag
57561	9:		 # Do divide by zero trap
57562		 addiu $15,$15,112
57563		 jal   Exception
57564		 ori   $2,$0,5          	 # Delay slot
57565
57566		 bgez  $0,7b
57567		 nop                    	 # Delay slot
57568OP0_81fc:				#:
57569
57570		 addiu $23,$23,2
57571
57572		 addiu $15,$15,-154
57573		 srl   $24,$24,7
57574		 andi  $24,$24,0x1C
57575		 lh    $2,0x00($23)
57576		 addiu $23,$23,2
57577		 beq   $2,$0,9f         	 # do div by zero trap
57578		 nop                    	 # Delay slot
57579		 addu  $24,$24,$21
57580		 lw    $8,0x00($24)
57581		 div   $0,$8,$2
57582		 mflo  $9
57583		 sll   $8,$9,16
57584		 sra   $8,$8,16
57585		 bne   $8,$9,8f
57586		 andi  $9,$9,0xffff     	 # Delay slot
57587		 mfhi  $3
57588		 sll   $3,$3,16
57589		 or    $2,$9,$3
57590		 sw    $2,0x00($24)
57591		 and   $16,$0,$0        	 # Clear Carry
57592		 and   $17,$0,$0        	 # Clear Overflow
57593		 srl   $19,$9,15         	 # Set Sign
57594		 sltiu $18,$9,1         	 # Set Zero
57595	7:
57596		 bgez  $15,3f
57597		 lhu   $24,0x00($23)    	 # Delay slot
57598		 j     MainExit
57599	3:
57600		 sll   $7,$24,2         	 # Delay slot
57601		 addu  $7,$7,$30
57602		 lw    $7,0x00($7)
57603		 jr    $7
57604		 nop                    	 # Delay slot
57605
57606	8:
57607		 bgez  $0,7b
57608		 ori   $17,$0,1         	 # Selay slot - V flag
57609	9:		 # Do divide by zero trap
57610		 addiu $15,$15,112
57611		 jal   Exception
57612		 ori   $2,$0,5          	 # Delay slot
57613
57614		 bgez  $0,7b
57615		 nop                    	 # Delay slot
57616OP0_4840:				#:
57617		 addiu $23,$23,2
57618
57619		 andi  $24,$24,0x07
57620		 sll   $24,$24,2
57621		 addu  $24,$24,$21
57622		 lw    $2,0x00($24)
57623		 ror   $2,$2,16
57624		 sw    $2,0x00($24)
57625		 and   $16,$0,$0        	 # Clear Carry
57626		 and   $17,$0,$0        	 # Clear Overflow
57627		 slt   $19,$2,$0        	 # Set Sign
57628		 sltiu $18,$2,1         	 # Set Zero
57629		 addiu $15,$15,-4
57630		 bgez  $15,3f
57631		 lhu   $24,0x00($23)    	 # Delay slot
57632		 j     MainExit
57633	3:
57634		 sll   $7,$24,2         	 # Delay slot
57635		 addu  $7,$7,$30
57636		 lw    $7,0x00($7)
57637		 jr    $7
57638		 nop                    	 # Delay slot
57639
57640OP0_4000:				#:
57641		 addiu $23,$23,2
57642
57643		 andi  $24,$24,0x07
57644		 sll   $24,$24,2
57645		 addu  $24,$24,$21
57646		 lb    $8,0x00($24)
57647		 addu  $2,$8,$20
57648		 subu  $2,$0,$2
57649		 addu  $25,$8,$20
57650		 sltu  $16,$0,$25       	 # Set Carry
57651		 xor   $17,$0,$8
57652		 xor   $25,$2,$0
57653		 and   $17,$17,$25
57654		 srl   $17,$17,7
57655		 andi  $17,$17,0x01     	 # Set Overflow
57656		 seb  $25,$2
57657		 slt   $19,$25,$0        	 # Set Sign
57658		 sltiu $25,$25,1
57659		 and   $18,$18,$25      	 # Set Zero
57660		 or    $20,$0,$16      	 # Copy Carry to X
57661		 sb    $2,0x00($24)
57662		 addiu $15,$15,-4
57663		 bgez  $15,3f
57664		 lhu   $24,0x00($23)    	 # Delay slot
57665		 j     MainExit
57666	3:
57667		 sll   $7,$24,2         	 # Delay slot
57668		 addu  $7,$7,$30
57669		 lw    $7,0x00($7)
57670		 jr    $7
57671		 nop                    	 # Delay slot
57672
57673OP0_4010:				#:
57674		 addiu $23,$23,2
57675
57676		 andi  $24,$24,0x07
57677		 sll   $24,$24,2
57678		 addu  $24,$24,$21
57679		 lw    $14,0x20($24)
57680		 lw    $25,0x7C($21)
57681		 sw    $15,m68k_ICount
57682		 sw    $14,0x44($29)
57683		 or    $4,$0,$14
57684		 jalr  $25
57685		 sw    $23,0x4C($21)    	 # Delay slot
57686		 lw    $14,0x44($29)
57687		 lw    $15,m68k_ICount
57688		 seb   $8,$2
57689		 addu  $2,$8,$20
57690		 subu  $2,$0,$2
57691		 addu  $25,$8,$20
57692		 sltu  $16,$0,$25       	 # Set Carry
57693		 xor   $17,$0,$8
57694		 xor   $25,$2,$0
57695		 and   $17,$17,$25
57696		 srl   $17,$17,7
57697		 andi  $17,$17,0x01     	 # Set Overflow
57698		 seb  $25,$2
57699		 slt   $19,$25,$0        	 # Set Sign
57700		 sltiu $25,$25,1
57701		 and   $18,$18,$25      	 # Set Zero
57702		 or    $20,$0,$16      	 # Copy Carry to X
57703		 lw    $25,0x88($21)
57704		 sw    $15,m68k_ICount
57705		 or    $5,$0,$2
57706		 or    $4,$0,$14
57707		 jalr  $25
57708		 sw    $23,0x4C($21)    	 # Delay slot
57709		 lw    $15,m68k_ICount
57710		 addiu $15,$15,-8
57711		 bgez  $15,3f
57712		 lhu   $24,0x00($23)    	 # Delay slot
57713		 j     MainExit
57714	3:
57715		 sll   $7,$24,2         	 # Delay slot
57716		 addu  $7,$7,$30
57717		 lw    $7,0x00($7)
57718		 jr    $7
57719		 nop                    	 # Delay slot
57720
57721OP0_4018:				#:
57722		 addiu $23,$23,2
57723
57724		 andi  $24,$24,0x07
57725		 sll   $24,$24,2
57726		 addu  $24,$24,$21
57727		 lw    $14,0x20($24)
57728		 addiu $25,$14,1
57729		 sw    $25,0x20($24)
57730		 lw    $25,0x7C($21)
57731		 sw    $15,m68k_ICount
57732		 sw    $14,0x44($29)
57733		 or    $4,$0,$14
57734		 jalr  $25
57735		 sw    $23,0x4C($21)    	 # Delay slot
57736		 lw    $14,0x44($29)
57737		 lw    $15,m68k_ICount
57738		 seb   $8,$2
57739		 addu  $2,$8,$20
57740		 subu  $2,$0,$2
57741		 addu  $25,$8,$20
57742		 sltu  $16,$0,$25       	 # Set Carry
57743		 xor   $17,$0,$8
57744		 xor   $25,$2,$0
57745		 and   $17,$17,$25
57746		 srl   $17,$17,7
57747		 andi  $17,$17,0x01     	 # Set Overflow
57748		 seb  $25,$2
57749		 slt   $19,$25,$0        	 # Set Sign
57750		 sltiu $25,$25,1
57751		 and   $18,$18,$25      	 # Set Zero
57752		 or    $20,$0,$16      	 # Copy Carry to X
57753		 lw    $25,0x88($21)
57754		 sw    $15,m68k_ICount
57755		 or    $5,$0,$2
57756		 or    $4,$0,$14
57757		 jalr  $25
57758		 sw    $23,0x4C($21)    	 # Delay slot
57759		 lw    $15,m68k_ICount
57760		 addiu $15,$15,-8
57761		 bgez  $15,3f
57762		 lhu   $24,0x00($23)    	 # Delay slot
57763		 j     MainExit
57764	3:
57765		 sll   $7,$24,2         	 # Delay slot
57766		 addu  $7,$7,$30
57767		 lw    $7,0x00($7)
57768		 jr    $7
57769		 nop                    	 # Delay slot
57770
57771OP0_401f:				#:
57772		 addiu $23,$23,2
57773
57774		 lw    $14,0x3C($21)    	 # Get A7
57775		 addiu $25,$14,2
57776		 sw    $25,0x3C($21)
57777		 lw    $25,0x7C($21)
57778		 sw    $15,m68k_ICount
57779		 sw    $14,0x44($29)
57780		 or    $4,$0,$14
57781		 jalr  $25
57782		 sw    $23,0x4C($21)    	 # Delay slot
57783		 lw    $14,0x44($29)
57784		 lw    $15,m68k_ICount
57785		 seb   $8,$2
57786		 addu  $2,$8,$20
57787		 subu  $2,$0,$2
57788		 addu  $25,$8,$20
57789		 sltu  $16,$0,$25       	 # Set Carry
57790		 xor   $17,$0,$8
57791		 xor   $25,$2,$0
57792		 and   $17,$17,$25
57793		 srl   $17,$17,7
57794		 andi  $17,$17,0x01     	 # Set Overflow
57795		 seb  $25,$2
57796		 slt   $19,$25,$0        	 # Set Sign
57797		 sltiu $25,$25,1
57798		 and   $18,$18,$25      	 # Set Zero
57799		 or    $20,$0,$16      	 # Copy Carry to X
57800		 lw    $25,0x88($21)
57801		 sw    $15,m68k_ICount
57802		 or    $5,$0,$2
57803		 or    $4,$0,$14
57804		 jalr  $25
57805		 sw    $23,0x4C($21)    	 # Delay slot
57806		 lw    $15,m68k_ICount
57807		 addiu $15,$15,-8
57808		 bgez  $15,3f
57809		 lhu   $24,0x00($23)    	 # Delay slot
57810		 j     MainExit
57811	3:
57812		 sll   $7,$24,2         	 # Delay slot
57813		 addu  $7,$7,$30
57814		 lw    $7,0x00($7)
57815		 jr    $7
57816		 nop                    	 # Delay slot
57817
57818OP0_4020:				#:
57819		 addiu $23,$23,2
57820
57821		 andi  $24,$24,0x07
57822		 sll   $24,$24,2
57823		 addu  $24,$24,$21
57824		 lw    $14,0x20($24)
57825		 addiu $14,$14,-1
57826		 sw    $14,0x20($24)
57827		 lw    $25,0x7C($21)
57828		 sw    $15,m68k_ICount
57829		 sw    $14,0x44($29)
57830		 or    $4,$0,$14
57831		 jalr  $25
57832		 sw    $23,0x4C($21)    	 # Delay slot
57833		 lw    $14,0x44($29)
57834		 lw    $15,m68k_ICount
57835		 seb   $8,$2
57836		 addu  $2,$8,$20
57837		 subu  $2,$0,$2
57838		 addu  $25,$8,$20
57839		 sltu  $16,$0,$25       	 # Set Carry
57840		 xor   $17,$0,$8
57841		 xor   $25,$2,$0
57842		 and   $17,$17,$25
57843		 srl   $17,$17,7
57844		 andi  $17,$17,0x01     	 # Set Overflow
57845		 seb  $25,$2
57846		 slt   $19,$25,$0        	 # Set Sign
57847		 sltiu $25,$25,1
57848		 and   $18,$18,$25      	 # Set Zero
57849		 or    $20,$0,$16      	 # Copy Carry to X
57850		 lw    $25,0x88($21)
57851		 sw    $15,m68k_ICount
57852		 or    $5,$0,$2
57853		 or    $4,$0,$14
57854		 jalr  $25
57855		 sw    $23,0x4C($21)    	 # Delay slot
57856		 lw    $15,m68k_ICount
57857		 addiu $15,$15,-10
57858		 bgez  $15,3f
57859		 lhu   $24,0x00($23)    	 # Delay slot
57860		 j     MainExit
57861	3:
57862		 sll   $7,$24,2         	 # Delay slot
57863		 addu  $7,$7,$30
57864		 lw    $7,0x00($7)
57865		 jr    $7
57866		 nop                    	 # Delay slot
57867
57868OP0_4027:				#:
57869		 addiu $23,$23,2
57870
57871		 lw    $14,0x3C($21)    	 # Get A7
57872		 addiu $14,$14,-2
57873		 sw    $14,0x3C($21)
57874		 lw    $25,0x7C($21)
57875		 sw    $15,m68k_ICount
57876		 sw    $14,0x44($29)
57877		 or    $4,$0,$14
57878		 jalr  $25
57879		 sw    $23,0x4C($21)    	 # Delay slot
57880		 lw    $14,0x44($29)
57881		 lw    $15,m68k_ICount
57882		 seb   $8,$2
57883		 addu  $2,$8,$20
57884		 subu  $2,$0,$2
57885		 addu  $25,$8,$20
57886		 sltu  $16,$0,$25       	 # Set Carry
57887		 xor   $17,$0,$8
57888		 xor   $25,$2,$0
57889		 and   $17,$17,$25
57890		 srl   $17,$17,7
57891		 andi  $17,$17,0x01     	 # Set Overflow
57892		 seb  $25,$2
57893		 slt   $19,$25,$0        	 # Set Sign
57894		 sltiu $25,$25,1
57895		 and   $18,$18,$25      	 # Set Zero
57896		 or    $20,$0,$16      	 # Copy Carry to X
57897		 lw    $25,0x88($21)
57898		 sw    $15,m68k_ICount
57899		 or    $5,$0,$2
57900		 or    $4,$0,$14
57901		 jalr  $25
57902		 sw    $23,0x4C($21)    	 # Delay slot
57903		 lw    $15,m68k_ICount
57904		 addiu $15,$15,-10
57905		 bgez  $15,3f
57906		 lhu   $24,0x00($23)    	 # Delay slot
57907		 j     MainExit
57908	3:
57909		 sll   $7,$24,2         	 # Delay slot
57910		 addu  $7,$7,$30
57911		 lw    $7,0x00($7)
57912		 jr    $7
57913		 nop                    	 # Delay slot
57914
57915OP0_4028:				#:
57916		 addiu $23,$23,2
57917
57918		 andi  $24,$24,0x07
57919		 lh    $7,0x00($23)
57920		 sll   $24,$24,2
57921		 addu  $24,$24,$21
57922		 lw    $14,0x20($24)
57923		 addiu $23,$23,2
57924		 addu  $14,$14,$7
57925		 lw    $25,0x7C($21)
57926		 sw    $15,m68k_ICount
57927		 sw    $14,0x44($29)
57928		 or    $4,$0,$14
57929		 jalr  $25
57930		 sw    $23,0x4C($21)    	 # Delay slot
57931		 lw    $14,0x44($29)
57932		 lw    $15,m68k_ICount
57933		 seb   $8,$2
57934		 addu  $2,$8,$20
57935		 subu  $2,$0,$2
57936		 addu  $25,$8,$20
57937		 sltu  $16,$0,$25       	 # Set Carry
57938		 xor   $17,$0,$8
57939		 xor   $25,$2,$0
57940		 and   $17,$17,$25
57941		 srl   $17,$17,7
57942		 andi  $17,$17,0x01     	 # Set Overflow
57943		 seb  $25,$2
57944		 slt   $19,$25,$0        	 # Set Sign
57945		 sltiu $25,$25,1
57946		 and   $18,$18,$25      	 # Set Zero
57947		 or    $20,$0,$16      	 # Copy Carry to X
57948		 lw    $25,0x88($21)
57949		 sw    $15,m68k_ICount
57950		 or    $5,$0,$2
57951		 or    $4,$0,$14
57952		 jalr  $25
57953		 sw    $23,0x4C($21)    	 # Delay slot
57954		 lw    $15,m68k_ICount
57955		 addiu $15,$15,-12
57956		 bgez  $15,3f
57957		 lhu   $24,0x00($23)    	 # Delay slot
57958		 j     MainExit
57959	3:
57960		 sll   $7,$24,2         	 # Delay slot
57961		 addu  $7,$7,$30
57962		 lw    $7,0x00($7)
57963		 jr    $7
57964		 nop                    	 # Delay slot
57965
57966OP0_4030:				#:
57967		 addiu $23,$23,2
57968
57969		 andi  $24,$24,0x07
57970		 sll   $24,$24,2
57971		 addu  $24,$24,$21
57972		 lw    $14,0x20($24)
57973		 lhu   $7,0x00($23)
57974		 addiu $23,$23,2
57975		 seb   $6,$7
57976		 or    $25,$0,$7
57977		 srl   $7,$7,12
57978		 andi  $25,$25,0x0800
57979		 sll   $7,$7,2
57980		 addu  $7,$7,$21
57981		 bne   $25,$0,0f
57982		 lw    $25,0x00($7)      	 # Delay slot
57983		 seh   $25,$25
57984	0:
57985		 addu  $25,$14,$25
57986		 addu  $14,$25,$6
57987		 lw    $25,0x7C($21)
57988		 sw    $15,m68k_ICount
57989		 sw    $14,0x44($29)
57990		 or    $4,$0,$14
57991		 jalr  $25
57992		 sw    $23,0x4C($21)    	 # Delay slot
57993		 lw    $14,0x44($29)
57994		 lw    $15,m68k_ICount
57995		 seb   $8,$2
57996		 addu  $2,$8,$20
57997		 subu  $2,$0,$2
57998		 addu  $25,$8,$20
57999		 sltu  $16,$0,$25       	 # Set Carry
58000		 xor   $17,$0,$8
58001		 xor   $25,$2,$0
58002		 and   $17,$17,$25
58003		 srl   $17,$17,7
58004		 andi  $17,$17,0x01     	 # Set Overflow
58005		 seb  $25,$2
58006		 slt   $19,$25,$0        	 # Set Sign
58007		 sltiu $25,$25,1
58008		 and   $18,$18,$25      	 # Set Zero
58009		 or    $20,$0,$16      	 # Copy Carry to X
58010		 lw    $25,0x88($21)
58011		 sw    $15,m68k_ICount
58012		 or    $5,$0,$2
58013		 or    $4,$0,$14
58014		 jalr  $25
58015		 sw    $23,0x4C($21)    	 # Delay slot
58016		 lw    $15,m68k_ICount
58017		 addiu $15,$15,-14
58018		 bgez  $15,3f
58019		 lhu   $24,0x00($23)    	 # Delay slot
58020		 j     MainExit
58021	3:
58022		 sll   $7,$24,2         	 # Delay slot
58023		 addu  $7,$7,$30
58024		 lw    $7,0x00($7)
58025		 jr    $7
58026		 nop                    	 # Delay slot
58027
58028OP0_4038:				#:
58029		 addiu $23,$23,2
58030
58031		 lh    $14,0x00($23)
58032		 addiu $23,$23,2
58033		 lw    $25,0x7C($21)
58034		 sw    $15,m68k_ICount
58035		 sw    $14,0x44($29)
58036		 or    $4,$0,$14
58037		 jalr  $25
58038		 sw    $23,0x4C($21)    	 # Delay slot
58039		 lw    $14,0x44($29)
58040		 lw    $15,m68k_ICount
58041		 seb   $8,$2
58042		 addu  $2,$8,$20
58043		 subu  $2,$0,$2
58044		 addu  $25,$8,$20
58045		 sltu  $16,$0,$25       	 # Set Carry
58046		 xor   $17,$0,$8
58047		 xor   $25,$2,$0
58048		 and   $17,$17,$25
58049		 srl   $17,$17,7
58050		 andi  $17,$17,0x01     	 # Set Overflow
58051		 seb  $25,$2
58052		 slt   $19,$25,$0        	 # Set Sign
58053		 sltiu $25,$25,1
58054		 and   $18,$18,$25      	 # Set Zero
58055		 or    $20,$0,$16      	 # Copy Carry to X
58056		 lw    $25,0x88($21)
58057		 sw    $15,m68k_ICount
58058		 or    $5,$0,$2
58059		 or    $4,$0,$14
58060		 jalr  $25
58061		 sw    $23,0x4C($21)    	 # Delay slot
58062		 lw    $15,m68k_ICount
58063		 addiu $15,$15,-12
58064		 bgez  $15,3f
58065		 lhu   $24,0x00($23)    	 # Delay slot
58066		 j     MainExit
58067	3:
58068		 sll   $7,$24,2         	 # Delay slot
58069		 addu  $7,$7,$30
58070		 lw    $7,0x00($7)
58071		 jr    $7
58072		 nop                    	 # Delay slot
58073
58074OP0_4039:				#:
58075		 addiu $23,$23,2
58076
58077		 lhu   $14,0x00($23)
58078		 lhu   $25,0x02($23)
58079		 sll   $14,$14,16
58080		 or    $14,$14,$25
58081		 addiu $23,$23,4
58082		 lw    $25,0x7C($21)
58083		 sw    $15,m68k_ICount
58084		 sw    $14,0x44($29)
58085		 or    $4,$0,$14
58086		 jalr  $25
58087		 sw    $23,0x4C($21)    	 # Delay slot
58088		 lw    $14,0x44($29)
58089		 lw    $15,m68k_ICount
58090		 seb   $8,$2
58091		 addu  $2,$8,$20
58092		 subu  $2,$0,$2
58093		 addu  $25,$8,$20
58094		 sltu  $16,$0,$25       	 # Set Carry
58095		 xor   $17,$0,$8
58096		 xor   $25,$2,$0
58097		 and   $17,$17,$25
58098		 srl   $17,$17,7
58099		 andi  $17,$17,0x01     	 # Set Overflow
58100		 seb  $25,$2
58101		 slt   $19,$25,$0        	 # Set Sign
58102		 sltiu $25,$25,1
58103		 and   $18,$18,$25      	 # Set Zero
58104		 or    $20,$0,$16      	 # Copy Carry to X
58105		 lw    $25,0x88($21)
58106		 sw    $15,m68k_ICount
58107		 or    $5,$0,$2
58108		 or    $4,$0,$14
58109		 jalr  $25
58110		 sw    $23,0x4C($21)    	 # Delay slot
58111		 lw    $15,m68k_ICount
58112		 addiu $15,$15,-16
58113		 bgez  $15,3f
58114		 lhu   $24,0x00($23)    	 # Delay slot
58115		 j     MainExit
58116	3:
58117		 sll   $7,$24,2         	 # Delay slot
58118		 addu  $7,$7,$30
58119		 lw    $7,0x00($7)
58120		 jr    $7
58121		 nop                    	 # Delay slot
58122
58123OP0_4040:				#:
58124		 addiu $23,$23,2
58125
58126		 andi  $24,$24,0x07
58127		 sll   $24,$24,2
58128		 addu  $24,$24,$21
58129		 lh    $8,0x00($24)
58130		 addu  $2,$8,$20
58131		 subu  $2,$0,$2
58132		 addu  $25,$8,$20
58133		 sltu  $16,$0,$25       	 # Set Carry
58134		 xor   $17,$0,$8
58135		 xor   $25,$2,$0
58136		 and   $17,$17,$25
58137		 srl   $17,$17,15
58138		 andi  $17,$17,0x01     	 # Set Overflow
58139		 seh  $25,$2
58140		 slt   $19,$25,$0        	 # Set Sign
58141		 sltiu $25,$25,1
58142		 and   $18,$18,$25      	 # Set Zero
58143		 or    $20,$0,$16      	 # Copy Carry to X
58144		 sh    $2,0x00($24)
58145		 addiu $15,$15,-4
58146		 bgez  $15,3f
58147		 lhu   $24,0x00($23)    	 # Delay slot
58148		 j     MainExit
58149	3:
58150		 sll   $7,$24,2         	 # Delay slot
58151		 addu  $7,$7,$30
58152		 lw    $7,0x00($7)
58153		 jr    $7
58154		 nop                    	 # Delay slot
58155
58156OP0_4050:				#:
58157		 addiu $23,$23,2
58158
58159		 andi  $24,$24,0x07
58160		 sll   $24,$24,2
58161		 addu  $24,$24,$21
58162		 lw    $14,0x20($24)
58163		 lw    $25,0x80($21)
58164		 sw    $15,m68k_ICount
58165		 sw    $14,0x44($29)
58166		 or    $4,$0,$14
58167		 jalr  $25
58168		 sw    $23,0x4C($21)    	 # Delay slot
58169		 lw    $14,0x44($29)
58170		 lw    $15,m68k_ICount
58171		 seh   $8,$2
58172		 addu  $2,$8,$20
58173		 subu  $2,$0,$2
58174		 addu  $25,$8,$20
58175		 sltu  $16,$0,$25       	 # Set Carry
58176		 xor   $17,$0,$8
58177		 xor   $25,$2,$0
58178		 and   $17,$17,$25
58179		 srl   $17,$17,15
58180		 andi  $17,$17,0x01     	 # Set Overflow
58181		 seh  $25,$2
58182		 slt   $19,$25,$0        	 # Set Sign
58183		 sltiu $25,$25,1
58184		 and   $18,$18,$25      	 # Set Zero
58185		 or    $20,$0,$16      	 # Copy Carry to X
58186		 lw    $25,0x8C($21)
58187		 sw    $15,m68k_ICount
58188		 or    $5,$0,$2
58189		 or    $4,$0,$14
58190		 jalr  $25
58191		 sw    $23,0x4C($21)    	 # Delay slot
58192		 lw    $15,m68k_ICount
58193		 addiu $15,$15,-8
58194		 bgez  $15,3f
58195		 lhu   $24,0x00($23)    	 # Delay slot
58196		 j     MainExit
58197	3:
58198		 sll   $7,$24,2         	 # Delay slot
58199		 addu  $7,$7,$30
58200		 lw    $7,0x00($7)
58201		 jr    $7
58202		 nop                    	 # Delay slot
58203
58204OP0_4058:				#:
58205		 addiu $23,$23,2
58206
58207		 andi  $24,$24,0x07
58208		 sll   $24,$24,2
58209		 addu  $24,$24,$21
58210		 lw    $14,0x20($24)
58211		 addiu $25,$14,2
58212		 sw    $25,0x20($24)
58213		 lw    $25,0x80($21)
58214		 sw    $15,m68k_ICount
58215		 sw    $14,0x44($29)
58216		 or    $4,$0,$14
58217		 jalr  $25
58218		 sw    $23,0x4C($21)    	 # Delay slot
58219		 lw    $14,0x44($29)
58220		 lw    $15,m68k_ICount
58221		 seh   $8,$2
58222		 addu  $2,$8,$20
58223		 subu  $2,$0,$2
58224		 addu  $25,$8,$20
58225		 sltu  $16,$0,$25       	 # Set Carry
58226		 xor   $17,$0,$8
58227		 xor   $25,$2,$0
58228		 and   $17,$17,$25
58229		 srl   $17,$17,15
58230		 andi  $17,$17,0x01     	 # Set Overflow
58231		 seh  $25,$2
58232		 slt   $19,$25,$0        	 # Set Sign
58233		 sltiu $25,$25,1
58234		 and   $18,$18,$25      	 # Set Zero
58235		 or    $20,$0,$16      	 # Copy Carry to X
58236		 lw    $25,0x8C($21)
58237		 sw    $15,m68k_ICount
58238		 or    $5,$0,$2
58239		 or    $4,$0,$14
58240		 jalr  $25
58241		 sw    $23,0x4C($21)    	 # Delay slot
58242		 lw    $15,m68k_ICount
58243		 addiu $15,$15,-8
58244		 bgez  $15,3f
58245		 lhu   $24,0x00($23)    	 # Delay slot
58246		 j     MainExit
58247	3:
58248		 sll   $7,$24,2         	 # Delay slot
58249		 addu  $7,$7,$30
58250		 lw    $7,0x00($7)
58251		 jr    $7
58252		 nop                    	 # Delay slot
58253
58254OP0_4060:				#:
58255		 addiu $23,$23,2
58256
58257		 andi  $24,$24,0x07
58258		 sll   $24,$24,2
58259		 addu  $24,$24,$21
58260		 lw    $14,0x20($24)
58261		 addiu $14,$14,-2
58262		 sw    $14,0x20($24)
58263		 lw    $25,0x80($21)
58264		 sw    $15,m68k_ICount
58265		 sw    $14,0x44($29)
58266		 or    $4,$0,$14
58267		 jalr  $25
58268		 sw    $23,0x4C($21)    	 # Delay slot
58269		 lw    $14,0x44($29)
58270		 lw    $15,m68k_ICount
58271		 seh   $8,$2
58272		 addu  $2,$8,$20
58273		 subu  $2,$0,$2
58274		 addu  $25,$8,$20
58275		 sltu  $16,$0,$25       	 # Set Carry
58276		 xor   $17,$0,$8
58277		 xor   $25,$2,$0
58278		 and   $17,$17,$25
58279		 srl   $17,$17,15
58280		 andi  $17,$17,0x01     	 # Set Overflow
58281		 seh  $25,$2
58282		 slt   $19,$25,$0        	 # Set Sign
58283		 sltiu $25,$25,1
58284		 and   $18,$18,$25      	 # Set Zero
58285		 or    $20,$0,$16      	 # Copy Carry to X
58286		 lw    $25,0x8C($21)
58287		 sw    $15,m68k_ICount
58288		 or    $5,$0,$2
58289		 or    $4,$0,$14
58290		 jalr  $25
58291		 sw    $23,0x4C($21)    	 # Delay slot
58292		 lw    $15,m68k_ICount
58293		 addiu $15,$15,-10
58294		 bgez  $15,3f
58295		 lhu   $24,0x00($23)    	 # Delay slot
58296		 j     MainExit
58297	3:
58298		 sll   $7,$24,2         	 # Delay slot
58299		 addu  $7,$7,$30
58300		 lw    $7,0x00($7)
58301		 jr    $7
58302		 nop                    	 # Delay slot
58303
58304OP0_4068:				#:
58305		 addiu $23,$23,2
58306
58307		 andi  $24,$24,0x07
58308		 lh    $7,0x00($23)
58309		 sll   $24,$24,2
58310		 addu  $24,$24,$21
58311		 lw    $14,0x20($24)
58312		 addiu $23,$23,2
58313		 addu  $14,$14,$7
58314		 lw    $25,0x80($21)
58315		 sw    $15,m68k_ICount
58316		 sw    $14,0x44($29)
58317		 or    $4,$0,$14
58318		 jalr  $25
58319		 sw    $23,0x4C($21)    	 # Delay slot
58320		 lw    $14,0x44($29)
58321		 lw    $15,m68k_ICount
58322		 seh   $8,$2
58323		 addu  $2,$8,$20
58324		 subu  $2,$0,$2
58325		 addu  $25,$8,$20
58326		 sltu  $16,$0,$25       	 # Set Carry
58327		 xor   $17,$0,$8
58328		 xor   $25,$2,$0
58329		 and   $17,$17,$25
58330		 srl   $17,$17,15
58331		 andi  $17,$17,0x01     	 # Set Overflow
58332		 seh  $25,$2
58333		 slt   $19,$25,$0        	 # Set Sign
58334		 sltiu $25,$25,1
58335		 and   $18,$18,$25      	 # Set Zero
58336		 or    $20,$0,$16      	 # Copy Carry to X
58337		 lw    $25,0x8C($21)
58338		 sw    $15,m68k_ICount
58339		 or    $5,$0,$2
58340		 or    $4,$0,$14
58341		 jalr  $25
58342		 sw    $23,0x4C($21)    	 # Delay slot
58343		 lw    $15,m68k_ICount
58344		 addiu $15,$15,-12
58345		 bgez  $15,3f
58346		 lhu   $24,0x00($23)    	 # Delay slot
58347		 j     MainExit
58348	3:
58349		 sll   $7,$24,2         	 # Delay slot
58350		 addu  $7,$7,$30
58351		 lw    $7,0x00($7)
58352		 jr    $7
58353		 nop                    	 # Delay slot
58354
58355OP0_4070:				#:
58356		 addiu $23,$23,2
58357
58358		 andi  $24,$24,0x07
58359		 sll   $24,$24,2
58360		 addu  $24,$24,$21
58361		 lw    $14,0x20($24)
58362		 lhu   $7,0x00($23)
58363		 addiu $23,$23,2
58364		 seb   $6,$7
58365		 or    $25,$0,$7
58366		 srl   $7,$7,12
58367		 andi  $25,$25,0x0800
58368		 sll   $7,$7,2
58369		 addu  $7,$7,$21
58370		 bne   $25,$0,0f
58371		 lw    $25,0x00($7)      	 # Delay slot
58372		 seh   $25,$25
58373	0:
58374		 addu  $25,$14,$25
58375		 addu  $14,$25,$6
58376		 lw    $25,0x80($21)
58377		 sw    $15,m68k_ICount
58378		 sw    $14,0x44($29)
58379		 or    $4,$0,$14
58380		 jalr  $25
58381		 sw    $23,0x4C($21)    	 # Delay slot
58382		 lw    $14,0x44($29)
58383		 lw    $15,m68k_ICount
58384		 seh   $8,$2
58385		 addu  $2,$8,$20
58386		 subu  $2,$0,$2
58387		 addu  $25,$8,$20
58388		 sltu  $16,$0,$25       	 # Set Carry
58389		 xor   $17,$0,$8
58390		 xor   $25,$2,$0
58391		 and   $17,$17,$25
58392		 srl   $17,$17,15
58393		 andi  $17,$17,0x01     	 # Set Overflow
58394		 seh  $25,$2
58395		 slt   $19,$25,$0        	 # Set Sign
58396		 sltiu $25,$25,1
58397		 and   $18,$18,$25      	 # Set Zero
58398		 or    $20,$0,$16      	 # Copy Carry to X
58399		 lw    $25,0x8C($21)
58400		 sw    $15,m68k_ICount
58401		 or    $5,$0,$2
58402		 or    $4,$0,$14
58403		 jalr  $25
58404		 sw    $23,0x4C($21)    	 # Delay slot
58405		 lw    $15,m68k_ICount
58406		 addiu $15,$15,-14
58407		 bgez  $15,3f
58408		 lhu   $24,0x00($23)    	 # Delay slot
58409		 j     MainExit
58410	3:
58411		 sll   $7,$24,2         	 # Delay slot
58412		 addu  $7,$7,$30
58413		 lw    $7,0x00($7)
58414		 jr    $7
58415		 nop                    	 # Delay slot
58416
58417OP0_4078:				#:
58418		 addiu $23,$23,2
58419
58420		 lh    $14,0x00($23)
58421		 addiu $23,$23,2
58422		 lw    $25,0x80($21)
58423		 sw    $15,m68k_ICount
58424		 sw    $14,0x44($29)
58425		 or    $4,$0,$14
58426		 jalr  $25
58427		 sw    $23,0x4C($21)    	 # Delay slot
58428		 lw    $14,0x44($29)
58429		 lw    $15,m68k_ICount
58430		 seh   $8,$2
58431		 addu  $2,$8,$20
58432		 subu  $2,$0,$2
58433		 addu  $25,$8,$20
58434		 sltu  $16,$0,$25       	 # Set Carry
58435		 xor   $17,$0,$8
58436		 xor   $25,$2,$0
58437		 and   $17,$17,$25
58438		 srl   $17,$17,15
58439		 andi  $17,$17,0x01     	 # Set Overflow
58440		 seh  $25,$2
58441		 slt   $19,$25,$0        	 # Set Sign
58442		 sltiu $25,$25,1
58443		 and   $18,$18,$25      	 # Set Zero
58444		 or    $20,$0,$16      	 # Copy Carry to X
58445		 lw    $25,0x8C($21)
58446		 sw    $15,m68k_ICount
58447		 or    $5,$0,$2
58448		 or    $4,$0,$14
58449		 jalr  $25
58450		 sw    $23,0x4C($21)    	 # Delay slot
58451		 lw    $15,m68k_ICount
58452		 addiu $15,$15,-12
58453		 bgez  $15,3f
58454		 lhu   $24,0x00($23)    	 # Delay slot
58455		 j     MainExit
58456	3:
58457		 sll   $7,$24,2         	 # Delay slot
58458		 addu  $7,$7,$30
58459		 lw    $7,0x00($7)
58460		 jr    $7
58461		 nop                    	 # Delay slot
58462
58463OP0_4079:				#:
58464		 addiu $23,$23,2
58465
58466		 lhu   $14,0x00($23)
58467		 lhu   $25,0x02($23)
58468		 sll   $14,$14,16
58469		 or    $14,$14,$25
58470		 addiu $23,$23,4
58471		 lw    $25,0x80($21)
58472		 sw    $15,m68k_ICount
58473		 sw    $14,0x44($29)
58474		 or    $4,$0,$14
58475		 jalr  $25
58476		 sw    $23,0x4C($21)    	 # Delay slot
58477		 lw    $14,0x44($29)
58478		 lw    $15,m68k_ICount
58479		 seh   $8,$2
58480		 addu  $2,$8,$20
58481		 subu  $2,$0,$2
58482		 addu  $25,$8,$20
58483		 sltu  $16,$0,$25       	 # Set Carry
58484		 xor   $17,$0,$8
58485		 xor   $25,$2,$0
58486		 and   $17,$17,$25
58487		 srl   $17,$17,15
58488		 andi  $17,$17,0x01     	 # Set Overflow
58489		 seh  $25,$2
58490		 slt   $19,$25,$0        	 # Set Sign
58491		 sltiu $25,$25,1
58492		 and   $18,$18,$25      	 # Set Zero
58493		 or    $20,$0,$16      	 # Copy Carry to X
58494		 lw    $25,0x8C($21)
58495		 sw    $15,m68k_ICount
58496		 or    $5,$0,$2
58497		 or    $4,$0,$14
58498		 jalr  $25
58499		 sw    $23,0x4C($21)    	 # Delay slot
58500		 lw    $15,m68k_ICount
58501		 addiu $15,$15,-16
58502		 bgez  $15,3f
58503		 lhu   $24,0x00($23)    	 # Delay slot
58504		 j     MainExit
58505	3:
58506		 sll   $7,$24,2         	 # Delay slot
58507		 addu  $7,$7,$30
58508		 lw    $7,0x00($7)
58509		 jr    $7
58510		 nop                    	 # Delay slot
58511
58512OP0_4080:				#:
58513		 addiu $23,$23,2
58514
58515		 andi  $24,$24,0x07
58516		 sll   $24,$24,2
58517		 addu  $24,$24,$21
58518		 lw    $8,0x00($24)
58519		 addu  $2,$8,$20
58520		 subu  $2,$0,$2
58521		 addu  $25,$8,$20
58522		 sltu  $16,$0,$25       	 # Set Carry
58523		 xor   $17,$0,$8
58524		 xor   $25,$2,$0
58525		 and   $17,$17,$25
58526		 srl   $17,$17,31        	 # Set Overflow
58527		 slt   $19,$2,$0        	 # Set Sign
58528		 sltiu $25,$2,1
58529		 and   $18,$18,$25      	 # Set Zero
58530		 or    $20,$0,$16      	 # Copy Carry to X
58531		 sw    $2,0x00($24)
58532		 addiu $15,$15,-6
58533		 bgez  $15,3f
58534		 lhu   $24,0x00($23)    	 # Delay slot
58535		 j     MainExit
58536	3:
58537		 sll   $7,$24,2         	 # Delay slot
58538		 addu  $7,$7,$30
58539		 lw    $7,0x00($7)
58540		 jr    $7
58541		 nop                    	 # Delay slot
58542
58543OP0_4090:				#:
58544		 addiu $23,$23,2
58545
58546		 andi  $24,$24,0x07
58547		 sll   $24,$24,2
58548		 addu  $24,$24,$21
58549		 lw    $14,0x20($24)
58550		 lw    $25,0x84($21)
58551		 sw    $15,m68k_ICount
58552		 sw    $14,0x44($29)
58553		 or    $4,$0,$14
58554		 jalr  $25
58555		 sw    $23,0x4C($21)    	 # Delay slot
58556		 lw    $14,0x44($29)
58557		 lw    $15,m68k_ICount
58558		 or    $8,$0,$2
58559		 addu  $2,$8,$20
58560		 subu  $2,$0,$2
58561		 addu  $25,$8,$20
58562		 sltu  $16,$0,$25       	 # Set Carry
58563		 xor   $17,$0,$8
58564		 xor   $25,$2,$0
58565		 and   $17,$17,$25
58566		 srl   $17,$17,31        	 # Set Overflow
58567		 slt   $19,$2,$0        	 # Set Sign
58568		 sltiu $25,$2,1
58569		 and   $18,$18,$25      	 # Set Zero
58570		 or    $20,$0,$16      	 # Copy Carry to X
58571		 lw    $25,0x90($21)
58572		 sw    $15,m68k_ICount
58573		 or    $5,$0,$2
58574		 or    $4,$0,$14
58575		 jalr  $25
58576		 sw    $23,0x4C($21)    	 # Delay slot
58577		 lw    $15,m68k_ICount
58578		 addiu $15,$15,-14
58579		 bgez  $15,3f
58580		 lhu   $24,0x00($23)    	 # Delay slot
58581		 j     MainExit
58582	3:
58583		 sll   $7,$24,2         	 # Delay slot
58584		 addu  $7,$7,$30
58585		 lw    $7,0x00($7)
58586		 jr    $7
58587		 nop                    	 # Delay slot
58588
58589OP0_4098:				#:
58590		 addiu $23,$23,2
58591
58592		 andi  $24,$24,0x07
58593		 sll   $24,$24,2
58594		 addu  $24,$24,$21
58595		 lw    $14,0x20($24)
58596		 addiu $25,$14,4
58597		 sw    $25,0x20($24)
58598		 lw    $25,0x84($21)
58599		 sw    $15,m68k_ICount
58600		 sw    $14,0x44($29)
58601		 or    $4,$0,$14
58602		 jalr  $25
58603		 sw    $23,0x4C($21)    	 # Delay slot
58604		 lw    $14,0x44($29)
58605		 lw    $15,m68k_ICount
58606		 or    $8,$0,$2
58607		 addu  $2,$8,$20
58608		 subu  $2,$0,$2
58609		 addu  $25,$8,$20
58610		 sltu  $16,$0,$25       	 # Set Carry
58611		 xor   $17,$0,$8
58612		 xor   $25,$2,$0
58613		 and   $17,$17,$25
58614		 srl   $17,$17,31        	 # Set Overflow
58615		 slt   $19,$2,$0        	 # Set Sign
58616		 sltiu $25,$2,1
58617		 and   $18,$18,$25      	 # Set Zero
58618		 or    $20,$0,$16      	 # Copy Carry to X
58619		 lw    $25,0x90($21)
58620		 sw    $15,m68k_ICount
58621		 or    $5,$0,$2
58622		 or    $4,$0,$14
58623		 jalr  $25
58624		 sw    $23,0x4C($21)    	 # Delay slot
58625		 lw    $15,m68k_ICount
58626		 addiu $15,$15,-14
58627		 bgez  $15,3f
58628		 lhu   $24,0x00($23)    	 # Delay slot
58629		 j     MainExit
58630	3:
58631		 sll   $7,$24,2         	 # Delay slot
58632		 addu  $7,$7,$30
58633		 lw    $7,0x00($7)
58634		 jr    $7
58635		 nop                    	 # Delay slot
58636
58637OP0_40a0:				#:
58638		 addiu $23,$23,2
58639
58640		 andi  $24,$24,0x07
58641		 sll   $24,$24,2
58642		 addu  $24,$24,$21
58643		 lw    $14,0x20($24)
58644		 addiu $14,$14,-4
58645		 sw    $14,0x20($24)
58646		 lw    $25,0x84($21)
58647		 sw    $15,m68k_ICount
58648		 sw    $14,0x44($29)
58649		 or    $4,$0,$14
58650		 jalr  $25
58651		 sw    $23,0x4C($21)    	 # Delay slot
58652		 lw    $14,0x44($29)
58653		 lw    $15,m68k_ICount
58654		 or    $8,$0,$2
58655		 addu  $2,$8,$20
58656		 subu  $2,$0,$2
58657		 addu  $25,$8,$20
58658		 sltu  $16,$0,$25       	 # Set Carry
58659		 xor   $17,$0,$8
58660		 xor   $25,$2,$0
58661		 and   $17,$17,$25
58662		 srl   $17,$17,31        	 # Set Overflow
58663		 slt   $19,$2,$0        	 # Set Sign
58664		 sltiu $25,$2,1
58665		 and   $18,$18,$25      	 # Set Zero
58666		 or    $20,$0,$16      	 # Copy Carry to X
58667		 lw    $25,0x90($21)
58668		 sw    $15,m68k_ICount
58669		 or    $5,$0,$2
58670		 or    $4,$0,$14
58671		 jalr  $25
58672		 sw    $23,0x4C($21)    	 # Delay slot
58673		 lw    $15,m68k_ICount
58674		 addiu $15,$15,-16
58675		 bgez  $15,3f
58676		 lhu   $24,0x00($23)    	 # Delay slot
58677		 j     MainExit
58678	3:
58679		 sll   $7,$24,2         	 # Delay slot
58680		 addu  $7,$7,$30
58681		 lw    $7,0x00($7)
58682		 jr    $7
58683		 nop                    	 # Delay slot
58684
58685OP0_40a8:				#:
58686		 addiu $23,$23,2
58687
58688		 andi  $24,$24,0x07
58689		 lh    $7,0x00($23)
58690		 sll   $24,$24,2
58691		 addu  $24,$24,$21
58692		 lw    $14,0x20($24)
58693		 addiu $23,$23,2
58694		 addu  $14,$14,$7
58695		 lw    $25,0x84($21)
58696		 sw    $15,m68k_ICount
58697		 sw    $14,0x44($29)
58698		 or    $4,$0,$14
58699		 jalr  $25
58700		 sw    $23,0x4C($21)    	 # Delay slot
58701		 lw    $14,0x44($29)
58702		 lw    $15,m68k_ICount
58703		 or    $8,$0,$2
58704		 addu  $2,$8,$20
58705		 subu  $2,$0,$2
58706		 addu  $25,$8,$20
58707		 sltu  $16,$0,$25       	 # Set Carry
58708		 xor   $17,$0,$8
58709		 xor   $25,$2,$0
58710		 and   $17,$17,$25
58711		 srl   $17,$17,31        	 # Set Overflow
58712		 slt   $19,$2,$0        	 # Set Sign
58713		 sltiu $25,$2,1
58714		 and   $18,$18,$25      	 # Set Zero
58715		 or    $20,$0,$16      	 # Copy Carry to X
58716		 lw    $25,0x90($21)
58717		 sw    $15,m68k_ICount
58718		 or    $5,$0,$2
58719		 or    $4,$0,$14
58720		 jalr  $25
58721		 sw    $23,0x4C($21)    	 # Delay slot
58722		 lw    $15,m68k_ICount
58723		 addiu $15,$15,-18
58724		 bgez  $15,3f
58725		 lhu   $24,0x00($23)    	 # Delay slot
58726		 j     MainExit
58727	3:
58728		 sll   $7,$24,2         	 # Delay slot
58729		 addu  $7,$7,$30
58730		 lw    $7,0x00($7)
58731		 jr    $7
58732		 nop                    	 # Delay slot
58733
58734OP0_40b0:				#:
58735		 addiu $23,$23,2
58736
58737		 andi  $24,$24,0x07
58738		 sll   $24,$24,2
58739		 addu  $24,$24,$21
58740		 lw    $14,0x20($24)
58741		 lhu   $7,0x00($23)
58742		 addiu $23,$23,2
58743		 seb   $6,$7
58744		 or    $25,$0,$7
58745		 srl   $7,$7,12
58746		 andi  $25,$25,0x0800
58747		 sll   $7,$7,2
58748		 addu  $7,$7,$21
58749		 bne   $25,$0,0f
58750		 lw    $25,0x00($7)      	 # Delay slot
58751		 seh   $25,$25
58752	0:
58753		 addu  $25,$14,$25
58754		 addu  $14,$25,$6
58755		 lw    $25,0x84($21)
58756		 sw    $15,m68k_ICount
58757		 sw    $14,0x44($29)
58758		 or    $4,$0,$14
58759		 jalr  $25
58760		 sw    $23,0x4C($21)    	 # Delay slot
58761		 lw    $14,0x44($29)
58762		 lw    $15,m68k_ICount
58763		 or    $8,$0,$2
58764		 addu  $2,$8,$20
58765		 subu  $2,$0,$2
58766		 addu  $25,$8,$20
58767		 sltu  $16,$0,$25       	 # Set Carry
58768		 xor   $17,$0,$8
58769		 xor   $25,$2,$0
58770		 and   $17,$17,$25
58771		 srl   $17,$17,31        	 # Set Overflow
58772		 slt   $19,$2,$0        	 # Set Sign
58773		 sltiu $25,$2,1
58774		 and   $18,$18,$25      	 # Set Zero
58775		 or    $20,$0,$16      	 # Copy Carry to X
58776		 lw    $25,0x90($21)
58777		 sw    $15,m68k_ICount
58778		 or    $5,$0,$2
58779		 or    $4,$0,$14
58780		 jalr  $25
58781		 sw    $23,0x4C($21)    	 # Delay slot
58782		 lw    $15,m68k_ICount
58783		 addiu $15,$15,-20
58784		 bgez  $15,3f
58785		 lhu   $24,0x00($23)    	 # Delay slot
58786		 j     MainExit
58787	3:
58788		 sll   $7,$24,2         	 # Delay slot
58789		 addu  $7,$7,$30
58790		 lw    $7,0x00($7)
58791		 jr    $7
58792		 nop                    	 # Delay slot
58793
58794OP0_40b8:				#:
58795		 addiu $23,$23,2
58796
58797		 lh    $14,0x00($23)
58798		 addiu $23,$23,2
58799		 lw    $25,0x84($21)
58800		 sw    $15,m68k_ICount
58801		 sw    $14,0x44($29)
58802		 or    $4,$0,$14
58803		 jalr  $25
58804		 sw    $23,0x4C($21)    	 # Delay slot
58805		 lw    $14,0x44($29)
58806		 lw    $15,m68k_ICount
58807		 or    $8,$0,$2
58808		 addu  $2,$8,$20
58809		 subu  $2,$0,$2
58810		 addu  $25,$8,$20
58811		 sltu  $16,$0,$25       	 # Set Carry
58812		 xor   $17,$0,$8
58813		 xor   $25,$2,$0
58814		 and   $17,$17,$25
58815		 srl   $17,$17,31        	 # Set Overflow
58816		 slt   $19,$2,$0        	 # Set Sign
58817		 sltiu $25,$2,1
58818		 and   $18,$18,$25      	 # Set Zero
58819		 or    $20,$0,$16      	 # Copy Carry to X
58820		 lw    $25,0x90($21)
58821		 sw    $15,m68k_ICount
58822		 or    $5,$0,$2
58823		 or    $4,$0,$14
58824		 jalr  $25
58825		 sw    $23,0x4C($21)    	 # Delay slot
58826		 lw    $15,m68k_ICount
58827		 addiu $15,$15,-18
58828		 bgez  $15,3f
58829		 lhu   $24,0x00($23)    	 # Delay slot
58830		 j     MainExit
58831	3:
58832		 sll   $7,$24,2         	 # Delay slot
58833		 addu  $7,$7,$30
58834		 lw    $7,0x00($7)
58835		 jr    $7
58836		 nop                    	 # Delay slot
58837
58838OP0_40b9:				#:
58839		 addiu $23,$23,2
58840
58841		 lhu   $14,0x00($23)
58842		 lhu   $25,0x02($23)
58843		 sll   $14,$14,16
58844		 or    $14,$14,$25
58845		 addiu $23,$23,4
58846		 lw    $25,0x84($21)
58847		 sw    $15,m68k_ICount
58848		 sw    $14,0x44($29)
58849		 or    $4,$0,$14
58850		 jalr  $25
58851		 sw    $23,0x4C($21)    	 # Delay slot
58852		 lw    $14,0x44($29)
58853		 lw    $15,m68k_ICount
58854		 or    $8,$0,$2
58855		 addu  $2,$8,$20
58856		 subu  $2,$0,$2
58857		 addu  $25,$8,$20
58858		 sltu  $16,$0,$25       	 # Set Carry
58859		 xor   $17,$0,$8
58860		 xor   $25,$2,$0
58861		 and   $17,$17,$25
58862		 srl   $17,$17,31        	 # Set Overflow
58863		 slt   $19,$2,$0        	 # Set Sign
58864		 sltiu $25,$2,1
58865		 and   $18,$18,$25      	 # Set Zero
58866		 or    $20,$0,$16      	 # Copy Carry to X
58867		 lw    $25,0x90($21)
58868		 sw    $15,m68k_ICount
58869		 or    $5,$0,$2
58870		 or    $4,$0,$14
58871		 jalr  $25
58872		 sw    $23,0x4C($21)    	 # Delay slot
58873		 lw    $15,m68k_ICount
58874		 addiu $15,$15,-22
58875		 bgez  $15,3f
58876		 lhu   $24,0x00($23)    	 # Delay slot
58877		 j     MainExit
58878	3:
58879		 sll   $7,$24,2         	 # Delay slot
58880		 addu  $7,$7,$30
58881		 lw    $7,0x00($7)
58882		 jr    $7
58883		 nop                    	 # Delay slot
58884
58885OP0_4200:				#:
58886		 addiu $23,$23,2
58887
58888		 andi  $24,$24,0x07
58889		 and   $2,$0,$0
58890		 sll   $24,$24,2
58891		 addu  $24,$24,$21
58892		 sb    $2,0x00($24)
58893		 and   $16,$0,$0
58894		 and   $17,$0,$0
58895		 ori   $18,$0,1
58896		 and   $19,$0,$0
58897		 addiu $15,$15,-4
58898		 bgez  $15,3f
58899		 lhu   $24,0x00($23)    	 # Delay slot
58900		 j     MainExit
58901	3:
58902		 sll   $7,$24,2         	 # Delay slot
58903		 addu  $7,$7,$30
58904		 lw    $7,0x00($7)
58905		 jr    $7
58906		 nop                    	 # Delay slot
58907
58908OP0_4210:				#:
58909		 addiu $23,$23,2
58910
58911		 andi  $24,$24,0x07
58912		 and   $2,$0,$0
58913		 sll   $24,$24,2
58914		 addu  $24,$24,$21
58915		 lw    $14,0x20($24)
58916		 lw    $25,0x88($21)
58917		 sw    $15,m68k_ICount
58918		 or    $5,$0,$2
58919		 or    $4,$0,$14
58920		 jalr  $25
58921		 sw    $23,0x4C($21)    	 # Delay slot
58922		 lw    $15,m68k_ICount
58923		 and   $16,$0,$0
58924		 and   $17,$0,$0
58925		 ori   $18,$0,1
58926		 and   $19,$0,$0
58927		 addiu $15,$15,-8
58928		 bgez  $15,3f
58929		 lhu   $24,0x00($23)    	 # Delay slot
58930		 j     MainExit
58931	3:
58932		 sll   $7,$24,2         	 # Delay slot
58933		 addu  $7,$7,$30
58934		 lw    $7,0x00($7)
58935		 jr    $7
58936		 nop                    	 # Delay slot
58937
58938OP0_4218:				#:
58939		 addiu $23,$23,2
58940
58941		 andi  $24,$24,0x07
58942		 and   $2,$0,$0
58943		 sll   $24,$24,2
58944		 addu  $24,$24,$21
58945		 lw    $14,0x20($24)
58946		 addiu $25,$14,1
58947		 sw    $25,0x20($24)
58948		 lw    $25,0x88($21)
58949		 sw    $15,m68k_ICount
58950		 or    $5,$0,$2
58951		 or    $4,$0,$14
58952		 jalr  $25
58953		 sw    $23,0x4C($21)    	 # Delay slot
58954		 lw    $15,m68k_ICount
58955		 and   $16,$0,$0
58956		 and   $17,$0,$0
58957		 ori   $18,$0,1
58958		 and   $19,$0,$0
58959		 addiu $15,$15,-8
58960		 bgez  $15,3f
58961		 lhu   $24,0x00($23)    	 # Delay slot
58962		 j     MainExit
58963	3:
58964		 sll   $7,$24,2         	 # Delay slot
58965		 addu  $7,$7,$30
58966		 lw    $7,0x00($7)
58967		 jr    $7
58968		 nop                    	 # Delay slot
58969
58970OP0_421f:				#:
58971		 addiu $23,$23,2
58972
58973		 and   $2,$0,$0
58974		 lw    $14,0x3C($21)    	 # Get A7
58975		 addiu $25,$14,2
58976		 sw    $25,0x3C($21)
58977		 lw    $25,0x88($21)
58978		 sw    $15,m68k_ICount
58979		 or    $5,$0,$2
58980		 or    $4,$0,$14
58981		 jalr  $25
58982		 sw    $23,0x4C($21)    	 # Delay slot
58983		 lw    $15,m68k_ICount
58984		 and   $16,$0,$0
58985		 and   $17,$0,$0
58986		 ori   $18,$0,1
58987		 and   $19,$0,$0
58988		 addiu $15,$15,-8
58989		 bgez  $15,3f
58990		 lhu   $24,0x00($23)    	 # Delay slot
58991		 j     MainExit
58992	3:
58993		 sll   $7,$24,2         	 # Delay slot
58994		 addu  $7,$7,$30
58995		 lw    $7,0x00($7)
58996		 jr    $7
58997		 nop                    	 # Delay slot
58998
58999OP0_4220:				#:
59000		 addiu $23,$23,2
59001
59002		 andi  $24,$24,0x07
59003		 and   $2,$0,$0
59004		 sll   $24,$24,2
59005		 addu  $24,$24,$21
59006		 lw    $14,0x20($24)
59007		 addiu $14,$14,-1
59008		 sw    $14,0x20($24)
59009		 lw    $25,0x88($21)
59010		 sw    $15,m68k_ICount
59011		 or    $5,$0,$2
59012		 or    $4,$0,$14
59013		 jalr  $25
59014		 sw    $23,0x4C($21)    	 # Delay slot
59015		 lw    $15,m68k_ICount
59016		 and   $16,$0,$0
59017		 and   $17,$0,$0
59018		 ori   $18,$0,1
59019		 and   $19,$0,$0
59020		 addiu $15,$15,-10
59021		 bgez  $15,3f
59022		 lhu   $24,0x00($23)    	 # Delay slot
59023		 j     MainExit
59024	3:
59025		 sll   $7,$24,2         	 # Delay slot
59026		 addu  $7,$7,$30
59027		 lw    $7,0x00($7)
59028		 jr    $7
59029		 nop                    	 # Delay slot
59030
59031OP0_4227:				#:
59032		 addiu $23,$23,2
59033
59034		 and   $2,$0,$0
59035		 lw    $14,0x3C($21)    	 # Get A7
59036		 addiu $14,$14,-2
59037		 sw    $14,0x3C($21)
59038		 lw    $25,0x88($21)
59039		 sw    $15,m68k_ICount
59040		 or    $5,$0,$2
59041		 or    $4,$0,$14
59042		 jalr  $25
59043		 sw    $23,0x4C($21)    	 # Delay slot
59044		 lw    $15,m68k_ICount
59045		 and   $16,$0,$0
59046		 and   $17,$0,$0
59047		 ori   $18,$0,1
59048		 and   $19,$0,$0
59049		 addiu $15,$15,-10
59050		 bgez  $15,3f
59051		 lhu   $24,0x00($23)    	 # Delay slot
59052		 j     MainExit
59053	3:
59054		 sll   $7,$24,2         	 # Delay slot
59055		 addu  $7,$7,$30
59056		 lw    $7,0x00($7)
59057		 jr    $7
59058		 nop                    	 # Delay slot
59059
59060OP0_4228:				#:
59061		 addiu $23,$23,2
59062
59063		 andi  $24,$24,0x07
59064		 and   $2,$0,$0
59065		 lh    $7,0x00($23)
59066		 sll   $24,$24,2
59067		 addu  $24,$24,$21
59068		 lw    $14,0x20($24)
59069		 addiu $23,$23,2
59070		 addu  $14,$14,$7
59071		 lw    $25,0x88($21)
59072		 sw    $15,m68k_ICount
59073		 or    $5,$0,$2
59074		 or    $4,$0,$14
59075		 jalr  $25
59076		 sw    $23,0x4C($21)    	 # Delay slot
59077		 lw    $15,m68k_ICount
59078		 and   $16,$0,$0
59079		 and   $17,$0,$0
59080		 ori   $18,$0,1
59081		 and   $19,$0,$0
59082		 addiu $15,$15,-12
59083		 bgez  $15,3f
59084		 lhu   $24,0x00($23)    	 # Delay slot
59085		 j     MainExit
59086	3:
59087		 sll   $7,$24,2         	 # Delay slot
59088		 addu  $7,$7,$30
59089		 lw    $7,0x00($7)
59090		 jr    $7
59091		 nop                    	 # Delay slot
59092
59093OP0_4230:				#:
59094		 addiu $23,$23,2
59095
59096		 andi  $24,$24,0x07
59097		 and   $2,$0,$0
59098		 sll   $24,$24,2
59099		 addu  $24,$24,$21
59100		 lw    $14,0x20($24)
59101		 lhu   $7,0x00($23)
59102		 addiu $23,$23,2
59103		 seb   $6,$7
59104		 or    $25,$0,$7
59105		 srl   $7,$7,12
59106		 andi  $25,$25,0x0800
59107		 sll   $7,$7,2
59108		 addu  $7,$7,$21
59109		 bne   $25,$0,0f
59110		 lw    $25,0x00($7)      	 # Delay slot
59111		 seh   $25,$25
59112	0:
59113		 addu  $25,$14,$25
59114		 addu  $14,$25,$6
59115		 lw    $25,0x88($21)
59116		 sw    $15,m68k_ICount
59117		 or    $5,$0,$2
59118		 or    $4,$0,$14
59119		 jalr  $25
59120		 sw    $23,0x4C($21)    	 # Delay slot
59121		 lw    $15,m68k_ICount
59122		 and   $16,$0,$0
59123		 and   $17,$0,$0
59124		 ori   $18,$0,1
59125		 and   $19,$0,$0
59126		 addiu $15,$15,-14
59127		 bgez  $15,3f
59128		 lhu   $24,0x00($23)    	 # Delay slot
59129		 j     MainExit
59130	3:
59131		 sll   $7,$24,2         	 # Delay slot
59132		 addu  $7,$7,$30
59133		 lw    $7,0x00($7)
59134		 jr    $7
59135		 nop                    	 # Delay slot
59136
59137OP0_4238:				#:
59138		 addiu $23,$23,2
59139
59140		 and   $2,$0,$0
59141		 lh    $14,0x00($23)
59142		 addiu $23,$23,2
59143		 lw    $25,0x88($21)
59144		 sw    $15,m68k_ICount
59145		 or    $5,$0,$2
59146		 or    $4,$0,$14
59147		 jalr  $25
59148		 sw    $23,0x4C($21)    	 # Delay slot
59149		 lw    $15,m68k_ICount
59150		 and   $16,$0,$0
59151		 and   $17,$0,$0
59152		 ori   $18,$0,1
59153		 and   $19,$0,$0
59154		 addiu $15,$15,-12
59155		 bgez  $15,3f
59156		 lhu   $24,0x00($23)    	 # Delay slot
59157		 j     MainExit
59158	3:
59159		 sll   $7,$24,2         	 # Delay slot
59160		 addu  $7,$7,$30
59161		 lw    $7,0x00($7)
59162		 jr    $7
59163		 nop                    	 # Delay slot
59164
59165OP0_4239:				#:
59166		 addiu $23,$23,2
59167
59168		 and   $2,$0,$0
59169		 lhu   $14,0x00($23)
59170		 lhu   $25,0x02($23)
59171		 sll   $14,$14,16
59172		 or    $14,$14,$25
59173		 addiu $23,$23,4
59174		 lw    $25,0x88($21)
59175		 sw    $15,m68k_ICount
59176		 or    $5,$0,$2
59177		 or    $4,$0,$14
59178		 jalr  $25
59179		 sw    $23,0x4C($21)    	 # Delay slot
59180		 lw    $15,m68k_ICount
59181		 and   $16,$0,$0
59182		 and   $17,$0,$0
59183		 ori   $18,$0,1
59184		 and   $19,$0,$0
59185		 addiu $15,$15,-16
59186		 bgez  $15,3f
59187		 lhu   $24,0x00($23)    	 # Delay slot
59188		 j     MainExit
59189	3:
59190		 sll   $7,$24,2         	 # Delay slot
59191		 addu  $7,$7,$30
59192		 lw    $7,0x00($7)
59193		 jr    $7
59194		 nop                    	 # Delay slot
59195
59196OP0_4240:				#:
59197		 addiu $23,$23,2
59198
59199		 andi  $24,$24,0x07
59200		 and   $2,$0,$0
59201		 sll   $24,$24,2
59202		 addu  $24,$24,$21
59203		 sh    $2,0x00($24)
59204		 and   $16,$0,$0
59205		 and   $17,$0,$0
59206		 ori   $18,$0,1
59207		 and   $19,$0,$0
59208		 addiu $15,$15,-4
59209		 bgez  $15,3f
59210		 lhu   $24,0x00($23)    	 # Delay slot
59211		 j     MainExit
59212	3:
59213		 sll   $7,$24,2         	 # Delay slot
59214		 addu  $7,$7,$30
59215		 lw    $7,0x00($7)
59216		 jr    $7
59217		 nop                    	 # Delay slot
59218
59219OP0_4250:				#:
59220		 addiu $23,$23,2
59221
59222		 andi  $24,$24,0x07
59223		 and   $2,$0,$0
59224		 sll   $24,$24,2
59225		 addu  $24,$24,$21
59226		 lw    $14,0x20($24)
59227		 lw    $25,0x8C($21)
59228		 sw    $15,m68k_ICount
59229		 or    $5,$0,$2
59230		 or    $4,$0,$14
59231		 jalr  $25
59232		 sw    $23,0x4C($21)    	 # Delay slot
59233		 lw    $15,m68k_ICount
59234		 and   $16,$0,$0
59235		 and   $17,$0,$0
59236		 ori   $18,$0,1
59237		 and   $19,$0,$0
59238		 addiu $15,$15,-8
59239		 bgez  $15,3f
59240		 lhu   $24,0x00($23)    	 # Delay slot
59241		 j     MainExit
59242	3:
59243		 sll   $7,$24,2         	 # Delay slot
59244		 addu  $7,$7,$30
59245		 lw    $7,0x00($7)
59246		 jr    $7
59247		 nop                    	 # Delay slot
59248
59249OP0_4258:				#:
59250		 addiu $23,$23,2
59251
59252		 andi  $24,$24,0x07
59253		 and   $2,$0,$0
59254		 sll   $24,$24,2
59255		 addu  $24,$24,$21
59256		 lw    $14,0x20($24)
59257		 addiu $25,$14,2
59258		 sw    $25,0x20($24)
59259		 lw    $25,0x8C($21)
59260		 sw    $15,m68k_ICount
59261		 or    $5,$0,$2
59262		 or    $4,$0,$14
59263		 jalr  $25
59264		 sw    $23,0x4C($21)    	 # Delay slot
59265		 lw    $15,m68k_ICount
59266		 and   $16,$0,$0
59267		 and   $17,$0,$0
59268		 ori   $18,$0,1
59269		 and   $19,$0,$0
59270		 addiu $15,$15,-8
59271		 bgez  $15,3f
59272		 lhu   $24,0x00($23)    	 # Delay slot
59273		 j     MainExit
59274	3:
59275		 sll   $7,$24,2         	 # Delay slot
59276		 addu  $7,$7,$30
59277		 lw    $7,0x00($7)
59278		 jr    $7
59279		 nop                    	 # Delay slot
59280
59281OP0_4260:				#:
59282		 addiu $23,$23,2
59283
59284		 andi  $24,$24,0x07
59285		 and   $2,$0,$0
59286		 sll   $24,$24,2
59287		 addu  $24,$24,$21
59288		 lw    $14,0x20($24)
59289		 addiu $14,$14,-2
59290		 sw    $14,0x20($24)
59291		 lw    $25,0x8C($21)
59292		 sw    $15,m68k_ICount
59293		 or    $5,$0,$2
59294		 or    $4,$0,$14
59295		 jalr  $25
59296		 sw    $23,0x4C($21)    	 # Delay slot
59297		 lw    $15,m68k_ICount
59298		 and   $16,$0,$0
59299		 and   $17,$0,$0
59300		 ori   $18,$0,1
59301		 and   $19,$0,$0
59302		 addiu $15,$15,-10
59303		 bgez  $15,3f
59304		 lhu   $24,0x00($23)    	 # Delay slot
59305		 j     MainExit
59306	3:
59307		 sll   $7,$24,2         	 # Delay slot
59308		 addu  $7,$7,$30
59309		 lw    $7,0x00($7)
59310		 jr    $7
59311		 nop                    	 # Delay slot
59312
59313OP0_4268:				#:
59314		 addiu $23,$23,2
59315
59316		 andi  $24,$24,0x07
59317		 and   $2,$0,$0
59318		 lh    $7,0x00($23)
59319		 sll   $24,$24,2
59320		 addu  $24,$24,$21
59321		 lw    $14,0x20($24)
59322		 addiu $23,$23,2
59323		 addu  $14,$14,$7
59324		 lw    $25,0x8C($21)
59325		 sw    $15,m68k_ICount
59326		 or    $5,$0,$2
59327		 or    $4,$0,$14
59328		 jalr  $25
59329		 sw    $23,0x4C($21)    	 # Delay slot
59330		 lw    $15,m68k_ICount
59331		 and   $16,$0,$0
59332		 and   $17,$0,$0
59333		 ori   $18,$0,1
59334		 and   $19,$0,$0
59335		 addiu $15,$15,-12
59336		 bgez  $15,3f
59337		 lhu   $24,0x00($23)    	 # Delay slot
59338		 j     MainExit
59339	3:
59340		 sll   $7,$24,2         	 # Delay slot
59341		 addu  $7,$7,$30
59342		 lw    $7,0x00($7)
59343		 jr    $7
59344		 nop                    	 # Delay slot
59345
59346OP0_4270:				#:
59347		 addiu $23,$23,2
59348
59349		 andi  $24,$24,0x07
59350		 and   $2,$0,$0
59351		 sll   $24,$24,2
59352		 addu  $24,$24,$21
59353		 lw    $14,0x20($24)
59354		 lhu   $7,0x00($23)
59355		 addiu $23,$23,2
59356		 seb   $6,$7
59357		 or    $25,$0,$7
59358		 srl   $7,$7,12
59359		 andi  $25,$25,0x0800
59360		 sll   $7,$7,2
59361		 addu  $7,$7,$21
59362		 bne   $25,$0,0f
59363		 lw    $25,0x00($7)      	 # Delay slot
59364		 seh   $25,$25
59365	0:
59366		 addu  $25,$14,$25
59367		 addu  $14,$25,$6
59368		 lw    $25,0x8C($21)
59369		 sw    $15,m68k_ICount
59370		 or    $5,$0,$2
59371		 or    $4,$0,$14
59372		 jalr  $25
59373		 sw    $23,0x4C($21)    	 # Delay slot
59374		 lw    $15,m68k_ICount
59375		 and   $16,$0,$0
59376		 and   $17,$0,$0
59377		 ori   $18,$0,1
59378		 and   $19,$0,$0
59379		 addiu $15,$15,-14
59380		 bgez  $15,3f
59381		 lhu   $24,0x00($23)    	 # Delay slot
59382		 j     MainExit
59383	3:
59384		 sll   $7,$24,2         	 # Delay slot
59385		 addu  $7,$7,$30
59386		 lw    $7,0x00($7)
59387		 jr    $7
59388		 nop                    	 # Delay slot
59389
59390OP0_4278:				#:
59391		 addiu $23,$23,2
59392
59393		 and   $2,$0,$0
59394		 lh    $14,0x00($23)
59395		 addiu $23,$23,2
59396		 lw    $25,0x8C($21)
59397		 sw    $15,m68k_ICount
59398		 or    $5,$0,$2
59399		 or    $4,$0,$14
59400		 jalr  $25
59401		 sw    $23,0x4C($21)    	 # Delay slot
59402		 lw    $15,m68k_ICount
59403		 and   $16,$0,$0
59404		 and   $17,$0,$0
59405		 ori   $18,$0,1
59406		 and   $19,$0,$0
59407		 addiu $15,$15,-12
59408		 bgez  $15,3f
59409		 lhu   $24,0x00($23)    	 # Delay slot
59410		 j     MainExit
59411	3:
59412		 sll   $7,$24,2         	 # Delay slot
59413		 addu  $7,$7,$30
59414		 lw    $7,0x00($7)
59415		 jr    $7
59416		 nop                    	 # Delay slot
59417
59418OP0_4279:				#:
59419		 addiu $23,$23,2
59420
59421		 and   $2,$0,$0
59422		 lhu   $14,0x00($23)
59423		 lhu   $25,0x02($23)
59424		 sll   $14,$14,16
59425		 or    $14,$14,$25
59426		 addiu $23,$23,4
59427		 lw    $25,0x8C($21)
59428		 sw    $15,m68k_ICount
59429		 or    $5,$0,$2
59430		 or    $4,$0,$14
59431		 jalr  $25
59432		 sw    $23,0x4C($21)    	 # Delay slot
59433		 lw    $15,m68k_ICount
59434		 and   $16,$0,$0
59435		 and   $17,$0,$0
59436		 ori   $18,$0,1
59437		 and   $19,$0,$0
59438		 addiu $15,$15,-16
59439		 bgez  $15,3f
59440		 lhu   $24,0x00($23)    	 # Delay slot
59441		 j     MainExit
59442	3:
59443		 sll   $7,$24,2         	 # Delay slot
59444		 addu  $7,$7,$30
59445		 lw    $7,0x00($7)
59446		 jr    $7
59447		 nop                    	 # Delay slot
59448
59449OP0_4280:				#:
59450		 addiu $23,$23,2
59451
59452		 andi  $24,$24,0x07
59453		 and   $2,$0,$0
59454		 sll   $24,$24,2
59455		 addu  $24,$24,$21
59456		 sw    $2,0x00($24)
59457		 and   $16,$0,$0
59458		 and   $17,$0,$0
59459		 ori   $18,$0,1
59460		 and   $19,$0,$0
59461		 addiu $15,$15,-6
59462		 bgez  $15,3f
59463		 lhu   $24,0x00($23)    	 # Delay slot
59464		 j     MainExit
59465	3:
59466		 sll   $7,$24,2         	 # Delay slot
59467		 addu  $7,$7,$30
59468		 lw    $7,0x00($7)
59469		 jr    $7
59470		 nop                    	 # Delay slot
59471
59472OP0_4290:				#:
59473		 addiu $23,$23,2
59474
59475		 andi  $24,$24,0x07
59476		 and   $2,$0,$0
59477		 sll   $24,$24,2
59478		 addu  $24,$24,$21
59479		 lw    $14,0x20($24)
59480		 lw    $25,0x90($21)
59481		 sw    $15,m68k_ICount
59482		 or    $5,$0,$2
59483		 or    $4,$0,$14
59484		 jalr  $25
59485		 sw    $23,0x4C($21)    	 # Delay slot
59486		 lw    $15,m68k_ICount
59487		 and   $16,$0,$0
59488		 and   $17,$0,$0
59489		 ori   $18,$0,1
59490		 and   $19,$0,$0
59491		 addiu $15,$15,-14
59492		 bgez  $15,3f
59493		 lhu   $24,0x00($23)    	 # Delay slot
59494		 j     MainExit
59495	3:
59496		 sll   $7,$24,2         	 # Delay slot
59497		 addu  $7,$7,$30
59498		 lw    $7,0x00($7)
59499		 jr    $7
59500		 nop                    	 # Delay slot
59501
59502OP0_4298:				#:
59503		 addiu $23,$23,2
59504
59505		 andi  $24,$24,0x07
59506		 and   $2,$0,$0
59507		 sll   $24,$24,2
59508		 addu  $24,$24,$21
59509		 lw    $14,0x20($24)
59510		 addiu $25,$14,4
59511		 sw    $25,0x20($24)
59512		 lw    $25,0x90($21)
59513		 sw    $15,m68k_ICount
59514		 or    $5,$0,$2
59515		 or    $4,$0,$14
59516		 jalr  $25
59517		 sw    $23,0x4C($21)    	 # Delay slot
59518		 lw    $15,m68k_ICount
59519		 and   $16,$0,$0
59520		 and   $17,$0,$0
59521		 ori   $18,$0,1
59522		 and   $19,$0,$0
59523		 addiu $15,$15,-14
59524		 bgez  $15,3f
59525		 lhu   $24,0x00($23)    	 # Delay slot
59526		 j     MainExit
59527	3:
59528		 sll   $7,$24,2         	 # Delay slot
59529		 addu  $7,$7,$30
59530		 lw    $7,0x00($7)
59531		 jr    $7
59532		 nop                    	 # Delay slot
59533
59534OP0_42a0:				#:
59535		 addiu $23,$23,2
59536
59537		 andi  $24,$24,0x07
59538		 and   $2,$0,$0
59539		 sll   $24,$24,2
59540		 addu  $24,$24,$21
59541		 lw    $14,0x20($24)
59542		 addiu $14,$14,-4
59543		 sw    $14,0x20($24)
59544		 lw    $25,0x90($21)
59545		 sw    $15,m68k_ICount
59546		 or    $5,$0,$2
59547		 or    $4,$0,$14
59548		 jalr  $25
59549		 sw    $23,0x4C($21)    	 # Delay slot
59550		 lw    $15,m68k_ICount
59551		 and   $16,$0,$0
59552		 and   $17,$0,$0
59553		 ori   $18,$0,1
59554		 and   $19,$0,$0
59555		 addiu $15,$15,-16
59556		 bgez  $15,3f
59557		 lhu   $24,0x00($23)    	 # Delay slot
59558		 j     MainExit
59559	3:
59560		 sll   $7,$24,2         	 # Delay slot
59561		 addu  $7,$7,$30
59562		 lw    $7,0x00($7)
59563		 jr    $7
59564		 nop                    	 # Delay slot
59565
59566OP0_42a8:				#:
59567		 addiu $23,$23,2
59568
59569		 andi  $24,$24,0x07
59570		 and   $2,$0,$0
59571		 lh    $7,0x00($23)
59572		 sll   $24,$24,2
59573		 addu  $24,$24,$21
59574		 lw    $14,0x20($24)
59575		 addiu $23,$23,2
59576		 addu  $14,$14,$7
59577		 lw    $25,0x90($21)
59578		 sw    $15,m68k_ICount
59579		 or    $5,$0,$2
59580		 or    $4,$0,$14
59581		 jalr  $25
59582		 sw    $23,0x4C($21)    	 # Delay slot
59583		 lw    $15,m68k_ICount
59584		 and   $16,$0,$0
59585		 and   $17,$0,$0
59586		 ori   $18,$0,1
59587		 and   $19,$0,$0
59588		 addiu $15,$15,-18
59589		 bgez  $15,3f
59590		 lhu   $24,0x00($23)    	 # Delay slot
59591		 j     MainExit
59592	3:
59593		 sll   $7,$24,2         	 # Delay slot
59594		 addu  $7,$7,$30
59595		 lw    $7,0x00($7)
59596		 jr    $7
59597		 nop                    	 # Delay slot
59598
59599OP0_42b0:				#:
59600		 addiu $23,$23,2
59601
59602		 andi  $24,$24,0x07
59603		 and   $2,$0,$0
59604		 sll   $24,$24,2
59605		 addu  $24,$24,$21
59606		 lw    $14,0x20($24)
59607		 lhu   $7,0x00($23)
59608		 addiu $23,$23,2
59609		 seb   $6,$7
59610		 or    $25,$0,$7
59611		 srl   $7,$7,12
59612		 andi  $25,$25,0x0800
59613		 sll   $7,$7,2
59614		 addu  $7,$7,$21
59615		 bne   $25,$0,0f
59616		 lw    $25,0x00($7)      	 # Delay slot
59617		 seh   $25,$25
59618	0:
59619		 addu  $25,$14,$25
59620		 addu  $14,$25,$6
59621		 lw    $25,0x90($21)
59622		 sw    $15,m68k_ICount
59623		 or    $5,$0,$2
59624		 or    $4,$0,$14
59625		 jalr  $25
59626		 sw    $23,0x4C($21)    	 # Delay slot
59627		 lw    $15,m68k_ICount
59628		 and   $16,$0,$0
59629		 and   $17,$0,$0
59630		 ori   $18,$0,1
59631		 and   $19,$0,$0
59632		 addiu $15,$15,-20
59633		 bgez  $15,3f
59634		 lhu   $24,0x00($23)    	 # Delay slot
59635		 j     MainExit
59636	3:
59637		 sll   $7,$24,2         	 # Delay slot
59638		 addu  $7,$7,$30
59639		 lw    $7,0x00($7)
59640		 jr    $7
59641		 nop                    	 # Delay slot
59642
59643OP0_42b8:				#:
59644		 addiu $23,$23,2
59645
59646		 and   $2,$0,$0
59647		 lh    $14,0x00($23)
59648		 addiu $23,$23,2
59649		 lw    $25,0x90($21)
59650		 sw    $15,m68k_ICount
59651		 or    $5,$0,$2
59652		 or    $4,$0,$14
59653		 jalr  $25
59654		 sw    $23,0x4C($21)    	 # Delay slot
59655		 lw    $15,m68k_ICount
59656		 and   $16,$0,$0
59657		 and   $17,$0,$0
59658		 ori   $18,$0,1
59659		 and   $19,$0,$0
59660		 addiu $15,$15,-18
59661		 bgez  $15,3f
59662		 lhu   $24,0x00($23)    	 # Delay slot
59663		 j     MainExit
59664	3:
59665		 sll   $7,$24,2         	 # Delay slot
59666		 addu  $7,$7,$30
59667		 lw    $7,0x00($7)
59668		 jr    $7
59669		 nop                    	 # Delay slot
59670
59671OP0_42b9:				#:
59672		 addiu $23,$23,2
59673
59674		 and   $2,$0,$0
59675		 lhu   $14,0x00($23)
59676		 lhu   $25,0x02($23)
59677		 sll   $14,$14,16
59678		 or    $14,$14,$25
59679		 addiu $23,$23,4
59680		 lw    $25,0x90($21)
59681		 sw    $15,m68k_ICount
59682		 or    $5,$0,$2
59683		 or    $4,$0,$14
59684		 jalr  $25
59685		 sw    $23,0x4C($21)    	 # Delay slot
59686		 lw    $15,m68k_ICount
59687		 and   $16,$0,$0
59688		 and   $17,$0,$0
59689		 ori   $18,$0,1
59690		 and   $19,$0,$0
59691		 addiu $15,$15,-22
59692		 bgez  $15,3f
59693		 lhu   $24,0x00($23)    	 # Delay slot
59694		 j     MainExit
59695	3:
59696		 sll   $7,$24,2         	 # Delay slot
59697		 addu  $7,$7,$30
59698		 lw    $7,0x00($7)
59699		 jr    $7
59700		 nop                    	 # Delay slot
59701
59702OP0_4400:				#:
59703		 addiu $23,$23,2
59704
59705		 andi  $24,$24,0x07
59706		 sll   $24,$24,2
59707		 addu  $24,$24,$21
59708		 lb    $8,0x00($24)
59709		 subu  $2,$0,$8
59710		 sltu  $16,$0,$8       	 # Set Carry
59711		 xor   $17,$0,$8
59712		 xor   $25,$2,$0
59713		 and   $17,$17,$25
59714		 srl   $17,$17,7
59715		 andi  $17,$17,0x01     	 # Set Overflow
59716		 seb  $25,$2
59717		 slt   $19,$25,$0        	 # Set Sign
59718		 sltiu $18,$25,1         	 # Set Zero
59719		 or    $20,$0,$16      	 # Copy Carry to X
59720		 sb    $2,0x00($24)
59721		 addiu $15,$15,-4
59722		 bgez  $15,3f
59723		 lhu   $24,0x00($23)    	 # Delay slot
59724		 j     MainExit
59725	3:
59726		 sll   $7,$24,2         	 # Delay slot
59727		 addu  $7,$7,$30
59728		 lw    $7,0x00($7)
59729		 jr    $7
59730		 nop                    	 # Delay slot
59731
59732OP0_4410:				#:
59733		 addiu $23,$23,2
59734
59735		 andi  $24,$24,0x07
59736		 sll   $24,$24,2
59737		 addu  $24,$24,$21
59738		 lw    $14,0x20($24)
59739		 lw    $25,0x7C($21)
59740		 sw    $15,m68k_ICount
59741		 sw    $14,0x44($29)
59742		 or    $4,$0,$14
59743		 jalr  $25
59744		 sw    $23,0x4C($21)    	 # Delay slot
59745		 lw    $14,0x44($29)
59746		 lw    $15,m68k_ICount
59747		 seb   $8,$2
59748		 subu  $2,$0,$8
59749		 sltu  $16,$0,$8       	 # Set Carry
59750		 xor   $17,$0,$8
59751		 xor   $25,$2,$0
59752		 and   $17,$17,$25
59753		 srl   $17,$17,7
59754		 andi  $17,$17,0x01     	 # Set Overflow
59755		 seb  $25,$2
59756		 slt   $19,$25,$0        	 # Set Sign
59757		 sltiu $18,$25,1         	 # Set Zero
59758		 or    $20,$0,$16      	 # Copy Carry to X
59759		 lw    $25,0x88($21)
59760		 sw    $15,m68k_ICount
59761		 or    $5,$0,$2
59762		 or    $4,$0,$14
59763		 jalr  $25
59764		 sw    $23,0x4C($21)    	 # Delay slot
59765		 lw    $15,m68k_ICount
59766		 addiu $15,$15,-8
59767		 bgez  $15,3f
59768		 lhu   $24,0x00($23)    	 # Delay slot
59769		 j     MainExit
59770	3:
59771		 sll   $7,$24,2         	 # Delay slot
59772		 addu  $7,$7,$30
59773		 lw    $7,0x00($7)
59774		 jr    $7
59775		 nop                    	 # Delay slot
59776
59777OP0_4418:				#:
59778		 addiu $23,$23,2
59779
59780		 andi  $24,$24,0x07
59781		 sll   $24,$24,2
59782		 addu  $24,$24,$21
59783		 lw    $14,0x20($24)
59784		 addiu $25,$14,1
59785		 sw    $25,0x20($24)
59786		 lw    $25,0x7C($21)
59787		 sw    $15,m68k_ICount
59788		 sw    $14,0x44($29)
59789		 or    $4,$0,$14
59790		 jalr  $25
59791		 sw    $23,0x4C($21)    	 # Delay slot
59792		 lw    $14,0x44($29)
59793		 lw    $15,m68k_ICount
59794		 seb   $8,$2
59795		 subu  $2,$0,$8
59796		 sltu  $16,$0,$8       	 # Set Carry
59797		 xor   $17,$0,$8
59798		 xor   $25,$2,$0
59799		 and   $17,$17,$25
59800		 srl   $17,$17,7
59801		 andi  $17,$17,0x01     	 # Set Overflow
59802		 seb  $25,$2
59803		 slt   $19,$25,$0        	 # Set Sign
59804		 sltiu $18,$25,1         	 # Set Zero
59805		 or    $20,$0,$16      	 # Copy Carry to X
59806		 lw    $25,0x88($21)
59807		 sw    $15,m68k_ICount
59808		 or    $5,$0,$2
59809		 or    $4,$0,$14
59810		 jalr  $25
59811		 sw    $23,0x4C($21)    	 # Delay slot
59812		 lw    $15,m68k_ICount
59813		 addiu $15,$15,-8
59814		 bgez  $15,3f
59815		 lhu   $24,0x00($23)    	 # Delay slot
59816		 j     MainExit
59817	3:
59818		 sll   $7,$24,2         	 # Delay slot
59819		 addu  $7,$7,$30
59820		 lw    $7,0x00($7)
59821		 jr    $7
59822		 nop                    	 # Delay slot
59823
59824OP0_441f:				#:
59825		 addiu $23,$23,2
59826
59827		 lw    $14,0x3C($21)    	 # Get A7
59828		 addiu $25,$14,2
59829		 sw    $25,0x3C($21)
59830		 lw    $25,0x7C($21)
59831		 sw    $15,m68k_ICount
59832		 sw    $14,0x44($29)
59833		 or    $4,$0,$14
59834		 jalr  $25
59835		 sw    $23,0x4C($21)    	 # Delay slot
59836		 lw    $14,0x44($29)
59837		 lw    $15,m68k_ICount
59838		 seb   $8,$2
59839		 subu  $2,$0,$8
59840		 sltu  $16,$0,$8       	 # Set Carry
59841		 xor   $17,$0,$8
59842		 xor   $25,$2,$0
59843		 and   $17,$17,$25
59844		 srl   $17,$17,7
59845		 andi  $17,$17,0x01     	 # Set Overflow
59846		 seb  $25,$2
59847		 slt   $19,$25,$0        	 # Set Sign
59848		 sltiu $18,$25,1         	 # Set Zero
59849		 or    $20,$0,$16      	 # Copy Carry to X
59850		 lw    $25,0x88($21)
59851		 sw    $15,m68k_ICount
59852		 or    $5,$0,$2
59853		 or    $4,$0,$14
59854		 jalr  $25
59855		 sw    $23,0x4C($21)    	 # Delay slot
59856		 lw    $15,m68k_ICount
59857		 addiu $15,$15,-8
59858		 bgez  $15,3f
59859		 lhu   $24,0x00($23)    	 # Delay slot
59860		 j     MainExit
59861	3:
59862		 sll   $7,$24,2         	 # Delay slot
59863		 addu  $7,$7,$30
59864		 lw    $7,0x00($7)
59865		 jr    $7
59866		 nop                    	 # Delay slot
59867
59868OP0_4420:				#:
59869		 addiu $23,$23,2
59870
59871		 andi  $24,$24,0x07
59872		 sll   $24,$24,2
59873		 addu  $24,$24,$21
59874		 lw    $14,0x20($24)
59875		 addiu $14,$14,-1
59876		 sw    $14,0x20($24)
59877		 lw    $25,0x7C($21)
59878		 sw    $15,m68k_ICount
59879		 sw    $14,0x44($29)
59880		 or    $4,$0,$14
59881		 jalr  $25
59882		 sw    $23,0x4C($21)    	 # Delay slot
59883		 lw    $14,0x44($29)
59884		 lw    $15,m68k_ICount
59885		 seb   $8,$2
59886		 subu  $2,$0,$8
59887		 sltu  $16,$0,$8       	 # Set Carry
59888		 xor   $17,$0,$8
59889		 xor   $25,$2,$0
59890		 and   $17,$17,$25
59891		 srl   $17,$17,7
59892		 andi  $17,$17,0x01     	 # Set Overflow
59893		 seb  $25,$2
59894		 slt   $19,$25,$0        	 # Set Sign
59895		 sltiu $18,$25,1         	 # Set Zero
59896		 or    $20,$0,$16      	 # Copy Carry to X
59897		 lw    $25,0x88($21)
59898		 sw    $15,m68k_ICount
59899		 or    $5,$0,$2
59900		 or    $4,$0,$14
59901		 jalr  $25
59902		 sw    $23,0x4C($21)    	 # Delay slot
59903		 lw    $15,m68k_ICount
59904		 addiu $15,$15,-10
59905		 bgez  $15,3f
59906		 lhu   $24,0x00($23)    	 # Delay slot
59907		 j     MainExit
59908	3:
59909		 sll   $7,$24,2         	 # Delay slot
59910		 addu  $7,$7,$30
59911		 lw    $7,0x00($7)
59912		 jr    $7
59913		 nop                    	 # Delay slot
59914
59915OP0_4427:				#:
59916		 addiu $23,$23,2
59917
59918		 lw    $14,0x3C($21)    	 # Get A7
59919		 addiu $14,$14,-2
59920		 sw    $14,0x3C($21)
59921		 lw    $25,0x7C($21)
59922		 sw    $15,m68k_ICount
59923		 sw    $14,0x44($29)
59924		 or    $4,$0,$14
59925		 jalr  $25
59926		 sw    $23,0x4C($21)    	 # Delay slot
59927		 lw    $14,0x44($29)
59928		 lw    $15,m68k_ICount
59929		 seb   $8,$2
59930		 subu  $2,$0,$8
59931		 sltu  $16,$0,$8       	 # Set Carry
59932		 xor   $17,$0,$8
59933		 xor   $25,$2,$0
59934		 and   $17,$17,$25
59935		 srl   $17,$17,7
59936		 andi  $17,$17,0x01     	 # Set Overflow
59937		 seb  $25,$2
59938		 slt   $19,$25,$0        	 # Set Sign
59939		 sltiu $18,$25,1         	 # Set Zero
59940		 or    $20,$0,$16      	 # Copy Carry to X
59941		 lw    $25,0x88($21)
59942		 sw    $15,m68k_ICount
59943		 or    $5,$0,$2
59944		 or    $4,$0,$14
59945		 jalr  $25
59946		 sw    $23,0x4C($21)    	 # Delay slot
59947		 lw    $15,m68k_ICount
59948		 addiu $15,$15,-10
59949		 bgez  $15,3f
59950		 lhu   $24,0x00($23)    	 # Delay slot
59951		 j     MainExit
59952	3:
59953		 sll   $7,$24,2         	 # Delay slot
59954		 addu  $7,$7,$30
59955		 lw    $7,0x00($7)
59956		 jr    $7
59957		 nop                    	 # Delay slot
59958
59959OP0_4428:				#:
59960		 addiu $23,$23,2
59961
59962		 andi  $24,$24,0x07
59963		 lh    $7,0x00($23)
59964		 sll   $24,$24,2
59965		 addu  $24,$24,$21
59966		 lw    $14,0x20($24)
59967		 addiu $23,$23,2
59968		 addu  $14,$14,$7
59969		 lw    $25,0x7C($21)
59970		 sw    $15,m68k_ICount
59971		 sw    $14,0x44($29)
59972		 or    $4,$0,$14
59973		 jalr  $25
59974		 sw    $23,0x4C($21)    	 # Delay slot
59975		 lw    $14,0x44($29)
59976		 lw    $15,m68k_ICount
59977		 seb   $8,$2
59978		 subu  $2,$0,$8
59979		 sltu  $16,$0,$8       	 # Set Carry
59980		 xor   $17,$0,$8
59981		 xor   $25,$2,$0
59982		 and   $17,$17,$25
59983		 srl   $17,$17,7
59984		 andi  $17,$17,0x01     	 # Set Overflow
59985		 seb  $25,$2
59986		 slt   $19,$25,$0        	 # Set Sign
59987		 sltiu $18,$25,1         	 # Set Zero
59988		 or    $20,$0,$16      	 # Copy Carry to X
59989		 lw    $25,0x88($21)
59990		 sw    $15,m68k_ICount
59991		 or    $5,$0,$2
59992		 or    $4,$0,$14
59993		 jalr  $25
59994		 sw    $23,0x4C($21)    	 # Delay slot
59995		 lw    $15,m68k_ICount
59996		 addiu $15,$15,-12
59997		 bgez  $15,3f
59998		 lhu   $24,0x00($23)    	 # Delay slot
59999		 j     MainExit
60000	3:
60001		 sll   $7,$24,2         	 # Delay slot
60002		 addu  $7,$7,$30
60003		 lw    $7,0x00($7)
60004		 jr    $7
60005		 nop                    	 # Delay slot
60006
60007OP0_4430:				#:
60008		 addiu $23,$23,2
60009
60010		 andi  $24,$24,0x07
60011		 sll   $24,$24,2
60012		 addu  $24,$24,$21
60013		 lw    $14,0x20($24)
60014		 lhu   $7,0x00($23)
60015		 addiu $23,$23,2
60016		 seb   $6,$7
60017		 or    $25,$0,$7
60018		 srl   $7,$7,12
60019		 andi  $25,$25,0x0800
60020		 sll   $7,$7,2
60021		 addu  $7,$7,$21
60022		 bne   $25,$0,0f
60023		 lw    $25,0x00($7)      	 # Delay slot
60024		 seh   $25,$25
60025	0:
60026		 addu  $25,$14,$25
60027		 addu  $14,$25,$6
60028		 lw    $25,0x7C($21)
60029		 sw    $15,m68k_ICount
60030		 sw    $14,0x44($29)
60031		 or    $4,$0,$14
60032		 jalr  $25
60033		 sw    $23,0x4C($21)    	 # Delay slot
60034		 lw    $14,0x44($29)
60035		 lw    $15,m68k_ICount
60036		 seb   $8,$2
60037		 subu  $2,$0,$8
60038		 sltu  $16,$0,$8       	 # Set Carry
60039		 xor   $17,$0,$8
60040		 xor   $25,$2,$0
60041		 and   $17,$17,$25
60042		 srl   $17,$17,7
60043		 andi  $17,$17,0x01     	 # Set Overflow
60044		 seb  $25,$2
60045		 slt   $19,$25,$0        	 # Set Sign
60046		 sltiu $18,$25,1         	 # Set Zero
60047		 or    $20,$0,$16      	 # Copy Carry to X
60048		 lw    $25,0x88($21)
60049		 sw    $15,m68k_ICount
60050		 or    $5,$0,$2
60051		 or    $4,$0,$14
60052		 jalr  $25
60053		 sw    $23,0x4C($21)    	 # Delay slot
60054		 lw    $15,m68k_ICount
60055		 addiu $15,$15,-14
60056		 bgez  $15,3f
60057		 lhu   $24,0x00($23)    	 # Delay slot
60058		 j     MainExit
60059	3:
60060		 sll   $7,$24,2         	 # Delay slot
60061		 addu  $7,$7,$30
60062		 lw    $7,0x00($7)
60063		 jr    $7
60064		 nop                    	 # Delay slot
60065
60066OP0_4438:				#:
60067		 addiu $23,$23,2
60068
60069		 lh    $14,0x00($23)
60070		 addiu $23,$23,2
60071		 lw    $25,0x7C($21)
60072		 sw    $15,m68k_ICount
60073		 sw    $14,0x44($29)
60074		 or    $4,$0,$14
60075		 jalr  $25
60076		 sw    $23,0x4C($21)    	 # Delay slot
60077		 lw    $14,0x44($29)
60078		 lw    $15,m68k_ICount
60079		 seb   $8,$2
60080		 subu  $2,$0,$8
60081		 sltu  $16,$0,$8       	 # Set Carry
60082		 xor   $17,$0,$8
60083		 xor   $25,$2,$0
60084		 and   $17,$17,$25
60085		 srl   $17,$17,7
60086		 andi  $17,$17,0x01     	 # Set Overflow
60087		 seb  $25,$2
60088		 slt   $19,$25,$0        	 # Set Sign
60089		 sltiu $18,$25,1         	 # Set Zero
60090		 or    $20,$0,$16      	 # Copy Carry to X
60091		 lw    $25,0x88($21)
60092		 sw    $15,m68k_ICount
60093		 or    $5,$0,$2
60094		 or    $4,$0,$14
60095		 jalr  $25
60096		 sw    $23,0x4C($21)    	 # Delay slot
60097		 lw    $15,m68k_ICount
60098		 addiu $15,$15,-12
60099		 bgez  $15,3f
60100		 lhu   $24,0x00($23)    	 # Delay slot
60101		 j     MainExit
60102	3:
60103		 sll   $7,$24,2         	 # Delay slot
60104		 addu  $7,$7,$30
60105		 lw    $7,0x00($7)
60106		 jr    $7
60107		 nop                    	 # Delay slot
60108
60109OP0_4439:				#:
60110		 addiu $23,$23,2
60111
60112		 lhu   $14,0x00($23)
60113		 lhu   $25,0x02($23)
60114		 sll   $14,$14,16
60115		 or    $14,$14,$25
60116		 addiu $23,$23,4
60117		 lw    $25,0x7C($21)
60118		 sw    $15,m68k_ICount
60119		 sw    $14,0x44($29)
60120		 or    $4,$0,$14
60121		 jalr  $25
60122		 sw    $23,0x4C($21)    	 # Delay slot
60123		 lw    $14,0x44($29)
60124		 lw    $15,m68k_ICount
60125		 seb   $8,$2
60126		 subu  $2,$0,$8
60127		 sltu  $16,$0,$8       	 # Set Carry
60128		 xor   $17,$0,$8
60129		 xor   $25,$2,$0
60130		 and   $17,$17,$25
60131		 srl   $17,$17,7
60132		 andi  $17,$17,0x01     	 # Set Overflow
60133		 seb  $25,$2
60134		 slt   $19,$25,$0        	 # Set Sign
60135		 sltiu $18,$25,1         	 # Set Zero
60136		 or    $20,$0,$16      	 # Copy Carry to X
60137		 lw    $25,0x88($21)
60138		 sw    $15,m68k_ICount
60139		 or    $5,$0,$2
60140		 or    $4,$0,$14
60141		 jalr  $25
60142		 sw    $23,0x4C($21)    	 # Delay slot
60143		 lw    $15,m68k_ICount
60144		 addiu $15,$15,-16
60145		 bgez  $15,3f
60146		 lhu   $24,0x00($23)    	 # Delay slot
60147		 j     MainExit
60148	3:
60149		 sll   $7,$24,2         	 # Delay slot
60150		 addu  $7,$7,$30
60151		 lw    $7,0x00($7)
60152		 jr    $7
60153		 nop                    	 # Delay slot
60154
60155OP0_4440:				#:
60156		 addiu $23,$23,2
60157
60158		 andi  $24,$24,0x07
60159		 sll   $24,$24,2
60160		 addu  $24,$24,$21
60161		 lh    $8,0x00($24)
60162		 subu  $2,$0,$8
60163		 sltu  $16,$0,$8       	 # Set Carry
60164		 xor   $17,$0,$8
60165		 xor   $25,$2,$0
60166		 and   $17,$17,$25
60167		 srl   $17,$17,15
60168		 andi  $17,$17,0x01     	 # Set Overflow
60169		 seh  $25,$2
60170		 slt   $19,$25,$0        	 # Set Sign
60171		 sltiu $18,$25,1         	 # Set Zero
60172		 or    $20,$0,$16      	 # Copy Carry to X
60173		 sh    $2,0x00($24)
60174		 addiu $15,$15,-4
60175		 bgez  $15,3f
60176		 lhu   $24,0x00($23)    	 # Delay slot
60177		 j     MainExit
60178	3:
60179		 sll   $7,$24,2         	 # Delay slot
60180		 addu  $7,$7,$30
60181		 lw    $7,0x00($7)
60182		 jr    $7
60183		 nop                    	 # Delay slot
60184
60185OP0_4450:				#:
60186		 addiu $23,$23,2
60187
60188		 andi  $24,$24,0x07
60189		 sll   $24,$24,2
60190		 addu  $24,$24,$21
60191		 lw    $14,0x20($24)
60192		 lw    $25,0x80($21)
60193		 sw    $15,m68k_ICount
60194		 sw    $14,0x44($29)
60195		 or    $4,$0,$14
60196		 jalr  $25
60197		 sw    $23,0x4C($21)    	 # Delay slot
60198		 lw    $14,0x44($29)
60199		 lw    $15,m68k_ICount
60200		 seh   $8,$2
60201		 subu  $2,$0,$8
60202		 sltu  $16,$0,$8       	 # Set Carry
60203		 xor   $17,$0,$8
60204		 xor   $25,$2,$0
60205		 and   $17,$17,$25
60206		 srl   $17,$17,15
60207		 andi  $17,$17,0x01     	 # Set Overflow
60208		 seh  $25,$2
60209		 slt   $19,$25,$0        	 # Set Sign
60210		 sltiu $18,$25,1         	 # Set Zero
60211		 or    $20,$0,$16      	 # Copy Carry to X
60212		 lw    $25,0x8C($21)
60213		 sw    $15,m68k_ICount
60214		 or    $5,$0,$2
60215		 or    $4,$0,$14
60216		 jalr  $25
60217		 sw    $23,0x4C($21)    	 # Delay slot
60218		 lw    $15,m68k_ICount
60219		 addiu $15,$15,-8
60220		 bgez  $15,3f
60221		 lhu   $24,0x00($23)    	 # Delay slot
60222		 j     MainExit
60223	3:
60224		 sll   $7,$24,2         	 # Delay slot
60225		 addu  $7,$7,$30
60226		 lw    $7,0x00($7)
60227		 jr    $7
60228		 nop                    	 # Delay slot
60229
60230OP0_4458:				#:
60231		 addiu $23,$23,2
60232
60233		 andi  $24,$24,0x07
60234		 sll   $24,$24,2
60235		 addu  $24,$24,$21
60236		 lw    $14,0x20($24)
60237		 addiu $25,$14,2
60238		 sw    $25,0x20($24)
60239		 lw    $25,0x80($21)
60240		 sw    $15,m68k_ICount
60241		 sw    $14,0x44($29)
60242		 or    $4,$0,$14
60243		 jalr  $25
60244		 sw    $23,0x4C($21)    	 # Delay slot
60245		 lw    $14,0x44($29)
60246		 lw    $15,m68k_ICount
60247		 seh   $8,$2
60248		 subu  $2,$0,$8
60249		 sltu  $16,$0,$8       	 # Set Carry
60250		 xor   $17,$0,$8
60251		 xor   $25,$2,$0
60252		 and   $17,$17,$25
60253		 srl   $17,$17,15
60254		 andi  $17,$17,0x01     	 # Set Overflow
60255		 seh  $25,$2
60256		 slt   $19,$25,$0        	 # Set Sign
60257		 sltiu $18,$25,1         	 # Set Zero
60258		 or    $20,$0,$16      	 # Copy Carry to X
60259		 lw    $25,0x8C($21)
60260		 sw    $15,m68k_ICount
60261		 or    $5,$0,$2
60262		 or    $4,$0,$14
60263		 jalr  $25
60264		 sw    $23,0x4C($21)    	 # Delay slot
60265		 lw    $15,m68k_ICount
60266		 addiu $15,$15,-8
60267		 bgez  $15,3f
60268		 lhu   $24,0x00($23)    	 # Delay slot
60269		 j     MainExit
60270	3:
60271		 sll   $7,$24,2         	 # Delay slot
60272		 addu  $7,$7,$30
60273		 lw    $7,0x00($7)
60274		 jr    $7
60275		 nop                    	 # Delay slot
60276
60277OP0_4460:				#:
60278		 addiu $23,$23,2
60279
60280		 andi  $24,$24,0x07
60281		 sll   $24,$24,2
60282		 addu  $24,$24,$21
60283		 lw    $14,0x20($24)
60284		 addiu $14,$14,-2
60285		 sw    $14,0x20($24)
60286		 lw    $25,0x80($21)
60287		 sw    $15,m68k_ICount
60288		 sw    $14,0x44($29)
60289		 or    $4,$0,$14
60290		 jalr  $25
60291		 sw    $23,0x4C($21)    	 # Delay slot
60292		 lw    $14,0x44($29)
60293		 lw    $15,m68k_ICount
60294		 seh   $8,$2
60295		 subu  $2,$0,$8
60296		 sltu  $16,$0,$8       	 # Set Carry
60297		 xor   $17,$0,$8
60298		 xor   $25,$2,$0
60299		 and   $17,$17,$25
60300		 srl   $17,$17,15
60301		 andi  $17,$17,0x01     	 # Set Overflow
60302		 seh  $25,$2
60303		 slt   $19,$25,$0        	 # Set Sign
60304		 sltiu $18,$25,1         	 # Set Zero
60305		 or    $20,$0,$16      	 # Copy Carry to X
60306		 lw    $25,0x8C($21)
60307		 sw    $15,m68k_ICount
60308		 or    $5,$0,$2
60309		 or    $4,$0,$14
60310		 jalr  $25
60311		 sw    $23,0x4C($21)    	 # Delay slot
60312		 lw    $15,m68k_ICount
60313		 addiu $15,$15,-10
60314		 bgez  $15,3f
60315		 lhu   $24,0x00($23)    	 # Delay slot
60316		 j     MainExit
60317	3:
60318		 sll   $7,$24,2         	 # Delay slot
60319		 addu  $7,$7,$30
60320		 lw    $7,0x00($7)
60321		 jr    $7
60322		 nop                    	 # Delay slot
60323
60324OP0_4468:				#:
60325		 addiu $23,$23,2
60326
60327		 andi  $24,$24,0x07
60328		 lh    $7,0x00($23)
60329		 sll   $24,$24,2
60330		 addu  $24,$24,$21
60331		 lw    $14,0x20($24)
60332		 addiu $23,$23,2
60333		 addu  $14,$14,$7
60334		 lw    $25,0x80($21)
60335		 sw    $15,m68k_ICount
60336		 sw    $14,0x44($29)
60337		 or    $4,$0,$14
60338		 jalr  $25
60339		 sw    $23,0x4C($21)    	 # Delay slot
60340		 lw    $14,0x44($29)
60341		 lw    $15,m68k_ICount
60342		 seh   $8,$2
60343		 subu  $2,$0,$8
60344		 sltu  $16,$0,$8       	 # Set Carry
60345		 xor   $17,$0,$8
60346		 xor   $25,$2,$0
60347		 and   $17,$17,$25
60348		 srl   $17,$17,15
60349		 andi  $17,$17,0x01     	 # Set Overflow
60350		 seh  $25,$2
60351		 slt   $19,$25,$0        	 # Set Sign
60352		 sltiu $18,$25,1         	 # Set Zero
60353		 or    $20,$0,$16      	 # Copy Carry to X
60354		 lw    $25,0x8C($21)
60355		 sw    $15,m68k_ICount
60356		 or    $5,$0,$2
60357		 or    $4,$0,$14
60358		 jalr  $25
60359		 sw    $23,0x4C($21)    	 # Delay slot
60360		 lw    $15,m68k_ICount
60361		 addiu $15,$15,-12
60362		 bgez  $15,3f
60363		 lhu   $24,0x00($23)    	 # Delay slot
60364		 j     MainExit
60365	3:
60366		 sll   $7,$24,2         	 # Delay slot
60367		 addu  $7,$7,$30
60368		 lw    $7,0x00($7)
60369		 jr    $7
60370		 nop                    	 # Delay slot
60371
60372OP0_4470:				#:
60373		 addiu $23,$23,2
60374
60375		 andi  $24,$24,0x07
60376		 sll   $24,$24,2
60377		 addu  $24,$24,$21
60378		 lw    $14,0x20($24)
60379		 lhu   $7,0x00($23)
60380		 addiu $23,$23,2
60381		 seb   $6,$7
60382		 or    $25,$0,$7
60383		 srl   $7,$7,12
60384		 andi  $25,$25,0x0800
60385		 sll   $7,$7,2
60386		 addu  $7,$7,$21
60387		 bne   $25,$0,0f
60388		 lw    $25,0x00($7)      	 # Delay slot
60389		 seh   $25,$25
60390	0:
60391		 addu  $25,$14,$25
60392		 addu  $14,$25,$6
60393		 lw    $25,0x80($21)
60394		 sw    $15,m68k_ICount
60395		 sw    $14,0x44($29)
60396		 or    $4,$0,$14
60397		 jalr  $25
60398		 sw    $23,0x4C($21)    	 # Delay slot
60399		 lw    $14,0x44($29)
60400		 lw    $15,m68k_ICount
60401		 seh   $8,$2
60402		 subu  $2,$0,$8
60403		 sltu  $16,$0,$8       	 # Set Carry
60404		 xor   $17,$0,$8
60405		 xor   $25,$2,$0
60406		 and   $17,$17,$25
60407		 srl   $17,$17,15
60408		 andi  $17,$17,0x01     	 # Set Overflow
60409		 seh  $25,$2
60410		 slt   $19,$25,$0        	 # Set Sign
60411		 sltiu $18,$25,1         	 # Set Zero
60412		 or    $20,$0,$16      	 # Copy Carry to X
60413		 lw    $25,0x8C($21)
60414		 sw    $15,m68k_ICount
60415		 or    $5,$0,$2
60416		 or    $4,$0,$14
60417		 jalr  $25
60418		 sw    $23,0x4C($21)    	 # Delay slot
60419		 lw    $15,m68k_ICount
60420		 addiu $15,$15,-14
60421		 bgez  $15,3f
60422		 lhu   $24,0x00($23)    	 # Delay slot
60423		 j     MainExit
60424	3:
60425		 sll   $7,$24,2         	 # Delay slot
60426		 addu  $7,$7,$30
60427		 lw    $7,0x00($7)
60428		 jr    $7
60429		 nop                    	 # Delay slot
60430
60431OP0_4478:				#:
60432		 addiu $23,$23,2
60433
60434		 lh    $14,0x00($23)
60435		 addiu $23,$23,2
60436		 lw    $25,0x80($21)
60437		 sw    $15,m68k_ICount
60438		 sw    $14,0x44($29)
60439		 or    $4,$0,$14
60440		 jalr  $25
60441		 sw    $23,0x4C($21)    	 # Delay slot
60442		 lw    $14,0x44($29)
60443		 lw    $15,m68k_ICount
60444		 seh   $8,$2
60445		 subu  $2,$0,$8
60446		 sltu  $16,$0,$8       	 # Set Carry
60447		 xor   $17,$0,$8
60448		 xor   $25,$2,$0
60449		 and   $17,$17,$25
60450		 srl   $17,$17,15
60451		 andi  $17,$17,0x01     	 # Set Overflow
60452		 seh  $25,$2
60453		 slt   $19,$25,$0        	 # Set Sign
60454		 sltiu $18,$25,1         	 # Set Zero
60455		 or    $20,$0,$16      	 # Copy Carry to X
60456		 lw    $25,0x8C($21)
60457		 sw    $15,m68k_ICount
60458		 or    $5,$0,$2
60459		 or    $4,$0,$14
60460		 jalr  $25
60461		 sw    $23,0x4C($21)    	 # Delay slot
60462		 lw    $15,m68k_ICount
60463		 addiu $15,$15,-12
60464		 bgez  $15,3f
60465		 lhu   $24,0x00($23)    	 # Delay slot
60466		 j     MainExit
60467	3:
60468		 sll   $7,$24,2         	 # Delay slot
60469		 addu  $7,$7,$30
60470		 lw    $7,0x00($7)
60471		 jr    $7
60472		 nop                    	 # Delay slot
60473
60474OP0_4479:				#:
60475		 addiu $23,$23,2
60476
60477		 lhu   $14,0x00($23)
60478		 lhu   $25,0x02($23)
60479		 sll   $14,$14,16
60480		 or    $14,$14,$25
60481		 addiu $23,$23,4
60482		 lw    $25,0x80($21)
60483		 sw    $15,m68k_ICount
60484		 sw    $14,0x44($29)
60485		 or    $4,$0,$14
60486		 jalr  $25
60487		 sw    $23,0x4C($21)    	 # Delay slot
60488		 lw    $14,0x44($29)
60489		 lw    $15,m68k_ICount
60490		 seh   $8,$2
60491		 subu  $2,$0,$8
60492		 sltu  $16,$0,$8       	 # Set Carry
60493		 xor   $17,$0,$8
60494		 xor   $25,$2,$0
60495		 and   $17,$17,$25
60496		 srl   $17,$17,15
60497		 andi  $17,$17,0x01     	 # Set Overflow
60498		 seh  $25,$2
60499		 slt   $19,$25,$0        	 # Set Sign
60500		 sltiu $18,$25,1         	 # Set Zero
60501		 or    $20,$0,$16      	 # Copy Carry to X
60502		 lw    $25,0x8C($21)
60503		 sw    $15,m68k_ICount
60504		 or    $5,$0,$2
60505		 or    $4,$0,$14
60506		 jalr  $25
60507		 sw    $23,0x4C($21)    	 # Delay slot
60508		 lw    $15,m68k_ICount
60509		 addiu $15,$15,-16
60510		 bgez  $15,3f
60511		 lhu   $24,0x00($23)    	 # Delay slot
60512		 j     MainExit
60513	3:
60514		 sll   $7,$24,2         	 # Delay slot
60515		 addu  $7,$7,$30
60516		 lw    $7,0x00($7)
60517		 jr    $7
60518		 nop                    	 # Delay slot
60519
60520OP0_4480:				#:
60521		 addiu $23,$23,2
60522
60523		 andi  $24,$24,0x07
60524		 sll   $24,$24,2
60525		 addu  $24,$24,$21
60526		 lw    $8,0x00($24)
60527		 subu  $2,$0,$8
60528		 sltu  $16,$0,$8       	 # Set Carry
60529		 xor   $17,$0,$8
60530		 xor   $25,$2,$0
60531		 and   $17,$17,$25
60532		 srl   $17,$17,31        	 # Set Overflow
60533		 slt   $19,$2,$0        	 # Set Sign
60534		 sltiu $18,$2,1         	 # Set Zero
60535		 or    $20,$0,$16      	 # Copy Carry to X
60536		 sw    $2,0x00($24)
60537		 addiu $15,$15,-6
60538		 bgez  $15,3f
60539		 lhu   $24,0x00($23)    	 # Delay slot
60540		 j     MainExit
60541	3:
60542		 sll   $7,$24,2         	 # Delay slot
60543		 addu  $7,$7,$30
60544		 lw    $7,0x00($7)
60545		 jr    $7
60546		 nop                    	 # Delay slot
60547
60548OP0_4490:				#:
60549		 addiu $23,$23,2
60550
60551		 andi  $24,$24,0x07
60552		 sll   $24,$24,2
60553		 addu  $24,$24,$21
60554		 lw    $14,0x20($24)
60555		 lw    $25,0x84($21)
60556		 sw    $15,m68k_ICount
60557		 sw    $14,0x44($29)
60558		 or    $4,$0,$14
60559		 jalr  $25
60560		 sw    $23,0x4C($21)    	 # Delay slot
60561		 lw    $14,0x44($29)
60562		 lw    $15,m68k_ICount
60563		 or    $8,$0,$2
60564		 subu  $2,$0,$8
60565		 sltu  $16,$0,$8       	 # Set Carry
60566		 xor   $17,$0,$8
60567		 xor   $25,$2,$0
60568		 and   $17,$17,$25
60569		 srl   $17,$17,31        	 # Set Overflow
60570		 slt   $19,$2,$0        	 # Set Sign
60571		 sltiu $18,$2,1         	 # Set Zero
60572		 or    $20,$0,$16      	 # Copy Carry to X
60573		 lw    $25,0x90($21)
60574		 sw    $15,m68k_ICount
60575		 or    $5,$0,$2
60576		 or    $4,$0,$14
60577		 jalr  $25
60578		 sw    $23,0x4C($21)    	 # Delay slot
60579		 lw    $15,m68k_ICount
60580		 addiu $15,$15,-14
60581		 bgez  $15,3f
60582		 lhu   $24,0x00($23)    	 # Delay slot
60583		 j     MainExit
60584	3:
60585		 sll   $7,$24,2         	 # Delay slot
60586		 addu  $7,$7,$30
60587		 lw    $7,0x00($7)
60588		 jr    $7
60589		 nop                    	 # Delay slot
60590
60591OP0_4498:				#:
60592		 addiu $23,$23,2
60593
60594		 andi  $24,$24,0x07
60595		 sll   $24,$24,2
60596		 addu  $24,$24,$21
60597		 lw    $14,0x20($24)
60598		 addiu $25,$14,4
60599		 sw    $25,0x20($24)
60600		 lw    $25,0x84($21)
60601		 sw    $15,m68k_ICount
60602		 sw    $14,0x44($29)
60603		 or    $4,$0,$14
60604		 jalr  $25
60605		 sw    $23,0x4C($21)    	 # Delay slot
60606		 lw    $14,0x44($29)
60607		 lw    $15,m68k_ICount
60608		 or    $8,$0,$2
60609		 subu  $2,$0,$8
60610		 sltu  $16,$0,$8       	 # Set Carry
60611		 xor   $17,$0,$8
60612		 xor   $25,$2,$0
60613		 and   $17,$17,$25
60614		 srl   $17,$17,31        	 # Set Overflow
60615		 slt   $19,$2,$0        	 # Set Sign
60616		 sltiu $18,$2,1         	 # Set Zero
60617		 or    $20,$0,$16      	 # Copy Carry to X
60618		 lw    $25,0x90($21)
60619		 sw    $15,m68k_ICount
60620		 or    $5,$0,$2
60621		 or    $4,$0,$14
60622		 jalr  $25
60623		 sw    $23,0x4C($21)    	 # Delay slot
60624		 lw    $15,m68k_ICount
60625		 addiu $15,$15,-14
60626		 bgez  $15,3f
60627		 lhu   $24,0x00($23)    	 # Delay slot
60628		 j     MainExit
60629	3:
60630		 sll   $7,$24,2         	 # Delay slot
60631		 addu  $7,$7,$30
60632		 lw    $7,0x00($7)
60633		 jr    $7
60634		 nop                    	 # Delay slot
60635
60636OP0_44a0:				#:
60637		 addiu $23,$23,2
60638
60639		 andi  $24,$24,0x07
60640		 sll   $24,$24,2
60641		 addu  $24,$24,$21
60642		 lw    $14,0x20($24)
60643		 addiu $14,$14,-4
60644		 sw    $14,0x20($24)
60645		 lw    $25,0x84($21)
60646		 sw    $15,m68k_ICount
60647		 sw    $14,0x44($29)
60648		 or    $4,$0,$14
60649		 jalr  $25
60650		 sw    $23,0x4C($21)    	 # Delay slot
60651		 lw    $14,0x44($29)
60652		 lw    $15,m68k_ICount
60653		 or    $8,$0,$2
60654		 subu  $2,$0,$8
60655		 sltu  $16,$0,$8       	 # Set Carry
60656		 xor   $17,$0,$8
60657		 xor   $25,$2,$0
60658		 and   $17,$17,$25
60659		 srl   $17,$17,31        	 # Set Overflow
60660		 slt   $19,$2,$0        	 # Set Sign
60661		 sltiu $18,$2,1         	 # Set Zero
60662		 or    $20,$0,$16      	 # Copy Carry to X
60663		 lw    $25,0x90($21)
60664		 sw    $15,m68k_ICount
60665		 or    $5,$0,$2
60666		 or    $4,$0,$14
60667		 jalr  $25
60668		 sw    $23,0x4C($21)    	 # Delay slot
60669		 lw    $15,m68k_ICount
60670		 addiu $15,$15,-16
60671		 bgez  $15,3f
60672		 lhu   $24,0x00($23)    	 # Delay slot
60673		 j     MainExit
60674	3:
60675		 sll   $7,$24,2         	 # Delay slot
60676		 addu  $7,$7,$30
60677		 lw    $7,0x00($7)
60678		 jr    $7
60679		 nop                    	 # Delay slot
60680
60681OP0_44a8:				#:
60682		 addiu $23,$23,2
60683
60684		 andi  $24,$24,0x07
60685		 lh    $7,0x00($23)
60686		 sll   $24,$24,2
60687		 addu  $24,$24,$21
60688		 lw    $14,0x20($24)
60689		 addiu $23,$23,2
60690		 addu  $14,$14,$7
60691		 lw    $25,0x84($21)
60692		 sw    $15,m68k_ICount
60693		 sw    $14,0x44($29)
60694		 or    $4,$0,$14
60695		 jalr  $25
60696		 sw    $23,0x4C($21)    	 # Delay slot
60697		 lw    $14,0x44($29)
60698		 lw    $15,m68k_ICount
60699		 or    $8,$0,$2
60700		 subu  $2,$0,$8
60701		 sltu  $16,$0,$8       	 # Set Carry
60702		 xor   $17,$0,$8
60703		 xor   $25,$2,$0
60704		 and   $17,$17,$25
60705		 srl   $17,$17,31        	 # Set Overflow
60706		 slt   $19,$2,$0        	 # Set Sign
60707		 sltiu $18,$2,1         	 # Set Zero
60708		 or    $20,$0,$16      	 # Copy Carry to X
60709		 lw    $25,0x90($21)
60710		 sw    $15,m68k_ICount
60711		 or    $5,$0,$2
60712		 or    $4,$0,$14
60713		 jalr  $25
60714		 sw    $23,0x4C($21)    	 # Delay slot
60715		 lw    $15,m68k_ICount
60716		 addiu $15,$15,-18
60717		 bgez  $15,3f
60718		 lhu   $24,0x00($23)    	 # Delay slot
60719		 j     MainExit
60720	3:
60721		 sll   $7,$24,2         	 # Delay slot
60722		 addu  $7,$7,$30
60723		 lw    $7,0x00($7)
60724		 jr    $7
60725		 nop                    	 # Delay slot
60726
60727OP0_44b0:				#:
60728		 addiu $23,$23,2
60729
60730		 andi  $24,$24,0x07
60731		 sll   $24,$24,2
60732		 addu  $24,$24,$21
60733		 lw    $14,0x20($24)
60734		 lhu   $7,0x00($23)
60735		 addiu $23,$23,2
60736		 seb   $6,$7
60737		 or    $25,$0,$7
60738		 srl   $7,$7,12
60739		 andi  $25,$25,0x0800
60740		 sll   $7,$7,2
60741		 addu  $7,$7,$21
60742		 bne   $25,$0,0f
60743		 lw    $25,0x00($7)      	 # Delay slot
60744		 seh   $25,$25
60745	0:
60746		 addu  $25,$14,$25
60747		 addu  $14,$25,$6
60748		 lw    $25,0x84($21)
60749		 sw    $15,m68k_ICount
60750		 sw    $14,0x44($29)
60751		 or    $4,$0,$14
60752		 jalr  $25
60753		 sw    $23,0x4C($21)    	 # Delay slot
60754		 lw    $14,0x44($29)
60755		 lw    $15,m68k_ICount
60756		 or    $8,$0,$2
60757		 subu  $2,$0,$8
60758		 sltu  $16,$0,$8       	 # Set Carry
60759		 xor   $17,$0,$8
60760		 xor   $25,$2,$0
60761		 and   $17,$17,$25
60762		 srl   $17,$17,31        	 # Set Overflow
60763		 slt   $19,$2,$0        	 # Set Sign
60764		 sltiu $18,$2,1         	 # Set Zero
60765		 or    $20,$0,$16      	 # Copy Carry to X
60766		 lw    $25,0x90($21)
60767		 sw    $15,m68k_ICount
60768		 or    $5,$0,$2
60769		 or    $4,$0,$14
60770		 jalr  $25
60771		 sw    $23,0x4C($21)    	 # Delay slot
60772		 lw    $15,m68k_ICount
60773		 addiu $15,$15,-20
60774		 bgez  $15,3f
60775		 lhu   $24,0x00($23)    	 # Delay slot
60776		 j     MainExit
60777	3:
60778		 sll   $7,$24,2         	 # Delay slot
60779		 addu  $7,$7,$30
60780		 lw    $7,0x00($7)
60781		 jr    $7
60782		 nop                    	 # Delay slot
60783
60784OP0_44b8:				#:
60785		 addiu $23,$23,2
60786
60787		 lh    $14,0x00($23)
60788		 addiu $23,$23,2
60789		 lw    $25,0x84($21)
60790		 sw    $15,m68k_ICount
60791		 sw    $14,0x44($29)
60792		 or    $4,$0,$14
60793		 jalr  $25
60794		 sw    $23,0x4C($21)    	 # Delay slot
60795		 lw    $14,0x44($29)
60796		 lw    $15,m68k_ICount
60797		 or    $8,$0,$2
60798		 subu  $2,$0,$8
60799		 sltu  $16,$0,$8       	 # Set Carry
60800		 xor   $17,$0,$8
60801		 xor   $25,$2,$0
60802		 and   $17,$17,$25
60803		 srl   $17,$17,31        	 # Set Overflow
60804		 slt   $19,$2,$0        	 # Set Sign
60805		 sltiu $18,$2,1         	 # Set Zero
60806		 or    $20,$0,$16      	 # Copy Carry to X
60807		 lw    $25,0x90($21)
60808		 sw    $15,m68k_ICount
60809		 or    $5,$0,$2
60810		 or    $4,$0,$14
60811		 jalr  $25
60812		 sw    $23,0x4C($21)    	 # Delay slot
60813		 lw    $15,m68k_ICount
60814		 addiu $15,$15,-18
60815		 bgez  $15,3f
60816		 lhu   $24,0x00($23)    	 # Delay slot
60817		 j     MainExit
60818	3:
60819		 sll   $7,$24,2         	 # Delay slot
60820		 addu  $7,$7,$30
60821		 lw    $7,0x00($7)
60822		 jr    $7
60823		 nop                    	 # Delay slot
60824
60825OP0_44b9:				#:
60826		 addiu $23,$23,2
60827
60828		 lhu   $14,0x00($23)
60829		 lhu   $25,0x02($23)
60830		 sll   $14,$14,16
60831		 or    $14,$14,$25
60832		 addiu $23,$23,4
60833		 lw    $25,0x84($21)
60834		 sw    $15,m68k_ICount
60835		 sw    $14,0x44($29)
60836		 or    $4,$0,$14
60837		 jalr  $25
60838		 sw    $23,0x4C($21)    	 # Delay slot
60839		 lw    $14,0x44($29)
60840		 lw    $15,m68k_ICount
60841		 or    $8,$0,$2
60842		 subu  $2,$0,$8
60843		 sltu  $16,$0,$8       	 # Set Carry
60844		 xor   $17,$0,$8
60845		 xor   $25,$2,$0
60846		 and   $17,$17,$25
60847		 srl   $17,$17,31        	 # Set Overflow
60848		 slt   $19,$2,$0        	 # Set Sign
60849		 sltiu $18,$2,1         	 # Set Zero
60850		 or    $20,$0,$16      	 # Copy Carry to X
60851		 lw    $25,0x90($21)
60852		 sw    $15,m68k_ICount
60853		 or    $5,$0,$2
60854		 or    $4,$0,$14
60855		 jalr  $25
60856		 sw    $23,0x4C($21)    	 # Delay slot
60857		 lw    $15,m68k_ICount
60858		 addiu $15,$15,-22
60859		 bgez  $15,3f
60860		 lhu   $24,0x00($23)    	 # Delay slot
60861		 j     MainExit
60862	3:
60863		 sll   $7,$24,2         	 # Delay slot
60864		 addu  $7,$7,$30
60865		 lw    $7,0x00($7)
60866		 jr    $7
60867		 nop                    	 # Delay slot
60868
60869OP0_4600:				#:
60870		 addiu $23,$23,2
60871
60872		 andi  $24,$24,0x07
60873		 sll   $24,$24,2
60874		 addu  $24,$24,$21
60875		 lb    $2,0x00($24)
60876		 nor   $2,$0,$2
60877		 and   $16,$0,$0        	 # Clear Carry
60878		 and   $17,$0,$0        	 # Clear Overflow
60879		 slt   $19,$2,$0        	 # Set Sign
60880		 sltiu $18,$2,1         	 # Set Zero
60881		 sb    $2,0x00($24)
60882		 addiu $15,$15,-4
60883		 bgez  $15,3f
60884		 lhu   $24,0x00($23)    	 # Delay slot
60885		 j     MainExit
60886	3:
60887		 sll   $7,$24,2         	 # Delay slot
60888		 addu  $7,$7,$30
60889		 lw    $7,0x00($7)
60890		 jr    $7
60891		 nop                    	 # Delay slot
60892
60893OP0_4610:				#:
60894		 addiu $23,$23,2
60895
60896		 andi  $24,$24,0x07
60897		 sll   $24,$24,2
60898		 addu  $24,$24,$21
60899		 lw    $14,0x20($24)
60900		 lw    $25,0x7C($21)
60901		 sw    $15,m68k_ICount
60902		 sw    $14,0x44($29)
60903		 or    $4,$0,$14
60904		 jalr  $25
60905		 sw    $23,0x4C($21)    	 # Delay slot
60906		 lw    $14,0x44($29)
60907		 lw    $15,m68k_ICount
60908		 seb   $2,$2
60909		 nor   $2,$0,$2
60910		 and   $16,$0,$0        	 # Clear Carry
60911		 and   $17,$0,$0        	 # Clear Overflow
60912		 slt   $19,$2,$0        	 # Set Sign
60913		 sltiu $18,$2,1         	 # Set Zero
60914		 lw    $25,0x88($21)
60915		 sw    $15,m68k_ICount
60916		 or    $5,$0,$2
60917		 or    $4,$0,$14
60918		 jalr  $25
60919		 sw    $23,0x4C($21)    	 # Delay slot
60920		 lw    $15,m68k_ICount
60921		 addiu $15,$15,-8
60922		 bgez  $15,3f
60923		 lhu   $24,0x00($23)    	 # Delay slot
60924		 j     MainExit
60925	3:
60926		 sll   $7,$24,2         	 # Delay slot
60927		 addu  $7,$7,$30
60928		 lw    $7,0x00($7)
60929		 jr    $7
60930		 nop                    	 # Delay slot
60931
60932OP0_4618:				#:
60933		 addiu $23,$23,2
60934
60935		 andi  $24,$24,0x07
60936		 sll   $24,$24,2
60937		 addu  $24,$24,$21
60938		 lw    $14,0x20($24)
60939		 addiu $25,$14,1
60940		 sw    $25,0x20($24)
60941		 lw    $25,0x7C($21)
60942		 sw    $15,m68k_ICount
60943		 sw    $14,0x44($29)
60944		 or    $4,$0,$14
60945		 jalr  $25
60946		 sw    $23,0x4C($21)    	 # Delay slot
60947		 lw    $14,0x44($29)
60948		 lw    $15,m68k_ICount
60949		 seb   $2,$2
60950		 nor   $2,$0,$2
60951		 and   $16,$0,$0        	 # Clear Carry
60952		 and   $17,$0,$0        	 # Clear Overflow
60953		 slt   $19,$2,$0        	 # Set Sign
60954		 sltiu $18,$2,1         	 # Set Zero
60955		 lw    $25,0x88($21)
60956		 sw    $15,m68k_ICount
60957		 or    $5,$0,$2
60958		 or    $4,$0,$14
60959		 jalr  $25
60960		 sw    $23,0x4C($21)    	 # Delay slot
60961		 lw    $15,m68k_ICount
60962		 addiu $15,$15,-8
60963		 bgez  $15,3f
60964		 lhu   $24,0x00($23)    	 # Delay slot
60965		 j     MainExit
60966	3:
60967		 sll   $7,$24,2         	 # Delay slot
60968		 addu  $7,$7,$30
60969		 lw    $7,0x00($7)
60970		 jr    $7
60971		 nop                    	 # Delay slot
60972
60973OP0_461f:				#:
60974		 addiu $23,$23,2
60975
60976		 lw    $14,0x3C($21)    	 # Get A7
60977		 addiu $25,$14,2
60978		 sw    $25,0x3C($21)
60979		 lw    $25,0x7C($21)
60980		 sw    $15,m68k_ICount
60981		 sw    $14,0x44($29)
60982		 or    $4,$0,$14
60983		 jalr  $25
60984		 sw    $23,0x4C($21)    	 # Delay slot
60985		 lw    $14,0x44($29)
60986		 lw    $15,m68k_ICount
60987		 seb   $2,$2
60988		 nor   $2,$0,$2
60989		 and   $16,$0,$0        	 # Clear Carry
60990		 and   $17,$0,$0        	 # Clear Overflow
60991		 slt   $19,$2,$0        	 # Set Sign
60992		 sltiu $18,$2,1         	 # Set Zero
60993		 lw    $25,0x88($21)
60994		 sw    $15,m68k_ICount
60995		 or    $5,$0,$2
60996		 or    $4,$0,$14
60997		 jalr  $25
60998		 sw    $23,0x4C($21)    	 # Delay slot
60999		 lw    $15,m68k_ICount
61000		 addiu $15,$15,-8
61001		 bgez  $15,3f
61002		 lhu   $24,0x00($23)    	 # Delay slot
61003		 j     MainExit
61004	3:
61005		 sll   $7,$24,2         	 # Delay slot
61006		 addu  $7,$7,$30
61007		 lw    $7,0x00($7)
61008		 jr    $7
61009		 nop                    	 # Delay slot
61010
61011OP0_4620:				#:
61012		 addiu $23,$23,2
61013
61014		 andi  $24,$24,0x07
61015		 sll   $24,$24,2
61016		 addu  $24,$24,$21
61017		 lw    $14,0x20($24)
61018		 addiu $14,$14,-1
61019		 sw    $14,0x20($24)
61020		 lw    $25,0x7C($21)
61021		 sw    $15,m68k_ICount
61022		 sw    $14,0x44($29)
61023		 or    $4,$0,$14
61024		 jalr  $25
61025		 sw    $23,0x4C($21)    	 # Delay slot
61026		 lw    $14,0x44($29)
61027		 lw    $15,m68k_ICount
61028		 seb   $2,$2
61029		 nor   $2,$0,$2
61030		 and   $16,$0,$0        	 # Clear Carry
61031		 and   $17,$0,$0        	 # Clear Overflow
61032		 slt   $19,$2,$0        	 # Set Sign
61033		 sltiu $18,$2,1         	 # Set Zero
61034		 lw    $25,0x88($21)
61035		 sw    $15,m68k_ICount
61036		 or    $5,$0,$2
61037		 or    $4,$0,$14
61038		 jalr  $25
61039		 sw    $23,0x4C($21)    	 # Delay slot
61040		 lw    $15,m68k_ICount
61041		 addiu $15,$15,-10
61042		 bgez  $15,3f
61043		 lhu   $24,0x00($23)    	 # Delay slot
61044		 j     MainExit
61045	3:
61046		 sll   $7,$24,2         	 # Delay slot
61047		 addu  $7,$7,$30
61048		 lw    $7,0x00($7)
61049		 jr    $7
61050		 nop                    	 # Delay slot
61051
61052OP0_4627:				#:
61053		 addiu $23,$23,2
61054
61055		 lw    $14,0x3C($21)    	 # Get A7
61056		 addiu $14,$14,-2
61057		 sw    $14,0x3C($21)
61058		 lw    $25,0x7C($21)
61059		 sw    $15,m68k_ICount
61060		 sw    $14,0x44($29)
61061		 or    $4,$0,$14
61062		 jalr  $25
61063		 sw    $23,0x4C($21)    	 # Delay slot
61064		 lw    $14,0x44($29)
61065		 lw    $15,m68k_ICount
61066		 seb   $2,$2
61067		 nor   $2,$0,$2
61068		 and   $16,$0,$0        	 # Clear Carry
61069		 and   $17,$0,$0        	 # Clear Overflow
61070		 slt   $19,$2,$0        	 # Set Sign
61071		 sltiu $18,$2,1         	 # Set Zero
61072		 lw    $25,0x88($21)
61073		 sw    $15,m68k_ICount
61074		 or    $5,$0,$2
61075		 or    $4,$0,$14
61076		 jalr  $25
61077		 sw    $23,0x4C($21)    	 # Delay slot
61078		 lw    $15,m68k_ICount
61079		 addiu $15,$15,-10
61080		 bgez  $15,3f
61081		 lhu   $24,0x00($23)    	 # Delay slot
61082		 j     MainExit
61083	3:
61084		 sll   $7,$24,2         	 # Delay slot
61085		 addu  $7,$7,$30
61086		 lw    $7,0x00($7)
61087		 jr    $7
61088		 nop                    	 # Delay slot
61089
61090OP0_4628:				#:
61091		 addiu $23,$23,2
61092
61093		 andi  $24,$24,0x07
61094		 lh    $7,0x00($23)
61095		 sll   $24,$24,2
61096		 addu  $24,$24,$21
61097		 lw    $14,0x20($24)
61098		 addiu $23,$23,2
61099		 addu  $14,$14,$7
61100		 lw    $25,0x7C($21)
61101		 sw    $15,m68k_ICount
61102		 sw    $14,0x44($29)
61103		 or    $4,$0,$14
61104		 jalr  $25
61105		 sw    $23,0x4C($21)    	 # Delay slot
61106		 lw    $14,0x44($29)
61107		 lw    $15,m68k_ICount
61108		 seb   $2,$2
61109		 nor   $2,$0,$2
61110		 and   $16,$0,$0        	 # Clear Carry
61111		 and   $17,$0,$0        	 # Clear Overflow
61112		 slt   $19,$2,$0        	 # Set Sign
61113		 sltiu $18,$2,1         	 # Set Zero
61114		 lw    $25,0x88($21)
61115		 sw    $15,m68k_ICount
61116		 or    $5,$0,$2
61117		 or    $4,$0,$14
61118		 jalr  $25
61119		 sw    $23,0x4C($21)    	 # Delay slot
61120		 lw    $15,m68k_ICount
61121		 addiu $15,$15,-12
61122		 bgez  $15,3f
61123		 lhu   $24,0x00($23)    	 # Delay slot
61124		 j     MainExit
61125	3:
61126		 sll   $7,$24,2         	 # Delay slot
61127		 addu  $7,$7,$30
61128		 lw    $7,0x00($7)
61129		 jr    $7
61130		 nop                    	 # Delay slot
61131
61132OP0_4630:				#:
61133		 addiu $23,$23,2
61134
61135		 andi  $24,$24,0x07
61136		 sll   $24,$24,2
61137		 addu  $24,$24,$21
61138		 lw    $14,0x20($24)
61139		 lhu   $7,0x00($23)
61140		 addiu $23,$23,2
61141		 seb   $6,$7
61142		 or    $25,$0,$7
61143		 srl   $7,$7,12
61144		 andi  $25,$25,0x0800
61145		 sll   $7,$7,2
61146		 addu  $7,$7,$21
61147		 bne   $25,$0,0f
61148		 lw    $25,0x00($7)      	 # Delay slot
61149		 seh   $25,$25
61150	0:
61151		 addu  $25,$14,$25
61152		 addu  $14,$25,$6
61153		 lw    $25,0x7C($21)
61154		 sw    $15,m68k_ICount
61155		 sw    $14,0x44($29)
61156		 or    $4,$0,$14
61157		 jalr  $25
61158		 sw    $23,0x4C($21)    	 # Delay slot
61159		 lw    $14,0x44($29)
61160		 lw    $15,m68k_ICount
61161		 seb   $2,$2
61162		 nor   $2,$0,$2
61163		 and   $16,$0,$0        	 # Clear Carry
61164		 and   $17,$0,$0        	 # Clear Overflow
61165		 slt   $19,$2,$0        	 # Set Sign
61166		 sltiu $18,$2,1         	 # Set Zero
61167		 lw    $25,0x88($21)
61168		 sw    $15,m68k_ICount
61169		 or    $5,$0,$2
61170		 or    $4,$0,$14
61171		 jalr  $25
61172		 sw    $23,0x4C($21)    	 # Delay slot
61173		 lw    $15,m68k_ICount
61174		 addiu $15,$15,-14
61175		 bgez  $15,3f
61176		 lhu   $24,0x00($23)    	 # Delay slot
61177		 j     MainExit
61178	3:
61179		 sll   $7,$24,2         	 # Delay slot
61180		 addu  $7,$7,$30
61181		 lw    $7,0x00($7)
61182		 jr    $7
61183		 nop                    	 # Delay slot
61184
61185OP0_4638:				#:
61186		 addiu $23,$23,2
61187
61188		 lh    $14,0x00($23)
61189		 addiu $23,$23,2
61190		 lw    $25,0x7C($21)
61191		 sw    $15,m68k_ICount
61192		 sw    $14,0x44($29)
61193		 or    $4,$0,$14
61194		 jalr  $25
61195		 sw    $23,0x4C($21)    	 # Delay slot
61196		 lw    $14,0x44($29)
61197		 lw    $15,m68k_ICount
61198		 seb   $2,$2
61199		 nor   $2,$0,$2
61200		 and   $16,$0,$0        	 # Clear Carry
61201		 and   $17,$0,$0        	 # Clear Overflow
61202		 slt   $19,$2,$0        	 # Set Sign
61203		 sltiu $18,$2,1         	 # Set Zero
61204		 lw    $25,0x88($21)
61205		 sw    $15,m68k_ICount
61206		 or    $5,$0,$2
61207		 or    $4,$0,$14
61208		 jalr  $25
61209		 sw    $23,0x4C($21)    	 # Delay slot
61210		 lw    $15,m68k_ICount
61211		 addiu $15,$15,-12
61212		 bgez  $15,3f
61213		 lhu   $24,0x00($23)    	 # Delay slot
61214		 j     MainExit
61215	3:
61216		 sll   $7,$24,2         	 # Delay slot
61217		 addu  $7,$7,$30
61218		 lw    $7,0x00($7)
61219		 jr    $7
61220		 nop                    	 # Delay slot
61221
61222OP0_4639:				#:
61223		 addiu $23,$23,2
61224
61225		 lhu   $14,0x00($23)
61226		 lhu   $25,0x02($23)
61227		 sll   $14,$14,16
61228		 or    $14,$14,$25
61229		 addiu $23,$23,4
61230		 lw    $25,0x7C($21)
61231		 sw    $15,m68k_ICount
61232		 sw    $14,0x44($29)
61233		 or    $4,$0,$14
61234		 jalr  $25
61235		 sw    $23,0x4C($21)    	 # Delay slot
61236		 lw    $14,0x44($29)
61237		 lw    $15,m68k_ICount
61238		 seb   $2,$2
61239		 nor   $2,$0,$2
61240		 and   $16,$0,$0        	 # Clear Carry
61241		 and   $17,$0,$0        	 # Clear Overflow
61242		 slt   $19,$2,$0        	 # Set Sign
61243		 sltiu $18,$2,1         	 # Set Zero
61244		 lw    $25,0x88($21)
61245		 sw    $15,m68k_ICount
61246		 or    $5,$0,$2
61247		 or    $4,$0,$14
61248		 jalr  $25
61249		 sw    $23,0x4C($21)    	 # Delay slot
61250		 lw    $15,m68k_ICount
61251		 addiu $15,$15,-16
61252		 bgez  $15,3f
61253		 lhu   $24,0x00($23)    	 # Delay slot
61254		 j     MainExit
61255	3:
61256		 sll   $7,$24,2         	 # Delay slot
61257		 addu  $7,$7,$30
61258		 lw    $7,0x00($7)
61259		 jr    $7
61260		 nop                    	 # Delay slot
61261
61262OP0_4640:				#:
61263		 addiu $23,$23,2
61264
61265		 andi  $24,$24,0x07
61266		 sll   $24,$24,2
61267		 addu  $24,$24,$21
61268		 lh    $2,0x00($24)
61269		 nor   $2,$0,$2
61270		 and   $16,$0,$0        	 # Clear Carry
61271		 and   $17,$0,$0        	 # Clear Overflow
61272		 slt   $19,$2,$0        	 # Set Sign
61273		 sltiu $18,$2,1         	 # Set Zero
61274		 sh    $2,0x00($24)
61275		 addiu $15,$15,-4
61276		 bgez  $15,3f
61277		 lhu   $24,0x00($23)    	 # Delay slot
61278		 j     MainExit
61279	3:
61280		 sll   $7,$24,2         	 # Delay slot
61281		 addu  $7,$7,$30
61282		 lw    $7,0x00($7)
61283		 jr    $7
61284		 nop                    	 # Delay slot
61285
61286OP0_4650:				#:
61287		 addiu $23,$23,2
61288
61289		 andi  $24,$24,0x07
61290		 sll   $24,$24,2
61291		 addu  $24,$24,$21
61292		 lw    $14,0x20($24)
61293		 lw    $25,0x80($21)
61294		 sw    $15,m68k_ICount
61295		 sw    $14,0x44($29)
61296		 or    $4,$0,$14
61297		 jalr  $25
61298		 sw    $23,0x4C($21)    	 # Delay slot
61299		 lw    $14,0x44($29)
61300		 lw    $15,m68k_ICount
61301		 seh   $2,$2
61302		 nor   $2,$0,$2
61303		 and   $16,$0,$0        	 # Clear Carry
61304		 and   $17,$0,$0        	 # Clear Overflow
61305		 slt   $19,$2,$0        	 # Set Sign
61306		 sltiu $18,$2,1         	 # Set Zero
61307		 lw    $25,0x8C($21)
61308		 sw    $15,m68k_ICount
61309		 or    $5,$0,$2
61310		 or    $4,$0,$14
61311		 jalr  $25
61312		 sw    $23,0x4C($21)    	 # Delay slot
61313		 lw    $15,m68k_ICount
61314		 addiu $15,$15,-8
61315		 bgez  $15,3f
61316		 lhu   $24,0x00($23)    	 # Delay slot
61317		 j     MainExit
61318	3:
61319		 sll   $7,$24,2         	 # Delay slot
61320		 addu  $7,$7,$30
61321		 lw    $7,0x00($7)
61322		 jr    $7
61323		 nop                    	 # Delay slot
61324
61325OP0_4658:				#:
61326		 addiu $23,$23,2
61327
61328		 andi  $24,$24,0x07
61329		 sll   $24,$24,2
61330		 addu  $24,$24,$21
61331		 lw    $14,0x20($24)
61332		 addiu $25,$14,2
61333		 sw    $25,0x20($24)
61334		 lw    $25,0x80($21)
61335		 sw    $15,m68k_ICount
61336		 sw    $14,0x44($29)
61337		 or    $4,$0,$14
61338		 jalr  $25
61339		 sw    $23,0x4C($21)    	 # Delay slot
61340		 lw    $14,0x44($29)
61341		 lw    $15,m68k_ICount
61342		 seh   $2,$2
61343		 nor   $2,$0,$2
61344		 and   $16,$0,$0        	 # Clear Carry
61345		 and   $17,$0,$0        	 # Clear Overflow
61346		 slt   $19,$2,$0        	 # Set Sign
61347		 sltiu $18,$2,1         	 # Set Zero
61348		 lw    $25,0x8C($21)
61349		 sw    $15,m68k_ICount
61350		 or    $5,$0,$2
61351		 or    $4,$0,$14
61352		 jalr  $25
61353		 sw    $23,0x4C($21)    	 # Delay slot
61354		 lw    $15,m68k_ICount
61355		 addiu $15,$15,-8
61356		 bgez  $15,3f
61357		 lhu   $24,0x00($23)    	 # Delay slot
61358		 j     MainExit
61359	3:
61360		 sll   $7,$24,2         	 # Delay slot
61361		 addu  $7,$7,$30
61362		 lw    $7,0x00($7)
61363		 jr    $7
61364		 nop                    	 # Delay slot
61365
61366OP0_4660:				#:
61367		 addiu $23,$23,2
61368
61369		 andi  $24,$24,0x07
61370		 sll   $24,$24,2
61371		 addu  $24,$24,$21
61372		 lw    $14,0x20($24)
61373		 addiu $14,$14,-2
61374		 sw    $14,0x20($24)
61375		 lw    $25,0x80($21)
61376		 sw    $15,m68k_ICount
61377		 sw    $14,0x44($29)
61378		 or    $4,$0,$14
61379		 jalr  $25
61380		 sw    $23,0x4C($21)    	 # Delay slot
61381		 lw    $14,0x44($29)
61382		 lw    $15,m68k_ICount
61383		 seh   $2,$2
61384		 nor   $2,$0,$2
61385		 and   $16,$0,$0        	 # Clear Carry
61386		 and   $17,$0,$0        	 # Clear Overflow
61387		 slt   $19,$2,$0        	 # Set Sign
61388		 sltiu $18,$2,1         	 # Set Zero
61389		 lw    $25,0x8C($21)
61390		 sw    $15,m68k_ICount
61391		 or    $5,$0,$2
61392		 or    $4,$0,$14
61393		 jalr  $25
61394		 sw    $23,0x4C($21)    	 # Delay slot
61395		 lw    $15,m68k_ICount
61396		 addiu $15,$15,-10
61397		 bgez  $15,3f
61398		 lhu   $24,0x00($23)    	 # Delay slot
61399		 j     MainExit
61400	3:
61401		 sll   $7,$24,2         	 # Delay slot
61402		 addu  $7,$7,$30
61403		 lw    $7,0x00($7)
61404		 jr    $7
61405		 nop                    	 # Delay slot
61406
61407OP0_4668:				#:
61408		 addiu $23,$23,2
61409
61410		 andi  $24,$24,0x07
61411		 lh    $7,0x00($23)
61412		 sll   $24,$24,2
61413		 addu  $24,$24,$21
61414		 lw    $14,0x20($24)
61415		 addiu $23,$23,2
61416		 addu  $14,$14,$7
61417		 lw    $25,0x80($21)
61418		 sw    $15,m68k_ICount
61419		 sw    $14,0x44($29)
61420		 or    $4,$0,$14
61421		 jalr  $25
61422		 sw    $23,0x4C($21)    	 # Delay slot
61423		 lw    $14,0x44($29)
61424		 lw    $15,m68k_ICount
61425		 seh   $2,$2
61426		 nor   $2,$0,$2
61427		 and   $16,$0,$0        	 # Clear Carry
61428		 and   $17,$0,$0        	 # Clear Overflow
61429		 slt   $19,$2,$0        	 # Set Sign
61430		 sltiu $18,$2,1         	 # Set Zero
61431		 lw    $25,0x8C($21)
61432		 sw    $15,m68k_ICount
61433		 or    $5,$0,$2
61434		 or    $4,$0,$14
61435		 jalr  $25
61436		 sw    $23,0x4C($21)    	 # Delay slot
61437		 lw    $15,m68k_ICount
61438		 addiu $15,$15,-12
61439		 bgez  $15,3f
61440		 lhu   $24,0x00($23)    	 # Delay slot
61441		 j     MainExit
61442	3:
61443		 sll   $7,$24,2         	 # Delay slot
61444		 addu  $7,$7,$30
61445		 lw    $7,0x00($7)
61446		 jr    $7
61447		 nop                    	 # Delay slot
61448
61449OP0_4670:				#:
61450		 addiu $23,$23,2
61451
61452		 andi  $24,$24,0x07
61453		 sll   $24,$24,2
61454		 addu  $24,$24,$21
61455		 lw    $14,0x20($24)
61456		 lhu   $7,0x00($23)
61457		 addiu $23,$23,2
61458		 seb   $6,$7
61459		 or    $25,$0,$7
61460		 srl   $7,$7,12
61461		 andi  $25,$25,0x0800
61462		 sll   $7,$7,2
61463		 addu  $7,$7,$21
61464		 bne   $25,$0,0f
61465		 lw    $25,0x00($7)      	 # Delay slot
61466		 seh   $25,$25
61467	0:
61468		 addu  $25,$14,$25
61469		 addu  $14,$25,$6
61470		 lw    $25,0x80($21)
61471		 sw    $15,m68k_ICount
61472		 sw    $14,0x44($29)
61473		 or    $4,$0,$14
61474		 jalr  $25
61475		 sw    $23,0x4C($21)    	 # Delay slot
61476		 lw    $14,0x44($29)
61477		 lw    $15,m68k_ICount
61478		 seh   $2,$2
61479		 nor   $2,$0,$2
61480		 and   $16,$0,$0        	 # Clear Carry
61481		 and   $17,$0,$0        	 # Clear Overflow
61482		 slt   $19,$2,$0        	 # Set Sign
61483		 sltiu $18,$2,1         	 # Set Zero
61484		 lw    $25,0x8C($21)
61485		 sw    $15,m68k_ICount
61486		 or    $5,$0,$2
61487		 or    $4,$0,$14
61488		 jalr  $25
61489		 sw    $23,0x4C($21)    	 # Delay slot
61490		 lw    $15,m68k_ICount
61491		 addiu $15,$15,-14
61492		 bgez  $15,3f
61493		 lhu   $24,0x00($23)    	 # Delay slot
61494		 j     MainExit
61495	3:
61496		 sll   $7,$24,2         	 # Delay slot
61497		 addu  $7,$7,$30
61498		 lw    $7,0x00($7)
61499		 jr    $7
61500		 nop                    	 # Delay slot
61501
61502OP0_4678:				#:
61503		 addiu $23,$23,2
61504
61505		 lh    $14,0x00($23)
61506		 addiu $23,$23,2
61507		 lw    $25,0x80($21)
61508		 sw    $15,m68k_ICount
61509		 sw    $14,0x44($29)
61510		 or    $4,$0,$14
61511		 jalr  $25
61512		 sw    $23,0x4C($21)    	 # Delay slot
61513		 lw    $14,0x44($29)
61514		 lw    $15,m68k_ICount
61515		 seh   $2,$2
61516		 nor   $2,$0,$2
61517		 and   $16,$0,$0        	 # Clear Carry
61518		 and   $17,$0,$0        	 # Clear Overflow
61519		 slt   $19,$2,$0        	 # Set Sign
61520		 sltiu $18,$2,1         	 # Set Zero
61521		 lw    $25,0x8C($21)
61522		 sw    $15,m68k_ICount
61523		 or    $5,$0,$2
61524		 or    $4,$0,$14
61525		 jalr  $25
61526		 sw    $23,0x4C($21)    	 # Delay slot
61527		 lw    $15,m68k_ICount
61528		 addiu $15,$15,-12
61529		 bgez  $15,3f
61530		 lhu   $24,0x00($23)    	 # Delay slot
61531		 j     MainExit
61532	3:
61533		 sll   $7,$24,2         	 # Delay slot
61534		 addu  $7,$7,$30
61535		 lw    $7,0x00($7)
61536		 jr    $7
61537		 nop                    	 # Delay slot
61538
61539OP0_4679:				#:
61540		 addiu $23,$23,2
61541
61542		 lhu   $14,0x00($23)
61543		 lhu   $25,0x02($23)
61544		 sll   $14,$14,16
61545		 or    $14,$14,$25
61546		 addiu $23,$23,4
61547		 lw    $25,0x80($21)
61548		 sw    $15,m68k_ICount
61549		 sw    $14,0x44($29)
61550		 or    $4,$0,$14
61551		 jalr  $25
61552		 sw    $23,0x4C($21)    	 # Delay slot
61553		 lw    $14,0x44($29)
61554		 lw    $15,m68k_ICount
61555		 seh   $2,$2
61556		 nor   $2,$0,$2
61557		 and   $16,$0,$0        	 # Clear Carry
61558		 and   $17,$0,$0        	 # Clear Overflow
61559		 slt   $19,$2,$0        	 # Set Sign
61560		 sltiu $18,$2,1         	 # Set Zero
61561		 lw    $25,0x8C($21)
61562		 sw    $15,m68k_ICount
61563		 or    $5,$0,$2
61564		 or    $4,$0,$14
61565		 jalr  $25
61566		 sw    $23,0x4C($21)    	 # Delay slot
61567		 lw    $15,m68k_ICount
61568		 addiu $15,$15,-16
61569		 bgez  $15,3f
61570		 lhu   $24,0x00($23)    	 # Delay slot
61571		 j     MainExit
61572	3:
61573		 sll   $7,$24,2         	 # Delay slot
61574		 addu  $7,$7,$30
61575		 lw    $7,0x00($7)
61576		 jr    $7
61577		 nop                    	 # Delay slot
61578
61579OP0_4680:				#:
61580		 addiu $23,$23,2
61581
61582		 andi  $24,$24,0x07
61583		 sll   $24,$24,2
61584		 addu  $24,$24,$21
61585		 lw    $2,0x00($24)
61586		 nor   $2,$0,$2
61587		 and   $16,$0,$0        	 # Clear Carry
61588		 and   $17,$0,$0        	 # Clear Overflow
61589		 slt   $19,$2,$0        	 # Set Sign
61590		 sltiu $18,$2,1         	 # Set Zero
61591		 sw    $2,0x00($24)
61592		 addiu $15,$15,-6
61593		 bgez  $15,3f
61594		 lhu   $24,0x00($23)    	 # Delay slot
61595		 j     MainExit
61596	3:
61597		 sll   $7,$24,2         	 # Delay slot
61598		 addu  $7,$7,$30
61599		 lw    $7,0x00($7)
61600		 jr    $7
61601		 nop                    	 # Delay slot
61602
61603OP0_4690:				#:
61604		 addiu $23,$23,2
61605
61606		 andi  $24,$24,0x07
61607		 sll   $24,$24,2
61608		 addu  $24,$24,$21
61609		 lw    $14,0x20($24)
61610		 lw    $25,0x84($21)
61611		 sw    $15,m68k_ICount
61612		 sw    $14,0x44($29)
61613		 or    $4,$0,$14
61614		 jalr  $25
61615		 sw    $23,0x4C($21)    	 # Delay slot
61616		 lw    $14,0x44($29)
61617		 lw    $15,m68k_ICount
61618		 nor   $2,$0,$2
61619		 and   $16,$0,$0        	 # Clear Carry
61620		 and   $17,$0,$0        	 # Clear Overflow
61621		 slt   $19,$2,$0        	 # Set Sign
61622		 sltiu $18,$2,1         	 # Set Zero
61623		 lw    $25,0x90($21)
61624		 sw    $15,m68k_ICount
61625		 or    $5,$0,$2
61626		 or    $4,$0,$14
61627		 jalr  $25
61628		 sw    $23,0x4C($21)    	 # Delay slot
61629		 lw    $15,m68k_ICount
61630		 addiu $15,$15,-14
61631		 bgez  $15,3f
61632		 lhu   $24,0x00($23)    	 # Delay slot
61633		 j     MainExit
61634	3:
61635		 sll   $7,$24,2         	 # Delay slot
61636		 addu  $7,$7,$30
61637		 lw    $7,0x00($7)
61638		 jr    $7
61639		 nop                    	 # Delay slot
61640
61641OP0_4698:				#:
61642		 addiu $23,$23,2
61643
61644		 andi  $24,$24,0x07
61645		 sll   $24,$24,2
61646		 addu  $24,$24,$21
61647		 lw    $14,0x20($24)
61648		 addiu $25,$14,4
61649		 sw    $25,0x20($24)
61650		 lw    $25,0x84($21)
61651		 sw    $15,m68k_ICount
61652		 sw    $14,0x44($29)
61653		 or    $4,$0,$14
61654		 jalr  $25
61655		 sw    $23,0x4C($21)    	 # Delay slot
61656		 lw    $14,0x44($29)
61657		 lw    $15,m68k_ICount
61658		 nor   $2,$0,$2
61659		 and   $16,$0,$0        	 # Clear Carry
61660		 and   $17,$0,$0        	 # Clear Overflow
61661		 slt   $19,$2,$0        	 # Set Sign
61662		 sltiu $18,$2,1         	 # Set Zero
61663		 lw    $25,0x90($21)
61664		 sw    $15,m68k_ICount
61665		 or    $5,$0,$2
61666		 or    $4,$0,$14
61667		 jalr  $25
61668		 sw    $23,0x4C($21)    	 # Delay slot
61669		 lw    $15,m68k_ICount
61670		 addiu $15,$15,-14
61671		 bgez  $15,3f
61672		 lhu   $24,0x00($23)    	 # Delay slot
61673		 j     MainExit
61674	3:
61675		 sll   $7,$24,2         	 # Delay slot
61676		 addu  $7,$7,$30
61677		 lw    $7,0x00($7)
61678		 jr    $7
61679		 nop                    	 # Delay slot
61680
61681OP0_46a0:				#:
61682		 addiu $23,$23,2
61683
61684		 andi  $24,$24,0x07
61685		 sll   $24,$24,2
61686		 addu  $24,$24,$21
61687		 lw    $14,0x20($24)
61688		 addiu $14,$14,-4
61689		 sw    $14,0x20($24)
61690		 lw    $25,0x84($21)
61691		 sw    $15,m68k_ICount
61692		 sw    $14,0x44($29)
61693		 or    $4,$0,$14
61694		 jalr  $25
61695		 sw    $23,0x4C($21)    	 # Delay slot
61696		 lw    $14,0x44($29)
61697		 lw    $15,m68k_ICount
61698		 nor   $2,$0,$2
61699		 and   $16,$0,$0        	 # Clear Carry
61700		 and   $17,$0,$0        	 # Clear Overflow
61701		 slt   $19,$2,$0        	 # Set Sign
61702		 sltiu $18,$2,1         	 # Set Zero
61703		 lw    $25,0x90($21)
61704		 sw    $15,m68k_ICount
61705		 or    $5,$0,$2
61706		 or    $4,$0,$14
61707		 jalr  $25
61708		 sw    $23,0x4C($21)    	 # Delay slot
61709		 lw    $15,m68k_ICount
61710		 addiu $15,$15,-16
61711		 bgez  $15,3f
61712		 lhu   $24,0x00($23)    	 # Delay slot
61713		 j     MainExit
61714	3:
61715		 sll   $7,$24,2         	 # Delay slot
61716		 addu  $7,$7,$30
61717		 lw    $7,0x00($7)
61718		 jr    $7
61719		 nop                    	 # Delay slot
61720
61721OP0_46a8:				#:
61722		 addiu $23,$23,2
61723
61724		 andi  $24,$24,0x07
61725		 lh    $7,0x00($23)
61726		 sll   $24,$24,2
61727		 addu  $24,$24,$21
61728		 lw    $14,0x20($24)
61729		 addiu $23,$23,2
61730		 addu  $14,$14,$7
61731		 lw    $25,0x84($21)
61732		 sw    $15,m68k_ICount
61733		 sw    $14,0x44($29)
61734		 or    $4,$0,$14
61735		 jalr  $25
61736		 sw    $23,0x4C($21)    	 # Delay slot
61737		 lw    $14,0x44($29)
61738		 lw    $15,m68k_ICount
61739		 nor   $2,$0,$2
61740		 and   $16,$0,$0        	 # Clear Carry
61741		 and   $17,$0,$0        	 # Clear Overflow
61742		 slt   $19,$2,$0        	 # Set Sign
61743		 sltiu $18,$2,1         	 # Set Zero
61744		 lw    $25,0x90($21)
61745		 sw    $15,m68k_ICount
61746		 or    $5,$0,$2
61747		 or    $4,$0,$14
61748		 jalr  $25
61749		 sw    $23,0x4C($21)    	 # Delay slot
61750		 lw    $15,m68k_ICount
61751		 addiu $15,$15,-18
61752		 bgez  $15,3f
61753		 lhu   $24,0x00($23)    	 # Delay slot
61754		 j     MainExit
61755	3:
61756		 sll   $7,$24,2         	 # Delay slot
61757		 addu  $7,$7,$30
61758		 lw    $7,0x00($7)
61759		 jr    $7
61760		 nop                    	 # Delay slot
61761
61762OP0_46b0:				#:
61763		 addiu $23,$23,2
61764
61765		 andi  $24,$24,0x07
61766		 sll   $24,$24,2
61767		 addu  $24,$24,$21
61768		 lw    $14,0x20($24)
61769		 lhu   $7,0x00($23)
61770		 addiu $23,$23,2
61771		 seb   $6,$7
61772		 or    $25,$0,$7
61773		 srl   $7,$7,12
61774		 andi  $25,$25,0x0800
61775		 sll   $7,$7,2
61776		 addu  $7,$7,$21
61777		 bne   $25,$0,0f
61778		 lw    $25,0x00($7)      	 # Delay slot
61779		 seh   $25,$25
61780	0:
61781		 addu  $25,$14,$25
61782		 addu  $14,$25,$6
61783		 lw    $25,0x84($21)
61784		 sw    $15,m68k_ICount
61785		 sw    $14,0x44($29)
61786		 or    $4,$0,$14
61787		 jalr  $25
61788		 sw    $23,0x4C($21)    	 # Delay slot
61789		 lw    $14,0x44($29)
61790		 lw    $15,m68k_ICount
61791		 nor   $2,$0,$2
61792		 and   $16,$0,$0        	 # Clear Carry
61793		 and   $17,$0,$0        	 # Clear Overflow
61794		 slt   $19,$2,$0        	 # Set Sign
61795		 sltiu $18,$2,1         	 # Set Zero
61796		 lw    $25,0x90($21)
61797		 sw    $15,m68k_ICount
61798		 or    $5,$0,$2
61799		 or    $4,$0,$14
61800		 jalr  $25
61801		 sw    $23,0x4C($21)    	 # Delay slot
61802		 lw    $15,m68k_ICount
61803		 addiu $15,$15,-20
61804		 bgez  $15,3f
61805		 lhu   $24,0x00($23)    	 # Delay slot
61806		 j     MainExit
61807	3:
61808		 sll   $7,$24,2         	 # Delay slot
61809		 addu  $7,$7,$30
61810		 lw    $7,0x00($7)
61811		 jr    $7
61812		 nop                    	 # Delay slot
61813
61814OP0_46b8:				#:
61815		 addiu $23,$23,2
61816
61817		 lh    $14,0x00($23)
61818		 addiu $23,$23,2
61819		 lw    $25,0x84($21)
61820		 sw    $15,m68k_ICount
61821		 sw    $14,0x44($29)
61822		 or    $4,$0,$14
61823		 jalr  $25
61824		 sw    $23,0x4C($21)    	 # Delay slot
61825		 lw    $14,0x44($29)
61826		 lw    $15,m68k_ICount
61827		 nor   $2,$0,$2
61828		 and   $16,$0,$0        	 # Clear Carry
61829		 and   $17,$0,$0        	 # Clear Overflow
61830		 slt   $19,$2,$0        	 # Set Sign
61831		 sltiu $18,$2,1         	 # Set Zero
61832		 lw    $25,0x90($21)
61833		 sw    $15,m68k_ICount
61834		 or    $5,$0,$2
61835		 or    $4,$0,$14
61836		 jalr  $25
61837		 sw    $23,0x4C($21)    	 # Delay slot
61838		 lw    $15,m68k_ICount
61839		 addiu $15,$15,-18
61840		 bgez  $15,3f
61841		 lhu   $24,0x00($23)    	 # Delay slot
61842		 j     MainExit
61843	3:
61844		 sll   $7,$24,2         	 # Delay slot
61845		 addu  $7,$7,$30
61846		 lw    $7,0x00($7)
61847		 jr    $7
61848		 nop                    	 # Delay slot
61849
61850OP0_46b9:				#:
61851		 addiu $23,$23,2
61852
61853		 lhu   $14,0x00($23)
61854		 lhu   $25,0x02($23)
61855		 sll   $14,$14,16
61856		 or    $14,$14,$25
61857		 addiu $23,$23,4
61858		 lw    $25,0x84($21)
61859		 sw    $15,m68k_ICount
61860		 sw    $14,0x44($29)
61861		 or    $4,$0,$14
61862		 jalr  $25
61863		 sw    $23,0x4C($21)    	 # Delay slot
61864		 lw    $14,0x44($29)
61865		 lw    $15,m68k_ICount
61866		 nor   $2,$0,$2
61867		 and   $16,$0,$0        	 # Clear Carry
61868		 and   $17,$0,$0        	 # Clear Overflow
61869		 slt   $19,$2,$0        	 # Set Sign
61870		 sltiu $18,$2,1         	 # Set Zero
61871		 lw    $25,0x90($21)
61872		 sw    $15,m68k_ICount
61873		 or    $5,$0,$2
61874		 or    $4,$0,$14
61875		 jalr  $25
61876		 sw    $23,0x4C($21)    	 # Delay slot
61877		 lw    $15,m68k_ICount
61878		 addiu $15,$15,-22
61879		 bgez  $15,3f
61880		 lhu   $24,0x00($23)    	 # Delay slot
61881		 j     MainExit
61882	3:
61883		 sll   $7,$24,2         	 # Delay slot
61884		 addu  $7,$7,$30
61885		 lw    $7,0x00($7)
61886		 jr    $7
61887		 nop                    	 # Delay slot
61888
61889OP0_4e60:				#
61890		 lbu   $8,0x44($21)
61891		 andi  $8,$8,0x20       	 # Supervisor Mode ?
61892		 beq   $8,$0,9f
61893		 addiu $23,$23,2        	 # Delay slot
61894
61895		 andi  $8,$24,0x07
61896		 sll   $8,$8,2
61897		 addu  $8,$8,$21
61898		 lw    $2,0x20($8)
61899		 sw    $2,0x68($21)
61900		 addiu $15,$15,-4
61901		 bgez  $15,3f
61902		 lhu   $24,0x00($23)    	 # Delay slot
61903		 j     MainExit
61904	3:
61905		 sll   $7,$24,2         	 # Delay slot
61906		 addu  $7,$7,$30
61907		 lw    $7,0x00($7)
61908		 jr    $7
61909		 nop                    	 # Delay slot
61910
61911	9:
61912		 addiu $23,$23,-2
61913		 jal   Exception
61914		 ori   $2,$0,8
61915
61916		 addiu $15,$15,-4
61917		 bgez  $15,3f
61918		 lhu   $24,0x00($23)    	 # Delay slot
61919		 j     MainExit
61920	3:
61921		 sll   $7,$24,2         	 # Delay slot
61922		 addu  $7,$7,$30
61923		 lw    $7,0x00($7)
61924		 jr    $7
61925		 nop                    	 # Delay slot
61926
61927OP0_4e68:				#
61928		 lbu   $8,0x44($21)
61929		 andi  $8,$8,0x20       	 # Supervisor Mode ?
61930		 beq   $8,$0,9f
61931		 addiu $23,$23,2        	 # Delay slot
61932
61933		 andi  $8,$24,0x07
61934		 sll   $8,$8,2
61935		 addu  $8,$8,$21
61936		 lw    $2,0x68($21)
61937		 sw    $2,0x20($8)
61938		 addiu $15,$15,-4
61939		 bgez  $15,3f
61940		 lhu   $24,0x00($23)    	 # Delay slot
61941		 j     MainExit
61942	3:
61943		 sll   $7,$24,2         	 # Delay slot
61944		 addu  $7,$7,$30
61945		 lw    $7,0x00($7)
61946		 jr    $7
61947		 nop                    	 # Delay slot
61948
61949	9:
61950		 addiu $23,$23,-2
61951		 jal   Exception
61952		 ori   $2,$0,8
61953
61954		 addiu $15,$15,-4
61955		 bgez  $15,3f
61956		 lhu   $24,0x00($23)    	 # Delay slot
61957		 j     MainExit
61958	3:
61959		 sll   $7,$24,2         	 # Delay slot
61960		 addu  $7,$7,$30
61961		 lw    $7,0x00($7)
61962		 jr    $7
61963		 nop                    	 # Delay slot
61964
61965OP0_4180:				#:
61966		 addiu $23,$23,2
61967
61968		 srl   $8,$24,7
61969		 andi  $8,$8,0x1C
61970		 addu  $8,$8,$21
61971		 andi  $24,$24,0x07
61972		 lh    $8,0x00($8)
61973		 sll   $24,$24,2
61974		 addu  $24,$24,$21
61975		 lh    $2,0x00($24)
61976		 and   $16,$0,$0
61977		 and   $17,$0,$0
61978		 sltiu $18,$8,1
61979		 slt   $19,$8,$0
61980		 bne   $19,$0,8f
61981		 slt   $8,$2,$8         	 # Delay slot
61982		 bne   $8,$0,9f
61983		 nop                    	 # Delay slot
61984		 addiu $15,$15,-10
61985		 bgez  $15,3f
61986		 lhu   $24,0x00($23)    	 # Delay slot
61987		 j     MainExit
61988	3:
61989		 sll   $7,$24,2         	 # Delay slot
61990		 addu  $7,$7,$30
61991		 lw    $7,0x00($7)
61992		 jr    $7
61993		 nop                    	 # Delay slot
61994
61995	9:
61996		 and   $19,$0,$0
61997	8:
61998		 jal   Exception
61999		 ori   $2,$0,6          	 # Delay slot
62000
62001		 addiu $15,$15,-10
62002		 bgez  $15,3f
62003		 lhu   $24,0x00($23)    	 # Delay slot
62004		 j     MainExit
62005	3:
62006		 sll   $7,$24,2         	 # Delay slot
62007		 addu  $7,$7,$30
62008		 lw    $7,0x00($7)
62009		 jr    $7
62010		 nop                    	 # Delay slot
62011
62012OP0_4190:				#:
62013		 addiu $23,$23,2
62014
62015		 srl   $8,$24,7
62016		 andi  $8,$8,0x1C
62017		 addu  $8,$8,$21
62018		 andi  $24,$24,0x07
62019		 lh    $8,0x00($8)
62020		 sll   $24,$24,2
62021		 addu  $24,$24,$21
62022		 lw    $14,0x20($24)
62023		 lw    $25,0x80($21)
62024		 sw    $15,m68k_ICount
62025		 sw    $8,0x44($29)
62026		 or    $4,$0,$14
62027		 jalr  $25
62028		 sw    $23,0x4C($21)    	 # Delay slot
62029		 lw    $8,0x44($29)
62030		 lw    $15,m68k_ICount
62031		 seh   $2,$2
62032		 and   $16,$0,$0
62033		 and   $17,$0,$0
62034		 sltiu $18,$8,1
62035		 slt   $19,$8,$0
62036		 bne   $19,$0,8f
62037		 slt   $8,$2,$8         	 # Delay slot
62038		 bne   $8,$0,9f
62039		 nop                    	 # Delay slot
62040		 addiu $15,$15,-14
62041		 bgez  $15,3f
62042		 lhu   $24,0x00($23)    	 # Delay slot
62043		 j     MainExit
62044	3:
62045		 sll   $7,$24,2         	 # Delay slot
62046		 addu  $7,$7,$30
62047		 lw    $7,0x00($7)
62048		 jr    $7
62049		 nop                    	 # Delay slot
62050
62051	9:
62052		 and   $19,$0,$0
62053	8:
62054		 jal   Exception
62055		 ori   $2,$0,6          	 # Delay slot
62056
62057		 addiu $15,$15,-14
62058		 bgez  $15,3f
62059		 lhu   $24,0x00($23)    	 # Delay slot
62060		 j     MainExit
62061	3:
62062		 sll   $7,$24,2         	 # Delay slot
62063		 addu  $7,$7,$30
62064		 lw    $7,0x00($7)
62065		 jr    $7
62066		 nop                    	 # Delay slot
62067
62068OP0_4198:				#:
62069		 addiu $23,$23,2
62070
62071		 srl   $8,$24,7
62072		 andi  $8,$8,0x1C
62073		 addu  $8,$8,$21
62074		 andi  $24,$24,0x07
62075		 lh    $8,0x00($8)
62076		 sll   $24,$24,2
62077		 addu  $24,$24,$21
62078		 lw    $14,0x20($24)
62079		 addiu $25,$14,2
62080		 sw    $25,0x20($24)
62081		 lw    $25,0x80($21)
62082		 sw    $15,m68k_ICount
62083		 sw    $8,0x44($29)
62084		 or    $4,$0,$14
62085		 jalr  $25
62086		 sw    $23,0x4C($21)    	 # Delay slot
62087		 lw    $8,0x44($29)
62088		 lw    $15,m68k_ICount
62089		 seh   $2,$2
62090		 and   $16,$0,$0
62091		 and   $17,$0,$0
62092		 sltiu $18,$8,1
62093		 slt   $19,$8,$0
62094		 bne   $19,$0,8f
62095		 slt   $8,$2,$8         	 # Delay slot
62096		 bne   $8,$0,9f
62097		 nop                    	 # Delay slot
62098		 addiu $15,$15,-14
62099		 bgez  $15,3f
62100		 lhu   $24,0x00($23)    	 # Delay slot
62101		 j     MainExit
62102	3:
62103		 sll   $7,$24,2         	 # Delay slot
62104		 addu  $7,$7,$30
62105		 lw    $7,0x00($7)
62106		 jr    $7
62107		 nop                    	 # Delay slot
62108
62109	9:
62110		 and   $19,$0,$0
62111	8:
62112		 jal   Exception
62113		 ori   $2,$0,6          	 # Delay slot
62114
62115		 addiu $15,$15,-14
62116		 bgez  $15,3f
62117		 lhu   $24,0x00($23)    	 # Delay slot
62118		 j     MainExit
62119	3:
62120		 sll   $7,$24,2         	 # Delay slot
62121		 addu  $7,$7,$30
62122		 lw    $7,0x00($7)
62123		 jr    $7
62124		 nop                    	 # Delay slot
62125
62126OP0_41a0:				#:
62127		 addiu $23,$23,2
62128
62129		 srl   $8,$24,7
62130		 andi  $8,$8,0x1C
62131		 addu  $8,$8,$21
62132		 andi  $24,$24,0x07
62133		 lh    $8,0x00($8)
62134		 sll   $24,$24,2
62135		 addu  $24,$24,$21
62136		 lw    $14,0x20($24)
62137		 addiu $14,$14,-2
62138		 sw    $14,0x20($24)
62139		 lw    $25,0x80($21)
62140		 sw    $15,m68k_ICount
62141		 sw    $8,0x44($29)
62142		 or    $4,$0,$14
62143		 jalr  $25
62144		 sw    $23,0x4C($21)    	 # Delay slot
62145		 lw    $8,0x44($29)
62146		 lw    $15,m68k_ICount
62147		 seh   $2,$2
62148		 and   $16,$0,$0
62149		 and   $17,$0,$0
62150		 sltiu $18,$8,1
62151		 slt   $19,$8,$0
62152		 bne   $19,$0,8f
62153		 slt   $8,$2,$8         	 # Delay slot
62154		 bne   $8,$0,9f
62155		 nop                    	 # Delay slot
62156		 addiu $15,$15,-16
62157		 bgez  $15,3f
62158		 lhu   $24,0x00($23)    	 # Delay slot
62159		 j     MainExit
62160	3:
62161		 sll   $7,$24,2         	 # Delay slot
62162		 addu  $7,$7,$30
62163		 lw    $7,0x00($7)
62164		 jr    $7
62165		 nop                    	 # Delay slot
62166
62167	9:
62168		 and   $19,$0,$0
62169	8:
62170		 jal   Exception
62171		 ori   $2,$0,6          	 # Delay slot
62172
62173		 addiu $15,$15,-16
62174		 bgez  $15,3f
62175		 lhu   $24,0x00($23)    	 # Delay slot
62176		 j     MainExit
62177	3:
62178		 sll   $7,$24,2         	 # Delay slot
62179		 addu  $7,$7,$30
62180		 lw    $7,0x00($7)
62181		 jr    $7
62182		 nop                    	 # Delay slot
62183
62184OP0_41a8:				#:
62185		 addiu $23,$23,2
62186
62187		 srl   $8,$24,7
62188		 andi  $8,$8,0x1C
62189		 addu  $8,$8,$21
62190		 andi  $24,$24,0x07
62191		 lh    $8,0x00($8)
62192		 lh    $7,0x00($23)
62193		 sll   $24,$24,2
62194		 addu  $24,$24,$21
62195		 lw    $14,0x20($24)
62196		 addiu $23,$23,2
62197		 addu  $14,$14,$7
62198		 lw    $25,0x80($21)
62199		 sw    $15,m68k_ICount
62200		 sw    $8,0x44($29)
62201		 or    $4,$0,$14
62202		 jalr  $25
62203		 sw    $23,0x4C($21)    	 # Delay slot
62204		 lw    $8,0x44($29)
62205		 lw    $15,m68k_ICount
62206		 seh   $2,$2
62207		 and   $16,$0,$0
62208		 and   $17,$0,$0
62209		 sltiu $18,$8,1
62210		 slt   $19,$8,$0
62211		 bne   $19,$0,8f
62212		 slt   $8,$2,$8         	 # Delay slot
62213		 bne   $8,$0,9f
62214		 nop                    	 # Delay slot
62215		 addiu $15,$15,-18
62216		 bgez  $15,3f
62217		 lhu   $24,0x00($23)    	 # Delay slot
62218		 j     MainExit
62219	3:
62220		 sll   $7,$24,2         	 # Delay slot
62221		 addu  $7,$7,$30
62222		 lw    $7,0x00($7)
62223		 jr    $7
62224		 nop                    	 # Delay slot
62225
62226	9:
62227		 and   $19,$0,$0
62228	8:
62229		 jal   Exception
62230		 ori   $2,$0,6          	 # Delay slot
62231
62232		 addiu $15,$15,-18
62233		 bgez  $15,3f
62234		 lhu   $24,0x00($23)    	 # Delay slot
62235		 j     MainExit
62236	3:
62237		 sll   $7,$24,2         	 # Delay slot
62238		 addu  $7,$7,$30
62239		 lw    $7,0x00($7)
62240		 jr    $7
62241		 nop                    	 # Delay slot
62242
62243OP0_41b0:				#:
62244		 addiu $23,$23,2
62245
62246		 srl   $8,$24,7
62247		 andi  $8,$8,0x1C
62248		 addu  $8,$8,$21
62249		 andi  $24,$24,0x07
62250		 lh    $8,0x00($8)
62251		 sll   $24,$24,2
62252		 addu  $24,$24,$21
62253		 lw    $14,0x20($24)
62254		 lhu   $7,0x00($23)
62255		 addiu $23,$23,2
62256		 seb   $6,$7
62257		 or    $25,$0,$7
62258		 srl   $7,$7,12
62259		 andi  $25,$25,0x0800
62260		 sll   $7,$7,2
62261		 addu  $7,$7,$21
62262		 bne   $25,$0,0f
62263		 lw    $25,0x00($7)      	 # Delay slot
62264		 seh   $25,$25
62265	0:
62266		 addu  $25,$14,$25
62267		 addu  $14,$25,$6
62268		 lw    $25,0x80($21)
62269		 sw    $15,m68k_ICount
62270		 sw    $8,0x44($29)
62271		 or    $4,$0,$14
62272		 jalr  $25
62273		 sw    $23,0x4C($21)    	 # Delay slot
62274		 lw    $8,0x44($29)
62275		 lw    $15,m68k_ICount
62276		 seh   $2,$2
62277		 and   $16,$0,$0
62278		 and   $17,$0,$0
62279		 sltiu $18,$8,1
62280		 slt   $19,$8,$0
62281		 bne   $19,$0,8f
62282		 slt   $8,$2,$8         	 # Delay slot
62283		 bne   $8,$0,9f
62284		 nop                    	 # Delay slot
62285		 addiu $15,$15,-20
62286		 bgez  $15,3f
62287		 lhu   $24,0x00($23)    	 # Delay slot
62288		 j     MainExit
62289	3:
62290		 sll   $7,$24,2         	 # Delay slot
62291		 addu  $7,$7,$30
62292		 lw    $7,0x00($7)
62293		 jr    $7
62294		 nop                    	 # Delay slot
62295
62296	9:
62297		 and   $19,$0,$0
62298	8:
62299		 jal   Exception
62300		 ori   $2,$0,6          	 # Delay slot
62301
62302		 addiu $15,$15,-20
62303		 bgez  $15,3f
62304		 lhu   $24,0x00($23)    	 # Delay slot
62305		 j     MainExit
62306	3:
62307		 sll   $7,$24,2         	 # Delay slot
62308		 addu  $7,$7,$30
62309		 lw    $7,0x00($7)
62310		 jr    $7
62311		 nop                    	 # Delay slot
62312
62313OP0_41b8:				#:
62314		 addiu $23,$23,2
62315
62316		 srl   $24,$24,7
62317		 andi  $24,$24,0x1C
62318		 addu  $24,$24,$21
62319		 lh    $24,0x00($24)
62320		 lh    $14,0x00($23)
62321		 addiu $23,$23,2
62322		 lw    $25,0x80($21)
62323		 sw    $15,m68k_ICount
62324		 or    $4,$0,$14
62325		 jalr  $25
62326		 sw    $23,0x4C($21)    	 # Delay slot
62327		 lw    $15,m68k_ICount
62328		 seh   $2,$2
62329		 and   $16,$0,$0
62330		 and   $17,$0,$0
62331		 sltiu $18,$24,1
62332		 slt   $19,$24,$0
62333		 bne   $19,$0,8f
62334		 slt   $8,$2,$24         	 # Delay slot
62335		 bne   $8,$0,9f
62336		 nop                    	 # Delay slot
62337		 addiu $15,$15,-18
62338		 bgez  $15,3f
62339		 lhu   $24,0x00($23)    	 # Delay slot
62340		 j     MainExit
62341	3:
62342		 sll   $7,$24,2         	 # Delay slot
62343		 addu  $7,$7,$30
62344		 lw    $7,0x00($7)
62345		 jr    $7
62346		 nop                    	 # Delay slot
62347
62348	9:
62349		 and   $19,$0,$0
62350	8:
62351		 jal   Exception
62352		 ori   $2,$0,6          	 # Delay slot
62353
62354		 addiu $15,$15,-18
62355		 bgez  $15,3f
62356		 lhu   $24,0x00($23)    	 # Delay slot
62357		 j     MainExit
62358	3:
62359		 sll   $7,$24,2         	 # Delay slot
62360		 addu  $7,$7,$30
62361		 lw    $7,0x00($7)
62362		 jr    $7
62363		 nop                    	 # Delay slot
62364
62365OP0_41b9:				#:
62366		 addiu $23,$23,2
62367
62368		 srl   $24,$24,7
62369		 andi  $24,$24,0x1C
62370		 addu  $24,$24,$21
62371		 lh    $24,0x00($24)
62372		 lhu   $14,0x00($23)
62373		 lhu   $25,0x02($23)
62374		 sll   $14,$14,16
62375		 or    $14,$14,$25
62376		 addiu $23,$23,4
62377		 lw    $25,0x80($21)
62378		 sw    $15,m68k_ICount
62379		 or    $4,$0,$14
62380		 jalr  $25
62381		 sw    $23,0x4C($21)    	 # Delay slot
62382		 lw    $15,m68k_ICount
62383		 seh   $2,$2
62384		 and   $16,$0,$0
62385		 and   $17,$0,$0
62386		 sltiu $18,$24,1
62387		 slt   $19,$24,$0
62388		 bne   $19,$0,8f
62389		 slt   $8,$2,$24         	 # Delay slot
62390		 bne   $8,$0,9f
62391		 nop                    	 # Delay slot
62392		 addiu $15,$15,-22
62393		 bgez  $15,3f
62394		 lhu   $24,0x00($23)    	 # Delay slot
62395		 j     MainExit
62396	3:
62397		 sll   $7,$24,2         	 # Delay slot
62398		 addu  $7,$7,$30
62399		 lw    $7,0x00($7)
62400		 jr    $7
62401		 nop                    	 # Delay slot
62402
62403	9:
62404		 and   $19,$0,$0
62405	8:
62406		 jal   Exception
62407		 ori   $2,$0,6          	 # Delay slot
62408
62409		 addiu $15,$15,-22
62410		 bgez  $15,3f
62411		 lhu   $24,0x00($23)    	 # Delay slot
62412		 j     MainExit
62413	3:
62414		 sll   $7,$24,2         	 # Delay slot
62415		 addu  $7,$7,$30
62416		 lw    $7,0x00($7)
62417		 jr    $7
62418		 nop                    	 # Delay slot
62419
62420OP0_41ba:				#:
62421		 addiu $23,$23,2
62422
62423		 srl   $24,$24,7
62424		 andi  $24,$24,0x1C
62425		 addu  $24,$24,$21
62426		 lh    $24,0x00($24)
62427		 lh    $7,0x00($23)
62428		 subu  $25,$23,$22
62429		 addu  $14,$25,$7       	 # Add Offset to PC
62430		 addiu $23,$23,2
62431		 lw    $25,0x9C($21)
62432		 sw    $15,m68k_ICount
62433		 or    $4,$0,$14
62434		 jalr  $25
62435		 sw    $23,0x4C($21)    	 # Delay slot
62436		 lw    $15,m68k_ICount
62437		 seh   $2,$2
62438		 and   $16,$0,$0
62439		 and   $17,$0,$0
62440		 sltiu $18,$24,1
62441		 slt   $19,$24,$0
62442		 bne   $19,$0,8f
62443		 slt   $8,$2,$24         	 # Delay slot
62444		 bne   $8,$0,9f
62445		 nop                    	 # Delay slot
62446		 addiu $15,$15,-18
62447		 bgez  $15,3f
62448		 lhu   $24,0x00($23)    	 # Delay slot
62449		 j     MainExit
62450	3:
62451		 sll   $7,$24,2         	 # Delay slot
62452		 addu  $7,$7,$30
62453		 lw    $7,0x00($7)
62454		 jr    $7
62455		 nop                    	 # Delay slot
62456
62457	9:
62458		 and   $19,$0,$0
62459	8:
62460		 jal   Exception
62461		 ori   $2,$0,6          	 # Delay slot
62462
62463		 addiu $15,$15,-18
62464		 bgez  $15,3f
62465		 lhu   $24,0x00($23)    	 # Delay slot
62466		 j     MainExit
62467	3:
62468		 sll   $7,$24,2         	 # Delay slot
62469		 addu  $7,$7,$30
62470		 lw    $7,0x00($7)
62471		 jr    $7
62472		 nop                    	 # Delay slot
62473
62474OP0_41bb:				#:
62475		 addiu $23,$23,2
62476
62477		 srl   $24,$24,7
62478		 andi  $24,$24,0x1C
62479		 addu  $24,$24,$21
62480		 lh    $24,0x00($24)
62481		 subu  $14,$23,$22       	 # Get PC
62482		 lhu   $7,0x00($23)
62483		 addiu $23,$23,2
62484		 seb   $6,$7
62485		 or    $25,$0,$7
62486		 srl   $7,$7,12
62487		 andi  $25,$25,0x0800
62488		 sll   $7,$7,2
62489		 addu  $7,$7,$21
62490		 bne   $25,$0,0f
62491		 lw    $25,0x00($7)      	 # Delay slot
62492		 seh   $25,$25
62493	0:
62494		 addu  $25,$14,$25
62495		 addu  $14,$25,$6
62496		 lw    $25,0x9C($21)
62497		 sw    $15,m68k_ICount
62498		 or    $4,$0,$14
62499		 jalr  $25
62500		 sw    $23,0x4C($21)    	 # Delay slot
62501		 lw    $15,m68k_ICount
62502		 seh   $2,$2
62503		 and   $16,$0,$0
62504		 and   $17,$0,$0
62505		 sltiu $18,$24,1
62506		 slt   $19,$24,$0
62507		 bne   $19,$0,8f
62508		 slt   $8,$2,$24         	 # Delay slot
62509		 bne   $8,$0,9f
62510		 nop                    	 # Delay slot
62511		 addiu $15,$15,-20
62512		 bgez  $15,3f
62513		 lhu   $24,0x00($23)    	 # Delay slot
62514		 j     MainExit
62515	3:
62516		 sll   $7,$24,2         	 # Delay slot
62517		 addu  $7,$7,$30
62518		 lw    $7,0x00($7)
62519		 jr    $7
62520		 nop                    	 # Delay slot
62521
62522	9:
62523		 and   $19,$0,$0
62524	8:
62525		 jal   Exception
62526		 ori   $2,$0,6          	 # Delay slot
62527
62528		 addiu $15,$15,-20
62529		 bgez  $15,3f
62530		 lhu   $24,0x00($23)    	 # Delay slot
62531		 j     MainExit
62532	3:
62533		 sll   $7,$24,2         	 # Delay slot
62534		 addu  $7,$7,$30
62535		 lw    $7,0x00($7)
62536		 jr    $7
62537		 nop                    	 # Delay slot
62538
62539OP0_41bc:				#:
62540		 addiu $23,$23,2
62541
62542		 srl   $24,$24,7
62543		 andi  $24,$24,0x1C
62544		 addu  $24,$24,$21
62545		 lh    $24,0x00($24)
62546		 lh    $2,0x00($23)
62547		 addiu $23,$23,2
62548		 and   $16,$0,$0
62549		 and   $17,$0,$0
62550		 sltiu $18,$24,1
62551		 slt   $19,$24,$0
62552		 bne   $19,$0,8f
62553		 slt   $8,$2,$24         	 # Delay slot
62554		 bne   $8,$0,9f
62555		 nop                    	 # Delay slot
62556		 addiu $15,$15,-10
62557		 bgez  $15,3f
62558		 lhu   $24,0x00($23)    	 # Delay slot
62559		 j     MainExit
62560	3:
62561		 sll   $7,$24,2         	 # Delay slot
62562		 addu  $7,$7,$30
62563		 lw    $7,0x00($7)
62564		 jr    $7
62565		 nop                    	 # Delay slot
62566
62567	9:
62568		 and   $19,$0,$0
62569	8:
62570		 jal   Exception
62571		 ori   $2,$0,6          	 # Delay slot
62572
62573		 addiu $15,$15,-10
62574		 bgez  $15,3f
62575		 lhu   $24,0x00($23)    	 # Delay slot
62576		 j     MainExit
62577	3:
62578		 sll   $7,$24,2         	 # Delay slot
62579		 addu  $7,$7,$30
62580		 lw    $7,0x00($7)
62581		 jr    $7
62582		 nop                    	 # Delay slot
62583
62584OP0_c140:				#:
62585		 addiu $23,$23,2
62586
62587		 andi  $8,$24,0x07
62588		 srl   $24,$24,7
62589		 sll   $8,$8,2
62590		 andi  $24,$24,0x1C
62591		 addu  $8,$8,$21
62592		 addu  $24,$24,$21
62593		 lw    $2,0x00($8)
62594		 lw    $3,0x00($24)
62595		 sw    $2,0x00($24)
62596		 sw    $3,0x00($8)
62597		 addiu $15,$15,-6
62598		 bgez  $15,3f
62599		 lhu   $24,0x00($23)    	 # Delay slot
62600		 j     MainExit
62601	3:
62602		 sll   $7,$24,2         	 # Delay slot
62603		 addu  $7,$7,$30
62604		 lw    $7,0x00($7)
62605		 jr    $7
62606		 nop                    	 # Delay slot
62607
62608OP0_c148:				#:
62609		 addiu $23,$23,2
62610
62611		 andi  $8,$24,0x07
62612		 srl   $24,$24,7
62613		 sll   $8,$8,2
62614		 andi  $24,$24,0x1C
62615		 addu  $8,$8,$21
62616		 addu  $24,$24,$21
62617		 lw    $2,0x20($8)
62618		 lw    $3,0x20($24)
62619		 sw    $2,0x20($24)
62620		 sw    $3,0x20($8)
62621		 addiu $15,$15,-6
62622		 bgez  $15,3f
62623		 lhu   $24,0x00($23)    	 # Delay slot
62624		 j     MainExit
62625	3:
62626		 sll   $7,$24,2         	 # Delay slot
62627		 addu  $7,$7,$30
62628		 lw    $7,0x00($7)
62629		 jr    $7
62630		 nop                    	 # Delay slot
62631
62632OP0_c188:				#:
62633		 addiu $23,$23,2
62634
62635		 andi  $8,$24,0x07
62636		 srl   $24,$24,7
62637		 sll   $8,$8,2
62638		 andi  $24,$24,0x1C
62639		 addu  $8,$8,$21
62640		 addu  $24,$24,$21
62641		 lw    $2,0x20($8)
62642		 lw    $3,0x00($24)
62643		 sw    $2,0x00($24)
62644		 sw    $3,0x20($8)
62645		 addiu $15,$15,-6
62646		 bgez  $15,3f
62647		 lhu   $24,0x00($23)    	 # Delay slot
62648		 j     MainExit
62649	3:
62650		 sll   $7,$24,2         	 # Delay slot
62651		 addu  $7,$7,$30
62652		 lw    $7,0x00($7)
62653		 jr    $7
62654		 nop                    	 # Delay slot
62655
62656OP0_b108:				#:
62657		 addiu $23,$23,2
62658
62659		 andi  $8,$24,0x07
62660		 srl   $24,$24,7
62661		 andi  $24,$24,0x1C
62662		 sll   $8,$8,2
62663		 addu  $8,$8,$21
62664		 lw    $14,0x20($8)
62665		 addiu $25,$14,1
62666		 sw    $25,0x20($8)
62667		 lw    $25,0x7C($21)
62668		 sw    $15,m68k_ICount
62669		 sw    $24,0x44($29)
62670		 or    $4,$0,$14
62671		 jalr  $25
62672		 sw    $23,0x4C($21)    	 # Delay slot
62673		 lw    $24,0x44($29)
62674		 lw    $15,m68k_ICount
62675		 seb   $8,$2
62676		 addu  $24,$24,$21
62677		 lw    $14,0x20($24)
62678		 addiu $25,$14,1
62679		 sw    $25,0x20($24)
62680		 lw    $25,0x7C($21)
62681		 sw    $15,m68k_ICount
62682		 sw    $8,0x44($29)
62683		 or    $4,$0,$14
62684		 jalr  $25
62685		 sw    $23,0x4C($21)    	 # Delay slot
62686		 lw    $8,0x44($29)
62687		 lw    $15,m68k_ICount
62688		 seb   $2,$2
62689		 subu  $3,$2,$8
62690		 sltu  $16,$2,$8       	 # Set Carry
62691		 xor   $17,$2,$8
62692		 xor   $25,$3,$2
62693		 and   $17,$17,$25
62694		 srl   $17,$17,7
62695		 andi  $17,$17,0x01     	 # Set Overflow
62696		 seb  $25,$3
62697		 slt   $19,$25,$0        	 # Set Sign
62698		 sltiu $18,$25,1         	 # Set Zero
62699		 addiu $15,$15,-12
62700		 bgez  $15,3f
62701		 lhu   $24,0x00($23)    	 # Delay slot
62702		 j     MainExit
62703	3:
62704		 sll   $7,$24,2         	 # Delay slot
62705		 addu  $7,$7,$30
62706		 lw    $7,0x00($7)
62707		 jr    $7
62708		 nop                    	 # Delay slot
62709
62710OP0_b10f:				#:
62711		 addiu $23,$23,2
62712
62713		 andi  $8,$24,0x07
62714		 srl   $24,$24,7
62715		 andi  $24,$24,0x1C
62716		 lw    $14,0x3C($21)    	 # Get A7
62717		 addiu $25,$14,2
62718		 sw    $25,0x3C($21)
62719		 lw    $25,0x7C($21)
62720		 sw    $15,m68k_ICount
62721		 sw    $24,0x44($29)
62722		 or    $4,$0,$14
62723		 jalr  $25
62724		 sw    $23,0x4C($21)    	 # Delay slot
62725		 lw    $24,0x44($29)
62726		 lw    $15,m68k_ICount
62727		 seb   $8,$2
62728		 addu  $24,$24,$21
62729		 lw    $14,0x20($24)
62730		 addiu $25,$14,1
62731		 sw    $25,0x20($24)
62732		 lw    $25,0x7C($21)
62733		 sw    $15,m68k_ICount
62734		 sw    $8,0x44($29)
62735		 or    $4,$0,$14
62736		 jalr  $25
62737		 sw    $23,0x4C($21)    	 # Delay slot
62738		 lw    $8,0x44($29)
62739		 lw    $15,m68k_ICount
62740		 seb   $2,$2
62741		 subu  $3,$2,$8
62742		 sltu  $16,$2,$8       	 # Set Carry
62743		 xor   $17,$2,$8
62744		 xor   $25,$3,$2
62745		 and   $17,$17,$25
62746		 srl   $17,$17,7
62747		 andi  $17,$17,0x01     	 # Set Overflow
62748		 seb  $25,$3
62749		 slt   $19,$25,$0        	 # Set Sign
62750		 sltiu $18,$25,1         	 # Set Zero
62751		 addiu $15,$15,-12
62752		 bgez  $15,3f
62753		 lhu   $24,0x00($23)    	 # Delay slot
62754		 j     MainExit
62755	3:
62756		 sll   $7,$24,2         	 # Delay slot
62757		 addu  $7,$7,$30
62758		 lw    $7,0x00($7)
62759		 jr    $7
62760		 nop                    	 # Delay slot
62761
62762OP0_b148:				#:
62763		 addiu $23,$23,2
62764
62765		 andi  $8,$24,0x07
62766		 srl   $24,$24,7
62767		 andi  $24,$24,0x1C
62768		 sll   $8,$8,2
62769		 addu  $8,$8,$21
62770		 lw    $14,0x20($8)
62771		 addiu $25,$14,2
62772		 sw    $25,0x20($8)
62773		 lw    $25,0x80($21)
62774		 sw    $15,m68k_ICount
62775		 sw    $24,0x44($29)
62776		 or    $4,$0,$14
62777		 jalr  $25
62778		 sw    $23,0x4C($21)    	 # Delay slot
62779		 lw    $24,0x44($29)
62780		 lw    $15,m68k_ICount
62781		 seh   $8,$2
62782		 addu  $24,$24,$21
62783		 lw    $14,0x20($24)
62784		 addiu $25,$14,2
62785		 sw    $25,0x20($24)
62786		 lw    $25,0x80($21)
62787		 sw    $15,m68k_ICount
62788		 sw    $8,0x44($29)
62789		 or    $4,$0,$14
62790		 jalr  $25
62791		 sw    $23,0x4C($21)    	 # Delay slot
62792		 lw    $8,0x44($29)
62793		 lw    $15,m68k_ICount
62794		 seh   $2,$2
62795		 subu  $3,$2,$8
62796		 sltu  $16,$2,$8       	 # Set Carry
62797		 xor   $17,$2,$8
62798		 xor   $25,$3,$2
62799		 and   $17,$17,$25
62800		 srl   $17,$17,15
62801		 andi  $17,$17,0x01     	 # Set Overflow
62802		 seh  $25,$3
62803		 slt   $19,$25,$0        	 # Set Sign
62804		 sltiu $18,$25,1         	 # Set Zero
62805		 addiu $15,$15,-12
62806		 bgez  $15,3f
62807		 lhu   $24,0x00($23)    	 # Delay slot
62808		 j     MainExit
62809	3:
62810		 sll   $7,$24,2         	 # Delay slot
62811		 addu  $7,$7,$30
62812		 lw    $7,0x00($7)
62813		 jr    $7
62814		 nop                    	 # Delay slot
62815
62816OP0_b188:				#:
62817		 addiu $23,$23,2
62818
62819		 andi  $8,$24,0x07
62820		 srl   $24,$24,7
62821		 andi  $24,$24,0x1C
62822		 sll   $8,$8,2
62823		 addu  $8,$8,$21
62824		 lw    $14,0x20($8)
62825		 addiu $25,$14,4
62826		 sw    $25,0x20($8)
62827		 lw    $25,0x84($21)
62828		 sw    $15,m68k_ICount
62829		 sw    $24,0x44($29)
62830		 or    $4,$0,$14
62831		 jalr  $25
62832		 sw    $23,0x4C($21)    	 # Delay slot
62833		 lw    $24,0x44($29)
62834		 lw    $15,m68k_ICount
62835		 or    $8,$0,$2
62836		 addu  $24,$24,$21
62837		 lw    $14,0x20($24)
62838		 addiu $25,$14,4
62839		 sw    $25,0x20($24)
62840		 lw    $25,0x84($21)
62841		 sw    $15,m68k_ICount
62842		 sw    $8,0x44($29)
62843		 or    $4,$0,$14
62844		 jalr  $25
62845		 sw    $23,0x4C($21)    	 # Delay slot
62846		 lw    $8,0x44($29)
62847		 lw    $15,m68k_ICount
62848		 subu  $3,$2,$8
62849		 sltu  $16,$2,$8       	 # Set Carry
62850		 xor   $17,$2,$8
62851		 xor   $25,$3,$2
62852		 and   $17,$17,$25
62853		 srl   $17,$17,31        	 # Set Overflow
62854		 slt   $19,$3,$0        	 # Set Sign
62855		 sltiu $18,$3,1         	 # Set Zero
62856		 addiu $15,$15,-20
62857		 bgez  $15,3f
62858		 lhu   $24,0x00($23)    	 # Delay slot
62859		 j     MainExit
62860	3:
62861		 sll   $7,$24,2         	 # Delay slot
62862		 addu  $7,$7,$30
62863		 lw    $7,0x00($7)
62864		 jr    $7
62865		 nop                    	 # Delay slot
62866
62867OP0_bf08:				#:
62868		 addiu $23,$23,2
62869
62870		 andi  $8,$24,0x07
62871		 srl   $24,$24,7
62872		 andi  $24,$24,0x1C
62873		 sll   $8,$8,2
62874		 addu  $8,$8,$21
62875		 lw    $14,0x20($8)
62876		 addiu $25,$14,1
62877		 sw    $25,0x20($8)
62878		 lw    $25,0x7C($21)
62879		 sw    $15,m68k_ICount
62880		 sw    $24,0x44($29)
62881		 or    $4,$0,$14
62882		 jalr  $25
62883		 sw    $23,0x4C($21)    	 # Delay slot
62884		 lw    $24,0x44($29)
62885		 lw    $15,m68k_ICount
62886		 seb   $8,$2
62887		 lw    $14,0x3C($21)    	 # Get A7
62888		 addiu $25,$14,2
62889		 sw    $25,0x3C($21)
62890		 lw    $25,0x7C($21)
62891		 sw    $15,m68k_ICount
62892		 sw    $8,0x44($29)
62893		 or    $4,$0,$14
62894		 jalr  $25
62895		 sw    $23,0x4C($21)    	 # Delay slot
62896		 lw    $8,0x44($29)
62897		 lw    $15,m68k_ICount
62898		 seb   $2,$2
62899		 subu  $3,$2,$8
62900		 sltu  $16,$2,$8       	 # Set Carry
62901		 xor   $17,$2,$8
62902		 xor   $25,$3,$2
62903		 and   $17,$17,$25
62904		 srl   $17,$17,7
62905		 andi  $17,$17,0x01     	 # Set Overflow
62906		 seb  $25,$3
62907		 slt   $19,$25,$0        	 # Set Sign
62908		 sltiu $18,$25,1         	 # Set Zero
62909		 addiu $15,$15,-12
62910		 bgez  $15,3f
62911		 lhu   $24,0x00($23)    	 # Delay slot
62912		 j     MainExit
62913	3:
62914		 sll   $7,$24,2         	 # Delay slot
62915		 addu  $7,$7,$30
62916		 lw    $7,0x00($7)
62917		 jr    $7
62918		 nop                    	 # Delay slot
62919
62920OP0_bf0f:				#:
62921		 addiu $23,$23,2
62922
62923		 andi  $8,$24,0x07
62924		 srl   $24,$24,7
62925		 andi  $24,$24,0x1C
62926		 lw    $14,0x3C($21)    	 # Get A7
62927		 addiu $25,$14,2
62928		 sw    $25,0x3C($21)
62929		 lw    $25,0x7C($21)
62930		 sw    $15,m68k_ICount
62931		 sw    $24,0x44($29)
62932		 or    $4,$0,$14
62933		 jalr  $25
62934		 sw    $23,0x4C($21)    	 # Delay slot
62935		 lw    $24,0x44($29)
62936		 lw    $15,m68k_ICount
62937		 seb   $8,$2
62938		 lw    $14,0x3C($21)    	 # Get A7
62939		 addiu $25,$14,2
62940		 sw    $25,0x3C($21)
62941		 lw    $25,0x7C($21)
62942		 sw    $15,m68k_ICount
62943		 sw    $8,0x44($29)
62944		 or    $4,$0,$14
62945		 jalr  $25
62946		 sw    $23,0x4C($21)    	 # Delay slot
62947		 lw    $8,0x44($29)
62948		 lw    $15,m68k_ICount
62949		 seb   $2,$2
62950		 subu  $3,$2,$8
62951		 sltu  $16,$2,$8       	 # Set Carry
62952		 xor   $17,$2,$8
62953		 xor   $25,$3,$2
62954		 and   $17,$17,$25
62955		 srl   $17,$17,7
62956		 andi  $17,$17,0x01     	 # Set Overflow
62957		 seb  $25,$3
62958		 slt   $19,$25,$0        	 # Set Sign
62959		 sltiu $18,$25,1         	 # Set Zero
62960		 addiu $15,$15,-12
62961		 bgez  $15,3f
62962		 lhu   $24,0x00($23)    	 # Delay slot
62963		 j     MainExit
62964	3:
62965		 sll   $7,$24,2         	 # Delay slot
62966		 addu  $7,$7,$30
62967		 lw    $7,0x00($7)
62968		 jr    $7
62969		 nop                    	 # Delay slot
62970
62971OP0_c0c0:				#:
62972		 addiu $23,$23,2
62973
62974		 andi  $8,$24,0x07
62975		 srl   $24,$24,7
62976		 andi  $24,$24,0x1C
62977		 addu  $24,$24,$21
62978		 lhu   $9,0x00($24)
62979		 sll   $8,$8,2
62980		 addu  $8,$8,$21
62981		 lhu   $2,0x00($8)
62982		 multu $2,$9
62983		 mflo  $8
62984		 sw    $8,0x00($24)
62985		 and   $16,$0,$0        	 # Clear Carry
62986		 and   $17,$0,$0        	 # Clear Overflow
62987		 slt   $19,$8,$0        	 # Set Sign
62988		 sltiu $18,$8,1         	 # Set Zero
62989		 addiu $15,$15,-54
62990		 bgez  $15,3f
62991		 lhu   $24,0x00($23)    	 # Delay slot
62992		 j     MainExit
62993	3:
62994		 sll   $7,$24,2         	 # Delay slot
62995		 addu  $7,$7,$30
62996		 lw    $7,0x00($7)
62997		 jr    $7
62998		 nop                    	 # Delay slot
62999
63000OP0_c0d0:				#:
63001		 addiu $23,$23,2
63002
63003		 andi  $8,$24,0x07
63004		 srl   $24,$24,7
63005		 andi  $24,$24,0x1C
63006		 addu  $24,$24,$21
63007		 lhu   $9,0x00($24)
63008		 sll   $8,$8,2
63009		 addu  $8,$8,$21
63010		 lw    $14,0x20($8)
63011		 lw    $25,0x80($21)
63012		 sw    $15,m68k_ICount
63013		 sw    $24,0x44($29)
63014		 or    $4,$0,$14
63015		 jalr  $25
63016		 sw    $23,0x4C($21)    	 # Delay slot
63017		 lw    $24,0x44($29)
63018		 lw    $15,m68k_ICount
63019		 multu $2,$9
63020		 mflo  $8
63021		 sw    $8,0x00($24)
63022		 and   $16,$0,$0        	 # Clear Carry
63023		 and   $17,$0,$0        	 # Clear Overflow
63024		 slt   $19,$8,$0        	 # Set Sign
63025		 sltiu $18,$8,1         	 # Set Zero
63026		 addiu $15,$15,-58
63027		 bgez  $15,3f
63028		 lhu   $24,0x00($23)    	 # Delay slot
63029		 j     MainExit
63030	3:
63031		 sll   $7,$24,2         	 # Delay slot
63032		 addu  $7,$7,$30
63033		 lw    $7,0x00($7)
63034		 jr    $7
63035		 nop                    	 # Delay slot
63036
63037OP0_c0d8:				#:
63038		 addiu $23,$23,2
63039
63040		 andi  $8,$24,0x07
63041		 srl   $24,$24,7
63042		 andi  $24,$24,0x1C
63043		 addu  $24,$24,$21
63044		 lhu   $9,0x00($24)
63045		 sll   $8,$8,2
63046		 addu  $8,$8,$21
63047		 lw    $14,0x20($8)
63048		 addiu $25,$14,2
63049		 sw    $25,0x20($8)
63050		 lw    $25,0x80($21)
63051		 sw    $15,m68k_ICount
63052		 sw    $24,0x44($29)
63053		 or    $4,$0,$14
63054		 jalr  $25
63055		 sw    $23,0x4C($21)    	 # Delay slot
63056		 lw    $24,0x44($29)
63057		 lw    $15,m68k_ICount
63058		 multu $2,$9
63059		 mflo  $8
63060		 sw    $8,0x00($24)
63061		 and   $16,$0,$0        	 # Clear Carry
63062		 and   $17,$0,$0        	 # Clear Overflow
63063		 slt   $19,$8,$0        	 # Set Sign
63064		 sltiu $18,$8,1         	 # Set Zero
63065		 addiu $15,$15,-58
63066		 bgez  $15,3f
63067		 lhu   $24,0x00($23)    	 # Delay slot
63068		 j     MainExit
63069	3:
63070		 sll   $7,$24,2         	 # Delay slot
63071		 addu  $7,$7,$30
63072		 lw    $7,0x00($7)
63073		 jr    $7
63074		 nop                    	 # Delay slot
63075
63076OP0_c0e0:				#:
63077		 addiu $23,$23,2
63078
63079		 andi  $8,$24,0x07
63080		 srl   $24,$24,7
63081		 andi  $24,$24,0x1C
63082		 addu  $24,$24,$21
63083		 lhu   $9,0x00($24)
63084		 sll   $8,$8,2
63085		 addu  $8,$8,$21
63086		 lw    $14,0x20($8)
63087		 addiu $14,$14,-2
63088		 sw    $14,0x20($8)
63089		 lw    $25,0x80($21)
63090		 sw    $15,m68k_ICount
63091		 sw    $24,0x44($29)
63092		 or    $4,$0,$14
63093		 jalr  $25
63094		 sw    $23,0x4C($21)    	 # Delay slot
63095		 lw    $24,0x44($29)
63096		 lw    $15,m68k_ICount
63097		 multu $2,$9
63098		 mflo  $8
63099		 sw    $8,0x00($24)
63100		 and   $16,$0,$0        	 # Clear Carry
63101		 and   $17,$0,$0        	 # Clear Overflow
63102		 slt   $19,$8,$0        	 # Set Sign
63103		 sltiu $18,$8,1         	 # Set Zero
63104		 addiu $15,$15,-60
63105		 bgez  $15,3f
63106		 lhu   $24,0x00($23)    	 # Delay slot
63107		 j     MainExit
63108	3:
63109		 sll   $7,$24,2         	 # Delay slot
63110		 addu  $7,$7,$30
63111		 lw    $7,0x00($7)
63112		 jr    $7
63113		 nop                    	 # Delay slot
63114
63115OP0_c0e8:				#:
63116		 addiu $23,$23,2
63117
63118		 andi  $8,$24,0x07
63119		 srl   $24,$24,7
63120		 andi  $24,$24,0x1C
63121		 addu  $24,$24,$21
63122		 lhu   $9,0x00($24)
63123		 lh    $7,0x00($23)
63124		 sll   $8,$8,2
63125		 addu  $8,$8,$21
63126		 lw    $14,0x20($8)
63127		 addiu $23,$23,2
63128		 addu  $14,$14,$7
63129		 lw    $25,0x80($21)
63130		 sw    $15,m68k_ICount
63131		 sw    $24,0x44($29)
63132		 or    $4,$0,$14
63133		 jalr  $25
63134		 sw    $23,0x4C($21)    	 # Delay slot
63135		 lw    $24,0x44($29)
63136		 lw    $15,m68k_ICount
63137		 multu $2,$9
63138		 mflo  $8
63139		 sw    $8,0x00($24)
63140		 and   $16,$0,$0        	 # Clear Carry
63141		 and   $17,$0,$0        	 # Clear Overflow
63142		 slt   $19,$8,$0        	 # Set Sign
63143		 sltiu $18,$8,1         	 # Set Zero
63144		 addiu $15,$15,-62
63145		 bgez  $15,3f
63146		 lhu   $24,0x00($23)    	 # Delay slot
63147		 j     MainExit
63148	3:
63149		 sll   $7,$24,2         	 # Delay slot
63150		 addu  $7,$7,$30
63151		 lw    $7,0x00($7)
63152		 jr    $7
63153		 nop                    	 # Delay slot
63154
63155OP0_c0f0:				#:
63156		 addiu $23,$23,2
63157
63158		 andi  $8,$24,0x07
63159		 srl   $24,$24,7
63160		 andi  $24,$24,0x1C
63161		 addu  $24,$24,$21
63162		 lhu   $9,0x00($24)
63163		 sll   $8,$8,2
63164		 addu  $8,$8,$21
63165		 lw    $14,0x20($8)
63166		 lhu   $7,0x00($23)
63167		 addiu $23,$23,2
63168		 seb   $6,$7
63169		 or    $25,$0,$7
63170		 srl   $7,$7,12
63171		 andi  $25,$25,0x0800
63172		 sll   $7,$7,2
63173		 addu  $7,$7,$21
63174		 bne   $25,$0,0f
63175		 lw    $25,0x00($7)      	 # Delay slot
63176		 seh   $25,$25
63177	0:
63178		 addu  $25,$14,$25
63179		 addu  $14,$25,$6
63180		 lw    $25,0x80($21)
63181		 sw    $15,m68k_ICount
63182		 sw    $24,0x44($29)
63183		 or    $4,$0,$14
63184		 jalr  $25
63185		 sw    $23,0x4C($21)    	 # Delay slot
63186		 lw    $24,0x44($29)
63187		 lw    $15,m68k_ICount
63188		 multu $2,$9
63189		 mflo  $8
63190		 sw    $8,0x00($24)
63191		 and   $16,$0,$0        	 # Clear Carry
63192		 and   $17,$0,$0        	 # Clear Overflow
63193		 slt   $19,$8,$0        	 # Set Sign
63194		 sltiu $18,$8,1         	 # Set Zero
63195		 addiu $15,$15,-64
63196		 bgez  $15,3f
63197		 lhu   $24,0x00($23)    	 # Delay slot
63198		 j     MainExit
63199	3:
63200		 sll   $7,$24,2         	 # Delay slot
63201		 addu  $7,$7,$30
63202		 lw    $7,0x00($7)
63203		 jr    $7
63204		 nop                    	 # Delay slot
63205
63206OP0_c0f8:				#:
63207		 addiu $23,$23,2
63208
63209		 srl   $24,$24,7
63210		 andi  $24,$24,0x1C
63211		 addu  $24,$24,$21
63212		 lhu   $9,0x00($24)
63213		 lh    $14,0x00($23)
63214		 addiu $23,$23,2
63215		 lw    $25,0x80($21)
63216		 sw    $15,m68k_ICount
63217		 sw    $24,0x44($29)
63218		 or    $4,$0,$14
63219		 jalr  $25
63220		 sw    $23,0x4C($21)    	 # Delay slot
63221		 lw    $24,0x44($29)
63222		 lw    $15,m68k_ICount
63223		 multu $2,$9
63224		 mflo  $8
63225		 sw    $8,0x00($24)
63226		 and   $16,$0,$0        	 # Clear Carry
63227		 and   $17,$0,$0        	 # Clear Overflow
63228		 slt   $19,$8,$0        	 # Set Sign
63229		 sltiu $18,$8,1         	 # Set Zero
63230		 addiu $15,$15,-62
63231		 bgez  $15,3f
63232		 lhu   $24,0x00($23)    	 # Delay slot
63233		 j     MainExit
63234	3:
63235		 sll   $7,$24,2         	 # Delay slot
63236		 addu  $7,$7,$30
63237		 lw    $7,0x00($7)
63238		 jr    $7
63239		 nop                    	 # Delay slot
63240
63241OP0_c0f9:				#:
63242		 addiu $23,$23,2
63243
63244		 srl   $24,$24,7
63245		 andi  $24,$24,0x1C
63246		 addu  $24,$24,$21
63247		 lhu   $9,0x00($24)
63248		 lhu   $14,0x00($23)
63249		 lhu   $25,0x02($23)
63250		 sll   $14,$14,16
63251		 or    $14,$14,$25
63252		 addiu $23,$23,4
63253		 lw    $25,0x80($21)
63254		 sw    $15,m68k_ICount
63255		 sw    $24,0x44($29)
63256		 or    $4,$0,$14
63257		 jalr  $25
63258		 sw    $23,0x4C($21)    	 # Delay slot
63259		 lw    $24,0x44($29)
63260		 lw    $15,m68k_ICount
63261		 multu $2,$9
63262		 mflo  $8
63263		 sw    $8,0x00($24)
63264		 and   $16,$0,$0        	 # Clear Carry
63265		 and   $17,$0,$0        	 # Clear Overflow
63266		 slt   $19,$8,$0        	 # Set Sign
63267		 sltiu $18,$8,1         	 # Set Zero
63268		 addiu $15,$15,-66
63269		 bgez  $15,3f
63270		 lhu   $24,0x00($23)    	 # Delay slot
63271		 j     MainExit
63272	3:
63273		 sll   $7,$24,2         	 # Delay slot
63274		 addu  $7,$7,$30
63275		 lw    $7,0x00($7)
63276		 jr    $7
63277		 nop                    	 # Delay slot
63278
63279OP0_c0fa:				#:
63280		 addiu $23,$23,2
63281
63282		 srl   $24,$24,7
63283		 andi  $24,$24,0x1C
63284		 addu  $24,$24,$21
63285		 lhu   $9,0x00($24)
63286		 lh    $7,0x00($23)
63287		 subu  $25,$23,$22
63288		 addu  $14,$25,$7       	 # Add Offset to PC
63289		 addiu $23,$23,2
63290		 lw    $25,0x9C($21)
63291		 sw    $15,m68k_ICount
63292		 sw    $24,0x44($29)
63293		 or    $4,$0,$14
63294		 jalr  $25
63295		 sw    $23,0x4C($21)    	 # Delay slot
63296		 lw    $24,0x44($29)
63297		 lw    $15,m68k_ICount
63298		 multu $2,$9
63299		 mflo  $8
63300		 sw    $8,0x00($24)
63301		 and   $16,$0,$0        	 # Clear Carry
63302		 and   $17,$0,$0        	 # Clear Overflow
63303		 slt   $19,$8,$0        	 # Set Sign
63304		 sltiu $18,$8,1         	 # Set Zero
63305		 addiu $15,$15,-62
63306		 bgez  $15,3f
63307		 lhu   $24,0x00($23)    	 # Delay slot
63308		 j     MainExit
63309	3:
63310		 sll   $7,$24,2         	 # Delay slot
63311		 addu  $7,$7,$30
63312		 lw    $7,0x00($7)
63313		 jr    $7
63314		 nop                    	 # Delay slot
63315
63316OP0_c0fb:				#:
63317		 addiu $23,$23,2
63318
63319		 srl   $24,$24,7
63320		 andi  $24,$24,0x1C
63321		 addu  $24,$24,$21
63322		 lhu   $9,0x00($24)
63323		 subu  $14,$23,$22       	 # Get PC
63324		 lhu   $7,0x00($23)
63325		 addiu $23,$23,2
63326		 seb   $6,$7
63327		 or    $25,$0,$7
63328		 srl   $7,$7,12
63329		 andi  $25,$25,0x0800
63330		 sll   $7,$7,2
63331		 addu  $7,$7,$21
63332		 bne   $25,$0,0f
63333		 lw    $25,0x00($7)      	 # Delay slot
63334		 seh   $25,$25
63335	0:
63336		 addu  $25,$14,$25
63337		 addu  $14,$25,$6
63338		 lw    $25,0x9C($21)
63339		 sw    $15,m68k_ICount
63340		 sw    $24,0x44($29)
63341		 or    $4,$0,$14
63342		 jalr  $25
63343		 sw    $23,0x4C($21)    	 # Delay slot
63344		 lw    $24,0x44($29)
63345		 lw    $15,m68k_ICount
63346		 multu $2,$9
63347		 mflo  $8
63348		 sw    $8,0x00($24)
63349		 and   $16,$0,$0        	 # Clear Carry
63350		 and   $17,$0,$0        	 # Clear Overflow
63351		 slt   $19,$8,$0        	 # Set Sign
63352		 sltiu $18,$8,1         	 # Set Zero
63353		 addiu $15,$15,-64
63354		 bgez  $15,3f
63355		 lhu   $24,0x00($23)    	 # Delay slot
63356		 j     MainExit
63357	3:
63358		 sll   $7,$24,2         	 # Delay slot
63359		 addu  $7,$7,$30
63360		 lw    $7,0x00($7)
63361		 jr    $7
63362		 nop                    	 # Delay slot
63363
63364OP0_c0fc:				#:
63365		 addiu $23,$23,2
63366
63367		 srl   $24,$24,7
63368		 andi  $24,$24,0x1C
63369		 addu  $24,$24,$21
63370		 lhu   $9,0x00($24)
63371		 lhu   $2,0x00($23)
63372		 addiu $23,$23,2
63373		 multu $2,$9
63374		 mflo  $8
63375		 sw    $8,0x00($24)
63376		 and   $16,$0,$0        	 # Clear Carry
63377		 and   $17,$0,$0        	 # Clear Overflow
63378		 slt   $19,$8,$0        	 # Set Sign
63379		 sltiu $18,$8,1         	 # Set Zero
63380		 addiu $15,$15,-54
63381		 bgez  $15,3f
63382		 lhu   $24,0x00($23)    	 # Delay slot
63383		 j     MainExit
63384	3:
63385		 sll   $7,$24,2         	 # Delay slot
63386		 addu  $7,$7,$30
63387		 lw    $7,0x00($7)
63388		 jr    $7
63389		 nop                    	 # Delay slot
63390
63391OP0_c1c0:				#:
63392		 addiu $23,$23,2
63393
63394		 andi  $8,$24,0x07
63395		 srl   $24,$24,7
63396		 andi  $24,$24,0x1C
63397		 addu  $24,$24,$21
63398		 lh    $9,0x00($24)
63399		 sll   $8,$8,2
63400		 addu  $8,$8,$21
63401		 lh    $2,0x00($8)
63402		 mult  $2,$9
63403		 mflo  $8
63404		 sw    $8,0x00($24)
63405		 and   $16,$0,$0        	 # Clear Carry
63406		 and   $17,$0,$0        	 # Clear Overflow
63407		 slt   $19,$8,$0        	 # Set Sign
63408		 sltiu $18,$8,1         	 # Set Zero
63409		 addiu $15,$15,-54
63410		 bgez  $15,3f
63411		 lhu   $24,0x00($23)    	 # Delay slot
63412		 j     MainExit
63413	3:
63414		 sll   $7,$24,2         	 # Delay slot
63415		 addu  $7,$7,$30
63416		 lw    $7,0x00($7)
63417		 jr    $7
63418		 nop                    	 # Delay slot
63419
63420OP0_c1d0:				#:
63421		 addiu $23,$23,2
63422
63423		 andi  $8,$24,0x07
63424		 srl   $24,$24,7
63425		 andi  $24,$24,0x1C
63426		 addu  $24,$24,$21
63427		 lh    $9,0x00($24)
63428		 sll   $8,$8,2
63429		 addu  $8,$8,$21
63430		 lw    $14,0x20($8)
63431		 lw    $25,0x80($21)
63432		 sw    $15,m68k_ICount
63433		 sw    $24,0x44($29)
63434		 or    $4,$0,$14
63435		 jalr  $25
63436		 sw    $23,0x4C($21)    	 # Delay slot
63437		 lw    $24,0x44($29)
63438		 lw    $15,m68k_ICount
63439		 seh   $2,$2
63440		 mult  $2,$9
63441		 mflo  $8
63442		 sw    $8,0x00($24)
63443		 and   $16,$0,$0        	 # Clear Carry
63444		 and   $17,$0,$0        	 # Clear Overflow
63445		 slt   $19,$8,$0        	 # Set Sign
63446		 sltiu $18,$8,1         	 # Set Zero
63447		 addiu $15,$15,-58
63448		 bgez  $15,3f
63449		 lhu   $24,0x00($23)    	 # Delay slot
63450		 j     MainExit
63451	3:
63452		 sll   $7,$24,2         	 # Delay slot
63453		 addu  $7,$7,$30
63454		 lw    $7,0x00($7)
63455		 jr    $7
63456		 nop                    	 # Delay slot
63457
63458OP0_c1d8:				#:
63459		 addiu $23,$23,2
63460
63461		 andi  $8,$24,0x07
63462		 srl   $24,$24,7
63463		 andi  $24,$24,0x1C
63464		 addu  $24,$24,$21
63465		 lh    $9,0x00($24)
63466		 sll   $8,$8,2
63467		 addu  $8,$8,$21
63468		 lw    $14,0x20($8)
63469		 addiu $25,$14,2
63470		 sw    $25,0x20($8)
63471		 lw    $25,0x80($21)
63472		 sw    $15,m68k_ICount
63473		 sw    $24,0x44($29)
63474		 or    $4,$0,$14
63475		 jalr  $25
63476		 sw    $23,0x4C($21)    	 # Delay slot
63477		 lw    $24,0x44($29)
63478		 lw    $15,m68k_ICount
63479		 seh   $2,$2
63480		 mult  $2,$9
63481		 mflo  $8
63482		 sw    $8,0x00($24)
63483		 and   $16,$0,$0        	 # Clear Carry
63484		 and   $17,$0,$0        	 # Clear Overflow
63485		 slt   $19,$8,$0        	 # Set Sign
63486		 sltiu $18,$8,1         	 # Set Zero
63487		 addiu $15,$15,-58
63488		 bgez  $15,3f
63489		 lhu   $24,0x00($23)    	 # Delay slot
63490		 j     MainExit
63491	3:
63492		 sll   $7,$24,2         	 # Delay slot
63493		 addu  $7,$7,$30
63494		 lw    $7,0x00($7)
63495		 jr    $7
63496		 nop                    	 # Delay slot
63497
63498OP0_c1e0:				#:
63499		 addiu $23,$23,2
63500
63501		 andi  $8,$24,0x07
63502		 srl   $24,$24,7
63503		 andi  $24,$24,0x1C
63504		 addu  $24,$24,$21
63505		 lh    $9,0x00($24)
63506		 sll   $8,$8,2
63507		 addu  $8,$8,$21
63508		 lw    $14,0x20($8)
63509		 addiu $14,$14,-2
63510		 sw    $14,0x20($8)
63511		 lw    $25,0x80($21)
63512		 sw    $15,m68k_ICount
63513		 sw    $24,0x44($29)
63514		 or    $4,$0,$14
63515		 jalr  $25
63516		 sw    $23,0x4C($21)    	 # Delay slot
63517		 lw    $24,0x44($29)
63518		 lw    $15,m68k_ICount
63519		 seh   $2,$2
63520		 mult  $2,$9
63521		 mflo  $8
63522		 sw    $8,0x00($24)
63523		 and   $16,$0,$0        	 # Clear Carry
63524		 and   $17,$0,$0        	 # Clear Overflow
63525		 slt   $19,$8,$0        	 # Set Sign
63526		 sltiu $18,$8,1         	 # Set Zero
63527		 addiu $15,$15,-60
63528		 bgez  $15,3f
63529		 lhu   $24,0x00($23)    	 # Delay slot
63530		 j     MainExit
63531	3:
63532		 sll   $7,$24,2         	 # Delay slot
63533		 addu  $7,$7,$30
63534		 lw    $7,0x00($7)
63535		 jr    $7
63536		 nop                    	 # Delay slot
63537
63538OP0_c1e8:				#:
63539		 addiu $23,$23,2
63540
63541		 andi  $8,$24,0x07
63542		 srl   $24,$24,7
63543		 andi  $24,$24,0x1C
63544		 addu  $24,$24,$21
63545		 lh    $9,0x00($24)
63546		 lh    $7,0x00($23)
63547		 sll   $8,$8,2
63548		 addu  $8,$8,$21
63549		 lw    $14,0x20($8)
63550		 addiu $23,$23,2
63551		 addu  $14,$14,$7
63552		 lw    $25,0x80($21)
63553		 sw    $15,m68k_ICount
63554		 sw    $24,0x44($29)
63555		 or    $4,$0,$14
63556		 jalr  $25
63557		 sw    $23,0x4C($21)    	 # Delay slot
63558		 lw    $24,0x44($29)
63559		 lw    $15,m68k_ICount
63560		 seh   $2,$2
63561		 mult  $2,$9
63562		 mflo  $8
63563		 sw    $8,0x00($24)
63564		 and   $16,$0,$0        	 # Clear Carry
63565		 and   $17,$0,$0        	 # Clear Overflow
63566		 slt   $19,$8,$0        	 # Set Sign
63567		 sltiu $18,$8,1         	 # Set Zero
63568		 addiu $15,$15,-62
63569		 bgez  $15,3f
63570		 lhu   $24,0x00($23)    	 # Delay slot
63571		 j     MainExit
63572	3:
63573		 sll   $7,$24,2         	 # Delay slot
63574		 addu  $7,$7,$30
63575		 lw    $7,0x00($7)
63576		 jr    $7
63577		 nop                    	 # Delay slot
63578
63579OP0_c1f0:				#:
63580		 addiu $23,$23,2
63581
63582		 andi  $8,$24,0x07
63583		 srl   $24,$24,7
63584		 andi  $24,$24,0x1C
63585		 addu  $24,$24,$21
63586		 lh    $9,0x00($24)
63587		 sll   $8,$8,2
63588		 addu  $8,$8,$21
63589		 lw    $14,0x20($8)
63590		 lhu   $7,0x00($23)
63591		 addiu $23,$23,2
63592		 seb   $6,$7
63593		 or    $25,$0,$7
63594		 srl   $7,$7,12
63595		 andi  $25,$25,0x0800
63596		 sll   $7,$7,2
63597		 addu  $7,$7,$21
63598		 bne   $25,$0,0f
63599		 lw    $25,0x00($7)      	 # Delay slot
63600		 seh   $25,$25
63601	0:
63602		 addu  $25,$14,$25
63603		 addu  $14,$25,$6
63604		 lw    $25,0x80($21)
63605		 sw    $15,m68k_ICount
63606		 sw    $24,0x44($29)
63607		 or    $4,$0,$14
63608		 jalr  $25
63609		 sw    $23,0x4C($21)    	 # Delay slot
63610		 lw    $24,0x44($29)
63611		 lw    $15,m68k_ICount
63612		 seh   $2,$2
63613		 mult  $2,$9
63614		 mflo  $8
63615		 sw    $8,0x00($24)
63616		 and   $16,$0,$0        	 # Clear Carry
63617		 and   $17,$0,$0        	 # Clear Overflow
63618		 slt   $19,$8,$0        	 # Set Sign
63619		 sltiu $18,$8,1         	 # Set Zero
63620		 addiu $15,$15,-64
63621		 bgez  $15,3f
63622		 lhu   $24,0x00($23)    	 # Delay slot
63623		 j     MainExit
63624	3:
63625		 sll   $7,$24,2         	 # Delay slot
63626		 addu  $7,$7,$30
63627		 lw    $7,0x00($7)
63628		 jr    $7
63629		 nop                    	 # Delay slot
63630
63631OP0_c1f8:				#:
63632		 addiu $23,$23,2
63633
63634		 srl   $24,$24,7
63635		 andi  $24,$24,0x1C
63636		 addu  $24,$24,$21
63637		 lh    $9,0x00($24)
63638		 lh    $14,0x00($23)
63639		 addiu $23,$23,2
63640		 lw    $25,0x80($21)
63641		 sw    $15,m68k_ICount
63642		 sw    $24,0x44($29)
63643		 or    $4,$0,$14
63644		 jalr  $25
63645		 sw    $23,0x4C($21)    	 # Delay slot
63646		 lw    $24,0x44($29)
63647		 lw    $15,m68k_ICount
63648		 seh   $2,$2
63649		 mult  $2,$9
63650		 mflo  $8
63651		 sw    $8,0x00($24)
63652		 and   $16,$0,$0        	 # Clear Carry
63653		 and   $17,$0,$0        	 # Clear Overflow
63654		 slt   $19,$8,$0        	 # Set Sign
63655		 sltiu $18,$8,1         	 # Set Zero
63656		 addiu $15,$15,-62
63657		 bgez  $15,3f
63658		 lhu   $24,0x00($23)    	 # Delay slot
63659		 j     MainExit
63660	3:
63661		 sll   $7,$24,2         	 # Delay slot
63662		 addu  $7,$7,$30
63663		 lw    $7,0x00($7)
63664		 jr    $7
63665		 nop                    	 # Delay slot
63666
63667OP0_c1f9:				#:
63668		 addiu $23,$23,2
63669
63670		 srl   $24,$24,7
63671		 andi  $24,$24,0x1C
63672		 addu  $24,$24,$21
63673		 lh    $9,0x00($24)
63674		 lhu   $14,0x00($23)
63675		 lhu   $25,0x02($23)
63676		 sll   $14,$14,16
63677		 or    $14,$14,$25
63678		 addiu $23,$23,4
63679		 lw    $25,0x80($21)
63680		 sw    $15,m68k_ICount
63681		 sw    $24,0x44($29)
63682		 or    $4,$0,$14
63683		 jalr  $25
63684		 sw    $23,0x4C($21)    	 # Delay slot
63685		 lw    $24,0x44($29)
63686		 lw    $15,m68k_ICount
63687		 seh   $2,$2
63688		 mult  $2,$9
63689		 mflo  $8
63690		 sw    $8,0x00($24)
63691		 and   $16,$0,$0        	 # Clear Carry
63692		 and   $17,$0,$0        	 # Clear Overflow
63693		 slt   $19,$8,$0        	 # Set Sign
63694		 sltiu $18,$8,1         	 # Set Zero
63695		 addiu $15,$15,-66
63696		 bgez  $15,3f
63697		 lhu   $24,0x00($23)    	 # Delay slot
63698		 j     MainExit
63699	3:
63700		 sll   $7,$24,2         	 # Delay slot
63701		 addu  $7,$7,$30
63702		 lw    $7,0x00($7)
63703		 jr    $7
63704		 nop                    	 # Delay slot
63705
63706OP0_c1fa:				#:
63707		 addiu $23,$23,2
63708
63709		 srl   $24,$24,7
63710		 andi  $24,$24,0x1C
63711		 addu  $24,$24,$21
63712		 lh    $9,0x00($24)
63713		 lh    $7,0x00($23)
63714		 subu  $25,$23,$22
63715		 addu  $14,$25,$7       	 # Add Offset to PC
63716		 addiu $23,$23,2
63717		 lw    $25,0x9C($21)
63718		 sw    $15,m68k_ICount
63719		 sw    $24,0x44($29)
63720		 or    $4,$0,$14
63721		 jalr  $25
63722		 sw    $23,0x4C($21)    	 # Delay slot
63723		 lw    $24,0x44($29)
63724		 lw    $15,m68k_ICount
63725		 seh   $2,$2
63726		 mult  $2,$9
63727		 mflo  $8
63728		 sw    $8,0x00($24)
63729		 and   $16,$0,$0        	 # Clear Carry
63730		 and   $17,$0,$0        	 # Clear Overflow
63731		 slt   $19,$8,$0        	 # Set Sign
63732		 sltiu $18,$8,1         	 # Set Zero
63733		 addiu $15,$15,-62
63734		 bgez  $15,3f
63735		 lhu   $24,0x00($23)    	 # Delay slot
63736		 j     MainExit
63737	3:
63738		 sll   $7,$24,2         	 # Delay slot
63739		 addu  $7,$7,$30
63740		 lw    $7,0x00($7)
63741		 jr    $7
63742		 nop                    	 # Delay slot
63743
63744OP0_c1fb:				#:
63745		 addiu $23,$23,2
63746
63747		 srl   $24,$24,7
63748		 andi  $24,$24,0x1C
63749		 addu  $24,$24,$21
63750		 lh    $9,0x00($24)
63751		 subu  $14,$23,$22       	 # Get PC
63752		 lhu   $7,0x00($23)
63753		 addiu $23,$23,2
63754		 seb   $6,$7
63755		 or    $25,$0,$7
63756		 srl   $7,$7,12
63757		 andi  $25,$25,0x0800
63758		 sll   $7,$7,2
63759		 addu  $7,$7,$21
63760		 bne   $25,$0,0f
63761		 lw    $25,0x00($7)      	 # Delay slot
63762		 seh   $25,$25
63763	0:
63764		 addu  $25,$14,$25
63765		 addu  $14,$25,$6
63766		 lw    $25,0x9C($21)
63767		 sw    $15,m68k_ICount
63768		 sw    $24,0x44($29)
63769		 or    $4,$0,$14
63770		 jalr  $25
63771		 sw    $23,0x4C($21)    	 # Delay slot
63772		 lw    $24,0x44($29)
63773		 lw    $15,m68k_ICount
63774		 seh   $2,$2
63775		 mult  $2,$9
63776		 mflo  $8
63777		 sw    $8,0x00($24)
63778		 and   $16,$0,$0        	 # Clear Carry
63779		 and   $17,$0,$0        	 # Clear Overflow
63780		 slt   $19,$8,$0        	 # Set Sign
63781		 sltiu $18,$8,1         	 # Set Zero
63782		 addiu $15,$15,-64
63783		 bgez  $15,3f
63784		 lhu   $24,0x00($23)    	 # Delay slot
63785		 j     MainExit
63786	3:
63787		 sll   $7,$24,2         	 # Delay slot
63788		 addu  $7,$7,$30
63789		 lw    $7,0x00($7)
63790		 jr    $7
63791		 nop                    	 # Delay slot
63792
63793OP0_c1fc:				#:
63794		 addiu $23,$23,2
63795
63796		 srl   $24,$24,7
63797		 andi  $24,$24,0x1C
63798		 addu  $24,$24,$21
63799		 lh    $9,0x00($24)
63800		 lh    $2,0x00($23)
63801		 addiu $23,$23,2
63802		 mult  $2,$9
63803		 mflo  $8
63804		 sw    $8,0x00($24)
63805		 and   $16,$0,$0        	 # Clear Carry
63806		 and   $17,$0,$0        	 # Clear Overflow
63807		 slt   $19,$8,$0        	 # Set Sign
63808		 sltiu $18,$8,1         	 # Set Zero
63809		 addiu $15,$15,-54
63810		 bgez  $15,3f
63811		 lhu   $24,0x00($23)    	 # Delay slot
63812		 j     MainExit
63813	3:
63814		 sll   $7,$24,2         	 # Delay slot
63815		 addu  $7,$7,$30
63816		 lw    $7,0x00($7)
63817		 jr    $7
63818		 nop                    	 # Delay slot
63819
63820OP0_4e77:				#:
63821		 lw    $16,0x3C($21)
63822		 lw    $25,0x80($21)
63823		 sw    $15,m68k_ICount
63824		 or    $4,$0,$16
63825		 jalr  $25
63826		 sw    $23,0x4C($21)    	 # Delay slot
63827		 lw    $15,m68k_ICount
63828		 addiu $8,$16,6
63829		 sw    $8,0x3C($21)
63830		 addiu $16,$16,2
63831		 or    $17,$0,$2
63832		 lw    $25,0x84($21)
63833		 sw    $15,m68k_ICount
63834		 or    $4,$0,$16
63835		 jalr  $25
63836		 sw    $23,0x4C($21)    	 # Delay slot
63837		 lw    $15,m68k_ICount
63838		 or    $8,$0,$2
63839		 or    $2,$0,$17
63840		 or    $20,$0,$2
63841		 or    $19,$0,$2
63842		 or    $18,$0,$2
63843		 or    $17,$0,$2
63844		 or    $16,$0,$2
63845		 andi  $20,$20,0x10
63846		 andi  $19,$19,0x08
63847		 andi  $18,$18,0x04
63848		 andi  $17,$17,0x02
63849		 andi  $16,$16,0x01
63850		 srl   $20,$20,4
63851		 srl   $19,$19,3
63852		 srl   $18,$18,2
63853		 srl   $17,$17,1
63854		 andi  $25,$8,0x01
63855		 beq   $25,$0,2f
63856		 addu  $23,$22,$8     	 # Delay slot
63857		 addiu $23,$23,-2
63858		 jal   Exception
63859		 ori   $2,$0,3
63860
63861		 addiu $15,$15,-20
63862		 bgez  $15,3f
63863		 lhu   $24,0x00($23)    	 # Delay slot
63864		 j     MainExit
63865	3:
63866		 sll   $7,$24,2         	 # Delay slot
63867		 addu  $7,$7,$30
63868		 lw    $7,0x00($7)
63869		 jr    $7
63870		 nop                    	 # Delay slot
63871
63872	2:
63873		 sw    $8,0x74($21)
63874		 lw    $6,mem_amask
63875		 lw    $25,0x94($21)
63876		 and   $23,$8,$6
63877		 sw    $15,m68k_ICount
63878		 jalr  $25
63879		 or    $4,$0,$23   	 # Delay slot
63880		 lw    $15,m68k_ICount
63881		 lw    $22,OP_ROM
63882		 addu  $23,$23,$22
63883 # End of Banking code:
63884		 addiu $15,$15,-20
63885		 bgez  $15,3f
63886		 lhu   $24,0x00($23)    	 # Delay slot
63887		 j     MainExit
63888	3:
63889		 sll   $7,$24,2         	 # Delay slot
63890		 addu  $7,$7,$30
63891		 lw    $7,0x00($7)
63892		 jr    $7
63893		 nop                    	 # Delay slot
63894
63895OP0_4e75:				#:
63896		 lw    $4,0x3C($21)
63897		 addiu $8,$4,4
63898		 sw    $8,0x3C($21)
63899		 lw    $25,0x84($21)
63900		 sw    $15,m68k_ICount
63901		 jalr  $25
63902		 sw    $23,0x4C($21)    	 # Delay slot
63903		 lw    $15,m68k_ICount
63904		 or    $8,$0,$2
63905		 andi  $25,$8,0x01
63906		 beq   $25,$0,2f
63907		 addu  $23,$22,$8     	 # Delay slot
63908		 addiu $23,$23,-2
63909		 jal   Exception
63910		 ori   $2,$0,3
63911
63912		 addiu $15,$15,-16
63913		 bgez  $15,3f
63914		 lhu   $24,0x00($23)    	 # Delay slot
63915		 j     MainExit
63916	3:
63917		 sll   $7,$24,2         	 # Delay slot
63918		 addu  $7,$7,$30
63919		 lw    $7,0x00($7)
63920		 jr    $7
63921		 nop                    	 # Delay slot
63922
63923	2:
63924		 sw    $8,0x74($21)
63925		 lw    $6,mem_amask
63926		 lw    $25,0x94($21)
63927		 and   $23,$8,$6
63928		 sw    $15,m68k_ICount
63929		 jalr  $25
63930		 or    $4,$0,$23   	 # Delay slot
63931		 lw    $15,m68k_ICount
63932		 lw    $22,OP_ROM
63933		 addu  $23,$23,$22
63934 # End of Banking code:
63935		 addiu $15,$15,-16
63936		 bgez  $15,3f
63937		 lhu   $24,0x00($23)    	 # Delay slot
63938		 j     MainExit
63939	3:
63940		 sll   $7,$24,2         	 # Delay slot
63941		 addu  $7,$7,$30
63942		 lw    $7,0x00($7)
63943		 jr    $7
63944		 nop                    	 # Delay slot
63945
63946OP0_4e90:				#:
63947		 addiu $23,$23,2
63948
63949		 andi  $24,$24,0x07
63950		 sll   $24,$24,2
63951		 addu  $24,$24,$21
63952		 lw    $14,0x20($24)
63953		 lw    $5,0x74($21)
63954		 lui   $25,0xFF00
63955		 lw    $4,0x3C($21)     	 # Push onto Stack
63956		 and   $5,$5,$25
63957		 subu  $25,$23,$22
63958		 addiu $4,$4,-4
63959		 sw    $4,0x3C($21)
63960		 or    $5,$5,$25
63961		 lw    $25,0x90($21)
63962		 sw    $15,m68k_ICount
63963		 sw    $14,0x44($29)
63964		 jalr  $25
63965		 sw    $23,0x4C($21)    	 # Delay slot
63966		 lw    $14,0x44($29)
63967		 lw    $15,m68k_ICount
63968		 andi  $25,$14,0x01
63969		 beq   $25,$0,2f
63970		 addu  $23,$22,$14     	 # Delay slot
63971		 addiu $23,$23,-2
63972		 jal   Exception
63973		 ori   $2,$0,3
63974
63975		 addiu $15,$15,-24
63976		 bgez  $15,3f
63977		 lhu   $24,0x00($23)    	 # Delay slot
63978		 j     MainExit
63979	3:
63980		 sll   $7,$24,2         	 # Delay slot
63981		 addu  $7,$7,$30
63982		 lw    $7,0x00($7)
63983		 jr    $7
63984		 nop                    	 # Delay slot
63985
63986	2:
63987		 sw    $14,0x74($21)
63988		 lw    $6,mem_amask
63989		 lw    $25,0x94($21)
63990		 and   $23,$14,$6
63991		 sw    $15,m68k_ICount
63992		 jalr  $25
63993		 or    $4,$0,$23   	 # Delay slot
63994		 lw    $15,m68k_ICount
63995		 lw    $22,OP_ROM
63996		 addu  $23,$23,$22
63997 # End of Banking code:
63998		 addiu $15,$15,-24
63999		 bgez  $15,3f
64000		 lhu   $24,0x00($23)    	 # Delay slot
64001		 j     MainExit
64002	3:
64003		 sll   $7,$24,2         	 # Delay slot
64004		 addu  $7,$7,$30
64005		 lw    $7,0x00($7)
64006		 jr    $7
64007		 nop                    	 # Delay slot
64008
64009OP0_4ea8:				#:
64010		 addiu $23,$23,2
64011
64012		 andi  $24,$24,0x07
64013		 lh    $7,0x00($23)
64014		 sll   $24,$24,2
64015		 addu  $24,$24,$21
64016		 lw    $14,0x20($24)
64017		 addiu $23,$23,2
64018		 addu  $14,$14,$7
64019		 lw    $5,0x74($21)
64020		 lui   $25,0xFF00
64021		 lw    $4,0x3C($21)     	 # Push onto Stack
64022		 and   $5,$5,$25
64023		 subu  $25,$23,$22
64024		 addiu $4,$4,-4
64025		 sw    $4,0x3C($21)
64026		 or    $5,$5,$25
64027		 lw    $25,0x90($21)
64028		 sw    $15,m68k_ICount
64029		 sw    $14,0x44($29)
64030		 jalr  $25
64031		 sw    $23,0x4C($21)    	 # Delay slot
64032		 lw    $14,0x44($29)
64033		 lw    $15,m68k_ICount
64034		 andi  $25,$14,0x01
64035		 beq   $25,$0,2f
64036		 addu  $23,$22,$14     	 # Delay slot
64037		 addiu $23,$23,-2
64038		 jal   Exception
64039		 ori   $2,$0,3
64040
64041		 addiu $15,$15,-30
64042		 bgez  $15,3f
64043		 lhu   $24,0x00($23)    	 # Delay slot
64044		 j     MainExit
64045	3:
64046		 sll   $7,$24,2         	 # Delay slot
64047		 addu  $7,$7,$30
64048		 lw    $7,0x00($7)
64049		 jr    $7
64050		 nop                    	 # Delay slot
64051
64052	2:
64053		 sw    $14,0x74($21)
64054		 lw    $6,mem_amask
64055		 lw    $25,0x94($21)
64056		 and   $23,$14,$6
64057		 sw    $15,m68k_ICount
64058		 jalr  $25
64059		 or    $4,$0,$23   	 # Delay slot
64060		 lw    $15,m68k_ICount
64061		 lw    $22,OP_ROM
64062		 addu  $23,$23,$22
64063 # End of Banking code:
64064		 addiu $15,$15,-30
64065		 bgez  $15,3f
64066		 lhu   $24,0x00($23)    	 # Delay slot
64067		 j     MainExit
64068	3:
64069		 sll   $7,$24,2         	 # Delay slot
64070		 addu  $7,$7,$30
64071		 lw    $7,0x00($7)
64072		 jr    $7
64073		 nop                    	 # Delay slot
64074
64075OP0_4eb0:				#:
64076		 addiu $23,$23,2
64077
64078		 andi  $24,$24,0x07
64079		 sll   $24,$24,2
64080		 addu  $24,$24,$21
64081		 lw    $14,0x20($24)
64082		 lhu   $7,0x00($23)
64083		 addiu $23,$23,2
64084		 seb   $6,$7
64085		 or    $25,$0,$7
64086		 srl   $7,$7,12
64087		 andi  $25,$25,0x0800
64088		 sll   $7,$7,2
64089		 addu  $7,$7,$21
64090		 bne   $25,$0,0f
64091		 lw    $25,0x00($7)      	 # Delay slot
64092		 seh   $25,$25
64093	0:
64094		 addu  $25,$14,$25
64095		 addu  $14,$25,$6
64096		 lw    $5,0x74($21)
64097		 lui   $25,0xFF00
64098		 lw    $4,0x3C($21)     	 # Push onto Stack
64099		 and   $5,$5,$25
64100		 subu  $25,$23,$22
64101		 addiu $4,$4,-4
64102		 sw    $4,0x3C($21)
64103		 or    $5,$5,$25
64104		 lw    $25,0x90($21)
64105		 sw    $15,m68k_ICount
64106		 sw    $14,0x44($29)
64107		 jalr  $25
64108		 sw    $23,0x4C($21)    	 # Delay slot
64109		 lw    $14,0x44($29)
64110		 lw    $15,m68k_ICount
64111		 andi  $25,$14,0x01
64112		 beq   $25,$0,2f
64113		 addu  $23,$22,$14     	 # Delay slot
64114		 addiu $23,$23,-2
64115		 jal   Exception
64116		 ori   $2,$0,3
64117
64118		 addiu $15,$15,-36
64119		 bgez  $15,3f
64120		 lhu   $24,0x00($23)    	 # Delay slot
64121		 j     MainExit
64122	3:
64123		 sll   $7,$24,2         	 # Delay slot
64124		 addu  $7,$7,$30
64125		 lw    $7,0x00($7)
64126		 jr    $7
64127		 nop                    	 # Delay slot
64128
64129	2:
64130		 sw    $14,0x74($21)
64131		 lw    $6,mem_amask
64132		 lw    $25,0x94($21)
64133		 and   $23,$14,$6
64134		 sw    $15,m68k_ICount
64135		 jalr  $25
64136		 or    $4,$0,$23   	 # Delay slot
64137		 lw    $15,m68k_ICount
64138		 lw    $22,OP_ROM
64139		 addu  $23,$23,$22
64140 # End of Banking code:
64141		 addiu $15,$15,-36
64142		 bgez  $15,3f
64143		 lhu   $24,0x00($23)    	 # Delay slot
64144		 j     MainExit
64145	3:
64146		 sll   $7,$24,2         	 # Delay slot
64147		 addu  $7,$7,$30
64148		 lw    $7,0x00($7)
64149		 jr    $7
64150		 nop                    	 # Delay slot
64151
64152OP0_4eb8:				#:
64153		 addiu $23,$23,2
64154
64155		 lh    $14,0x00($23)
64156		 addiu $23,$23,2
64157		 lw    $5,0x74($21)
64158		 lui   $25,0xFF00
64159		 lw    $4,0x3C($21)     	 # Push onto Stack
64160		 and   $5,$5,$25
64161		 subu  $25,$23,$22
64162		 addiu $4,$4,-4
64163		 sw    $4,0x3C($21)
64164		 or    $5,$5,$25
64165		 lw    $25,0x90($21)
64166		 sw    $15,m68k_ICount
64167		 sw    $14,0x44($29)
64168		 jalr  $25
64169		 sw    $23,0x4C($21)    	 # Delay slot
64170		 lw    $14,0x44($29)
64171		 lw    $15,m68k_ICount
64172		 andi  $25,$14,0x01
64173		 beq   $25,$0,2f
64174		 addu  $23,$22,$14     	 # Delay slot
64175		 addiu $23,$23,-2
64176		 jal   Exception
64177		 ori   $2,$0,3
64178
64179		 addiu $15,$15,-30
64180		 bgez  $15,3f
64181		 lhu   $24,0x00($23)    	 # Delay slot
64182		 j     MainExit
64183	3:
64184		 sll   $7,$24,2         	 # Delay slot
64185		 addu  $7,$7,$30
64186		 lw    $7,0x00($7)
64187		 jr    $7
64188		 nop                    	 # Delay slot
64189
64190	2:
64191		 sw    $14,0x74($21)
64192		 lw    $6,mem_amask
64193		 lw    $25,0x94($21)
64194		 and   $23,$14,$6
64195		 sw    $15,m68k_ICount
64196		 jalr  $25
64197		 or    $4,$0,$23   	 # Delay slot
64198		 lw    $15,m68k_ICount
64199		 lw    $22,OP_ROM
64200		 addu  $23,$23,$22
64201 # End of Banking code:
64202		 addiu $15,$15,-30
64203		 bgez  $15,3f
64204		 lhu   $24,0x00($23)    	 # Delay slot
64205		 j     MainExit
64206	3:
64207		 sll   $7,$24,2         	 # Delay slot
64208		 addu  $7,$7,$30
64209		 lw    $7,0x00($7)
64210		 jr    $7
64211		 nop                    	 # Delay slot
64212
64213OP0_4eb9:				#:
64214		 addiu $23,$23,2
64215
64216		 lhu   $14,0x00($23)
64217		 lhu   $25,0x02($23)
64218		 sll   $14,$14,16
64219		 or    $14,$14,$25
64220		 addiu $23,$23,4
64221		 lw    $5,0x74($21)
64222		 lui   $25,0xFF00
64223		 lw    $4,0x3C($21)     	 # Push onto Stack
64224		 and   $5,$5,$25
64225		 subu  $25,$23,$22
64226		 addiu $4,$4,-4
64227		 sw    $4,0x3C($21)
64228		 or    $5,$5,$25
64229		 lw    $25,0x90($21)
64230		 sw    $15,m68k_ICount
64231		 sw    $14,0x44($29)
64232		 jalr  $25
64233		 sw    $23,0x4C($21)    	 # Delay slot
64234		 lw    $14,0x44($29)
64235		 lw    $15,m68k_ICount
64236		 andi  $25,$14,0x01
64237		 beq   $25,$0,2f
64238		 addu  $23,$22,$14     	 # Delay slot
64239		 addiu $23,$23,-2
64240		 jal   Exception
64241		 ori   $2,$0,3
64242
64243		 addiu $15,$15,-34
64244		 bgez  $15,3f
64245		 lhu   $24,0x00($23)    	 # Delay slot
64246		 j     MainExit
64247	3:
64248		 sll   $7,$24,2         	 # Delay slot
64249		 addu  $7,$7,$30
64250		 lw    $7,0x00($7)
64251		 jr    $7
64252		 nop                    	 # Delay slot
64253
64254	2:
64255		 sw    $14,0x74($21)
64256		 lw    $6,mem_amask
64257		 lw    $25,0x94($21)
64258		 and   $23,$14,$6
64259		 sw    $15,m68k_ICount
64260		 jalr  $25
64261		 or    $4,$0,$23   	 # Delay slot
64262		 lw    $15,m68k_ICount
64263		 lw    $22,OP_ROM
64264		 addu  $23,$23,$22
64265 # End of Banking code:
64266		 addiu $15,$15,-34
64267		 bgez  $15,3f
64268		 lhu   $24,0x00($23)    	 # Delay slot
64269		 j     MainExit
64270	3:
64271		 sll   $7,$24,2         	 # Delay slot
64272		 addu  $7,$7,$30
64273		 lw    $7,0x00($7)
64274		 jr    $7
64275		 nop                    	 # Delay slot
64276
64277OP0_4eba:				#:
64278		 addiu $23,$23,2
64279
64280		 lh    $7,0x00($23)
64281		 subu  $25,$23,$22
64282		 addu  $14,$25,$7       	 # Add Offset to PC
64283		 addiu $23,$23,2
64284		 lw    $5,0x74($21)
64285		 lui   $25,0xFF00
64286		 lw    $4,0x3C($21)     	 # Push onto Stack
64287		 and   $5,$5,$25
64288		 subu  $25,$23,$22
64289		 addiu $4,$4,-4
64290		 sw    $4,0x3C($21)
64291		 or    $5,$5,$25
64292		 lw    $25,0x90($21)
64293		 sw    $15,m68k_ICount
64294		 sw    $14,0x44($29)
64295		 jalr  $25
64296		 sw    $23,0x4C($21)    	 # Delay slot
64297		 lw    $14,0x44($29)
64298		 lw    $15,m68k_ICount
64299		 andi  $25,$14,0x01
64300		 beq   $25,$0,2f
64301		 addu  $23,$22,$14     	 # Delay slot
64302		 addiu $23,$23,-2
64303		 jal   Exception
64304		 ori   $2,$0,3
64305
64306		 addiu $15,$15,-30
64307		 bgez  $15,3f
64308		 lhu   $24,0x00($23)    	 # Delay slot
64309		 j     MainExit
64310	3:
64311		 sll   $7,$24,2         	 # Delay slot
64312		 addu  $7,$7,$30
64313		 lw    $7,0x00($7)
64314		 jr    $7
64315		 nop                    	 # Delay slot
64316
64317	2:
64318		 sw    $14,0x74($21)
64319		 lw    $6,mem_amask
64320		 lw    $25,0x94($21)
64321		 and   $23,$14,$6
64322		 sw    $15,m68k_ICount
64323		 jalr  $25
64324		 or    $4,$0,$23   	 # Delay slot
64325		 lw    $15,m68k_ICount
64326		 lw    $22,OP_ROM
64327		 addu  $23,$23,$22
64328 # End of Banking code:
64329		 addiu $15,$15,-30
64330		 bgez  $15,3f
64331		 lhu   $24,0x00($23)    	 # Delay slot
64332		 j     MainExit
64333	3:
64334		 sll   $7,$24,2         	 # Delay slot
64335		 addu  $7,$7,$30
64336		 lw    $7,0x00($7)
64337		 jr    $7
64338		 nop                    	 # Delay slot
64339
64340OP0_4ebb:				#:
64341		 addiu $23,$23,2
64342
64343		 subu  $14,$23,$22       	 # Get PC
64344		 lhu   $7,0x00($23)
64345		 addiu $23,$23,2
64346		 seb   $6,$7
64347		 or    $25,$0,$7
64348		 srl   $7,$7,12
64349		 andi  $25,$25,0x0800
64350		 sll   $7,$7,2
64351		 addu  $7,$7,$21
64352		 bne   $25,$0,0f
64353		 lw    $25,0x00($7)      	 # Delay slot
64354		 seh   $25,$25
64355	0:
64356		 addu  $25,$14,$25
64357		 addu  $14,$25,$6
64358		 lw    $5,0x74($21)
64359		 lui   $25,0xFF00
64360		 lw    $4,0x3C($21)     	 # Push onto Stack
64361		 and   $5,$5,$25
64362		 subu  $25,$23,$22
64363		 addiu $4,$4,-4
64364		 sw    $4,0x3C($21)
64365		 or    $5,$5,$25
64366		 lw    $25,0x90($21)
64367		 sw    $15,m68k_ICount
64368		 sw    $14,0x44($29)
64369		 jalr  $25
64370		 sw    $23,0x4C($21)    	 # Delay slot
64371		 lw    $14,0x44($29)
64372		 lw    $15,m68k_ICount
64373		 andi  $25,$14,0x01
64374		 beq   $25,$0,2f
64375		 addu  $23,$22,$14     	 # Delay slot
64376		 addiu $23,$23,-2
64377		 jal   Exception
64378		 ori   $2,$0,3
64379
64380		 addiu $15,$15,-32
64381		 bgez  $15,3f
64382		 lhu   $24,0x00($23)    	 # Delay slot
64383		 j     MainExit
64384	3:
64385		 sll   $7,$24,2         	 # Delay slot
64386		 addu  $7,$7,$30
64387		 lw    $7,0x00($7)
64388		 jr    $7
64389		 nop                    	 # Delay slot
64390
64391	2:
64392		 sw    $14,0x74($21)
64393		 lw    $6,mem_amask
64394		 lw    $25,0x94($21)
64395		 and   $23,$14,$6
64396		 sw    $15,m68k_ICount
64397		 jalr  $25
64398		 or    $4,$0,$23   	 # Delay slot
64399		 lw    $15,m68k_ICount
64400		 lw    $22,OP_ROM
64401		 addu  $23,$23,$22
64402 # End of Banking code:
64403		 addiu $15,$15,-32
64404		 bgez  $15,3f
64405		 lhu   $24,0x00($23)    	 # Delay slot
64406		 j     MainExit
64407	3:
64408		 sll   $7,$24,2         	 # Delay slot
64409		 addu  $7,$7,$30
64410		 lw    $7,0x00($7)
64411		 jr    $7
64412		 nop                    	 # Delay slot
64413
64414OP0_4ed0:				#:
64415		 andi  $24,$24,0x07
64416		 sll   $24,$24,2
64417		 addu  $24,$24,$21
64418		 lw    $14,0x20($24)
64419		 andi  $25,$14,0x01
64420		 beq   $25,$0,2f
64421		 addu  $23,$22,$14     	 # Delay slot
64422		 addiu $23,$23,-2
64423		 jal   Exception
64424		 ori   $2,$0,3
64425
64426		 addiu $15,$15,-16
64427		 bgez  $15,3f
64428		 lhu   $24,0x00($23)    	 # Delay slot
64429		 j     MainExit
64430	3:
64431		 sll   $7,$24,2         	 # Delay slot
64432		 addu  $7,$7,$30
64433		 lw    $7,0x00($7)
64434		 jr    $7
64435		 nop                    	 # Delay slot
64436
64437	2:
64438		 sw    $14,0x74($21)
64439		 lw    $6,mem_amask
64440		 lw    $25,0x94($21)
64441		 and   $23,$14,$6
64442		 sw    $15,m68k_ICount
64443		 jalr  $25
64444		 or    $4,$0,$23   	 # Delay slot
64445		 lw    $15,m68k_ICount
64446		 lw    $22,OP_ROM
64447		 addu  $23,$23,$22
64448 # End of Banking code:
64449		 addiu $15,$15,-16
64450		 bgez  $15,3f
64451		 lhu   $24,0x00($23)    	 # Delay slot
64452		 j     MainExit
64453	3:
64454		 sll   $7,$24,2         	 # Delay slot
64455		 addu  $7,$7,$30
64456		 lw    $7,0x00($7)
64457		 jr    $7
64458		 nop                    	 # Delay slot
64459
64460OP0_4ee8:				#:
64461		 addiu $23,$23,2
64462
64463		 andi  $24,$24,0x07
64464		 lh    $7,0x00($23)
64465		 sll   $24,$24,2
64466		 addu  $24,$24,$21
64467		 lw    $14,0x20($24)
64468		 addiu $23,$23,2
64469		 addu  $14,$14,$7
64470		 andi  $25,$14,0x01
64471		 beq   $25,$0,2f
64472		 addu  $23,$22,$14     	 # Delay slot
64473		 addiu $23,$23,-2
64474		 jal   Exception
64475		 ori   $2,$0,3
64476
64477		 addiu $15,$15,-22
64478		 bgez  $15,3f
64479		 lhu   $24,0x00($23)    	 # Delay slot
64480		 j     MainExit
64481	3:
64482		 sll   $7,$24,2         	 # Delay slot
64483		 addu  $7,$7,$30
64484		 lw    $7,0x00($7)
64485		 jr    $7
64486		 nop                    	 # Delay slot
64487
64488	2:
64489		 sw    $14,0x74($21)
64490		 lw    $6,mem_amask
64491		 lw    $25,0x94($21)
64492		 and   $23,$14,$6
64493		 sw    $15,m68k_ICount
64494		 jalr  $25
64495		 or    $4,$0,$23   	 # Delay slot
64496		 lw    $15,m68k_ICount
64497		 lw    $22,OP_ROM
64498		 addu  $23,$23,$22
64499 # End of Banking code:
64500		 addiu $15,$15,-22
64501		 bgez  $15,3f
64502		 lhu   $24,0x00($23)    	 # Delay slot
64503		 j     MainExit
64504	3:
64505		 sll   $7,$24,2         	 # Delay slot
64506		 addu  $7,$7,$30
64507		 lw    $7,0x00($7)
64508		 jr    $7
64509		 nop                    	 # Delay slot
64510
64511OP0_4ef0:				#:
64512		 addiu $23,$23,2
64513
64514		 andi  $24,$24,0x07
64515		 sll   $24,$24,2
64516		 addu  $24,$24,$21
64517		 lw    $14,0x20($24)
64518		 lhu   $7,0x00($23)
64519		 addiu $23,$23,2
64520		 seb   $6,$7
64521		 or    $25,$0,$7
64522		 srl   $7,$7,12
64523		 andi  $25,$25,0x0800
64524		 sll   $7,$7,2
64525		 addu  $7,$7,$21
64526		 bne   $25,$0,0f
64527		 lw    $25,0x00($7)      	 # Delay slot
64528		 seh   $25,$25
64529	0:
64530		 addu  $25,$14,$25
64531		 addu  $14,$25,$6
64532		 andi  $25,$14,0x01
64533		 beq   $25,$0,2f
64534		 addu  $23,$22,$14     	 # Delay slot
64535		 addiu $23,$23,-2
64536		 jal   Exception
64537		 ori   $2,$0,3
64538
64539		 addiu $15,$15,-28
64540		 bgez  $15,3f
64541		 lhu   $24,0x00($23)    	 # Delay slot
64542		 j     MainExit
64543	3:
64544		 sll   $7,$24,2         	 # Delay slot
64545		 addu  $7,$7,$30
64546		 lw    $7,0x00($7)
64547		 jr    $7
64548		 nop                    	 # Delay slot
64549
64550	2:
64551		 sw    $14,0x74($21)
64552		 lw    $6,mem_amask
64553		 lw    $25,0x94($21)
64554		 and   $23,$14,$6
64555		 sw    $15,m68k_ICount
64556		 jalr  $25
64557		 or    $4,$0,$23   	 # Delay slot
64558		 lw    $15,m68k_ICount
64559		 lw    $22,OP_ROM
64560		 addu  $23,$23,$22
64561 # End of Banking code:
64562		 addiu $15,$15,-28
64563		 bgez  $15,3f
64564		 lhu   $24,0x00($23)    	 # Delay slot
64565		 j     MainExit
64566	3:
64567		 sll   $7,$24,2         	 # Delay slot
64568		 addu  $7,$7,$30
64569		 lw    $7,0x00($7)
64570		 jr    $7
64571		 nop                    	 # Delay slot
64572
64573OP0_4ef8:				#:
64574		 addiu $23,$23,2
64575
64576		 lh    $14,0x00($23)
64577		 addiu $23,$23,2
64578		 andi  $25,$14,0x01
64579		 beq   $25,$0,2f
64580		 addu  $23,$22,$14     	 # Delay slot
64581		 addiu $23,$23,-2
64582		 jal   Exception
64583		 ori   $2,$0,3
64584
64585		 addiu $15,$15,-22
64586		 bgez  $15,3f
64587		 lhu   $24,0x00($23)    	 # Delay slot
64588		 j     MainExit
64589	3:
64590		 sll   $7,$24,2         	 # Delay slot
64591		 addu  $7,$7,$30
64592		 lw    $7,0x00($7)
64593		 jr    $7
64594		 nop                    	 # Delay slot
64595
64596	2:
64597		 sw    $14,0x74($21)
64598		 lw    $6,mem_amask
64599		 lw    $25,0x94($21)
64600		 and   $23,$14,$6
64601		 sw    $15,m68k_ICount
64602		 jalr  $25
64603		 or    $4,$0,$23   	 # Delay slot
64604		 lw    $15,m68k_ICount
64605		 lw    $22,OP_ROM
64606		 addu  $23,$23,$22
64607 # End of Banking code:
64608		 addiu $15,$15,-22
64609		 bgez  $15,3f
64610		 lhu   $24,0x00($23)    	 # Delay slot
64611		 j     MainExit
64612	3:
64613		 sll   $7,$24,2         	 # Delay slot
64614		 addu  $7,$7,$30
64615		 lw    $7,0x00($7)
64616		 jr    $7
64617		 nop                    	 # Delay slot
64618
64619OP0_4ef9:				#:
64620		 addiu $23,$23,2
64621
64622		 lhu   $14,0x00($23)
64623		 lhu   $25,0x02($23)
64624		 sll   $14,$14,16
64625		 or    $14,$14,$25
64626		 addiu $23,$23,4
64627		 andi  $25,$14,0x01
64628		 beq   $25,$0,2f
64629		 addu  $23,$22,$14     	 # Delay slot
64630		 addiu $23,$23,-2
64631		 jal   Exception
64632		 ori   $2,$0,3
64633
64634		 addiu $15,$15,-26
64635		 bgez  $15,3f
64636		 lhu   $24,0x00($23)    	 # Delay slot
64637		 j     MainExit
64638	3:
64639		 sll   $7,$24,2         	 # Delay slot
64640		 addu  $7,$7,$30
64641		 lw    $7,0x00($7)
64642		 jr    $7
64643		 nop                    	 # Delay slot
64644
64645	2:
64646		 sw    $14,0x74($21)
64647		 lw    $6,mem_amask
64648		 lw    $25,0x94($21)
64649		 and   $23,$14,$6
64650		 sw    $15,m68k_ICount
64651		 jalr  $25
64652		 or    $4,$0,$23   	 # Delay slot
64653		 lw    $15,m68k_ICount
64654		 lw    $22,OP_ROM
64655		 addu  $23,$23,$22
64656 # End of Banking code:
64657		 addiu $15,$15,-26
64658		 bgez  $15,3f
64659		 lhu   $24,0x00($23)    	 # Delay slot
64660		 j     MainExit
64661	3:
64662		 sll   $7,$24,2         	 # Delay slot
64663		 addu  $7,$7,$30
64664		 lw    $7,0x00($7)
64665		 jr    $7
64666		 nop                    	 # Delay slot
64667
64668OP0_4efa:				#:
64669		 addiu $23,$23,2
64670
64671		 lh    $7,0x00($23)
64672		 subu  $25,$23,$22
64673		 addu  $14,$25,$7       	 # Add Offset to PC
64674		 addiu $23,$23,2
64675		 andi  $25,$14,0x01
64676		 beq   $25,$0,2f
64677		 addu  $23,$22,$14     	 # Delay slot
64678		 addiu $23,$23,-2
64679		 jal   Exception
64680		 ori   $2,$0,3
64681
64682		 addiu $15,$15,-22
64683		 bgez  $15,3f
64684		 lhu   $24,0x00($23)    	 # Delay slot
64685		 j     MainExit
64686	3:
64687		 sll   $7,$24,2         	 # Delay slot
64688		 addu  $7,$7,$30
64689		 lw    $7,0x00($7)
64690		 jr    $7
64691		 nop                    	 # Delay slot
64692
64693	2:
64694		 sw    $14,0x74($21)
64695		 lw    $6,mem_amask
64696		 lw    $25,0x94($21)
64697		 and   $23,$14,$6
64698		 sw    $15,m68k_ICount
64699		 jalr  $25
64700		 or    $4,$0,$23   	 # Delay slot
64701		 lw    $15,m68k_ICount
64702		 lw    $22,OP_ROM
64703		 addu  $23,$23,$22
64704 # End of Banking code:
64705		 addiu $15,$15,-22
64706		 bgez  $15,3f
64707		 lhu   $24,0x00($23)    	 # Delay slot
64708		 j     MainExit
64709	3:
64710		 sll   $7,$24,2         	 # Delay slot
64711		 addu  $7,$7,$30
64712		 lw    $7,0x00($7)
64713		 jr    $7
64714		 nop                    	 # Delay slot
64715
64716OP0_4efb:				#:
64717		 addiu $23,$23,2
64718
64719		 subu  $14,$23,$22       	 # Get PC
64720		 lhu   $7,0x00($23)
64721		 addiu $23,$23,2
64722		 seb   $6,$7
64723		 or    $25,$0,$7
64724		 srl   $7,$7,12
64725		 andi  $25,$25,0x0800
64726		 sll   $7,$7,2
64727		 addu  $7,$7,$21
64728		 bne   $25,$0,0f
64729		 lw    $25,0x00($7)      	 # Delay slot
64730		 seh   $25,$25
64731	0:
64732		 addu  $25,$14,$25
64733		 addu  $14,$25,$6
64734		 andi  $25,$14,0x01
64735		 beq   $25,$0,2f
64736		 addu  $23,$22,$14     	 # Delay slot
64737		 addiu $23,$23,-2
64738		 jal   Exception
64739		 ori   $2,$0,3
64740
64741		 addiu $15,$15,-24
64742		 bgez  $15,3f
64743		 lhu   $24,0x00($23)    	 # Delay slot
64744		 j     MainExit
64745	3:
64746		 sll   $7,$24,2         	 # Delay slot
64747		 addu  $7,$7,$30
64748		 lw    $7,0x00($7)
64749		 jr    $7
64750		 nop                    	 # Delay slot
64751
64752	2:
64753		 sw    $14,0x74($21)
64754		 lw    $6,mem_amask
64755		 lw    $25,0x94($21)
64756		 and   $23,$14,$6
64757		 sw    $15,m68k_ICount
64758		 jalr  $25
64759		 or    $4,$0,$23   	 # Delay slot
64760		 lw    $15,m68k_ICount
64761		 lw    $22,OP_ROM
64762		 addu  $23,$23,$22
64763 # End of Banking code:
64764		 addiu $15,$15,-24
64765		 bgez  $15,3f
64766		 lhu   $24,0x00($23)    	 # Delay slot
64767		 j     MainExit
64768	3:
64769		 sll   $7,$24,2         	 # Delay slot
64770		 addu  $7,$7,$30
64771		 lw    $7,0x00($7)
64772		 jr    $7
64773		 nop                    	 # Delay slot
64774
64775OP0_4800:				#:
64776		 addiu $23,$23,2
64777
64778		 andi  $24,$24,0x07
64779		 sll   $24,$24,2
64780		 addu  $24,$24,$21
64781		 lbu   $2,0x00($24)
64782		 subu  $17,$0,$2
64783		 subu  $17,$17,$20
64784		 andi  $17,$17,0xFF
64785		 andi  $9,$2,0x0F
64786		 andi  $8,$2,0xF0
64787		 subu  $9,$0,$9
64788		 subu  $9,$9,$20
64789		 subu  $8,$0,$8
64790		 sltiu $10,$9,10
64791		 xori  $10,$10,1
64792		 sll   $10,$10,1
64793		 subu  $9,$9,$10
64794		 sll   $10,$10,1
64795		 subu  $9,$9,$10
64796		 addu  $2,$8,$9
64797		 sltiu $16,$2,0x9a
64798		 xori  $16,$16,1        	 # Set Carry
64799		 sll   $10,$16,5
64800		 addu  $2,$2,$10
64801		 sll   $10,$10,2
64802		 addu  $2,$2,$10
64803		 xor   $19,$17,$2
64804		 and   $17,$17,$19
64805		 srl   $17,$17,7        	 # Set Overflow
64806		 sltiu $25,$2,1
64807		 and   $18,$18,$25       	 # Set Zero
64808		 srl   $19,$2,7         	 # Set Sign
64809		 or    $20,$0,$16       	 # Copy Carry to X
64810		 sb    $2,0x00($24)
64811		 addiu $15,$15,-6
64812		 bgez  $15,3f
64813		 lhu   $24,0x00($23)    	 # Delay slot
64814		 j     MainExit
64815	3:
64816		 sll   $7,$24,2         	 # Delay slot
64817		 addu  $7,$7,$30
64818		 lw    $7,0x00($7)
64819		 jr    $7
64820		 nop                    	 # Delay slot
64821
64822OP0_4810:				#:
64823		 addiu $23,$23,2
64824
64825		 andi  $24,$24,0x07
64826		 sll   $24,$24,2
64827		 addu  $24,$24,$21
64828		 lw    $14,0x20($24)
64829		 lw    $25,0x7C($21)
64830		 sw    $15,m68k_ICount
64831		 sw    $14,0x44($29)
64832		 or    $4,$0,$14
64833		 jalr  $25
64834		 sw    $23,0x4C($21)    	 # Delay slot
64835		 lw    $14,0x44($29)
64836		 lw    $15,m68k_ICount
64837		 subu  $17,$0,$2
64838		 subu  $17,$17,$20
64839		 andi  $17,$17,0xFF
64840		 andi  $9,$2,0x0F
64841		 andi  $8,$2,0xF0
64842		 subu  $9,$0,$9
64843		 subu  $9,$9,$20
64844		 subu  $8,$0,$8
64845		 sltiu $10,$9,10
64846		 xori  $10,$10,1
64847		 sll   $10,$10,1
64848		 subu  $9,$9,$10
64849		 sll   $10,$10,1
64850		 subu  $9,$9,$10
64851		 addu  $2,$8,$9
64852		 sltiu $16,$2,0x9a
64853		 xori  $16,$16,1        	 # Set Carry
64854		 sll   $10,$16,5
64855		 addu  $2,$2,$10
64856		 sll   $10,$10,2
64857		 addu  $2,$2,$10
64858		 xor   $19,$17,$2
64859		 and   $17,$17,$19
64860		 srl   $17,$17,7        	 # Set Overflow
64861		 sltiu $25,$2,1
64862		 and   $18,$18,$25       	 # Set Zero
64863		 srl   $19,$2,7         	 # Set Sign
64864		 or    $20,$0,$16       	 # Copy Carry to X
64865		 lw    $25,0x88($21)
64866		 sw    $15,m68k_ICount
64867		 or    $5,$0,$2
64868		 or    $4,$0,$14
64869		 jalr  $25
64870		 sw    $23,0x4C($21)    	 # Delay slot
64871		 lw    $15,m68k_ICount
64872		 addiu $15,$15,-12
64873		 bgez  $15,3f
64874		 lhu   $24,0x00($23)    	 # Delay slot
64875		 j     MainExit
64876	3:
64877		 sll   $7,$24,2         	 # Delay slot
64878		 addu  $7,$7,$30
64879		 lw    $7,0x00($7)
64880		 jr    $7
64881		 nop                    	 # Delay slot
64882
64883OP0_4818:				#:
64884		 addiu $23,$23,2
64885
64886		 andi  $24,$24,0x07
64887		 sll   $24,$24,2
64888		 addu  $24,$24,$21
64889		 lw    $14,0x20($24)
64890		 addiu $25,$14,1
64891		 sw    $25,0x20($24)
64892		 lw    $25,0x7C($21)
64893		 sw    $15,m68k_ICount
64894		 sw    $14,0x44($29)
64895		 or    $4,$0,$14
64896		 jalr  $25
64897		 sw    $23,0x4C($21)    	 # Delay slot
64898		 lw    $14,0x44($29)
64899		 lw    $15,m68k_ICount
64900		 subu  $17,$0,$2
64901		 subu  $17,$17,$20
64902		 andi  $17,$17,0xFF
64903		 andi  $9,$2,0x0F
64904		 andi  $8,$2,0xF0
64905		 subu  $9,$0,$9
64906		 subu  $9,$9,$20
64907		 subu  $8,$0,$8
64908		 sltiu $10,$9,10
64909		 xori  $10,$10,1
64910		 sll   $10,$10,1
64911		 subu  $9,$9,$10
64912		 sll   $10,$10,1
64913		 subu  $9,$9,$10
64914		 addu  $2,$8,$9
64915		 sltiu $16,$2,0x9a
64916		 xori  $16,$16,1        	 # Set Carry
64917		 sll   $10,$16,5
64918		 addu  $2,$2,$10
64919		 sll   $10,$10,2
64920		 addu  $2,$2,$10
64921		 xor   $19,$17,$2
64922		 and   $17,$17,$19
64923		 srl   $17,$17,7        	 # Set Overflow
64924		 sltiu $25,$2,1
64925		 and   $18,$18,$25       	 # Set Zero
64926		 srl   $19,$2,7         	 # Set Sign
64927		 or    $20,$0,$16       	 # Copy Carry to X
64928		 lw    $25,0x88($21)
64929		 sw    $15,m68k_ICount
64930		 or    $5,$0,$2
64931		 or    $4,$0,$14
64932		 jalr  $25
64933		 sw    $23,0x4C($21)    	 # Delay slot
64934		 lw    $15,m68k_ICount
64935		 addiu $15,$15,-12
64936		 bgez  $15,3f
64937		 lhu   $24,0x00($23)    	 # Delay slot
64938		 j     MainExit
64939	3:
64940		 sll   $7,$24,2         	 # Delay slot
64941		 addu  $7,$7,$30
64942		 lw    $7,0x00($7)
64943		 jr    $7
64944		 nop                    	 # Delay slot
64945
64946OP0_481f:				#:
64947		 addiu $23,$23,2
64948
64949		 andi  $24,$24,0x07
64950		 lw    $14,0x3C($21)    	 # Get A7
64951		 addiu $25,$14,2
64952		 sw    $25,0x3C($21)
64953		 lw    $25,0x7C($21)
64954		 sw    $15,m68k_ICount
64955		 sw    $14,0x44($29)
64956		 or    $4,$0,$14
64957		 jalr  $25
64958		 sw    $23,0x4C($21)    	 # Delay slot
64959		 lw    $14,0x44($29)
64960		 lw    $15,m68k_ICount
64961		 subu  $17,$0,$2
64962		 subu  $17,$17,$20
64963		 andi  $17,$17,0xFF
64964		 andi  $9,$2,0x0F
64965		 andi  $8,$2,0xF0
64966		 subu  $9,$0,$9
64967		 subu  $9,$9,$20
64968		 subu  $8,$0,$8
64969		 sltiu $10,$9,10
64970		 xori  $10,$10,1
64971		 sll   $10,$10,1
64972		 subu  $9,$9,$10
64973		 sll   $10,$10,1
64974		 subu  $9,$9,$10
64975		 addu  $2,$8,$9
64976		 sltiu $16,$2,0x9a
64977		 xori  $16,$16,1        	 # Set Carry
64978		 sll   $10,$16,5
64979		 addu  $2,$2,$10
64980		 sll   $10,$10,2
64981		 addu  $2,$2,$10
64982		 xor   $19,$17,$2
64983		 and   $17,$17,$19
64984		 srl   $17,$17,7        	 # Set Overflow
64985		 sltiu $25,$2,1
64986		 and   $18,$18,$25       	 # Set Zero
64987		 srl   $19,$2,7         	 # Set Sign
64988		 or    $20,$0,$16       	 # Copy Carry to X
64989		 lw    $25,0x88($21)
64990		 sw    $15,m68k_ICount
64991		 or    $5,$0,$2
64992		 or    $4,$0,$14
64993		 jalr  $25
64994		 sw    $23,0x4C($21)    	 # Delay slot
64995		 lw    $15,m68k_ICount
64996		 addiu $15,$15,-12
64997		 bgez  $15,3f
64998		 lhu   $24,0x00($23)    	 # Delay slot
64999		 j     MainExit
65000	3:
65001		 sll   $7,$24,2         	 # Delay slot
65002		 addu  $7,$7,$30
65003		 lw    $7,0x00($7)
65004		 jr    $7
65005		 nop                    	 # Delay slot
65006
65007OP0_4820:				#:
65008		 addiu $23,$23,2
65009
65010		 andi  $24,$24,0x07
65011		 sll   $24,$24,2
65012		 addu  $24,$24,$21
65013		 lw    $14,0x20($24)
65014		 addiu $14,$14,-1
65015		 sw    $14,0x20($24)
65016		 lw    $25,0x7C($21)
65017		 sw    $15,m68k_ICount
65018		 sw    $14,0x44($29)
65019		 or    $4,$0,$14
65020		 jalr  $25
65021		 sw    $23,0x4C($21)    	 # Delay slot
65022		 lw    $14,0x44($29)
65023		 lw    $15,m68k_ICount
65024		 subu  $17,$0,$2
65025		 subu  $17,$17,$20
65026		 andi  $17,$17,0xFF
65027		 andi  $9,$2,0x0F
65028		 andi  $8,$2,0xF0
65029		 subu  $9,$0,$9
65030		 subu  $9,$9,$20
65031		 subu  $8,$0,$8
65032		 sltiu $10,$9,10
65033		 xori  $10,$10,1
65034		 sll   $10,$10,1
65035		 subu  $9,$9,$10
65036		 sll   $10,$10,1
65037		 subu  $9,$9,$10
65038		 addu  $2,$8,$9
65039		 sltiu $16,$2,0x9a
65040		 xori  $16,$16,1        	 # Set Carry
65041		 sll   $10,$16,5
65042		 addu  $2,$2,$10
65043		 sll   $10,$10,2
65044		 addu  $2,$2,$10
65045		 xor   $19,$17,$2
65046		 and   $17,$17,$19
65047		 srl   $17,$17,7        	 # Set Overflow
65048		 sltiu $25,$2,1
65049		 and   $18,$18,$25       	 # Set Zero
65050		 srl   $19,$2,7         	 # Set Sign
65051		 or    $20,$0,$16       	 # Copy Carry to X
65052		 lw    $25,0x88($21)
65053		 sw    $15,m68k_ICount
65054		 or    $5,$0,$2
65055		 or    $4,$0,$14
65056		 jalr  $25
65057		 sw    $23,0x4C($21)    	 # Delay slot
65058		 lw    $15,m68k_ICount
65059		 addiu $15,$15,-14
65060		 bgez  $15,3f
65061		 lhu   $24,0x00($23)    	 # Delay slot
65062		 j     MainExit
65063	3:
65064		 sll   $7,$24,2         	 # Delay slot
65065		 addu  $7,$7,$30
65066		 lw    $7,0x00($7)
65067		 jr    $7
65068		 nop                    	 # Delay slot
65069
65070OP0_4827:				#:
65071		 addiu $23,$23,2
65072
65073		 andi  $24,$24,0x07
65074		 lw    $14,0x3C($21)    	 # Get A7
65075		 addiu $14,$14,-2
65076		 sw    $14,0x3C($21)
65077		 lw    $25,0x7C($21)
65078		 sw    $15,m68k_ICount
65079		 sw    $14,0x44($29)
65080		 or    $4,$0,$14
65081		 jalr  $25
65082		 sw    $23,0x4C($21)    	 # Delay slot
65083		 lw    $14,0x44($29)
65084		 lw    $15,m68k_ICount
65085		 subu  $17,$0,$2
65086		 subu  $17,$17,$20
65087		 andi  $17,$17,0xFF
65088		 andi  $9,$2,0x0F
65089		 andi  $8,$2,0xF0
65090		 subu  $9,$0,$9
65091		 subu  $9,$9,$20
65092		 subu  $8,$0,$8
65093		 sltiu $10,$9,10
65094		 xori  $10,$10,1
65095		 sll   $10,$10,1
65096		 subu  $9,$9,$10
65097		 sll   $10,$10,1
65098		 subu  $9,$9,$10
65099		 addu  $2,$8,$9
65100		 sltiu $16,$2,0x9a
65101		 xori  $16,$16,1        	 # Set Carry
65102		 sll   $10,$16,5
65103		 addu  $2,$2,$10
65104		 sll   $10,$10,2
65105		 addu  $2,$2,$10
65106		 xor   $19,$17,$2
65107		 and   $17,$17,$19
65108		 srl   $17,$17,7        	 # Set Overflow
65109		 sltiu $25,$2,1
65110		 and   $18,$18,$25       	 # Set Zero
65111		 srl   $19,$2,7         	 # Set Sign
65112		 or    $20,$0,$16       	 # Copy Carry to X
65113		 lw    $25,0x88($21)
65114		 sw    $15,m68k_ICount
65115		 or    $5,$0,$2
65116		 or    $4,$0,$14
65117		 jalr  $25
65118		 sw    $23,0x4C($21)    	 # Delay slot
65119		 lw    $15,m68k_ICount
65120		 addiu $15,$15,-14
65121		 bgez  $15,3f
65122		 lhu   $24,0x00($23)    	 # Delay slot
65123		 j     MainExit
65124	3:
65125		 sll   $7,$24,2         	 # Delay slot
65126		 addu  $7,$7,$30
65127		 lw    $7,0x00($7)
65128		 jr    $7
65129		 nop                    	 # Delay slot
65130
65131OP0_4828:				#:
65132		 addiu $23,$23,2
65133
65134		 andi  $24,$24,0x07
65135		 lh    $7,0x00($23)
65136		 sll   $24,$24,2
65137		 addu  $24,$24,$21
65138		 lw    $14,0x20($24)
65139		 addiu $23,$23,2
65140		 addu  $14,$14,$7
65141		 lw    $25,0x7C($21)
65142		 sw    $15,m68k_ICount
65143		 sw    $14,0x44($29)
65144		 or    $4,$0,$14
65145		 jalr  $25
65146		 sw    $23,0x4C($21)    	 # Delay slot
65147		 lw    $14,0x44($29)
65148		 lw    $15,m68k_ICount
65149		 subu  $17,$0,$2
65150		 subu  $17,$17,$20
65151		 andi  $17,$17,0xFF
65152		 andi  $9,$2,0x0F
65153		 andi  $8,$2,0xF0
65154		 subu  $9,$0,$9
65155		 subu  $9,$9,$20
65156		 subu  $8,$0,$8
65157		 sltiu $10,$9,10
65158		 xori  $10,$10,1
65159		 sll   $10,$10,1
65160		 subu  $9,$9,$10
65161		 sll   $10,$10,1
65162		 subu  $9,$9,$10
65163		 addu  $2,$8,$9
65164		 sltiu $16,$2,0x9a
65165		 xori  $16,$16,1        	 # Set Carry
65166		 sll   $10,$16,5
65167		 addu  $2,$2,$10
65168		 sll   $10,$10,2
65169		 addu  $2,$2,$10
65170		 xor   $19,$17,$2
65171		 and   $17,$17,$19
65172		 srl   $17,$17,7        	 # Set Overflow
65173		 sltiu $25,$2,1
65174		 and   $18,$18,$25       	 # Set Zero
65175		 srl   $19,$2,7         	 # Set Sign
65176		 or    $20,$0,$16       	 # Copy Carry to X
65177		 lw    $25,0x88($21)
65178		 sw    $15,m68k_ICount
65179		 or    $5,$0,$2
65180		 or    $4,$0,$14
65181		 jalr  $25
65182		 sw    $23,0x4C($21)    	 # Delay slot
65183		 lw    $15,m68k_ICount
65184		 addiu $15,$15,-16
65185		 bgez  $15,3f
65186		 lhu   $24,0x00($23)    	 # Delay slot
65187		 j     MainExit
65188	3:
65189		 sll   $7,$24,2         	 # Delay slot
65190		 addu  $7,$7,$30
65191		 lw    $7,0x00($7)
65192		 jr    $7
65193		 nop                    	 # Delay slot
65194
65195OP0_4830:				#:
65196		 addiu $23,$23,2
65197
65198		 andi  $24,$24,0x07
65199		 sll   $24,$24,2
65200		 addu  $24,$24,$21
65201		 lw    $14,0x20($24)
65202		 lhu   $7,0x00($23)
65203		 addiu $23,$23,2
65204		 seb   $6,$7
65205		 or    $25,$0,$7
65206		 srl   $7,$7,12
65207		 andi  $25,$25,0x0800
65208		 sll   $7,$7,2
65209		 addu  $7,$7,$21
65210		 bne   $25,$0,0f
65211		 lw    $25,0x00($7)      	 # Delay slot
65212		 seh   $25,$25
65213	0:
65214		 addu  $25,$14,$25
65215		 addu  $14,$25,$6
65216		 lw    $25,0x7C($21)
65217		 sw    $15,m68k_ICount
65218		 sw    $14,0x44($29)
65219		 or    $4,$0,$14
65220		 jalr  $25
65221		 sw    $23,0x4C($21)    	 # Delay slot
65222		 lw    $14,0x44($29)
65223		 lw    $15,m68k_ICount
65224		 subu  $17,$0,$2
65225		 subu  $17,$17,$20
65226		 andi  $17,$17,0xFF
65227		 andi  $9,$2,0x0F
65228		 andi  $8,$2,0xF0
65229		 subu  $9,$0,$9
65230		 subu  $9,$9,$20
65231		 subu  $8,$0,$8
65232		 sltiu $10,$9,10
65233		 xori  $10,$10,1
65234		 sll   $10,$10,1
65235		 subu  $9,$9,$10
65236		 sll   $10,$10,1
65237		 subu  $9,$9,$10
65238		 addu  $2,$8,$9
65239		 sltiu $16,$2,0x9a
65240		 xori  $16,$16,1        	 # Set Carry
65241		 sll   $10,$16,5
65242		 addu  $2,$2,$10
65243		 sll   $10,$10,2
65244		 addu  $2,$2,$10
65245		 xor   $19,$17,$2
65246		 and   $17,$17,$19
65247		 srl   $17,$17,7        	 # Set Overflow
65248		 sltiu $25,$2,1
65249		 and   $18,$18,$25       	 # Set Zero
65250		 srl   $19,$2,7         	 # Set Sign
65251		 or    $20,$0,$16       	 # Copy Carry to X
65252		 lw    $25,0x88($21)
65253		 sw    $15,m68k_ICount
65254		 or    $5,$0,$2
65255		 or    $4,$0,$14
65256		 jalr  $25
65257		 sw    $23,0x4C($21)    	 # Delay slot
65258		 lw    $15,m68k_ICount
65259		 addiu $15,$15,-18
65260		 bgez  $15,3f
65261		 lhu   $24,0x00($23)    	 # Delay slot
65262		 j     MainExit
65263	3:
65264		 sll   $7,$24,2         	 # Delay slot
65265		 addu  $7,$7,$30
65266		 lw    $7,0x00($7)
65267		 jr    $7
65268		 nop                    	 # Delay slot
65269
65270OP0_4838:				#:
65271		 addiu $23,$23,2
65272
65273		 andi  $24,$24,0x07
65274		 lh    $14,0x00($23)
65275		 addiu $23,$23,2
65276		 lw    $25,0x7C($21)
65277		 sw    $15,m68k_ICount
65278		 sw    $14,0x44($29)
65279		 or    $4,$0,$14
65280		 jalr  $25
65281		 sw    $23,0x4C($21)    	 # Delay slot
65282		 lw    $14,0x44($29)
65283		 lw    $15,m68k_ICount
65284		 subu  $17,$0,$2
65285		 subu  $17,$17,$20
65286		 andi  $17,$17,0xFF
65287		 andi  $9,$2,0x0F
65288		 andi  $8,$2,0xF0
65289		 subu  $9,$0,$9
65290		 subu  $9,$9,$20
65291		 subu  $8,$0,$8
65292		 sltiu $10,$9,10
65293		 xori  $10,$10,1
65294		 sll   $10,$10,1
65295		 subu  $9,$9,$10
65296		 sll   $10,$10,1
65297		 subu  $9,$9,$10
65298		 addu  $2,$8,$9
65299		 sltiu $16,$2,0x9a
65300		 xori  $16,$16,1        	 # Set Carry
65301		 sll   $10,$16,5
65302		 addu  $2,$2,$10
65303		 sll   $10,$10,2
65304		 addu  $2,$2,$10
65305		 xor   $19,$17,$2
65306		 and   $17,$17,$19
65307		 srl   $17,$17,7        	 # Set Overflow
65308		 sltiu $25,$2,1
65309		 and   $18,$18,$25       	 # Set Zero
65310		 srl   $19,$2,7         	 # Set Sign
65311		 or    $20,$0,$16       	 # Copy Carry to X
65312		 lw    $25,0x88($21)
65313		 sw    $15,m68k_ICount
65314		 or    $5,$0,$2
65315		 or    $4,$0,$14
65316		 jalr  $25
65317		 sw    $23,0x4C($21)    	 # Delay slot
65318		 lw    $15,m68k_ICount
65319		 addiu $15,$15,-16
65320		 bgez  $15,3f
65321		 lhu   $24,0x00($23)    	 # Delay slot
65322		 j     MainExit
65323	3:
65324		 sll   $7,$24,2         	 # Delay slot
65325		 addu  $7,$7,$30
65326		 lw    $7,0x00($7)
65327		 jr    $7
65328		 nop                    	 # Delay slot
65329
65330OP0_4839:				#:
65331		 addiu $23,$23,2
65332
65333		 andi  $24,$24,0x07
65334		 lhu   $14,0x00($23)
65335		 lhu   $25,0x02($23)
65336		 sll   $14,$14,16
65337		 or    $14,$14,$25
65338		 addiu $23,$23,4
65339		 lw    $25,0x7C($21)
65340		 sw    $15,m68k_ICount
65341		 sw    $14,0x44($29)
65342		 or    $4,$0,$14
65343		 jalr  $25
65344		 sw    $23,0x4C($21)    	 # Delay slot
65345		 lw    $14,0x44($29)
65346		 lw    $15,m68k_ICount
65347		 subu  $17,$0,$2
65348		 subu  $17,$17,$20
65349		 andi  $17,$17,0xFF
65350		 andi  $9,$2,0x0F
65351		 andi  $8,$2,0xF0
65352		 subu  $9,$0,$9
65353		 subu  $9,$9,$20
65354		 subu  $8,$0,$8
65355		 sltiu $10,$9,10
65356		 xori  $10,$10,1
65357		 sll   $10,$10,1
65358		 subu  $9,$9,$10
65359		 sll   $10,$10,1
65360		 subu  $9,$9,$10
65361		 addu  $2,$8,$9
65362		 sltiu $16,$2,0x9a
65363		 xori  $16,$16,1        	 # Set Carry
65364		 sll   $10,$16,5
65365		 addu  $2,$2,$10
65366		 sll   $10,$10,2
65367		 addu  $2,$2,$10
65368		 xor   $19,$17,$2
65369		 and   $17,$17,$19
65370		 srl   $17,$17,7        	 # Set Overflow
65371		 sltiu $25,$2,1
65372		 and   $18,$18,$25       	 # Set Zero
65373		 srl   $19,$2,7         	 # Set Sign
65374		 or    $20,$0,$16       	 # Copy Carry to X
65375		 lw    $25,0x88($21)
65376		 sw    $15,m68k_ICount
65377		 or    $5,$0,$2
65378		 or    $4,$0,$14
65379		 jalr  $25
65380		 sw    $23,0x4C($21)    	 # Delay slot
65381		 lw    $15,m68k_ICount
65382		 addiu $15,$15,-20
65383		 bgez  $15,3f
65384		 lhu   $24,0x00($23)    	 # Delay slot
65385		 j     MainExit
65386	3:
65387		 sll   $7,$24,2         	 # Delay slot
65388		 addu  $7,$7,$30
65389		 lw    $7,0x00($7)
65390		 jr    $7
65391		 nop                    	 # Delay slot
65392
65393OP0_4ac0:				#:
65394		 addiu $23,$23,2
65395
65396		 andi  $24,$24,0x07
65397		 sll   $24,$24,2
65398		 addu  $24,$24,$21
65399		 lbu   $2,0x00($24)
65400		 and   $16,$0,$0        	 # Clear Carry
65401		 and   $17,$0,$0        	 # Clear Overflow
65402		 srl   $19,$2,7         	 # Set Sign
65403		 sltiu $18,$2,1         	 # Set Zero
65404		 or    $2,$2,0x80
65405		 sb    $2,0x00($24)
65406		 addiu $15,$15,-4
65407		 bgez  $15,3f
65408		 lhu   $24,0x00($23)    	 # Delay slot
65409		 j     MainExit
65410	3:
65411		 sll   $7,$24,2         	 # Delay slot
65412		 addu  $7,$7,$30
65413		 lw    $7,0x00($7)
65414		 jr    $7
65415		 nop                    	 # Delay slot
65416
65417OP0_4ad0:				#:
65418		 addiu $23,$23,2
65419
65420		 andi  $24,$24,0x07
65421		 sll   $24,$24,2
65422		 addu  $24,$24,$21
65423		 lw    $14,0x20($24)
65424		 lw    $25,0x7C($21)
65425		 sw    $15,m68k_ICount
65426		 sw    $14,0x44($29)
65427		 or    $4,$0,$14
65428		 jalr  $25
65429		 sw    $23,0x4C($21)    	 # Delay slot
65430		 lw    $14,0x44($29)
65431		 lw    $15,m68k_ICount
65432		 and   $16,$0,$0        	 # Clear Carry
65433		 and   $17,$0,$0        	 # Clear Overflow
65434		 srl   $19,$2,7         	 # Set Sign
65435		 sltiu $18,$2,1         	 # Set Zero
65436		 or    $2,$2,0x80
65437		 lw    $25,0x88($21)
65438		 sw    $15,m68k_ICount
65439		 or    $5,$0,$2
65440		 or    $4,$0,$14
65441		 jalr  $25
65442		 sw    $23,0x4C($21)    	 # Delay slot
65443		 lw    $15,m68k_ICount
65444		 addiu $15,$15,-18
65445		 bgez  $15,3f
65446		 lhu   $24,0x00($23)    	 # Delay slot
65447		 j     MainExit
65448	3:
65449		 sll   $7,$24,2         	 # Delay slot
65450		 addu  $7,$7,$30
65451		 lw    $7,0x00($7)
65452		 jr    $7
65453		 nop                    	 # Delay slot
65454
65455OP0_4ad8:				#:
65456		 addiu $23,$23,2
65457
65458		 andi  $24,$24,0x07
65459		 sll   $24,$24,2
65460		 addu  $24,$24,$21
65461		 lw    $14,0x20($24)
65462		 addiu $25,$14,1
65463		 sw    $25,0x20($24)
65464		 lw    $25,0x7C($21)
65465		 sw    $15,m68k_ICount
65466		 sw    $14,0x44($29)
65467		 or    $4,$0,$14
65468		 jalr  $25
65469		 sw    $23,0x4C($21)    	 # Delay slot
65470		 lw    $14,0x44($29)
65471		 lw    $15,m68k_ICount
65472		 and   $16,$0,$0        	 # Clear Carry
65473		 and   $17,$0,$0        	 # Clear Overflow
65474		 srl   $19,$2,7         	 # Set Sign
65475		 sltiu $18,$2,1         	 # Set Zero
65476		 or    $2,$2,0x80
65477		 lw    $25,0x88($21)
65478		 sw    $15,m68k_ICount
65479		 or    $5,$0,$2
65480		 or    $4,$0,$14
65481		 jalr  $25
65482		 sw    $23,0x4C($21)    	 # Delay slot
65483		 lw    $15,m68k_ICount
65484		 addiu $15,$15,-18
65485		 bgez  $15,3f
65486		 lhu   $24,0x00($23)    	 # Delay slot
65487		 j     MainExit
65488	3:
65489		 sll   $7,$24,2         	 # Delay slot
65490		 addu  $7,$7,$30
65491		 lw    $7,0x00($7)
65492		 jr    $7
65493		 nop                    	 # Delay slot
65494
65495OP0_4adf:				#:
65496		 addiu $23,$23,2
65497
65498		 lw    $14,0x3C($21)    	 # Get A7
65499		 addiu $25,$14,2
65500		 sw    $25,0x3C($21)
65501		 lw    $25,0x7C($21)
65502		 sw    $15,m68k_ICount
65503		 sw    $14,0x44($29)
65504		 or    $4,$0,$14
65505		 jalr  $25
65506		 sw    $23,0x4C($21)    	 # Delay slot
65507		 lw    $14,0x44($29)
65508		 lw    $15,m68k_ICount
65509		 and   $16,$0,$0        	 # Clear Carry
65510		 and   $17,$0,$0        	 # Clear Overflow
65511		 srl   $19,$2,7         	 # Set Sign
65512		 sltiu $18,$2,1         	 # Set Zero
65513		 or    $2,$2,0x80
65514		 lw    $25,0x88($21)
65515		 sw    $15,m68k_ICount
65516		 or    $5,$0,$2
65517		 or    $4,$0,$14
65518		 jalr  $25
65519		 sw    $23,0x4C($21)    	 # Delay slot
65520		 lw    $15,m68k_ICount
65521		 addiu $15,$15,-18
65522		 bgez  $15,3f
65523		 lhu   $24,0x00($23)    	 # Delay slot
65524		 j     MainExit
65525	3:
65526		 sll   $7,$24,2         	 # Delay slot
65527		 addu  $7,$7,$30
65528		 lw    $7,0x00($7)
65529		 jr    $7
65530		 nop                    	 # Delay slot
65531
65532OP0_4ae0:				#:
65533		 addiu $23,$23,2
65534
65535		 andi  $24,$24,0x07
65536		 sll   $24,$24,2
65537		 addu  $24,$24,$21
65538		 lw    $14,0x20($24)
65539		 addiu $14,$14,-1
65540		 sw    $14,0x20($24)
65541		 lw    $25,0x7C($21)
65542		 sw    $15,m68k_ICount
65543		 sw    $14,0x44($29)
65544		 or    $4,$0,$14
65545		 jalr  $25
65546		 sw    $23,0x4C($21)    	 # Delay slot
65547		 lw    $14,0x44($29)
65548		 lw    $15,m68k_ICount
65549		 and   $16,$0,$0        	 # Clear Carry
65550		 and   $17,$0,$0        	 # Clear Overflow
65551		 srl   $19,$2,7         	 # Set Sign
65552		 sltiu $18,$2,1         	 # Set Zero
65553		 or    $2,$2,0x80
65554		 lw    $25,0x88($21)
65555		 sw    $15,m68k_ICount
65556		 or    $5,$0,$2
65557		 or    $4,$0,$14
65558		 jalr  $25
65559		 sw    $23,0x4C($21)    	 # Delay slot
65560		 lw    $15,m68k_ICount
65561		 addiu $15,$15,-20
65562		 bgez  $15,3f
65563		 lhu   $24,0x00($23)    	 # Delay slot
65564		 j     MainExit
65565	3:
65566		 sll   $7,$24,2         	 # Delay slot
65567		 addu  $7,$7,$30
65568		 lw    $7,0x00($7)
65569		 jr    $7
65570		 nop                    	 # Delay slot
65571
65572OP0_4ae7:				#:
65573		 addiu $23,$23,2
65574
65575		 lw    $14,0x3C($21)    	 # Get A7
65576		 addiu $14,$14,-2
65577		 sw    $14,0x3C($21)
65578		 lw    $25,0x7C($21)
65579		 sw    $15,m68k_ICount
65580		 sw    $14,0x44($29)
65581		 or    $4,$0,$14
65582		 jalr  $25
65583		 sw    $23,0x4C($21)    	 # Delay slot
65584		 lw    $14,0x44($29)
65585		 lw    $15,m68k_ICount
65586		 and   $16,$0,$0        	 # Clear Carry
65587		 and   $17,$0,$0        	 # Clear Overflow
65588		 srl   $19,$2,7         	 # Set Sign
65589		 sltiu $18,$2,1         	 # Set Zero
65590		 or    $2,$2,0x80
65591		 lw    $25,0x88($21)
65592		 sw    $15,m68k_ICount
65593		 or    $5,$0,$2
65594		 or    $4,$0,$14
65595		 jalr  $25
65596		 sw    $23,0x4C($21)    	 # Delay slot
65597		 lw    $15,m68k_ICount
65598		 addiu $15,$15,-20
65599		 bgez  $15,3f
65600		 lhu   $24,0x00($23)    	 # Delay slot
65601		 j     MainExit
65602	3:
65603		 sll   $7,$24,2         	 # Delay slot
65604		 addu  $7,$7,$30
65605		 lw    $7,0x00($7)
65606		 jr    $7
65607		 nop                    	 # Delay slot
65608
65609OP0_4ae8:				#:
65610		 addiu $23,$23,2
65611
65612		 andi  $24,$24,0x07
65613		 lh    $7,0x00($23)
65614		 sll   $24,$24,2
65615		 addu  $24,$24,$21
65616		 lw    $14,0x20($24)
65617		 addiu $23,$23,2
65618		 addu  $14,$14,$7
65619		 lw    $25,0x7C($21)
65620		 sw    $15,m68k_ICount
65621		 sw    $14,0x44($29)
65622		 or    $4,$0,$14
65623		 jalr  $25
65624		 sw    $23,0x4C($21)    	 # Delay slot
65625		 lw    $14,0x44($29)
65626		 lw    $15,m68k_ICount
65627		 and   $16,$0,$0        	 # Clear Carry
65628		 and   $17,$0,$0        	 # Clear Overflow
65629		 srl   $19,$2,7         	 # Set Sign
65630		 sltiu $18,$2,1         	 # Set Zero
65631		 or    $2,$2,0x80
65632		 lw    $25,0x88($21)
65633		 sw    $15,m68k_ICount
65634		 or    $5,$0,$2
65635		 or    $4,$0,$14
65636		 jalr  $25
65637		 sw    $23,0x4C($21)    	 # Delay slot
65638		 lw    $15,m68k_ICount
65639		 addiu $15,$15,-22
65640		 bgez  $15,3f
65641		 lhu   $24,0x00($23)    	 # Delay slot
65642		 j     MainExit
65643	3:
65644		 sll   $7,$24,2         	 # Delay slot
65645		 addu  $7,$7,$30
65646		 lw    $7,0x00($7)
65647		 jr    $7
65648		 nop                    	 # Delay slot
65649
65650OP0_4af0:				#:
65651		 addiu $23,$23,2
65652
65653		 andi  $24,$24,0x07
65654		 sll   $24,$24,2
65655		 addu  $24,$24,$21
65656		 lw    $14,0x20($24)
65657		 lhu   $7,0x00($23)
65658		 addiu $23,$23,2
65659		 seb   $6,$7
65660		 or    $25,$0,$7
65661		 srl   $7,$7,12
65662		 andi  $25,$25,0x0800
65663		 sll   $7,$7,2
65664		 addu  $7,$7,$21
65665		 bne   $25,$0,0f
65666		 lw    $25,0x00($7)      	 # Delay slot
65667		 seh   $25,$25
65668	0:
65669		 addu  $25,$14,$25
65670		 addu  $14,$25,$6
65671		 lw    $25,0x7C($21)
65672		 sw    $15,m68k_ICount
65673		 sw    $14,0x44($29)
65674		 or    $4,$0,$14
65675		 jalr  $25
65676		 sw    $23,0x4C($21)    	 # Delay slot
65677		 lw    $14,0x44($29)
65678		 lw    $15,m68k_ICount
65679		 and   $16,$0,$0        	 # Clear Carry
65680		 and   $17,$0,$0        	 # Clear Overflow
65681		 srl   $19,$2,7         	 # Set Sign
65682		 sltiu $18,$2,1         	 # Set Zero
65683		 or    $2,$2,0x80
65684		 lw    $25,0x88($21)
65685		 sw    $15,m68k_ICount
65686		 or    $5,$0,$2
65687		 or    $4,$0,$14
65688		 jalr  $25
65689		 sw    $23,0x4C($21)    	 # Delay slot
65690		 lw    $15,m68k_ICount
65691		 addiu $15,$15,-24
65692		 bgez  $15,3f
65693		 lhu   $24,0x00($23)    	 # Delay slot
65694		 j     MainExit
65695	3:
65696		 sll   $7,$24,2         	 # Delay slot
65697		 addu  $7,$7,$30
65698		 lw    $7,0x00($7)
65699		 jr    $7
65700		 nop                    	 # Delay slot
65701
65702OP0_4af8:				#:
65703		 addiu $23,$23,2
65704
65705		 lh    $14,0x00($23)
65706		 addiu $23,$23,2
65707		 lw    $25,0x7C($21)
65708		 sw    $15,m68k_ICount
65709		 sw    $14,0x44($29)
65710		 or    $4,$0,$14
65711		 jalr  $25
65712		 sw    $23,0x4C($21)    	 # Delay slot
65713		 lw    $14,0x44($29)
65714		 lw    $15,m68k_ICount
65715		 and   $16,$0,$0        	 # Clear Carry
65716		 and   $17,$0,$0        	 # Clear Overflow
65717		 srl   $19,$2,7         	 # Set Sign
65718		 sltiu $18,$2,1         	 # Set Zero
65719		 or    $2,$2,0x80
65720		 lw    $25,0x88($21)
65721		 sw    $15,m68k_ICount
65722		 or    $5,$0,$2
65723		 or    $4,$0,$14
65724		 jalr  $25
65725		 sw    $23,0x4C($21)    	 # Delay slot
65726		 lw    $15,m68k_ICount
65727		 addiu $15,$15,-22
65728		 bgez  $15,3f
65729		 lhu   $24,0x00($23)    	 # Delay slot
65730		 j     MainExit
65731	3:
65732		 sll   $7,$24,2         	 # Delay slot
65733		 addu  $7,$7,$30
65734		 lw    $7,0x00($7)
65735		 jr    $7
65736		 nop                    	 # Delay slot
65737
65738OP0_4af9:				#:
65739		 addiu $23,$23,2
65740
65741		 lhu   $14,0x00($23)
65742		 lhu   $25,0x02($23)
65743		 sll   $14,$14,16
65744		 or    $14,$14,$25
65745		 addiu $23,$23,4
65746		 lw    $25,0x7C($21)
65747		 sw    $15,m68k_ICount
65748		 sw    $14,0x44($29)
65749		 or    $4,$0,$14
65750		 jalr  $25
65751		 sw    $23,0x4C($21)    	 # Delay slot
65752		 lw    $14,0x44($29)
65753		 lw    $15,m68k_ICount
65754		 and   $16,$0,$0        	 # Clear Carry
65755		 and   $17,$0,$0        	 # Clear Overflow
65756		 srl   $19,$2,7         	 # Set Sign
65757		 sltiu $18,$2,1         	 # Set Zero
65758		 or    $2,$2,0x80
65759		 lw    $25,0x88($21)
65760		 sw    $15,m68k_ICount
65761		 or    $5,$0,$2
65762		 or    $4,$0,$14
65763		 jalr  $25
65764		 sw    $23,0x4C($21)    	 # Delay slot
65765		 lw    $15,m68k_ICount
65766		 addiu $15,$15,-26
65767		 bgez  $15,3f
65768		 lhu   $24,0x00($23)    	 # Delay slot
65769		 j     MainExit
65770	3:
65771		 sll   $7,$24,2         	 # Delay slot
65772		 addu  $7,$7,$30
65773		 lw    $7,0x00($7)
65774		 jr    $7
65775		 nop                    	 # Delay slot
65776
65777OP0_4e40:				#:
65778		 addiu $23,$23,2
65779
65780		 andi  $2,$24,0x0f
65781		 jal   Exception
65782		 ori   $2,$2,32         	 # Delay slot
65783
65784		 bgez  $15,3f
65785		 lhu   $24,0x00($23)    	 # Delay slot
65786		 j     MainExit
65787	3:
65788		 sll   $7,$24,2         	 # Delay slot
65789		 addu  $7,$7,$30
65790		 lw    $7,0x00($7)
65791		 jr    $7
65792		 nop                    	 # Delay slot
65793
65794OP0_4e76:				#
65795		 beq   $17,$0,9f
65796		 addiu $23,$23,2        	 # Delay slot
65797
65798		 addiu $23,$23,-2
65799		 jal   Exception
65800		 ori   $2,$0,7
65801
65802		 addiu $15,$15,-4
65803		 bgez  $15,3f
65804		 lhu   $24,0x00($23)    	 # Delay slot
65805		 j     MainExit
65806	3:
65807		 sll   $7,$24,2         	 # Delay slot
65808		 addu  $7,$7,$30
65809		 lw    $7,0x00($7)
65810		 jr    $7
65811		 nop                    	 # Delay slot
65812
65813	9:
65814		 addiu $15,$15,-4
65815		 bgez  $15,3f
65816		 lhu   $24,0x00($23)    	 # Delay slot
65817		 j     MainExit
65818	3:
65819		 sll   $7,$24,2         	 # Delay slot
65820		 addu  $7,$7,$30
65821		 lw    $7,0x00($7)
65822		 jr    $7
65823		 nop                    	 # Delay slot
65824
65825OP0_4e70:				#:
65826		 lbu   $8,0x44($21)
65827		 andi  $8,$8,0x20       	 # Supervisor Mode ?
65828		 bne   $8,$0,9f
65829		 addiu $23,$23,2        	 # Delay slot
65830
65831		 addiu $23,$23,-2
65832		 jal   Exception
65833		 ori   $2,$0,8
65834
65835		 addiu $15,$15,-132
65836		 bgez  $15,3f
65837		 lhu   $24,0x00($23)    	 # Delay slot
65838		 j     MainExit
65839	3:
65840		 sll   $7,$24,2         	 # Delay slot
65841		 addu  $7,$7,$30
65842		 lw    $7,0x00($7)
65843		 jr    $7
65844		 nop                    	 # Delay slot
65845
65846
65847	9:
65848		 lw    $25,0x5C($21)
65849		 beq   $25,$0,9f
65850		 lhu   $24,0x00($23)    	 # Delay slot
65851		 sw    $15,m68k_ICount
65852		 jalr  $25
65853		 sw    $23,0x4C($21)    	 # Delay slot
65854		 lw    $15,m68k_ICount
65855		 lw    $23,0x4C($21)
65856		 lhu   $24,0x00($23)
65857	9:
65858		 sll   $7,$24,2
65859		 addu  $7,$7,$30
65860
65861		 lw    $7,0x00($7)
65862
65863		 jr    $7
65864		 addiu $15,$15,-132      	 # Delay slot
65865OP0_4e71:				#:
65866		 addiu $23,$23,2
65867
65868		 addiu $15,$15,-4
65869		 bgez  $15,3f
65870		 lhu   $24,0x00($23)    	 # Delay slot
65871		 j     MainExit
65872	3:
65873		 sll   $7,$24,2         	 # Delay slot
65874		 addu  $7,$7,$30
65875		 lw    $7,0x00($7)
65876		 jr    $7
65877		 nop                    	 # Delay slot
65878
65879OP0_4e72:				#:
65880		 lbu   $8,0x44($21)
65881		 andi  $8,$8,0x20       	 # Supervisor Mode ?
65882		 beq   $8,$0,9f
65883		 addiu $23,$23,2        	 # Delay slot
65884
65885		 lhu   $2,0x00($23)
65886		 addiu $23,$23,2
65887		 andi  $25,$2,0x2000    	 # User Mode ?
65888		 bne   $25,$0,0f
65889		 or    $18,$0,$2       	 # Delay slot
65890		 lw    $16,0x3C($21)
65891		 lw    $17,0x68($21)
65892		 sw    $16,0x40($21)
65893		 sw    $17,0x3C($21)
65894	0:
65895		 srl   $18,$18,8
65896		 sb    $18,0x44($21)    	 # T, S & I
65897		 or    $20,$0,$2
65898		 or    $19,$0,$2
65899		 or    $18,$0,$2
65900		 or    $17,$0,$2
65901		 or    $16,$0,$2
65902		 andi  $20,$20,0x10
65903		 andi  $19,$19,0x08
65904		 andi  $18,$18,0x04
65905		 andi  $17,$17,0x02
65906		 andi  $16,$16,0x01
65907		 srl   $20,$20,4
65908		 srl   $19,$19,3
65909		 srl   $18,$18,2
65910		 srl   $17,$17,1
65911		 lbu   $3,0x50($21)
65912		 andi  $2,$3,0x07
65913		 xori  $25,$2,0x07       	 # Always take 7
65914		 bne   $25,$0,8f
65915		 nop                    	 # Delay slot
65916
65917		 j     procint
65918		 nop                    	 # Delay slot
65919
65920	8:
65921
65922		 lbu   $8,0x44($21)     	 # int mask
65923		 andi  $8,$8,0x07
65924		 subu  $25,$8,$2
65925		 bgez  $25,8f
65926		 nop                    	 # Delay slot
65927
65928		 j     procint
65929		 nop                    	 # Delay slot
65930
65931	8:
65932
65933		 and   $15,$0,$0
65934		 ori   $3,$3,0x80
65935		 sb    $3,0x50($21)
65936		 addiu $15,$15,-4
65937		 bgez  $15,3f
65938		 lhu   $24,0x00($23)    	 # Delay slot
65939		 j     MainExit
65940	3:
65941		 sll   $7,$24,2         	 # Delay slot
65942		 addu  $7,$7,$30
65943		 lw    $7,0x00($7)
65944		 jr    $7
65945		 nop                    	 # Delay slot
65946
65947	9:
65948		 addiu $23,$23,-2
65949		 jal   Exception
65950		 ori   $2,$0,8
65951
65952		 addiu $15,$15,-4
65953		 bgez  $15,3f
65954		 lhu   $24,0x00($23)    	 # Delay slot
65955		 j     MainExit
65956	3:
65957		 sll   $7,$24,2         	 # Delay slot
65958		 addu  $7,$7,$30
65959		 lw    $7,0x00($7)
65960		 jr    $7
65961		 nop                    	 # Delay slot
65962
65963OP0_4880:				#:
65964		 addiu $23,$23,2
65965
65966		 andi  $24,$24,0x07
65967		 sll   $24,$24,2
65968		 addu  $24,$24,$21
65969		 lb    $2,0x00($24)
65970		 and   $16,$0,$0        	 # Clear Carry
65971		 and   $17,$0,$0        	 # Clear Overflow
65972		 slt   $19,$2,$0        	 # Set Sign
65973		 sltiu $18,$2,1         	 # Set Zero
65974		 sh    $2,0x00($24)
65975		 addiu $15,$15,-4
65976		 bgez  $15,3f
65977		 lhu   $24,0x00($23)    	 # Delay slot
65978		 j     MainExit
65979	3:
65980		 sll   $7,$24,2         	 # Delay slot
65981		 addu  $7,$7,$30
65982		 lw    $7,0x00($7)
65983		 jr    $7
65984		 nop                    	 # Delay slot
65985
65986OP0_48c0:				#:
65987		 addiu $23,$23,2
65988
65989		 andi  $24,$24,0x07
65990		 sll   $24,$24,2
65991		 addu  $24,$24,$21
65992		 lh    $2,0x00($24)
65993		 and   $16,$0,$0        	 # Clear Carry
65994		 and   $17,$0,$0        	 # Clear Overflow
65995		 slt   $19,$2,$0        	 # Set Sign
65996		 sltiu $18,$2,1         	 # Set Zero
65997		 sw    $2,0x00($24)
65998		 addiu $15,$15,-4
65999		 bgez  $15,3f
66000		 lhu   $24,0x00($23)    	 # Delay slot
66001		 j     MainExit
66002	3:
66003		 sll   $7,$24,2         	 # Delay slot
66004		 addu  $7,$7,$30
66005		 lw    $7,0x00($7)
66006		 jr    $7
66007		 nop                    	 # Delay slot
66008
66009OP0_4e73:				#:
66010		 lbu   $8,0x44($21)
66011		 andi  $8,$8,0x20       	 # Supervisor Mode ?
66012		 beq   $8,$0,9f
66013		 addiu $23,$23,2        	 # Delay slot
66014
66015		 lw    $16,0x3C($21)
66016		 lw    $25,0x80($21)
66017		 sw    $15,m68k_ICount
66018		 or    $4,$0,$16
66019		 jalr  $25
66020		 sw    $23,0x4C($21)    	 # Delay slot
66021		 lw    $15,m68k_ICount
66022		 addiu $8,$16,6
66023		 sw    $8,0x3C($21)
66024		 addiu $16,$16,2
66025		 or    $17,$0,$2
66026		 lw    $25,0x84($21)
66027		 sw    $15,m68k_ICount
66028		 or    $4,$0,$16
66029		 jalr  $25
66030		 sw    $23,0x4C($21)    	 # Delay slot
66031		 lw    $15,m68k_ICount
66032		 or    $8,$0,$2
66033		 or    $2,$0,$17
66034		 andi  $25,$2,0x2000    	 # User Mode ?
66035		 bne   $25,$0,0f
66036		 or    $18,$0,$2       	 # Delay slot
66037		 lw    $16,0x3C($21)
66038		 lw    $17,0x68($21)
66039		 sw    $16,0x40($21)
66040		 sw    $17,0x3C($21)
66041	0:
66042		 srl   $18,$18,8
66043		 sb    $18,0x44($21)    	 # T, S & I
66044		 or    $20,$0,$2
66045		 or    $19,$0,$2
66046		 or    $18,$0,$2
66047		 or    $17,$0,$2
66048		 or    $16,$0,$2
66049		 andi  $20,$20,0x10
66050		 andi  $19,$19,0x08
66051		 andi  $18,$18,0x04
66052		 andi  $17,$17,0x02
66053		 andi  $16,$16,0x01
66054		 srl   $20,$20,4
66055		 srl   $19,$19,3
66056		 srl   $18,$18,2
66057		 srl   $17,$17,1
66058		 andi  $25,$8,0x01
66059		 beq   $25,$0,2f
66060		 addu  $23,$22,$8     	 # Delay slot
66061		 addiu $23,$23,-2
66062		 jal   Exception
66063		 ori   $2,$0,3
66064
66065		 addiu $15,$15,-20
66066		 bgez  $15,3f
66067		 lbu   $7,0x50($21)     	 # Delay slot
66068		 j     MainExit
66069	3:
66070 # Check for Interrupt waiting
66071
66072		 andi  $7,$7,0x07       	 # Delay slot
66073		 beq   $7,$0,3f
66074		 nop                    	 # Delay slot
66075		 j     interrupt
66076	3:
66077		 lhu   $24,0x00($23)    	 # Delay slot
66078		 sll   $7,$24,2
66079		 addu  $7,$7,$30
66080		 lw    $7,0x00($7)
66081		 jr    $7
66082		 nop                    	 # Delay slot
66083
66084	2:
66085		 sw    $8,0x74($21)
66086		 lw    $6,mem_amask
66087		 lw    $25,0x94($21)
66088		 and   $23,$8,$6
66089		 sw    $15,m68k_ICount
66090		 jalr  $25
66091		 or    $4,$0,$23   	 # Delay slot
66092		 lw    $15,m68k_ICount
66093		 lw    $22,OP_ROM
66094		 addu  $23,$23,$22
66095 # End of Banking code:
66096		 addiu $15,$15,-20
66097		 bgez  $15,3f
66098		 lbu   $7,0x50($21)     	 # Delay slot
66099		 j     MainExit
66100	3:
66101 # Check for Interrupt waiting
66102
66103		 andi  $7,$7,0x07       	 # Delay slot
66104		 beq   $7,$0,3f
66105		 nop                    	 # Delay slot
66106		 j     interrupt
66107	3:
66108		 lhu   $24,0x00($23)    	 # Delay slot
66109		 sll   $7,$24,2
66110		 addu  $7,$7,$30
66111		 lw    $7,0x00($7)
66112		 jr    $7
66113		 nop                    	 # Delay slot
66114
66115	9:
66116		 addiu $23,$23,-2
66117		 jal   Exception
66118		 ori   $2,$0,8
66119
66120		 addiu $15,$15,-20
66121		 bgez  $15,3f
66122		 lbu   $7,0x50($21)     	 # Delay slot
66123		 j     MainExit
66124	3:
66125 # Check for Interrupt waiting
66126
66127		 andi  $7,$7,0x07       	 # Delay slot
66128		 beq   $7,$0,3f
66129		 nop                    	 # Delay slot
66130		 j     interrupt
66131	3:
66132		 lhu   $24,0x00($23)    	 # Delay slot
66133		 sll   $7,$24,2
66134		 addu  $7,$7,$30
66135		 lw    $7,0x00($7)
66136		 jr    $7
66137		 nop                    	 # Delay slot
66138
66139OP0_4a00:				#:
66140		 addiu $23,$23,2
66141
66142		 andi  $24,$24,0x07
66143
66144		 sll   $24,$24,2
66145		 addu  $24,$24,$21
66146		 lbu   $2,0x00($24)
66147		 and   $16,$0,$0        	 # Clear Carry
66148		 and   $17,$0,$0        	 # Clear Overflow
66149		 srl   $19,$2,7         	 # Set Sign
66150		 sltiu $18,$2,1         	 # Set Zero
66151		 addiu $15,$15,-4
66152		 bgez  $15,3f
66153		 lhu   $24,0x00($23)    	 # Delay slot
66154		 j     MainExit
66155	3:
66156		 sll   $7,$24,2         	 # Delay slot
66157		 addu  $7,$7,$30
66158		 lw    $7,0x00($7)
66159		 jr    $7
66160		 nop                    	 # Delay slot
66161
66162OP0_4a10:				#:
66163		 addiu $23,$23,2
66164
66165		 andi  $24,$24,0x07
66166
66167		 sll   $24,$24,2
66168		 addu  $24,$24,$21
66169		 lw    $14,0x20($24)
66170		 lw    $25,0x7C($21)
66171		 sw    $15,m68k_ICount
66172		 or    $4,$0,$14
66173		 jalr  $25
66174		 sw    $23,0x4C($21)    	 # Delay slot
66175		 lw    $15,m68k_ICount
66176		 and   $16,$0,$0        	 # Clear Carry
66177		 and   $17,$0,$0        	 # Clear Overflow
66178		 srl   $19,$2,7         	 # Set Sign
66179		 sltiu $18,$2,1         	 # Set Zero
66180		 addiu $15,$15,-8
66181		 bgez  $15,3f
66182		 lhu   $24,0x00($23)    	 # Delay slot
66183		 j     MainExit
66184	3:
66185		 sll   $7,$24,2         	 # Delay slot
66186		 addu  $7,$7,$30
66187		 lw    $7,0x00($7)
66188		 jr    $7
66189		 nop                    	 # Delay slot
66190
66191OP0_4a18:				#:
66192		 addiu $23,$23,2
66193
66194		 andi  $24,$24,0x07
66195
66196		 sll   $24,$24,2
66197		 addu  $24,$24,$21
66198		 lw    $14,0x20($24)
66199		 addiu $25,$14,1
66200		 sw    $25,0x20($24)
66201		 lw    $25,0x7C($21)
66202		 sw    $15,m68k_ICount
66203		 or    $4,$0,$14
66204		 jalr  $25
66205		 sw    $23,0x4C($21)    	 # Delay slot
66206		 lw    $15,m68k_ICount
66207		 and   $16,$0,$0        	 # Clear Carry
66208		 and   $17,$0,$0        	 # Clear Overflow
66209		 srl   $19,$2,7         	 # Set Sign
66210		 sltiu $18,$2,1         	 # Set Zero
66211		 addiu $15,$15,-8
66212		 bgez  $15,3f
66213		 lhu   $24,0x00($23)    	 # Delay slot
66214		 j     MainExit
66215	3:
66216		 sll   $7,$24,2         	 # Delay slot
66217		 addu  $7,$7,$30
66218		 lw    $7,0x00($7)
66219		 jr    $7
66220		 nop                    	 # Delay slot
66221
66222OP0_4a1f:				#:
66223		 addiu $23,$23,2
66224
66225		 lw    $14,0x3C($21)    	 # Get A7
66226		 addiu $25,$14,2
66227		 sw    $25,0x3C($21)
66228		 lw    $25,0x7C($21)
66229		 sw    $15,m68k_ICount
66230		 or    $4,$0,$14
66231		 jalr  $25
66232		 sw    $23,0x4C($21)    	 # Delay slot
66233		 lw    $15,m68k_ICount
66234		 and   $16,$0,$0        	 # Clear Carry
66235		 and   $17,$0,$0        	 # Clear Overflow
66236		 srl   $19,$2,7         	 # Set Sign
66237		 sltiu $18,$2,1         	 # Set Zero
66238		 addiu $15,$15,-8
66239		 bgez  $15,3f
66240		 lhu   $24,0x00($23)    	 # Delay slot
66241		 j     MainExit
66242	3:
66243		 sll   $7,$24,2         	 # Delay slot
66244		 addu  $7,$7,$30
66245		 lw    $7,0x00($7)
66246		 jr    $7
66247		 nop                    	 # Delay slot
66248
66249OP0_4a20:				#:
66250		 addiu $23,$23,2
66251
66252		 andi  $24,$24,0x07
66253
66254		 sll   $24,$24,2
66255		 addu  $24,$24,$21
66256		 lw    $14,0x20($24)
66257		 addiu $14,$14,-1
66258		 sw    $14,0x20($24)
66259		 lw    $25,0x7C($21)
66260		 sw    $15,m68k_ICount
66261		 or    $4,$0,$14
66262		 jalr  $25
66263		 sw    $23,0x4C($21)    	 # Delay slot
66264		 lw    $15,m68k_ICount
66265		 and   $16,$0,$0        	 # Clear Carry
66266		 and   $17,$0,$0        	 # Clear Overflow
66267		 srl   $19,$2,7         	 # Set Sign
66268		 sltiu $18,$2,1         	 # Set Zero
66269		 addiu $15,$15,-10
66270		 bgez  $15,3f
66271		 lhu   $24,0x00($23)    	 # Delay slot
66272		 j     MainExit
66273	3:
66274		 sll   $7,$24,2         	 # Delay slot
66275		 addu  $7,$7,$30
66276		 lw    $7,0x00($7)
66277		 jr    $7
66278		 nop                    	 # Delay slot
66279
66280OP0_4a27:				#:
66281		 addiu $23,$23,2
66282
66283		 lw    $14,0x3C($21)    	 # Get A7
66284		 addiu $14,$14,-2
66285		 sw    $14,0x3C($21)
66286		 lw    $25,0x7C($21)
66287		 sw    $15,m68k_ICount
66288		 or    $4,$0,$14
66289		 jalr  $25
66290		 sw    $23,0x4C($21)    	 # Delay slot
66291		 lw    $15,m68k_ICount
66292		 and   $16,$0,$0        	 # Clear Carry
66293		 and   $17,$0,$0        	 # Clear Overflow
66294		 srl   $19,$2,7         	 # Set Sign
66295		 sltiu $18,$2,1         	 # Set Zero
66296		 addiu $15,$15,-10
66297		 bgez  $15,3f
66298		 lhu   $24,0x00($23)    	 # Delay slot
66299		 j     MainExit
66300	3:
66301		 sll   $7,$24,2         	 # Delay slot
66302		 addu  $7,$7,$30
66303		 lw    $7,0x00($7)
66304		 jr    $7
66305		 nop                    	 # Delay slot
66306
66307OP0_4a28:				#:
66308		 addiu $23,$23,2
66309
66310		 andi  $24,$24,0x07
66311
66312		 lh    $7,0x00($23)
66313		 sll   $24,$24,2
66314		 addu  $24,$24,$21
66315		 lw    $14,0x20($24)
66316		 addiu $23,$23,2
66317		 addu  $14,$14,$7
66318		 lw    $25,0x7C($21)
66319		 sw    $15,m68k_ICount
66320		 or    $4,$0,$14
66321		 jalr  $25
66322		 sw    $23,0x4C($21)    	 # Delay slot
66323		 lw    $15,m68k_ICount
66324		 and   $16,$0,$0        	 # Clear Carry
66325		 and   $17,$0,$0        	 # Clear Overflow
66326		 srl   $19,$2,7         	 # Set Sign
66327		 sltiu $18,$2,1         	 # Set Zero
66328		 addiu $15,$15,-12
66329		 bgez  $15,3f
66330		 lhu   $24,0x00($23)    	 # Delay slot
66331		 j     MainExit
66332	3:
66333		 sll   $7,$24,2         	 # Delay slot
66334		 addu  $7,$7,$30
66335		 lw    $7,0x00($7)
66336		 jr    $7
66337		 nop                    	 # Delay slot
66338
66339OP0_4a30:				#:
66340		 addiu $23,$23,2
66341
66342		 andi  $24,$24,0x07
66343
66344		 sll   $24,$24,2
66345		 addu  $24,$24,$21
66346		 lw    $14,0x20($24)
66347		 lhu   $7,0x00($23)
66348		 addiu $23,$23,2
66349		 seb   $6,$7
66350		 or    $25,$0,$7
66351		 srl   $7,$7,12
66352		 andi  $25,$25,0x0800
66353		 sll   $7,$7,2
66354		 addu  $7,$7,$21
66355		 bne   $25,$0,0f
66356		 lw    $25,0x00($7)      	 # Delay slot
66357		 seh   $25,$25
66358	0:
66359		 addu  $25,$14,$25
66360		 addu  $14,$25,$6
66361		 lw    $25,0x7C($21)
66362		 sw    $15,m68k_ICount
66363		 or    $4,$0,$14
66364		 jalr  $25
66365		 sw    $23,0x4C($21)    	 # Delay slot
66366		 lw    $15,m68k_ICount
66367		 and   $16,$0,$0        	 # Clear Carry
66368		 and   $17,$0,$0        	 # Clear Overflow
66369		 srl   $19,$2,7         	 # Set Sign
66370		 sltiu $18,$2,1         	 # Set Zero
66371		 addiu $15,$15,-14
66372		 bgez  $15,3f
66373		 lhu   $24,0x00($23)    	 # Delay slot
66374		 j     MainExit
66375	3:
66376		 sll   $7,$24,2         	 # Delay slot
66377		 addu  $7,$7,$30
66378		 lw    $7,0x00($7)
66379		 jr    $7
66380		 nop                    	 # Delay slot
66381
66382OP0_4a38:				#:
66383		 addiu $23,$23,2
66384
66385		 lh    $14,0x00($23)
66386		 addiu $23,$23,2
66387		 lw    $25,0x7C($21)
66388		 sw    $15,m68k_ICount
66389		 or    $4,$0,$14
66390		 jalr  $25
66391		 sw    $23,0x4C($21)    	 # Delay slot
66392		 lw    $15,m68k_ICount
66393		 and   $16,$0,$0        	 # Clear Carry
66394		 and   $17,$0,$0        	 # Clear Overflow
66395		 srl   $19,$2,7         	 # Set Sign
66396		 sltiu $18,$2,1         	 # Set Zero
66397		 addiu $15,$15,-12
66398		 bgez  $15,3f
66399		 lhu   $24,0x00($23)    	 # Delay slot
66400		 j     MainExit
66401	3:
66402		 sll   $7,$24,2         	 # Delay slot
66403		 addu  $7,$7,$30
66404		 lw    $7,0x00($7)
66405		 jr    $7
66406		 nop                    	 # Delay slot
66407
66408OP0_4a39:				#:
66409		 addiu $23,$23,2
66410
66411		 lhu   $14,0x00($23)
66412		 lhu   $25,0x02($23)
66413		 sll   $14,$14,16
66414		 or    $14,$14,$25
66415		 addiu $23,$23,4
66416		 lw    $25,0x7C($21)
66417		 sw    $15,m68k_ICount
66418		 or    $4,$0,$14
66419		 jalr  $25
66420		 sw    $23,0x4C($21)    	 # Delay slot
66421		 lw    $15,m68k_ICount
66422		 and   $16,$0,$0        	 # Clear Carry
66423		 and   $17,$0,$0        	 # Clear Overflow
66424		 srl   $19,$2,7         	 # Set Sign
66425		 sltiu $18,$2,1         	 # Set Zero
66426		 addiu $15,$15,-16
66427		 bgez  $15,3f
66428		 lhu   $24,0x00($23)    	 # Delay slot
66429		 j     MainExit
66430	3:
66431		 sll   $7,$24,2         	 # Delay slot
66432		 addu  $7,$7,$30
66433		 lw    $7,0x00($7)
66434		 jr    $7
66435		 nop                    	 # Delay slot
66436
66437OP0_4a40:				#:
66438		 addiu $23,$23,2
66439
66440		 andi  $24,$24,0x07
66441
66442		 sll   $24,$24,2
66443		 addu  $24,$24,$21
66444		 lhu   $2,0x00($24)
66445		 and   $16,$0,$0        	 # Clear Carry
66446		 and   $17,$0,$0        	 # Clear Overflow
66447		 srl   $19,$2,15         	 # Set Sign
66448		 sltiu $18,$2,1         	 # Set Zero
66449		 addiu $15,$15,-4
66450		 bgez  $15,3f
66451		 lhu   $24,0x00($23)    	 # Delay slot
66452		 j     MainExit
66453	3:
66454		 sll   $7,$24,2         	 # Delay slot
66455		 addu  $7,$7,$30
66456		 lw    $7,0x00($7)
66457		 jr    $7
66458		 nop                    	 # Delay slot
66459
66460OP0_4a50:				#:
66461		 addiu $23,$23,2
66462
66463		 andi  $24,$24,0x07
66464
66465		 sll   $24,$24,2
66466		 addu  $24,$24,$21
66467		 lw    $14,0x20($24)
66468		 lw    $25,0x80($21)
66469		 sw    $15,m68k_ICount
66470		 or    $4,$0,$14
66471		 jalr  $25
66472		 sw    $23,0x4C($21)    	 # Delay slot
66473		 lw    $15,m68k_ICount
66474		 and   $16,$0,$0        	 # Clear Carry
66475		 and   $17,$0,$0        	 # Clear Overflow
66476		 srl   $19,$2,15         	 # Set Sign
66477		 sltiu $18,$2,1         	 # Set Zero
66478		 addiu $15,$15,-8
66479		 bgez  $15,3f
66480		 lhu   $24,0x00($23)    	 # Delay slot
66481		 j     MainExit
66482	3:
66483		 sll   $7,$24,2         	 # Delay slot
66484		 addu  $7,$7,$30
66485		 lw    $7,0x00($7)
66486		 jr    $7
66487		 nop                    	 # Delay slot
66488
66489OP0_4a58:				#:
66490		 addiu $23,$23,2
66491
66492		 andi  $24,$24,0x07
66493
66494		 sll   $24,$24,2
66495		 addu  $24,$24,$21
66496		 lw    $14,0x20($24)
66497		 addiu $25,$14,2
66498		 sw    $25,0x20($24)
66499		 lw    $25,0x80($21)
66500		 sw    $15,m68k_ICount
66501		 or    $4,$0,$14
66502		 jalr  $25
66503		 sw    $23,0x4C($21)    	 # Delay slot
66504		 lw    $15,m68k_ICount
66505		 and   $16,$0,$0        	 # Clear Carry
66506		 and   $17,$0,$0        	 # Clear Overflow
66507		 srl   $19,$2,15         	 # Set Sign
66508		 sltiu $18,$2,1         	 # Set Zero
66509		 addiu $15,$15,-8
66510		 bgez  $15,3f
66511		 lhu   $24,0x00($23)    	 # Delay slot
66512		 j     MainExit
66513	3:
66514		 sll   $7,$24,2         	 # Delay slot
66515		 addu  $7,$7,$30
66516		 lw    $7,0x00($7)
66517		 jr    $7
66518		 nop                    	 # Delay slot
66519
66520OP0_4a60:				#:
66521		 addiu $23,$23,2
66522
66523		 andi  $24,$24,0x07
66524
66525		 sll   $24,$24,2
66526		 addu  $24,$24,$21
66527		 lw    $14,0x20($24)
66528		 addiu $14,$14,-2
66529		 sw    $14,0x20($24)
66530		 lw    $25,0x80($21)
66531		 sw    $15,m68k_ICount
66532		 or    $4,$0,$14
66533		 jalr  $25
66534		 sw    $23,0x4C($21)    	 # Delay slot
66535		 lw    $15,m68k_ICount
66536		 and   $16,$0,$0        	 # Clear Carry
66537		 and   $17,$0,$0        	 # Clear Overflow
66538		 srl   $19,$2,15         	 # Set Sign
66539		 sltiu $18,$2,1         	 # Set Zero
66540		 addiu $15,$15,-10
66541		 bgez  $15,3f
66542		 lhu   $24,0x00($23)    	 # Delay slot
66543		 j     MainExit
66544	3:
66545		 sll   $7,$24,2         	 # Delay slot
66546		 addu  $7,$7,$30
66547		 lw    $7,0x00($7)
66548		 jr    $7
66549		 nop                    	 # Delay slot
66550
66551OP0_4a68:				#:
66552		 addiu $23,$23,2
66553
66554		 andi  $24,$24,0x07
66555
66556		 lh    $7,0x00($23)
66557		 sll   $24,$24,2
66558		 addu  $24,$24,$21
66559		 lw    $14,0x20($24)
66560		 addiu $23,$23,2
66561		 addu  $14,$14,$7
66562		 lw    $25,0x80($21)
66563		 sw    $15,m68k_ICount
66564		 or    $4,$0,$14
66565		 jalr  $25
66566		 sw    $23,0x4C($21)    	 # Delay slot
66567		 lw    $15,m68k_ICount
66568		 and   $16,$0,$0        	 # Clear Carry
66569		 and   $17,$0,$0        	 # Clear Overflow
66570		 srl   $19,$2,15         	 # Set Sign
66571		 sltiu $18,$2,1         	 # Set Zero
66572		 addiu $15,$15,-12
66573		 bgez  $15,3f
66574		 lhu   $24,0x00($23)    	 # Delay slot
66575		 j     MainExit
66576	3:
66577		 sll   $7,$24,2         	 # Delay slot
66578		 addu  $7,$7,$30
66579		 lw    $7,0x00($7)
66580		 jr    $7
66581		 nop                    	 # Delay slot
66582
66583OP0_4a70:				#:
66584		 addiu $23,$23,2
66585
66586		 andi  $24,$24,0x07
66587
66588		 sll   $24,$24,2
66589		 addu  $24,$24,$21
66590		 lw    $14,0x20($24)
66591		 lhu   $7,0x00($23)
66592		 addiu $23,$23,2
66593		 seb   $6,$7
66594		 or    $25,$0,$7
66595		 srl   $7,$7,12
66596		 andi  $25,$25,0x0800
66597		 sll   $7,$7,2
66598		 addu  $7,$7,$21
66599		 bne   $25,$0,0f
66600		 lw    $25,0x00($7)      	 # Delay slot
66601		 seh   $25,$25
66602	0:
66603		 addu  $25,$14,$25
66604		 addu  $14,$25,$6
66605		 lw    $25,0x80($21)
66606		 sw    $15,m68k_ICount
66607		 or    $4,$0,$14
66608		 jalr  $25
66609		 sw    $23,0x4C($21)    	 # Delay slot
66610		 lw    $15,m68k_ICount
66611		 and   $16,$0,$0        	 # Clear Carry
66612		 and   $17,$0,$0        	 # Clear Overflow
66613		 srl   $19,$2,15         	 # Set Sign
66614		 sltiu $18,$2,1         	 # Set Zero
66615		 addiu $15,$15,-14
66616		 bgez  $15,3f
66617		 lhu   $24,0x00($23)    	 # Delay slot
66618		 j     MainExit
66619	3:
66620		 sll   $7,$24,2         	 # Delay slot
66621		 addu  $7,$7,$30
66622		 lw    $7,0x00($7)
66623		 jr    $7
66624		 nop                    	 # Delay slot
66625
66626OP0_4a78:				#:
66627		 addiu $23,$23,2
66628
66629		 lh    $14,0x00($23)
66630		 addiu $23,$23,2
66631		 lw    $25,0x80($21)
66632		 sw    $15,m68k_ICount
66633		 or    $4,$0,$14
66634		 jalr  $25
66635		 sw    $23,0x4C($21)    	 # Delay slot
66636		 lw    $15,m68k_ICount
66637		 and   $16,$0,$0        	 # Clear Carry
66638		 and   $17,$0,$0        	 # Clear Overflow
66639		 srl   $19,$2,15         	 # Set Sign
66640		 sltiu $18,$2,1         	 # Set Zero
66641		 addiu $15,$15,-12
66642		 bgez  $15,3f
66643		 lhu   $24,0x00($23)    	 # Delay slot
66644		 j     MainExit
66645	3:
66646		 sll   $7,$24,2         	 # Delay slot
66647		 addu  $7,$7,$30
66648		 lw    $7,0x00($7)
66649		 jr    $7
66650		 nop                    	 # Delay slot
66651
66652OP0_4a79:				#:
66653		 addiu $23,$23,2
66654
66655		 lhu   $14,0x00($23)
66656		 lhu   $25,0x02($23)
66657		 sll   $14,$14,16
66658		 or    $14,$14,$25
66659		 addiu $23,$23,4
66660		 lw    $25,0x80($21)
66661		 sw    $15,m68k_ICount
66662		 or    $4,$0,$14
66663		 jalr  $25
66664		 sw    $23,0x4C($21)    	 # Delay slot
66665		 lw    $15,m68k_ICount
66666		 and   $16,$0,$0        	 # Clear Carry
66667		 and   $17,$0,$0        	 # Clear Overflow
66668		 srl   $19,$2,15         	 # Set Sign
66669		 sltiu $18,$2,1         	 # Set Zero
66670		 addiu $15,$15,-16
66671		 bgez  $15,3f
66672		 lhu   $24,0x00($23)    	 # Delay slot
66673		 j     MainExit
66674	3:
66675		 sll   $7,$24,2         	 # Delay slot
66676		 addu  $7,$7,$30
66677		 lw    $7,0x00($7)
66678		 jr    $7
66679		 nop                    	 # Delay slot
66680
66681OP0_4a80:				#:
66682		 addiu $23,$23,2
66683
66684		 andi  $24,$24,0x07
66685
66686		 sll   $24,$24,2
66687		 addu  $24,$24,$21
66688		 lw    $2,0x00($24)
66689		 and   $16,$0,$0        	 # Clear Carry
66690		 and   $17,$0,$0        	 # Clear Overflow
66691		 srl   $19,$2,31         	 # Set Sign
66692		 sltiu $18,$2,1         	 # Set Zero
66693		 addiu $15,$15,-4
66694		 bgez  $15,3f
66695		 lhu   $24,0x00($23)    	 # Delay slot
66696		 j     MainExit
66697	3:
66698		 sll   $7,$24,2         	 # Delay slot
66699		 addu  $7,$7,$30
66700		 lw    $7,0x00($7)
66701		 jr    $7
66702		 nop                    	 # Delay slot
66703
66704OP0_4a90:				#:
66705		 addiu $23,$23,2
66706
66707		 andi  $24,$24,0x07
66708
66709		 sll   $24,$24,2
66710		 addu  $24,$24,$21
66711		 lw    $14,0x20($24)
66712		 lw    $25,0x84($21)
66713		 sw    $15,m68k_ICount
66714		 or    $4,$0,$14
66715		 jalr  $25
66716		 sw    $23,0x4C($21)    	 # Delay slot
66717		 lw    $15,m68k_ICount
66718		 and   $16,$0,$0        	 # Clear Carry
66719		 and   $17,$0,$0        	 # Clear Overflow
66720		 srl   $19,$2,31         	 # Set Sign
66721		 sltiu $18,$2,1         	 # Set Zero
66722		 addiu $15,$15,-12
66723		 bgez  $15,3f
66724		 lhu   $24,0x00($23)    	 # Delay slot
66725		 j     MainExit
66726	3:
66727		 sll   $7,$24,2         	 # Delay slot
66728		 addu  $7,$7,$30
66729		 lw    $7,0x00($7)
66730		 jr    $7
66731		 nop                    	 # Delay slot
66732
66733OP0_4a98:				#:
66734		 addiu $23,$23,2
66735
66736		 andi  $24,$24,0x07
66737
66738		 sll   $24,$24,2
66739		 addu  $24,$24,$21
66740		 lw    $14,0x20($24)
66741		 addiu $25,$14,4
66742		 sw    $25,0x20($24)
66743		 lw    $25,0x84($21)
66744		 sw    $15,m68k_ICount
66745		 or    $4,$0,$14
66746		 jalr  $25
66747		 sw    $23,0x4C($21)    	 # Delay slot
66748		 lw    $15,m68k_ICount
66749		 and   $16,$0,$0        	 # Clear Carry
66750		 and   $17,$0,$0        	 # Clear Overflow
66751		 srl   $19,$2,31         	 # Set Sign
66752		 sltiu $18,$2,1         	 # Set Zero
66753		 addiu $15,$15,-12
66754		 bgez  $15,3f
66755		 lhu   $24,0x00($23)    	 # Delay slot
66756		 j     MainExit
66757	3:
66758		 sll   $7,$24,2         	 # Delay slot
66759		 addu  $7,$7,$30
66760		 lw    $7,0x00($7)
66761		 jr    $7
66762		 nop                    	 # Delay slot
66763
66764OP0_4aa0:				#:
66765		 addiu $23,$23,2
66766
66767		 andi  $24,$24,0x07
66768
66769		 sll   $24,$24,2
66770		 addu  $24,$24,$21
66771		 lw    $14,0x20($24)
66772		 addiu $14,$14,-4
66773		 sw    $14,0x20($24)
66774		 lw    $25,0x84($21)
66775		 sw    $15,m68k_ICount
66776		 or    $4,$0,$14
66777		 jalr  $25
66778		 sw    $23,0x4C($21)    	 # Delay slot
66779		 lw    $15,m68k_ICount
66780		 and   $16,$0,$0        	 # Clear Carry
66781		 and   $17,$0,$0        	 # Clear Overflow
66782		 srl   $19,$2,31         	 # Set Sign
66783		 sltiu $18,$2,1         	 # Set Zero
66784		 addiu $15,$15,-14
66785		 bgez  $15,3f
66786		 lhu   $24,0x00($23)    	 # Delay slot
66787		 j     MainExit
66788	3:
66789		 sll   $7,$24,2         	 # Delay slot
66790		 addu  $7,$7,$30
66791		 lw    $7,0x00($7)
66792		 jr    $7
66793		 nop                    	 # Delay slot
66794
66795OP0_4aa8:				#:
66796		 addiu $23,$23,2
66797
66798		 andi  $24,$24,0x07
66799
66800		 lh    $7,0x00($23)
66801		 sll   $24,$24,2
66802		 addu  $24,$24,$21
66803		 lw    $14,0x20($24)
66804		 addiu $23,$23,2
66805		 addu  $14,$14,$7
66806		 lw    $25,0x84($21)
66807		 sw    $15,m68k_ICount
66808		 or    $4,$0,$14
66809		 jalr  $25
66810		 sw    $23,0x4C($21)    	 # Delay slot
66811		 lw    $15,m68k_ICount
66812		 and   $16,$0,$0        	 # Clear Carry
66813		 and   $17,$0,$0        	 # Clear Overflow
66814		 srl   $19,$2,31         	 # Set Sign
66815		 sltiu $18,$2,1         	 # Set Zero
66816		 addiu $15,$15,-16
66817		 bgez  $15,3f
66818		 lhu   $24,0x00($23)    	 # Delay slot
66819		 j     MainExit
66820	3:
66821		 sll   $7,$24,2         	 # Delay slot
66822		 addu  $7,$7,$30
66823		 lw    $7,0x00($7)
66824		 jr    $7
66825		 nop                    	 # Delay slot
66826
66827OP0_4ab0:				#:
66828		 addiu $23,$23,2
66829
66830		 andi  $24,$24,0x07
66831
66832		 sll   $24,$24,2
66833		 addu  $24,$24,$21
66834		 lw    $14,0x20($24)
66835		 lhu   $7,0x00($23)
66836		 addiu $23,$23,2
66837		 seb   $6,$7
66838		 or    $25,$0,$7
66839		 srl   $7,$7,12
66840		 andi  $25,$25,0x0800
66841		 sll   $7,$7,2
66842		 addu  $7,$7,$21
66843		 bne   $25,$0,0f
66844		 lw    $25,0x00($7)      	 # Delay slot
66845		 seh   $25,$25
66846	0:
66847		 addu  $25,$14,$25
66848		 addu  $14,$25,$6
66849		 lw    $25,0x84($21)
66850		 sw    $15,m68k_ICount
66851		 or    $4,$0,$14
66852		 jalr  $25
66853		 sw    $23,0x4C($21)    	 # Delay slot
66854		 lw    $15,m68k_ICount
66855		 and   $16,$0,$0        	 # Clear Carry
66856		 and   $17,$0,$0        	 # Clear Overflow
66857		 srl   $19,$2,31         	 # Set Sign
66858		 sltiu $18,$2,1         	 # Set Zero
66859		 addiu $15,$15,-18
66860		 bgez  $15,3f
66861		 lhu   $24,0x00($23)    	 # Delay slot
66862		 j     MainExit
66863	3:
66864		 sll   $7,$24,2         	 # Delay slot
66865		 addu  $7,$7,$30
66866		 lw    $7,0x00($7)
66867		 jr    $7
66868		 nop                    	 # Delay slot
66869
66870OP0_4ab8:				#:
66871		 addiu $23,$23,2
66872
66873		 lh    $14,0x00($23)
66874		 addiu $23,$23,2
66875		 lw    $25,0x84($21)
66876		 sw    $15,m68k_ICount
66877		 or    $4,$0,$14
66878		 jalr  $25
66879		 sw    $23,0x4C($21)    	 # Delay slot
66880		 lw    $15,m68k_ICount
66881		 and   $16,$0,$0        	 # Clear Carry
66882		 and   $17,$0,$0        	 # Clear Overflow
66883		 srl   $19,$2,31         	 # Set Sign
66884		 sltiu $18,$2,1         	 # Set Zero
66885		 addiu $15,$15,-16
66886		 bgez  $15,3f
66887		 lhu   $24,0x00($23)    	 # Delay slot
66888		 j     MainExit
66889	3:
66890		 sll   $7,$24,2         	 # Delay slot
66891		 addu  $7,$7,$30
66892		 lw    $7,0x00($7)
66893		 jr    $7
66894		 nop                    	 # Delay slot
66895
66896OP0_4ab9:				#:
66897		 addiu $23,$23,2
66898
66899		 lhu   $14,0x00($23)
66900		 lhu   $25,0x02($23)
66901		 sll   $14,$14,16
66902		 or    $14,$14,$25
66903		 addiu $23,$23,4
66904		 lw    $25,0x84($21)
66905		 sw    $15,m68k_ICount
66906		 or    $4,$0,$14
66907		 jalr  $25
66908		 sw    $23,0x4C($21)    	 # Delay slot
66909		 lw    $15,m68k_ICount
66910		 and   $16,$0,$0        	 # Clear Carry
66911		 and   $17,$0,$0        	 # Clear Overflow
66912		 srl   $19,$2,31         	 # Set Sign
66913		 sltiu $18,$2,1         	 # Set Zero
66914		 addiu $15,$15,-20
66915		 bgez  $15,3f
66916		 lhu   $24,0x00($23)    	 # Delay slot
66917		 j     MainExit
66918	3:
66919		 sll   $7,$24,2         	 # Delay slot
66920		 addu  $7,$7,$30
66921		 lw    $7,0x00($7)
66922		 jr    $7
66923		 nop                    	 # Delay slot
66924
66925OP0_4890:				#:
66926		 addiu $23,$23,2
66927
66928		 lhu   $12,0x00($23)
66929		 addiu $23,$23,2
66930		 andi  $24,$24,0x07
66931		 sll   $24,$24,2
66932		 addu  $24,$24,$21
66933		 lw    $14,0x20($24)
66934		 ori   $8,$0,1
66935		 or    $9,$0,$21
66936	9:
66937		 and   $10,$12,$8
66938		 beq   $10,$0,8f
66939		 lw    $5,0x00($9)      	 # Delay slot
66940		 lw    $25,0x8C($21)
66941		 sw    $15,m68k_ICount
66942		 sw    $8,0x44($29)
66943		 sw    $9,0x40($29)
66944		 sw    $12,0x3C($29)
66945		 sw    $14,0x38($29)
66946		 or    $4,$0,$14
66947		 jalr  $25
66948		 sw    $23,0x4C($21)    	 # Delay slot
66949		 lw    $14,0x38($29)
66950		 lw    $12,0x3C($29)
66951		 lw    $9,0x40($29)
66952		 lw    $8,0x44($29)
66953		 lw    $15,m68k_ICount
66954		 addiu $14,$14,2
66955		 addiu $15,$15,-4
66956	8:
66957		 sll   $8,$8,1
66958		 andi  $7,$8,0xffff
66959		 bne   $7,$0,9b
66960		 addiu $9,$9,4          	 # Delay slot
66961		 addiu $15,$15,-16
66962		 bgez  $15,3f
66963		 lhu   $24,0x00($23)    	 # Delay slot
66964		 j     MainExit
66965	3:
66966		 sll   $7,$24,2         	 # Delay slot
66967		 addu  $7,$7,$30
66968		 lw    $7,0x00($7)
66969		 jr    $7
66970		 nop                    	 # Delay slot
66971
66972OP0_48a0:				#:
66973		 addiu $23,$23,2
66974
66975		 lhu   $12,0x00($23)
66976		 addiu $23,$23,2
66977		 andi  $24,$24,0x07
66978		 sll   $24,$24,2
66979		 addu  $24,$24,$21
66980		 lw    $14,0x20($24)
66981		 ori   $8,$0,1
66982		 addiu $9,$21,0x3C
66983	9:
66984		 and   $10,$12,$8
66985		 beq   $10,$0,8f
66986		 lw    $5,0x00($9)      	 # Delay slot
66987		 addiu $14,$14,-2
66988		 lw    $25,0x8C($21)
66989		 sw    $15,m68k_ICount
66990		 sw    $8,0x44($29)
66991		 sw    $9,0x40($29)
66992		 sw    $12,0x3C($29)
66993		 sw    $14,0x38($29)
66994		 sw    $24,0x34($29)
66995		 or    $4,$0,$14
66996		 jalr  $25
66997		 sw    $23,0x4C($21)    	 # Delay slot
66998		 lw    $24,0x34($29)
66999		 lw    $14,0x38($29)
67000		 lw    $12,0x3C($29)
67001		 lw    $9,0x40($29)
67002		 lw    $8,0x44($29)
67003		 lw    $15,m68k_ICount
67004		 addiu $15,$15,-4
67005	8:
67006		 sll   $8,$8,1
67007		 andi  $7,$8,0xffff
67008		 bne   $7,$0,9b
67009		 addiu $9,$9,-4         	 # Delay slot
67010		 sw    $14,0x20($24)
67011		 addiu $15,$15,-8
67012		 bgez  $15,3f
67013		 lhu   $24,0x00($23)    	 # Delay slot
67014		 j     MainExit
67015	3:
67016		 sll   $7,$24,2         	 # Delay slot
67017		 addu  $7,$7,$30
67018		 lw    $7,0x00($7)
67019		 jr    $7
67020		 nop                    	 # Delay slot
67021
67022OP0_48a8:				#:
67023		 addiu $23,$23,2
67024
67025		 lhu   $12,0x00($23)
67026		 addiu $23,$23,2
67027		 andi  $24,$24,0x07
67028		 lh    $7,0x00($23)
67029		 sll   $24,$24,2
67030		 addu  $24,$24,$21
67031		 lw    $14,0x20($24)
67032		 addiu $23,$23,2
67033		 addu  $14,$14,$7
67034		 ori   $8,$0,1
67035		 or    $9,$0,$21
67036	9:
67037		 and   $10,$12,$8
67038		 beq   $10,$0,8f
67039		 lw    $5,0x00($9)      	 # Delay slot
67040		 lw    $25,0x8C($21)
67041		 sw    $15,m68k_ICount
67042		 sw    $8,0x44($29)
67043		 sw    $9,0x40($29)
67044		 sw    $12,0x3C($29)
67045		 sw    $14,0x38($29)
67046		 or    $4,$0,$14
67047		 jalr  $25
67048		 sw    $23,0x4C($21)    	 # Delay slot
67049		 lw    $14,0x38($29)
67050		 lw    $12,0x3C($29)
67051		 lw    $9,0x40($29)
67052		 lw    $8,0x44($29)
67053		 lw    $15,m68k_ICount
67054		 addiu $14,$14,2
67055		 addiu $15,$15,-4
67056	8:
67057		 sll   $8,$8,1
67058		 andi  $7,$8,0xffff
67059		 bne   $7,$0,9b
67060		 addiu $9,$9,4          	 # Delay slot
67061		 addiu $15,$15,-24
67062		 bgez  $15,3f
67063		 lhu   $24,0x00($23)    	 # Delay slot
67064		 j     MainExit
67065	3:
67066		 sll   $7,$24,2         	 # Delay slot
67067		 addu  $7,$7,$30
67068		 lw    $7,0x00($7)
67069		 jr    $7
67070		 nop                    	 # Delay slot
67071
67072OP0_48b0:				#:
67073		 addiu $23,$23,2
67074
67075		 lhu   $12,0x00($23)
67076		 addiu $23,$23,2
67077		 andi  $24,$24,0x07
67078		 sll   $24,$24,2
67079		 addu  $24,$24,$21
67080		 lw    $14,0x20($24)
67081		 lhu   $7,0x00($23)
67082		 addiu $23,$23,2
67083		 seb   $6,$7
67084		 or    $25,$0,$7
67085		 srl   $7,$7,12
67086		 andi  $25,$25,0x0800
67087		 sll   $7,$7,2
67088		 addu  $7,$7,$21
67089		 bne   $25,$0,0f
67090		 lw    $25,0x00($7)      	 # Delay slot
67091		 seh   $25,$25
67092	0:
67093		 addu  $25,$14,$25
67094		 addu  $14,$25,$6
67095		 ori   $8,$0,1
67096		 or    $9,$0,$21
67097	9:
67098		 and   $10,$12,$8
67099		 beq   $10,$0,8f
67100		 lw    $5,0x00($9)      	 # Delay slot
67101		 lw    $25,0x8C($21)
67102		 sw    $15,m68k_ICount
67103		 sw    $8,0x44($29)
67104		 sw    $9,0x40($29)
67105		 sw    $12,0x3C($29)
67106		 sw    $14,0x38($29)
67107		 or    $4,$0,$14
67108		 jalr  $25
67109		 sw    $23,0x4C($21)    	 # Delay slot
67110		 lw    $14,0x38($29)
67111		 lw    $12,0x3C($29)
67112		 lw    $9,0x40($29)
67113		 lw    $8,0x44($29)
67114		 lw    $15,m68k_ICount
67115		 addiu $14,$14,2
67116		 addiu $15,$15,-4
67117	8:
67118		 sll   $8,$8,1
67119		 andi  $7,$8,0xffff
67120		 bne   $7,$0,9b
67121		 addiu $9,$9,4          	 # Delay slot
67122		 addiu $15,$15,-28
67123		 bgez  $15,3f
67124		 lhu   $24,0x00($23)    	 # Delay slot
67125		 j     MainExit
67126	3:
67127		 sll   $7,$24,2         	 # Delay slot
67128		 addu  $7,$7,$30
67129		 lw    $7,0x00($7)
67130		 jr    $7
67131		 nop                    	 # Delay slot
67132
67133OP0_48b8:				#:
67134		 addiu $23,$23,2
67135
67136		 lhu   $12,0x00($23)
67137		 addiu $23,$23,2
67138		 lh    $14,0x00($23)
67139		 addiu $23,$23,2
67140		 ori   $8,$0,1
67141		 or    $9,$0,$21
67142	9:
67143		 and   $10,$12,$8
67144		 beq   $10,$0,8f
67145		 lw    $5,0x00($9)      	 # Delay slot
67146		 lw    $25,0x8C($21)
67147		 sw    $15,m68k_ICount
67148		 sw    $8,0x44($29)
67149		 sw    $9,0x40($29)
67150		 sw    $12,0x3C($29)
67151		 sw    $14,0x38($29)
67152		 or    $4,$0,$14
67153		 jalr  $25
67154		 sw    $23,0x4C($21)    	 # Delay slot
67155		 lw    $14,0x38($29)
67156		 lw    $12,0x3C($29)
67157		 lw    $9,0x40($29)
67158		 lw    $8,0x44($29)
67159		 lw    $15,m68k_ICount
67160		 addiu $14,$14,2
67161		 addiu $15,$15,-4
67162	8:
67163		 sll   $8,$8,1
67164		 andi  $7,$8,0xffff
67165		 bne   $7,$0,9b
67166		 addiu $9,$9,4          	 # Delay slot
67167		 addiu $15,$15,-24
67168		 bgez  $15,3f
67169		 lhu   $24,0x00($23)    	 # Delay slot
67170		 j     MainExit
67171	3:
67172		 sll   $7,$24,2         	 # Delay slot
67173		 addu  $7,$7,$30
67174		 lw    $7,0x00($7)
67175		 jr    $7
67176		 nop                    	 # Delay slot
67177
67178OP0_48b9:				#:
67179		 addiu $23,$23,2
67180
67181		 lhu   $12,0x00($23)
67182		 addiu $23,$23,2
67183		 lhu   $14,0x00($23)
67184		 lhu   $25,0x02($23)
67185		 sll   $14,$14,16
67186		 or    $14,$14,$25
67187		 addiu $23,$23,4
67188		 ori   $8,$0,1
67189		 or    $9,$0,$21
67190	9:
67191		 and   $10,$12,$8
67192		 beq   $10,$0,8f
67193		 lw    $5,0x00($9)      	 # Delay slot
67194		 lw    $25,0x8C($21)
67195		 sw    $15,m68k_ICount
67196		 sw    $8,0x44($29)
67197		 sw    $9,0x40($29)
67198		 sw    $12,0x3C($29)
67199		 sw    $14,0x38($29)
67200		 or    $4,$0,$14
67201		 jalr  $25
67202		 sw    $23,0x4C($21)    	 # Delay slot
67203		 lw    $14,0x38($29)
67204		 lw    $12,0x3C($29)
67205		 lw    $9,0x40($29)
67206		 lw    $8,0x44($29)
67207		 lw    $15,m68k_ICount
67208		 addiu $14,$14,2
67209		 addiu $15,$15,-4
67210	8:
67211		 sll   $8,$8,1
67212		 andi  $7,$8,0xffff
67213		 bne   $7,$0,9b
67214		 addiu $9,$9,4          	 # Delay slot
67215		 addiu $15,$15,-28
67216		 bgez  $15,3f
67217		 lhu   $24,0x00($23)    	 # Delay slot
67218		 j     MainExit
67219	3:
67220		 sll   $7,$24,2         	 # Delay slot
67221		 addu  $7,$7,$30
67222		 lw    $7,0x00($7)
67223		 jr    $7
67224		 nop                    	 # Delay slot
67225
67226OP0_48d0:				#:
67227		 addiu $23,$23,2
67228
67229		 lhu   $12,0x00($23)
67230		 addiu $23,$23,2
67231		 andi  $24,$24,0x07
67232		 sll   $24,$24,2
67233		 addu  $24,$24,$21
67234		 lw    $14,0x20($24)
67235		 ori   $8,$0,1
67236		 or    $9,$0,$21
67237	9:
67238		 and   $10,$12,$8
67239		 beq   $10,$0,8f
67240		 lw    $5,0x00($9)      	 # Delay slot
67241		 lw    $25,0x90($21)
67242		 sw    $15,m68k_ICount
67243		 sw    $8,0x44($29)
67244		 sw    $9,0x40($29)
67245		 sw    $12,0x3C($29)
67246		 sw    $14,0x38($29)
67247		 or    $4,$0,$14
67248		 jalr  $25
67249		 sw    $23,0x4C($21)    	 # Delay slot
67250		 lw    $14,0x38($29)
67251		 lw    $12,0x3C($29)
67252		 lw    $9,0x40($29)
67253		 lw    $8,0x44($29)
67254		 lw    $15,m68k_ICount
67255		 addiu $14,$14,4
67256		 addiu $15,$15,-8
67257	8:
67258		 sll   $8,$8,1
67259		 andi  $7,$8,0xffff
67260		 bne   $7,$0,9b
67261		 addiu $9,$9,4          	 # Delay slot
67262		 addiu $15,$15,-16
67263		 bgez  $15,3f
67264		 lhu   $24,0x00($23)    	 # Delay slot
67265		 j     MainExit
67266	3:
67267		 sll   $7,$24,2         	 # Delay slot
67268		 addu  $7,$7,$30
67269		 lw    $7,0x00($7)
67270		 jr    $7
67271		 nop                    	 # Delay slot
67272
67273OP0_48e0:				#:
67274		 addiu $23,$23,2
67275
67276		 lhu   $12,0x00($23)
67277		 addiu $23,$23,2
67278		 andi  $24,$24,0x07
67279		 sll   $24,$24,2
67280		 addu  $24,$24,$21
67281		 lw    $14,0x20($24)
67282		 ori   $8,$0,1
67283		 addiu $9,$21,0x3C
67284	9:
67285		 and   $10,$12,$8
67286		 beq   $10,$0,8f
67287		 lw    $5,0x00($9)      	 # Delay slot
67288		 addiu $14,$14,-4
67289		 lw    $25,0x90($21)
67290		 sw    $15,m68k_ICount
67291		 sw    $8,0x44($29)
67292		 sw    $9,0x40($29)
67293		 sw    $12,0x3C($29)
67294		 sw    $14,0x38($29)
67295		 sw    $24,0x34($29)
67296		 or    $4,$0,$14
67297		 jalr  $25
67298		 sw    $23,0x4C($21)    	 # Delay slot
67299		 lw    $24,0x34($29)
67300		 lw    $14,0x38($29)
67301		 lw    $12,0x3C($29)
67302		 lw    $9,0x40($29)
67303		 lw    $8,0x44($29)
67304		 lw    $15,m68k_ICount
67305		 addiu $15,$15,-8
67306	8:
67307		 sll   $8,$8,1
67308		 andi  $7,$8,0xffff
67309		 bne   $7,$0,9b
67310		 addiu $9,$9,-4         	 # Delay slot
67311		 sw    $14,0x20($24)
67312		 addiu $15,$15,-8
67313		 bgez  $15,3f
67314		 lhu   $24,0x00($23)    	 # Delay slot
67315		 j     MainExit
67316	3:
67317		 sll   $7,$24,2         	 # Delay slot
67318		 addu  $7,$7,$30
67319		 lw    $7,0x00($7)
67320		 jr    $7
67321		 nop                    	 # Delay slot
67322
67323OP0_48e8:				#:
67324		 addiu $23,$23,2
67325
67326		 lhu   $12,0x00($23)
67327		 addiu $23,$23,2
67328		 andi  $24,$24,0x07
67329		 lh    $7,0x00($23)
67330		 sll   $24,$24,2
67331		 addu  $24,$24,$21
67332		 lw    $14,0x20($24)
67333		 addiu $23,$23,2
67334		 addu  $14,$14,$7
67335		 ori   $8,$0,1
67336		 or    $9,$0,$21
67337	9:
67338		 and   $10,$12,$8
67339		 beq   $10,$0,8f
67340		 lw    $5,0x00($9)      	 # Delay slot
67341		 lw    $25,0x90($21)
67342		 sw    $15,m68k_ICount
67343		 sw    $8,0x44($29)
67344		 sw    $9,0x40($29)
67345		 sw    $12,0x3C($29)
67346		 sw    $14,0x38($29)
67347		 or    $4,$0,$14
67348		 jalr  $25
67349		 sw    $23,0x4C($21)    	 # Delay slot
67350		 lw    $14,0x38($29)
67351		 lw    $12,0x3C($29)
67352		 lw    $9,0x40($29)
67353		 lw    $8,0x44($29)
67354		 lw    $15,m68k_ICount
67355		 addiu $14,$14,4
67356		 addiu $15,$15,-8
67357	8:
67358		 sll   $8,$8,1
67359		 andi  $7,$8,0xffff
67360		 bne   $7,$0,9b
67361		 addiu $9,$9,4          	 # Delay slot
67362		 addiu $15,$15,-24
67363		 bgez  $15,3f
67364		 lhu   $24,0x00($23)    	 # Delay slot
67365		 j     MainExit
67366	3:
67367		 sll   $7,$24,2         	 # Delay slot
67368		 addu  $7,$7,$30
67369		 lw    $7,0x00($7)
67370		 jr    $7
67371		 nop                    	 # Delay slot
67372
67373OP0_48f0:				#:
67374		 addiu $23,$23,2
67375
67376		 lhu   $12,0x00($23)
67377		 addiu $23,$23,2
67378		 andi  $24,$24,0x07
67379		 sll   $24,$24,2
67380		 addu  $24,$24,$21
67381		 lw    $14,0x20($24)
67382		 lhu   $7,0x00($23)
67383		 addiu $23,$23,2
67384		 seb   $6,$7
67385		 or    $25,$0,$7
67386		 srl   $7,$7,12
67387		 andi  $25,$25,0x0800
67388		 sll   $7,$7,2
67389		 addu  $7,$7,$21
67390		 bne   $25,$0,0f
67391		 lw    $25,0x00($7)      	 # Delay slot
67392		 seh   $25,$25
67393	0:
67394		 addu  $25,$14,$25
67395		 addu  $14,$25,$6
67396		 ori   $8,$0,1
67397		 or    $9,$0,$21
67398	9:
67399		 and   $10,$12,$8
67400		 beq   $10,$0,8f
67401		 lw    $5,0x00($9)      	 # Delay slot
67402		 lw    $25,0x90($21)
67403		 sw    $15,m68k_ICount
67404		 sw    $8,0x44($29)
67405		 sw    $9,0x40($29)
67406		 sw    $12,0x3C($29)
67407		 sw    $14,0x38($29)
67408		 or    $4,$0,$14
67409		 jalr  $25
67410		 sw    $23,0x4C($21)    	 # Delay slot
67411		 lw    $14,0x38($29)
67412		 lw    $12,0x3C($29)
67413		 lw    $9,0x40($29)
67414		 lw    $8,0x44($29)
67415		 lw    $15,m68k_ICount
67416		 addiu $14,$14,4
67417		 addiu $15,$15,-8
67418	8:
67419		 sll   $8,$8,1
67420		 andi  $7,$8,0xffff
67421		 bne   $7,$0,9b
67422		 addiu $9,$9,4          	 # Delay slot
67423		 addiu $15,$15,-28
67424		 bgez  $15,3f
67425		 lhu   $24,0x00($23)    	 # Delay slot
67426		 j     MainExit
67427	3:
67428		 sll   $7,$24,2         	 # Delay slot
67429		 addu  $7,$7,$30
67430		 lw    $7,0x00($7)
67431		 jr    $7
67432		 nop                    	 # Delay slot
67433
67434OP0_48f8:				#:
67435		 addiu $23,$23,2
67436
67437		 lhu   $12,0x00($23)
67438		 addiu $23,$23,2
67439		 lh    $14,0x00($23)
67440		 addiu $23,$23,2
67441		 ori   $8,$0,1
67442		 or    $9,$0,$21
67443	9:
67444		 and   $10,$12,$8
67445		 beq   $10,$0,8f
67446		 lw    $5,0x00($9)      	 # Delay slot
67447		 lw    $25,0x90($21)
67448		 sw    $15,m68k_ICount
67449		 sw    $8,0x44($29)
67450		 sw    $9,0x40($29)
67451		 sw    $12,0x3C($29)
67452		 sw    $14,0x38($29)
67453		 or    $4,$0,$14
67454		 jalr  $25
67455		 sw    $23,0x4C($21)    	 # Delay slot
67456		 lw    $14,0x38($29)
67457		 lw    $12,0x3C($29)
67458		 lw    $9,0x40($29)
67459		 lw    $8,0x44($29)
67460		 lw    $15,m68k_ICount
67461		 addiu $14,$14,4
67462		 addiu $15,$15,-8
67463	8:
67464		 sll   $8,$8,1
67465		 andi  $7,$8,0xffff
67466		 bne   $7,$0,9b
67467		 addiu $9,$9,4          	 # Delay slot
67468		 addiu $15,$15,-24
67469		 bgez  $15,3f
67470		 lhu   $24,0x00($23)    	 # Delay slot
67471		 j     MainExit
67472	3:
67473		 sll   $7,$24,2         	 # Delay slot
67474		 addu  $7,$7,$30
67475		 lw    $7,0x00($7)
67476		 jr    $7
67477		 nop                    	 # Delay slot
67478
67479OP0_48f9:				#:
67480		 addiu $23,$23,2
67481
67482		 lhu   $12,0x00($23)
67483		 addiu $23,$23,2
67484		 lhu   $14,0x00($23)
67485		 lhu   $25,0x02($23)
67486		 sll   $14,$14,16
67487		 or    $14,$14,$25
67488		 addiu $23,$23,4
67489		 ori   $8,$0,1
67490		 or    $9,$0,$21
67491	9:
67492		 and   $10,$12,$8
67493		 beq   $10,$0,8f
67494		 lw    $5,0x00($9)      	 # Delay slot
67495		 lw    $25,0x90($21)
67496		 sw    $15,m68k_ICount
67497		 sw    $8,0x44($29)
67498		 sw    $9,0x40($29)
67499		 sw    $12,0x3C($29)
67500		 sw    $14,0x38($29)
67501		 or    $4,$0,$14
67502		 jalr  $25
67503		 sw    $23,0x4C($21)    	 # Delay slot
67504		 lw    $14,0x38($29)
67505		 lw    $12,0x3C($29)
67506		 lw    $9,0x40($29)
67507		 lw    $8,0x44($29)
67508		 lw    $15,m68k_ICount
67509		 addiu $14,$14,4
67510		 addiu $15,$15,-8
67511	8:
67512		 sll   $8,$8,1
67513		 andi  $7,$8,0xffff
67514		 bne   $7,$0,9b
67515		 addiu $9,$9,4          	 # Delay slot
67516		 addiu $15,$15,-28
67517		 bgez  $15,3f
67518		 lhu   $24,0x00($23)    	 # Delay slot
67519		 j     MainExit
67520	3:
67521		 sll   $7,$24,2         	 # Delay slot
67522		 addu  $7,$7,$30
67523		 lw    $7,0x00($7)
67524		 jr    $7
67525		 nop                    	 # Delay slot
67526
67527OP0_4c90:				#:
67528		 addiu $23,$23,2
67529
67530		 lhu   $12,0x00($23)
67531		 addiu $23,$23,2
67532		 andi  $24,$24,0x07
67533		 sll   $24,$24,2
67534		 addu  $24,$24,$21
67535		 lw    $14,0x20($24)
67536		 ori   $8,$0,1
67537		 or    $9,$0,$21
67538	9:
67539		 and   $10,$12,$8
67540		 beq   $10,$0,8f
67541		 nop                    	 # Delay slot
67542		 lw    $25,0x80($21)
67543		 sw    $15,m68k_ICount
67544		 sw    $8,0x44($29)
67545		 sw    $9,0x40($29)
67546		 sw    $12,0x3C($29)
67547		 sw    $14,0x38($29)
67548		 or    $4,$0,$14
67549		 jalr  $25
67550		 sw    $23,0x4C($21)    	 # Delay slot
67551		 lw    $14,0x38($29)
67552		 lw    $12,0x3C($29)
67553		 lw    $9,0x40($29)
67554		 lw    $8,0x44($29)
67555		 lw    $15,m68k_ICount
67556		 sll   $2,$2,16
67557		 sra   $2,$2,16
67558		 sw    $2,0x00($9)
67559		 addiu $14,$14,2
67560		 addiu $15,$15,-4
67561	8:
67562		 sll   $8,$8,1
67563		 andi  $7,$8,0xffff
67564		 bne   $7,$0,9b
67565		 addiu $9,$9,4          	 # Delay slot
67566		 addiu $15,$15,-16
67567		 bgez  $15,3f
67568		 lhu   $24,0x00($23)    	 # Delay slot
67569		 j     MainExit
67570	3:
67571		 sll   $7,$24,2         	 # Delay slot
67572		 addu  $7,$7,$30
67573		 lw    $7,0x00($7)
67574		 jr    $7
67575		 nop                    	 # Delay slot
67576
67577OP0_4c98:				#:
67578		 addiu $23,$23,2
67579
67580		 lhu   $12,0x00($23)
67581		 addiu $23,$23,2
67582		 andi  $24,$24,0x07
67583		 sll   $24,$24,2
67584		 addu  $24,$24,$21
67585		 lw    $14,0x20($24)
67586		 addiu $25,$14,4
67587		 sw    $25,0x20($24)
67588		 ori   $8,$0,1
67589		 or    $9,$0,$21
67590	9:
67591		 and   $10,$12,$8
67592		 beq   $10,$0,8f
67593		 nop                    	 # Delay slot
67594		 lw    $25,0x80($21)
67595		 sw    $15,m68k_ICount
67596		 sw    $8,0x44($29)
67597		 sw    $9,0x40($29)
67598		 sw    $12,0x3C($29)
67599		 sw    $14,0x38($29)
67600		 sw    $24,0x34($29)
67601		 or    $4,$0,$14
67602		 jalr  $25
67603		 sw    $23,0x4C($21)    	 # Delay slot
67604		 lw    $24,0x34($29)
67605		 lw    $14,0x38($29)
67606		 lw    $12,0x3C($29)
67607		 lw    $9,0x40($29)
67608		 lw    $8,0x44($29)
67609		 lw    $15,m68k_ICount
67610		 sll   $2,$2,16
67611		 sra   $2,$2,16
67612		 sw    $2,0x00($9)
67613		 addiu $14,$14,2
67614		 addiu $15,$15,-4
67615	8:
67616		 sll   $8,$8,1
67617		 andi  $7,$8,0xffff
67618		 bne   $7,$0,9b
67619		 addiu $9,$9,4          	 # Delay slot
67620		 sw    $14,0x20($24)
67621		 bgez  $15,3f
67622		 lhu   $24,0x00($23)    	 # Delay slot
67623		 j     MainExit
67624	3:
67625		 sll   $7,$24,2         	 # Delay slot
67626		 addu  $7,$7,$30
67627		 lw    $7,0x00($7)
67628		 jr    $7
67629		 nop                    	 # Delay slot
67630
67631OP0_4ca8:				#:
67632		 addiu $23,$23,2
67633
67634		 lhu   $12,0x00($23)
67635		 addiu $23,$23,2
67636		 andi  $24,$24,0x07
67637		 lh    $7,0x00($23)
67638		 sll   $24,$24,2
67639		 addu  $24,$24,$21
67640		 lw    $14,0x20($24)
67641		 addiu $23,$23,2
67642		 addu  $14,$14,$7
67643		 ori   $8,$0,1
67644		 or    $9,$0,$21
67645	9:
67646		 and   $10,$12,$8
67647		 beq   $10,$0,8f
67648		 nop                    	 # Delay slot
67649		 lw    $25,0x80($21)
67650		 sw    $15,m68k_ICount
67651		 sw    $8,0x44($29)
67652		 sw    $9,0x40($29)
67653		 sw    $12,0x3C($29)
67654		 sw    $14,0x38($29)
67655		 or    $4,$0,$14
67656		 jalr  $25
67657		 sw    $23,0x4C($21)    	 # Delay slot
67658		 lw    $14,0x38($29)
67659		 lw    $12,0x3C($29)
67660		 lw    $9,0x40($29)
67661		 lw    $8,0x44($29)
67662		 lw    $15,m68k_ICount
67663		 sll   $2,$2,16
67664		 sra   $2,$2,16
67665		 sw    $2,0x00($9)
67666		 addiu $14,$14,2
67667		 addiu $15,$15,-4
67668	8:
67669		 sll   $8,$8,1
67670		 andi  $7,$8,0xffff
67671		 bne   $7,$0,9b
67672		 addiu $9,$9,4          	 # Delay slot
67673		 addiu $15,$15,-24
67674		 bgez  $15,3f
67675		 lhu   $24,0x00($23)    	 # Delay slot
67676		 j     MainExit
67677	3:
67678		 sll   $7,$24,2         	 # Delay slot
67679		 addu  $7,$7,$30
67680		 lw    $7,0x00($7)
67681		 jr    $7
67682		 nop                    	 # Delay slot
67683
67684OP0_4cb0:				#:
67685		 addiu $23,$23,2
67686
67687		 lhu   $12,0x00($23)
67688		 addiu $23,$23,2
67689		 andi  $24,$24,0x07
67690		 sll   $24,$24,2
67691		 addu  $24,$24,$21
67692		 lw    $14,0x20($24)
67693		 lhu   $7,0x00($23)
67694		 addiu $23,$23,2
67695		 seb   $6,$7
67696		 or    $25,$0,$7
67697		 srl   $7,$7,12
67698		 andi  $25,$25,0x0800
67699		 sll   $7,$7,2
67700		 addu  $7,$7,$21
67701		 bne   $25,$0,0f
67702		 lw    $25,0x00($7)      	 # Delay slot
67703		 seh   $25,$25
67704	0:
67705		 addu  $25,$14,$25
67706		 addu  $14,$25,$6
67707		 ori   $8,$0,1
67708		 or    $9,$0,$21
67709	9:
67710		 and   $10,$12,$8
67711		 beq   $10,$0,8f
67712		 nop                    	 # Delay slot
67713		 lw    $25,0x80($21)
67714		 sw    $15,m68k_ICount
67715		 sw    $8,0x44($29)
67716		 sw    $9,0x40($29)
67717		 sw    $12,0x3C($29)
67718		 sw    $14,0x38($29)
67719		 or    $4,$0,$14
67720		 jalr  $25
67721		 sw    $23,0x4C($21)    	 # Delay slot
67722		 lw    $14,0x38($29)
67723		 lw    $12,0x3C($29)
67724		 lw    $9,0x40($29)
67725		 lw    $8,0x44($29)
67726		 lw    $15,m68k_ICount
67727		 sll   $2,$2,16
67728		 sra   $2,$2,16
67729		 sw    $2,0x00($9)
67730		 addiu $14,$14,2
67731		 addiu $15,$15,-4
67732	8:
67733		 sll   $8,$8,1
67734		 andi  $7,$8,0xffff
67735		 bne   $7,$0,9b
67736		 addiu $9,$9,4          	 # Delay slot
67737		 addiu $15,$15,-28
67738		 bgez  $15,3f
67739		 lhu   $24,0x00($23)    	 # Delay slot
67740		 j     MainExit
67741	3:
67742		 sll   $7,$24,2         	 # Delay slot
67743		 addu  $7,$7,$30
67744		 lw    $7,0x00($7)
67745		 jr    $7
67746		 nop                    	 # Delay slot
67747
67748OP0_4cb8:				#:
67749		 addiu $23,$23,2
67750
67751		 lhu   $12,0x00($23)
67752		 addiu $23,$23,2
67753		 lh    $14,0x00($23)
67754		 addiu $23,$23,2
67755		 ori   $8,$0,1
67756		 or    $9,$0,$21
67757	9:
67758		 and   $10,$12,$8
67759		 beq   $10,$0,8f
67760		 nop                    	 # Delay slot
67761		 lw    $25,0x80($21)
67762		 sw    $15,m68k_ICount
67763		 sw    $8,0x44($29)
67764		 sw    $9,0x40($29)
67765		 sw    $12,0x3C($29)
67766		 sw    $14,0x38($29)
67767		 or    $4,$0,$14
67768		 jalr  $25
67769		 sw    $23,0x4C($21)    	 # Delay slot
67770		 lw    $14,0x38($29)
67771		 lw    $12,0x3C($29)
67772		 lw    $9,0x40($29)
67773		 lw    $8,0x44($29)
67774		 lw    $15,m68k_ICount
67775		 sll   $2,$2,16
67776		 sra   $2,$2,16
67777		 sw    $2,0x00($9)
67778		 addiu $14,$14,2
67779		 addiu $15,$15,-4
67780	8:
67781		 sll   $8,$8,1
67782		 andi  $7,$8,0xffff
67783		 bne   $7,$0,9b
67784		 addiu $9,$9,4          	 # Delay slot
67785		 addiu $15,$15,-24
67786		 bgez  $15,3f
67787		 lhu   $24,0x00($23)    	 # Delay slot
67788		 j     MainExit
67789	3:
67790		 sll   $7,$24,2         	 # Delay slot
67791		 addu  $7,$7,$30
67792		 lw    $7,0x00($7)
67793		 jr    $7
67794		 nop                    	 # Delay slot
67795
67796OP0_4cb9:				#:
67797		 addiu $23,$23,2
67798
67799		 lhu   $12,0x00($23)
67800		 addiu $23,$23,2
67801		 lhu   $14,0x00($23)
67802		 lhu   $25,0x02($23)
67803		 sll   $14,$14,16
67804		 or    $14,$14,$25
67805		 addiu $23,$23,4
67806		 ori   $8,$0,1
67807		 or    $9,$0,$21
67808	9:
67809		 and   $10,$12,$8
67810		 beq   $10,$0,8f
67811		 nop                    	 # Delay slot
67812		 lw    $25,0x80($21)
67813		 sw    $15,m68k_ICount
67814		 sw    $8,0x44($29)
67815		 sw    $9,0x40($29)
67816		 sw    $12,0x3C($29)
67817		 sw    $14,0x38($29)
67818		 or    $4,$0,$14
67819		 jalr  $25
67820		 sw    $23,0x4C($21)    	 # Delay slot
67821		 lw    $14,0x38($29)
67822		 lw    $12,0x3C($29)
67823		 lw    $9,0x40($29)
67824		 lw    $8,0x44($29)
67825		 lw    $15,m68k_ICount
67826		 sll   $2,$2,16
67827		 sra   $2,$2,16
67828		 sw    $2,0x00($9)
67829		 addiu $14,$14,2
67830		 addiu $15,$15,-4
67831	8:
67832		 sll   $8,$8,1
67833		 andi  $7,$8,0xffff
67834		 bne   $7,$0,9b
67835		 addiu $9,$9,4          	 # Delay slot
67836		 addiu $15,$15,-28
67837		 bgez  $15,3f
67838		 lhu   $24,0x00($23)    	 # Delay slot
67839		 j     MainExit
67840	3:
67841		 sll   $7,$24,2         	 # Delay slot
67842		 addu  $7,$7,$30
67843		 lw    $7,0x00($7)
67844		 jr    $7
67845		 nop                    	 # Delay slot
67846
67847OP0_4cba:				#:
67848		 addiu $23,$23,2
67849
67850		 lhu   $12,0x00($23)
67851		 addiu $23,$23,2
67852		 lh    $7,0x00($23)
67853		 subu  $25,$23,$22
67854		 addu  $14,$25,$7       	 # Add Offset to PC
67855		 addiu $23,$23,2
67856		 ori   $8,$0,1
67857		 or    $9,$0,$21
67858	9:
67859		 and   $10,$12,$8
67860		 beq   $10,$0,8f
67861		 nop                    	 # Delay slot
67862		 lw    $25,0x9C($21)
67863		 sw    $15,m68k_ICount
67864		 sw    $8,0x44($29)
67865		 sw    $9,0x40($29)
67866		 sw    $12,0x3C($29)
67867		 sw    $14,0x38($29)
67868		 or    $4,$0,$14
67869		 jalr  $25
67870		 sw    $23,0x4C($21)    	 # Delay slot
67871		 lw    $14,0x38($29)
67872		 lw    $12,0x3C($29)
67873		 lw    $9,0x40($29)
67874		 lw    $8,0x44($29)
67875		 lw    $15,m68k_ICount
67876		 sll   $2,$2,16
67877		 sra   $2,$2,16
67878		 sw    $2,0x00($9)
67879		 addiu $14,$14,2
67880		 addiu $15,$15,-4
67881	8:
67882		 sll   $8,$8,1
67883		 andi  $7,$8,0xffff
67884		 bne   $7,$0,9b
67885		 addiu $9,$9,4          	 # Delay slot
67886		 addiu $15,$15,-24
67887		 bgez  $15,3f
67888		 lhu   $24,0x00($23)    	 # Delay slot
67889		 j     MainExit
67890	3:
67891		 sll   $7,$24,2         	 # Delay slot
67892		 addu  $7,$7,$30
67893		 lw    $7,0x00($7)
67894		 jr    $7
67895		 nop                    	 # Delay slot
67896
67897OP0_4cbb:				#:
67898		 addiu $23,$23,2
67899
67900		 lhu   $12,0x00($23)
67901		 addiu $23,$23,2
67902		 subu  $14,$23,$22       	 # Get PC
67903		 lhu   $7,0x00($23)
67904		 addiu $23,$23,2
67905		 seb   $6,$7
67906		 or    $25,$0,$7
67907		 srl   $7,$7,12
67908		 andi  $25,$25,0x0800
67909		 sll   $7,$7,2
67910		 addu  $7,$7,$21
67911		 bne   $25,$0,0f
67912		 lw    $25,0x00($7)      	 # Delay slot
67913		 seh   $25,$25
67914	0:
67915		 addu  $25,$14,$25
67916		 addu  $14,$25,$6
67917		 ori   $8,$0,1
67918		 or    $9,$0,$21
67919	9:
67920		 and   $10,$12,$8
67921		 beq   $10,$0,8f
67922		 nop                    	 # Delay slot
67923		 lw    $25,0x9C($21)
67924		 sw    $15,m68k_ICount
67925		 sw    $8,0x44($29)
67926		 sw    $9,0x40($29)
67927		 sw    $12,0x3C($29)
67928		 sw    $14,0x38($29)
67929		 or    $4,$0,$14
67930		 jalr  $25
67931		 sw    $23,0x4C($21)    	 # Delay slot
67932		 lw    $14,0x38($29)
67933		 lw    $12,0x3C($29)
67934		 lw    $9,0x40($29)
67935		 lw    $8,0x44($29)
67936		 lw    $15,m68k_ICount
67937		 sll   $2,$2,16
67938		 sra   $2,$2,16
67939		 sw    $2,0x00($9)
67940		 addiu $14,$14,2
67941		 addiu $15,$15,-4
67942	8:
67943		 sll   $8,$8,1
67944		 andi  $7,$8,0xffff
67945		 bne   $7,$0,9b
67946		 addiu $9,$9,4          	 # Delay slot
67947		 addiu $15,$15,-26
67948		 bgez  $15,3f
67949		 lhu   $24,0x00($23)    	 # Delay slot
67950		 j     MainExit
67951	3:
67952		 sll   $7,$24,2         	 # Delay slot
67953		 addu  $7,$7,$30
67954		 lw    $7,0x00($7)
67955		 jr    $7
67956		 nop                    	 # Delay slot
67957
67958OP0_4cd0:				#:
67959		 addiu $23,$23,2
67960
67961		 lhu   $12,0x00($23)
67962		 addiu $23,$23,2
67963		 andi  $24,$24,0x07
67964		 sll   $24,$24,2
67965		 addu  $24,$24,$21
67966		 lw    $14,0x20($24)
67967		 ori   $8,$0,1
67968		 or    $9,$0,$21
67969	9:
67970		 and   $10,$12,$8
67971		 beq   $10,$0,8f
67972		 nop                    	 # Delay slot
67973		 lw    $25,0x84($21)
67974		 sw    $15,m68k_ICount
67975		 sw    $8,0x44($29)
67976		 sw    $9,0x40($29)
67977		 sw    $12,0x3C($29)
67978		 sw    $14,0x38($29)
67979		 or    $4,$0,$14
67980		 jalr  $25
67981		 sw    $23,0x4C($21)    	 # Delay slot
67982		 lw    $14,0x38($29)
67983		 lw    $12,0x3C($29)
67984		 lw    $9,0x40($29)
67985		 lw    $8,0x44($29)
67986		 lw    $15,m68k_ICount
67987		 sw    $2,0x00($9)
67988		 addiu $14,$14,4
67989		 addiu $15,$15,-8
67990	8:
67991		 sll   $8,$8,1
67992		 andi  $7,$8,0xffff
67993		 bne   $7,$0,9b
67994		 addiu $9,$9,4          	 # Delay slot
67995		 addiu $15,$15,-16
67996		 bgez  $15,3f
67997		 lhu   $24,0x00($23)    	 # Delay slot
67998		 j     MainExit
67999	3:
68000		 sll   $7,$24,2         	 # Delay slot
68001		 addu  $7,$7,$30
68002		 lw    $7,0x00($7)
68003		 jr    $7
68004		 nop                    	 # Delay slot
68005
68006OP0_4cd8:				#:
68007		 addiu $23,$23,2
68008
68009		 lhu   $12,0x00($23)
68010		 addiu $23,$23,2
68011		 andi  $24,$24,0x07
68012		 sll   $24,$24,2
68013		 addu  $24,$24,$21
68014		 lw    $14,0x20($24)
68015		 addiu $25,$14,4
68016		 sw    $25,0x20($24)
68017		 ori   $8,$0,1
68018		 or    $9,$0,$21
68019	9:
68020		 and   $10,$12,$8
68021		 beq   $10,$0,8f
68022		 nop                    	 # Delay slot
68023		 lw    $25,0x84($21)
68024		 sw    $15,m68k_ICount
68025		 sw    $8,0x44($29)
68026		 sw    $9,0x40($29)
68027		 sw    $12,0x3C($29)
68028		 sw    $14,0x38($29)
68029		 sw    $24,0x34($29)
68030		 or    $4,$0,$14
68031		 jalr  $25
68032		 sw    $23,0x4C($21)    	 # Delay slot
68033		 lw    $24,0x34($29)
68034		 lw    $14,0x38($29)
68035		 lw    $12,0x3C($29)
68036		 lw    $9,0x40($29)
68037		 lw    $8,0x44($29)
68038		 lw    $15,m68k_ICount
68039		 sw    $2,0x00($9)
68040		 addiu $14,$14,4
68041		 addiu $15,$15,-8
68042	8:
68043		 sll   $8,$8,1
68044		 andi  $7,$8,0xffff
68045		 bne   $7,$0,9b
68046		 addiu $9,$9,4          	 # Delay slot
68047		 sw    $14,0x20($24)
68048		 bgez  $15,3f
68049		 lhu   $24,0x00($23)    	 # Delay slot
68050		 j     MainExit
68051	3:
68052		 sll   $7,$24,2         	 # Delay slot
68053		 addu  $7,$7,$30
68054		 lw    $7,0x00($7)
68055		 jr    $7
68056		 nop                    	 # Delay slot
68057
68058OP0_4ce8:				#:
68059		 addiu $23,$23,2
68060
68061		 lhu   $12,0x00($23)
68062		 addiu $23,$23,2
68063		 andi  $24,$24,0x07
68064		 lh    $7,0x00($23)
68065		 sll   $24,$24,2
68066		 addu  $24,$24,$21
68067		 lw    $14,0x20($24)
68068		 addiu $23,$23,2
68069		 addu  $14,$14,$7
68070		 ori   $8,$0,1
68071		 or    $9,$0,$21
68072	9:
68073		 and   $10,$12,$8
68074		 beq   $10,$0,8f
68075		 nop                    	 # Delay slot
68076		 lw    $25,0x84($21)
68077		 sw    $15,m68k_ICount
68078		 sw    $8,0x44($29)
68079		 sw    $9,0x40($29)
68080		 sw    $12,0x3C($29)
68081		 sw    $14,0x38($29)
68082		 or    $4,$0,$14
68083		 jalr  $25
68084		 sw    $23,0x4C($21)    	 # Delay slot
68085		 lw    $14,0x38($29)
68086		 lw    $12,0x3C($29)
68087		 lw    $9,0x40($29)
68088		 lw    $8,0x44($29)
68089		 lw    $15,m68k_ICount
68090		 sw    $2,0x00($9)
68091		 addiu $14,$14,4
68092		 addiu $15,$15,-8
68093	8:
68094		 sll   $8,$8,1
68095		 andi  $7,$8,0xffff
68096		 bne   $7,$0,9b
68097		 addiu $9,$9,4          	 # Delay slot
68098		 addiu $15,$15,-24
68099		 bgez  $15,3f
68100		 lhu   $24,0x00($23)    	 # Delay slot
68101		 j     MainExit
68102	3:
68103		 sll   $7,$24,2         	 # Delay slot
68104		 addu  $7,$7,$30
68105		 lw    $7,0x00($7)
68106		 jr    $7
68107		 nop                    	 # Delay slot
68108
68109OP0_4cf0:				#:
68110		 addiu $23,$23,2
68111
68112		 lhu   $12,0x00($23)
68113		 addiu $23,$23,2
68114		 andi  $24,$24,0x07
68115		 sll   $24,$24,2
68116		 addu  $24,$24,$21
68117		 lw    $14,0x20($24)
68118		 lhu   $7,0x00($23)
68119		 addiu $23,$23,2
68120		 seb   $6,$7
68121		 or    $25,$0,$7
68122		 srl   $7,$7,12
68123		 andi  $25,$25,0x0800
68124		 sll   $7,$7,2
68125		 addu  $7,$7,$21
68126		 bne   $25,$0,0f
68127		 lw    $25,0x00($7)      	 # Delay slot
68128		 seh   $25,$25
68129	0:
68130		 addu  $25,$14,$25
68131		 addu  $14,$25,$6
68132		 ori   $8,$0,1
68133		 or    $9,$0,$21
68134	9:
68135		 and   $10,$12,$8
68136		 beq   $10,$0,8f
68137		 nop                    	 # Delay slot
68138		 lw    $25,0x84($21)
68139		 sw    $15,m68k_ICount
68140		 sw    $8,0x44($29)
68141		 sw    $9,0x40($29)
68142		 sw    $12,0x3C($29)
68143		 sw    $14,0x38($29)
68144		 or    $4,$0,$14
68145		 jalr  $25
68146		 sw    $23,0x4C($21)    	 # Delay slot
68147		 lw    $14,0x38($29)
68148		 lw    $12,0x3C($29)
68149		 lw    $9,0x40($29)
68150		 lw    $8,0x44($29)
68151		 lw    $15,m68k_ICount
68152		 sw    $2,0x00($9)
68153		 addiu $14,$14,4
68154		 addiu $15,$15,-8
68155	8:
68156		 sll   $8,$8,1
68157		 andi  $7,$8,0xffff
68158		 bne   $7,$0,9b
68159		 addiu $9,$9,4          	 # Delay slot
68160		 addiu $15,$15,-28
68161		 bgez  $15,3f
68162		 lhu   $24,0x00($23)    	 # Delay slot
68163		 j     MainExit
68164	3:
68165		 sll   $7,$24,2         	 # Delay slot
68166		 addu  $7,$7,$30
68167		 lw    $7,0x00($7)
68168		 jr    $7
68169		 nop                    	 # Delay slot
68170
68171OP0_4cf8:				#:
68172		 addiu $23,$23,2
68173
68174		 lhu   $12,0x00($23)
68175		 addiu $23,$23,2
68176		 lh    $14,0x00($23)
68177		 addiu $23,$23,2
68178		 ori   $8,$0,1
68179		 or    $9,$0,$21
68180	9:
68181		 and   $10,$12,$8
68182		 beq   $10,$0,8f
68183		 nop                    	 # Delay slot
68184		 lw    $25,0x84($21)
68185		 sw    $15,m68k_ICount
68186		 sw    $8,0x44($29)
68187		 sw    $9,0x40($29)
68188		 sw    $12,0x3C($29)
68189		 sw    $14,0x38($29)
68190		 or    $4,$0,$14
68191		 jalr  $25
68192		 sw    $23,0x4C($21)    	 # Delay slot
68193		 lw    $14,0x38($29)
68194		 lw    $12,0x3C($29)
68195		 lw    $9,0x40($29)
68196		 lw    $8,0x44($29)
68197		 lw    $15,m68k_ICount
68198		 sw    $2,0x00($9)
68199		 addiu $14,$14,4
68200		 addiu $15,$15,-8
68201	8:
68202		 sll   $8,$8,1
68203		 andi  $7,$8,0xffff
68204		 bne   $7,$0,9b
68205		 addiu $9,$9,4          	 # Delay slot
68206		 addiu $15,$15,-24
68207		 bgez  $15,3f
68208		 lhu   $24,0x00($23)    	 # Delay slot
68209		 j     MainExit
68210	3:
68211		 sll   $7,$24,2         	 # Delay slot
68212		 addu  $7,$7,$30
68213		 lw    $7,0x00($7)
68214		 jr    $7
68215		 nop                    	 # Delay slot
68216
68217OP0_4cf9:				#:
68218		 addiu $23,$23,2
68219
68220		 lhu   $12,0x00($23)
68221		 addiu $23,$23,2
68222		 lhu   $14,0x00($23)
68223		 lhu   $25,0x02($23)
68224		 sll   $14,$14,16
68225		 or    $14,$14,$25
68226		 addiu $23,$23,4
68227		 ori   $8,$0,1
68228		 or    $9,$0,$21
68229	9:
68230		 and   $10,$12,$8
68231		 beq   $10,$0,8f
68232		 nop                    	 # Delay slot
68233		 lw    $25,0x84($21)
68234		 sw    $15,m68k_ICount
68235		 sw    $8,0x44($29)
68236		 sw    $9,0x40($29)
68237		 sw    $12,0x3C($29)
68238		 sw    $14,0x38($29)
68239		 or    $4,$0,$14
68240		 jalr  $25
68241		 sw    $23,0x4C($21)    	 # Delay slot
68242		 lw    $14,0x38($29)
68243		 lw    $12,0x3C($29)
68244		 lw    $9,0x40($29)
68245		 lw    $8,0x44($29)
68246		 lw    $15,m68k_ICount
68247		 sw    $2,0x00($9)
68248		 addiu $14,$14,4
68249		 addiu $15,$15,-8
68250	8:
68251		 sll   $8,$8,1
68252		 andi  $7,$8,0xffff
68253		 bne   $7,$0,9b
68254		 addiu $9,$9,4          	 # Delay slot
68255		 addiu $15,$15,-28
68256		 bgez  $15,3f
68257		 lhu   $24,0x00($23)    	 # Delay slot
68258		 j     MainExit
68259	3:
68260		 sll   $7,$24,2         	 # Delay slot
68261		 addu  $7,$7,$30
68262		 lw    $7,0x00($7)
68263		 jr    $7
68264		 nop                    	 # Delay slot
68265
68266OP0_4cfa:				#:
68267		 addiu $23,$23,2
68268
68269		 lhu   $12,0x00($23)
68270		 addiu $23,$23,2
68271		 lh    $7,0x00($23)
68272		 subu  $25,$23,$22
68273		 addu  $14,$25,$7       	 # Add Offset to PC
68274		 addiu $23,$23,2
68275		 ori   $8,$0,1
68276		 or    $9,$0,$21
68277	9:
68278		 and   $10,$12,$8
68279		 beq   $10,$0,8f
68280		 nop                    	 # Delay slot
68281		 lw    $25,0xA0($21)
68282		 sw    $15,m68k_ICount
68283		 sw    $8,0x44($29)
68284		 sw    $9,0x40($29)
68285		 sw    $12,0x3C($29)
68286		 sw    $14,0x38($29)
68287		 or    $4,$0,$14
68288		 jalr  $25
68289		 sw    $23,0x4C($21)    	 # Delay slot
68290		 lw    $14,0x38($29)
68291		 lw    $12,0x3C($29)
68292		 lw    $9,0x40($29)
68293		 lw    $8,0x44($29)
68294		 lw    $15,m68k_ICount
68295		 sw    $2,0x00($9)
68296		 addiu $14,$14,4
68297		 addiu $15,$15,-8
68298	8:
68299		 sll   $8,$8,1
68300		 andi  $7,$8,0xffff
68301		 bne   $7,$0,9b
68302		 addiu $9,$9,4          	 # Delay slot
68303		 addiu $15,$15,-24
68304		 bgez  $15,3f
68305		 lhu   $24,0x00($23)    	 # Delay slot
68306		 j     MainExit
68307	3:
68308		 sll   $7,$24,2         	 # Delay slot
68309		 addu  $7,$7,$30
68310		 lw    $7,0x00($7)
68311		 jr    $7
68312		 nop                    	 # Delay slot
68313
68314OP0_4cfb:				#:
68315		 addiu $23,$23,2
68316
68317		 lhu   $12,0x00($23)
68318		 addiu $23,$23,2
68319		 subu  $14,$23,$22       	 # Get PC
68320		 lhu   $7,0x00($23)
68321		 addiu $23,$23,2
68322		 seb   $6,$7
68323		 or    $25,$0,$7
68324		 srl   $7,$7,12
68325		 andi  $25,$25,0x0800
68326		 sll   $7,$7,2
68327		 addu  $7,$7,$21
68328		 bne   $25,$0,0f
68329		 lw    $25,0x00($7)      	 # Delay slot
68330		 seh   $25,$25
68331	0:
68332		 addu  $25,$14,$25
68333		 addu  $14,$25,$6
68334		 ori   $8,$0,1
68335		 or    $9,$0,$21
68336	9:
68337		 and   $10,$12,$8
68338		 beq   $10,$0,8f
68339		 nop                    	 # Delay slot
68340		 lw    $25,0xA0($21)
68341		 sw    $15,m68k_ICount
68342		 sw    $8,0x44($29)
68343		 sw    $9,0x40($29)
68344		 sw    $12,0x3C($29)
68345		 sw    $14,0x38($29)
68346		 or    $4,$0,$14
68347		 jalr  $25
68348		 sw    $23,0x4C($21)    	 # Delay slot
68349		 lw    $14,0x38($29)
68350		 lw    $12,0x3C($29)
68351		 lw    $9,0x40($29)
68352		 lw    $8,0x44($29)
68353		 lw    $15,m68k_ICount
68354		 sw    $2,0x00($9)
68355		 addiu $14,$14,4
68356		 addiu $15,$15,-8
68357	8:
68358		 sll   $8,$8,1
68359		 andi  $7,$8,0xffff
68360		 bne   $7,$0,9b
68361		 addiu $9,$9,4          	 # Delay slot
68362		 addiu $15,$15,-26
68363		 bgez  $15,3f
68364		 lhu   $24,0x00($23)    	 # Delay slot
68365		 j     MainExit
68366	3:
68367		 sll   $7,$24,2         	 # Delay slot
68368		 addu  $7,$7,$30
68369		 lw    $7,0x00($7)
68370		 jr    $7
68371		 nop                    	 # Delay slot
68372
68373OP0_4e50:				#:
68374		 addiu $23,$23,2
68375
68376		 lw    $14,0x3C($21)
68377		 andi  $24,$24,0x07
68378		 addiu $14,$14,-4
68379		 sll   $24,$24,2
68380		 addu  $24,$24,$21
68381		 lw    $5,0x20($24)
68382		 sw    $14,0x20($24)
68383		 lw    $25,0x90($21)
68384		 sw    $15,m68k_ICount
68385		 sw    $14,0x44($29)
68386		 or    $4,$0,$14
68387		 jalr  $25
68388		 sw    $23,0x4C($21)    	 # Delay slot
68389		 lw    $14,0x44($29)
68390		 lw    $15,m68k_ICount
68391		 lh    $2,0x00($23)
68392		 addiu $23,$23,2
68393		 addu  $14,$14,$2
68394		 sw    $14,0x3C($21)
68395		 addiu $15,$15,-16
68396		 bgez  $15,3f
68397		 lhu   $24,0x00($23)    	 # Delay slot
68398		 j     MainExit
68399	3:
68400		 sll   $7,$24,2         	 # Delay slot
68401		 addu  $7,$7,$30
68402		 lw    $7,0x00($7)
68403		 jr    $7
68404		 nop                    	 # Delay slot
68405
68406OP0_4e58:				#:
68407		 addiu $23,$23,2
68408
68409		 andi  $8,$24,0x07
68410		 sll   $8,$8,2
68411		 addu  $8,$8,$21
68412		 lw    $14,0x20($8)
68413		 lw    $25,0x84($21)
68414		 sw    $15,m68k_ICount
68415		 sw    $8,0x44($29)
68416		 sw    $14,0x40($29)
68417		 or    $4,$0,$14
68418		 jalr  $25
68419		 sw    $23,0x4C($21)    	 # Delay slot
68420		 lw    $14,0x40($29)
68421		 lw    $8,0x44($29)
68422		 lw    $15,m68k_ICount
68423		 sw    $2,0x20($8)
68424		 addiu $14,$14,4
68425		 sw    $14,0x3C($21)
68426		 addiu $15,$15,-12
68427		 bgez  $15,3f
68428		 lhu   $24,0x00($23)    	 # Delay slot
68429		 j     MainExit
68430	3:
68431		 sll   $7,$24,2         	 # Delay slot
68432		 addu  $7,$7,$30
68433		 lw    $7,0x00($7)
68434		 jr    $7
68435		 nop                    	 # Delay slot
68436
68437OP0_e000:				#:
68438		 addiu $23,$23,2
68439
68440		 andi  $8,$24,0x07
68441		 srl   $24,$24,9
68442		 addiu $24,$24,-1       	 # Move range down
68443		 andi  $24,$24,0x07     	 # Mask out lower bits
68444		 addiu $24,$24,1        	 # correct range
68445		 sll   $8,$8,2
68446		 addu  $8,$8,$21
68447		 lb    $2,0x00($8)
68448		 and   $17,$0,$0        	 # Clear Overflow
68449		 beq   $24,$0,9f
68450		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68451		 sll   $25,$24,1
68452		 subu  $15,$15,$25
68453		 addiu $9,$24,-1
68454		 sll   $25,$24,26
68455		 sra   $25,$25,31
68456		 andi  $25,$25,0x1f
68457		 or    $24,$24,$25
68458		 sll   $25,$9,26
68459		 sra   $25,$25,31
68460		 andi  $25,$25,0x1f
68461		 or    $9,$9,$25
68462		 srlv  $16,$2,$9
68463		 andi  $16,$16,0x01     	 # Set Carry
68464		 srav  $2,$2,$24
68465		 sb    $2,0x00($8)
68466		 or    $20,$0,$16       	 # Copy Carry to X
68467	9:
68468		 slt   $19,$2,$0        	 # Set Sign
68469		 sltiu $18,$2,1         	 # Set Zero
68470		 addiu $15,$15,-6
68471		 bgez  $15,3f
68472		 lhu   $24,0x00($23)    	 # Delay slot
68473		 j     MainExit
68474	3:
68475		 sll   $7,$24,2         	 # Delay slot
68476		 addu  $7,$7,$30
68477		 lw    $7,0x00($7)
68478		 jr    $7
68479		 nop                    	 # Delay slot
68480
68481OP0_e020:				#:
68482		 addiu $23,$23,2
68483
68484		 andi  $8,$24,0x07
68485		 srl   $24,$24,7
68486		 andi  $24,$24,0x1C
68487		 addu  $24,$24,$21
68488		 lw    $24,0x00($24)
68489		 andi  $24,$24,0x3F
68490		 sll   $8,$8,2
68491		 addu  $8,$8,$21
68492		 lb    $2,0x00($8)
68493		 and   $17,$0,$0        	 # Clear Overflow
68494		 beq   $24,$0,9f
68495		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68496		 sll   $25,$24,1
68497		 subu  $15,$15,$25
68498		 addiu $9,$24,-1
68499		 sll   $25,$24,26
68500		 sra   $25,$25,31
68501		 andi  $25,$25,0x1f
68502		 or    $24,$24,$25
68503		 sll   $25,$9,26
68504		 sra   $25,$25,31
68505		 andi  $25,$25,0x1f
68506		 or    $9,$9,$25
68507		 srlv  $16,$2,$9
68508		 andi  $16,$16,0x01     	 # Set Carry
68509		 srav  $2,$2,$24
68510		 sb    $2,0x00($8)
68511		 or    $20,$0,$16       	 # Copy Carry to X
68512	9:
68513		 slt   $19,$2,$0        	 # Set Sign
68514		 sltiu $18,$2,1         	 # Set Zero
68515		 addiu $15,$15,-6
68516		 bgez  $15,3f
68517		 lhu   $24,0x00($23)    	 # Delay slot
68518		 j     MainExit
68519	3:
68520		 sll   $7,$24,2         	 # Delay slot
68521		 addu  $7,$7,$30
68522		 lw    $7,0x00($7)
68523		 jr    $7
68524		 nop                    	 # Delay slot
68525
68526OP0_e040:				#:
68527		 addiu $23,$23,2
68528
68529		 andi  $8,$24,0x07
68530		 srl   $24,$24,9
68531		 addiu $24,$24,-1       	 # Move range down
68532		 andi  $24,$24,0x07     	 # Mask out lower bits
68533		 addiu $24,$24,1        	 # correct range
68534		 sll   $8,$8,2
68535		 addu  $8,$8,$21
68536		 lh    $2,0x00($8)
68537		 and   $17,$0,$0        	 # Clear Overflow
68538		 beq   $24,$0,9f
68539		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68540		 sll   $25,$24,1
68541		 subu  $15,$15,$25
68542		 addiu $9,$24,-1
68543		 sll   $25,$24,26
68544		 sra   $25,$25,31
68545		 andi  $25,$25,0x1f
68546		 or    $24,$24,$25
68547		 sll   $25,$9,26
68548		 sra   $25,$25,31
68549		 andi  $25,$25,0x1f
68550		 or    $9,$9,$25
68551		 srlv  $16,$2,$9
68552		 andi  $16,$16,0x01     	 # Set Carry
68553		 srav  $2,$2,$24
68554		 sh    $2,0x00($8)
68555		 or    $20,$0,$16       	 # Copy Carry to X
68556	9:
68557		 slt   $19,$2,$0        	 # Set Sign
68558		 sltiu $18,$2,1         	 # Set Zero
68559		 addiu $15,$15,-6
68560		 bgez  $15,3f
68561		 lhu   $24,0x00($23)    	 # Delay slot
68562		 j     MainExit
68563	3:
68564		 sll   $7,$24,2         	 # Delay slot
68565		 addu  $7,$7,$30
68566		 lw    $7,0x00($7)
68567		 jr    $7
68568		 nop                    	 # Delay slot
68569
68570OP0_e060:				#:
68571		 addiu $23,$23,2
68572
68573		 andi  $8,$24,0x07
68574		 srl   $24,$24,7
68575		 andi  $24,$24,0x1C
68576		 addu  $24,$24,$21
68577		 lw    $24,0x00($24)
68578		 andi  $24,$24,0x3F
68579		 sll   $8,$8,2
68580		 addu  $8,$8,$21
68581		 lh    $2,0x00($8)
68582		 and   $17,$0,$0        	 # Clear Overflow
68583		 beq   $24,$0,9f
68584		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68585		 sll   $25,$24,1
68586		 subu  $15,$15,$25
68587		 addiu $9,$24,-1
68588		 sll   $25,$24,26
68589		 sra   $25,$25,31
68590		 andi  $25,$25,0x1f
68591		 or    $24,$24,$25
68592		 sll   $25,$9,26
68593		 sra   $25,$25,31
68594		 andi  $25,$25,0x1f
68595		 or    $9,$9,$25
68596		 srlv  $16,$2,$9
68597		 andi  $16,$16,0x01     	 # Set Carry
68598		 srav  $2,$2,$24
68599		 sh    $2,0x00($8)
68600		 or    $20,$0,$16       	 # Copy Carry to X
68601	9:
68602		 slt   $19,$2,$0        	 # Set Sign
68603		 sltiu $18,$2,1         	 # Set Zero
68604		 addiu $15,$15,-6
68605		 bgez  $15,3f
68606		 lhu   $24,0x00($23)    	 # Delay slot
68607		 j     MainExit
68608	3:
68609		 sll   $7,$24,2         	 # Delay slot
68610		 addu  $7,$7,$30
68611		 lw    $7,0x00($7)
68612		 jr    $7
68613		 nop                    	 # Delay slot
68614
68615OP0_e080:				#:
68616		 addiu $23,$23,2
68617
68618		 andi  $8,$24,0x07
68619		 srl   $24,$24,9
68620		 addiu $24,$24,-1       	 # Move range down
68621		 andi  $24,$24,0x07     	 # Mask out lower bits
68622		 addiu $24,$24,1        	 # correct range
68623		 sll   $8,$8,2
68624		 addu  $8,$8,$21
68625		 lw    $2,0x00($8)
68626		 and   $17,$0,$0        	 # Clear Overflow
68627		 beq   $24,$0,9f
68628		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68629		 sll   $25,$24,1
68630		 subu  $15,$15,$25
68631		 addiu $9,$24,-1
68632		 sll   $25,$24,26
68633		 sra   $25,$25,31
68634		 andi  $25,$25,0x1f
68635		 or    $24,$24,$25
68636		 sll   $25,$9,26
68637		 sra   $25,$25,31
68638		 andi  $25,$25,0x1f
68639		 or    $9,$9,$25
68640		 srlv  $16,$2,$9
68641		 andi  $16,$16,0x01     	 # Set Carry
68642		 srav  $2,$2,$24
68643		 sw    $2,0x00($8)
68644		 or    $20,$0,$16       	 # Copy Carry to X
68645	9:
68646		 slt   $19,$2,$0        	 # Set Sign
68647		 sltiu $18,$2,1         	 # Set Zero
68648		 addiu $15,$15,-8
68649		 bgez  $15,3f
68650		 lhu   $24,0x00($23)    	 # Delay slot
68651		 j     MainExit
68652	3:
68653		 sll   $7,$24,2         	 # Delay slot
68654		 addu  $7,$7,$30
68655		 lw    $7,0x00($7)
68656		 jr    $7
68657		 nop                    	 # Delay slot
68658
68659OP0_e0a0:				#:
68660		 addiu $23,$23,2
68661
68662		 andi  $8,$24,0x07
68663		 srl   $24,$24,7
68664		 andi  $24,$24,0x1C
68665		 addu  $24,$24,$21
68666		 lw    $24,0x00($24)
68667		 andi  $24,$24,0x3F
68668		 sll   $8,$8,2
68669		 addu  $8,$8,$21
68670		 lw    $2,0x00($8)
68671		 and   $17,$0,$0        	 # Clear Overflow
68672		 beq   $24,$0,9f
68673		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68674		 sll   $25,$24,1
68675		 subu  $15,$15,$25
68676		 addiu $9,$24,-1
68677		 sll   $25,$24,26
68678		 sra   $25,$25,31
68679		 andi  $25,$25,0x1f
68680		 or    $24,$24,$25
68681		 sll   $25,$9,26
68682		 sra   $25,$25,31
68683		 andi  $25,$25,0x1f
68684		 or    $9,$9,$25
68685		 srlv  $16,$2,$9
68686		 andi  $16,$16,0x01     	 # Set Carry
68687		 srav  $2,$2,$24
68688		 sw    $2,0x00($8)
68689		 or    $20,$0,$16       	 # Copy Carry to X
68690	9:
68691		 slt   $19,$2,$0        	 # Set Sign
68692		 sltiu $18,$2,1         	 # Set Zero
68693		 addiu $15,$15,-8
68694		 bgez  $15,3f
68695		 lhu   $24,0x00($23)    	 # Delay slot
68696		 j     MainExit
68697	3:
68698		 sll   $7,$24,2         	 # Delay slot
68699		 addu  $7,$7,$30
68700		 lw    $7,0x00($7)
68701		 jr    $7
68702		 nop                    	 # Delay slot
68703
68704OP0_e100:				#:
68705		 addiu $23,$23,2
68706
68707		 andi  $8,$24,0x07
68708		 srl   $24,$24,9
68709		 addiu $24,$24,-1       	 # Move range down
68710		 andi  $24,$24,0x07     	 # Mask out lower bits
68711		 addiu $24,$24,1        	 # correct range
68712		 sll   $8,$8,2
68713		 addu  $8,$8,$21
68714		 lb    $2,0x00($8)
68715		 and   $17,$0,$0        	 # Clear Overflow
68716		 beq   $24,$0,9f
68717		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68718		 sll   $25,$24,1
68719		 subu  $15,$15,$25
68720		 sll   $25,$24,26
68721		 sra   $25,$25,31
68722		 andi  $25,$25,0x1f
68723		 or    $25,$24,$25
68724		 clz   $9,$2
68725		 clo   $10,$2
68726		 addiu $9,$9,-24
68727		 addiu $10,$10,-24
68728		 sltu  $9,$9,$25
68729		 sltu  $10,$10,$25
68730		 or    $17,$9,$10        	 # Set Overflow
68731		 subu  $9,$0,$24
68732		 andi  $9,$9,0x07
68733		 srlv   $16,$2,$9
68734		 andi  $16,$16,0x01     	 # Set Carry
68735		 sllv   $2,$2,$24
68736		 sb    $2,0x00($8)
68737		 or    $20,$0,$16       	 # Copy Carry to X
68738	9:
68739		 slt   $19,$2,$0        	 # Set Sign
68740		 sltiu $18,$2,1         	 # Set Zero
68741		 addiu $15,$15,-6
68742		 bgez  $15,3f
68743		 lhu   $24,0x00($23)    	 # Delay slot
68744		 j     MainExit
68745	3:
68746		 sll   $7,$24,2         	 # Delay slot
68747		 addu  $7,$7,$30
68748		 lw    $7,0x00($7)
68749		 jr    $7
68750		 nop                    	 # Delay slot
68751
68752OP0_e120:				#:
68753		 addiu $23,$23,2
68754
68755		 andi  $8,$24,0x07
68756		 srl   $24,$24,7
68757		 andi  $24,$24,0x1C
68758		 addu  $24,$24,$21
68759		 lw    $24,0x00($24)
68760		 andi  $24,$24,0x3F
68761		 sll   $8,$8,2
68762		 addu  $8,$8,$21
68763		 lb    $2,0x00($8)
68764		 and   $17,$0,$0        	 # Clear Overflow
68765		 beq   $24,$0,9f
68766		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68767		 sll   $25,$24,1
68768		 subu  $15,$15,$25
68769		 sll   $25,$24,26
68770		 sra   $25,$25,31
68771		 andi  $25,$25,0x1f
68772		 or    $25,$24,$25
68773		 clz   $9,$2
68774		 clo   $10,$2
68775		 addiu $9,$9,-24
68776		 addiu $10,$10,-24
68777		 sltu  $9,$9,$25
68778		 sltu  $10,$10,$25
68779		 or    $17,$9,$10        	 # Set Overflow
68780		 subu  $9,$0,$24
68781		 andi  $9,$9,0x07
68782		 srlv   $16,$2,$9
68783		 andi  $16,$16,0x01     	 # Set Carry
68784		 sllv   $2,$2,$24
68785		 sb    $2,0x00($8)
68786		 or    $20,$0,$16       	 # Copy Carry to X
68787	9:
68788		 slt   $19,$2,$0        	 # Set Sign
68789		 sltiu $18,$2,1         	 # Set Zero
68790		 addiu $15,$15,-6
68791		 bgez  $15,3f
68792		 lhu   $24,0x00($23)    	 # Delay slot
68793		 j     MainExit
68794	3:
68795		 sll   $7,$24,2         	 # Delay slot
68796		 addu  $7,$7,$30
68797		 lw    $7,0x00($7)
68798		 jr    $7
68799		 nop                    	 # Delay slot
68800
68801OP0_e140:				#:
68802		 addiu $23,$23,2
68803
68804		 andi  $8,$24,0x07
68805		 srl   $24,$24,9
68806		 addiu $24,$24,-1       	 # Move range down
68807		 andi  $24,$24,0x07     	 # Mask out lower bits
68808		 addiu $24,$24,1        	 # correct range
68809		 sll   $8,$8,2
68810		 addu  $8,$8,$21
68811		 lh    $2,0x00($8)
68812		 and   $17,$0,$0        	 # Clear Overflow
68813		 beq   $24,$0,9f
68814		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68815		 sll   $25,$24,1
68816		 subu  $15,$15,$25
68817		 sll   $25,$24,26
68818		 sra   $25,$25,31
68819		 andi  $25,$25,0x1f
68820		 or    $25,$24,$25
68821		 clz   $9,$2
68822		 clo   $10,$2
68823		 addiu $9,$9,-16
68824		 addiu $10,$10,-16
68825		 sltu  $9,$9,$25
68826		 sltu  $10,$10,$25
68827		 or    $17,$9,$10        	 # Set Overflow
68828		 subu  $9,$0,$24
68829		 andi  $9,$9,0x0F
68830		 srlv   $16,$2,$9
68831		 andi  $16,$16,0x01     	 # Set Carry
68832		 sllv   $2,$2,$24
68833		 sh    $2,0x00($8)
68834		 or    $20,$0,$16       	 # Copy Carry to X
68835	9:
68836		 slt   $19,$2,$0        	 # Set Sign
68837		 sltiu $18,$2,1         	 # Set Zero
68838		 addiu $15,$15,-6
68839		 bgez  $15,3f
68840		 lhu   $24,0x00($23)    	 # Delay slot
68841		 j     MainExit
68842	3:
68843		 sll   $7,$24,2         	 # Delay slot
68844		 addu  $7,$7,$30
68845		 lw    $7,0x00($7)
68846		 jr    $7
68847		 nop                    	 # Delay slot
68848
68849OP0_e160:				#:
68850		 addiu $23,$23,2
68851
68852		 andi  $8,$24,0x07
68853		 srl   $24,$24,7
68854		 andi  $24,$24,0x1C
68855		 addu  $24,$24,$21
68856		 lw    $24,0x00($24)
68857		 andi  $24,$24,0x3F
68858		 sll   $8,$8,2
68859		 addu  $8,$8,$21
68860		 lh    $2,0x00($8)
68861		 and   $17,$0,$0        	 # Clear Overflow
68862		 beq   $24,$0,9f
68863		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68864		 sll   $25,$24,1
68865		 subu  $15,$15,$25
68866		 sll   $25,$24,26
68867		 sra   $25,$25,31
68868		 andi  $25,$25,0x1f
68869		 or    $25,$24,$25
68870		 clz   $9,$2
68871		 clo   $10,$2
68872		 addiu $9,$9,-16
68873		 addiu $10,$10,-16
68874		 sltu  $9,$9,$25
68875		 sltu  $10,$10,$25
68876		 or    $17,$9,$10        	 # Set Overflow
68877		 subu  $9,$0,$24
68878		 andi  $9,$9,0x0F
68879		 srlv   $16,$2,$9
68880		 andi  $16,$16,0x01     	 # Set Carry
68881		 sllv   $2,$2,$24
68882		 sh    $2,0x00($8)
68883		 or    $20,$0,$16       	 # Copy Carry to X
68884	9:
68885		 slt   $19,$2,$0        	 # Set Sign
68886		 sltiu $18,$2,1         	 # Set Zero
68887		 addiu $15,$15,-6
68888		 bgez  $15,3f
68889		 lhu   $24,0x00($23)    	 # Delay slot
68890		 j     MainExit
68891	3:
68892		 sll   $7,$24,2         	 # Delay slot
68893		 addu  $7,$7,$30
68894		 lw    $7,0x00($7)
68895		 jr    $7
68896		 nop                    	 # Delay slot
68897
68898OP0_e180:				#:
68899		 addiu $23,$23,2
68900
68901		 andi  $8,$24,0x07
68902		 srl   $24,$24,9
68903		 addiu $24,$24,-1       	 # Move range down
68904		 andi  $24,$24,0x07     	 # Mask out lower bits
68905		 addiu $24,$24,1        	 # correct range
68906		 sll   $8,$8,2
68907		 addu  $8,$8,$21
68908		 lw    $2,0x00($8)
68909		 and   $17,$0,$0        	 # Clear Overflow
68910		 beq   $24,$0,9f
68911		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68912		 sll   $25,$24,1
68913		 subu  $15,$15,$25
68914		 sll   $25,$24,26
68915		 sra   $25,$25,31
68916		 andi  $25,$25,0x1f
68917		 or    $25,$24,$25
68918		 clz   $9,$2
68919		 clo   $10,$2
68920		 sltu  $9,$9,$25
68921		 sltu  $10,$10,$25
68922		 or    $17,$9,$10        	 # Set Overflow
68923		 subu  $9,$0,$24
68924		 srlv   $16,$2,$9
68925		 andi  $16,$16,0x01     	 # Set Carry
68926		 sllv   $2,$2,$24
68927		 sw    $2,0x00($8)
68928		 or    $20,$0,$16       	 # Copy Carry to X
68929	9:
68930		 slt   $19,$2,$0        	 # Set Sign
68931		 sltiu $18,$2,1         	 # Set Zero
68932		 addiu $15,$15,-8
68933		 bgez  $15,3f
68934		 lhu   $24,0x00($23)    	 # Delay slot
68935		 j     MainExit
68936	3:
68937		 sll   $7,$24,2         	 # Delay slot
68938		 addu  $7,$7,$30
68939		 lw    $7,0x00($7)
68940		 jr    $7
68941		 nop                    	 # Delay slot
68942
68943OP0_e1a0:				#:
68944		 addiu $23,$23,2
68945
68946		 andi  $8,$24,0x07
68947		 srl   $24,$24,7
68948		 andi  $24,$24,0x1C
68949		 addu  $24,$24,$21
68950		 lw    $24,0x00($24)
68951		 andi  $24,$24,0x3F
68952		 sll   $8,$8,2
68953		 addu  $8,$8,$21
68954		 lw    $2,0x00($8)
68955		 and   $17,$0,$0        	 # Clear Overflow
68956		 beq   $24,$0,9f
68957		 and   $16,$0,$0        	 # Delay slot - Clear Carry
68958		 sll   $25,$24,1
68959		 subu  $15,$15,$25
68960		 sll   $25,$24,26
68961		 sra   $25,$25,31
68962		 andi  $25,$25,0x1f
68963		 or    $25,$24,$25
68964		 clz   $9,$2
68965		 clo   $10,$2
68966		 sltu  $9,$9,$25
68967		 sltu  $10,$10,$25
68968		 or    $17,$9,$10        	 # Set Overflow
68969		 andi  $9,$24,0x20
68970		 movn  $2,$0,$9
68971		 subu  $9,$0,$24
68972		 srlv   $16,$2,$9
68973		 andi  $16,$16,0x01     	 # Set Carry
68974		 sllv   $2,$2,$24
68975		 sw    $2,0x00($8)
68976		 or    $20,$0,$16       	 # Copy Carry to X
68977	9:
68978		 slt   $19,$2,$0        	 # Set Sign
68979		 sltiu $18,$2,1         	 # Set Zero
68980		 addiu $15,$15,-8
68981		 bgez  $15,3f
68982		 lhu   $24,0x00($23)    	 # Delay slot
68983		 j     MainExit
68984	3:
68985		 sll   $7,$24,2         	 # Delay slot
68986		 addu  $7,$7,$30
68987		 lw    $7,0x00($7)
68988		 jr    $7
68989		 nop                    	 # Delay slot
68990
68991OP0_e300:				#:
68992		 andi  $24,$24,0x07
68993		 sll   $24,$24,2
68994		 addu  $24,$24,$21
68995		 lbu   $3,0x00($24)
68996
68997		 addiu $23,$23,2
68998
68999		 sll   $2,$3,1
69000		 sb    $2,0x00($24)
69001		 srl   $16,$3,7        	 # Set Carry
69002		 xor   $17,$2,$3
69003		 srl   $17,$17,7
69004		 andi  $17,$17,0x01     	 # Set Overflow
69005		 andi  $18,$2,0xFF
69006		 sltiu $18,$18,1        	 # Set Zero
69007		 srl   $19,$2,7        	 # Set Sign
69008		 or    $20,$0,$16       	 # Copy Carry to X
69009		 addiu $15,$15,-6
69010		 bgez  $15,3f
69011		 lhu   $24,0x00($23)    	 # Delay slot
69012		 j     MainExit
69013	3:
69014		 sll   $7,$24,2         	 # Delay slot
69015		 addu  $7,$7,$30
69016		 lw    $7,0x00($7)
69017		 jr    $7
69018		 nop                    	 # Delay slot
69019
69020OP0_e340:				#:
69021		 andi  $24,$24,0x07
69022		 sll   $24,$24,2
69023		 addu  $24,$24,$21
69024		 lhu   $3,0x00($24)
69025
69026		 addiu $23,$23,2
69027
69028		 sll   $2,$3,1
69029		 sh    $2,0x00($24)
69030		 srl   $16,$3,15        	 # Set Carry
69031		 xor   $17,$2,$3
69032		 srl   $17,$17,15
69033		 andi  $17,$17,0x01     	 # Set Overflow
69034		 andi  $18,$2,0xFFFF
69035		 sltiu $18,$18,1        	 # Set Zero
69036		 srl   $19,$2,15        	 # Set Sign
69037		 or    $20,$0,$16       	 # Copy Carry to X
69038		 addiu $15,$15,-6
69039		 bgez  $15,3f
69040		 lhu   $24,0x00($23)    	 # Delay slot
69041		 j     MainExit
69042	3:
69043		 sll   $7,$24,2         	 # Delay slot
69044		 addu  $7,$7,$30
69045		 lw    $7,0x00($7)
69046		 jr    $7
69047		 nop                    	 # Delay slot
69048
69049OP0_e380:				#:
69050		 andi  $24,$24,0x07
69051		 sll   $24,$24,2
69052		 addu  $24,$24,$21
69053		 lw    $3,0x00($24)
69054
69055		 addiu $23,$23,2
69056
69057		 sll   $2,$3,1
69058		 sw    $2,0x00($24)
69059		 srl   $16,$3,31        	 # Set Carry
69060		 xor   $17,$2,$3
69061		 srl   $17,$17,31       	 # Set Overflow
69062		 or    $18,$0,$2
69063		 sltiu $18,$18,1        	 # Set Zero
69064		 srl   $19,$2,31        	 # Set Sign
69065		 or    $20,$0,$16       	 # Copy Carry to X
69066		 addiu $15,$15,-8
69067		 bgez  $15,3f
69068		 lhu   $24,0x00($23)    	 # Delay slot
69069		 j     MainExit
69070	3:
69071		 sll   $7,$24,2         	 # Delay slot
69072		 addu  $7,$7,$30
69073		 lw    $7,0x00($7)
69074		 jr    $7
69075		 nop                    	 # Delay slot
69076
69077OP0_e0d0:				#:
69078
69079		 addiu $23,$23,2
69080
69081		 andi  $24,$24,0x07
69082		 sll   $24,$24,2
69083		 addu  $24,$24,$21
69084		 lw    $14,0x20($24)
69085		 lw    $25,0x80($21)
69086		 sw    $15,m68k_ICount
69087		 sw    $14,0x44($29)
69088		 or    $4,$0,$14
69089		 jalr  $25
69090		 sw    $23,0x4C($21)    	 # Delay slot
69091		 lw    $14,0x44($29)
69092		 lw    $15,m68k_ICount
69093		 seh   $2,$2
69094		 andi  $16,$2,0x01      	 # Set Carry
69095		 and   $17,$0,$0        	 # Clear Overflow
69096		 sra   $2,$2,1
69097		 slt   $19,$2,$0        	 # Set Sign
69098		 sltiu $18,$2,1        	 # Set Zero
69099		 or    $20,$0,$16       	 # Copy Carry to X
69100		 lw    $25,0x8C($21)
69101		 sw    $15,m68k_ICount
69102		 or    $5,$0,$2
69103		 or    $4,$0,$14
69104		 jalr  $25
69105		 sw    $23,0x4C($21)    	 # Delay slot
69106		 lw    $15,m68k_ICount
69107		 addiu $15,$15,-12
69108		 bgez  $15,3f
69109		 lhu   $24,0x00($23)    	 # Delay slot
69110		 j     MainExit
69111	3:
69112		 sll   $7,$24,2         	 # Delay slot
69113		 addu  $7,$7,$30
69114		 lw    $7,0x00($7)
69115		 jr    $7
69116		 nop                    	 # Delay slot
69117
69118OP0_e0d8:				#:
69119
69120		 addiu $23,$23,2
69121
69122		 andi  $24,$24,0x07
69123		 sll   $24,$24,2
69124		 addu  $24,$24,$21
69125		 lw    $14,0x20($24)
69126		 addiu $25,$14,2
69127		 sw    $25,0x20($24)
69128		 lw    $25,0x80($21)
69129		 sw    $15,m68k_ICount
69130		 sw    $14,0x44($29)
69131		 or    $4,$0,$14
69132		 jalr  $25
69133		 sw    $23,0x4C($21)    	 # Delay slot
69134		 lw    $14,0x44($29)
69135		 lw    $15,m68k_ICount
69136		 seh   $2,$2
69137		 andi  $16,$2,0x01      	 # Set Carry
69138		 and   $17,$0,$0        	 # Clear Overflow
69139		 sra   $2,$2,1
69140		 slt   $19,$2,$0        	 # Set Sign
69141		 sltiu $18,$2,1        	 # Set Zero
69142		 or    $20,$0,$16       	 # Copy Carry to X
69143		 lw    $25,0x8C($21)
69144		 sw    $15,m68k_ICount
69145		 or    $5,$0,$2
69146		 or    $4,$0,$14
69147		 jalr  $25
69148		 sw    $23,0x4C($21)    	 # Delay slot
69149		 lw    $15,m68k_ICount
69150		 addiu $15,$15,-12
69151		 bgez  $15,3f
69152		 lhu   $24,0x00($23)    	 # Delay slot
69153		 j     MainExit
69154	3:
69155		 sll   $7,$24,2         	 # Delay slot
69156		 addu  $7,$7,$30
69157		 lw    $7,0x00($7)
69158		 jr    $7
69159		 nop                    	 # Delay slot
69160
69161OP0_e0e0:				#:
69162
69163		 addiu $23,$23,2
69164
69165		 andi  $24,$24,0x07
69166		 sll   $24,$24,2
69167		 addu  $24,$24,$21
69168		 lw    $14,0x20($24)
69169		 addiu $14,$14,-2
69170		 sw    $14,0x20($24)
69171		 lw    $25,0x80($21)
69172		 sw    $15,m68k_ICount
69173		 sw    $14,0x44($29)
69174		 or    $4,$0,$14
69175		 jalr  $25
69176		 sw    $23,0x4C($21)    	 # Delay slot
69177		 lw    $14,0x44($29)
69178		 lw    $15,m68k_ICount
69179		 seh   $2,$2
69180		 andi  $16,$2,0x01      	 # Set Carry
69181		 and   $17,$0,$0        	 # Clear Overflow
69182		 sra   $2,$2,1
69183		 slt   $19,$2,$0        	 # Set Sign
69184		 sltiu $18,$2,1        	 # Set Zero
69185		 or    $20,$0,$16       	 # Copy Carry to X
69186		 lw    $25,0x8C($21)
69187		 sw    $15,m68k_ICount
69188		 or    $5,$0,$2
69189		 or    $4,$0,$14
69190		 jalr  $25
69191		 sw    $23,0x4C($21)    	 # Delay slot
69192		 lw    $15,m68k_ICount
69193		 addiu $15,$15,-14
69194		 bgez  $15,3f
69195		 lhu   $24,0x00($23)    	 # Delay slot
69196		 j     MainExit
69197	3:
69198		 sll   $7,$24,2         	 # Delay slot
69199		 addu  $7,$7,$30
69200		 lw    $7,0x00($7)
69201		 jr    $7
69202		 nop                    	 # Delay slot
69203
69204OP0_e0e8:				#:
69205
69206		 addiu $23,$23,2
69207
69208		 andi  $24,$24,0x07
69209		 lh    $7,0x00($23)
69210		 sll   $24,$24,2
69211		 addu  $24,$24,$21
69212		 lw    $14,0x20($24)
69213		 addiu $23,$23,2
69214		 addu  $14,$14,$7
69215		 lw    $25,0x80($21)
69216		 sw    $15,m68k_ICount
69217		 sw    $14,0x44($29)
69218		 or    $4,$0,$14
69219		 jalr  $25
69220		 sw    $23,0x4C($21)    	 # Delay slot
69221		 lw    $14,0x44($29)
69222		 lw    $15,m68k_ICount
69223		 seh   $2,$2
69224		 andi  $16,$2,0x01      	 # Set Carry
69225		 and   $17,$0,$0        	 # Clear Overflow
69226		 sra   $2,$2,1
69227		 slt   $19,$2,$0        	 # Set Sign
69228		 sltiu $18,$2,1        	 # Set Zero
69229		 or    $20,$0,$16       	 # Copy Carry to X
69230		 lw    $25,0x8C($21)
69231		 sw    $15,m68k_ICount
69232		 or    $5,$0,$2
69233		 or    $4,$0,$14
69234		 jalr  $25
69235		 sw    $23,0x4C($21)    	 # Delay slot
69236		 lw    $15,m68k_ICount
69237		 addiu $15,$15,-16
69238		 bgez  $15,3f
69239		 lhu   $24,0x00($23)    	 # Delay slot
69240		 j     MainExit
69241	3:
69242		 sll   $7,$24,2         	 # Delay slot
69243		 addu  $7,$7,$30
69244		 lw    $7,0x00($7)
69245		 jr    $7
69246		 nop                    	 # Delay slot
69247
69248OP0_e0f0:				#:
69249
69250		 addiu $23,$23,2
69251
69252		 andi  $24,$24,0x07
69253		 sll   $24,$24,2
69254		 addu  $24,$24,$21
69255		 lw    $14,0x20($24)
69256		 lhu   $7,0x00($23)
69257		 addiu $23,$23,2
69258		 seb   $6,$7
69259		 or    $25,$0,$7
69260		 srl   $7,$7,12
69261		 andi  $25,$25,0x0800
69262		 sll   $7,$7,2
69263		 addu  $7,$7,$21
69264		 bne   $25,$0,0f
69265		 lw    $25,0x00($7)      	 # Delay slot
69266		 seh   $25,$25
69267	0:
69268		 addu  $25,$14,$25
69269		 addu  $14,$25,$6
69270		 lw    $25,0x80($21)
69271		 sw    $15,m68k_ICount
69272		 sw    $14,0x44($29)
69273		 or    $4,$0,$14
69274		 jalr  $25
69275		 sw    $23,0x4C($21)    	 # Delay slot
69276		 lw    $14,0x44($29)
69277		 lw    $15,m68k_ICount
69278		 seh   $2,$2
69279		 andi  $16,$2,0x01      	 # Set Carry
69280		 and   $17,$0,$0        	 # Clear Overflow
69281		 sra   $2,$2,1
69282		 slt   $19,$2,$0        	 # Set Sign
69283		 sltiu $18,$2,1        	 # Set Zero
69284		 or    $20,$0,$16       	 # Copy Carry to X
69285		 lw    $25,0x8C($21)
69286		 sw    $15,m68k_ICount
69287		 or    $5,$0,$2
69288		 or    $4,$0,$14
69289		 jalr  $25
69290		 sw    $23,0x4C($21)    	 # Delay slot
69291		 lw    $15,m68k_ICount
69292		 addiu $15,$15,-18
69293		 bgez  $15,3f
69294		 lhu   $24,0x00($23)    	 # Delay slot
69295		 j     MainExit
69296	3:
69297		 sll   $7,$24,2         	 # Delay slot
69298		 addu  $7,$7,$30
69299		 lw    $7,0x00($7)
69300		 jr    $7
69301		 nop                    	 # Delay slot
69302
69303OP0_e0f8:				#:
69304
69305		 addiu $23,$23,2
69306
69307		 lh    $14,0x00($23)
69308		 addiu $23,$23,2
69309		 lw    $25,0x80($21)
69310		 sw    $15,m68k_ICount
69311		 sw    $14,0x44($29)
69312		 or    $4,$0,$14
69313		 jalr  $25
69314		 sw    $23,0x4C($21)    	 # Delay slot
69315		 lw    $14,0x44($29)
69316		 lw    $15,m68k_ICount
69317		 seh   $2,$2
69318		 andi  $16,$2,0x01      	 # Set Carry
69319		 and   $17,$0,$0        	 # Clear Overflow
69320		 sra   $2,$2,1
69321		 slt   $19,$2,$0        	 # Set Sign
69322		 sltiu $18,$2,1        	 # Set Zero
69323		 or    $20,$0,$16       	 # Copy Carry to X
69324		 lw    $25,0x8C($21)
69325		 sw    $15,m68k_ICount
69326		 or    $5,$0,$2
69327		 or    $4,$0,$14
69328		 jalr  $25
69329		 sw    $23,0x4C($21)    	 # Delay slot
69330		 lw    $15,m68k_ICount
69331		 addiu $15,$15,-16
69332		 bgez  $15,3f
69333		 lhu   $24,0x00($23)    	 # Delay slot
69334		 j     MainExit
69335	3:
69336		 sll   $7,$24,2         	 # Delay slot
69337		 addu  $7,$7,$30
69338		 lw    $7,0x00($7)
69339		 jr    $7
69340		 nop                    	 # Delay slot
69341
69342OP0_e0f9:				#:
69343
69344		 addiu $23,$23,2
69345
69346		 lhu   $14,0x00($23)
69347		 lhu   $25,0x02($23)
69348		 sll   $14,$14,16
69349		 or    $14,$14,$25
69350		 addiu $23,$23,4
69351		 lw    $25,0x80($21)
69352		 sw    $15,m68k_ICount
69353		 sw    $14,0x44($29)
69354		 or    $4,$0,$14
69355		 jalr  $25
69356		 sw    $23,0x4C($21)    	 # Delay slot
69357		 lw    $14,0x44($29)
69358		 lw    $15,m68k_ICount
69359		 seh   $2,$2
69360		 andi  $16,$2,0x01      	 # Set Carry
69361		 and   $17,$0,$0        	 # Clear Overflow
69362		 sra   $2,$2,1
69363		 slt   $19,$2,$0        	 # Set Sign
69364		 sltiu $18,$2,1        	 # Set Zero
69365		 or    $20,$0,$16       	 # Copy Carry to X
69366		 lw    $25,0x8C($21)
69367		 sw    $15,m68k_ICount
69368		 or    $5,$0,$2
69369		 or    $4,$0,$14
69370		 jalr  $25
69371		 sw    $23,0x4C($21)    	 # Delay slot
69372		 lw    $15,m68k_ICount
69373		 addiu $15,$15,-20
69374		 bgez  $15,3f
69375		 lhu   $24,0x00($23)    	 # Delay slot
69376		 j     MainExit
69377	3:
69378		 sll   $7,$24,2         	 # Delay slot
69379		 addu  $7,$7,$30
69380		 lw    $7,0x00($7)
69381		 jr    $7
69382		 nop                    	 # Delay slot
69383
69384OP0_e1d0:				#:
69385
69386		 addiu $23,$23,2
69387
69388		 andi  $24,$24,0x07
69389		 sll   $24,$24,2
69390		 addu  $24,$24,$21
69391		 lw    $14,0x20($24)
69392		 lw    $25,0x80($21)
69393		 sw    $15,m68k_ICount
69394		 sw    $14,0x44($29)
69395		 or    $4,$0,$14
69396		 jalr  $25
69397		 sw    $23,0x4C($21)    	 # Delay slot
69398		 lw    $14,0x44($29)
69399		 lw    $15,m68k_ICount
69400		 or    $3,$0,$2
69401		 sll   $2,$3,1
69402		 srl   $16,$3,15        	 # Set Carry
69403		 xor   $17,$2,$3
69404		 srl   $17,$17,15
69405		 andi  $17,$17,0x01     	 # Set Overflow
69406		 andi  $2,$2,0xffff
69407		 srl   $19,$2,15        	 # Set Sign
69408		 sltiu $18,$2,1        	 # Set Zero
69409		 or    $20,$0,$16       	 # Copy Carry to X
69410		 lw    $25,0x8C($21)
69411		 sw    $15,m68k_ICount
69412		 or    $5,$0,$2
69413		 or    $4,$0,$14
69414		 jalr  $25
69415		 sw    $23,0x4C($21)    	 # Delay slot
69416		 lw    $15,m68k_ICount
69417		 addiu $15,$15,-12
69418		 bgez  $15,3f
69419		 lhu   $24,0x00($23)    	 # Delay slot
69420		 j     MainExit
69421	3:
69422		 sll   $7,$24,2         	 # Delay slot
69423		 addu  $7,$7,$30
69424		 lw    $7,0x00($7)
69425		 jr    $7
69426		 nop                    	 # Delay slot
69427
69428OP0_e1d8:				#:
69429
69430		 addiu $23,$23,2
69431
69432		 andi  $24,$24,0x07
69433		 sll   $24,$24,2
69434		 addu  $24,$24,$21
69435		 lw    $14,0x20($24)
69436		 addiu $25,$14,2
69437		 sw    $25,0x20($24)
69438		 lw    $25,0x80($21)
69439		 sw    $15,m68k_ICount
69440		 sw    $14,0x44($29)
69441		 or    $4,$0,$14
69442		 jalr  $25
69443		 sw    $23,0x4C($21)    	 # Delay slot
69444		 lw    $14,0x44($29)
69445		 lw    $15,m68k_ICount
69446		 or    $3,$0,$2
69447		 sll   $2,$3,1
69448		 srl   $16,$3,15        	 # Set Carry
69449		 xor   $17,$2,$3
69450		 srl   $17,$17,15
69451		 andi  $17,$17,0x01     	 # Set Overflow
69452		 andi  $2,$2,0xffff
69453		 srl   $19,$2,15        	 # Set Sign
69454		 sltiu $18,$2,1        	 # Set Zero
69455		 or    $20,$0,$16       	 # Copy Carry to X
69456		 lw    $25,0x8C($21)
69457		 sw    $15,m68k_ICount
69458		 or    $5,$0,$2
69459		 or    $4,$0,$14
69460		 jalr  $25
69461		 sw    $23,0x4C($21)    	 # Delay slot
69462		 lw    $15,m68k_ICount
69463		 addiu $15,$15,-12
69464		 bgez  $15,3f
69465		 lhu   $24,0x00($23)    	 # Delay slot
69466		 j     MainExit
69467	3:
69468		 sll   $7,$24,2         	 # Delay slot
69469		 addu  $7,$7,$30
69470		 lw    $7,0x00($7)
69471		 jr    $7
69472		 nop                    	 # Delay slot
69473
69474OP0_e1e0:				#:
69475
69476		 addiu $23,$23,2
69477
69478		 andi  $24,$24,0x07
69479		 sll   $24,$24,2
69480		 addu  $24,$24,$21
69481		 lw    $14,0x20($24)
69482		 addiu $14,$14,-2
69483		 sw    $14,0x20($24)
69484		 lw    $25,0x80($21)
69485		 sw    $15,m68k_ICount
69486		 sw    $14,0x44($29)
69487		 or    $4,$0,$14
69488		 jalr  $25
69489		 sw    $23,0x4C($21)    	 # Delay slot
69490		 lw    $14,0x44($29)
69491		 lw    $15,m68k_ICount
69492		 or    $3,$0,$2
69493		 sll   $2,$3,1
69494		 srl   $16,$3,15        	 # Set Carry
69495		 xor   $17,$2,$3
69496		 srl   $17,$17,15
69497		 andi  $17,$17,0x01     	 # Set Overflow
69498		 andi  $2,$2,0xffff
69499		 srl   $19,$2,15        	 # Set Sign
69500		 sltiu $18,$2,1        	 # Set Zero
69501		 or    $20,$0,$16       	 # Copy Carry to X
69502		 lw    $25,0x8C($21)
69503		 sw    $15,m68k_ICount
69504		 or    $5,$0,$2
69505		 or    $4,$0,$14
69506		 jalr  $25
69507		 sw    $23,0x4C($21)    	 # Delay slot
69508		 lw    $15,m68k_ICount
69509		 addiu $15,$15,-14
69510		 bgez  $15,3f
69511		 lhu   $24,0x00($23)    	 # Delay slot
69512		 j     MainExit
69513	3:
69514		 sll   $7,$24,2         	 # Delay slot
69515		 addu  $7,$7,$30
69516		 lw    $7,0x00($7)
69517		 jr    $7
69518		 nop                    	 # Delay slot
69519
69520OP0_e1e8:				#:
69521
69522		 addiu $23,$23,2
69523
69524		 andi  $24,$24,0x07
69525		 lh    $7,0x00($23)
69526		 sll   $24,$24,2
69527		 addu  $24,$24,$21
69528		 lw    $14,0x20($24)
69529		 addiu $23,$23,2
69530		 addu  $14,$14,$7
69531		 lw    $25,0x80($21)
69532		 sw    $15,m68k_ICount
69533		 sw    $14,0x44($29)
69534		 or    $4,$0,$14
69535		 jalr  $25
69536		 sw    $23,0x4C($21)    	 # Delay slot
69537		 lw    $14,0x44($29)
69538		 lw    $15,m68k_ICount
69539		 or    $3,$0,$2
69540		 sll   $2,$3,1
69541		 srl   $16,$3,15        	 # Set Carry
69542		 xor   $17,$2,$3
69543		 srl   $17,$17,15
69544		 andi  $17,$17,0x01     	 # Set Overflow
69545		 andi  $2,$2,0xffff
69546		 srl   $19,$2,15        	 # Set Sign
69547		 sltiu $18,$2,1        	 # Set Zero
69548		 or    $20,$0,$16       	 # Copy Carry to X
69549		 lw    $25,0x8C($21)
69550		 sw    $15,m68k_ICount
69551		 or    $5,$0,$2
69552		 or    $4,$0,$14
69553		 jalr  $25
69554		 sw    $23,0x4C($21)    	 # Delay slot
69555		 lw    $15,m68k_ICount
69556		 addiu $15,$15,-16
69557		 bgez  $15,3f
69558		 lhu   $24,0x00($23)    	 # Delay slot
69559		 j     MainExit
69560	3:
69561		 sll   $7,$24,2         	 # Delay slot
69562		 addu  $7,$7,$30
69563		 lw    $7,0x00($7)
69564		 jr    $7
69565		 nop                    	 # Delay slot
69566
69567OP0_e1f0:				#:
69568
69569		 addiu $23,$23,2
69570
69571		 andi  $24,$24,0x07
69572		 sll   $24,$24,2
69573		 addu  $24,$24,$21
69574		 lw    $14,0x20($24)
69575		 lhu   $7,0x00($23)
69576		 addiu $23,$23,2
69577		 seb   $6,$7
69578		 or    $25,$0,$7
69579		 srl   $7,$7,12
69580		 andi  $25,$25,0x0800
69581		 sll   $7,$7,2
69582		 addu  $7,$7,$21
69583		 bne   $25,$0,0f
69584		 lw    $25,0x00($7)      	 # Delay slot
69585		 seh   $25,$25
69586	0:
69587		 addu  $25,$14,$25
69588		 addu  $14,$25,$6
69589		 lw    $25,0x80($21)
69590		 sw    $15,m68k_ICount
69591		 sw    $14,0x44($29)
69592		 or    $4,$0,$14
69593		 jalr  $25
69594		 sw    $23,0x4C($21)    	 # Delay slot
69595		 lw    $14,0x44($29)
69596		 lw    $15,m68k_ICount
69597		 or    $3,$0,$2
69598		 sll   $2,$3,1
69599		 srl   $16,$3,15        	 # Set Carry
69600		 xor   $17,$2,$3
69601		 srl   $17,$17,15
69602		 andi  $17,$17,0x01     	 # Set Overflow
69603		 andi  $2,$2,0xffff
69604		 srl   $19,$2,15        	 # Set Sign
69605		 sltiu $18,$2,1        	 # Set Zero
69606		 or    $20,$0,$16       	 # Copy Carry to X
69607		 lw    $25,0x8C($21)
69608		 sw    $15,m68k_ICount
69609		 or    $5,$0,$2
69610		 or    $4,$0,$14
69611		 jalr  $25
69612		 sw    $23,0x4C($21)    	 # Delay slot
69613		 lw    $15,m68k_ICount
69614		 addiu $15,$15,-18
69615		 bgez  $15,3f
69616		 lhu   $24,0x00($23)    	 # Delay slot
69617		 j     MainExit
69618	3:
69619		 sll   $7,$24,2         	 # Delay slot
69620		 addu  $7,$7,$30
69621		 lw    $7,0x00($7)
69622		 jr    $7
69623		 nop                    	 # Delay slot
69624
69625OP0_e1f8:				#:
69626
69627		 addiu $23,$23,2
69628
69629		 lh    $14,0x00($23)
69630		 addiu $23,$23,2
69631		 lw    $25,0x80($21)
69632		 sw    $15,m68k_ICount
69633		 sw    $14,0x44($29)
69634		 or    $4,$0,$14
69635		 jalr  $25
69636		 sw    $23,0x4C($21)    	 # Delay slot
69637		 lw    $14,0x44($29)
69638		 lw    $15,m68k_ICount
69639		 or    $3,$0,$2
69640		 sll   $2,$3,1
69641		 srl   $16,$3,15        	 # Set Carry
69642		 xor   $17,$2,$3
69643		 srl   $17,$17,15
69644		 andi  $17,$17,0x01     	 # Set Overflow
69645		 andi  $2,$2,0xffff
69646		 srl   $19,$2,15        	 # Set Sign
69647		 sltiu $18,$2,1        	 # Set Zero
69648		 or    $20,$0,$16       	 # Copy Carry to X
69649		 lw    $25,0x8C($21)
69650		 sw    $15,m68k_ICount
69651		 or    $5,$0,$2
69652		 or    $4,$0,$14
69653		 jalr  $25
69654		 sw    $23,0x4C($21)    	 # Delay slot
69655		 lw    $15,m68k_ICount
69656		 addiu $15,$15,-16
69657		 bgez  $15,3f
69658		 lhu   $24,0x00($23)    	 # Delay slot
69659		 j     MainExit
69660	3:
69661		 sll   $7,$24,2         	 # Delay slot
69662		 addu  $7,$7,$30
69663		 lw    $7,0x00($7)
69664		 jr    $7
69665		 nop                    	 # Delay slot
69666
69667OP0_e1f9:				#:
69668
69669		 addiu $23,$23,2
69670
69671		 lhu   $14,0x00($23)
69672		 lhu   $25,0x02($23)
69673		 sll   $14,$14,16
69674		 or    $14,$14,$25
69675		 addiu $23,$23,4
69676		 lw    $25,0x80($21)
69677		 sw    $15,m68k_ICount
69678		 sw    $14,0x44($29)
69679		 or    $4,$0,$14
69680		 jalr  $25
69681		 sw    $23,0x4C($21)    	 # Delay slot
69682		 lw    $14,0x44($29)
69683		 lw    $15,m68k_ICount
69684		 or    $3,$0,$2
69685		 sll   $2,$3,1
69686		 srl   $16,$3,15        	 # Set Carry
69687		 xor   $17,$2,$3
69688		 srl   $17,$17,15
69689		 andi  $17,$17,0x01     	 # Set Overflow
69690		 andi  $2,$2,0xffff
69691		 srl   $19,$2,15        	 # Set Sign
69692		 sltiu $18,$2,1        	 # Set Zero
69693		 or    $20,$0,$16       	 # Copy Carry to X
69694		 lw    $25,0x8C($21)
69695		 sw    $15,m68k_ICount
69696		 or    $5,$0,$2
69697		 or    $4,$0,$14
69698		 jalr  $25
69699		 sw    $23,0x4C($21)    	 # Delay slot
69700		 lw    $15,m68k_ICount
69701		 addiu $15,$15,-20
69702		 bgez  $15,3f
69703		 lhu   $24,0x00($23)    	 # Delay slot
69704		 j     MainExit
69705	3:
69706		 sll   $7,$24,2         	 # Delay slot
69707		 addu  $7,$7,$30
69708		 lw    $7,0x00($7)
69709		 jr    $7
69710		 nop                    	 # Delay slot
69711
69712OP0_e010:				#:
69713		 addiu $23,$23,2
69714
69715		 andi  $8,$24,0x07
69716		 srl   $24,$24,9
69717		 addiu $24,$24,-1       	 # Move range down
69718		 andi  $24,$24,0x07     	 # Mask out lower bits
69719		 addiu $24,$24,1        	 # correct range
69720		 sll   $8,$8,2
69721		 addu  $8,$8,$21
69722		 lbu   $2,0x00($8)
69723		 beq   $24,$0,9f
69724		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
69725		 sll   $25,$24,1
69726		 andi  $9,$24,1
69727		 bne   $9,$24,7f
69728		 subu  $15,$15,$25       	 # Delay slot
69729		 andi  $20,$2,0x01      	 # Set X
69730		 sll   $16,$16,7
69731		 srl   $2,$2,1
69732		 bgez  $0,6f
69733		 or    $2,$2,$16        	 # Delay slot
69734	7:
69735		 ori   $11,$0,9
69736	8:
69737		 subu  $9,$24,$11
69738		 addiu $25,$9,-1
69739		 slt   $25,$25,$0
69740		 beq   $25,$0,8b
69741		 movz  $24,$9,$25        	 # Delay slot
69742		 subu  $11,$11,$24
69743		 addiu $9,$24,-1
69744		 addiu $10,$11,-1
69745		 sllv  $16,$16,$10
69746		 srlv  $20,$2,$9
69747		 andi  $20,$20,0x01     	 # Set X
69748		 sllv  $25,$2,$11
69749		 srlv  $2,$2,$24
69750		 or    $2,$2,$25
69751		 or    $2,$2,$16
69752	6:
69753		 or    $16,$0,$20       	 # Copy X to Carry
69754	9:
69755		 andi  $2,$2,0xFF
69756		 and   $17,$0,$0        	 # Clear Overflow
69757		 srl   $19,$2,7        	 # Set Sign
69758		 sltiu $18,$2,1         	 # Set Zero
69759		 sb    $2,0x00($8)
69760		 addiu $15,$15,-6
69761		 bgez  $15,3f
69762		 lhu   $24,0x00($23)    	 # Delay slot
69763		 j     MainExit
69764	3:
69765		 sll   $7,$24,2         	 # Delay slot
69766		 addu  $7,$7,$30
69767		 lw    $7,0x00($7)
69768		 jr    $7
69769		 nop                    	 # Delay slot
69770
69771OP0_e030:				#:
69772		 addiu $23,$23,2
69773
69774		 andi  $8,$24,0x07
69775		 srl   $24,$24,7
69776		 andi  $24,$24,0x1C
69777		 addu  $24,$24,$21
69778		 lw    $24,0x00($24)
69779		 andi  $24,$24,0x3F
69780		 sll   $8,$8,2
69781		 addu  $8,$8,$21
69782		 lbu   $2,0x00($8)
69783		 beq   $24,$0,9f
69784		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
69785		 sll   $25,$24,1
69786		 andi  $9,$24,1
69787		 bne   $9,$24,7f
69788		 subu  $15,$15,$25       	 # Delay slot
69789		 andi  $20,$2,0x01      	 # Set X
69790		 sll   $16,$16,7
69791		 srl   $2,$2,1
69792		 bgez  $0,6f
69793		 or    $2,$2,$16        	 # Delay slot
69794	7:
69795		 ori   $11,$0,9
69796	8:
69797		 subu  $9,$24,$11
69798		 addiu $25,$9,-1
69799		 slt   $25,$25,$0
69800		 beq   $25,$0,8b
69801		 movz  $24,$9,$25        	 # Delay slot
69802		 subu  $11,$11,$24
69803		 addiu $9,$24,-1
69804		 addiu $10,$11,-1
69805		 sllv  $16,$16,$10
69806		 srlv  $20,$2,$9
69807		 andi  $20,$20,0x01     	 # Set X
69808		 sllv  $25,$2,$11
69809		 srlv  $2,$2,$24
69810		 or    $2,$2,$25
69811		 or    $2,$2,$16
69812	6:
69813		 or    $16,$0,$20       	 # Copy X to Carry
69814	9:
69815		 andi  $2,$2,0xFF
69816		 and   $17,$0,$0        	 # Clear Overflow
69817		 srl   $19,$2,7        	 # Set Sign
69818		 sltiu $18,$2,1         	 # Set Zero
69819		 sb    $2,0x00($8)
69820		 addiu $15,$15,-6
69821		 bgez  $15,3f
69822		 lhu   $24,0x00($23)    	 # Delay slot
69823		 j     MainExit
69824	3:
69825		 sll   $7,$24,2         	 # Delay slot
69826		 addu  $7,$7,$30
69827		 lw    $7,0x00($7)
69828		 jr    $7
69829		 nop                    	 # Delay slot
69830
69831OP0_e050:				#:
69832		 addiu $23,$23,2
69833
69834		 andi  $8,$24,0x07
69835		 srl   $24,$24,9
69836		 addiu $24,$24,-1       	 # Move range down
69837		 andi  $24,$24,0x07     	 # Mask out lower bits
69838		 addiu $24,$24,1        	 # correct range
69839		 sll   $8,$8,2
69840		 addu  $8,$8,$21
69841		 lhu   $2,0x00($8)
69842		 beq   $24,$0,9f
69843		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
69844		 sll   $25,$24,1
69845		 andi  $9,$24,1
69846		 bne   $9,$24,7f
69847		 subu  $15,$15,$25       	 # Delay slot
69848		 andi  $20,$2,0x01      	 # Set X
69849		 sll   $16,$16,15
69850		 srl   $2,$2,1
69851		 bgez  $0,6f
69852		 or    $2,$2,$16        	 # Delay slot
69853	7:
69854		 ori   $11,$0,17
69855	8:
69856		 subu  $9,$24,$11
69857		 addiu $25,$9,-1
69858		 slt   $25,$25,$0
69859		 beq   $25,$0,8b
69860		 movz  $24,$9,$25        	 # Delay slot
69861		 subu  $11,$11,$24
69862		 addiu $9,$24,-1
69863		 addiu $10,$11,-1
69864		 sllv  $16,$16,$10
69865		 srlv  $20,$2,$9
69866		 andi  $20,$20,0x01     	 # Set X
69867		 sllv  $25,$2,$11
69868		 srlv  $2,$2,$24
69869		 or    $2,$2,$25
69870		 or    $2,$2,$16
69871	6:
69872		 or    $16,$0,$20       	 # Copy X to Carry
69873	9:
69874		 andi  $2,$2,0xFFFF
69875		 and   $17,$0,$0        	 # Clear Overflow
69876		 srl   $19,$2,15        	 # Set Sign
69877		 sltiu $18,$2,1         	 # Set Zero
69878		 sh    $2,0x00($8)
69879		 addiu $15,$15,-6
69880		 bgez  $15,3f
69881		 lhu   $24,0x00($23)    	 # Delay slot
69882		 j     MainExit
69883	3:
69884		 sll   $7,$24,2         	 # Delay slot
69885		 addu  $7,$7,$30
69886		 lw    $7,0x00($7)
69887		 jr    $7
69888		 nop                    	 # Delay slot
69889
69890OP0_e070:				#:
69891		 addiu $23,$23,2
69892
69893		 andi  $8,$24,0x07
69894		 srl   $24,$24,7
69895		 andi  $24,$24,0x1C
69896		 addu  $24,$24,$21
69897		 lw    $24,0x00($24)
69898		 andi  $24,$24,0x3F
69899		 sll   $8,$8,2
69900		 addu  $8,$8,$21
69901		 lhu   $2,0x00($8)
69902		 beq   $24,$0,9f
69903		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
69904		 sll   $25,$24,1
69905		 andi  $9,$24,1
69906		 bne   $9,$24,7f
69907		 subu  $15,$15,$25       	 # Delay slot
69908		 andi  $20,$2,0x01      	 # Set X
69909		 sll   $16,$16,15
69910		 srl   $2,$2,1
69911		 bgez  $0,6f
69912		 or    $2,$2,$16        	 # Delay slot
69913	7:
69914		 ori   $11,$0,17
69915	8:
69916		 subu  $9,$24,$11
69917		 addiu $25,$9,-1
69918		 slt   $25,$25,$0
69919		 beq   $25,$0,8b
69920		 movz  $24,$9,$25        	 # Delay slot
69921		 subu  $11,$11,$24
69922		 addiu $9,$24,-1
69923		 addiu $10,$11,-1
69924		 sllv  $16,$16,$10
69925		 srlv  $20,$2,$9
69926		 andi  $20,$20,0x01     	 # Set X
69927		 sllv  $25,$2,$11
69928		 srlv  $2,$2,$24
69929		 or    $2,$2,$25
69930		 or    $2,$2,$16
69931	6:
69932		 or    $16,$0,$20       	 # Copy X to Carry
69933	9:
69934		 andi  $2,$2,0xFFFF
69935		 and   $17,$0,$0        	 # Clear Overflow
69936		 srl   $19,$2,15        	 # Set Sign
69937		 sltiu $18,$2,1         	 # Set Zero
69938		 sh    $2,0x00($8)
69939		 addiu $15,$15,-6
69940		 bgez  $15,3f
69941		 lhu   $24,0x00($23)    	 # Delay slot
69942		 j     MainExit
69943	3:
69944		 sll   $7,$24,2         	 # Delay slot
69945		 addu  $7,$7,$30
69946		 lw    $7,0x00($7)
69947		 jr    $7
69948		 nop                    	 # Delay slot
69949
69950OP0_e090:				#:
69951		 addiu $23,$23,2
69952
69953		 andi  $8,$24,0x07
69954		 srl   $24,$24,9
69955		 addiu $24,$24,-1       	 # Move range down
69956		 andi  $24,$24,0x07     	 # Mask out lower bits
69957		 addiu $24,$24,1        	 # correct range
69958		 sll   $8,$8,2
69959		 addu  $8,$8,$21
69960		 lw    $2,0x00($8)
69961		 beq   $24,$0,9f
69962		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
69963		 sll   $25,$24,1
69964		 andi  $9,$24,1
69965		 bne   $9,$24,7f
69966		 subu  $15,$15,$25       	 # Delay slot
69967		 andi  $20,$2,0x01      	 # Set X
69968		 sll   $16,$16,31
69969		 srl   $2,$2,1
69970		 bgez  $0,6f
69971		 or    $2,$2,$16        	 # Delay slot
69972	7:
69973		 ori   $11,$0,33
69974	8:
69975		 subu  $9,$24,$11
69976		 addiu $25,$9,-1
69977		 slt   $25,$25,$0
69978		 beq   $25,$0,8b
69979		 movz  $24,$9,$25        	 # Delay slot
69980		 subu  $11,$11,$24
69981		 addiu $9,$24,-1
69982		 addiu $10,$11,-1
69983		 sllv  $16,$16,$10
69984		 srlv  $20,$2,$9
69985		 andi  $20,$20,0x01     	 # Set X
69986		 sllv  $25,$2,$11
69987		 srlv  $2,$2,$24
69988		 or    $2,$2,$25
69989		 or    $2,$2,$16
69990	6:
69991		 or    $16,$0,$20       	 # Copy X to Carry
69992	9:
69993		 and   $17,$0,$0        	 # Clear Overflow
69994		 srl   $19,$2,31        	 # Set Sign
69995		 sltiu $18,$2,1         	 # Set Zero
69996		 sw    $2,0x00($8)
69997		 addiu $15,$15,-8
69998		 bgez  $15,3f
69999		 lhu   $24,0x00($23)    	 # Delay slot
70000		 j     MainExit
70001	3:
70002		 sll   $7,$24,2         	 # Delay slot
70003		 addu  $7,$7,$30
70004		 lw    $7,0x00($7)
70005		 jr    $7
70006		 nop                    	 # Delay slot
70007
70008OP0_e0b0:				#:
70009		 addiu $23,$23,2
70010
70011		 andi  $8,$24,0x07
70012		 srl   $24,$24,7
70013		 andi  $24,$24,0x1C
70014		 addu  $24,$24,$21
70015		 lw    $24,0x00($24)
70016		 andi  $24,$24,0x3F
70017		 sll   $8,$8,2
70018		 addu  $8,$8,$21
70019		 lw    $2,0x00($8)
70020		 beq   $24,$0,9f
70021		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
70022		 sll   $25,$24,1
70023		 andi  $9,$24,1
70024		 bne   $9,$24,7f
70025		 subu  $15,$15,$25       	 # Delay slot
70026		 andi  $20,$2,0x01      	 # Set X
70027		 sll   $16,$16,31
70028		 srl   $2,$2,1
70029		 bgez  $0,6f
70030		 or    $2,$2,$16        	 # Delay slot
70031	7:
70032		 ori   $11,$0,33
70033	8:
70034		 subu  $9,$24,$11
70035		 addiu $25,$9,-1
70036		 slt   $25,$25,$0
70037		 beq   $25,$0,8b
70038		 movz  $24,$9,$25        	 # Delay slot
70039		 subu  $11,$11,$24
70040		 addiu $9,$24,-1
70041		 addiu $10,$11,-1
70042		 sllv  $16,$16,$10
70043		 srlv  $20,$2,$9
70044		 andi  $20,$20,0x01     	 # Set X
70045		 sllv  $25,$2,$11
70046		 srlv  $2,$2,$24
70047		 or    $2,$2,$25
70048		 or    $2,$2,$16
70049	6:
70050		 or    $16,$0,$20       	 # Copy X to Carry
70051	9:
70052		 and   $17,$0,$0        	 # Clear Overflow
70053		 srl   $19,$2,31        	 # Set Sign
70054		 sltiu $18,$2,1         	 # Set Zero
70055		 sw    $2,0x00($8)
70056		 addiu $15,$15,-8
70057		 bgez  $15,3f
70058		 lhu   $24,0x00($23)    	 # Delay slot
70059		 j     MainExit
70060	3:
70061		 sll   $7,$24,2         	 # Delay slot
70062		 addu  $7,$7,$30
70063		 lw    $7,0x00($7)
70064		 jr    $7
70065		 nop                    	 # Delay slot
70066
70067OP0_e110:				#:
70068		 addiu $23,$23,2
70069
70070		 andi  $8,$24,0x07
70071		 srl   $24,$24,9
70072		 addiu $24,$24,-1       	 # Move range down
70073		 andi  $24,$24,0x07     	 # Mask out lower bits
70074		 addiu $24,$24,1        	 # correct range
70075		 sll   $8,$8,2
70076		 addu  $8,$8,$21
70077		 lbu   $2,0x00($8)
70078		 beq   $24,$0,9f
70079		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
70080		 sll   $25,$24,1
70081		 andi  $9,$24,1
70082		 bne   $9,$24,7f
70083		 subu  $15,$15,$25       	 # Delay slot
70084		 srl   $20,$2,7        	 # Set X
70085		 sll   $2,$2,1
70086		 bgez  $0,6f
70087		 or    $2,$2,$16        	 # Delay slot
70088	7:
70089		 ori   $11,$0,9
70090	8:
70091		 subu  $9,$24,$11
70092		 addiu $25,$9,-1
70093		 slt   $25,$25,$0
70094		 beq   $25,$0,8b
70095		 movz  $24,$9,$25        	 # Delay slot
70096		 subu  $11,$11,$24
70097		 addiu $9,$24,-1
70098		 sllv  $16,$16,$9
70099		 srlv  $20,$2,$11
70100		 andi  $20,$20,0x01     	 # Set X
70101		 srlv  $25,$2,$11
70102		 sllv  $2,$2,$24
70103		 or    $2,$2,$25
70104		 or    $2,$2,$16
70105	6:
70106		 or    $16,$0,$20       	 # Copy X to Carry
70107	9:
70108		 andi  $2,$2,0xFF
70109		 and   $17,$0,$0        	 # Clear Overflow
70110		 srl   $19,$2,7        	 # Set Sign
70111		 sltiu $18,$2,1         	 # Set Zero
70112		 sb    $2,0x00($8)
70113		 addiu $15,$15,-6
70114		 bgez  $15,3f
70115		 lhu   $24,0x00($23)    	 # Delay slot
70116		 j     MainExit
70117	3:
70118		 sll   $7,$24,2         	 # Delay slot
70119		 addu  $7,$7,$30
70120		 lw    $7,0x00($7)
70121		 jr    $7
70122		 nop                    	 # Delay slot
70123
70124OP0_e130:				#:
70125		 addiu $23,$23,2
70126
70127		 andi  $8,$24,0x07
70128		 srl   $24,$24,7
70129		 andi  $24,$24,0x1C
70130		 addu  $24,$24,$21
70131		 lw    $24,0x00($24)
70132		 andi  $24,$24,0x3F
70133		 sll   $8,$8,2
70134		 addu  $8,$8,$21
70135		 lbu   $2,0x00($8)
70136		 beq   $24,$0,9f
70137		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
70138		 sll   $25,$24,1
70139		 andi  $9,$24,1
70140		 bne   $9,$24,7f
70141		 subu  $15,$15,$25       	 # Delay slot
70142		 srl   $20,$2,7        	 # Set X
70143		 sll   $2,$2,1
70144		 bgez  $0,6f
70145		 or    $2,$2,$16        	 # Delay slot
70146	7:
70147		 ori   $11,$0,9
70148	8:
70149		 subu  $9,$24,$11
70150		 addiu $25,$9,-1
70151		 slt   $25,$25,$0
70152		 beq   $25,$0,8b
70153		 movz  $24,$9,$25        	 # Delay slot
70154		 subu  $11,$11,$24
70155		 addiu $9,$24,-1
70156		 sllv  $16,$16,$9
70157		 srlv  $20,$2,$11
70158		 andi  $20,$20,0x01     	 # Set X
70159		 srlv  $25,$2,$11
70160		 sllv  $2,$2,$24
70161		 or    $2,$2,$25
70162		 or    $2,$2,$16
70163	6:
70164		 or    $16,$0,$20       	 # Copy X to Carry
70165	9:
70166		 andi  $2,$2,0xFF
70167		 and   $17,$0,$0        	 # Clear Overflow
70168		 srl   $19,$2,7        	 # Set Sign
70169		 sltiu $18,$2,1         	 # Set Zero
70170		 sb    $2,0x00($8)
70171		 addiu $15,$15,-6
70172		 bgez  $15,3f
70173		 lhu   $24,0x00($23)    	 # Delay slot
70174		 j     MainExit
70175	3:
70176		 sll   $7,$24,2         	 # Delay slot
70177		 addu  $7,$7,$30
70178		 lw    $7,0x00($7)
70179		 jr    $7
70180		 nop                    	 # Delay slot
70181
70182OP0_e150:				#:
70183		 addiu $23,$23,2
70184
70185		 andi  $8,$24,0x07
70186		 srl   $24,$24,9
70187		 addiu $24,$24,-1       	 # Move range down
70188		 andi  $24,$24,0x07     	 # Mask out lower bits
70189		 addiu $24,$24,1        	 # correct range
70190		 sll   $8,$8,2
70191		 addu  $8,$8,$21
70192		 lhu   $2,0x00($8)
70193		 beq   $24,$0,9f
70194		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
70195		 sll   $25,$24,1
70196		 andi  $9,$24,1
70197		 bne   $9,$24,7f
70198		 subu  $15,$15,$25       	 # Delay slot
70199		 srl   $20,$2,15        	 # Set X
70200		 sll   $2,$2,1
70201		 bgez  $0,6f
70202		 or    $2,$2,$16        	 # Delay slot
70203	7:
70204		 ori   $11,$0,17
70205	8:
70206		 subu  $9,$24,$11
70207		 addiu $25,$9,-1
70208		 slt   $25,$25,$0
70209		 beq   $25,$0,8b
70210		 movz  $24,$9,$25        	 # Delay slot
70211		 subu  $11,$11,$24
70212		 addiu $9,$24,-1
70213		 sllv  $16,$16,$9
70214		 srlv  $20,$2,$11
70215		 andi  $20,$20,0x01     	 # Set X
70216		 srlv  $25,$2,$11
70217		 sllv  $2,$2,$24
70218		 or    $2,$2,$25
70219		 or    $2,$2,$16
70220	6:
70221		 or    $16,$0,$20       	 # Copy X to Carry
70222	9:
70223		 andi  $2,$2,0xFFFF
70224		 and   $17,$0,$0        	 # Clear Overflow
70225		 srl   $19,$2,15        	 # Set Sign
70226		 sltiu $18,$2,1         	 # Set Zero
70227		 sh    $2,0x00($8)
70228		 addiu $15,$15,-6
70229		 bgez  $15,3f
70230		 lhu   $24,0x00($23)    	 # Delay slot
70231		 j     MainExit
70232	3:
70233		 sll   $7,$24,2         	 # Delay slot
70234		 addu  $7,$7,$30
70235		 lw    $7,0x00($7)
70236		 jr    $7
70237		 nop                    	 # Delay slot
70238
70239OP0_e170:				#:
70240		 addiu $23,$23,2
70241
70242		 andi  $8,$24,0x07
70243		 srl   $24,$24,7
70244		 andi  $24,$24,0x1C
70245		 addu  $24,$24,$21
70246		 lw    $24,0x00($24)
70247		 andi  $24,$24,0x3F
70248		 sll   $8,$8,2
70249		 addu  $8,$8,$21
70250		 lhu   $2,0x00($8)
70251		 beq   $24,$0,9f
70252		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
70253		 sll   $25,$24,1
70254		 andi  $9,$24,1
70255		 bne   $9,$24,7f
70256		 subu  $15,$15,$25       	 # Delay slot
70257		 srl   $20,$2,15        	 # Set X
70258		 sll   $2,$2,1
70259		 bgez  $0,6f
70260		 or    $2,$2,$16        	 # Delay slot
70261	7:
70262		 ori   $11,$0,17
70263	8:
70264		 subu  $9,$24,$11
70265		 addiu $25,$9,-1
70266		 slt   $25,$25,$0
70267		 beq   $25,$0,8b
70268		 movz  $24,$9,$25        	 # Delay slot
70269		 subu  $11,$11,$24
70270		 addiu $9,$24,-1
70271		 sllv  $16,$16,$9
70272		 srlv  $20,$2,$11
70273		 andi  $20,$20,0x01     	 # Set X
70274		 srlv  $25,$2,$11
70275		 sllv  $2,$2,$24
70276		 or    $2,$2,$25
70277		 or    $2,$2,$16
70278	6:
70279		 or    $16,$0,$20       	 # Copy X to Carry
70280	9:
70281		 andi  $2,$2,0xFFFF
70282		 and   $17,$0,$0        	 # Clear Overflow
70283		 srl   $19,$2,15        	 # Set Sign
70284		 sltiu $18,$2,1         	 # Set Zero
70285		 sh    $2,0x00($8)
70286		 addiu $15,$15,-6
70287		 bgez  $15,3f
70288		 lhu   $24,0x00($23)    	 # Delay slot
70289		 j     MainExit
70290	3:
70291		 sll   $7,$24,2         	 # Delay slot
70292		 addu  $7,$7,$30
70293		 lw    $7,0x00($7)
70294		 jr    $7
70295		 nop                    	 # Delay slot
70296
70297OP0_e190:				#:
70298		 addiu $23,$23,2
70299
70300		 andi  $8,$24,0x07
70301		 srl   $24,$24,9
70302		 addiu $24,$24,-1       	 # Move range down
70303		 andi  $24,$24,0x07     	 # Mask out lower bits
70304		 addiu $24,$24,1        	 # correct range
70305		 sll   $8,$8,2
70306		 addu  $8,$8,$21
70307		 lw    $2,0x00($8)
70308		 beq   $24,$0,9f
70309		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
70310		 sll   $25,$24,1
70311		 andi  $9,$24,1
70312		 bne   $9,$24,7f
70313		 subu  $15,$15,$25       	 # Delay slot
70314		 srl   $20,$2,31        	 # Set X
70315		 sll   $2,$2,1
70316		 bgez  $0,6f
70317		 or    $2,$2,$16        	 # Delay slot
70318	7:
70319		 ori   $11,$0,33
70320	8:
70321		 subu  $9,$24,$11
70322		 addiu $25,$9,-1
70323		 slt   $25,$25,$0
70324		 beq   $25,$0,8b
70325		 movz  $24,$9,$25        	 # Delay slot
70326		 subu  $11,$11,$24
70327		 addiu $9,$24,-1
70328		 sllv  $16,$16,$9
70329		 srlv  $20,$2,$11
70330		 andi  $20,$20,0x01     	 # Set X
70331		 srlv  $25,$2,$11
70332		 sllv  $2,$2,$24
70333		 or    $2,$2,$25
70334		 or    $2,$2,$16
70335	6:
70336		 or    $16,$0,$20       	 # Copy X to Carry
70337	9:
70338		 and   $17,$0,$0        	 # Clear Overflow
70339		 srl   $19,$2,31        	 # Set Sign
70340		 sltiu $18,$2,1         	 # Set Zero
70341		 sw    $2,0x00($8)
70342		 addiu $15,$15,-8
70343		 bgez  $15,3f
70344		 lhu   $24,0x00($23)    	 # Delay slot
70345		 j     MainExit
70346	3:
70347		 sll   $7,$24,2         	 # Delay slot
70348		 addu  $7,$7,$30
70349		 lw    $7,0x00($7)
70350		 jr    $7
70351		 nop                    	 # Delay slot
70352
70353OP0_e1b0:				#:
70354		 addiu $23,$23,2
70355
70356		 andi  $8,$24,0x07
70357		 srl   $24,$24,7
70358		 andi  $24,$24,0x1C
70359		 addu  $24,$24,$21
70360		 lw    $24,0x00($24)
70361		 andi  $24,$24,0x3F
70362		 sll   $8,$8,2
70363		 addu  $8,$8,$21
70364		 lw    $2,0x00($8)
70365		 beq   $24,$0,9f
70366		 or    $16,$0,$20       	 # Delay slot - Copy X to Carry
70367		 sll   $25,$24,1
70368		 andi  $9,$24,1
70369		 bne   $9,$24,7f
70370		 subu  $15,$15,$25       	 # Delay slot
70371		 srl   $20,$2,31        	 # Set X
70372		 sll   $2,$2,1
70373		 bgez  $0,6f
70374		 or    $2,$2,$16        	 # Delay slot
70375	7:
70376		 ori   $11,$0,33
70377	8:
70378		 subu  $9,$24,$11
70379		 addiu $25,$9,-1
70380		 slt   $25,$25,$0
70381		 beq   $25,$0,8b
70382		 movz  $24,$9,$25        	 # Delay slot
70383		 subu  $11,$11,$24
70384		 addiu $9,$24,-1
70385		 sllv  $16,$16,$9
70386		 srlv  $20,$2,$11
70387		 andi  $20,$20,0x01     	 # Set X
70388		 srlv  $25,$2,$11
70389		 sllv  $2,$2,$24
70390		 or    $2,$2,$25
70391		 or    $2,$2,$16
70392	6:
70393		 or    $16,$0,$20       	 # Copy X to Carry
70394	9:
70395		 and   $17,$0,$0        	 # Clear Overflow
70396		 srl   $19,$2,31        	 # Set Sign
70397		 sltiu $18,$2,1         	 # Set Zero
70398		 sw    $2,0x00($8)
70399		 addiu $15,$15,-8
70400		 bgez  $15,3f
70401		 lhu   $24,0x00($23)    	 # Delay slot
70402		 j     MainExit
70403	3:
70404		 sll   $7,$24,2         	 # Delay slot
70405		 addu  $7,$7,$30
70406		 lw    $7,0x00($7)
70407		 jr    $7
70408		 nop                    	 # Delay slot
70409
70410OP0_e210:				#:
70411		 addiu $23,$23,2
70412
70413		 andi  $24,$24,0x07
70414		 sll   $24,$24,2
70415		 addu  $24,$24,$21
70416		 lbu   $2,0x00($24)
70417		 sll   $9,$20,7
70418		 andi  $20,$2,0x01      	 # Set X
70419		 srl   $2,$2,1
70420		 or    $2,$2,$9
70421		 or    $16,$0,$20       	 # Copy X to Carry
70422		 andi  $2,$2,0xFF
70423		 and   $17,$0,$0        	 # Clear Overflow
70424		 srl   $19,$2,7        	 # Set Sign
70425		 sltiu $18,$2,1         	 # Set Zero
70426		 sb    $2,0x00($24)
70427		 addiu $15,$15,-8
70428		 bgez  $15,3f
70429		 lhu   $24,0x00($23)    	 # Delay slot
70430		 j     MainExit
70431	3:
70432		 sll   $7,$24,2         	 # Delay slot
70433		 addu  $7,$7,$30
70434		 lw    $7,0x00($7)
70435		 jr    $7
70436		 nop                    	 # Delay slot
70437
70438OP0_e250:				#:
70439		 addiu $23,$23,2
70440
70441		 andi  $24,$24,0x07
70442		 sll   $24,$24,2
70443		 addu  $24,$24,$21
70444		 lhu   $2,0x00($24)
70445		 sll   $9,$20,15
70446		 andi  $20,$2,0x01      	 # Set X
70447		 srl   $2,$2,1
70448		 or    $2,$2,$9
70449		 or    $16,$0,$20       	 # Copy X to Carry
70450		 andi  $2,$2,0xFFFF
70451		 and   $17,$0,$0        	 # Clear Overflow
70452		 srl   $19,$2,15        	 # Set Sign
70453		 sltiu $18,$2,1         	 # Set Zero
70454		 sh    $2,0x00($24)
70455		 addiu $15,$15,-8
70456		 bgez  $15,3f
70457		 lhu   $24,0x00($23)    	 # Delay slot
70458		 j     MainExit
70459	3:
70460		 sll   $7,$24,2         	 # Delay slot
70461		 addu  $7,$7,$30
70462		 lw    $7,0x00($7)
70463		 jr    $7
70464		 nop                    	 # Delay slot
70465
70466OP0_e290:				#:
70467		 addiu $23,$23,2
70468
70469		 andi  $24,$24,0x07
70470		 sll   $24,$24,2
70471		 addu  $24,$24,$21
70472		 lw    $2,0x00($24)
70473		 sll   $9,$20,31
70474		 andi  $20,$2,0x01      	 # Set X
70475		 srl   $2,$2,1
70476		 or    $2,$2,$9
70477		 or    $16,$0,$20       	 # Copy X to Carry
70478		 and   $17,$0,$0        	 # Clear Overflow
70479		 srl   $19,$2,31        	 # Set Sign
70480		 sltiu $18,$2,1         	 # Set Zero
70481		 sw    $2,0x00($24)
70482		 addiu $15,$15,-10
70483		 bgez  $15,3f
70484		 lhu   $24,0x00($23)    	 # Delay slot
70485		 j     MainExit
70486	3:
70487		 sll   $7,$24,2         	 # Delay slot
70488		 addu  $7,$7,$30
70489		 lw    $7,0x00($7)
70490		 jr    $7
70491		 nop                    	 # Delay slot
70492
70493OP0_e310:				#:
70494		 addiu $23,$23,2
70495
70496		 andi  $24,$24,0x07
70497		 sll   $24,$24,2
70498		 addu  $24,$24,$21
70499		 lbu   $2,0x00($24)
70500		 or    $9,$0,$20
70501		 srl   $20,$2,7        	 # Set X
70502		 sll   $2,$2,1
70503		 or    $2,$2,$9
70504		 or    $16,$0,$20       	 # Copy X to Carry
70505		 andi  $2,$2,0xFF
70506		 and   $17,$0,$0        	 # Clear Overflow
70507		 srl   $19,$2,7        	 # Set Sign
70508		 sltiu $18,$2,1         	 # Set Zero
70509		 sb    $2,0x00($24)
70510		 addiu $15,$15,-8
70511		 bgez  $15,3f
70512		 lhu   $24,0x00($23)    	 # Delay slot
70513		 j     MainExit
70514	3:
70515		 sll   $7,$24,2         	 # Delay slot
70516		 addu  $7,$7,$30
70517		 lw    $7,0x00($7)
70518		 jr    $7
70519		 nop                    	 # Delay slot
70520
70521OP0_e350:				#:
70522		 addiu $23,$23,2
70523
70524		 andi  $24,$24,0x07
70525		 sll   $24,$24,2
70526		 addu  $24,$24,$21
70527		 lhu   $2,0x00($24)
70528		 or    $9,$0,$20
70529		 srl   $20,$2,15        	 # Set X
70530		 sll   $2,$2,1
70531		 or    $2,$2,$9
70532		 or    $16,$0,$20       	 # Copy X to Carry
70533		 andi  $2,$2,0xFFFF
70534		 and   $17,$0,$0        	 # Clear Overflow
70535		 srl   $19,$2,15        	 # Set Sign
70536		 sltiu $18,$2,1         	 # Set Zero
70537		 sh    $2,0x00($24)
70538		 addiu $15,$15,-8
70539		 bgez  $15,3f
70540		 lhu   $24,0x00($23)    	 # Delay slot
70541		 j     MainExit
70542	3:
70543		 sll   $7,$24,2         	 # Delay slot
70544		 addu  $7,$7,$30
70545		 lw    $7,0x00($7)
70546		 jr    $7
70547		 nop                    	 # Delay slot
70548
70549OP0_e390:				#:
70550		 addiu $23,$23,2
70551
70552		 andi  $24,$24,0x07
70553		 sll   $24,$24,2
70554		 addu  $24,$24,$21
70555		 lw    $2,0x00($24)
70556		 or    $9,$0,$20
70557		 srl   $20,$2,31        	 # Set X
70558		 sll   $2,$2,1
70559		 or    $2,$2,$9
70560		 or    $16,$0,$20       	 # Copy X to Carry
70561		 and   $17,$0,$0        	 # Clear Overflow
70562		 srl   $19,$2,31        	 # Set Sign
70563		 sltiu $18,$2,1         	 # Set Zero
70564		 sw    $2,0x00($24)
70565		 addiu $15,$15,-10
70566		 bgez  $15,3f
70567		 lhu   $24,0x00($23)    	 # Delay slot
70568		 j     MainExit
70569	3:
70570		 sll   $7,$24,2         	 # Delay slot
70571		 addu  $7,$7,$30
70572		 lw    $7,0x00($7)
70573		 jr    $7
70574		 nop                    	 # Delay slot
70575
70576OP0_e4d0:				#:
70577		 addiu $23,$23,2
70578
70579		 andi  $24,$24,0x07
70580		 sll   $24,$24,2
70581		 addu  $24,$24,$21
70582		 lw    $14,0x20($24)
70583		 lw    $25,0x80($21)
70584		 sw    $15,m68k_ICount
70585		 sw    $14,0x44($29)
70586		 or    $4,$0,$14
70587		 jalr  $25
70588		 sw    $23,0x4C($21)    	 # Delay slot
70589		 lw    $14,0x44($29)
70590		 lw    $15,m68k_ICount
70591		 sll   $9,$20,15
70592		 andi  $20,$2,0x01      	 # Set X
70593		 srl   $2,$2,1
70594		 or    $2,$2,$9
70595		 or    $16,$0,$20       	 # Copy X to Carry
70596		 andi  $2,$2,0xffff
70597		 and   $17,$0,$0        	 # Clear Overflow
70598		 srl   $19,$2,15        	 # Set Sign
70599		 sltiu $18,$2,1         	 # Set Zero
70600		 lw    $25,0x8C($21)
70601		 sw    $15,m68k_ICount
70602		 or    $5,$0,$2
70603		 or    $4,$0,$14
70604		 jalr  $25
70605		 sw    $23,0x4C($21)    	 # Delay slot
70606		 lw    $15,m68k_ICount
70607		 addiu $15,$15,-12
70608		 bgez  $15,3f
70609		 lhu   $24,0x00($23)    	 # Delay slot
70610		 j     MainExit
70611	3:
70612		 sll   $7,$24,2         	 # Delay slot
70613		 addu  $7,$7,$30
70614		 lw    $7,0x00($7)
70615		 jr    $7
70616		 nop                    	 # Delay slot
70617
70618OP0_e4d8:				#:
70619		 addiu $23,$23,2
70620
70621		 andi  $24,$24,0x07
70622		 sll   $24,$24,2
70623		 addu  $24,$24,$21
70624		 lw    $14,0x20($24)
70625		 addiu $25,$14,2
70626		 sw    $25,0x20($24)
70627		 lw    $25,0x80($21)
70628		 sw    $15,m68k_ICount
70629		 sw    $14,0x44($29)
70630		 or    $4,$0,$14
70631		 jalr  $25
70632		 sw    $23,0x4C($21)    	 # Delay slot
70633		 lw    $14,0x44($29)
70634		 lw    $15,m68k_ICount
70635		 sll   $9,$20,15
70636		 andi  $20,$2,0x01      	 # Set X
70637		 srl   $2,$2,1
70638		 or    $2,$2,$9
70639		 or    $16,$0,$20       	 # Copy X to Carry
70640		 andi  $2,$2,0xffff
70641		 and   $17,$0,$0        	 # Clear Overflow
70642		 srl   $19,$2,15        	 # Set Sign
70643		 sltiu $18,$2,1         	 # Set Zero
70644		 lw    $25,0x8C($21)
70645		 sw    $15,m68k_ICount
70646		 or    $5,$0,$2
70647		 or    $4,$0,$14
70648		 jalr  $25
70649		 sw    $23,0x4C($21)    	 # Delay slot
70650		 lw    $15,m68k_ICount
70651		 addiu $15,$15,-12
70652		 bgez  $15,3f
70653		 lhu   $24,0x00($23)    	 # Delay slot
70654		 j     MainExit
70655	3:
70656		 sll   $7,$24,2         	 # Delay slot
70657		 addu  $7,$7,$30
70658		 lw    $7,0x00($7)
70659		 jr    $7
70660		 nop                    	 # Delay slot
70661
70662OP0_e4e0:				#:
70663		 addiu $23,$23,2
70664
70665		 andi  $24,$24,0x07
70666		 sll   $24,$24,2
70667		 addu  $24,$24,$21
70668		 lw    $14,0x20($24)
70669		 addiu $14,$14,-2
70670		 sw    $14,0x20($24)
70671		 lw    $25,0x80($21)
70672		 sw    $15,m68k_ICount
70673		 sw    $14,0x44($29)
70674		 or    $4,$0,$14
70675		 jalr  $25
70676		 sw    $23,0x4C($21)    	 # Delay slot
70677		 lw    $14,0x44($29)
70678		 lw    $15,m68k_ICount
70679		 sll   $9,$20,15
70680		 andi  $20,$2,0x01      	 # Set X
70681		 srl   $2,$2,1
70682		 or    $2,$2,$9
70683		 or    $16,$0,$20       	 # Copy X to Carry
70684		 andi  $2,$2,0xffff
70685		 and   $17,$0,$0        	 # Clear Overflow
70686		 srl   $19,$2,15        	 # Set Sign
70687		 sltiu $18,$2,1         	 # Set Zero
70688		 lw    $25,0x8C($21)
70689		 sw    $15,m68k_ICount
70690		 or    $5,$0,$2
70691		 or    $4,$0,$14
70692		 jalr  $25
70693		 sw    $23,0x4C($21)    	 # Delay slot
70694		 lw    $15,m68k_ICount
70695		 addiu $15,$15,-14
70696		 bgez  $15,3f
70697		 lhu   $24,0x00($23)    	 # Delay slot
70698		 j     MainExit
70699	3:
70700		 sll   $7,$24,2         	 # Delay slot
70701		 addu  $7,$7,$30
70702		 lw    $7,0x00($7)
70703		 jr    $7
70704		 nop                    	 # Delay slot
70705
70706OP0_e4e8:				#:
70707		 addiu $23,$23,2
70708
70709		 andi  $24,$24,0x07
70710		 lh    $7,0x00($23)
70711		 sll   $24,$24,2
70712		 addu  $24,$24,$21
70713		 lw    $14,0x20($24)
70714		 addiu $23,$23,2
70715		 addu  $14,$14,$7
70716		 lw    $25,0x80($21)
70717		 sw    $15,m68k_ICount
70718		 sw    $14,0x44($29)
70719		 or    $4,$0,$14
70720		 jalr  $25
70721		 sw    $23,0x4C($21)    	 # Delay slot
70722		 lw    $14,0x44($29)
70723		 lw    $15,m68k_ICount
70724		 sll   $9,$20,15
70725		 andi  $20,$2,0x01      	 # Set X
70726		 srl   $2,$2,1
70727		 or    $2,$2,$9
70728		 or    $16,$0,$20       	 # Copy X to Carry
70729		 andi  $2,$2,0xffff
70730		 and   $17,$0,$0        	 # Clear Overflow
70731		 srl   $19,$2,15        	 # Set Sign
70732		 sltiu $18,$2,1         	 # Set Zero
70733		 lw    $25,0x8C($21)
70734		 sw    $15,m68k_ICount
70735		 or    $5,$0,$2
70736		 or    $4,$0,$14
70737		 jalr  $25
70738		 sw    $23,0x4C($21)    	 # Delay slot
70739		 lw    $15,m68k_ICount
70740		 addiu $15,$15,-16
70741		 bgez  $15,3f
70742		 lhu   $24,0x00($23)    	 # Delay slot
70743		 j     MainExit
70744	3:
70745		 sll   $7,$24,2         	 # Delay slot
70746		 addu  $7,$7,$30
70747		 lw    $7,0x00($7)
70748		 jr    $7
70749		 nop                    	 # Delay slot
70750
70751OP0_e4f0:				#:
70752		 addiu $23,$23,2
70753
70754		 andi  $24,$24,0x07
70755		 sll   $24,$24,2
70756		 addu  $24,$24,$21
70757		 lw    $14,0x20($24)
70758		 lhu   $7,0x00($23)
70759		 addiu $23,$23,2
70760		 seb   $6,$7
70761		 or    $25,$0,$7
70762		 srl   $7,$7,12
70763		 andi  $25,$25,0x0800
70764		 sll   $7,$7,2
70765		 addu  $7,$7,$21
70766		 bne   $25,$0,0f
70767		 lw    $25,0x00($7)      	 # Delay slot
70768		 seh   $25,$25
70769	0:
70770		 addu  $25,$14,$25
70771		 addu  $14,$25,$6
70772		 lw    $25,0x80($21)
70773		 sw    $15,m68k_ICount
70774		 sw    $14,0x44($29)
70775		 or    $4,$0,$14
70776		 jalr  $25
70777		 sw    $23,0x4C($21)    	 # Delay slot
70778		 lw    $14,0x44($29)
70779		 lw    $15,m68k_ICount
70780		 sll   $9,$20,15
70781		 andi  $20,$2,0x01      	 # Set X
70782		 srl   $2,$2,1
70783		 or    $2,$2,$9
70784		 or    $16,$0,$20       	 # Copy X to Carry
70785		 andi  $2,$2,0xffff
70786		 and   $17,$0,$0        	 # Clear Overflow
70787		 srl   $19,$2,15        	 # Set Sign
70788		 sltiu $18,$2,1         	 # Set Zero
70789		 lw    $25,0x8C($21)
70790		 sw    $15,m68k_ICount
70791		 or    $5,$0,$2
70792		 or    $4,$0,$14
70793		 jalr  $25
70794		 sw    $23,0x4C($21)    	 # Delay slot
70795		 lw    $15,m68k_ICount
70796		 addiu $15,$15,-18
70797		 bgez  $15,3f
70798		 lhu   $24,0x00($23)    	 # Delay slot
70799		 j     MainExit
70800	3:
70801		 sll   $7,$24,2         	 # Delay slot
70802		 addu  $7,$7,$30
70803		 lw    $7,0x00($7)
70804		 jr    $7
70805		 nop                    	 # Delay slot
70806
70807OP0_e4f8:				#:
70808		 addiu $23,$23,2
70809
70810		 lh    $14,0x00($23)
70811		 addiu $23,$23,2
70812		 lw    $25,0x80($21)
70813		 sw    $15,m68k_ICount
70814		 sw    $14,0x44($29)
70815		 or    $4,$0,$14
70816		 jalr  $25
70817		 sw    $23,0x4C($21)    	 # Delay slot
70818		 lw    $14,0x44($29)
70819		 lw    $15,m68k_ICount
70820		 sll   $9,$20,15
70821		 andi  $20,$2,0x01      	 # Set X
70822		 srl   $2,$2,1
70823		 or    $2,$2,$9
70824		 or    $16,$0,$20       	 # Copy X to Carry
70825		 andi  $2,$2,0xffff
70826		 and   $17,$0,$0        	 # Clear Overflow
70827		 srl   $19,$2,15        	 # Set Sign
70828		 sltiu $18,$2,1         	 # Set Zero
70829		 lw    $25,0x8C($21)
70830		 sw    $15,m68k_ICount
70831		 or    $5,$0,$2
70832		 or    $4,$0,$14
70833		 jalr  $25
70834		 sw    $23,0x4C($21)    	 # Delay slot
70835		 lw    $15,m68k_ICount
70836		 addiu $15,$15,-16
70837		 bgez  $15,3f
70838		 lhu   $24,0x00($23)    	 # Delay slot
70839		 j     MainExit
70840	3:
70841		 sll   $7,$24,2         	 # Delay slot
70842		 addu  $7,$7,$30
70843		 lw    $7,0x00($7)
70844		 jr    $7
70845		 nop                    	 # Delay slot
70846
70847OP0_e4f9:				#:
70848		 addiu $23,$23,2
70849
70850		 lhu   $14,0x00($23)
70851		 lhu   $25,0x02($23)
70852		 sll   $14,$14,16
70853		 or    $14,$14,$25
70854		 addiu $23,$23,4
70855		 lw    $25,0x80($21)
70856		 sw    $15,m68k_ICount
70857		 sw    $14,0x44($29)
70858		 or    $4,$0,$14
70859		 jalr  $25
70860		 sw    $23,0x4C($21)    	 # Delay slot
70861		 lw    $14,0x44($29)
70862		 lw    $15,m68k_ICount
70863		 sll   $9,$20,15
70864		 andi  $20,$2,0x01      	 # Set X
70865		 srl   $2,$2,1
70866		 or    $2,$2,$9
70867		 or    $16,$0,$20       	 # Copy X to Carry
70868		 andi  $2,$2,0xffff
70869		 and   $17,$0,$0        	 # Clear Overflow
70870		 srl   $19,$2,15        	 # Set Sign
70871		 sltiu $18,$2,1         	 # Set Zero
70872		 lw    $25,0x8C($21)
70873		 sw    $15,m68k_ICount
70874		 or    $5,$0,$2
70875		 or    $4,$0,$14
70876		 jalr  $25
70877		 sw    $23,0x4C($21)    	 # Delay slot
70878		 lw    $15,m68k_ICount
70879		 addiu $15,$15,-20
70880		 bgez  $15,3f
70881		 lhu   $24,0x00($23)    	 # Delay slot
70882		 j     MainExit
70883	3:
70884		 sll   $7,$24,2         	 # Delay slot
70885		 addu  $7,$7,$30
70886		 lw    $7,0x00($7)
70887		 jr    $7
70888		 nop                    	 # Delay slot
70889
70890OP0_e5d0:				#:
70891		 addiu $23,$23,2
70892
70893		 andi  $24,$24,0x07
70894		 sll   $24,$24,2
70895		 addu  $24,$24,$21
70896		 lw    $14,0x20($24)
70897		 lw    $25,0x80($21)
70898		 sw    $15,m68k_ICount
70899		 sw    $14,0x44($29)
70900		 or    $4,$0,$14
70901		 jalr  $25
70902		 sw    $23,0x4C($21)    	 # Delay slot
70903		 lw    $14,0x44($29)
70904		 lw    $15,m68k_ICount
70905		 andi  $9,$20,0x01
70906		 srl   $20,$2,15        	 # Set X
70907		 sll   $2,$2,1
70908		 or    $2,$2,$9
70909		 or    $16,$0,$20       	 # Copy X to Carry
70910		 andi  $2,$2,0xffff
70911		 and   $17,$0,$0        	 # Clear Overflow
70912		 srl   $19,$2,15        	 # Set Sign
70913		 sltiu $18,$2,1         	 # Set Zero
70914		 lw    $25,0x8C($21)
70915		 sw    $15,m68k_ICount
70916		 or    $5,$0,$2
70917		 or    $4,$0,$14
70918		 jalr  $25
70919		 sw    $23,0x4C($21)    	 # Delay slot
70920		 lw    $15,m68k_ICount
70921		 addiu $15,$15,-12
70922		 bgez  $15,3f
70923		 lhu   $24,0x00($23)    	 # Delay slot
70924		 j     MainExit
70925	3:
70926		 sll   $7,$24,2         	 # Delay slot
70927		 addu  $7,$7,$30
70928		 lw    $7,0x00($7)
70929		 jr    $7
70930		 nop                    	 # Delay slot
70931
70932OP0_e5d8:				#:
70933		 addiu $23,$23,2
70934
70935		 andi  $24,$24,0x07
70936		 sll   $24,$24,2
70937		 addu  $24,$24,$21
70938		 lw    $14,0x20($24)
70939		 addiu $25,$14,2
70940		 sw    $25,0x20($24)
70941		 lw    $25,0x80($21)
70942		 sw    $15,m68k_ICount
70943		 sw    $14,0x44($29)
70944		 or    $4,$0,$14
70945		 jalr  $25
70946		 sw    $23,0x4C($21)    	 # Delay slot
70947		 lw    $14,0x44($29)
70948		 lw    $15,m68k_ICount
70949		 andi  $9,$20,0x01
70950		 srl   $20,$2,15        	 # Set X
70951		 sll   $2,$2,1
70952		 or    $2,$2,$9
70953		 or    $16,$0,$20       	 # Copy X to Carry
70954		 andi  $2,$2,0xffff
70955		 and   $17,$0,$0        	 # Clear Overflow
70956		 srl   $19,$2,15        	 # Set Sign
70957		 sltiu $18,$2,1         	 # Set Zero
70958		 lw    $25,0x8C($21)
70959		 sw    $15,m68k_ICount
70960		 or    $5,$0,$2
70961		 or    $4,$0,$14
70962		 jalr  $25
70963		 sw    $23,0x4C($21)    	 # Delay slot
70964		 lw    $15,m68k_ICount
70965		 addiu $15,$15,-12
70966		 bgez  $15,3f
70967		 lhu   $24,0x00($23)    	 # Delay slot
70968		 j     MainExit
70969	3:
70970		 sll   $7,$24,2         	 # Delay slot
70971		 addu  $7,$7,$30
70972		 lw    $7,0x00($7)
70973		 jr    $7
70974		 nop                    	 # Delay slot
70975
70976OP0_e5e0:				#:
70977		 addiu $23,$23,2
70978
70979		 andi  $24,$24,0x07
70980		 sll   $24,$24,2
70981		 addu  $24,$24,$21
70982		 lw    $14,0x20($24)
70983		 addiu $14,$14,-2
70984		 sw    $14,0x20($24)
70985		 lw    $25,0x80($21)
70986		 sw    $15,m68k_ICount
70987		 sw    $14,0x44($29)
70988		 or    $4,$0,$14
70989		 jalr  $25
70990		 sw    $23,0x4C($21)    	 # Delay slot
70991		 lw    $14,0x44($29)
70992		 lw    $15,m68k_ICount
70993		 andi  $9,$20,0x01
70994		 srl   $20,$2,15        	 # Set X
70995		 sll   $2,$2,1
70996		 or    $2,$2,$9
70997		 or    $16,$0,$20       	 # Copy X to Carry
70998		 andi  $2,$2,0xffff
70999		 and   $17,$0,$0        	 # Clear Overflow
71000		 srl   $19,$2,15        	 # Set Sign
71001		 sltiu $18,$2,1         	 # Set Zero
71002		 lw    $25,0x8C($21)
71003		 sw    $15,m68k_ICount
71004		 or    $5,$0,$2
71005		 or    $4,$0,$14
71006		 jalr  $25
71007		 sw    $23,0x4C($21)    	 # Delay slot
71008		 lw    $15,m68k_ICount
71009		 addiu $15,$15,-14
71010		 bgez  $15,3f
71011		 lhu   $24,0x00($23)    	 # Delay slot
71012		 j     MainExit
71013	3:
71014		 sll   $7,$24,2         	 # Delay slot
71015		 addu  $7,$7,$30
71016		 lw    $7,0x00($7)
71017		 jr    $7
71018		 nop                    	 # Delay slot
71019
71020OP0_e5e8:				#:
71021		 addiu $23,$23,2
71022
71023		 andi  $24,$24,0x07
71024		 lh    $7,0x00($23)
71025		 sll   $24,$24,2
71026		 addu  $24,$24,$21
71027		 lw    $14,0x20($24)
71028		 addiu $23,$23,2
71029		 addu  $14,$14,$7
71030		 lw    $25,0x80($21)
71031		 sw    $15,m68k_ICount
71032		 sw    $14,0x44($29)
71033		 or    $4,$0,$14
71034		 jalr  $25
71035		 sw    $23,0x4C($21)    	 # Delay slot
71036		 lw    $14,0x44($29)
71037		 lw    $15,m68k_ICount
71038		 andi  $9,$20,0x01
71039		 srl   $20,$2,15        	 # Set X
71040		 sll   $2,$2,1
71041		 or    $2,$2,$9
71042		 or    $16,$0,$20       	 # Copy X to Carry
71043		 andi  $2,$2,0xffff
71044		 and   $17,$0,$0        	 # Clear Overflow
71045		 srl   $19,$2,15        	 # Set Sign
71046		 sltiu $18,$2,1         	 # Set Zero
71047		 lw    $25,0x8C($21)
71048		 sw    $15,m68k_ICount
71049		 or    $5,$0,$2
71050		 or    $4,$0,$14
71051		 jalr  $25
71052		 sw    $23,0x4C($21)    	 # Delay slot
71053		 lw    $15,m68k_ICount
71054		 addiu $15,$15,-16
71055		 bgez  $15,3f
71056		 lhu   $24,0x00($23)    	 # Delay slot
71057		 j     MainExit
71058	3:
71059		 sll   $7,$24,2         	 # Delay slot
71060		 addu  $7,$7,$30
71061		 lw    $7,0x00($7)
71062		 jr    $7
71063		 nop                    	 # Delay slot
71064
71065OP0_e5f0:				#:
71066		 addiu $23,$23,2
71067
71068		 andi  $24,$24,0x07
71069		 sll   $24,$24,2
71070		 addu  $24,$24,$21
71071		 lw    $14,0x20($24)
71072		 lhu   $7,0x00($23)
71073		 addiu $23,$23,2
71074		 seb   $6,$7
71075		 or    $25,$0,$7
71076		 srl   $7,$7,12
71077		 andi  $25,$25,0x0800
71078		 sll   $7,$7,2
71079		 addu  $7,$7,$21
71080		 bne   $25,$0,0f
71081		 lw    $25,0x00($7)      	 # Delay slot
71082		 seh   $25,$25
71083	0:
71084		 addu  $25,$14,$25
71085		 addu  $14,$25,$6
71086		 lw    $25,0x80($21)
71087		 sw    $15,m68k_ICount
71088		 sw    $14,0x44($29)
71089		 or    $4,$0,$14
71090		 jalr  $25
71091		 sw    $23,0x4C($21)    	 # Delay slot
71092		 lw    $14,0x44($29)
71093		 lw    $15,m68k_ICount
71094		 andi  $9,$20,0x01
71095		 srl   $20,$2,15        	 # Set X
71096		 sll   $2,$2,1
71097		 or    $2,$2,$9
71098		 or    $16,$0,$20       	 # Copy X to Carry
71099		 andi  $2,$2,0xffff
71100		 and   $17,$0,$0        	 # Clear Overflow
71101		 srl   $19,$2,15        	 # Set Sign
71102		 sltiu $18,$2,1         	 # Set Zero
71103		 lw    $25,0x8C($21)
71104		 sw    $15,m68k_ICount
71105		 or    $5,$0,$2
71106		 or    $4,$0,$14
71107		 jalr  $25
71108		 sw    $23,0x4C($21)    	 # Delay slot
71109		 lw    $15,m68k_ICount
71110		 addiu $15,$15,-18
71111		 bgez  $15,3f
71112		 lhu   $24,0x00($23)    	 # Delay slot
71113		 j     MainExit
71114	3:
71115		 sll   $7,$24,2         	 # Delay slot
71116		 addu  $7,$7,$30
71117		 lw    $7,0x00($7)
71118		 jr    $7
71119		 nop                    	 # Delay slot
71120
71121OP0_e5f8:				#:
71122		 addiu $23,$23,2
71123
71124		 lh    $14,0x00($23)
71125		 addiu $23,$23,2
71126		 lw    $25,0x80($21)
71127		 sw    $15,m68k_ICount
71128		 sw    $14,0x44($29)
71129		 or    $4,$0,$14
71130		 jalr  $25
71131		 sw    $23,0x4C($21)    	 # Delay slot
71132		 lw    $14,0x44($29)
71133		 lw    $15,m68k_ICount
71134		 andi  $9,$20,0x01
71135		 srl   $20,$2,15        	 # Set X
71136		 sll   $2,$2,1
71137		 or    $2,$2,$9
71138		 or    $16,$0,$20       	 # Copy X to Carry
71139		 andi  $2,$2,0xffff
71140		 and   $17,$0,$0        	 # Clear Overflow
71141		 srl   $19,$2,15        	 # Set Sign
71142		 sltiu $18,$2,1         	 # Set Zero
71143		 lw    $25,0x8C($21)
71144		 sw    $15,m68k_ICount
71145		 or    $5,$0,$2
71146		 or    $4,$0,$14
71147		 jalr  $25
71148		 sw    $23,0x4C($21)    	 # Delay slot
71149		 lw    $15,m68k_ICount
71150		 addiu $15,$15,-16
71151		 bgez  $15,3f
71152		 lhu   $24,0x00($23)    	 # Delay slot
71153		 j     MainExit
71154	3:
71155		 sll   $7,$24,2         	 # Delay slot
71156		 addu  $7,$7,$30
71157		 lw    $7,0x00($7)
71158		 jr    $7
71159		 nop                    	 # Delay slot
71160
71161OP0_e5f9:				#:
71162		 addiu $23,$23,2
71163
71164		 lhu   $14,0x00($23)
71165		 lhu   $25,0x02($23)
71166		 sll   $14,$14,16
71167		 or    $14,$14,$25
71168		 addiu $23,$23,4
71169		 lw    $25,0x80($21)
71170		 sw    $15,m68k_ICount
71171		 sw    $14,0x44($29)
71172		 or    $4,$0,$14
71173		 jalr  $25
71174		 sw    $23,0x4C($21)    	 # Delay slot
71175		 lw    $14,0x44($29)
71176		 lw    $15,m68k_ICount
71177		 andi  $9,$20,0x01
71178		 srl   $20,$2,15        	 # Set X
71179		 sll   $2,$2,1
71180		 or    $2,$2,$9
71181		 or    $16,$0,$20       	 # Copy X to Carry
71182		 andi  $2,$2,0xffff
71183		 and   $17,$0,$0        	 # Clear Overflow
71184		 srl   $19,$2,15        	 # Set Sign
71185		 sltiu $18,$2,1         	 # Set Zero
71186		 lw    $25,0x8C($21)
71187		 sw    $15,m68k_ICount
71188		 or    $5,$0,$2
71189		 or    $4,$0,$14
71190		 jalr  $25
71191		 sw    $23,0x4C($21)    	 # Delay slot
71192		 lw    $15,m68k_ICount
71193		 addiu $15,$15,-20
71194		 bgez  $15,3f
71195		 lhu   $24,0x00($23)    	 # Delay slot
71196		 j     MainExit
71197	3:
71198		 sll   $7,$24,2         	 # Delay slot
71199		 addu  $7,$7,$30
71200		 lw    $7,0x00($7)
71201		 jr    $7
71202		 nop                    	 # Delay slot
71203
71204OP0_e008:				#:
71205		 addiu $23,$23,2
71206
71207		 andi  $8,$24,0x07
71208		 srl   $24,$24,9
71209		 addiu $24,$24,-1       	 # Move range down
71210		 andi  $24,$24,0x07     	 # Mask out lower bits
71211		 addiu $24,$24,1        	 # correct range
71212		 sll   $25,$24,1
71213		 subu  $15,$15,$25
71214		 sll   $8,$8,2
71215		 addu  $8,$8,$21
71216		 lbu   $2,0x00($8)
71217		 andi  $9,$24,0x20
71218		 addiu $10,$24,-1
71219		 andi  $11,$10,0x20
71220		 srlv  $16,$2,$10
71221		 andi  $16,$16,0x01     	 # Set Carry
71222		 srlv  $2,$2,$24
71223		 andi  $2,$2,0xFF
71224		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71225		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71226		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71227		 and   $17,$0,$0        	 # Clear Overflow
71228		 srl   $19,$2,7        	 # Set Sign
71229		 sltiu $18,$2,1         	 # Set Zero
71230		 movn  $20,$16,$24      	 # Set X if not shift by 0
71231		 sb    $2,0x00($8)
71232		 addiu $15,$15,-6
71233		 bgez  $15,3f
71234		 lhu   $24,0x00($23)    	 # Delay slot
71235		 j     MainExit
71236	3:
71237		 sll   $7,$24,2         	 # Delay slot
71238		 addu  $7,$7,$30
71239		 lw    $7,0x00($7)
71240		 jr    $7
71241		 nop                    	 # Delay slot
71242
71243OP0_e028:				#:
71244		 addiu $23,$23,2
71245
71246		 andi  $8,$24,0x07
71247		 srl   $24,$24,7
71248		 andi  $24,$24,0x1C
71249		 addu  $24,$24,$21
71250		 lw    $24,0x00($24)
71251		 andi  $24,$24,0x3F
71252		 sll   $25,$24,1
71253		 subu  $15,$15,$25
71254		 sll   $8,$8,2
71255		 addu  $8,$8,$21
71256		 lbu   $2,0x00($8)
71257		 andi  $9,$24,0x20
71258		 addiu $10,$24,-1
71259		 andi  $11,$10,0x20
71260		 srlv  $16,$2,$10
71261		 andi  $16,$16,0x01     	 # Set Carry
71262		 srlv  $2,$2,$24
71263		 andi  $2,$2,0xFF
71264		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71265		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71266		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71267		 and   $17,$0,$0        	 # Clear Overflow
71268		 srl   $19,$2,7        	 # Set Sign
71269		 sltiu $18,$2,1         	 # Set Zero
71270		 movn  $20,$16,$24      	 # Set X if not shift by 0
71271		 sb    $2,0x00($8)
71272		 addiu $15,$15,-6
71273		 bgez  $15,3f
71274		 lhu   $24,0x00($23)    	 # Delay slot
71275		 j     MainExit
71276	3:
71277		 sll   $7,$24,2         	 # Delay slot
71278		 addu  $7,$7,$30
71279		 lw    $7,0x00($7)
71280		 jr    $7
71281		 nop                    	 # Delay slot
71282
71283OP0_e048:				#:
71284		 addiu $23,$23,2
71285
71286		 andi  $8,$24,0x07
71287		 srl   $24,$24,9
71288		 addiu $24,$24,-1       	 # Move range down
71289		 andi  $24,$24,0x07     	 # Mask out lower bits
71290		 addiu $24,$24,1        	 # correct range
71291		 sll   $25,$24,1
71292		 subu  $15,$15,$25
71293		 sll   $8,$8,2
71294		 addu  $8,$8,$21
71295		 lhu   $2,0x00($8)
71296		 andi  $9,$24,0x20
71297		 addiu $10,$24,-1
71298		 andi  $11,$10,0x20
71299		 srlv  $16,$2,$10
71300		 andi  $16,$16,0x01     	 # Set Carry
71301		 srlv  $2,$2,$24
71302		 andi  $2,$2,0xFFFF
71303		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71304		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71305		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71306		 and   $17,$0,$0        	 # Clear Overflow
71307		 srl   $19,$2,15        	 # Set Sign
71308		 sltiu $18,$2,1         	 # Set Zero
71309		 movn  $20,$16,$24      	 # Set X if not shift by 0
71310		 sh    $2,0x00($8)
71311		 addiu $15,$15,-6
71312		 bgez  $15,3f
71313		 lhu   $24,0x00($23)    	 # Delay slot
71314		 j     MainExit
71315	3:
71316		 sll   $7,$24,2         	 # Delay slot
71317		 addu  $7,$7,$30
71318		 lw    $7,0x00($7)
71319		 jr    $7
71320		 nop                    	 # Delay slot
71321
71322OP0_e068:				#:
71323		 addiu $23,$23,2
71324
71325		 andi  $8,$24,0x07
71326		 srl   $24,$24,7
71327		 andi  $24,$24,0x1C
71328		 addu  $24,$24,$21
71329		 lw    $24,0x00($24)
71330		 andi  $24,$24,0x3F
71331		 sll   $25,$24,1
71332		 subu  $15,$15,$25
71333		 sll   $8,$8,2
71334		 addu  $8,$8,$21
71335		 lhu   $2,0x00($8)
71336		 andi  $9,$24,0x20
71337		 addiu $10,$24,-1
71338		 andi  $11,$10,0x20
71339		 srlv  $16,$2,$10
71340		 andi  $16,$16,0x01     	 # Set Carry
71341		 srlv  $2,$2,$24
71342		 andi  $2,$2,0xFFFF
71343		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71344		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71345		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71346		 and   $17,$0,$0        	 # Clear Overflow
71347		 srl   $19,$2,15        	 # Set Sign
71348		 sltiu $18,$2,1         	 # Set Zero
71349		 movn  $20,$16,$24      	 # Set X if not shift by 0
71350		 sh    $2,0x00($8)
71351		 addiu $15,$15,-6
71352		 bgez  $15,3f
71353		 lhu   $24,0x00($23)    	 # Delay slot
71354		 j     MainExit
71355	3:
71356		 sll   $7,$24,2         	 # Delay slot
71357		 addu  $7,$7,$30
71358		 lw    $7,0x00($7)
71359		 jr    $7
71360		 nop                    	 # Delay slot
71361
71362OP0_e088:				#:
71363		 addiu $23,$23,2
71364
71365		 andi  $8,$24,0x07
71366		 srl   $24,$24,9
71367		 addiu $24,$24,-1       	 # Move range down
71368		 andi  $24,$24,0x07     	 # Mask out lower bits
71369		 addiu $24,$24,1        	 # correct range
71370		 sll   $25,$24,1
71371		 subu  $15,$15,$25
71372		 sll   $8,$8,2
71373		 addu  $8,$8,$21
71374		 lw    $2,0x00($8)
71375		 andi  $9,$24,0x20
71376		 addiu $10,$24,-1
71377		 andi  $11,$10,0x20
71378		 srlv  $16,$2,$10
71379		 andi  $16,$16,0x01     	 # Set Carry
71380		 srlv  $2,$2,$24
71381		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71382		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71383		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71384		 and   $17,$0,$0        	 # Clear Overflow
71385		 slt   $19,$2,$0        	 # Set Sign
71386		 sltiu $18,$2,1         	 # Set Zero
71387		 movn  $20,$16,$24      	 # Set X if not shift by 0
71388		 sw    $2,0x00($8)
71389		 addiu $15,$15,-8
71390		 bgez  $15,3f
71391		 lhu   $24,0x00($23)    	 # Delay slot
71392		 j     MainExit
71393	3:
71394		 sll   $7,$24,2         	 # Delay slot
71395		 addu  $7,$7,$30
71396		 lw    $7,0x00($7)
71397		 jr    $7
71398		 nop                    	 # Delay slot
71399
71400OP0_e0a8:				#:
71401		 addiu $23,$23,2
71402
71403		 andi  $8,$24,0x07
71404		 srl   $24,$24,7
71405		 andi  $24,$24,0x1C
71406		 addu  $24,$24,$21
71407		 lw    $24,0x00($24)
71408		 andi  $24,$24,0x3F
71409		 sll   $25,$24,1
71410		 subu  $15,$15,$25
71411		 sll   $8,$8,2
71412		 addu  $8,$8,$21
71413		 lw    $2,0x00($8)
71414		 andi  $9,$24,0x20
71415		 addiu $10,$24,-1
71416		 andi  $11,$10,0x20
71417		 srlv  $16,$2,$10
71418		 andi  $16,$16,0x01     	 # Set Carry
71419		 srlv  $2,$2,$24
71420		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71421		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71422		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71423		 and   $17,$0,$0        	 # Clear Overflow
71424		 slt   $19,$2,$0        	 # Set Sign
71425		 sltiu $18,$2,1         	 # Set Zero
71426		 movn  $20,$16,$24      	 # Set X if not shift by 0
71427		 sw    $2,0x00($8)
71428		 addiu $15,$15,-8
71429		 bgez  $15,3f
71430		 lhu   $24,0x00($23)    	 # Delay slot
71431		 j     MainExit
71432	3:
71433		 sll   $7,$24,2         	 # Delay slot
71434		 addu  $7,$7,$30
71435		 lw    $7,0x00($7)
71436		 jr    $7
71437		 nop                    	 # Delay slot
71438
71439OP0_e108:				#:
71440		 addiu $23,$23,2
71441
71442		 andi  $8,$24,0x07
71443		 srl   $24,$24,9
71444		 addiu $24,$24,-1       	 # Move range down
71445		 andi  $24,$24,0x07     	 # Mask out lower bits
71446		 addiu $24,$24,1        	 # correct range
71447		 sll   $25,$24,1
71448		 subu  $15,$15,$25
71449		 sll   $8,$8,2
71450		 addu  $8,$8,$21
71451		 lbu   $2,0x00($8)
71452		 andi  $9,$24,0x20
71453		 addiu $10,$24,-1
71454		 andi  $11,$10,0x20
71455		 sll   $16,$2,24
71456		 sllv  $16,$16,$10
71457		 srl   $16,$16,31       	 # Set Carry
71458		 sllv  $2,$2,$24
71459		 andi  $2,$2,0xFF
71460		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71461		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71462		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71463		 and   $17,$0,$0        	 # Clear Overflow
71464		 srl   $19,$2,7        	 # Set Sign
71465		 sltiu $18,$2,1         	 # Set Zero
71466		 movn  $20,$16,$24      	 # Set X if not shift by 0
71467		 sb    $2,0x00($8)
71468		 addiu $15,$15,-6
71469		 bgez  $15,3f
71470		 lhu   $24,0x00($23)    	 # Delay slot
71471		 j     MainExit
71472	3:
71473		 sll   $7,$24,2         	 # Delay slot
71474		 addu  $7,$7,$30
71475		 lw    $7,0x00($7)
71476		 jr    $7
71477		 nop                    	 # Delay slot
71478
71479OP0_e128:				#:
71480		 addiu $23,$23,2
71481
71482		 andi  $8,$24,0x07
71483		 srl   $24,$24,7
71484		 andi  $24,$24,0x1C
71485		 addu  $24,$24,$21
71486		 lw    $24,0x00($24)
71487		 andi  $24,$24,0x3F
71488		 sll   $25,$24,1
71489		 subu  $15,$15,$25
71490		 sll   $8,$8,2
71491		 addu  $8,$8,$21
71492		 lbu   $2,0x00($8)
71493		 andi  $9,$24,0x20
71494		 addiu $10,$24,-1
71495		 andi  $11,$10,0x20
71496		 sll   $16,$2,24
71497		 sllv  $16,$16,$10
71498		 srl   $16,$16,31       	 # Set Carry
71499		 sllv  $2,$2,$24
71500		 andi  $2,$2,0xFF
71501		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71502		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71503		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71504		 and   $17,$0,$0        	 # Clear Overflow
71505		 srl   $19,$2,7        	 # Set Sign
71506		 sltiu $18,$2,1         	 # Set Zero
71507		 movn  $20,$16,$24      	 # Set X if not shift by 0
71508		 sb    $2,0x00($8)
71509		 addiu $15,$15,-6
71510		 bgez  $15,3f
71511		 lhu   $24,0x00($23)    	 # Delay slot
71512		 j     MainExit
71513	3:
71514		 sll   $7,$24,2         	 # Delay slot
71515		 addu  $7,$7,$30
71516		 lw    $7,0x00($7)
71517		 jr    $7
71518		 nop                    	 # Delay slot
71519
71520OP0_e148:				#:
71521		 addiu $23,$23,2
71522
71523		 andi  $8,$24,0x07
71524		 srl   $24,$24,9
71525		 addiu $24,$24,-1       	 # Move range down
71526		 andi  $24,$24,0x07     	 # Mask out lower bits
71527		 addiu $24,$24,1        	 # correct range
71528		 sll   $25,$24,1
71529		 subu  $15,$15,$25
71530		 sll   $8,$8,2
71531		 addu  $8,$8,$21
71532		 lhu   $2,0x00($8)
71533		 andi  $9,$24,0x20
71534		 addiu $10,$24,-1
71535		 andi  $11,$10,0x20
71536		 sll   $16,$2,16
71537		 sllv  $16,$16,$10
71538		 srl   $16,$16,31       	 # Set Carry
71539		 sllv  $2,$2,$24
71540		 andi  $2,$2,0xFFFF
71541		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71542		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71543		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71544		 and   $17,$0,$0        	 # Clear Overflow
71545		 srl   $19,$2,15        	 # Set Sign
71546		 sltiu $18,$2,1         	 # Set Zero
71547		 movn  $20,$16,$24      	 # Set X if not shift by 0
71548		 sh    $2,0x00($8)
71549		 addiu $15,$15,-6
71550		 bgez  $15,3f
71551		 lhu   $24,0x00($23)    	 # Delay slot
71552		 j     MainExit
71553	3:
71554		 sll   $7,$24,2         	 # Delay slot
71555		 addu  $7,$7,$30
71556		 lw    $7,0x00($7)
71557		 jr    $7
71558		 nop                    	 # Delay slot
71559
71560OP0_e168:				#:
71561		 addiu $23,$23,2
71562
71563		 andi  $8,$24,0x07
71564		 srl   $24,$24,7
71565		 andi  $24,$24,0x1C
71566		 addu  $24,$24,$21
71567		 lw    $24,0x00($24)
71568		 andi  $24,$24,0x3F
71569		 sll   $25,$24,1
71570		 subu  $15,$15,$25
71571		 sll   $8,$8,2
71572		 addu  $8,$8,$21
71573		 lhu   $2,0x00($8)
71574		 andi  $9,$24,0x20
71575		 addiu $10,$24,-1
71576		 andi  $11,$10,0x20
71577		 sll   $16,$2,16
71578		 sllv  $16,$16,$10
71579		 srl   $16,$16,31       	 # Set Carry
71580		 sllv  $2,$2,$24
71581		 andi  $2,$2,0xFFFF
71582		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71583		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71584		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71585		 and   $17,$0,$0        	 # Clear Overflow
71586		 srl   $19,$2,15        	 # Set Sign
71587		 sltiu $18,$2,1         	 # Set Zero
71588		 movn  $20,$16,$24      	 # Set X if not shift by 0
71589		 sh    $2,0x00($8)
71590		 addiu $15,$15,-6
71591		 bgez  $15,3f
71592		 lhu   $24,0x00($23)    	 # Delay slot
71593		 j     MainExit
71594	3:
71595		 sll   $7,$24,2         	 # Delay slot
71596		 addu  $7,$7,$30
71597		 lw    $7,0x00($7)
71598		 jr    $7
71599		 nop                    	 # Delay slot
71600
71601OP0_e188:				#:
71602		 addiu $23,$23,2
71603
71604		 andi  $8,$24,0x07
71605		 srl   $24,$24,9
71606		 addiu $24,$24,-1       	 # Move range down
71607		 andi  $24,$24,0x07     	 # Mask out lower bits
71608		 addiu $24,$24,1        	 # correct range
71609		 sll   $25,$24,1
71610		 subu  $15,$15,$25
71611		 sll   $8,$8,2
71612		 addu  $8,$8,$21
71613		 lw    $2,0x00($8)
71614		 andi  $9,$24,0x20
71615		 addiu $10,$24,-1
71616		 andi  $11,$10,0x20
71617		 sllv  $16,$16,$10
71618		 srl   $16,$16,31       	 # Set Carry
71619		 sllv  $2,$2,$24
71620		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71621		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71622		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71623		 and   $17,$0,$0        	 # Clear Overflow
71624		 slt   $19,$2,$0        	 # Set Sign
71625		 sltiu $18,$2,1         	 # Set Zero
71626		 movn  $20,$16,$24      	 # Set X if not shift by 0
71627		 sw    $2,0x00($8)
71628		 addiu $15,$15,-8
71629		 bgez  $15,3f
71630		 lhu   $24,0x00($23)    	 # Delay slot
71631		 j     MainExit
71632	3:
71633		 sll   $7,$24,2         	 # Delay slot
71634		 addu  $7,$7,$30
71635		 lw    $7,0x00($7)
71636		 jr    $7
71637		 nop                    	 # Delay slot
71638
71639OP0_e1a8:				#:
71640		 addiu $23,$23,2
71641
71642		 andi  $8,$24,0x07
71643		 srl   $24,$24,7
71644		 andi  $24,$24,0x1C
71645		 addu  $24,$24,$21
71646		 lw    $24,0x00($24)
71647		 andi  $24,$24,0x3F
71648		 sll   $25,$24,1
71649		 subu  $15,$15,$25
71650		 sll   $8,$8,2
71651		 addu  $8,$8,$21
71652		 lw    $2,0x00($8)
71653		 andi  $9,$24,0x20
71654		 addiu $10,$24,-1
71655		 andi  $11,$10,0x20
71656		 sllv  $16,$16,$10
71657		 srl   $16,$16,31       	 # Set Carry
71658		 sllv  $2,$2,$24
71659		 movn  $2,$0,$9         	 # Return 0 if shift by 32-63
71660		 movn  $16,$0,$11       	 # Clear Carry if shift by >32
71661		 movz  $16,$0,$24       	 # Clear Carry if shift by 0
71662		 and   $17,$0,$0        	 # Clear Overflow
71663		 slt   $19,$2,$0        	 # Set Sign
71664		 sltiu $18,$2,1         	 # Set Zero
71665		 movn  $20,$16,$24      	 # Set X if not shift by 0
71666		 sw    $2,0x00($8)
71667		 addiu $15,$15,-8
71668		 bgez  $15,3f
71669		 lhu   $24,0x00($23)    	 # Delay slot
71670		 j     MainExit
71671	3:
71672		 sll   $7,$24,2         	 # Delay slot
71673		 addu  $7,$7,$30
71674		 lw    $7,0x00($7)
71675		 jr    $7
71676		 nop                    	 # Delay slot
71677
71678OP0_e2d0:				#:
71679		 addiu $23,$23,2
71680
71681		 andi  $24,$24,0x07
71682		 sll   $24,$24,2
71683		 addu  $24,$24,$21
71684		 lw    $14,0x20($24)
71685		 lw    $25,0x80($21)
71686		 sw    $15,m68k_ICount
71687		 sw    $14,0x44($29)
71688		 or    $4,$0,$14
71689		 jalr  $25
71690		 sw    $23,0x4C($21)    	 # Delay slot
71691		 lw    $14,0x44($29)
71692		 lw    $15,m68k_ICount
71693		 andi  $16,$2,0x01      	 # Set Carry
71694		 srl   $2,$2,1
71695		 andi  $2,$2,0xffff
71696		 and   $17,$0,$0        	 # Clear Overflow
71697		 srl   $19,$2,15        	 # Set Sign
71698		 sltiu $18,$2,1         	 # Set Zero
71699		 movn  $20,$16,$24      	 # Set X if not shift by 0
71700		 lw    $25,0x8C($21)
71701		 sw    $15,m68k_ICount
71702		 or    $5,$0,$2
71703		 or    $4,$0,$14
71704		 jalr  $25
71705		 sw    $23,0x4C($21)    	 # Delay slot
71706		 lw    $15,m68k_ICount
71707		 addiu $15,$15,-12
71708		 bgez  $15,3f
71709		 lhu   $24,0x00($23)    	 # Delay slot
71710		 j     MainExit
71711	3:
71712		 sll   $7,$24,2         	 # Delay slot
71713		 addu  $7,$7,$30
71714		 lw    $7,0x00($7)
71715		 jr    $7
71716		 nop                    	 # Delay slot
71717
71718OP0_e2d8:				#:
71719		 addiu $23,$23,2
71720
71721		 andi  $24,$24,0x07
71722		 sll   $24,$24,2
71723		 addu  $24,$24,$21
71724		 lw    $14,0x20($24)
71725		 addiu $25,$14,2
71726		 sw    $25,0x20($24)
71727		 lw    $25,0x80($21)
71728		 sw    $15,m68k_ICount
71729		 sw    $14,0x44($29)
71730		 or    $4,$0,$14
71731		 jalr  $25
71732		 sw    $23,0x4C($21)    	 # Delay slot
71733		 lw    $14,0x44($29)
71734		 lw    $15,m68k_ICount
71735		 andi  $16,$2,0x01      	 # Set Carry
71736		 srl   $2,$2,1
71737		 andi  $2,$2,0xffff
71738		 and   $17,$0,$0        	 # Clear Overflow
71739		 srl   $19,$2,15        	 # Set Sign
71740		 sltiu $18,$2,1         	 # Set Zero
71741		 movn  $20,$16,$24      	 # Set X if not shift by 0
71742		 lw    $25,0x8C($21)
71743		 sw    $15,m68k_ICount
71744		 or    $5,$0,$2
71745		 or    $4,$0,$14
71746		 jalr  $25
71747		 sw    $23,0x4C($21)    	 # Delay slot
71748		 lw    $15,m68k_ICount
71749		 addiu $15,$15,-12
71750		 bgez  $15,3f
71751		 lhu   $24,0x00($23)    	 # Delay slot
71752		 j     MainExit
71753	3:
71754		 sll   $7,$24,2         	 # Delay slot
71755		 addu  $7,$7,$30
71756		 lw    $7,0x00($7)
71757		 jr    $7
71758		 nop                    	 # Delay slot
71759
71760OP0_e2e0:				#:
71761		 addiu $23,$23,2
71762
71763		 andi  $24,$24,0x07
71764		 sll   $24,$24,2
71765		 addu  $24,$24,$21
71766		 lw    $14,0x20($24)
71767		 addiu $14,$14,-2
71768		 sw    $14,0x20($24)
71769		 lw    $25,0x80($21)
71770		 sw    $15,m68k_ICount
71771		 sw    $14,0x44($29)
71772		 or    $4,$0,$14
71773		 jalr  $25
71774		 sw    $23,0x4C($21)    	 # Delay slot
71775		 lw    $14,0x44($29)
71776		 lw    $15,m68k_ICount
71777		 andi  $16,$2,0x01      	 # Set Carry
71778		 srl   $2,$2,1
71779		 andi  $2,$2,0xffff
71780		 and   $17,$0,$0        	 # Clear Overflow
71781		 srl   $19,$2,15        	 # Set Sign
71782		 sltiu $18,$2,1         	 # Set Zero
71783		 movn  $20,$16,$24      	 # Set X if not shift by 0
71784		 lw    $25,0x8C($21)
71785		 sw    $15,m68k_ICount
71786		 or    $5,$0,$2
71787		 or    $4,$0,$14
71788		 jalr  $25
71789		 sw    $23,0x4C($21)    	 # Delay slot
71790		 lw    $15,m68k_ICount
71791		 addiu $15,$15,-14
71792		 bgez  $15,3f
71793		 lhu   $24,0x00($23)    	 # Delay slot
71794		 j     MainExit
71795	3:
71796		 sll   $7,$24,2         	 # Delay slot
71797		 addu  $7,$7,$30
71798		 lw    $7,0x00($7)
71799		 jr    $7
71800		 nop                    	 # Delay slot
71801
71802OP0_e2e8:				#:
71803		 addiu $23,$23,2
71804
71805		 andi  $24,$24,0x07
71806		 lh    $7,0x00($23)
71807		 sll   $24,$24,2
71808		 addu  $24,$24,$21
71809		 lw    $14,0x20($24)
71810		 addiu $23,$23,2
71811		 addu  $14,$14,$7
71812		 lw    $25,0x80($21)
71813		 sw    $15,m68k_ICount
71814		 sw    $14,0x44($29)
71815		 or    $4,$0,$14
71816		 jalr  $25
71817		 sw    $23,0x4C($21)    	 # Delay slot
71818		 lw    $14,0x44($29)
71819		 lw    $15,m68k_ICount
71820		 andi  $16,$2,0x01      	 # Set Carry
71821		 srl   $2,$2,1
71822		 andi  $2,$2,0xffff
71823		 and   $17,$0,$0        	 # Clear Overflow
71824		 srl   $19,$2,15        	 # Set Sign
71825		 sltiu $18,$2,1         	 # Set Zero
71826		 movn  $20,$16,$24      	 # Set X if not shift by 0
71827		 lw    $25,0x8C($21)
71828		 sw    $15,m68k_ICount
71829		 or    $5,$0,$2
71830		 or    $4,$0,$14
71831		 jalr  $25
71832		 sw    $23,0x4C($21)    	 # Delay slot
71833		 lw    $15,m68k_ICount
71834		 addiu $15,$15,-16
71835		 bgez  $15,3f
71836		 lhu   $24,0x00($23)    	 # Delay slot
71837		 j     MainExit
71838	3:
71839		 sll   $7,$24,2         	 # Delay slot
71840		 addu  $7,$7,$30
71841		 lw    $7,0x00($7)
71842		 jr    $7
71843		 nop                    	 # Delay slot
71844
71845OP0_e2f0:				#:
71846		 addiu $23,$23,2
71847
71848		 andi  $24,$24,0x07
71849		 sll   $24,$24,2
71850		 addu  $24,$24,$21
71851		 lw    $14,0x20($24)
71852		 lhu   $7,0x00($23)
71853		 addiu $23,$23,2
71854		 seb   $6,$7
71855		 or    $25,$0,$7
71856		 srl   $7,$7,12
71857		 andi  $25,$25,0x0800
71858		 sll   $7,$7,2
71859		 addu  $7,$7,$21
71860		 bne   $25,$0,0f
71861		 lw    $25,0x00($7)      	 # Delay slot
71862		 seh   $25,$25
71863	0:
71864		 addu  $25,$14,$25
71865		 addu  $14,$25,$6
71866		 lw    $25,0x80($21)
71867		 sw    $15,m68k_ICount
71868		 sw    $14,0x44($29)
71869		 or    $4,$0,$14
71870		 jalr  $25
71871		 sw    $23,0x4C($21)    	 # Delay slot
71872		 lw    $14,0x44($29)
71873		 lw    $15,m68k_ICount
71874		 andi  $16,$2,0x01      	 # Set Carry
71875		 srl   $2,$2,1
71876		 andi  $2,$2,0xffff
71877		 and   $17,$0,$0        	 # Clear Overflow
71878		 srl   $19,$2,15        	 # Set Sign
71879		 sltiu $18,$2,1         	 # Set Zero
71880		 movn  $20,$16,$24      	 # Set X if not shift by 0
71881		 lw    $25,0x8C($21)
71882		 sw    $15,m68k_ICount
71883		 or    $5,$0,$2
71884		 or    $4,$0,$14
71885		 jalr  $25
71886		 sw    $23,0x4C($21)    	 # Delay slot
71887		 lw    $15,m68k_ICount
71888		 addiu $15,$15,-18
71889		 bgez  $15,3f
71890		 lhu   $24,0x00($23)    	 # Delay slot
71891		 j     MainExit
71892	3:
71893		 sll   $7,$24,2         	 # Delay slot
71894		 addu  $7,$7,$30
71895		 lw    $7,0x00($7)
71896		 jr    $7
71897		 nop                    	 # Delay slot
71898
71899OP0_e2f8:				#:
71900		 addiu $23,$23,2
71901
71902		 lh    $14,0x00($23)
71903		 addiu $23,$23,2
71904		 lw    $25,0x80($21)
71905		 sw    $15,m68k_ICount
71906		 sw    $14,0x44($29)
71907		 or    $4,$0,$14
71908		 jalr  $25
71909		 sw    $23,0x4C($21)    	 # Delay slot
71910		 lw    $14,0x44($29)
71911		 lw    $15,m68k_ICount
71912		 andi  $16,$2,0x01      	 # Set Carry
71913		 srl   $2,$2,1
71914		 andi  $2,$2,0xffff
71915		 and   $17,$0,$0        	 # Clear Overflow
71916		 srl   $19,$2,15        	 # Set Sign
71917		 sltiu $18,$2,1         	 # Set Zero
71918		 movn  $20,$16,$24      	 # Set X if not shift by 0
71919		 lw    $25,0x8C($21)
71920		 sw    $15,m68k_ICount
71921		 or    $5,$0,$2
71922		 or    $4,$0,$14
71923		 jalr  $25
71924		 sw    $23,0x4C($21)    	 # Delay slot
71925		 lw    $15,m68k_ICount
71926		 addiu $15,$15,-16
71927		 bgez  $15,3f
71928		 lhu   $24,0x00($23)    	 # Delay slot
71929		 j     MainExit
71930	3:
71931		 sll   $7,$24,2         	 # Delay slot
71932		 addu  $7,$7,$30
71933		 lw    $7,0x00($7)
71934		 jr    $7
71935		 nop                    	 # Delay slot
71936
71937OP0_e2f9:				#:
71938		 addiu $23,$23,2
71939
71940		 lhu   $14,0x00($23)
71941		 lhu   $25,0x02($23)
71942		 sll   $14,$14,16
71943		 or    $14,$14,$25
71944		 addiu $23,$23,4
71945		 lw    $25,0x80($21)
71946		 sw    $15,m68k_ICount
71947		 sw    $14,0x44($29)
71948		 or    $4,$0,$14
71949		 jalr  $25
71950		 sw    $23,0x4C($21)    	 # Delay slot
71951		 lw    $14,0x44($29)
71952		 lw    $15,m68k_ICount
71953		 andi  $16,$2,0x01      	 # Set Carry
71954		 srl   $2,$2,1
71955		 andi  $2,$2,0xffff
71956		 and   $17,$0,$0        	 # Clear Overflow
71957		 srl   $19,$2,15        	 # Set Sign
71958		 sltiu $18,$2,1         	 # Set Zero
71959		 movn  $20,$16,$24      	 # Set X if not shift by 0
71960		 lw    $25,0x8C($21)
71961		 sw    $15,m68k_ICount
71962		 or    $5,$0,$2
71963		 or    $4,$0,$14
71964		 jalr  $25
71965		 sw    $23,0x4C($21)    	 # Delay slot
71966		 lw    $15,m68k_ICount
71967		 addiu $15,$15,-20
71968		 bgez  $15,3f
71969		 lhu   $24,0x00($23)    	 # Delay slot
71970		 j     MainExit
71971	3:
71972		 sll   $7,$24,2         	 # Delay slot
71973		 addu  $7,$7,$30
71974		 lw    $7,0x00($7)
71975		 jr    $7
71976		 nop                    	 # Delay slot
71977
71978OP0_e3d0:				#:
71979		 addiu $23,$23,2
71980
71981		 andi  $24,$24,0x07
71982		 sll   $24,$24,2
71983		 addu  $24,$24,$21
71984		 lw    $14,0x20($24)
71985		 lw    $25,0x80($21)
71986		 sw    $15,m68k_ICount
71987		 sw    $14,0x44($29)
71988		 or    $4,$0,$14
71989		 jalr  $25
71990		 sw    $23,0x4C($21)    	 # Delay slot
71991		 lw    $14,0x44($29)
71992		 lw    $15,m68k_ICount
71993		 srl   $16,$2,15        	 # Set Carry
71994		 sll   $2,$2,1
71995		 andi  $2,$2,0xffff
71996		 and   $17,$0,$0        	 # Clear Overflow
71997		 srl   $19,$2,15        	 # Set Sign
71998		 sltiu $18,$2,1         	 # Set Zero
71999		 movn  $20,$16,$24      	 # Set X if not shift by 0
72000		 lw    $25,0x8C($21)
72001		 sw    $15,m68k_ICount
72002		 or    $5,$0,$2
72003		 or    $4,$0,$14
72004		 jalr  $25
72005		 sw    $23,0x4C($21)    	 # Delay slot
72006		 lw    $15,m68k_ICount
72007		 addiu $15,$15,-12
72008		 bgez  $15,3f
72009		 lhu   $24,0x00($23)    	 # Delay slot
72010		 j     MainExit
72011	3:
72012		 sll   $7,$24,2         	 # Delay slot
72013		 addu  $7,$7,$30
72014		 lw    $7,0x00($7)
72015		 jr    $7
72016		 nop                    	 # Delay slot
72017
72018OP0_e3d8:				#:
72019		 addiu $23,$23,2
72020
72021		 andi  $24,$24,0x07
72022		 sll   $24,$24,2
72023		 addu  $24,$24,$21
72024		 lw    $14,0x20($24)
72025		 addiu $25,$14,2
72026		 sw    $25,0x20($24)
72027		 lw    $25,0x80($21)
72028		 sw    $15,m68k_ICount
72029		 sw    $14,0x44($29)
72030		 or    $4,$0,$14
72031		 jalr  $25
72032		 sw    $23,0x4C($21)    	 # Delay slot
72033		 lw    $14,0x44($29)
72034		 lw    $15,m68k_ICount
72035		 srl   $16,$2,15        	 # Set Carry
72036		 sll   $2,$2,1
72037		 andi  $2,$2,0xffff
72038		 and   $17,$0,$0        	 # Clear Overflow
72039		 srl   $19,$2,15        	 # Set Sign
72040		 sltiu $18,$2,1         	 # Set Zero
72041		 movn  $20,$16,$24      	 # Set X if not shift by 0
72042		 lw    $25,0x8C($21)
72043		 sw    $15,m68k_ICount
72044		 or    $5,$0,$2
72045		 or    $4,$0,$14
72046		 jalr  $25
72047		 sw    $23,0x4C($21)    	 # Delay slot
72048		 lw    $15,m68k_ICount
72049		 addiu $15,$15,-12
72050		 bgez  $15,3f
72051		 lhu   $24,0x00($23)    	 # Delay slot
72052		 j     MainExit
72053	3:
72054		 sll   $7,$24,2         	 # Delay slot
72055		 addu  $7,$7,$30
72056		 lw    $7,0x00($7)
72057		 jr    $7
72058		 nop                    	 # Delay slot
72059
72060OP0_e3e0:				#:
72061		 addiu $23,$23,2
72062
72063		 andi  $24,$24,0x07
72064		 sll   $24,$24,2
72065		 addu  $24,$24,$21
72066		 lw    $14,0x20($24)
72067		 addiu $14,$14,-2
72068		 sw    $14,0x20($24)
72069		 lw    $25,0x80($21)
72070		 sw    $15,m68k_ICount
72071		 sw    $14,0x44($29)
72072		 or    $4,$0,$14
72073		 jalr  $25
72074		 sw    $23,0x4C($21)    	 # Delay slot
72075		 lw    $14,0x44($29)
72076		 lw    $15,m68k_ICount
72077		 srl   $16,$2,15        	 # Set Carry
72078		 sll   $2,$2,1
72079		 andi  $2,$2,0xffff
72080		 and   $17,$0,$0        	 # Clear Overflow
72081		 srl   $19,$2,15        	 # Set Sign
72082		 sltiu $18,$2,1         	 # Set Zero
72083		 movn  $20,$16,$24      	 # Set X if not shift by 0
72084		 lw    $25,0x8C($21)
72085		 sw    $15,m68k_ICount
72086		 or    $5,$0,$2
72087		 or    $4,$0,$14
72088		 jalr  $25
72089		 sw    $23,0x4C($21)    	 # Delay slot
72090		 lw    $15,m68k_ICount
72091		 addiu $15,$15,-14
72092		 bgez  $15,3f
72093		 lhu   $24,0x00($23)    	 # Delay slot
72094		 j     MainExit
72095	3:
72096		 sll   $7,$24,2         	 # Delay slot
72097		 addu  $7,$7,$30
72098		 lw    $7,0x00($7)
72099		 jr    $7
72100		 nop                    	 # Delay slot
72101
72102OP0_e3e8:				#:
72103		 addiu $23,$23,2
72104
72105		 andi  $24,$24,0x07
72106		 lh    $7,0x00($23)
72107		 sll   $24,$24,2
72108		 addu  $24,$24,$21
72109		 lw    $14,0x20($24)
72110		 addiu $23,$23,2
72111		 addu  $14,$14,$7
72112		 lw    $25,0x80($21)
72113		 sw    $15,m68k_ICount
72114		 sw    $14,0x44($29)
72115		 or    $4,$0,$14
72116		 jalr  $25
72117		 sw    $23,0x4C($21)    	 # Delay slot
72118		 lw    $14,0x44($29)
72119		 lw    $15,m68k_ICount
72120		 srl   $16,$2,15        	 # Set Carry
72121		 sll   $2,$2,1
72122		 andi  $2,$2,0xffff
72123		 and   $17,$0,$0        	 # Clear Overflow
72124		 srl   $19,$2,15        	 # Set Sign
72125		 sltiu $18,$2,1         	 # Set Zero
72126		 movn  $20,$16,$24      	 # Set X if not shift by 0
72127		 lw    $25,0x8C($21)
72128		 sw    $15,m68k_ICount
72129		 or    $5,$0,$2
72130		 or    $4,$0,$14
72131		 jalr  $25
72132		 sw    $23,0x4C($21)    	 # Delay slot
72133		 lw    $15,m68k_ICount
72134		 addiu $15,$15,-16
72135		 bgez  $15,3f
72136		 lhu   $24,0x00($23)    	 # Delay slot
72137		 j     MainExit
72138	3:
72139		 sll   $7,$24,2         	 # Delay slot
72140		 addu  $7,$7,$30
72141		 lw    $7,0x00($7)
72142		 jr    $7
72143		 nop                    	 # Delay slot
72144
72145OP0_e3f0:				#:
72146		 addiu $23,$23,2
72147
72148		 andi  $24,$24,0x07
72149		 sll   $24,$24,2
72150		 addu  $24,$24,$21
72151		 lw    $14,0x20($24)
72152		 lhu   $7,0x00($23)
72153		 addiu $23,$23,2
72154		 seb   $6,$7
72155		 or    $25,$0,$7
72156		 srl   $7,$7,12
72157		 andi  $25,$25,0x0800
72158		 sll   $7,$7,2
72159		 addu  $7,$7,$21
72160		 bne   $25,$0,0f
72161		 lw    $25,0x00($7)      	 # Delay slot
72162		 seh   $25,$25
72163	0:
72164		 addu  $25,$14,$25
72165		 addu  $14,$25,$6
72166		 lw    $25,0x80($21)
72167		 sw    $15,m68k_ICount
72168		 sw    $14,0x44($29)
72169		 or    $4,$0,$14
72170		 jalr  $25
72171		 sw    $23,0x4C($21)    	 # Delay slot
72172		 lw    $14,0x44($29)
72173		 lw    $15,m68k_ICount
72174		 srl   $16,$2,15        	 # Set Carry
72175		 sll   $2,$2,1
72176		 andi  $2,$2,0xffff
72177		 and   $17,$0,$0        	 # Clear Overflow
72178		 srl   $19,$2,15        	 # Set Sign
72179		 sltiu $18,$2,1         	 # Set Zero
72180		 movn  $20,$16,$24      	 # Set X if not shift by 0
72181		 lw    $25,0x8C($21)
72182		 sw    $15,m68k_ICount
72183		 or    $5,$0,$2
72184		 or    $4,$0,$14
72185		 jalr  $25
72186		 sw    $23,0x4C($21)    	 # Delay slot
72187		 lw    $15,m68k_ICount
72188		 addiu $15,$15,-18
72189		 bgez  $15,3f
72190		 lhu   $24,0x00($23)    	 # Delay slot
72191		 j     MainExit
72192	3:
72193		 sll   $7,$24,2         	 # Delay slot
72194		 addu  $7,$7,$30
72195		 lw    $7,0x00($7)
72196		 jr    $7
72197		 nop                    	 # Delay slot
72198
72199OP0_e3f8:				#:
72200		 addiu $23,$23,2
72201
72202		 lh    $14,0x00($23)
72203		 addiu $23,$23,2
72204		 lw    $25,0x80($21)
72205		 sw    $15,m68k_ICount
72206		 sw    $14,0x44($29)
72207		 or    $4,$0,$14
72208		 jalr  $25
72209		 sw    $23,0x4C($21)    	 # Delay slot
72210		 lw    $14,0x44($29)
72211		 lw    $15,m68k_ICount
72212		 srl   $16,$2,15        	 # Set Carry
72213		 sll   $2,$2,1
72214		 andi  $2,$2,0xffff
72215		 and   $17,$0,$0        	 # Clear Overflow
72216		 srl   $19,$2,15        	 # Set Sign
72217		 sltiu $18,$2,1         	 # Set Zero
72218		 movn  $20,$16,$24      	 # Set X if not shift by 0
72219		 lw    $25,0x8C($21)
72220		 sw    $15,m68k_ICount
72221		 or    $5,$0,$2
72222		 or    $4,$0,$14
72223		 jalr  $25
72224		 sw    $23,0x4C($21)    	 # Delay slot
72225		 lw    $15,m68k_ICount
72226		 addiu $15,$15,-16
72227		 bgez  $15,3f
72228		 lhu   $24,0x00($23)    	 # Delay slot
72229		 j     MainExit
72230	3:
72231		 sll   $7,$24,2         	 # Delay slot
72232		 addu  $7,$7,$30
72233		 lw    $7,0x00($7)
72234		 jr    $7
72235		 nop                    	 # Delay slot
72236
72237OP0_e3f9:				#:
72238		 addiu $23,$23,2
72239
72240		 lhu   $14,0x00($23)
72241		 lhu   $25,0x02($23)
72242		 sll   $14,$14,16
72243		 or    $14,$14,$25
72244		 addiu $23,$23,4
72245		 lw    $25,0x80($21)
72246		 sw    $15,m68k_ICount
72247		 sw    $14,0x44($29)
72248		 or    $4,$0,$14
72249		 jalr  $25
72250		 sw    $23,0x4C($21)    	 # Delay slot
72251		 lw    $14,0x44($29)
72252		 lw    $15,m68k_ICount
72253		 srl   $16,$2,15        	 # Set Carry
72254		 sll   $2,$2,1
72255		 andi  $2,$2,0xffff
72256		 and   $17,$0,$0        	 # Clear Overflow
72257		 srl   $19,$2,15        	 # Set Sign
72258		 sltiu $18,$2,1         	 # Set Zero
72259		 movn  $20,$16,$24      	 # Set X if not shift by 0
72260		 lw    $25,0x8C($21)
72261		 sw    $15,m68k_ICount
72262		 or    $5,$0,$2
72263		 or    $4,$0,$14
72264		 jalr  $25
72265		 sw    $23,0x4C($21)    	 # Delay slot
72266		 lw    $15,m68k_ICount
72267		 addiu $15,$15,-20
72268		 bgez  $15,3f
72269		 lhu   $24,0x00($23)    	 # Delay slot
72270		 j     MainExit
72271	3:
72272		 sll   $7,$24,2         	 # Delay slot
72273		 addu  $7,$7,$30
72274		 lw    $7,0x00($7)
72275		 jr    $7
72276		 nop                    	 # Delay slot
72277
72278OP0_e018:				#:
72279		 addiu $23,$23,2
72280
72281		 andi  $8,$24,0x07
72282		 srl   $24,$24,9
72283		 addiu $24,$24,-1       	 # Move range down
72284		 andi  $24,$24,0x07     	 # Mask out lower bits
72285		 addiu $24,$24,1        	 # correct range
72286		 sll   $8,$8,2
72287		 addu  $8,$8,$21
72288		 lbu   $2,0x00($8)
72289		 beq   $24,$0,9f
72290		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72291		 sll   $25,$24,1
72292		 subu  $15,$15,$25
72293		 andi  $24,$24,0x07
72294		 subu  $25,$0,$24
72295		 andi  $25,$25,0x07
72296		 sllv  $25,$2,$25
72297		 srlv  $2,$2,$24
72298		 or    $2,$2,$25
72299		 srl   $16,$2,7        	 # Set Carry
72300	9:
72301		 andi  $2,$2,0xFF
72302		 and   $17,$0,$0        	 # Clear Overflow
72303		 sltiu $18,$2,1         	 # Set Zero
72304		 srl   $19,$2,7        	 # Set Sign
72305		 sb    $2,0x00($8)
72306		 addiu $15,$15,-6
72307		 bgez  $15,3f
72308		 lhu   $24,0x00($23)    	 # Delay slot
72309		 j     MainExit
72310	3:
72311		 sll   $7,$24,2         	 # Delay slot
72312		 addu  $7,$7,$30
72313		 lw    $7,0x00($7)
72314		 jr    $7
72315		 nop                    	 # Delay slot
72316
72317OP0_e038:				#:
72318		 addiu $23,$23,2
72319
72320		 andi  $8,$24,0x07
72321		 srl   $24,$24,7
72322		 andi  $24,$24,0x1C
72323		 addu  $24,$24,$21
72324		 lw    $24,0x00($24)
72325		 andi  $24,$24,0x3F
72326		 sll   $8,$8,2
72327		 addu  $8,$8,$21
72328		 lbu   $2,0x00($8)
72329		 beq   $24,$0,9f
72330		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72331		 sll   $25,$24,1
72332		 subu  $15,$15,$25
72333		 andi  $24,$24,0x07
72334		 subu  $25,$0,$24
72335		 andi  $25,$25,0x07
72336		 sllv  $25,$2,$25
72337		 srlv  $2,$2,$24
72338		 or    $2,$2,$25
72339		 srl   $16,$2,7        	 # Set Carry
72340	9:
72341		 andi  $2,$2,0xFF
72342		 and   $17,$0,$0        	 # Clear Overflow
72343		 sltiu $18,$2,1         	 # Set Zero
72344		 srl   $19,$2,7        	 # Set Sign
72345		 sb    $2,0x00($8)
72346		 addiu $15,$15,-6
72347		 bgez  $15,3f
72348		 lhu   $24,0x00($23)    	 # Delay slot
72349		 j     MainExit
72350	3:
72351		 sll   $7,$24,2         	 # Delay slot
72352		 addu  $7,$7,$30
72353		 lw    $7,0x00($7)
72354		 jr    $7
72355		 nop                    	 # Delay slot
72356
72357OP0_e058:				#:
72358		 addiu $23,$23,2
72359
72360		 andi  $8,$24,0x07
72361		 srl   $24,$24,9
72362		 addiu $24,$24,-1       	 # Move range down
72363		 andi  $24,$24,0x07     	 # Mask out lower bits
72364		 addiu $24,$24,1        	 # correct range
72365		 sll   $8,$8,2
72366		 addu  $8,$8,$21
72367		 lhu   $2,0x00($8)
72368		 beq   $24,$0,9f
72369		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72370		 sll   $25,$24,1
72371		 subu  $15,$15,$25
72372		 andi  $24,$24,0x0F
72373		 subu  $25,$0,$24
72374		 andi  $25,$25,0x0F
72375		 sllv  $25,$2,$25
72376		 srlv  $2,$2,$24
72377		 or    $2,$2,$25
72378		 srl   $16,$2,15        	 # Set Carry
72379	9:
72380		 andi  $2,$2,0xFFFF
72381		 and   $17,$0,$0        	 # Clear Overflow
72382		 sltiu $18,$2,1         	 # Set Zero
72383		 srl   $19,$2,15        	 # Set Sign
72384		 sh    $2,0x00($8)
72385		 addiu $15,$15,-6
72386		 bgez  $15,3f
72387		 lhu   $24,0x00($23)    	 # Delay slot
72388		 j     MainExit
72389	3:
72390		 sll   $7,$24,2         	 # Delay slot
72391		 addu  $7,$7,$30
72392		 lw    $7,0x00($7)
72393		 jr    $7
72394		 nop                    	 # Delay slot
72395
72396OP0_e078:				#:
72397		 addiu $23,$23,2
72398
72399		 andi  $8,$24,0x07
72400		 srl   $24,$24,7
72401		 andi  $24,$24,0x1C
72402		 addu  $24,$24,$21
72403		 lw    $24,0x00($24)
72404		 andi  $24,$24,0x3F
72405		 sll   $8,$8,2
72406		 addu  $8,$8,$21
72407		 lhu   $2,0x00($8)
72408		 beq   $24,$0,9f
72409		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72410		 sll   $25,$24,1
72411		 subu  $15,$15,$25
72412		 andi  $24,$24,0x0F
72413		 subu  $25,$0,$24
72414		 andi  $25,$25,0x0F
72415		 sllv  $25,$2,$25
72416		 srlv  $2,$2,$24
72417		 or    $2,$2,$25
72418		 srl   $16,$2,15        	 # Set Carry
72419	9:
72420		 andi  $2,$2,0xFFFF
72421		 and   $17,$0,$0        	 # Clear Overflow
72422		 sltiu $18,$2,1         	 # Set Zero
72423		 srl   $19,$2,15        	 # Set Sign
72424		 sh    $2,0x00($8)
72425		 addiu $15,$15,-6
72426		 bgez  $15,3f
72427		 lhu   $24,0x00($23)    	 # Delay slot
72428		 j     MainExit
72429	3:
72430		 sll   $7,$24,2         	 # Delay slot
72431		 addu  $7,$7,$30
72432		 lw    $7,0x00($7)
72433		 jr    $7
72434		 nop                    	 # Delay slot
72435
72436OP0_e098:				#:
72437		 addiu $23,$23,2
72438
72439		 andi  $8,$24,0x07
72440		 srl   $24,$24,9
72441		 addiu $24,$24,-1       	 # Move range down
72442		 andi  $24,$24,0x07     	 # Mask out lower bits
72443		 addiu $24,$24,1        	 # correct range
72444		 sll   $8,$8,2
72445		 addu  $8,$8,$21
72446		 lw    $2,0x00($8)
72447		 beq   $24,$0,9f
72448		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72449		 sll   $25,$24,1
72450		 subu  $15,$15,$25
72451		 rorv  $2,$2,$24
72452		 srl   $16,$2,31        	 # Set Carry
72453	9:
72454		 and   $17,$0,$0        	 # Clear Overflow
72455		 sltiu $18,$2,1         	 # Set Zero
72456		 srl   $19,$2,31        	 # Set Sign
72457		 sw    $2,0x00($8)
72458		 addiu $15,$15,-8
72459		 bgez  $15,3f
72460		 lhu   $24,0x00($23)    	 # Delay slot
72461		 j     MainExit
72462	3:
72463		 sll   $7,$24,2         	 # Delay slot
72464		 addu  $7,$7,$30
72465		 lw    $7,0x00($7)
72466		 jr    $7
72467		 nop                    	 # Delay slot
72468
72469OP0_e0b8:				#:
72470		 addiu $23,$23,2
72471
72472		 andi  $8,$24,0x07
72473		 srl   $24,$24,7
72474		 andi  $24,$24,0x1C
72475		 addu  $24,$24,$21
72476		 lw    $24,0x00($24)
72477		 andi  $24,$24,0x3F
72478		 sll   $8,$8,2
72479		 addu  $8,$8,$21
72480		 lw    $2,0x00($8)
72481		 beq   $24,$0,9f
72482		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72483		 sll   $25,$24,1
72484		 subu  $15,$15,$25
72485		 rorv  $2,$2,$24
72486		 srl   $16,$2,31        	 # Set Carry
72487	9:
72488		 and   $17,$0,$0        	 # Clear Overflow
72489		 sltiu $18,$2,1         	 # Set Zero
72490		 srl   $19,$2,31        	 # Set Sign
72491		 sw    $2,0x00($8)
72492		 addiu $15,$15,-8
72493		 bgez  $15,3f
72494		 lhu   $24,0x00($23)    	 # Delay slot
72495		 j     MainExit
72496	3:
72497		 sll   $7,$24,2         	 # Delay slot
72498		 addu  $7,$7,$30
72499		 lw    $7,0x00($7)
72500		 jr    $7
72501		 nop                    	 # Delay slot
72502
72503OP0_e118:				#:
72504		 addiu $23,$23,2
72505
72506		 andi  $8,$24,0x07
72507		 srl   $24,$24,9
72508		 addiu $24,$24,-1       	 # Move range down
72509		 andi  $24,$24,0x07     	 # Mask out lower bits
72510		 addiu $24,$24,1        	 # correct range
72511		 sll   $8,$8,2
72512		 addu  $8,$8,$21
72513		 lbu   $2,0x00($8)
72514		 beq   $24,$0,9f
72515		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72516		 sll   $25,$24,1
72517		 subu  $15,$15,$25
72518		 andi  $24,$24,0x07
72519		 subu  $25,$0,$24
72520		 andi  $25,$25,0x07
72521		 srlv  $25,$2,$25
72522		 sllv  $2,$2,$24
72523		 or    $2,$2,$25
72524		 andi  $16,$2,0x01      	 # Set Carry
72525	9:
72526		 andi  $2,$2,0xFF
72527		 and   $17,$0,$0        	 # Clear Overflow
72528		 sltiu $18,$2,1         	 # Set Zero
72529		 srl   $19,$2,7        	 # Set Sign
72530		 sb    $2,0x00($8)
72531		 addiu $15,$15,-6
72532		 bgez  $15,3f
72533		 lhu   $24,0x00($23)    	 # Delay slot
72534		 j     MainExit
72535	3:
72536		 sll   $7,$24,2         	 # Delay slot
72537		 addu  $7,$7,$30
72538		 lw    $7,0x00($7)
72539		 jr    $7
72540		 nop                    	 # Delay slot
72541
72542OP0_e138:				#:
72543		 addiu $23,$23,2
72544
72545		 andi  $8,$24,0x07
72546		 srl   $24,$24,7
72547		 andi  $24,$24,0x1C
72548		 addu  $24,$24,$21
72549		 lw    $24,0x00($24)
72550		 andi  $24,$24,0x3F
72551		 sll   $8,$8,2
72552		 addu  $8,$8,$21
72553		 lbu   $2,0x00($8)
72554		 beq   $24,$0,9f
72555		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72556		 sll   $25,$24,1
72557		 subu  $15,$15,$25
72558		 andi  $24,$24,0x07
72559		 subu  $25,$0,$24
72560		 andi  $25,$25,0x07
72561		 srlv  $25,$2,$25
72562		 sllv  $2,$2,$24
72563		 or    $2,$2,$25
72564		 andi  $16,$2,0x01      	 # Set Carry
72565	9:
72566		 andi  $2,$2,0xFF
72567		 and   $17,$0,$0        	 # Clear Overflow
72568		 sltiu $18,$2,1         	 # Set Zero
72569		 srl   $19,$2,7        	 # Set Sign
72570		 sb    $2,0x00($8)
72571		 addiu $15,$15,-6
72572		 bgez  $15,3f
72573		 lhu   $24,0x00($23)    	 # Delay slot
72574		 j     MainExit
72575	3:
72576		 sll   $7,$24,2         	 # Delay slot
72577		 addu  $7,$7,$30
72578		 lw    $7,0x00($7)
72579		 jr    $7
72580		 nop                    	 # Delay slot
72581
72582OP0_e158:				#:
72583		 addiu $23,$23,2
72584
72585		 andi  $8,$24,0x07
72586		 srl   $24,$24,9
72587		 addiu $24,$24,-1       	 # Move range down
72588		 andi  $24,$24,0x07     	 # Mask out lower bits
72589		 addiu $24,$24,1        	 # correct range
72590		 sll   $8,$8,2
72591		 addu  $8,$8,$21
72592		 lhu   $2,0x00($8)
72593		 beq   $24,$0,9f
72594		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72595		 sll   $25,$24,1
72596		 subu  $15,$15,$25
72597		 andi  $24,$24,0x0F
72598		 subu  $25,$0,$24
72599		 andi  $25,$25,0x0F
72600		 srlv  $25,$2,$25
72601		 sllv  $2,$2,$24
72602		 or    $2,$2,$25
72603		 andi  $16,$2,0x01      	 # Set Carry
72604	9:
72605		 andi  $2,$2,0xFFFF
72606		 and   $17,$0,$0        	 # Clear Overflow
72607		 sltiu $18,$2,1         	 # Set Zero
72608		 srl   $19,$2,15        	 # Set Sign
72609		 sh    $2,0x00($8)
72610		 addiu $15,$15,-6
72611		 bgez  $15,3f
72612		 lhu   $24,0x00($23)    	 # Delay slot
72613		 j     MainExit
72614	3:
72615		 sll   $7,$24,2         	 # Delay slot
72616		 addu  $7,$7,$30
72617		 lw    $7,0x00($7)
72618		 jr    $7
72619		 nop                    	 # Delay slot
72620
72621OP0_e178:				#:
72622		 addiu $23,$23,2
72623
72624		 andi  $8,$24,0x07
72625		 srl   $24,$24,7
72626		 andi  $24,$24,0x1C
72627		 addu  $24,$24,$21
72628		 lw    $24,0x00($24)
72629		 andi  $24,$24,0x3F
72630		 sll   $8,$8,2
72631		 addu  $8,$8,$21
72632		 lhu   $2,0x00($8)
72633		 beq   $24,$0,9f
72634		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72635		 sll   $25,$24,1
72636		 subu  $15,$15,$25
72637		 andi  $24,$24,0x0F
72638		 subu  $25,$0,$24
72639		 andi  $25,$25,0x0F
72640		 srlv  $25,$2,$25
72641		 sllv  $2,$2,$24
72642		 or    $2,$2,$25
72643		 andi  $16,$2,0x01      	 # Set Carry
72644	9:
72645		 andi  $2,$2,0xFFFF
72646		 and   $17,$0,$0        	 # Clear Overflow
72647		 sltiu $18,$2,1         	 # Set Zero
72648		 srl   $19,$2,15        	 # Set Sign
72649		 sh    $2,0x00($8)
72650		 addiu $15,$15,-6
72651		 bgez  $15,3f
72652		 lhu   $24,0x00($23)    	 # Delay slot
72653		 j     MainExit
72654	3:
72655		 sll   $7,$24,2         	 # Delay slot
72656		 addu  $7,$7,$30
72657		 lw    $7,0x00($7)
72658		 jr    $7
72659		 nop                    	 # Delay slot
72660
72661OP0_e198:				#:
72662		 addiu $23,$23,2
72663
72664		 andi  $8,$24,0x07
72665		 srl   $24,$24,9
72666		 addiu $24,$24,-1       	 # Move range down
72667		 andi  $24,$24,0x07     	 # Mask out lower bits
72668		 addiu $24,$24,1        	 # correct range
72669		 sll   $8,$8,2
72670		 addu  $8,$8,$21
72671		 lw    $2,0x00($8)
72672		 beq   $24,$0,9f
72673		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72674		 sll   $25,$24,1
72675		 subu  $15,$15,$25
72676		 subu  $25,$0,$24
72677		 rorv  $2,$2,$25
72678		 andi  $16,$2,0x01      	 # Set Carry
72679	9:
72680		 and   $17,$0,$0        	 # Clear Overflow
72681		 sltiu $18,$2,1         	 # Set Zero
72682		 srl   $19,$2,31        	 # Set Sign
72683		 sw    $2,0x00($8)
72684		 addiu $15,$15,-8
72685		 bgez  $15,3f
72686		 lhu   $24,0x00($23)    	 # Delay slot
72687		 j     MainExit
72688	3:
72689		 sll   $7,$24,2         	 # Delay slot
72690		 addu  $7,$7,$30
72691		 lw    $7,0x00($7)
72692		 jr    $7
72693		 nop                    	 # Delay slot
72694
72695OP0_e1b8:				#:
72696		 addiu $23,$23,2
72697
72698		 andi  $8,$24,0x07
72699		 srl   $24,$24,7
72700		 andi  $24,$24,0x1C
72701		 addu  $24,$24,$21
72702		 lw    $24,0x00($24)
72703		 andi  $24,$24,0x3F
72704		 sll   $8,$8,2
72705		 addu  $8,$8,$21
72706		 lw    $2,0x00($8)
72707		 beq   $24,$0,9f
72708		 and   $16,$0,$0        	 # Delay slot - Clear Carry
72709		 sll   $25,$24,1
72710		 subu  $15,$15,$25
72711		 subu  $25,$0,$24
72712		 rorv  $2,$2,$25
72713		 andi  $16,$2,0x01      	 # Set Carry
72714	9:
72715		 and   $17,$0,$0        	 # Clear Overflow
72716		 sltiu $18,$2,1         	 # Set Zero
72717		 srl   $19,$2,31        	 # Set Sign
72718		 sw    $2,0x00($8)
72719		 addiu $15,$15,-8
72720		 bgez  $15,3f
72721		 lhu   $24,0x00($23)    	 # Delay slot
72722		 j     MainExit
72723	3:
72724		 sll   $7,$24,2         	 # Delay slot
72725		 addu  $7,$7,$30
72726		 lw    $7,0x00($7)
72727		 jr    $7
72728		 nop                    	 # Delay slot
72729
72730OP0_e6d0:				#:
72731		 addiu $23,$23,2
72732
72733		 andi  $24,$24,0x07
72734		 sll   $24,$24,2
72735		 addu  $24,$24,$21
72736		 lw    $14,0x20($24)
72737		 lw    $25,0x80($21)
72738		 sw    $15,m68k_ICount
72739		 sw    $14,0x44($29)
72740		 or    $4,$0,$14
72741		 jalr  $25
72742		 sw    $23,0x4C($21)    	 # Delay slot
72743		 lw    $14,0x44($29)
72744		 lw    $15,m68k_ICount
72745		 sll   $25,$2,15
72746		 srl   $2,$2,1
72747		 or    $2,$2,$25
72748		 srl   $16,$2,15        	 # Set Carry
72749		 andi  $2,$2,0xffff
72750		 and   $17,$0,$0        	 # Clear Overflow
72751		 sltiu $18,$2,1         	 # Set Zero
72752		 srl   $19,$2,15        	 # Set Sign
72753		 lw    $25,0x8C($21)
72754		 sw    $15,m68k_ICount
72755		 or    $5,$0,$2
72756		 or    $4,$0,$14
72757		 jalr  $25
72758		 sw    $23,0x4C($21)    	 # Delay slot
72759		 lw    $15,m68k_ICount
72760		 addiu $15,$15,-12
72761		 bgez  $15,3f
72762		 lhu   $24,0x00($23)    	 # Delay slot
72763		 j     MainExit
72764	3:
72765		 sll   $7,$24,2         	 # Delay slot
72766		 addu  $7,$7,$30
72767		 lw    $7,0x00($7)
72768		 jr    $7
72769		 nop                    	 # Delay slot
72770
72771OP0_e6d8:				#:
72772		 addiu $23,$23,2
72773
72774		 andi  $24,$24,0x07
72775		 sll   $24,$24,2
72776		 addu  $24,$24,$21
72777		 lw    $14,0x20($24)
72778		 addiu $25,$14,2
72779		 sw    $25,0x20($24)
72780		 lw    $25,0x80($21)
72781		 sw    $15,m68k_ICount
72782		 sw    $14,0x44($29)
72783		 or    $4,$0,$14
72784		 jalr  $25
72785		 sw    $23,0x4C($21)    	 # Delay slot
72786		 lw    $14,0x44($29)
72787		 lw    $15,m68k_ICount
72788		 sll   $25,$2,15
72789		 srl   $2,$2,1
72790		 or    $2,$2,$25
72791		 srl   $16,$2,15        	 # Set Carry
72792		 andi  $2,$2,0xffff
72793		 and   $17,$0,$0        	 # Clear Overflow
72794		 sltiu $18,$2,1         	 # Set Zero
72795		 srl   $19,$2,15        	 # Set Sign
72796		 lw    $25,0x8C($21)
72797		 sw    $15,m68k_ICount
72798		 or    $5,$0,$2
72799		 or    $4,$0,$14
72800		 jalr  $25
72801		 sw    $23,0x4C($21)    	 # Delay slot
72802		 lw    $15,m68k_ICount
72803		 addiu $15,$15,-12
72804		 bgez  $15,3f
72805		 lhu   $24,0x00($23)    	 # Delay slot
72806		 j     MainExit
72807	3:
72808		 sll   $7,$24,2         	 # Delay slot
72809		 addu  $7,$7,$30
72810		 lw    $7,0x00($7)
72811		 jr    $7
72812		 nop                    	 # Delay slot
72813
72814OP0_e6e0:				#:
72815		 addiu $23,$23,2
72816
72817		 andi  $24,$24,0x07
72818		 sll   $24,$24,2
72819		 addu  $24,$24,$21
72820		 lw    $14,0x20($24)
72821		 addiu $14,$14,-2
72822		 sw    $14,0x20($24)
72823		 lw    $25,0x80($21)
72824		 sw    $15,m68k_ICount
72825		 sw    $14,0x44($29)
72826		 or    $4,$0,$14
72827		 jalr  $25
72828		 sw    $23,0x4C($21)    	 # Delay slot
72829		 lw    $14,0x44($29)
72830		 lw    $15,m68k_ICount
72831		 sll   $25,$2,15
72832		 srl   $2,$2,1
72833		 or    $2,$2,$25
72834		 srl   $16,$2,15        	 # Set Carry
72835		 andi  $2,$2,0xffff
72836		 and   $17,$0,$0        	 # Clear Overflow
72837		 sltiu $18,$2,1         	 # Set Zero
72838		 srl   $19,$2,15        	 # Set Sign
72839		 lw    $25,0x8C($21)
72840		 sw    $15,m68k_ICount
72841		 or    $5,$0,$2
72842		 or    $4,$0,$14
72843		 jalr  $25
72844		 sw    $23,0x4C($21)    	 # Delay slot
72845		 lw    $15,m68k_ICount
72846		 addiu $15,$15,-14
72847		 bgez  $15,3f
72848		 lhu   $24,0x00($23)    	 # Delay slot
72849		 j     MainExit
72850	3:
72851		 sll   $7,$24,2         	 # Delay slot
72852		 addu  $7,$7,$30
72853		 lw    $7,0x00($7)
72854		 jr    $7
72855		 nop                    	 # Delay slot
72856
72857OP0_e6e8:				#:
72858		 addiu $23,$23,2
72859
72860		 andi  $24,$24,0x07
72861		 lh    $7,0x00($23)
72862		 sll   $24,$24,2
72863		 addu  $24,$24,$21
72864		 lw    $14,0x20($24)
72865		 addiu $23,$23,2
72866		 addu  $14,$14,$7
72867		 lw    $25,0x80($21)
72868		 sw    $15,m68k_ICount
72869		 sw    $14,0x44($29)
72870		 or    $4,$0,$14
72871		 jalr  $25
72872		 sw    $23,0x4C($21)    	 # Delay slot
72873		 lw    $14,0x44($29)
72874		 lw    $15,m68k_ICount
72875		 sll   $25,$2,15
72876		 srl   $2,$2,1
72877		 or    $2,$2,$25
72878		 srl   $16,$2,15        	 # Set Carry
72879		 andi  $2,$2,0xffff
72880		 and   $17,$0,$0        	 # Clear Overflow
72881		 sltiu $18,$2,1         	 # Set Zero
72882		 srl   $19,$2,15        	 # Set Sign
72883		 lw    $25,0x8C($21)
72884		 sw    $15,m68k_ICount
72885		 or    $5,$0,$2
72886		 or    $4,$0,$14
72887		 jalr  $25
72888		 sw    $23,0x4C($21)    	 # Delay slot
72889		 lw    $15,m68k_ICount
72890		 addiu $15,$15,-16
72891		 bgez  $15,3f
72892		 lhu   $24,0x00($23)    	 # Delay slot
72893		 j     MainExit
72894	3:
72895		 sll   $7,$24,2         	 # Delay slot
72896		 addu  $7,$7,$30
72897		 lw    $7,0x00($7)
72898		 jr    $7
72899		 nop                    	 # Delay slot
72900
72901OP0_e6f0:				#:
72902		 addiu $23,$23,2
72903
72904		 andi  $24,$24,0x07
72905		 sll   $24,$24,2
72906		 addu  $24,$24,$21
72907		 lw    $14,0x20($24)
72908		 lhu   $7,0x00($23)
72909		 addiu $23,$23,2
72910		 seb   $6,$7
72911		 or    $25,$0,$7
72912		 srl   $7,$7,12
72913		 andi  $25,$25,0x0800
72914		 sll   $7,$7,2
72915		 addu  $7,$7,$21
72916		 bne   $25,$0,0f
72917		 lw    $25,0x00($7)      	 # Delay slot
72918		 seh   $25,$25
72919	0:
72920		 addu  $25,$14,$25
72921		 addu  $14,$25,$6
72922		 lw    $25,0x80($21)
72923		 sw    $15,m68k_ICount
72924		 sw    $14,0x44($29)
72925		 or    $4,$0,$14
72926		 jalr  $25
72927		 sw    $23,0x4C($21)    	 # Delay slot
72928		 lw    $14,0x44($29)
72929		 lw    $15,m68k_ICount
72930		 sll   $25,$2,15
72931		 srl   $2,$2,1
72932		 or    $2,$2,$25
72933		 srl   $16,$2,15        	 # Set Carry
72934		 andi  $2,$2,0xffff
72935		 and   $17,$0,$0        	 # Clear Overflow
72936		 sltiu $18,$2,1         	 # Set Zero
72937		 srl   $19,$2,15        	 # Set Sign
72938		 lw    $25,0x8C($21)
72939		 sw    $15,m68k_ICount
72940		 or    $5,$0,$2
72941		 or    $4,$0,$14
72942		 jalr  $25
72943		 sw    $23,0x4C($21)    	 # Delay slot
72944		 lw    $15,m68k_ICount
72945		 addiu $15,$15,-18
72946		 bgez  $15,3f
72947		 lhu   $24,0x00($23)    	 # Delay slot
72948		 j     MainExit
72949	3:
72950		 sll   $7,$24,2         	 # Delay slot
72951		 addu  $7,$7,$30
72952		 lw    $7,0x00($7)
72953		 jr    $7
72954		 nop                    	 # Delay slot
72955
72956OP0_e6f8:				#:
72957		 addiu $23,$23,2
72958
72959		 lh    $14,0x00($23)
72960		 addiu $23,$23,2
72961		 lw    $25,0x80($21)
72962		 sw    $15,m68k_ICount
72963		 sw    $14,0x44($29)
72964		 or    $4,$0,$14
72965		 jalr  $25
72966		 sw    $23,0x4C($21)    	 # Delay slot
72967		 lw    $14,0x44($29)
72968		 lw    $15,m68k_ICount
72969		 sll   $25,$2,15
72970		 srl   $2,$2,1
72971		 or    $2,$2,$25
72972		 srl   $16,$2,15        	 # Set Carry
72973		 andi  $2,$2,0xffff
72974		 and   $17,$0,$0        	 # Clear Overflow
72975		 sltiu $18,$2,1         	 # Set Zero
72976		 srl   $19,$2,15        	 # Set Sign
72977		 lw    $25,0x8C($21)
72978		 sw    $15,m68k_ICount
72979		 or    $5,$0,$2
72980		 or    $4,$0,$14
72981		 jalr  $25
72982		 sw    $23,0x4C($21)    	 # Delay slot
72983		 lw    $15,m68k_ICount
72984		 addiu $15,$15,-16
72985		 bgez  $15,3f
72986		 lhu   $24,0x00($23)    	 # Delay slot
72987		 j     MainExit
72988	3:
72989		 sll   $7,$24,2         	 # Delay slot
72990		 addu  $7,$7,$30
72991		 lw    $7,0x00($7)
72992		 jr    $7
72993		 nop                    	 # Delay slot
72994
72995OP0_e6f9:				#:
72996		 addiu $23,$23,2
72997
72998		 lhu   $14,0x00($23)
72999		 lhu   $25,0x02($23)
73000		 sll   $14,$14,16
73001		 or    $14,$14,$25
73002		 addiu $23,$23,4
73003		 lw    $25,0x80($21)
73004		 sw    $15,m68k_ICount
73005		 sw    $14,0x44($29)
73006		 or    $4,$0,$14
73007		 jalr  $25
73008		 sw    $23,0x4C($21)    	 # Delay slot
73009		 lw    $14,0x44($29)
73010		 lw    $15,m68k_ICount
73011		 sll   $25,$2,15
73012		 srl   $2,$2,1
73013		 or    $2,$2,$25
73014		 srl   $16,$2,15        	 # Set Carry
73015		 andi  $2,$2,0xffff
73016		 and   $17,$0,$0        	 # Clear Overflow
73017		 sltiu $18,$2,1         	 # Set Zero
73018		 srl   $19,$2,15        	 # Set Sign
73019		 lw    $25,0x8C($21)
73020		 sw    $15,m68k_ICount
73021		 or    $5,$0,$2
73022		 or    $4,$0,$14
73023		 jalr  $25
73024		 sw    $23,0x4C($21)    	 # Delay slot
73025		 lw    $15,m68k_ICount
73026		 addiu $15,$15,-20
73027		 bgez  $15,3f
73028		 lhu   $24,0x00($23)    	 # Delay slot
73029		 j     MainExit
73030	3:
73031		 sll   $7,$24,2         	 # Delay slot
73032		 addu  $7,$7,$30
73033		 lw    $7,0x00($7)
73034		 jr    $7
73035		 nop                    	 # Delay slot
73036
73037OP0_e7d0:				#:
73038		 addiu $23,$23,2
73039
73040		 andi  $24,$24,0x07
73041		 sll   $24,$24,2
73042		 addu  $24,$24,$21
73043		 lw    $14,0x20($24)
73044		 lw    $25,0x80($21)
73045		 sw    $15,m68k_ICount
73046		 sw    $14,0x44($29)
73047		 or    $4,$0,$14
73048		 jalr  $25
73049		 sw    $23,0x4C($21)    	 # Delay slot
73050		 lw    $14,0x44($29)
73051		 lw    $15,m68k_ICount
73052		 srl   $25,$2,15
73053		 sll   $2,$2,1
73054		 or    $2,$2,$25
73055		 andi  $16,$2,0x01      	 # Set Carry
73056		 andi  $2,$2,0xffff
73057		 and   $17,$0,$0        	 # Clear Overflow
73058		 sltiu $18,$2,1         	 # Set Zero
73059		 srl   $19,$2,15        	 # Set Sign
73060		 lw    $25,0x8C($21)
73061		 sw    $15,m68k_ICount
73062		 or    $5,$0,$2
73063		 or    $4,$0,$14
73064		 jalr  $25
73065		 sw    $23,0x4C($21)    	 # Delay slot
73066		 lw    $15,m68k_ICount
73067		 addiu $15,$15,-12
73068		 bgez  $15,3f
73069		 lhu   $24,0x00($23)    	 # Delay slot
73070		 j     MainExit
73071	3:
73072		 sll   $7,$24,2         	 # Delay slot
73073		 addu  $7,$7,$30
73074		 lw    $7,0x00($7)
73075		 jr    $7
73076		 nop                    	 # Delay slot
73077
73078OP0_e7d8:				#:
73079		 addiu $23,$23,2
73080
73081		 andi  $24,$24,0x07
73082		 sll   $24,$24,2
73083		 addu  $24,$24,$21
73084		 lw    $14,0x20($24)
73085		 addiu $25,$14,2
73086		 sw    $25,0x20($24)
73087		 lw    $25,0x80($21)
73088		 sw    $15,m68k_ICount
73089		 sw    $14,0x44($29)
73090		 or    $4,$0,$14
73091		 jalr  $25
73092		 sw    $23,0x4C($21)    	 # Delay slot
73093		 lw    $14,0x44($29)
73094		 lw    $15,m68k_ICount
73095		 srl   $25,$2,15
73096		 sll   $2,$2,1
73097		 or    $2,$2,$25
73098		 andi  $16,$2,0x01      	 # Set Carry
73099		 andi  $2,$2,0xffff
73100		 and   $17,$0,$0        	 # Clear Overflow
73101		 sltiu $18,$2,1         	 # Set Zero
73102		 srl   $19,$2,15        	 # Set Sign
73103		 lw    $25,0x8C($21)
73104		 sw    $15,m68k_ICount
73105		 or    $5,$0,$2
73106		 or    $4,$0,$14
73107		 jalr  $25
73108		 sw    $23,0x4C($21)    	 # Delay slot
73109		 lw    $15,m68k_ICount
73110		 addiu $15,$15,-12
73111		 bgez  $15,3f
73112		 lhu   $24,0x00($23)    	 # Delay slot
73113		 j     MainExit
73114	3:
73115		 sll   $7,$24,2         	 # Delay slot
73116		 addu  $7,$7,$30
73117		 lw    $7,0x00($7)
73118		 jr    $7
73119		 nop                    	 # Delay slot
73120
73121OP0_e7e0:				#:
73122		 addiu $23,$23,2
73123
73124		 andi  $24,$24,0x07
73125		 sll   $24,$24,2
73126		 addu  $24,$24,$21
73127		 lw    $14,0x20($24)
73128		 addiu $14,$14,-2
73129		 sw    $14,0x20($24)
73130		 lw    $25,0x80($21)
73131		 sw    $15,m68k_ICount
73132		 sw    $14,0x44($29)
73133		 or    $4,$0,$14
73134		 jalr  $25
73135		 sw    $23,0x4C($21)    	 # Delay slot
73136		 lw    $14,0x44($29)
73137		 lw    $15,m68k_ICount
73138		 srl   $25,$2,15
73139		 sll   $2,$2,1
73140		 or    $2,$2,$25
73141		 andi  $16,$2,0x01      	 # Set Carry
73142		 andi  $2,$2,0xffff
73143		 and   $17,$0,$0        	 # Clear Overflow
73144		 sltiu $18,$2,1         	 # Set Zero
73145		 srl   $19,$2,15        	 # Set Sign
73146		 lw    $25,0x8C($21)
73147		 sw    $15,m68k_ICount
73148		 or    $5,$0,$2
73149		 or    $4,$0,$14
73150		 jalr  $25
73151		 sw    $23,0x4C($21)    	 # Delay slot
73152		 lw    $15,m68k_ICount
73153		 addiu $15,$15,-14
73154		 bgez  $15,3f
73155		 lhu   $24,0x00($23)    	 # Delay slot
73156		 j     MainExit
73157	3:
73158		 sll   $7,$24,2         	 # Delay slot
73159		 addu  $7,$7,$30
73160		 lw    $7,0x00($7)
73161		 jr    $7
73162		 nop                    	 # Delay slot
73163
73164OP0_e7e8:				#:
73165		 addiu $23,$23,2
73166
73167		 andi  $24,$24,0x07
73168		 lh    $7,0x00($23)
73169		 sll   $24,$24,2
73170		 addu  $24,$24,$21
73171		 lw    $14,0x20($24)
73172		 addiu $23,$23,2
73173		 addu  $14,$14,$7
73174		 lw    $25,0x80($21)
73175		 sw    $15,m68k_ICount
73176		 sw    $14,0x44($29)
73177		 or    $4,$0,$14
73178		 jalr  $25
73179		 sw    $23,0x4C($21)    	 # Delay slot
73180		 lw    $14,0x44($29)
73181		 lw    $15,m68k_ICount
73182		 srl   $25,$2,15
73183		 sll   $2,$2,1
73184		 or    $2,$2,$25
73185		 andi  $16,$2,0x01      	 # Set Carry
73186		 andi  $2,$2,0xffff
73187		 and   $17,$0,$0        	 # Clear Overflow
73188		 sltiu $18,$2,1         	 # Set Zero
73189		 srl   $19,$2,15        	 # Set Sign
73190		 lw    $25,0x8C($21)
73191		 sw    $15,m68k_ICount
73192		 or    $5,$0,$2
73193		 or    $4,$0,$14
73194		 jalr  $25
73195		 sw    $23,0x4C($21)    	 # Delay slot
73196		 lw    $15,m68k_ICount
73197		 addiu $15,$15,-16
73198		 bgez  $15,3f
73199		 lhu   $24,0x00($23)    	 # Delay slot
73200		 j     MainExit
73201	3:
73202		 sll   $7,$24,2         	 # Delay slot
73203		 addu  $7,$7,$30
73204		 lw    $7,0x00($7)
73205		 jr    $7
73206		 nop                    	 # Delay slot
73207
73208OP0_e7f0:				#:
73209		 addiu $23,$23,2
73210
73211		 andi  $24,$24,0x07
73212		 sll   $24,$24,2
73213		 addu  $24,$24,$21
73214		 lw    $14,0x20($24)
73215		 lhu   $7,0x00($23)
73216		 addiu $23,$23,2
73217		 seb   $6,$7
73218		 or    $25,$0,$7
73219		 srl   $7,$7,12
73220		 andi  $25,$25,0x0800
73221		 sll   $7,$7,2
73222		 addu  $7,$7,$21
73223		 bne   $25,$0,0f
73224		 lw    $25,0x00($7)      	 # Delay slot
73225		 seh   $25,$25
73226	0:
73227		 addu  $25,$14,$25
73228		 addu  $14,$25,$6
73229		 lw    $25,0x80($21)
73230		 sw    $15,m68k_ICount
73231		 sw    $14,0x44($29)
73232		 or    $4,$0,$14
73233		 jalr  $25
73234		 sw    $23,0x4C($21)    	 # Delay slot
73235		 lw    $14,0x44($29)
73236		 lw    $15,m68k_ICount
73237		 srl   $25,$2,15
73238		 sll   $2,$2,1
73239		 or    $2,$2,$25
73240		 andi  $16,$2,0x01      	 # Set Carry
73241		 andi  $2,$2,0xffff
73242		 and   $17,$0,$0        	 # Clear Overflow
73243		 sltiu $18,$2,1         	 # Set Zero
73244		 srl   $19,$2,15        	 # Set Sign
73245		 lw    $25,0x8C($21)
73246		 sw    $15,m68k_ICount
73247		 or    $5,$0,$2
73248		 or    $4,$0,$14
73249		 jalr  $25
73250		 sw    $23,0x4C($21)    	 # Delay slot
73251		 lw    $15,m68k_ICount
73252		 addiu $15,$15,-18
73253		 bgez  $15,3f
73254		 lhu   $24,0x00($23)    	 # Delay slot
73255		 j     MainExit
73256	3:
73257		 sll   $7,$24,2         	 # Delay slot
73258		 addu  $7,$7,$30
73259		 lw    $7,0x00($7)
73260		 jr    $7
73261		 nop                    	 # Delay slot
73262
73263OP0_e7f8:				#:
73264		 addiu $23,$23,2
73265
73266		 lh    $14,0x00($23)
73267		 addiu $23,$23,2
73268		 lw    $25,0x80($21)
73269		 sw    $15,m68k_ICount
73270		 sw    $14,0x44($29)
73271		 or    $4,$0,$14
73272		 jalr  $25
73273		 sw    $23,0x4C($21)    	 # Delay slot
73274		 lw    $14,0x44($29)
73275		 lw    $15,m68k_ICount
73276		 srl   $25,$2,15
73277		 sll   $2,$2,1
73278		 or    $2,$2,$25
73279		 andi  $16,$2,0x01      	 # Set Carry
73280		 andi  $2,$2,0xffff
73281		 and   $17,$0,$0        	 # Clear Overflow
73282		 sltiu $18,$2,1         	 # Set Zero
73283		 srl   $19,$2,15        	 # Set Sign
73284		 lw    $25,0x8C($21)
73285		 sw    $15,m68k_ICount
73286		 or    $5,$0,$2
73287		 or    $4,$0,$14
73288		 jalr  $25
73289		 sw    $23,0x4C($21)    	 # Delay slot
73290		 lw    $15,m68k_ICount
73291		 addiu $15,$15,-16
73292		 bgez  $15,3f
73293		 lhu   $24,0x00($23)    	 # Delay slot
73294		 j     MainExit
73295	3:
73296		 sll   $7,$24,2         	 # Delay slot
73297		 addu  $7,$7,$30
73298		 lw    $7,0x00($7)
73299		 jr    $7
73300		 nop                    	 # Delay slot
73301
73302OP0_e7f9:				#:
73303		 addiu $23,$23,2
73304
73305		 lhu   $14,0x00($23)
73306		 lhu   $25,0x02($23)
73307		 sll   $14,$14,16
73308		 or    $14,$14,$25
73309		 addiu $23,$23,4
73310		 lw    $25,0x80($21)
73311		 sw    $15,m68k_ICount
73312		 sw    $14,0x44($29)
73313		 or    $4,$0,$14
73314		 jalr  $25
73315		 sw    $23,0x4C($21)    	 # Delay slot
73316		 lw    $14,0x44($29)
73317		 lw    $15,m68k_ICount
73318		 srl   $25,$2,15
73319		 sll   $2,$2,1
73320		 or    $2,$2,$25
73321		 andi  $16,$2,0x01      	 # Set Carry
73322		 andi  $2,$2,0xffff
73323		 and   $17,$0,$0        	 # Clear Overflow
73324		 sltiu $18,$2,1         	 # Set Zero
73325		 srl   $19,$2,15        	 # Set Sign
73326		 lw    $25,0x8C($21)
73327		 sw    $15,m68k_ICount
73328		 or    $5,$0,$2
73329		 or    $4,$0,$14
73330		 jalr  $25
73331		 sw    $23,0x4C($21)    	 # Delay slot
73332		 lw    $15,m68k_ICount
73333		 addiu $15,$15,-20
73334		 bgez  $15,3f
73335		 lhu   $24,0x00($23)    	 # Delay slot
73336		 j     MainExit
73337	3:
73338		 sll   $7,$24,2         	 # Delay slot
73339		 addu  $7,$7,$30
73340		 lw    $7,0x00($7)
73341		 jr    $7
73342		 nop                    	 # Delay slot
73343
73344OP0_a000:				#:
73345		 addiu $23,$23,2
73346
73347		 addiu $23,$23,-2
73348		 jal   Exception
73349		 ori   $2,$0,10
73350
73351		 bgez  $15,3f
73352		 lhu   $24,0x00($23)    	 # Delay slot
73353		 j     MainExit
73354	3:
73355		 sll   $7,$24,2         	 # Delay slot
73356		 addu  $7,$7,$30
73357		 lw    $7,0x00($7)
73358		 jr    $7
73359		 nop                    	 # Delay slot
73360
73361OP0_f000:				#:
73362		 addiu $23,$23,2
73363
73364		 addiu $23,$23,-2
73365		 jal   Exception
73366		 ori   $2,$0,11
73367
73368		 bgez  $15,3f
73369		 lhu   $24,0x00($23)    	 # Delay slot
73370		 j     MainExit
73371	3:
73372		 sll   $7,$24,2         	 # Delay slot
73373		 addu  $7,$7,$30
73374		 lw    $7,0x00($7)
73375		 jr    $7
73376		 nop                    	 # Delay slot
73377
73378ILLEGAL:
73379		 subu  $25,$23,$22
73380		 sw    $24,illegal_op
73381		 sw    $25,illegal_pc
73382		 addiu $23,$23,-2
73383		 jal   Exception
73384		 ori   $2,$0,4
73385
73386		 bgez  $15,3f
73387		 lhu   $24,0x00($23)    	 # Delay slot
73388		 j     MainExit
73389	3:
73390		 sll   $7,$24,2         	 # Delay slot
73391		 addu  $7,$7,$30
73392		 lw    $7,0x00($7)
73393		 jr    $7
73394		 nop                    	 # Delay slot
73395
73396OP0_4e74:				#:
73397		 lw    $25,0x70($21)
73398		 bne   $25,$0,0f
73399		 nop                    	 # Delay slot
73400		 j     ILLEGAL
73401	0:
73402		 nop                    	 # Delay slot
73403
73404		 lw    $4,0x3C($21)
73405		 lw    $25,0x84($21)
73406		 sw    $15,m68k_ICount
73407		 jalr  $25
73408		 sw    $23,0x4C($21)    	 # Delay slot
73409		 lw    $15,m68k_ICount
73410		 lh    $8,0x00($23)
73411		 lw    $9,0x3C($21)
73412		 addiu $8,$8,4
73413		 addu  $9,$8,$9
73414		 sw    $9,0x3C($21)
73415		 andi  $25,$2,0x01
73416		 beq   $25,$0,2f
73417		 addu  $23,$22,$2     	 # Delay slot
73418		 addiu $23,$23,-2
73419		 jal   Exception
73420		 ori   $2,$0,3
73421
73422		 addiu $15,$15,-16
73423		 bgez  $15,3f
73424		 lhu   $24,0x00($23)    	 # Delay slot
73425		 j     MainExit
73426	3:
73427		 sll   $7,$24,2         	 # Delay slot
73428		 addu  $7,$7,$30
73429		 lw    $7,0x00($7)
73430		 jr    $7
73431		 nop                    	 # Delay slot
73432
73433	2:
73434		 sw    $2,0x74($21)
73435		 lw    $6,mem_amask
73436		 lw    $25,0x94($21)
73437		 and   $23,$2,$6
73438		 sw    $15,m68k_ICount
73439		 jalr  $25
73440		 or    $4,$0,$23   	 # Delay slot
73441		 lw    $15,m68k_ICount
73442		 lw    $22,OP_ROM
73443		 addu  $23,$23,$22
73444 # End of Banking code:
73445		 addiu $15,$15,-16
73446		 bgez  $15,3f
73447		 lhu   $24,0x00($23)    	 # Delay slot
73448		 j     MainExit
73449	3:
73450		 sll   $7,$24,2         	 # Delay slot
73451		 addu  $7,$7,$30
73452		 lw    $7,0x00($7)
73453		 jr    $7
73454		 nop                    	 # Delay slot
73455
73456OP0_4e7a:				#:
73457		 lw    $25,0x70($21)
73458		 bne   $25,$0,0f
73459		 nop                    	 # Delay slot
73460		 j     ILLEGAL
73461	0:
73462		 nop                    	 # Delay slot
73463
73464		 lbu   $8,0x44($21)
73465		 andi  $8,$8,0x20       	 # Supervisor Mode ?
73466		 beq   $8,$0,9f
73467		 addiu $23,$23,2        	 # Delay slot
73468		 lhu   $8,0x00($23)
73469		 addiu $23,$23,2
73470		 andi  $2,$8,0x01
73471		 srl   $24,$8,10
73472		 andi  $24,$24,0x02
73473		 or    $24,$24,$2
73474		 srl   $8,$8,12
73475		 sll   $24,$24,2
73476		 addu  $24,$24,$21
73477		 addiu $24,$24,96
73478		 lw    $2,0x00($24)
73479		 sll   $8,$8,2
73480		 addu  $8,$8,$21
73481		 sw    $2,0x00($8)
73482		 addiu $15,$15,-4
73483		 bgez  $15,3f
73484		 lhu   $24,0x00($23)    	 # Delay slot
73485		 j     MainExit
73486	3:
73487		 sll   $7,$24,2         	 # Delay slot
73488		 addu  $7,$7,$30
73489		 lw    $7,0x00($7)
73490		 jr    $7
73491		 nop                    	 # Delay slot
73492
73493	9:
73494		 addiu $23,$23,-2
73495		 jal   Exception
73496		 ori   $2,$0,8
73497
73498		 addiu $15,$15,-4
73499		 bgez  $15,3f
73500		 lhu   $24,0x00($23)    	 # Delay slot
73501		 j     MainExit
73502	3:
73503		 sll   $7,$24,2         	 # Delay slot
73504		 addu  $7,$7,$30
73505		 lw    $7,0x00($7)
73506		 jr    $7
73507		 nop                    	 # Delay slot
73508
73509OP0_4e7b:				#:
73510		 lw    $25,0x70($21)
73511		 bne   $25,$0,0f
73512		 nop                    	 # Delay slot
73513		 j     ILLEGAL
73514	0:
73515		 nop                    	 # Delay slot
73516
73517		 lbu   $8,0x44($21)
73518		 andi  $8,$8,0x20       	 # Supervisor Mode ?
73519		 beq   $8,$0,9f
73520		 addiu $23,$23,2        	 # Delay slot
73521		 lhu   $8,0x00($23)
73522		 addiu $23,$23,2
73523		 andi  $2,$8,0x01
73524		 srl   $24,$8,10
73525		 andi  $24,$24,0x02
73526		 or    $24,$24,$2
73527		 srl   $8,$8,12
73528		 sll   $8,$8,2
73529		 addu  $8,$8,$21
73530		 lw    $2,0x00($8)
73531		 andi  $9,$24,0x02
73532		 bne   $9,$0,8f
73533		 nop                    	 # Delay slot
73534		 andi  $2,$2,0x07
73535	8:
73536		 sll   $24,$24,2
73537		 addu  $24,$24,$21
73538		 addiu $24,$24,96
73539		 sw    $2,0x00($24)
73540		 addiu $15,$15,-4
73541		 bgez  $15,3f
73542		 lhu   $24,0x00($23)    	 # Delay slot
73543		 j     MainExit
73544	3:
73545		 sll   $7,$24,2         	 # Delay slot
73546		 addu  $7,$7,$30
73547		 lw    $7,0x00($7)
73548		 jr    $7
73549		 nop                    	 # Delay slot
73550
73551	9:
73552		 addiu $23,$23,-2
73553		 jal   Exception
73554		 ori   $2,$0,8
73555
73556		 addiu $15,$15,-4
73557		 bgez  $15,3f
73558		 lhu   $24,0x00($23)    	 # Delay slot
73559		 j     MainExit
73560	3:
73561		 sll   $7,$24,2         	 # Delay slot
73562		 addu  $7,$7,$30
73563		 lw    $7,0x00($7)
73564		 jr    $7
73565		 nop                    	 # Delay slot
73566
73567		 .data
73568
73569		 .align 6
73570
73571
73572 # Register Structure
73573
73574M68000_regs:
73575R_D0:	 .word 0			 # Data Registers
73576R_D1:	 .word 0
73577R_D2:	 .word 0
73578R_D3:	 .word 0
73579R_D4:	 .word 0
73580R_D5:	 .word 0
73581R_D6:	 .word 0
73582R_D7:	 .word 0
73583
73584R_A0:	 .word 0			 # Address Registers
73585R_A1:	 .word 0
73586R_A2:	 .word 0
73587R_A3:	 .word 0
73588R_A4:	 .word 0
73589R_A5:	 .word 0
73590R_A6:	 .word 0
73591R_A7:	 .word 0
73592
73593R_ISP:	 .word 0			 # Supervisor Stack
73594R_SR_H:	 .word 0			 # Status Register High TuSuuIII
73595R_SR:	 .word 0			 # Motorola Format SR
73596
73597R_PC:	 .word 0			 # Program Counter
73598R_IRQ:	 .word 0			 # IRQ Request Level
73599
73600R_IRQ_CALLBACK:	 .word 0			 # irq callback (get vector)
73601
73602R_PPC:	 .word 0			 # Previous Program Counter
73603R_RESET_CALLBACK:	 .word 0			 # Reset Callback
73604R_SFC:	 .word 0			 # Source Function Call
73605R_DFC:	 .word 0			 # Destination Function Call
73606R_USP:	 .word 0			 # User Stack
73607R_VBR:	 .word 0			 # Vector Base
73608CPUversion:	 .word 0
73609
73610FullPC:	 .word 0
73611
73612a68k_memory_intf:
73613	.rept 13
73614		.word 0
73615	.endr
73616
73617
73618exception_cycles:
73619		 .byte 0, 0, 0, 0, 38, 42, 44, 38, 38, 0, 38, 38, 0, 0, 0, 0
73620		 .byte 0, 0, 0, 0, 0, 0, 0, 0, 46, 46, 46, 46, 46, 46, 46, 46
73621		 .byte 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38, 38
73622
73623		 .align 2
73624 # Jump Table
73625
73626M68000_OPCODETABLE:
73627.include "a68ktbl.inc"
73628
73629