1 #include "../vidhrdw/taito_l.c"
2 #include "../sndhrdw/taitosnd.c"
3 /*
4 Taito L-System
5
6 Monoprocessor games (1 main z80, no sound z80)
7 - Plotting
8 - Puzznic
9 - Palamedes
10 - Cachat / Tube-It
11 - American Horseshoes
12 - Play Girls
13 - Play Girls 2
14 - Cuby Bop
15
16 Dual processor games
17 - Kuri Kinton
18
19 Triple processor games (2 main z80, 1 sound z80)
20 - Fighting hawk
21 - Raimais
22 - Champion Wrestler
23
24 Notes:
25 - the system uses RAM based characters, which aren't really supported by the
26 TileMap system, so we have to tilemap_mark_all_tiles_dirty() to compensate
27 - kurikina has some debug dip switches (invulnerability, slow motion) so might
28 be a prototype. It also doesn't have service mode (or has it disabled).
29
30 TODO:
31 - champwr ADPCM interface is not entirely understood, it involves also addresses
32 0xd000 and 0xe000, and maybe also YM2203 port B.
33 - slowdowns in fhawk, probably the interrupts have to be generated at a
34 different time.
35 - plgirls doesn't work without a kludge because of an interrupt issue. This
36 happens because the program enables interrupts before setting IM2, so the
37 interrupt vector is interpreted as IM0, which is obviously bogus.
38 - The puzznic protection is worked around, but I'm not happy with it
39 (the 68705-returned values are wrong, I'm sure of that).
40 - A bunch of control registers are simply ignored
41 - The source of irqs 0 and 1 is unknown, while 2 is vblank (0 is
42 usually ignored by the program, 1 leads to reading the
43 ports... maybe vbl-in, vbl-out and hblank ?).
44 - Text Plane colours are only right in Cuby Bop once you've started a game
45 & reset
46 - Scrolling in Cuby Bop's Game seems incorrect.
47
48 */
49
50
51 #include "driver.h"
52 #include "cpu/z80/z80.h"
53 #include "sndhrdw/taitosnd.h"
54
55 void taitol_eof_callback(void);
56 int taitol_vh_start(void);
57 void taitol_vh_screenrefresh(struct osd_bitmap *bitmap, int full_refresh);
58
59 void taitol_chardef14_m(int offset);
60 void taitol_chardef15_m(int offset);
61 void taitol_chardef16_m(int offset);
62 void taitol_chardef17_m(int offset);
63 void taitol_chardef1c_m(int offset);
64 void taitol_chardef1d_m(int offset);
65 void taitol_chardef1e_m(int offset);
66 void taitol_chardef1f_m(int offset);
67 void taitol_bg18_m(int offset);
68 void taitol_bg19_m(int offset);
69 void taitol_char1a_m(int offset);
70 void taitol_obj1b_m(int offset);
71
72 WRITE_HANDLER( taitol_control_w );
73 READ_HANDLER( taitol_control_r );
74 WRITE_HANDLER( horshoes_bankg_w );
75 WRITE_HANDLER( taitol_bankc_w );
76 READ_HANDLER( taitol_bankc_r );
77
78
79
80 static void (*rambank_modify_notifiers[12])(int) =
81 {
82 taitol_chardef14_m, // 14
83 taitol_chardef15_m, // 15
84 taitol_chardef16_m, // 16
85 taitol_chardef17_m, // 17
86
87 taitol_bg18_m, // 18
88 taitol_bg19_m, // 19
89 taitol_char1a_m, // 1a
90 taitol_obj1b_m, // 1b
91
92 taitol_chardef1c_m, // 1c
93 taitol_chardef1d_m, // 1d
94 taitol_chardef1e_m, // 1e
95 taitol_chardef1f_m, // 1f
96 };
97
98 static void (*current_notifier[4])(int);
99 static unsigned char *current_base[4];
100
101 static int cur_rombank, cur_rombank2, cur_rambank[4];
102 static int irq_adr_table[3];
103 static int irq_enable = 0;
104
105 unsigned char *taitol_rambanks;
106
107 static unsigned char *palette_ram;
108 static unsigned char *empty_ram;
109 static unsigned char *shared_ram;
110
111 static mem_read_handler porte0_r;
112 static mem_read_handler porte1_r;
113 static mem_read_handler portf0_r;
114 static mem_read_handler portf1_r;
115
palette_notifier(int addr)116 static void palette_notifier(int addr)
117 {
118 unsigned char *p = palette_ram + (addr & ~1);
119 unsigned char byte0 = *p++;
120 unsigned char byte1 = *p;
121
122 unsigned int b = (byte1 & 0xf) * 0x11;
123 unsigned int g = ((byte0 & 0xf0)>>4) * 0x11;
124 unsigned int r = (byte0 & 0xf) * 0x11;
125
126 // addr &= 0x1ff;
127
128 if(addr > 0x200)
129 {
130 //logerror("Large palette ? %03x (%04x) \n", addr, cpu_get_pc());
131 }
132 else
133 {
134 // r = g = b = ((addr & 0x1e) != 0)*255;
135 palette_change_color(addr/2, r, g, b);
136 }
137 }
138
machine_init(void)139 static void machine_init(void)
140 {
141 int i;
142
143 taitol_rambanks = (unsigned char*)malloc(0x1000*12);
144 palette_ram = (unsigned char*)malloc(0x1000);
145 empty_ram = (unsigned char*)malloc(0x1000);
146
147 for(i=0;i<3;i++)
148 irq_adr_table[i] = 0;
149
150 irq_enable = 0;
151
152 for(i=0;i<4;i++)
153 {
154 cur_rambank[i] = 0x80;
155 current_base[i] = palette_ram;
156 current_notifier[i] = palette_notifier;
157 cpu_setbank(2+i, current_base[i]);
158 }
159 cur_rombank = cur_rombank2 = 0;
160 cpu_setbank(1, memory_region(REGION_CPU1) + 0x10000);
161
162 for(i=0;i<512;i++)
163 {
164 decodechar(Machine->gfx[2], i, taitol_rambanks,
165 Machine->drv->gfxdecodeinfo[2].gfxlayout);
166 decodechar(Machine->gfx[2], i+512, taitol_rambanks + 0x4000,
167 Machine->drv->gfxdecodeinfo[2].gfxlayout);
168 }
169 }
170
171
fhawk_init(void)172 static void fhawk_init(void)
173 {
174 machine_init();
175 porte0_r = 0;
176 porte1_r = 0;
177 portf0_r = 0;
178 portf1_r = 0;
179 }
180
raimais_init(void)181 static void raimais_init(void)
182 {
183 machine_init();
184 porte0_r = 0;
185 porte1_r = 0;
186 portf0_r = 0;
187 portf1_r = 0;
188 }
189
champwr_init(void)190 static void champwr_init(void)
191 {
192 machine_init();
193 porte0_r = 0;
194 porte1_r = 0;
195 portf0_r = 0;
196 portf1_r = 0;
197 }
198
199
kurikint_init(void)200 static void kurikint_init(void)
201 {
202 machine_init();
203 porte0_r = 0;
204 porte1_r = 0;
205 portf0_r = 0;
206 portf1_r = 0;
207 }
208
209
puzznic_init(void)210 static void puzznic_init(void)
211 {
212 machine_init();
213 porte0_r = input_port_0_r;
214 porte1_r = input_port_1_r;
215 portf0_r = input_port_2_r;
216 portf1_r = input_port_3_r;
217 }
218
plotting_init(void)219 static void plotting_init(void)
220 {
221 machine_init();
222 porte0_r = input_port_0_r;
223 porte1_r = input_port_1_r;
224 portf0_r = input_port_2_r;
225 portf1_r = input_port_3_r;
226 }
227
palamed_init(void)228 static void palamed_init(void)
229 {
230 machine_init();
231 porte0_r = input_port_0_r;
232 porte1_r = 0;
233 portf0_r = input_port_1_r;
234 portf1_r = 0;
235 }
236
cachat_init(void)237 static void cachat_init(void)
238 {
239 machine_init();
240 porte0_r = input_port_0_r;
241 porte1_r = 0;
242 portf0_r = input_port_1_r;
243 portf1_r = 0;
244 }
245
horshoes_init(void)246 static void horshoes_init(void)
247 {
248 machine_init();
249 porte0_r = input_port_0_r;
250 porte1_r = input_port_1_r;
251 portf0_r = input_port_2_r;
252 portf1_r = input_port_3_r;
253 }
254
255
256
vbl_interrupt(void)257 static int vbl_interrupt(void)
258 {
259 /* kludge to make plgirls boot */
260 if (cpunum_get_reg(0,Z80_IM) != 2) return Z80_IGNORE_INT;
261
262 // What is really generating interrupts 0 and 1 is still to be found
263
264 if (cpu_getiloops() == 1 && (irq_enable & 1))
265 return irq_adr_table[0];
266 if (cpu_getiloops() == 2 && (irq_enable & 2))
267 return irq_adr_table[1];
268 if (cpu_getiloops() == 0 && (irq_enable & 4))
269 return irq_adr_table[2];
270
271 return Z80_IGNORE_INT;
272 }
273
WRITE_HANDLER(irq_adr_w)274 static WRITE_HANDLER( irq_adr_w )
275 {
276 //logerror("irq_adr_table[%d] = %02x \n",offset,data);
277 irq_adr_table[offset] = data;
278 }
279
READ_HANDLER(irq_adr_r)280 static READ_HANDLER( irq_adr_r )
281 {
282 return irq_adr_table[offset];
283 }
284
WRITE_HANDLER(irq_enable_w)285 static WRITE_HANDLER( irq_enable_w )
286 {
287 //logerror("irq_enable = %02x \n",data);
288 irq_enable = data;
289 }
290
READ_HANDLER(irq_enable_r)291 static READ_HANDLER( irq_enable_r )
292 {
293 return irq_enable;
294 }
295
296
WRITE_HANDLER(rombankswitch_w)297 static WRITE_HANDLER( rombankswitch_w )
298 {
299 static int high = 0;
300 if(cur_rombank != data)
301 {
302 if(data>high)
303 {
304 high = data;
305 //logerror("New rom size : %x \n", (high+1)*0x2000);
306 }
307
308 // logerror("robs %d, %02x (%04x) \n", offset, data, cpu_get_pc());
309 cur_rombank = data;
310 cpu_setbank(1, memory_region(REGION_CPU1)+0x10000+0x2000*cur_rombank);
311 }
312 }
313
WRITE_HANDLER(rombank2switch_w)314 static WRITE_HANDLER( rombank2switch_w )
315 {
316 static int high = 0;
317
318 data &= 0xf;
319
320 if(cur_rombank2 != data)
321 {
322 if(data>high)
323 {
324 high = data;
325 //logerror("New rom2 size : %x \n", (high+1)*0x4000);
326 }
327
328 // logerror("robs2 %02x (%04x) \n", data, cpu_get_pc());
329
330 cur_rombank2 = data;
331 cpu_setbank(6, memory_region(REGION_CPU3)+0x10000+0x4000*cur_rombank2);
332 }
333 }
334
READ_HANDLER(rombankswitch_r)335 static READ_HANDLER( rombankswitch_r )
336 {
337 return cur_rombank;
338 }
339
READ_HANDLER(rombank2switch_r)340 static READ_HANDLER( rombank2switch_r )
341 {
342 return cur_rombank2;
343 }
344
WRITE_HANDLER(rambankswitch_w)345 static WRITE_HANDLER( rambankswitch_w )
346 {
347 if(cur_rambank[offset]!=data)
348 {
349 cur_rambank[offset]=data;
350 //logerror("rabs %d, %02x (%04x) \n", offset, data, cpu_get_pc());
351 if(data>=0x14 && data<=0x1f)
352 {
353 data -= 0x14;
354 current_notifier[offset] = rambank_modify_notifiers[data];
355 current_base[offset] = taitol_rambanks+0x1000*data;
356 }
357 else if (data == 0x80)
358 {
359 current_notifier[offset] = palette_notifier;
360 current_base[offset] = palette_ram;
361 }
362 else
363 {
364 //logerror("unknown rambankswitch %d, %02x (%04x) \n", offset, data, cpu_get_pc());
365 current_notifier[offset] = 0;
366 current_base[offset] = empty_ram;
367 }
368 cpu_setbank(2+offset, current_base[offset]);
369 }
370 }
371
READ_HANDLER(rambankswitch_r)372 static READ_HANDLER( rambankswitch_r )
373 {
374 return cur_rambank[offset];
375 }
376
WRITE_HANDLER(bank0_w)377 static WRITE_HANDLER( bank0_w )
378 {
379 if(current_base[0][offset]!=data)
380 {
381 current_base[0][offset] = data;
382 if(current_notifier[0])
383 current_notifier[0](offset);
384 }
385 }
386
WRITE_HANDLER(bank1_w)387 static WRITE_HANDLER( bank1_w )
388 {
389 if(current_base[1][offset]!=data)
390 {
391 current_base[1][offset] = data;
392 if(current_notifier[1])
393 current_notifier[1](offset);
394 }
395 }
396
WRITE_HANDLER(bank2_w)397 static WRITE_HANDLER( bank2_w )
398 {
399 if(current_base[2][offset]!=data)
400 {
401 current_base[2][offset] = data;
402 if(current_notifier[2])
403 current_notifier[2](offset);
404 }
405 }
406
WRITE_HANDLER(bank3_w)407 static WRITE_HANDLER( bank3_w )
408 {
409 if(current_base[3][offset]!=data)
410 {
411 current_base[3][offset] = data;
412 if(current_notifier[3])
413 current_notifier[3](offset);
414 }
415 }
416
WRITE_HANDLER(control2_w)417 static WRITE_HANDLER( control2_w )
418 {
419 coin_lockout_w(0,~data & 0x01);
420 coin_lockout_w(1,~data & 0x02);
421 coin_counter_w(0,data & 0x04);
422 coin_counter_w(1,data & 0x08);
423 }
424
425 static int extport;
426
READ_HANDLER(portA_r)427 static READ_HANDLER( portA_r )
428 {
429 if (extport == 0) return porte0_r(0);
430 else return porte1_r(0);
431 }
432
READ_HANDLER(portB_r)433 static READ_HANDLER( portB_r )
434 {
435 if (extport == 0) return portf0_r(0);
436 else return portf1_r(0);
437 }
438
READ_HANDLER(ym2203_data0_r)439 static READ_HANDLER( ym2203_data0_r )
440 {
441 extport = 0;
442 return YM2203_read_port_0_r(offset);
443 }
444
READ_HANDLER(ym2203_data1_r)445 static READ_HANDLER( ym2203_data1_r )
446 {
447 extport = 1;
448 return YM2203_read_port_0_r(offset);
449 }
450
451 static int *mcu_reply;
452 static int mcu_pos = 0, mcu_reply_len = 0;
453 static int last_data_adr, last_data;
454
455 static int puzznic_mcu_reply[] = { 0x50, 0x1f, 0xb6, 0xba, 0x06, 0x03, 0x47, 0x05, 0x00 };
456
WRITE_HANDLER(mcu_data_w)457 static WRITE_HANDLER( mcu_data_w )
458 {
459 last_data = data;
460 last_data_adr = cpu_get_pc();
461 // logerror("mcu write %02x (%04x) \n", data, cpu_get_pc());
462 switch(data)
463 {
464 case 0x43:
465 mcu_pos = 0;
466 mcu_reply = puzznic_mcu_reply;
467 mcu_reply_len = sizeof(puzznic_mcu_reply);
468 break;
469 }
470 }
471
WRITE_HANDLER(mcu_control_w)472 static WRITE_HANDLER( mcu_control_w )
473 {
474 // logerror("mcu control %02x (%04x) \n", data, cpu_get_pc());
475 }
476
READ_HANDLER(mcu_data_r)477 static READ_HANDLER( mcu_data_r )
478 {
479 // logerror("mcu read (%04x) [%02x, %04x] \n", cpu_get_pc(), last_data, last_data_adr);
480 if(mcu_pos==mcu_reply_len)
481 return 0;
482
483 return mcu_reply[mcu_pos++];
484 }
485
READ_HANDLER(mcu_control_r)486 static READ_HANDLER( mcu_control_r )
487 {
488 // logerror("mcu control read (%04x) \n", cpu_get_pc());
489 return 0x1;
490 }
491
492 /*
493 static WRITE_HANDLER( sound_w )
494 {
495 logerror("Sound_w %02x (%04x) \n", data, cpu_get_pc());
496 }
497 */
498
READ_HANDLER(shared_r)499 static READ_HANDLER( shared_r )
500 {
501 return shared_ram[offset];
502 }
503
WRITE_HANDLER(shared_w)504 static WRITE_HANDLER( shared_w )
505 {
506 shared_ram[offset] = data;
507 }
508
509 static int mux_ctrl = 0;
510
READ_HANDLER(mux_r)511 static READ_HANDLER( mux_r )
512 {
513 switch(mux_ctrl)
514 {
515 case 0:
516 return input_port_0_r(0);
517 case 1:
518 return input_port_1_r(0);
519 case 2:
520 return input_port_2_r(0);
521 case 3:
522 return input_port_3_r(0);
523 case 7:
524 return input_port_4_r(0);
525 default:
526 //logerror("Mux read from unknown port %d (%04x) \n", mux_ctrl, cpu_get_pc());
527 return 0xff;
528 }
529 }
530
WRITE_HANDLER(mux_w)531 static WRITE_HANDLER( mux_w )
532 {
533 switch(mux_ctrl)
534 {
535 case 4:
536 control2_w(0, data);
537 break;
538 default:
539 //logerror("Mux write to unknown port %d, %02x (%04x) \n", mux_ctrl, data, cpu_get_pc());
540 break;
541 }
542 }
543
WRITE_HANDLER(mux_ctrl_w)544 static WRITE_HANDLER( mux_ctrl_w )
545 {
546 mux_ctrl = data;
547 }
548
549
550
551
552 static int champwr_adpcm_start;
553
WRITE_HANDLER(champwr_adpcm_lo_w)554 static WRITE_HANDLER( champwr_adpcm_lo_w )
555 {
556 champwr_adpcm_start = (champwr_adpcm_start & 0xff00ff) | (data << 8);
557 }
558
WRITE_HANDLER(champwr_adpcm_hi_w)559 static WRITE_HANDLER( champwr_adpcm_hi_w )
560 {
561 UINT8 *rom = memory_region(REGION_SOUND1);
562 int romlen = memory_region_length(REGION_SOUND1);
563 int length;
564 int i;
565
566 champwr_adpcm_start = ((champwr_adpcm_start & 0x00ffff) | (data << 16)) & (romlen-1);
567 i = champwr_adpcm_start + 0x20;
568 while (i < romlen && (rom[i] || rom[i+1] || rom[i+2] || rom[i+3]))
569 i += 4;
570 length = i - champwr_adpcm_start;
571
572 ADPCM_play(0,champwr_adpcm_start,length*2);
573 }
574
575
576
577 static int trackx,tracky;
578
READ_HANDLER(horshoes_tracky_reset_r)579 static READ_HANDLER( horshoes_tracky_reset_r )
580 {
581 /* reset the trackball counter */
582 tracky = readinputport(4);
583 return 0;
584 }
585
READ_HANDLER(horshoes_trackx_reset_r)586 static READ_HANDLER( horshoes_trackx_reset_r )
587 {
588 /* reset the trackball counter */
589 trackx = readinputport(5);
590 return 0;
591 }
592
READ_HANDLER(horshoes_tracky_lo_r)593 static READ_HANDLER( horshoes_tracky_lo_r )
594 {
595 return (readinputport(4) - tracky) & 0xff;
596 }
597
READ_HANDLER(horshoes_tracky_hi_r)598 static READ_HANDLER( horshoes_tracky_hi_r )
599 {
600 return (readinputport(4) - tracky) >> 8;
601 }
602
READ_HANDLER(horshoes_trackx_lo_r)603 static READ_HANDLER( horshoes_trackx_lo_r )
604 {
605 return (readinputport(5) - trackx) & 0xff;
606 }
607
READ_HANDLER(horshoes_trackx_hi_r)608 static READ_HANDLER( horshoes_trackx_hi_r )
609 {
610 return (readinputport(5) - trackx) >> 8;
611 }
612
613
614
615
616 #define COMMON_BANKS_READ \
617 { 0x0000, 0x5fff, MRA_ROM }, \
618 { 0x6000, 0x7fff, MRA_BANK1 }, \
619 { 0xc000, 0xcfff, MRA_BANK2 }, \
620 { 0xd000, 0xdfff, MRA_BANK3 }, \
621 { 0xe000, 0xefff, MRA_BANK4 }, \
622 { 0xf000, 0xfdff, MRA_BANK5 }, \
623 { 0xfe00, 0xfe03, taitol_bankc_r }, \
624 { 0xfe04, 0xfe04, taitol_control_r }, \
625 { 0xff00, 0xff02, irq_adr_r }, \
626 { 0xff03, 0xff03, irq_enable_r }, \
627 { 0xff04, 0xff07, rambankswitch_r }, \
628 { 0xff08, 0xff08, rombankswitch_r }
629
630 #define COMMON_BANKS_WRITE \
631 { 0x0000, 0x7fff, MWA_ROM }, \
632 { 0xc000, 0xcfff, bank0_w }, \
633 { 0xd000, 0xdfff, bank1_w }, \
634 { 0xe000, 0xefff, bank2_w }, \
635 { 0xf000, 0xfdff, bank3_w }, \
636 { 0xfe00, 0xfe03, taitol_bankc_w }, \
637 { 0xfe04, 0xfe04, taitol_control_w }, \
638 { 0xff00, 0xff02, irq_adr_w }, \
639 { 0xff03, 0xff03, irq_enable_w }, \
640 { 0xff04, 0xff07, rambankswitch_w }, \
641 { 0xff08, 0xff08, rombankswitch_w }
642
643 #define COMMON_SINGLE_READ \
644 { 0xa000, 0xa000, YM2203_status_port_0_r }, \
645 { 0xa001, 0xa001, ym2203_data0_r }, \
646 { 0xa003, 0xa003, ym2203_data1_r }, \
647 { 0x8000, 0x9fff, MRA_RAM }
648
649 #define COMMON_SINGLE_WRITE \
650 { 0xa000, 0xa000, YM2203_control_port_0_w }, \
651 { 0xa001, 0xa001, YM2203_write_port_0_w }, \
652 { 0x8000, 0x9fff, MWA_RAM }
653
654
655
656 static struct MemoryReadAddress fhawk_readmem[] =
657 {
658 COMMON_BANKS_READ,
659 { 0x8000, 0x9fff, MRA_RAM },
660 { 0xa000, 0xbfff, MRA_RAM },
661 { -1 } /* end of table */
662 };
663
664 static struct MemoryWriteAddress fhawk_writemem[] =
665 {
666 COMMON_BANKS_WRITE,
667 { 0x8000, 0x9fff, MWA_RAM, &shared_ram },
668 { 0xa000, 0xbfff, MWA_RAM },
669 { -1 } /* end of table */
670 };
671
672 static struct MemoryReadAddress fhawk_2_readmem[] =
673 {
674 { 0x0000, 0x7fff, MRA_ROM },
675 { 0x8000, 0xbfff, MRA_BANK6 },
676 { 0xc800, 0xc800, MRA_NOP },
677 { 0xc801, 0xc801, taitosound_comm_r },
678 { 0xe000, 0xffff, shared_r },
679 { 0xd000, 0xd000, input_port_0_r },
680 { 0xd001, 0xd001, input_port_1_r },
681 { 0xd002, 0xd002, input_port_2_r },
682 { 0xd003, 0xd003, input_port_3_r },
683 { 0xd007, 0xd007, input_port_4_r },
684 { -1 } /* end of table */
685 };
686
687 static struct MemoryWriteAddress fhawk_2_writemem[] =
688 {
689 { 0x0000, 0xbfff, MWA_ROM },
690 { 0xc000, 0xc000, rombank2switch_w },
691 { 0xc800, 0xc800, taitosound_port_w },
692 { 0xc801, 0xc801, taitosound_comm_w },
693 { 0xd000, 0xd000, MWA_NOP }, // Direct copy of input port 0
694 { 0xd004, 0xd004, control2_w },
695 { 0xd005, 0xd006, MWA_NOP }, // Always 0
696 { 0xe000, 0xffff, shared_w },
697 { -1 } /* end of table */
698 };
699
700 static struct MemoryReadAddress fhawk_3_readmem[] =
701 {
702 { 0x0000, 0x3fff, MRA_ROM },
703 { 0x4000, 0x7fff, MRA_BANK7 },
704 { 0x8000, 0x9fff, MRA_RAM },
705 { 0xe000, 0xe000, MRA_NOP },
706 { 0xe001, 0xe001, taitosound_slave_comm_r },
707 { 0xf000, 0xf000, YM2203_status_port_0_r },
708 { -1 } /* end of table */
709 };
710
711 static struct MemoryWriteAddress fhawk_3_writemem[] =
712 {
713 { 0x0000, 0x7fff, MWA_ROM },
714 { 0x8000, 0x9fff, MWA_RAM },
715 { 0xe000, 0xe000, taitosound_slave_port_w },
716 { 0xe001, 0xe001, taitosound_slave_comm_w },
717 { 0xf000, 0xf000, YM2203_control_port_0_w },
718 { 0xf001, 0xf001, YM2203_write_port_0_w },
719 { -1 } /* end of table */
720 };
721
722 static struct MemoryReadAddress raimais_readmem[] =
723 {
724 COMMON_BANKS_READ,
725 { 0x8000, 0x87ff, MRA_RAM },
726 { 0x8800, 0x8800, mux_r },
727 { 0x8801, 0x8801, MRA_NOP }, // Watchdog or interrupt ack (value ignored)
728 { 0x8c00, 0x8c00, MRA_NOP },
729 { 0x8c01, 0x8c01, taitosound_comm_r },
730 { 0xa000, 0xbfff, MRA_RAM },
731 { -1 } /* end of table */
732 };
733 static struct MemoryWriteAddress raimais_writemem[] =
734 {
735 COMMON_BANKS_WRITE,
736 { 0x8000, 0x87ff, MWA_RAM, &shared_ram },
737 { 0x8800, 0x8800, mux_w },
738 { 0x8801, 0x8801, mux_ctrl_w },
739 { 0x8c00, 0x8c00, taitosound_port_w },
740 { 0x8c01, 0x8c01, taitosound_comm_w },
741 { 0xa000, 0xbfff, MWA_RAM },
742 { -1 } /* end of table */
743 };
744
745 static struct MemoryReadAddress raimais_2_readmem[] =
746 {
747 { 0x0000, 0xbfff, MRA_ROM },
748 { 0xc000, 0xdfff, MRA_RAM },
749 { 0xe000, 0xe7ff, shared_r },
750 { -1 } /* end of table */
751 };
752
753 static struct MemoryWriteAddress raimais_2_writemem[] =
754 {
755 { 0x0000, 0xbfff, MWA_ROM },
756 { 0xc000, 0xdfff, MWA_RAM },
757 { 0xe000, 0xe7ff, shared_w },
758 { -1 } /* end of table */
759 };
760
761
762 static struct MemoryReadAddress raimais_3_readmem[] =
763 {
764 { 0x0000, 0x3fff, MRA_ROM },
765 { 0x4000, 0x7fff, MRA_BANK7 },
766 { 0xc000, 0xdfff, MRA_RAM },
767 { 0xe000, 0xe000, YM2610_status_port_0_A_r },
768 { 0xe001, 0xe001, YM2610_read_port_0_r },
769 { 0xe002, 0xe002, YM2610_status_port_0_B_r },
770 { 0xe200, 0xe200, MRA_NOP },
771 { 0xe201, 0xe201, taitosound_slave_comm_r },
772 { -1 } /* end of table */
773 };
774
WRITE_HANDLER(sound_bankswitch_w)775 static WRITE_HANDLER( sound_bankswitch_w )
776 {
777 unsigned char *RAM = memory_region(REGION_CPU2);
778 int banknum = (data - 1) & 3;
779
780 cpu_setbank (7, &RAM [0x10000 + (banknum * 0x4000)]);
781 }
782
783 static struct MemoryWriteAddress raimais_3_writemem[] =
784 {
785 { 0x0000, 0x7fff, MWA_ROM },
786 { 0xc000, 0xdfff, MWA_RAM },
787 { 0xe000, 0xe000, YM2610_control_port_0_A_w },
788 { 0xe001, 0xe001, YM2610_data_port_0_A_w },
789 { 0xe002, 0xe002, YM2610_control_port_0_B_w },
790 { 0xe003, 0xe003, YM2610_data_port_0_B_w },
791 { 0xe200, 0xe200, taitosound_slave_port_w },
792 { 0xe201, 0xe201, taitosound_slave_comm_w },
793 { 0xe400, 0xe403, MWA_NOP }, /* pan */
794 { 0xe600, 0xe600, MWA_NOP }, /* ? */
795 { 0xee00, 0xee00, MWA_NOP }, /* ? */
796 { 0xf000, 0xf000, MWA_NOP }, /* ? */
797 { 0xf200, 0xf200, sound_bankswitch_w },
798 { -1 } /* end of table */
799 };
800
801
802 static struct MemoryReadAddress champwr_readmem[] =
803 {
804 COMMON_BANKS_READ,
805 { 0x8000, 0x9fff, MRA_RAM },
806 { 0xa000, 0xbfff, MRA_RAM },
807 { -1 } /* end of table */
808 };
809
810
811 static struct MemoryWriteAddress champwr_writemem[] =
812 {
813 COMMON_BANKS_WRITE,
814 { 0x8000, 0x9fff, MWA_RAM },
815 { 0xa000, 0xbfff, MWA_RAM, &shared_ram },
816 { -1 } /* end of table */
817 };
818
819 static struct MemoryReadAddress champwr_2_readmem[] =
820 {
821 { 0x0000, 0x7fff, MRA_ROM },
822 { 0x8000, 0xbfff, MRA_BANK6 },
823 { 0xc000, 0xdfff, shared_r },
824 { 0xe000, 0xe000, input_port_0_r },
825 { 0xe001, 0xe001, input_port_1_r },
826 { 0xe002, 0xe002, input_port_2_r },
827 { 0xe003, 0xe003, input_port_3_r },
828 { 0xe007, 0xe007, input_port_4_r },
829 { 0xe008, 0xe00f, MRA_NOP },
830 { 0xe800, 0xe800, MRA_NOP },
831 { 0xe801, 0xe801, taitosound_comm_r },
832 { 0xf000, 0xf000, rombank2switch_r },
833 { -1 } /* end of table */
834 };
835
836 static struct MemoryWriteAddress champwr_2_writemem[] =
837 {
838 { 0x0000, 0xbfff, MWA_ROM },
839 { 0xc000, 0xdfff, shared_w },
840 { 0xe000, 0xe000, MWA_NOP }, // Watchdog
841 { 0xe004, 0xe004, control2_w },
842 { 0xe800, 0xe800, taitosound_port_w },
843 { 0xe801, 0xe801, taitosound_comm_w },
844 { 0xf000, 0xf000, rombank2switch_w },
845 { -1 } /* end of table */
846 };
847
848 static struct MemoryReadAddress champwr_3_readmem[] =
849 {
850 { 0x0000, 0x3fff, MRA_ROM },
851 { 0x4000, 0x7fff, MRA_BANK7 },
852 { 0x8000, 0x8fff, MRA_RAM },
853 { 0x9000, 0x9000, YM2203_status_port_0_r },
854 { 0xa000, 0xa000, MRA_NOP },
855 { 0xa001, 0xa001, taitosound_slave_comm_r },
856 { -1 } /* end of table */
857 };
858
859 static struct MemoryWriteAddress champwr_3_writemem[] =
860 {
861 { 0x0000, 0x7fff, MWA_ROM },
862 { 0x8000, 0x8fff, MWA_RAM },
863 { 0x9000, 0x9000, YM2203_control_port_0_w },
864 { 0x9001, 0x9001, YM2203_write_port_0_w },
865 { 0xa000, 0xa000, taitosound_slave_port_w },
866 { 0xa001, 0xa001, taitosound_slave_comm_w },
867 { 0xb000, 0xb000, champwr_adpcm_hi_w },
868 { 0xc000, 0xc000, champwr_adpcm_lo_w },
869 { 0xd000, 0xd000, MWA_NOP }, /* ADPCM related */
870 { 0xe000, 0xe000, MWA_NOP }, /* ADPCM related */
871 { -1 } /* end of table */
872 };
873
874
875
876 static struct MemoryReadAddress kurikint_readmem[] =
877 {
878 COMMON_BANKS_READ,
879 { 0x8000, 0x9fff, MRA_RAM },
880 { 0xa000, 0xa7ff, MRA_RAM },
881 { 0xa800, 0xa800, mux_r },
882 { 0xa801, 0xa801, MRA_NOP }, // Watchdog or interrupt ack (value ignored)
883 { -1 } /* end of table */
884 };
885
886 static struct MemoryWriteAddress kurikint_writemem[] =
887 {
888 COMMON_BANKS_WRITE,
889 { 0x8000, 0x9fff, MWA_RAM },
890 { 0xa000, 0xa7ff, MWA_RAM, &shared_ram },
891 { 0xa800, 0xa800, mux_w },
892 { 0xa801, 0xa801, mux_ctrl_w },
893 { -1 } /* end of table */
894 };
895
896 static struct MemoryReadAddress kurikint_2_readmem[] =
897 {
898 { 0x0000, 0x7fff, MRA_ROM },
899 { 0xc000, 0xdfff, MRA_RAM },
900 { 0xe000, 0xe7ff, shared_r },
901 { 0xe800, 0xe800, YM2203_status_port_0_r },
902 #if 0
903 { 0xd000, 0xd000, input_port_0_r },
904 { 0xd001, 0xd001, input_port_1_r },
905 { 0xd002, 0xd002, input_port_2_r },
906 { 0xd003, 0xd003, input_port_3_r },
907 { 0xd007, 0xd007, input_port_4_r },
908 #endif
909 { -1 } /* end of table */
910 };
911
912 static struct MemoryWriteAddress kurikint_2_writemem[] =
913 {
914 { 0x0000, 0x7fff, MWA_ROM },
915 { 0xc000, 0xdfff, MWA_RAM },
916 { 0xe000, 0xe7ff, shared_w },
917 { 0xe800, 0xe800, YM2203_control_port_0_w },
918 { 0xe801, 0xe801, YM2203_write_port_0_w },
919 #if 0
920 { 0xc000, 0xc000, rombank2switch_w },
921 #endif
922 { -1 } /* end of table */
923 };
924
925
926
927 static struct MemoryReadAddress puzznic_readmem[] =
928 {
929 COMMON_BANKS_READ,
930 COMMON_SINGLE_READ,
931 { 0xa800, 0xa800, MRA_NOP }, // Watchdog
932 { 0xb000, 0xb7ff, MRA_RAM }, // Wrong, used to overcome protection
933 { 0xb800, 0xb800, mcu_data_r },
934 { 0xb801, 0xb801, mcu_control_r },
935 { -1 } /* end of table */
936 };
937
938 static struct MemoryWriteAddress puzznic_writemem[] =
939 {
940 COMMON_BANKS_WRITE,
941 COMMON_SINGLE_WRITE,
942 { 0xb000, 0xb7ff, MWA_RAM }, // Wrong, used to overcome protection
943 { 0xb800, 0xb800, mcu_data_w },
944 { 0xb801, 0xb801, mcu_control_w },
945 { 0xbc00, 0xbc00, MWA_NOP }, // Control register, function unknown
946 { -1 } /* end of table */
947 };
948
949
950 static struct MemoryReadAddress plotting_readmem[] =
951 {
952 COMMON_BANKS_READ,
953 COMMON_SINGLE_READ,
954 { -1 } /* end of table */
955 };
956
957 static struct MemoryWriteAddress plotting_writemem[] =
958 {
959 COMMON_BANKS_WRITE,
960 COMMON_SINGLE_WRITE,
961 { 0xa800, 0xa800, MWA_NOP }, // Watchdog or interrupt ack
962 { 0xb800, 0xb800, MWA_NOP }, // Control register, function unknown
963 { -1 } /* end of table */
964 };
965
966
967 static struct MemoryReadAddress palamed_readmem[] =
968 {
969 COMMON_BANKS_READ,
970 COMMON_SINGLE_READ,
971 { 0xa800, 0xa800, input_port_2_r },
972 { 0xa801, 0xa801, input_port_3_r },
973 { 0xa802, 0xa802, input_port_4_r },
974 { 0xb001, 0xb001, MRA_NOP }, // Watchdog or interrupt ack
975 { -1 } /* end of table */
976 };
977
978 static struct MemoryWriteAddress palamed_writemem[] =
979 {
980 COMMON_BANKS_WRITE,
981 COMMON_SINGLE_WRITE,
982 { 0xa803, 0xa803, MWA_NOP }, // Control register, function unknown
983 { 0xb000, 0xb000, MWA_NOP }, // Control register, function unknown (copy of 8822)
984 { -1 } /* end of table */
985 };
986
987
988 static struct MemoryReadAddress cachat_readmem[] =
989 {
990 COMMON_BANKS_READ,
991 COMMON_SINGLE_READ,
992 { 0xa800, 0xa800, input_port_2_r },
993 { 0xa801, 0xa801, input_port_3_r },
994 { 0xa802, 0xa802, input_port_4_r },
995 { 0xb001, 0xb001, MRA_NOP }, // Watchdog or interrupt ack (value ignored)
996 { 0xfff8, 0xfff8, rombankswitch_r },
997 { -1 } /* end of table */
998 };
999
1000 static struct MemoryWriteAddress cachat_writemem[] =
1001 {
1002 COMMON_BANKS_WRITE,
1003 COMMON_SINGLE_WRITE,
1004 { 0xa803, 0xa803, MWA_NOP }, // Control register, function unknown
1005 { 0xb000, 0xb000, MWA_NOP }, // Control register, function unknown
1006 { 0xfff8, 0xfff8, rombankswitch_w },
1007 { -1 } /* end of table */
1008 };
1009
1010
1011 static struct MemoryReadAddress horshoes_readmem[] =
1012 {
1013 COMMON_BANKS_READ,
1014 COMMON_SINGLE_READ,
1015 { 0xa800, 0xa800, horshoes_tracky_lo_r },
1016 { 0xa802, 0xa802, horshoes_tracky_reset_r },
1017 { 0xa803, 0xa803, horshoes_trackx_reset_r },
1018 { 0xa804, 0xa804, horshoes_tracky_hi_r },
1019 { 0xa808, 0xa808, horshoes_trackx_lo_r },
1020 { 0xa80c, 0xa80c, horshoes_trackx_hi_r },
1021 { 0xb801, 0xb801, MRA_NOP }, // Watchdog or interrupt ack
1022 { -1 } /* end of table */
1023 };
1024
1025 static struct MemoryWriteAddress horshoes_writemem[] =
1026 {
1027 COMMON_BANKS_WRITE,
1028 COMMON_SINGLE_WRITE,
1029 { 0xb802, 0xb802, horshoes_bankg_w },
1030 { 0xbc00, 0xbc00, MWA_NOP },
1031 { -1 } /* end of table */
1032 };
1033
1034
1035
1036 /***********************************************************
1037 INPUT PORTS, DIPs
1038 ***********************************************************/
1039
1040 #define TAITO_COINAGE_WORLD_8 \
1041 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) \
1042 PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
1043 PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
1044 PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
1045 PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
1046 PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) \
1047 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_2C ) ) \
1048 PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) ) \
1049 PORT_DIPSETTING( 0x40, DEF_STR( 1C_4C ) ) \
1050 PORT_DIPSETTING( 0x00, DEF_STR( 1C_6C ) )
1051
1052 #define TAITO_COINAGE_JAPAN_8 \
1053 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) \
1054 PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) \
1055 PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
1056 PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
1057 PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) ) \
1058 PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) \
1059 PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
1060 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) ) \
1061 PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
1062 PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
1063
1064 #define TAITO_COINAGE_JAPAN_NEW_8 \
1065 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) \
1066 PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
1067 PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) \
1068 PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
1069 PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) ) \
1070 PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) \
1071 PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
1072 PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
1073 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) ) \
1074 PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
1075
1076 #define TAITO_COINAGE_US_8 \
1077 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) ) \
1078 PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
1079 PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
1080 PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
1081 PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
1082 PORT_DIPNAME( 0xc0, 0xc0, "Price to Continue" ) \
1083 PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
1084 PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
1085 PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) ) \
1086 PORT_DIPSETTING( 0xc0, "Same as Start" )
1087
1088 #define TAITO_DIFFICULTY_8 \
1089 PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) \
1090 PORT_DIPSETTING( 0x02, "Easy" ) \
1091 PORT_DIPSETTING( 0x03, "Medium" ) \
1092 PORT_DIPSETTING( 0x01, "Hard" ) \
1093 PORT_DIPSETTING( 0x00, "Hardest" )
1094
1095 #define TAITO_L_PLAYERS_INPUT( player ) \
1096 PORT_START \
1097 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | player ) \
1098 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | player ) \
1099 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | player ) \
1100 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | player ) \
1101 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | player ) \
1102 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | player ) \
1103 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1104 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1105
1106 #define TAITO_L_SYSTEM_INPUT( type, impulse ) \
1107 PORT_START \
1108 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT ) \
1109 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 ) \
1110 PORT_BIT_IMPULSE( 0x04, type, IPT_COIN1, impulse ) \
1111 PORT_BIT_IMPULSE( 0x08, type, IPT_COIN2, impulse ) \
1112 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1113 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1114 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 ) \
1115 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
1116
1117 #define TAITO_L_DSWA_2_4 \
1118 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) ) \
1119 PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) \
1120 PORT_DIPSETTING( 0x00, DEF_STR( On ) ) \
1121 PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) \
1122 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) \
1123 PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) \
1124 PORT_DIPSETTING( 0x08, DEF_STR( On ) )
1125
1126 INPUT_PORTS_START( fhawk )
1127 PORT_START
1128 PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
1129 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
1130 PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
1131 TAITO_L_DSWA_2_4
1132 TAITO_COINAGE_JAPAN_8
1133
1134 PORT_START
1135 TAITO_DIFFICULTY_8
1136 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unused ) ) // all in manual
1137 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1138 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1139 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unused ) )
1140 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1141 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1142 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )
1143 PORT_DIPSETTING( 0x30, "3" )
1144 PORT_DIPSETTING( 0x20, "4" )
1145 PORT_DIPSETTING( 0x10, "5" )
1146 PORT_DIPSETTING( 0x00, "6" )
1147 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unused ) )
1148 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1149 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1150 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) )
1151 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1152 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1153
1154 TAITO_L_PLAYERS_INPUT( IPF_PLAYER1 )
1155
1156 TAITO_L_PLAYERS_INPUT( IPF_PLAYER2 )
1157
1158 TAITO_L_SYSTEM_INPUT( IP_ACTIVE_LOW, 4 )
1159 INPUT_PORTS_END
1160
1161 INPUT_PORTS_START( raimais )
1162 PORT_START
1163 PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
1164 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
1165 PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
1166 TAITO_L_DSWA_2_4
1167 TAITO_COINAGE_JAPAN_8
1168
1169 PORT_START
1170 TAITO_DIFFICULTY_8
1171 PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )
1172 PORT_DIPSETTING( 0x08, "80k and 160k" )
1173 PORT_DIPSETTING( 0x0c, "80k only" )
1174 PORT_DIPSETTING( 0x04, "160k only" )
1175 PORT_DIPSETTING( 0x00, "None" )
1176 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )
1177 PORT_DIPSETTING( 0x30, "3" )
1178 PORT_DIPSETTING( 0x20, "4" )
1179 PORT_DIPSETTING( 0x10, "5" )
1180 PORT_DIPSETTING( 0x00, "6" )
1181 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1182 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1183 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1184 PORT_DIPNAME( 0x80, 0x00, "Allow Continue" )
1185 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1186 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1187
1188 TAITO_L_PLAYERS_INPUT( IPF_PLAYER1 )
1189
1190 TAITO_L_PLAYERS_INPUT( IPF_PLAYER2 )
1191
1192 TAITO_L_SYSTEM_INPUT( IP_ACTIVE_HIGH, 1 )
1193 INPUT_PORTS_END
1194
1195 #define CHAMPWR_DSWB \
1196 PORT_START \
1197 TAITO_DIFFICULTY_8 \
1198 PORT_DIPNAME( 0x0c, 0x0c, "Time" ) \
1199 PORT_DIPSETTING( 0x08, "2 minutes" ) \
1200 PORT_DIPSETTING( 0x0c, "3 minutes" ) \
1201 PORT_DIPSETTING( 0x04, "4 minutes" ) \
1202 PORT_DIPSETTING( 0x00, "5 minutes" ) \
1203 PORT_DIPNAME( 0x30, 0x30, "1 minute Lenght" ) \
1204 PORT_DIPSETTING( 0x00, "30 sec" ) \
1205 PORT_DIPSETTING( 0x10, "40 sec" ) \
1206 PORT_DIPSETTING( 0x30, "50 sec" ) \
1207 PORT_DIPSETTING( 0x20, "60 sec" ) \
1208 PORT_DIPNAME( 0x40, 0x40, "Allow Continue" ) \
1209 PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) \
1210 PORT_DIPSETTING( 0x40, DEF_STR( On ) ) \
1211 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) ) \
1212 PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) \
1213 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1214
1215 #define CHAMPWR_INPUTS \
1216 PORT_START \
1217 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 ) \
1218 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 ) \
1219 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 ) \
1220 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 ) \
1221 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 ) \
1222 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 ) \
1223 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_TILT ) \
1224 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 ) \
1225 \
1226 PORT_START \
1227 PORT_BIT_IMPULSE( 0x01, IP_ACTIVE_LOW, IPT_COIN2, 1 ) \
1228 PORT_BIT_IMPULSE( 0x02, IP_ACTIVE_LOW, IPT_COIN1, 1 ) \
1229 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1230 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1231 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1232 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1233 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1234 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
1235 \
1236 PORT_START \
1237 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 ) \
1238 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 ) \
1239 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 ) \
1240 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 ) \
1241 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 ) \
1242 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 ) \
1243 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 ) \
1244 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1245
1246 INPUT_PORTS_START( champwr )
1247 PORT_START
1248 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) ) // all 2 in manual
1249 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1250 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1251 TAITO_L_DSWA_2_4
1252 TAITO_COINAGE_WORLD_8
1253
1254 CHAMPWR_DSWB
1255
1256 CHAMPWR_INPUTS
1257 INPUT_PORTS_END
1258
1259 INPUT_PORTS_START( champwrj )
1260 PORT_START
1261 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
1262 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1263 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1264 TAITO_L_DSWA_2_4
1265 TAITO_COINAGE_JAPAN_8
1266
1267 CHAMPWR_DSWB
1268
1269 CHAMPWR_INPUTS
1270 INPUT_PORTS_END
1271
1272 INPUT_PORTS_START( champwru )
1273 PORT_START
1274 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
1275 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1276 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1277 TAITO_L_DSWA_2_4
1278 TAITO_COINAGE_US_8
1279
1280 CHAMPWR_DSWB
1281
1282 CHAMPWR_INPUTS
1283 INPUT_PORTS_END
1284
1285 INPUT_PORTS_START( kurikint )
1286 PORT_START
1287 PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
1288 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
1289 PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
1290 TAITO_L_DSWA_2_4
1291 TAITO_COINAGE_WORLD_8
1292
1293 PORT_START
1294 TAITO_DIFFICULTY_8
1295 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1296 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1297 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1298 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1299 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1300 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1301 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1302 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1303 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1304 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1305 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1306 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1307 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1308 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1309 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1310 PORT_DIPNAME( 0x80, 0x80, "Allow Continue" )
1311 PORT_DIPSETTING( 0x80, "5 Times" )
1312 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1313
1314 TAITO_L_PLAYERS_INPUT( IPF_PLAYER1 )
1315
1316 TAITO_L_PLAYERS_INPUT( IPF_PLAYER2 )
1317
1318 TAITO_L_SYSTEM_INPUT( IP_ACTIVE_HIGH, 4 )
1319 INPUT_PORTS_END
1320
1321 INPUT_PORTS_START( kurikina )
1322 PORT_START
1323 PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
1324 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
1325 PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
1326 PORT_DIPNAME( 0x02, 0x00, DEF_STR( Flip_Screen ) )
1327 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1328 PORT_DIPSETTING( 0x02, DEF_STR( On ) )
1329 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1330 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1331 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1332 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1333 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1334 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1335 TAITO_COINAGE_WORLD_8
1336
1337 PORT_START
1338 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1339 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1340 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1341 PORT_BITX( 0x02, 0x02, IPT_DIPSWITCH_NAME | IPF_CHEAT, "Invulnerability", IP_KEY_NONE, IP_JOY_NONE )
1342 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1343 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1344 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1345 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1346 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1347 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1348 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1349 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1350 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1351 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1352 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1353 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1354 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1355 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1356 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1357 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1358 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1359 PORT_BITX( 0x80, 0x80, IPT_DIPSWITCH_NAME | IPF_CHEAT, "Slow Motion", IP_KEY_NONE, IP_JOY_NONE )
1360 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1361 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1362
1363 TAITO_L_PLAYERS_INPUT( IPF_PLAYER1 )
1364
1365 TAITO_L_PLAYERS_INPUT( IPF_PLAYER2 )
1366
1367 TAITO_L_SYSTEM_INPUT( IP_ACTIVE_HIGH, 4 )
1368 INPUT_PORTS_END
1369
1370 INPUT_PORTS_START( puzznic )
1371 PORT_START
1372 PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
1373 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
1374 PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
1375 TAITO_L_DSWA_2_4
1376 /* There is no Coin B in the Manuals */
1377 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) )
1378 PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
1379 PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
1380 PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
1381 PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
1382 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unused ) )
1383 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1384 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1385 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) )
1386 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1387 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1388
1389 PORT_START
1390 /* Difficulty controls the Timer Speed (how many seconds are there in a minute) */
1391 TAITO_DIFFICULTY_8
1392 PORT_DIPNAME( 0x0c, 0x0c, "Retries" )
1393 PORT_DIPSETTING( 0x00, "0" )
1394 PORT_DIPSETTING( 0x04, "1" )
1395 PORT_DIPSETTING( 0x0c, "2" )
1396 PORT_DIPSETTING( 0x08, "3" )
1397 PORT_DIPNAME( 0x10, 0x10, "Bombs" )
1398 PORT_DIPSETTING( 0x10, "0" )
1399 PORT_DIPSETTING( 0x00, "2" )
1400 PORT_DIPNAME( 0x20, 0x20, "Girls" )
1401 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1402 PORT_DIPSETTING( 0x20, DEF_STR( Yes ) )
1403 PORT_DIPNAME( 0xc0, 0xc0, "Terms of Replay" )
1404 PORT_DIPSETTING( 0x40, "Stage one step back/Timer continuous" )
1405 PORT_DIPSETTING( 0xc0, "Stage reset to start/Timer continuous" )
1406 PORT_DIPSETTING( 0x80, "Stage reset to start/Timer reset to start" )
1407 // PORT_DIPSETTING( 0x00, "No Use" )
1408
1409 PORT_START
1410 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1411 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN1 )
1412 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
1413 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1414 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 )
1415 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 )
1416 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
1417 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1418
1419 PORT_START
1420 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
1421 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
1422 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
1423 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
1424 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
1425 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
1426 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
1427 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
1428
1429 PORT_START /* Not read yet. There is no Coin_B in manual */
1430 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1431 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1432 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1433 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1434 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1435 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1436 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1437 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1438 INPUT_PORTS_END
1439
1440 INPUT_PORTS_START( plotting )
1441 PORT_START
1442 PORT_DIPNAME( 0x01, 0x01, "Max Players" )
1443 PORT_DIPSETTING( 0x00, "1" )
1444 PORT_DIPSETTING( 0x01, "2" )
1445 TAITO_L_DSWA_2_4
1446 TAITO_COINAGE_WORLD_8
1447
1448 PORT_START
1449 TAITO_DIFFICULTY_8
1450 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1451 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1452 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1453 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1454 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1455 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1456 PORT_DIPNAME( 0x30, 0x30, "Misses" )
1457 PORT_DIPSETTING( 0x20, "1" )
1458 PORT_DIPSETTING( 0x30, "2" )
1459 PORT_DIPSETTING( 0x10, "3" )
1460 PORT_DIPSETTING( 0x00, "4" )
1461 PORT_DIPNAME( 0x40, 0x40, "Allow Continue" )
1462 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1463 PORT_DIPSETTING( 0x40, DEF_STR( On ) )
1464 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1465 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1466 PORT_DIPSETTING( 0x80, DEF_STR( On ) )
1467
1468 PORT_START
1469 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1470 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN1 )
1471 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
1472 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1473 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 )
1474 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 )
1475 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
1476 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1477
1478 PORT_START
1479 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
1480 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1481 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
1482 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
1483 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
1484 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
1485 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
1486 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
1487 INPUT_PORTS_END
1488
1489 INPUT_PORTS_START( palamed )
1490 PORT_START
1491 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1492 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1493 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1494 TAITO_L_DSWA_2_4
1495 TAITO_COINAGE_JAPAN_NEW_8
1496
1497 PORT_START
1498 /* Difficulty controls how faster falls the dice lines */
1499 TAITO_DIFFICULTY_8
1500 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1501 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1502 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1503 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1504 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1505 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1506 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1507 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1508 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1509 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1510 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1511 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1512 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1513 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1514 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1515 PORT_DIPNAME( 0x80, 0x80, "Versus Mode" )
1516 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1517 PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
1518
1519 PORT_START
1520 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1521 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_TILT )
1522 PORT_BIT_IMPULSE( 0x04, IP_ACTIVE_LOW, IPT_COIN1, 1 )
1523 PORT_BIT_IMPULSE( 0x08, IP_ACTIVE_LOW, IPT_COIN2, 1 )
1524 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
1525 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1526 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1527 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
1528
1529 PORT_START
1530 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1531 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 )
1532 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 )
1533 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
1534 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
1535 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
1536 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
1537 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
1538
1539 PORT_START
1540 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
1541 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
1542 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1543 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1544 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1545 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1546 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1547 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1548 INPUT_PORTS_END
1549
1550 INPUT_PORTS_START( cachat )
1551 PORT_START
1552 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1553 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1554 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1555 PORT_DIPNAME( 0x02, 0x00, DEF_STR( Flip_Screen ) )
1556 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1557 PORT_DIPSETTING( 0x02, DEF_STR( On ) )
1558 PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
1559 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
1560 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1561 PORT_DIPSETTING( 0x08, DEF_STR( On ) )
1562 TAITO_COINAGE_JAPAN_NEW_8
1563
1564 PORT_START
1565 TAITO_DIFFICULTY_8
1566 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1567 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1568 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1569 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1570 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1571 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1572 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1573 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1574 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1575 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1576 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1577 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1578 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1579 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1580 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1581 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1582 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1583 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1584
1585 PORT_START
1586 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1587 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_TILT )
1588 PORT_BIT_IMPULSE( 0x04, IP_ACTIVE_LOW, IPT_COIN1, 1 )
1589 PORT_BIT_IMPULSE( 0x08, IP_ACTIVE_LOW, IPT_COIN2, 1 )
1590 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
1591 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1592 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1593 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
1594
1595 PORT_START
1596 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1597 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 )
1598 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 )
1599 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
1600 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
1601 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
1602 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
1603 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
1604
1605 PORT_START
1606 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
1607 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
1608 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1609 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1610 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1611 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1612 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1613 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1614 INPUT_PORTS_END
1615
1616 INPUT_PORTS_START( tubeit )
1617 PORT_START
1618 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1619 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1620 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1621 PORT_DIPNAME( 0x02, 0x00, DEF_STR( Flip_Screen ) )
1622 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1623 PORT_DIPSETTING( 0x02, DEF_STR( On ) )
1624 PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
1625 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
1626 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1627 PORT_DIPSETTING( 0x08, DEF_STR( On ) )
1628 TAITO_COINAGE_WORLD_8
1629
1630 PORT_START
1631 TAITO_DIFFICULTY_8
1632 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1633 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1634 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1635 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1636 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1637 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1638 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1639 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1640 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1641 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1642 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1643 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1644 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1645 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1646 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1647 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1648 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1649 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1650
1651 PORT_START
1652 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1653 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_TILT )
1654 PORT_BIT_IMPULSE( 0x04, IP_ACTIVE_LOW, IPT_COIN1, 1 )
1655 PORT_BIT_IMPULSE( 0x08, IP_ACTIVE_LOW, IPT_COIN2, 1 )
1656 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
1657 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1658 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1659 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
1660
1661 PORT_START
1662 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1663 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 )
1664 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 )
1665 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
1666 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
1667 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
1668 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
1669 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
1670
1671 PORT_START
1672 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
1673 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
1674 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1675 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1676 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1677 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1678 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1679 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1680 INPUT_PORTS_END
1681
1682 INPUT_PORTS_START( horshoes )
1683 PORT_START
1684 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1685 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1686 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1687 TAITO_L_DSWA_2_4
1688 /* The Coinage is the same as US, but it has no Continue Price feature */
1689 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) )
1690 PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) )
1691 PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) )
1692 PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) )
1693 PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
1694 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1695 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1696 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1697 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1698 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1699 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1700
1701 PORT_START
1702 /* Not for sure, the CPU seems to play better when set to Hardest */
1703 TAITO_DIFFICULTY_8
1704 PORT_DIPNAME( 0x04, 0x04, "Time" )
1705 PORT_DIPSETTING( 0x00, "20 sec" )
1706 PORT_DIPSETTING( 0x04, "30 sec" )
1707 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1708 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1709 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1710 PORT_DIPNAME( 0x10, 0x10, "Innings" )
1711 PORT_DIPSETTING( 0x10, "3 per Credit" )
1712 PORT_DIPSETTING( 0x00, "9 per Credit" )
1713 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1714 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1715 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1716 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1717 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1718 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1719 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1720 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1721 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1722
1723 PORT_START
1724 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1725 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN1 )
1726 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1727 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1728 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1729 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1730 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1731 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1732
1733 PORT_START
1734 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
1735 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
1736 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1737 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1738 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1739 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1740 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1741 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
1742
1743 PORT_START
1744 PORT_ANALOG( 0xffff, 0x0000, IPT_TRACKBALL_Y | IPF_REVERSE, 50, 30, 0, 0 )
1745
1746 PORT_START
1747 PORT_ANALOG( 0xffff, 0x0000, IPT_TRACKBALL_X, 50, 30, 0, 0 )
1748 INPUT_PORTS_END
1749
1750 INPUT_PORTS_START( plgirls )
1751 PORT_START
1752 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Demo_Sounds ) )
1753 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1754 PORT_DIPSETTING( 0x01, DEF_STR( On ) )
1755 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
1756 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1757 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1758 PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
1759 PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coinage ) )
1760 PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) )
1761 PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) )
1762 PORT_DIPSETTING( 0x18, DEF_STR( 2C_1C ) )
1763 PORT_DIPSETTING( 0x38, DEF_STR( 1C_1C ) )
1764 PORT_DIPSETTING( 0x08, DEF_STR( 2C_3C ) )
1765 PORT_DIPSETTING( 0x28, DEF_STR( 1C_2C ) )
1766 PORT_DIPSETTING( 0x20, DEF_STR( 1C_4C ) )
1767 // PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
1768 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1769 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1770 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1771 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1772 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1773 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1774
1775 PORT_START
1776 /* Difficulty controls the Ball Speed */
1777 TAITO_DIFFICULTY_8
1778 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1779 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1780 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1781 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1782 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1783 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1784 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1785 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1786 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1787 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1788 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1789 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1790 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1791 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1792 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1793 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1794 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1795 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1796
1797 PORT_START
1798 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1799 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_TILT )
1800 PORT_BIT_IMPULSE( 0x04, IP_ACTIVE_LOW, IPT_COIN1, 1 )
1801 PORT_BIT_IMPULSE( 0x08, IP_ACTIVE_LOW, IPT_COIN2, 1 )
1802 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
1803 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1804 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1805 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
1806
1807 PORT_START
1808 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1809 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 )
1810 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 )
1811 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
1812 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
1813 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
1814 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
1815 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
1816
1817 PORT_START
1818 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
1819 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
1820 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1821 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1822 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1823 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1824 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1825 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1826 INPUT_PORTS_END
1827
1828 INPUT_PORTS_START( plgirls2 )
1829 PORT_START
1830 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1831 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1832 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1833 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
1834 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1835 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1836 PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
1837 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1838 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1839 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1840 TAITO_COINAGE_JAPAN_8
1841
1842 PORT_START
1843 /* Difficulty controls the number of hits requiered to destroy enemies */
1844 TAITO_DIFFICULTY_8
1845 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1846 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1847 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1848 PORT_DIPNAME( 0x18, 0x18, "Life" )
1849 PORT_DIPSETTING( 0x10, "3/2/3" )
1850 PORT_DIPSETTING( 0x18, "4/3/4" )
1851 PORT_DIPSETTING( 0x08, "5/4/5" )
1852 PORT_DIPSETTING( 0x00, "6/5/6" )
1853 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1854 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1855 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1856 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1857 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1858 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1859 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1860 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1861 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1862
1863 PORT_START
1864 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1865 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_TILT )
1866 PORT_BIT_IMPULSE( 0x04, IP_ACTIVE_LOW, IPT_COIN1, 1 )
1867 PORT_BIT_IMPULSE( 0x08, IP_ACTIVE_LOW, IPT_COIN2, 1 )
1868 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
1869 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1870 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1871 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
1872
1873 PORT_START
1874 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1875 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 )
1876 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 )
1877 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
1878 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
1879 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
1880 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
1881 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
1882
1883 PORT_START
1884 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
1885 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
1886 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1887 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1888 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1889 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1890 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1891 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1892 INPUT_PORTS_END
1893
1894 INPUT_PORTS_START( cubybop )
1895 PORT_START
1896 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1897 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1898 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1899 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
1900 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1901 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1902 PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
1903 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
1904 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
1905 PORT_DIPSETTING( 0x08, DEF_STR( On ) )
1906 TAITO_COINAGE_JAPAN_NEW_8
1907
1908 PORT_START
1909 TAITO_DIFFICULTY_8
1910 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1911 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1912 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1913 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1914 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1915 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1916 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1917 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1918 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1919 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1920 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1921 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1922 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1923 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1924 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1925 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1926 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1927 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1928
1929 PORT_START
1930 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
1931 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_TILT )
1932 PORT_BIT_IMPULSE( 0x04, IP_ACTIVE_LOW, IPT_COIN1, 1 )
1933 PORT_BIT_IMPULSE( 0x08, IP_ACTIVE_LOW, IPT_COIN2, 1 )
1934 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
1935 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
1936 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
1937 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
1938
1939 PORT_START
1940 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1 )
1941 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1 )
1942 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1 )
1943 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
1944 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
1945 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
1946 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
1947 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
1948
1949 PORT_START
1950 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
1951 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
1952 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1953 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1954 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1955 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1956 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1957 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1958 INPUT_PORTS_END
1959
1960
1961
1962
1963 static struct GfxLayout bg1_layout =
1964 {
1965 8, 8,
1966 RGN_FRAC(1,2),
1967 4,
1968 { RGN_FRAC(1,2)+0, RGN_FRAC(1,2)+4, 0, 4 },
1969 { 3, 2, 1, 0, 8+3, 8+2, 8+1, 8+0 },
1970 { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16 },
1971 8*8*2
1972 };
1973
1974 static struct GfxLayout bg2_layout =
1975 {
1976 8, 8,
1977 RGN_FRAC(1,1),
1978 4,
1979 { 8, 12, 0, 4 },
1980 { 3, 2, 1, 0, 19, 18, 17, 16 },
1981 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
1982 8*8*4
1983 };
1984
1985 #define O 8*8*2
1986 #define O2 2*O
1987 static struct GfxLayout sp1_layout =
1988 {
1989 16, 16,
1990 RGN_FRAC(1,2),
1991 4,
1992 { RGN_FRAC(1,2)+0, RGN_FRAC(1,2)+4, 0, 4 },
1993 { 3, 2, 1, 0, 8+3, 8+2, 8+1, 8+0, O+3, O+2, O+1, O+0, O+8+3, O+8+2, O+8+1, O+8+0 },
1994 { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16, O2+0*16, O2+1*16, O2+2*16, O2+3*16, O2+4*16, O2+5*16, O2+6*16, O2+7*16 },
1995 8*8*2*4
1996 };
1997 #undef O
1998 #undef O2
1999
2000 #define O 8*8*4
2001 #define O2 2*O
2002 static struct GfxLayout sp2_layout =
2003 {
2004 16, 16,
2005 RGN_FRAC(1,1),
2006 4,
2007 { 8, 12, 0, 4 },
2008 { 3, 2, 1, 0, 19, 18, 17, 16, O+3, O+2, O+1, O+0, O+19, O+18, O+17, O+16 },
2009 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32, O2+0*32, O2+1*32, O2+2*32, O2+3*32, O2+4*32, O2+5*32, O2+6*32, O2+7*32 },
2010 8*8*4*4
2011 };
2012 #undef O
2013 #undef O2
2014
2015 static struct GfxLayout char_layout =
2016 {
2017 8, 8,
2018 1024,
2019 4,
2020 { 8, 12, 0, 4 },
2021 { 3, 2, 1, 0, 19, 18, 17, 16},
2022 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
2023 8*8*4
2024 };
2025
2026 static struct GfxDecodeInfo gfxdecodeinfo1[] =
2027 {
2028 { REGION_GFX1, 0, &bg1_layout, 0, 16 },
2029 { REGION_GFX1, 0, &sp1_layout, 0, 16 },
2030 { 0, 0, &char_layout, 0, 16 }, // Ram-based
2031 { -1 }
2032 };
2033
2034 static struct GfxDecodeInfo gfxdecodeinfo2[] =
2035 {
2036 { REGION_GFX1, 0, &bg2_layout, 0, 16 },
2037 { REGION_GFX1, 0, &sp2_layout, 0, 16 },
2038 { 0, 0, &char_layout, 0, 16 }, // Ram-based
2039 { -1 }
2040 };
2041
2042
2043
irqhandler(int irq)2044 static void irqhandler(int irq)
2045 {
2046 cpu_set_irq_line(1,0,irq ? ASSERT_LINE : CLEAR_LINE);
2047 }
2048
WRITE_HANDLER(portA_w)2049 static WRITE_HANDLER( portA_w )
2050 {
2051 static int cur_bank = 0;
2052
2053 if (cur_bank != (data & 0x03) )
2054 {
2055 int bankaddress;
2056 unsigned char *RAM = memory_region(REGION_CPU2);
2057
2058 cur_bank = data & 0x03;
2059 bankaddress = 0x10000 + (cur_bank-1) * 0x4000;
2060 cpu_setbank(7,&RAM[bankaddress]);
2061 //logerror ("YM2203 bank change val=%02x pc=%04x \n",cur_bank, cpu_get_pc() );
2062 }
2063 }
2064
2065 static struct YM2203interface ym2203_interface_triple =
2066 {
2067 1, /* 1 chip */
2068 3000000, /* ??? */
2069 { YM2203_VOL(80,20) },
2070 { 0 },
2071 { 0 },
2072 { portA_w },
2073 { 0 },
2074 { irqhandler }
2075 };
2076
2077 static struct ADPCMinterface adpcm_interface =
2078 {
2079 1, /* 1 channel */
2080 8000, /* 8000Hz playback? */
2081 REGION_SOUND1, /* memory region */
2082 0,
2083 { 80 } /* volume */
2084 };
2085
2086
2087 static struct YM2610interface ym2610_interface =
2088 {
2089 1, /* 1 chip */
2090 8000000, /* 8 MHz */
2091 { 30 },
2092 { 0 },
2093 { 0 },
2094 { 0 },
2095 { 0 },
2096 { irqhandler },
2097 { REGION_SOUND1 },
2098 { REGION_SOUND1 },
2099 { YM3012_VOL(60,MIXER_PAN_LEFT,60,MIXER_PAN_RIGHT) }
2100 };
2101
2102 static struct YM2203interface ym2203_interface_double =
2103 {
2104 1, /* 1 chip */
2105 3000000, /* ??? */
2106 { YM2203_VOL(80,20) },
2107 { 0 },
2108 { 0 },
2109 { 0 },
2110 { 0 },
2111 { 0 }
2112 };
2113
2114 static struct YM2203interface ym2203_interface_single =
2115 {
2116 1, /* 1 chip */
2117 3000000, /* ??? */
2118 { YM2203_VOL(80,20) },
2119 { portA_r },
2120 { portB_r },
2121 { 0 },
2122 { 0 },
2123 { 0 }
2124 };
2125
2126
2127 #define MCH_TRIPLE(name) \
2128 static struct MachineDriver machine_driver_##name = \
2129 { \
2130 { \
2131 { \
2132 CPU_Z80, \
2133 6665280, /* ? xtal is 13.33056 */ \
2134 name ## _readmem, name ## _writemem, 0, 0, \
2135 vbl_interrupt,3 \
2136 }, \
2137 { \
2138 CPU_Z80 | CPU_AUDIO_CPU, \
2139 4000000, \
2140 name ## _3_readmem, name ## _3_writemem, 0, 0, \
2141 ignore_interrupt, 0 \
2142 }, \
2143 { \
2144 CPU_Z80, \
2145 4000000, \
2146 name ## _2_readmem, name ## _2_writemem, 0, 0, \
2147 interrupt, 1 \
2148 } \
2149 }, \
2150 60, DEFAULT_60HZ_VBLANK_DURATION, \
2151 100, \
2152 name ## _init, \
2153 \
2154 40*8, 32*8, { 0*8, 40*8-1, 2*8, 30*8-1 }, \
2155 gfxdecodeinfo2, \
2156 256, 256, \
2157 0, \
2158 \
2159 VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE, \
2160 taitol_eof_callback, \
2161 taitol_vh_start, \
2162 0, \
2163 taitol_vh_screenrefresh, \
2164 \
2165 0,0,0,0, \
2166 { \
2167 { \
2168 SOUND_YM2203, \
2169 &ym2203_interface_triple \
2170 } \
2171 } \
2172 };
2173
2174 #define MCH_TRIPLE_ADPCM(name) \
2175 static struct MachineDriver machine_driver_##name = \
2176 { \
2177 { \
2178 { \
2179 CPU_Z80, \
2180 6665280, /* ? xtal is 13.33056 */ \
2181 name ## _readmem, name ## _writemem, 0, 0, \
2182 vbl_interrupt,3 \
2183 }, \
2184 { \
2185 CPU_Z80 | CPU_AUDIO_CPU, \
2186 4000000, \
2187 name ## _3_readmem, name ## _3_writemem, 0, 0, \
2188 ignore_interrupt, 0 \
2189 }, \
2190 { \
2191 CPU_Z80, \
2192 4000000, \
2193 name ## _2_readmem, name ## _2_writemem, 0, 0, \
2194 interrupt, 1 \
2195 } \
2196 }, \
2197 60, DEFAULT_60HZ_VBLANK_DURATION, \
2198 100, \
2199 name ## _init, \
2200 \
2201 40*8, 32*8, { 0*8, 40*8-1, 2*8, 30*8-1 }, \
2202 gfxdecodeinfo2, \
2203 256, 256, \
2204 0, \
2205 \
2206 VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE, \
2207 taitol_eof_callback, \
2208 taitol_vh_start, \
2209 0, \
2210 taitol_vh_screenrefresh, \
2211 \
2212 0,0,0,0, \
2213 { \
2214 { \
2215 SOUND_YM2203, \
2216 &ym2203_interface_triple \
2217 }, \
2218 { \
2219 SOUND_ADPCM, \
2220 &adpcm_interface \
2221 } \
2222 } \
2223 };
2224
2225 #define MCH_TRIPLE_2610(name) \
2226 static struct MachineDriver machine_driver_##name = \
2227 { \
2228 { \
2229 { \
2230 CPU_Z80, \
2231 6665280, /* ? xtal is 13.33056 */ \
2232 name ## _readmem, name ## _writemem, 0, 0, \
2233 vbl_interrupt,3 \
2234 }, \
2235 { \
2236 CPU_Z80 | CPU_AUDIO_CPU, \
2237 4000000, \
2238 name ## _3_readmem, name ## _3_writemem, 0, 0, \
2239 ignore_interrupt, 0 \
2240 }, \
2241 { \
2242 CPU_Z80, \
2243 4000000, \
2244 name ## _2_readmem, name ## _2_writemem, 0, 0, \
2245 interrupt, 1 \
2246 } \
2247 }, \
2248 60, DEFAULT_60HZ_VBLANK_DURATION, \
2249 100, \
2250 name ## _init, \
2251 \
2252 40*8, 32*8, { 0*8, 40*8-1, 2*8, 30*8-1 }, \
2253 gfxdecodeinfo2, \
2254 256, 256, \
2255 0, \
2256 \
2257 VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE, \
2258 taitol_eof_callback, \
2259 taitol_vh_start, \
2260 0, \
2261 taitol_vh_screenrefresh, \
2262 \
2263 0,0,0,0, \
2264 { \
2265 { \
2266 SOUND_YM2610, \
2267 &ym2610_interface \
2268 } \
2269 } \
2270 };
2271
2272 #define MCH_DOUBLE(name) \
2273 static struct MachineDriver machine_driver_##name = \
2274 { \
2275 { \
2276 { \
2277 CPU_Z80, \
2278 6665280, /* ? xtal is 13.33056 */ \
2279 name ## _readmem, name ## _writemem, 0, 0, \
2280 vbl_interrupt,3 \
2281 }, \
2282 { \
2283 CPU_Z80, \
2284 4000000, \
2285 name ## _2_readmem, name ## _2_writemem, 0, 0, \
2286 interrupt, 1 \
2287 } \
2288 }, \
2289 60, DEFAULT_60HZ_VBLANK_DURATION, \
2290 100, \
2291 name ## _init, \
2292 \
2293 40*8, 32*8, { 0*8, 40*8-1, 2*8, 30*8-1 }, \
2294 gfxdecodeinfo2, \
2295 256, 256, \
2296 0, \
2297 \
2298 VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE, \
2299 taitol_eof_callback, \
2300 taitol_vh_start, \
2301 0, \
2302 taitol_vh_screenrefresh, \
2303 \
2304 0,0,0,0, \
2305 { \
2306 { \
2307 SOUND_YM2203, \
2308 &ym2203_interface_double \
2309 } \
2310 } \
2311 };
2312
2313 #define MCH_SINGLE(name) \
2314 static struct MachineDriver machine_driver_##name = \
2315 { \
2316 { \
2317 { \
2318 CPU_Z80, \
2319 6665280, /* ? xtal is 13.33056 */ \
2320 name ## _readmem, name ## _writemem, 0, 0, \
2321 vbl_interrupt,3 \
2322 } \
2323 }, \
2324 60, DEFAULT_60HZ_VBLANK_DURATION, \
2325 1, \
2326 name ## _init, \
2327 \
2328 40*8, 32*8, { 0*8, 40*8-1, 2*8, 30*8-1 }, \
2329 gfxdecodeinfo1, \
2330 256, 256, \
2331 0, \
2332 \
2333 VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE, \
2334 taitol_eof_callback, \
2335 taitol_vh_start, \
2336 0, \
2337 taitol_vh_screenrefresh, \
2338 \
2339 0,0,0,0, \
2340 { \
2341 { \
2342 SOUND_YM2203, \
2343 &ym2203_interface_single \
2344 } \
2345 } \
2346 };
2347
2348
2349 MCH_TRIPLE_2610(raimais)
MCH_TRIPLE(fhawk)2350 MCH_TRIPLE(fhawk)
2351 MCH_TRIPLE_ADPCM(champwr)
2352
2353 MCH_DOUBLE(kurikint)
2354
2355 MCH_SINGLE(plotting)
2356 MCH_SINGLE(puzznic)
2357 MCH_SINGLE(horshoes)
2358 MCH_SINGLE(palamed)
2359 MCH_SINGLE(cachat)
2360
2361
2362
2363 ROM_START( raimais )
2364 ROM_REGION( 0xb0000, REGION_CPU1 )
2365 ROM_LOAD( "b36-08-1.bin", 0x00000, 0x20000, 0x6cc8f79f )
2366 ROM_RELOAD( 0x10000, 0x20000 )
2367 ROM_LOAD( "b36-09.bin", 0x30000, 0x20000, 0x9c466e43 )
2368
2369 ROM_REGION( 0x1c000, REGION_CPU2 ) /* sound (sndhrdw/rastan.c wants it as #2 */
2370 ROM_LOAD( "b36-06.bin", 0x00000, 0x4000, 0x29bbc4f8 )
2371 ROM_CONTINUE( 0x10000, 0xc000 )
2372
2373 ROM_REGION( 0x10000, REGION_CPU3 )
2374 ROM_LOAD( "b36-07.bin", 0x00000, 0x10000, 0x4f3737e6 )
2375
2376 ROM_REGION( 0x100000, REGION_GFX1| REGIONFLAG_DISPOSE )
2377 ROM_LOAD( "b36-01.bin", 0x00000, 0x80000, 0x89355cb2 )
2378 ROM_LOAD( "b36-02.bin", 0x80000, 0x80000, 0xe71da5db )
2379
2380 ROM_REGION( 0x80000, REGION_SOUND1 )
2381 ROM_LOAD( "b36-03.bin", 0x00000, 0x80000, 0x96166516 )
2382 ROM_END
2383
2384 ROM_START( fhawk )
2385 ROM_REGION( 0xb0000, REGION_CPU1 )
2386 ROM_LOAD( "b70-07.bin", 0x00000, 0x20000, 0x939114af )
2387 ROM_RELOAD( 0x10000, 0x20000 )
2388 ROM_LOAD( "b70-03.bin", 0x30000, 0x80000, 0x42d5a9b8 )
2389
2390 ROM_REGION( 0x1c000, REGION_CPU2 ) /* sound (sndhrdw/rastan.c wants it as #2 */
2391 ROM_LOAD( "b70-09.bin", 0x00000, 0x4000, 0x85cccaa2 )
2392 ROM_CONTINUE( 0x10000, 0xc000 )
2393
2394 ROM_REGION( 0x30000, REGION_CPU3 )
2395 ROM_LOAD( "b70-08.bin", 0x00000, 0x20000, 0x4d795f48 )
2396 ROM_RELOAD( 0x10000, 0x20000 )
2397
2398 ROM_REGION( 0x100000, REGION_GFX1| REGIONFLAG_DISPOSE )
2399 ROM_LOAD( "b70-01.bin", 0x00000, 0x80000, 0xfcdf67e2 )
2400 ROM_LOAD( "b70-02.bin", 0x80000, 0x80000, 0x35f7172e )
2401 ROM_END
2402
2403 ROM_START( champwr )
2404 ROM_REGION( 0xf0000, REGION_CPU1 )
2405 ROM_LOAD( "c01-13.rom", 0x00000, 0x20000, 0x7ef47525 )
2406 ROM_RELOAD( 0x10000, 0x20000 )
2407 ROM_LOAD( "c01-04.rom", 0x30000, 0x20000, 0x358bd076 )
2408
2409 ROM_REGION( 0x1c000, REGION_CPU2 ) /* sound (sndhrdw/rastan.c wants it as #2 */
2410 ROM_LOAD( "c01-08.rom", 0x00000, 0x4000, 0x810efff8 )
2411 ROM_CONTINUE( 0x10000, 0xc000 )
2412
2413 ROM_REGION( 0x30000, REGION_CPU3 )
2414 ROM_LOAD( "c01-07.rom", 0x00000, 0x20000, 0x5117c98f )
2415 ROM_RELOAD( 0x10000, 0x20000 )
2416
2417 ROM_REGION( 0x180000, REGION_GFX1| REGIONFLAG_DISPOSE )
2418 ROM_LOAD( "c01-01.rom", 0x000000, 0x80000, 0xf302e6e9 )
2419 ROM_LOAD( "c01-02.rom", 0x080000, 0x80000, 0x1e0476c4 )
2420 ROM_LOAD( "c01-03.rom", 0x100000, 0x80000, 0x2a142dbc )
2421
2422 ROM_REGION( 0x20000, REGION_SOUND1 ) /* ADPCM samples */
2423 ROM_LOAD( "c01-05.rom", 0x00000, 0x20000, 0x22efad4a )
2424 ROM_END
2425
2426 ROM_START( champwru )
2427 ROM_REGION( 0xf0000, REGION_CPU1 )
2428 ROM_LOAD( "c01-12.rom", 0x00000, 0x20000, 0x09f345b3 )
2429 ROM_RELOAD( 0x10000, 0x20000 )
2430 ROM_LOAD( "c01-04.rom", 0x30000, 0x20000, 0x358bd076 )
2431
2432 ROM_REGION( 0x1c000, REGION_CPU2 ) /* sound (sndhrdw/rastan.c wants it as #2 */
2433 ROM_LOAD( "c01-08.rom", 0x00000, 0x4000, 0x810efff8 )
2434 ROM_CONTINUE( 0x10000, 0xc000 )
2435
2436 ROM_REGION( 0x30000, REGION_CPU3 )
2437 ROM_LOAD( "c01-07.rom", 0x00000, 0x20000, 0x5117c98f )
2438 ROM_RELOAD( 0x10000, 0x20000 )
2439
2440 ROM_REGION( 0x180000, REGION_GFX1| REGIONFLAG_DISPOSE )
2441 ROM_LOAD( "c01-01.rom", 0x000000, 0x80000, 0xf302e6e9 )
2442 ROM_LOAD( "c01-02.rom", 0x080000, 0x80000, 0x1e0476c4 )
2443 ROM_LOAD( "c01-03.rom", 0x100000, 0x80000, 0x2a142dbc )
2444
2445 ROM_REGION( 0x20000, REGION_SOUND1 ) /* ADPCM samples */
2446 ROM_LOAD( "c01-05.rom", 0x00000, 0x20000, 0x22efad4a )
2447 ROM_END
2448
2449 ROM_START( champwrj )
2450 ROM_REGION( 0xf0000, REGION_CPU1 )
2451 ROM_LOAD( "c01-06.bin", 0x00000, 0x20000, 0x90fa1409 )
2452 ROM_RELOAD( 0x10000, 0x20000 )
2453 ROM_LOAD( "c01-04.rom", 0x30000, 0x20000, 0x358bd076 )
2454
2455 ROM_REGION( 0x1c000, REGION_CPU2 ) /* sound (sndhrdw/rastan.c wants it as #2 */
2456 ROM_LOAD( "c01-08.rom", 0x00000, 0x4000, 0x810efff8 )
2457 ROM_CONTINUE( 0x10000, 0xc000 )
2458
2459 ROM_REGION( 0x30000, REGION_CPU3 )
2460 ROM_LOAD( "c01-07.rom", 0x00000, 0x20000, 0x5117c98f )
2461 ROM_RELOAD( 0x10000, 0x20000 )
2462
2463 ROM_REGION( 0x180000, REGION_GFX1| REGIONFLAG_DISPOSE )
2464 ROM_LOAD( "c01-01.rom", 0x000000, 0x80000, 0xf302e6e9 )
2465 ROM_LOAD( "c01-02.rom", 0x080000, 0x80000, 0x1e0476c4 )
2466 ROM_LOAD( "c01-03.rom", 0x100000, 0x80000, 0x2a142dbc )
2467
2468 ROM_REGION( 0x20000, REGION_SOUND1 ) /* ADPCM samples */
2469 ROM_LOAD( "c01-05.rom", 0x00000, 0x20000, 0x22efad4a )
2470 ROM_END
2471
2472
2473 ROM_START( kurikint )
2474 ROM_REGION( 0xb0000, REGION_CPU1 )
2475 ROM_LOAD( "b42-09.2", 0x00000, 0x20000, 0xe97c4394 )
2476 ROM_RELOAD( 0x10000, 0x20000 )
2477 ROM_LOAD( "b42-06.6", 0x30000, 0x20000, 0xfa15fd65 )
2478
2479 ROM_REGION( 0x10000, REGION_CPU2 )
2480 ROM_LOAD( "b42-07.22", 0x00000, 0x10000, 0x0f2719c0 )
2481
2482 ROM_REGION( 0x100000, REGION_GFX1| REGIONFLAG_DISPOSE )
2483 ROM_LOAD( "b42-01.1", 0x00000, 0x80000, 0x7d1a1fec )
2484 ROM_LOAD( "b42-02.5", 0x80000, 0x80000, 0x1a52e65c )
2485 ROM_END
2486
2487 ROM_START( kurikina )
2488 ROM_REGION( 0xb0000, REGION_CPU1 )
2489 ROM_LOAD( "kk_ic2.rom", 0x00000, 0x20000, 0x908603f2 )
2490 ROM_RELOAD( 0x10000, 0x20000 )
2491 ROM_LOAD( "kk_ic6.rom", 0x30000, 0x20000, 0xa4a957b1 )
2492
2493 ROM_REGION( 0x10000, REGION_CPU2 )
2494 ROM_LOAD( "b42-07.22", 0x00000, 0x10000, 0x0f2719c0 )
2495
2496 ROM_REGION( 0x100000, REGION_GFX1| REGIONFLAG_DISPOSE )
2497 ROM_LOAD( "kk_1-1l.rom", 0x00000, 0x20000, 0xdf1d4fcd )
2498 ROM_LOAD( "kk_2-2l.rom", 0x20000, 0x20000, 0xfca7f647 )
2499 ROM_LOAD( "kk_5-3l.rom", 0x40000, 0x20000, 0xd080fde1 )
2500 ROM_LOAD( "kk_7-4l.rom", 0x60000, 0x20000, 0xf5bf6829 )
2501 ROM_LOAD( "kk_3-1h.rom", 0x80000, 0x20000, 0x71af848e )
2502 ROM_LOAD( "kk_4-2h.rom", 0xa0000, 0x20000, 0xcebb5bac )
2503 ROM_LOAD( "kk_6-3h.rom", 0xc0000, 0x20000, 0x322e3752 )
2504 ROM_LOAD( "kk_8-4h.rom", 0xe0000, 0x20000, 0x117bde99 )
2505 ROM_END
2506
2507
2508 ROM_START( plotting )
2509 ROM_REGION( 0x20000, REGION_CPU1 )
2510 ROM_LOAD( "plot01.bin", 0x00000, 0x10000, 0x5b30bc25 )
2511 ROM_RELOAD( 0x10000, 0x10000 )
2512
2513 ROM_REGION( 0x20000, REGION_GFX1| REGIONFLAG_DISPOSE )
2514 ROM_LOAD( "plot07.bin", 0x00000, 0x10000, 0x6e0bad2a )
2515 ROM_LOAD( "plot08.bin", 0x10000, 0x10000, 0xfb5f3ca4 )
2516 ROM_END
2517
2518 ROM_START( puzznic )
2519 ROM_REGION( 0x30000, REGION_CPU1 )
2520 ROM_LOAD( "u11.rom", 0x00000, 0x20000, 0xa4150b6c )
2521 ROM_RELOAD( 0x10000, 0x20000 )
2522
2523 ROM_REGION( 0x0800, REGION_CPU2 ) /* 2k for the microcontroller */
2524 ROM_LOAD( "mc68705p", 0x0000, 0x0800, 0x00000000 )
2525
2526 ROM_REGION( 0x40000, REGION_GFX1| REGIONFLAG_DISPOSE )
2527 ROM_LOAD( "u10.rom", 0x00000, 0x20000, 0x4264056c )
2528 ROM_LOAD( "u09.rom", 0x20000, 0x20000, 0x3c115f8b )
2529 ROM_END
2530
2531 ROM_START( horshoes )
2532 ROM_REGION( 0x30000, REGION_CPU1 )
2533 ROM_LOAD( "c47.03", 0x00000, 0x20000, 0x37e15b20 )
2534 ROM_RELOAD( 0x10000, 0x20000 )
2535
2536 ROM_REGION( 0x80000, REGION_GFX1| REGIONFLAG_DISPOSE )
2537 ROM_LOAD( "c47.02", 0x00000, 0x10000, 0x35f96526 )
2538 ROM_CONTINUE ( 0x20000, 0x10000 )
2539 ROM_LOAD( "c47.04", 0x40000, 0x10000, 0xaeac7121 )
2540 ROM_CONTINUE ( 0x60000, 0x10000 )
2541 ROM_LOAD( "c47.01", 0x10000, 0x10000, 0x031c73d8 )
2542 ROM_CONTINUE ( 0x30000, 0x10000 )
2543 ROM_LOAD( "c47.05", 0x50000, 0x10000, 0xb2a3dafe )
2544 ROM_CONTINUE ( 0x70000, 0x10000 )
2545 ROM_END
2546
2547 ROM_START( palamed )
2548 ROM_REGION( 0x30000, REGION_CPU1 )
2549 ROM_LOAD( "c63.02", 0x00000, 0x20000, 0x55a82bb2 )
2550 ROM_RELOAD( 0x10000, 0x20000 )
2551
2552 ROM_REGION( 0x40000, REGION_GFX1| REGIONFLAG_DISPOSE )
2553 ROM_LOAD( "c63.04", 0x00000, 0x20000, 0xc7bbe460 )
2554 ROM_LOAD( "c63.03", 0x20000, 0x20000, 0xfcd86e44 )
2555 ROM_END
2556
2557 ROM_START( cachat )
2558 ROM_REGION( 0x30000, REGION_CPU1 )
2559 ROM_LOAD( "cac6", 0x00000, 0x20000, 0x8105cf5f )
2560 ROM_RELOAD( 0x10000, 0x20000 )
2561
2562 ROM_REGION( 0x80000, REGION_GFX1| REGIONFLAG_DISPOSE )
2563 ROM_LOAD( "cac9", 0x00000, 0x20000, 0xbc462914 )
2564 ROM_LOAD( "cac10", 0x20000, 0x20000, 0xecc64b31 )
2565 ROM_LOAD( "cac7", 0x40000, 0x20000, 0x7fb71578 )
2566 ROM_LOAD( "cac8", 0x60000, 0x20000, 0xd2a63799 )
2567 ROM_END
2568
2569 ROM_START( tubeit )
2570 ROM_REGION( 0x30000, REGION_CPU1 )
2571 ROM_LOAD( "t-i_02.6", 0x00000, 0x20000, 0x54730669 )
2572 ROM_RELOAD( 0x10000, 0x20000 )
2573
2574 ROM_REGION( 0x80000, REGION_GFX1| REGIONFLAG_DISPOSE )
2575 ROM_LOAD( "t-i_03.7", 0x40000, 0x40000, 0xe1c3fed0 )
2576 ROM_LOAD( "t-i_04.9", 0x00000, 0x40000, 0xb4a6e31d )
2577 ROM_END
2578
2579 ROM_START( cubybop )
2580 ROM_REGION( 0x50000, REGION_CPU1 )
2581 ROM_LOAD( "cb06.6", 0x00000, 0x40000, 0x66b89a85 )
2582 ROM_RELOAD( 0x10000, 0x40000 )
2583
2584 ROM_REGION( 0x100000, REGION_GFX1| REGIONFLAG_DISPOSE )
2585 ROM_LOAD( "cb09.9", 0x00000, 0x40000, 0x5f831e59 )
2586 ROM_LOAD( "cb10.10", 0x40000, 0x40000, 0x430510fc )
2587 ROM_LOAD( "cb07.7", 0x80000, 0x40000, 0x3582de99 )
2588 ROM_LOAD( "cb08.8", 0xc0000, 0x40000, 0x09e18a51 )
2589 ROM_END
2590
2591 ROM_START( plgirls )
2592 ROM_REGION( 0x50000, REGION_CPU1 )
2593 ROM_LOAD( "pg03.ic6", 0x00000, 0x40000, 0x6ca73092 )
2594 ROM_RELOAD( 0x10000, 0x40000 )
2595
2596 ROM_REGION( 0x80000, REGION_GFX1| REGIONFLAG_DISPOSE )
2597 ROM_LOAD( "pg02.ic9", 0x00000, 0x40000, 0x3cf05ca9 )
2598 ROM_LOAD( "pg01.ic7", 0x40000, 0x40000, 0x79e41e74 )
2599 ROM_END
2600
2601 ROM_START( plgirls2 )
2602 ROM_REGION( 0x50000, REGION_CPU1 )
2603 ROM_LOAD( "pg2_1j.ic6", 0x00000, 0x40000, 0xf924197a )
2604 ROM_RELOAD( 0x10000, 0x40000 )
2605
2606 ROM_REGION( 0x100000, REGION_GFX1| REGIONFLAG_DISPOSE )
2607 ROM_LOAD( "cho-l.ic9", 0x00000, 0x80000, 0x956384ec )
2608 ROM_LOAD( "cho-h.ic7", 0x80000, 0x80000, 0x992f99b1 )
2609 ROM_END
2610
2611
2612
2613 // bits 7..0 => bits 0..7
2614 static void init_plotting(void)
2615 {
2616 unsigned char tab[256];
2617 unsigned char *p;
2618 int i;
2619
2620 for(i=0;i<256;i++)
2621 {
2622 int j, v=0;
2623 for(j=0;j<8;j++)
2624 if(i & (1<<j))
2625 v |= 1<<(7-j);
2626 tab[i] = v;
2627 }
2628 p = memory_region(REGION_CPU1);
2629 for(i=0;i<0x20000;i++)
2630 {
2631 *p = tab[*p];
2632 p++;
2633 }
2634 }
2635
2636
2637 GAME( 1988, raimais, 0, raimais, raimais, 0, ROT0, "Taito Corporation", "Raimais (Japan)" )
2638 GAME( 1988, fhawk, 0, fhawk, fhawk, 0, ROT270, "Taito Corporation", "Fighting Hawk (Japan)" )
2639 GAME( 1989, champwr, 0, champwr, champwr, 0, ROT0, "Taito Corporation Japan", "Champion Wrestler (World)" )
2640 GAME( 1989, champwru, champwr, champwr, champwru, 0, ROT0, "Taito America Corporation", "Champion Wrestler (US)" )
2641 GAME( 1989, champwrj, champwr, champwr, champwrj, 0, ROT0, "Taito Corporation", "Champion Wrestler (Japan)" )
2642
2643 GAME( 1988, kurikint, 0, kurikint, kurikint, 0, ROT0, "Taito Corporation Japan", "Kuri Kinton (World)" )
2644 GAME( 1988, kurikina, kurikint, kurikint, kurikina, 0, ROT0, "Taito Corporation Japan", "Kuri Kinton (prototype?)" )
2645
2646 GAME( 1989, plotting, 0, plotting, plotting, plotting, ROT0, "Taito Corporation Japan", "Plotting (World)" )
2647 GAME( 1989, puzznic, 0, puzznic, puzznic, 0, ROT0, "Taito Corporation", "Puzznic (Japan)" )
2648 GAME( 1990, horshoes, 0, horshoes, horshoes, 0, ROT270, "Taito America Corporation", "American Horseshoes (US)" )
2649 GAME( 1990, palamed, 0, palamed, palamed, 0, ROT0, "Taito Corporation", "Palamedes (Japan)" )
2650 GAME( 1993, cachat, 0, cachat, cachat, 0, ROT0, "Taito Corporation", "Cachat (Japan)" )
2651 GAME( 1993, tubeit, cachat, cachat, tubeit, 0, ROT0, "Taito Corporation", "Tube-It" ) // No (c) message
2652 GAME( 199?, cubybop, 0, cachat, cubybop, 0, ROT0, "Taito Corporation", "Cuby Bop" ) // No (c) message
2653
2654 GAME( 1992, plgirls, 0, cachat, plgirls, 0, ROT270, "Hot-B.", "Play Girls" )
2655 GAME( 1993, plgirls2, 0, cachat, plgirls2, 0, ROT270, "Hot-B.", "Play Girls 2" )
2656