1 /****************************************************************************
2
3 Exterminator memory map
4
5 driver by Zsolt Vasvari and Alex Pasadyn
6
7
8 Master CPU (TMS34010, all addresses are in bits)
9
10 00000000-000fffff RW Video RAM (256x256x15)
11 00c00000-00ffffff RW RAM
12 01000000-010fffff W Host Control Interface (HSTADRL)
13 01100000-011fffff W Host Control Interface (HSTADRH)
14 01200000-012fffff RW Host Control Interface (HSTDATA)
15 01300000-013fffff W Host Control Interface (HSTCTLH)
16 01400000-01400007 R Input Port 0
17 01400008-0140000f R Input Port 1
18 01440000-01440007 R Input Port 2
19 01440008-0144000f R Input Port 3
20 01480000-01480007 R Input Port 4
21 01500000-0150000f W Output Port 0 (See machine/exterm.c)
22 01580000-0158000f W Sound Command
23 015c0000-015c000f W Watchdog
24 01800000-01807fff RW Palette RAM
25 02800000-02807fff RW EEPROM
26 03000000-03ffffff R ROM
27 3f000000-3fffffff R ROM Mirror
28 c0000000-c00001ff RW TMS34010 I/O Registers
29 ff000000-ffffffff R ROM Mirror
30
31
32 Slave CPU (TMS34010, all addresses are in bits)
33
34 00000000-000fffff RW Video RAM (2 banks of 256x256x8)
35 c0000000-c00001ff RW TMS34010 I/O Registers
36 ff800000-ffffffff RW RAM
37
38
39 DAC Controller CPU (6502)
40
41 0000-07ff RW RAM
42 4000 R Sound Command
43 8000-8001 W 2 Channels of DAC output
44 8000-ffff R ROM
45
46
47 YM2151 Controller CPU (6502)
48
49 0000-07ff RW RAM
50 4000 W YM2151 Command/Data Register (Controlled by a bit A000)
51 6000 W NMI occurence rate (fed into a binary counter)
52 6800 R Sound Command
53 7000 R Causes NMI on DAC CPU
54 8000-ffff R ROM
55 a000 W Control register (see sndhrdw/gottlieb.c)
56
57 ****************************************************************************/
58
59 #include "driver.h"
60 #include "cpu/tms34010/tms34010.h"
61
62 static size_t code_rom_size;
63 static data16_t *exterm_code_rom;
64 static data16_t *exterm_master_speedup, *exterm_slave_speedup;
65
66 extern data16_t *exterm_master_videoram, *exterm_slave_videoram;
67
68 static data8_t aimpos[2];
69 static data8_t trackball_old[2];
70
71
72 /* Functions in vidhrdw/exterm.c */
73 PALETTE_INIT( exterm );
74 VIDEO_START( exterm );
75
76 VIDEO_UPDATE( exterm );
77 void exterm_to_shiftreg_master(unsigned int address, unsigned short* shiftreg);
78 void exterm_from_shiftreg_master(unsigned int address, unsigned short* shiftreg);
79 void exterm_to_shiftreg_slave(unsigned int address, unsigned short* shiftreg);
80 void exterm_from_shiftreg_slave(unsigned int address, unsigned short* shiftreg);
81
82 /* Functions in sndhrdw/gottlieb.c */
83 void gottlieb_sound_init(void);
84 WRITE16_HANDLER( gottlieb_sh_word_w );
85 READ_HANDLER( gottlieb_cause_dac_nmi_r );
86 WRITE_HANDLER( gottlieb_nmi_rate_w );
87 WRITE_HANDLER( exterm_sound_control_w );
88 WRITE_HANDLER( exterm_ym2151_w );
89 WRITE_HANDLER( exterm_dac_vol_w );
90 WRITE_HANDLER( exterm_dac_data_w );
91
92
MACHINE_INIT(exterm)93 static MACHINE_INIT( exterm )
94 {
95 gottlieb_sound_init();
96 }
97
98
99 /*************************************
100 *
101 * Master/slave communications
102 *
103 *************************************/
104
WRITE16_HANDLER(exterm_host_data_w)105 WRITE16_HANDLER( exterm_host_data_w )
106 {
107 tms34010_host_w(1, offset / TOWORD(0x00100000), data);
108 }
109
110
READ16_HANDLER(exterm_host_data_r)111 READ16_HANDLER( exterm_host_data_r )
112 {
113 return tms34010_host_r(1, TMS34010_HOST_DATA);
114 }
115
116
117
118 /*************************************
119 *
120 * Input port handlers
121 *
122 *************************************/
123
exterm_trackball_port_r(int which,data16_t mem_mask)124 static data16_t exterm_trackball_port_r(int which, data16_t mem_mask)
125 {
126 data16_t port;
127
128 /* Read the fake input port */
129 data8_t trackball_pos = readinputport(3 + which);
130
131 /* Calculate the change from the last position. */
132 data8_t trackball_diff = trackball_old[which] - trackball_pos;
133
134 /* Store the new position for the next comparision. */
135 trackball_old[which] = trackball_pos;
136
137 /* Move the sign bit to the high bit of the 6-bit trackball count. */
138 if (trackball_diff & 0x80)
139 trackball_diff |= 0x20;
140
141 /* Keep adding the changes. The counters will be reset later by a hardware write. */
142 aimpos[which] = (aimpos[which] + trackball_diff) & 0x3f;
143
144 /* Combine it with the standard input bits */
145 port = which ? input_port_1_word_r(0, mem_mask) :
146 input_port_0_word_r(0, mem_mask);
147
148 return (port & 0xc0ff) | (aimpos[which] << 8);
149 }
150
READ16_HANDLER(exterm_input_port_0_r)151 READ16_HANDLER( exterm_input_port_0_r )
152 {
153 return exterm_trackball_port_r(0, mem_mask);
154 }
155
READ16_HANDLER(exterm_input_port_1_r)156 READ16_HANDLER( exterm_input_port_1_r )
157 {
158 return exterm_trackball_port_r(1, mem_mask);
159 }
160
161
162
163 /*************************************
164 *
165 * Output port handlers
166 *
167 *************************************/
168
WRITE16_HANDLER(exterm_output_port_0_w)169 WRITE16_HANDLER( exterm_output_port_0_w )
170 {
171 /* All the outputs are activated on the rising edge */
172
173 static data16_t last = 0;
174
175 if (ACCESSING_LSB)
176 {
177 /* Bit 0-1= Resets analog controls */
178 if ((data & 0x0001) && !(last & 0x0001))
179 aimpos[0] = 0;
180
181 if ((data & 0x0002) && !(last & 0x0002))
182 aimpos[1] = 0;
183 }
184
185 if (ACCESSING_MSB)
186 {
187 /* Bit 13 = Resets the slave CPU */
188 if ((data & 0x2000) && !(last & 0x2000))
189 cpu_set_reset_line(1, PULSE_LINE);
190
191 /* Bits 14-15 = Coin counters */
192 coin_counter_w(0, data & 0x8000);
193 coin_counter_w(1, data & 0x4000);
194 }
195
196 COMBINE_DATA(&last);
197 }
198
199
200
201 /*************************************
202 *
203 * Speedup handlers
204 *
205 *************************************/
206
READ16_HANDLER(exterm_master_speedup_r)207 READ16_HANDLER( exterm_master_speedup_r )
208 {
209 int value = exterm_master_speedup[offset];
210
211 /* Suspend cpu if it's waiting for an interrupt */
212 if (activecpu_get_pc() == 0xfff4d9b0 && !value)
213 cpu_spinuntil_int();
214
215 return value;
216 }
217
WRITE16_HANDLER(exterm_slave_speedup_w)218 WRITE16_HANDLER( exterm_slave_speedup_w )
219 {
220 /* Suspend cpu if it's waiting for an interrupt */
221 if (activecpu_get_pc() == 0xfffff050)
222 cpu_spinuntil_int();
223
224 COMBINE_DATA(&exterm_slave_speedup[offset]);
225 }
226
READ_HANDLER(exterm_sound_dac_speedup_r)227 READ_HANDLER( exterm_sound_dac_speedup_r )
228 {
229 UINT8 *RAM = memory_region(REGION_CPU3);
230 int value = RAM[0x0007];
231
232 /* Suspend cpu if it's waiting for an interrupt */
233 if (activecpu_get_pc() == 0x8e79 && !value)
234 cpu_spinuntil_int();
235
236 return value;
237 }
238
READ_HANDLER(exterm_sound_ym2151_speedup_r)239 READ_HANDLER( exterm_sound_ym2151_speedup_r )
240 {
241 /* Doing this won't flash the LED, but we're not emulating that anyhow, so
242 it doesn't matter */
243 UINT8 *RAM = memory_region(REGION_CPU4);
244 int value = RAM[0x02b6];
245
246 /* Suspend cpu if it's waiting for an interrupt */
247 if (activecpu_get_pc() == 0x8179 && !(value & 0x80) && RAM[0x00bc] == RAM[0x00bb] &&
248 RAM[0x0092] == 0x00 && RAM[0x0093] == 0x00 && !(RAM[0x0004] & 0x80))
249 cpu_spinuntil_int();
250
251 return value;
252 }
253
254
255
256 /*************************************
257 *
258 * Master/slave memory maps
259 *
260 *************************************/
261
MEMORY_READ16_START(master_readmem)262 static MEMORY_READ16_START( master_readmem )
263 { TOBYTE(0x00000000), TOBYTE(0x000fffff), MRA16_RAM },
264 { TOBYTE(0x00c00000), TOBYTE(0x00ffffff), MRA16_RAM },
265 { TOBYTE(0x01200000), TOBYTE(0x012fffff), exterm_host_data_r },
266 { TOBYTE(0x01400000), TOBYTE(0x0140000f), exterm_input_port_0_r },
267 { TOBYTE(0x01440000), TOBYTE(0x0144000f), exterm_input_port_1_r },
268 { TOBYTE(0x01480000), TOBYTE(0x0148000f), input_port_2_word_r },
269 { TOBYTE(0x01800000), TOBYTE(0x01807fff), MRA16_RAM },
270 { TOBYTE(0x02800000), TOBYTE(0x02807fff), MRA16_RAM },
271 { TOBYTE(0x03000000), TOBYTE(0x03ffffff), MRA16_BANK1 },
272 { TOBYTE(0x3f000000), TOBYTE(0x3fffffff), MRA16_BANK2 },
273 { TOBYTE(0xc0000000), TOBYTE(0xc00001ff), tms34010_io_register_r },
274 { TOBYTE(0xff000000), TOBYTE(0xffffffff), MRA16_RAM },
275 MEMORY_END
276
277 static MEMORY_WRITE16_START( master_writemem )
278 { TOBYTE(0x00000000), TOBYTE(0x000fffff), MWA16_RAM, &exterm_master_videoram },
279 { TOBYTE(0x00c00000), TOBYTE(0x00ffffff), MWA16_RAM },
280 { TOBYTE(0x01000000), TOBYTE(0x013fffff), exterm_host_data_w },
281 { TOBYTE(0x01500000), TOBYTE(0x0150000f), exterm_output_port_0_w },
282 { TOBYTE(0x01580000), TOBYTE(0x0158000f), gottlieb_sh_word_w },
283 { TOBYTE(0x015c0000), TOBYTE(0x015c000f), watchdog_reset16_w },
284 { TOBYTE(0x01800000), TOBYTE(0x01807fff), paletteram16_xRRRRRGGGGGBBBBB_word_w, &paletteram16 },
285 { TOBYTE(0x02800000), TOBYTE(0x02807fff), MWA16_RAM, (data16_t **)&generic_nvram, &generic_nvram_size }, /* EEPROM */
286 { TOBYTE(0xc0000000), TOBYTE(0xc00001ff), tms34010_io_register_w },
287 { TOBYTE(0xff000000), TOBYTE(0xffffffff), MWA16_ROM, &exterm_code_rom, &code_rom_size },
288 MEMORY_END
289
290
291 static MEMORY_READ16_START( slave_readmem )
292 { TOBYTE(0x00000000), TOBYTE(0x000fffff), MRA16_RAM },
293 { TOBYTE(0xc0000000), TOBYTE(0xc00001ff), tms34010_io_register_r },
294 { TOBYTE(0xff800000), TOBYTE(0xffffffff), MRA16_RAM },
295 MEMORY_END
296
297 static MEMORY_WRITE16_START( slave_writemem )
298 { TOBYTE(0x00000000), TOBYTE(0x000fffff), MWA16_RAM, &exterm_slave_videoram },
299 { TOBYTE(0xc0000000), TOBYTE(0xc00001ff), tms34010_io_register_w },
300 { TOBYTE(0xff800000), TOBYTE(0xffffffff), MWA16_RAM },
301 MEMORY_END
302
303
304
305 /*************************************
306 *
307 * Audio memory maps
308 *
309 *************************************/
310
311 static MEMORY_READ_START( sound_dac_readmem )
312 { 0x0000, 0x07ff, MRA_RAM },
313 { 0x4000, 0x4000, soundlatch_r },
314 { 0x8000, 0xffff, MRA_ROM },
315 MEMORY_END
316
317 static MEMORY_WRITE_START( sound_dac_writemem )
318 { 0x0000, 0x07ff, MWA_RAM },
319 { 0x8000, 0x8000, exterm_dac_vol_w },
320 { 0x8001, 0x8001, exterm_dac_data_w },
321 MEMORY_END
322
323
324 static MEMORY_READ_START( sound_ym2151_readmem )
325 { 0x0000, 0x07ff, MRA_RAM },
326 { 0x6800, 0x6800, soundlatch_r },
327 { 0x7000, 0x7000, gottlieb_cause_dac_nmi_r },
328 { 0x8000, 0xffff, MRA_ROM },
329 MEMORY_END
330
331 static MEMORY_WRITE_START( sound_ym2151_writemem )
332 { 0x0000, 0x07ff, MWA_RAM },
333 { 0x4000, 0x4000, exterm_ym2151_w },
334 { 0x6000, 0x6000, gottlieb_nmi_rate_w },
335 { 0xa000, 0xa000, exterm_sound_control_w },
336 MEMORY_END
337
338
339
340 /*************************************
341 *
342 * Input ports
343 *
344 *************************************/
345
346 INPUT_PORTS_START( exterm )
347 PORT_START /* IN0 */
348 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
349 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START1 )
350 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER1)
351 PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER1)
352 PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER1)
353 PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1)
354 PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
355 PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
356 PORT_BIT( 0x3f00, IP_ACTIVE_LOW, IPT_SPECIAL) /* trackball data */
357 PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNUSED )
358 PORT_SERVICE( 0x8000, IP_ACTIVE_LOW )
359
360 PORT_START /* IN1 */
361 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN2 )
362 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START2 )
363 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2)
364 PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2)
365 PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2)
366 PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2)
367 PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
368 PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
369 PORT_BIT( 0x3f00, IP_ACTIVE_LOW, IPT_SPECIAL) /* trackball data */
370 PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED )
371
372 PORT_START /* DSW */
373 PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unused ) ) /* According to the test screen */
374 PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
375 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
376 /* Note that the coin settings don't match the setting shown on the test screen,
377 but instead what the game appears to used. This is either a bug in the game,
378 or I don't know what else. */
379 PORT_DIPNAME( 0x0006, 0x0006, DEF_STR( Coin_A ) )
380 PORT_DIPSETTING( 0x0006, DEF_STR( 1C_1C ) )
381 PORT_DIPSETTING( 0x0002, DEF_STR( 1C_2C ) )
382 PORT_DIPSETTING( 0x0004, DEF_STR( 1C_3C ) )
383 PORT_DIPSETTING( 0x0000, DEF_STR( 1C_4C ) )
384 PORT_DIPNAME( 0x0038, 0x0038, DEF_STR( Coin_B ) )
385 PORT_DIPSETTING( 0x0038, DEF_STR( 1C_1C ) )
386 PORT_DIPSETTING( 0x0018, DEF_STR( 1C_2C ) )
387 PORT_DIPSETTING( 0x0028, DEF_STR( 1C_3C ) )
388 PORT_DIPSETTING( 0x0008, DEF_STR( 1C_4C ) )
389 PORT_DIPSETTING( 0x0030, DEF_STR( 1C_5C ) )
390 PORT_DIPSETTING( 0x0010, DEF_STR( 1C_6C ) )
391 PORT_DIPSETTING( 0x0020, DEF_STR( 1C_7C ) )
392 PORT_DIPSETTING( 0x0000, DEF_STR( 1C_8C ) )
393 PORT_DIPNAME( 0x0040, 0x0040, "Memory Test" )
394 PORT_DIPSETTING( 0x0040, "Once" )
395 PORT_DIPSETTING( 0x0000, "Continous" )
396 PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Free_Play ) )
397 PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
398 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
399 PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
400
401 PORT_START /* IN3, fake trackball input port */
402 PORT_ANALOG( 0xff, 0x00, IPT_DIAL | IPF_REVERSE | IPF_PLAYER1, 50, 10, 0, 0)
403
404 PORT_START /* IN4, fake trackball input port. */
405 PORT_ANALOG( 0xff, 0x00, IPT_DIAL | IPF_REVERSE | IPF_PLAYER2, 50, 10, 0, 0)
406
407 INPUT_PORTS_END
408
409
410
411 /*************************************
412 *
413 * 34010 configurations
414 *
415 *************************************/
416
417 static struct tms34010_config master_config =
418 {
419 0, /* halt on reset */
420 NULL, /* generate interrupt */
421 exterm_to_shiftreg_master, /* write to shiftreg function */
422 exterm_from_shiftreg_master /* read from shiftreg function */
423 };
424
425 static struct tms34010_config slave_config =
426 {
427 1, /* halt on reset */
428 NULL, /* generate interrupt */
429 exterm_to_shiftreg_slave, /* write to shiftreg function */
430 exterm_from_shiftreg_slave /* read from shiftreg function */
431 };
432
433
434
435 /*************************************
436 *
437 * Sound configurations
438 *
439 *************************************/
440
441 static struct DACinterface dac_interface =
442 {
443 2, /* 2 channels on 1 chip */
444 { 40, 40 },
445 };
446
447 static struct YM2151interface ym2151_interface =
448 {
449 1, /* 1 chip */
450 4000000, /* 4 MHz */
451 { YM3012_VOL(100,MIXER_PAN_LEFT,100,MIXER_PAN_RIGHT) },
452 { 0 }
453 };
454
455
456
457 /*************************************
458 *
459 * Machine drivers
460 *
461 *************************************/
462
463 static MACHINE_DRIVER_START( exterm )
464
465 /* basic machine hardware */
466 MDRV_CPU_ADD(TMS34010,40000000/TMS34010_CLOCK_DIVIDER)
MDRV_CPU_CONFIG(master_config)467 MDRV_CPU_CONFIG(master_config)
468 MDRV_CPU_MEMORY(master_readmem,master_writemem)
469
470 MDRV_CPU_ADD(TMS34010,40000000/TMS34010_CLOCK_DIVIDER)
471 MDRV_CPU_CONFIG(slave_config)
472 MDRV_CPU_MEMORY(slave_readmem,slave_writemem)
473
474 MDRV_CPU_ADD(M6502, 2000000)
475 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
476 MDRV_CPU_MEMORY(sound_dac_readmem,sound_dac_writemem)
477
478 MDRV_CPU_ADD(M6502, 2000000)
479 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
480 MDRV_CPU_MEMORY(sound_ym2151_readmem,sound_ym2151_writemem)
481
482 MDRV_FRAMES_PER_SECOND(60)
483 MDRV_VBLANK_DURATION((1000000 * (263 - 240)) / (60 * 263))
484 MDRV_INTERLEAVE(1675) // anything lower will have drop outs on the drums
485
486 MDRV_MACHINE_INIT(exterm)
487 MDRV_NVRAM_HANDLER(generic_0fill)
488
489 /* video hardware */
490 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
491 MDRV_SCREEN_SIZE(256, 240)
492 MDRV_VISIBLE_AREA(0, 255, 0, 239)
493 MDRV_PALETTE_LENGTH(4096+32768)
494
495 MDRV_PALETTE_INIT(exterm)
496 MDRV_VIDEO_START(exterm)
497 MDRV_VIDEO_UPDATE(exterm)
498
499 /* sound hardware */
500 MDRV_SOUND_ATTRIBUTES(SOUND_SUPPORTS_STEREO)
501 MDRV_SOUND_ADD(DAC, dac_interface)
502 MDRV_SOUND_ADD(YM2151, ym2151_interface)
503 MACHINE_DRIVER_END
504
505
506
507 /*************************************
508 *
509 * ROM definitions
510 *
511 *************************************/
512
513 ROM_START( exterm )
514 ROM_REGION( 0x20000, REGION_CPU1, 0 ) /* dummy region for TMS34010 #1 */
515
516 ROM_REGION( 0x20000, REGION_CPU2, 0 ) /* dummy region for TMS34010 #2 */
517
518 ROM_REGION( 0x10000, REGION_CPU3, 0 ) /* 64k for DAC code */
519 ROM_LOAD( "v101d1", 0x8000, 0x8000, CRC(83268b7d) SHA1(a9139e80e2382122e9919c0555937e120d4414cf) )
520
521 ROM_REGION( 0x10000, REGION_CPU4, 0 ) /* 64k for YM2151 code */
522 ROM_LOAD( "v101y1", 0x8000, 0x8000, CRC(cbeaa837) SHA1(87d8a258f059512dbf9bc0e7cfff728ef9e616f1) )
523
524 ROM_REGION16_LE( 0x200000, REGION_USER1, 0 ) /* 2MB for 34010 code */
525 ROM_LOAD16_BYTE( "v101bg0", 0x000000, 0x10000, CRC(8c8e72cf) SHA1(5e0fa805334f54f7e0293ea400bacb0e3e79ed56) )
526 ROM_LOAD16_BYTE( "v101bg1", 0x000001, 0x10000, CRC(cc2da0d8) SHA1(4ac23048d3ca771e315388603ad3b1b25030d6ff) )
527 ROM_LOAD16_BYTE( "v101bg2", 0x020000, 0x10000, CRC(2dcb3653) SHA1(2d74b58b02ae0587e3789d69feece268f582f226) )
528 ROM_LOAD16_BYTE( "v101bg3", 0x020001, 0x10000, CRC(4aedbba0) SHA1(73b7e4864b1e71103229edd3cae268ab91144ef2) )
529 ROM_LOAD16_BYTE( "v101bg4", 0x040000, 0x10000, CRC(576922d4) SHA1(c8cdfb0727c9f1f6e2d2008611372f386fd35fc4) )
530 ROM_LOAD16_BYTE( "v101bg5", 0x040001, 0x10000, CRC(a54a4bc2) SHA1(e0f3648454cafeee1f3f58af03489d3256f66965) )
531 ROM_LOAD16_BYTE( "v101bg6", 0x060000, 0x10000, CRC(7584a676) SHA1(c9bc651f90ab752f73e735cb80e5bb109e2cac5f) )
532 ROM_LOAD16_BYTE( "v101bg7", 0x060001, 0x10000, CRC(a4f24ff6) SHA1(adabbe1c93beb4fcc6fa2f13e687a866fb54fbdb) )
533 ROM_LOAD16_BYTE( "v101bg8", 0x080000, 0x10000, CRC(fda165d6) SHA1(901bdede00a936c0160d9fea8a2975ff893e52d0) )
534 ROM_LOAD16_BYTE( "v101bg9", 0x080001, 0x10000, CRC(e112a4c4) SHA1(8938d6857b3c5cd3f5560496e087e3b3ff3dab81) )
535 ROM_LOAD16_BYTE( "v101bg10", 0x0a0000, 0x10000, CRC(f1a5cf54) SHA1(749531036a1100e092b7edfba14097d5aaab26aa) )
536 ROM_LOAD16_BYTE( "v101bg11", 0x0a0001, 0x10000, CRC(8677e754) SHA1(dd8135de8819096150914798ab37a17ae396af32) )
537 ROM_LOAD16_BYTE( "v101fg0", 0x180000, 0x10000, CRC(38230d7d) SHA1(edd575192c0376183c415c61a3c3f19555522549) )
538 ROM_LOAD16_BYTE( "v101fg1", 0x180001, 0x10000, CRC(22a2bd61) SHA1(59ed479b8ae8328014be4e2a5575d00105fd83f3) )
539 ROM_LOAD16_BYTE( "v101fg2", 0x1a0000, 0x10000, CRC(9420e718) SHA1(1fd9784d40e496ebc4772baff472eb25b5106725) )
540 ROM_LOAD16_BYTE( "v101fg3", 0x1a0001, 0x10000, CRC(84992aa2) SHA1(7dce2bef695c2a9b5a03d217bbff8fbece459a92) )
541 ROM_LOAD16_BYTE( "v101fg4", 0x1c0000, 0x10000, CRC(38da606b) SHA1(59479ff99b1748ddc36de32b368dd38cb2965868) )
542 ROM_LOAD16_BYTE( "v101fg5", 0x1c0001, 0x10000, CRC(842de63a) SHA1(0b292a8b7f4b86a2d3bd6b5b7ec0287e2bf88263) )
543 ROM_LOAD16_BYTE( "v101p0", 0x1e0000, 0x10000, CRC(6c8ee79a) SHA1(aa051e33e3ed6eed475a37e5dae1be0ac6471b12) )
544 ROM_LOAD16_BYTE( "v101p1", 0x1e0001, 0x10000, CRC(557bfc84) SHA1(8d0f1b40adbf851a85f626663956f3726ca8026d) )
545 ROM_END
546
547
548
549 /*************************************
550 *
551 * Driver initialization
552 *
553 *************************************/
554
555 DRIVER_INIT( exterm )
556 {
557 memcpy(exterm_code_rom, memory_region(REGION_USER1), code_rom_size);
558
559 /* install speedups */
560 exterm_master_speedup = install_mem_read16_handler(0, TOBYTE(0x00c800e0), TOBYTE(0x00c800ef), exterm_master_speedup_r);
561 exterm_slave_speedup = install_mem_write16_handler(1, TOBYTE(0xfffffb90), TOBYTE(0xfffffb9f), exterm_slave_speedup_w);
562 install_mem_read_handler(2, 0x0007, 0x0007, exterm_sound_dac_speedup_r);
563 install_mem_read_handler(3, 0x02b6, 0x02b6, exterm_sound_ym2151_speedup_r);
564
565 /* set up mirrored ROM access */
566 cpu_setbank(1, exterm_code_rom);
567 cpu_setbank(2, exterm_code_rom);
568 }
569
570
571
572 /*************************************
573 *
574 * Game drivers
575 *
576 *************************************/
577
578 GAME( 1989, exterm, 0, exterm, exterm, exterm, ROT0, "Gottlieb / Premier Technology", "Exterminator" )
579