1 /************************************************************
2
3 NEC uPD7759 ADPCM Speech Processor
4 by: Juergen Buchmueller, Mike Balfour, Howie Cohen and
5 Olivier Galibert
6
7
8 Description:
9 The uPD7759 is a speech processing LSI that utilizes ADPCM to produce
10 speech or other sampled sounds. It can directly address up to 1Mbit
11 (128k) of external data ROM, or the host CPU can control the speech
12 data transfer. The uPD7759 is always hooked up to a 640 kHz clock and
13 has one 8-bit input port, a start pin, a busy pin, and a clock output.
14
15 The chip is composed of 3 parts:
16 - a clock divider
17 - a rom-reading engine
18 - an adpcm engine
19 - a 4-to-9 bit adpcm converter
20
21 The clock divider takes the base 640KHz clock and divides it first
22 by a fixed divisor of 4 and then by a value between 9 and 32. The
23 result gives a clock between 5KHz and 17.78KHz. It's probably
24 possible, but not recommended and certainly out-of-spec, to push the
25 chip harder by reducing the divider.
26
27 The rom-reading engine reads one byte every two divided clock cycles.
28 The factor two comes from the fact that a byte has two nibbles, i.e.
29 two samples.
30
31 The apdcm engine takes bytes and interprets them as commands:
32 00000000 sample end(?)
33 00dddddd silence
34 01-fffff send the 256 following nibbles to the converter
35 10-fffff nnnnnnnn send the n+1 following nibbles to the converter
36 11111111 start/stop engine ? (in slave mode)
37 11------ unknown
38
39 "fffff" is sent to the clock divider to be the base clock for the
40 adpcm converter. I.e., it's the sampling rate. If the number of
41 nibbles to send is odd the last nibble is ignored. The commands
42 are always 8-bits aligned.
43
44 "dddddd" is the duration of the silence. The base speed is unknown,
45 1ms sounds reasonably. It does not seem linked to the adpcm clock
46 speed because there often is a silence before any 01 or 10 command.
47
48
49 The adpcm converter converts nibbles into 9-bit DAC values. It has
50 an internal state of 4 bits that's used in conjunction with the
51 nibble to lookup which of the 256 possible steps is used. Then
52 the state is changed according to the nibble value. Essentially, the
53 higher the state, the bigger the steps are, and using big steps
54 increase the state. Conversely, using small steps reduces the state.
55 This allows the engine to be a little more adaptative than a
56 classical ADPCM algorithm.
57
58
59 The uPD7759 can run in two modes, master (also known as standalone)
60 and slave. The mode is selected through the "md" pin. No known
61 game changes modes on the fly, and it's unsure if that's even
62 possible to do.
63
64
65 Master mode:
66
67 The output of the rom reader is directly connected to the adpcm
68 converter. The controlling cpu only sends a sample number and the
69 7759 plays it.
70
71 The sample rom has an header at the beginning of the form
72 nn 5a a5 69 55
73 where nn is the number of the last sample. This is then followed by
74 a vector of 2-bytes msb-first values, one per sample. Multiplying
75 them by two gives the sample start offset in the rom. A 0x00 marks
76 the end of each sample.
77
78 It seems that the upd7759 reads at least part of the rom header at
79 startup. Games doing rom banking are careful to reset the chip after
80 each change.
81
82
83 Slave mode:
84
85 The rom reader is completely disconnected. The input port is
86 connected directly to the adpcm engine. The first write to the input
87 port activates the engine (the value itself is ignored). The engine
88 activates the clock output and waits for commands. The clock speed
89 is unknown, but its probably a divider of 640KHz. We use 40KHz here
90 because 80KHz crashes altbeast. The chip probably has an internal
91 fifo to the converter and suspends the clock when the fifo is full.
92 The first command is always 0xFF. A second 0xFF marks the end of the
93 sample and the engine stops. OTOH, there is a 0x00 at the end too.
94 Go figure.
95
96
97 Unknowns:
98 - Real rom and slave mode clock speeds
99 - Start pin effect in slave mode
100 - 0x00 vs. 0xff, sample on/off vs. drq on/off ?
101
102 *************************************************************/
103 //* : debug-note tags(AT)
104
105 #include <stdio.h>
106 #include <stdlib.h>
107 #include <math.h>
108
109 #include "driver.h"
110 #include "upd7759.h"
111 #include "streams.h"
112
113 #define MAX_UPD7759 2
114 #define DRQ_FREQUENCY 40000
115 #define SILENCE_FREQUENCY 1000
116
117 static struct {
118 const struct UPD7759_interface *intf;
119 struct UPD7759_chip {
120 int channel;
121
122 const UINT8 *rom;
123 const UINT8 *cur_rombank;
124
125 UINT8 reset, start, port;
126 UINT8 playing;
127 UINT8 buffer[512];
128 int buffer_ptr;
129 UINT32 rr_pos;
130
131 int play_length;
132 void *timer;
133
134 int param_mode, drq, suspend, waiting, wait_samples;
135
136 int freq;
137 UINT32 step, pos;
138
139 int sample, state, nibble, skip_last_nibble, next_skip_last_nibble, started;
140 } chip[MAX_UPD7759];
141 } UPD7759_chips;
142
143 const static int UPD7759_step[16][16] = {
144 { 0, 0, 1, 2, 3, 5, 7, 10, 0, 0, -1, -2, -3, -5, -7, -10 },
145 { 0, 1, 2, 3, 4, 6, 8, 13, 0, -1, -2, -3, -4, -6, -8, -13 },
146 { 0, 1, 2, 4, 5, 7, 10, 15, 0, -1, -2, -4, -5, -7, -10, -15 },
147 { 0, 1, 3, 4, 6, 9, 13, 19, 0, -1, -3, -4, -6, -9, -13, -19 },
148 { 0, 2, 3, 5, 8, 11, 15, 23, 0, -2, -3, -5, -8, -11, -15, -23 },
149 { 0, 2, 4, 7, 10, 14, 19, 29, 0, -2, -4, -7, -10, -14, -19, -29 },
150 { 0, 3, 5, 8, 12, 16, 22, 33, 0, -3, -5, -8, -12, -16, -22, -33 },
151 { 1, 4, 7, 10, 15, 20, 29, 43, -1, -4, -7, -10, -15, -20, -29, -43 },
152 { 1, 4, 8, 13, 18, 25, 35, 53, -1, -4, -8, -13, -18, -25, -35, -53 },
153 { 1, 6, 10, 16, 22, 31, 43, 64, -1, -6, -10, -16, -22, -31, -43, -64 },
154 { 2, 7, 12, 19, 27, 37, 51, 76, -2, -7, -12, -19, -27, -37, -51, -76 },
155 { 2, 9, 16, 24, 34, 46, 64, 96, -2, -9, -16, -24, -34, -46, -64, -96 },
156 { 3, 11, 19, 29, 41, 57, 79, 117, -3, -11, -19, -29, -41, -57, -79, -117 },
157 { 4, 13, 24, 36, 50, 69, 96, 143, -4, -13, -24, -36, -50, -69, -96, -143 },
158 { 4, 16, 29, 44, 62, 85, 118, 175, -4, -16, -29, -44, -62, -85, -118, -175 },
159 { 6, 20, 36, 54, 76, 104, 144, 214, -6, -20, -36, -54, -76, -104, -144, -214 },
160 };
161
162 const static int UPD7759_state[16] = { -1, -1, 0, 0, 1, 2, 2, 3, -1, -1, 0, 0, 1, 2, 2, 3 };
163
164 static void UPD7759_standalone_load_data(int chip);
165
166 // Generate the sound
UPD7759_update(int chip,INT16 * buffer,int length)167 static void UPD7759_update(int chip, INT16 *buffer, int length)
168 {
169 int sample, state, nibble, count;
170 UINT32 pos, step;
171 const unsigned char *data;
172 int i;
173 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
174
175 if(!ch->playing) {
176 memset(buffer, 0, 2*length);
177 return;
178 }
179
180 sample = ch->sample;
181 state = ch->state;
182 pos = ch->pos;
183 step = ch->step;
184 nibble = ch->nibble;
185
186 data = ch->buffer;
187 count = ch->buffer_ptr;
188
189 if(!step)
190 step = 0x10000;
191
192 for(i=0; i<length; i++) {
193 mode_change:
194 if(ch->waiting) {
195 ch->wait_samples--;
196 if(ch->wait_samples == 0)
197 ch->waiting = 0;
198 } else {
199 pos += step;
200 while(pos & ~0xffff) {
201 int adpcm;
202 get_nibble:
203 if(!nibble) {
204 if(!count) {
205 no_more_data:
206 ch->nibble = nibble = 0;
207 ch->skip_last_nibble = 0;
208 if(ch->wait_samples) {
209 ch->waiting = 1;
210 goto mode_change;
211 }
212 if(ch->drq) {
213 if(UPD7759_chips.intf->mode == UPD7759_STANDALONE_MODE) {
214 ch->suspend = 0;
215 ch->buffer_ptr = 0;
216 UPD7759_standalone_load_data(chip);
217 data = ch->buffer;
218 count = ch->buffer_ptr;
219 goto get_nibble;
220 }
221 while(i<length) {
222 *buffer++ = sample << 7;
223 i++;
224 }
225 ch->skip_last_nibble = 0;
226 goto end;
227 } else {
228 ch->playing = 0;
229 memset(buffer, 0, (length-i)*2);
230 return;
231 }
232 }
233 adpcm = (*data) >> 4;
234 } else {
235 adpcm = (*data) & 0xf;
236 data++;
237 count--;
238 if(!count && ch->skip_last_nibble)
239 goto no_more_data;
240 }
241 nibble = !nibble;
242 sample += UPD7759_step[state][adpcm];
243 state += UPD7759_state[adpcm];
244 if(state < 0)
245 state = 0;
246 else if(state > 15)
247 state = 15;
248 pos -= 0x10000;
249 }
250 }
251 *buffer++ = sample << 7;
252 }
253
254 end:
255
256 ch->sample = sample;
257 ch->state = state;
258 ch->pos = pos;
259 ch->nibble = nibble;
260 if(data != ch->buffer && count)
261 memmove(ch->buffer, data, count);
262 ch->buffer_ptr = count;
263
264 if(ch->suspend && (ch->buffer_ptr < sizeof(ch->buffer)) && (ch->waiting || !ch->wait_samples))
265 ch->suspend = 0;
266 }
267
UPD7759_slave_tick(int chip)268 static void UPD7759_slave_tick(int chip)
269 {
270 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
271 if(ch->drq) {
272 if(ch->suspend)
273 stream_update(ch->channel, 0);
274 else if(UPD7759_chips.intf->irqcallback[chip])
275 UPD7759_chips.intf->irqcallback[chip](chip);
276 }
277 }
278
279
280 // Start emulation of several ADPCM output streams
UPD7759_sh_start(const struct MachineSound * msound)281 int UPD7759_sh_start(const struct MachineSound *msound)
282 {
283 int chip;
284 const struct UPD7759_interface *intf = msound->sound_interface;
285
286 if(!Machine->sample_rate)
287 return 0;
288
289 memset(&UPD7759_chips, 0, sizeof(UPD7759_chips));
290 /* copy the interface pointer to a global */
291 UPD7759_chips.intf = intf;
292
293 for(chip=0; chip<intf->num; chip++) {
294 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
295 char name[20];
296
297 ch->rom = memory_region(intf->region[chip]);
298 ch->cur_rombank = ch->rom;
299 ch->reset = 0; //* active low, should be zero because we're initializing
300 ch->start = 0; //* active high, initial state should be low - not started
301 ch->port = 0;
302 ch->playing = 0;
303 ch->drq = 0;
304 ch->suspend = 0;
305 ch->waiting = 0;
306 ch->wait_samples = 0;
307 ch->buffer_ptr = 0;
308 ch->rr_pos = 0;
309 ch->freq = 0;
310 ch->step = 0;
311 ch->nibble = 0;
312 ch->pos = 0;
313 ch->play_length = 0;
314 ch->param_mode = 0;
315 ch->started = 0;
316 ch->timer = timer_alloc(UPD7759_slave_tick);
317
318 sprintf(name, "uPD7759 #%d", chip);
319
320 ch->channel = stream_init(name, intf->volume[chip], Machine->sample_rate, chip, UPD7759_update);
321
322 UPD7759_reset_w(chip, 0); //* more comprehensive init
323 }
324 return 0;
325 }
326
UPD7759_set_frequency(struct UPD7759_chip * ch,UINT8 data)327 static void UPD7759_set_frequency(struct UPD7759_chip *ch, UINT8 data)
328 {
329 ch->freq = (640000/4) / ((data & 0x1f)+1);
330 ch->step = (((UINT64)(640000/4))<<16)/(Machine->sample_rate*((data & 0x1f)+1));
331 }
332
UPD7759_start_play(int chip,int length)333 static void UPD7759_start_play(int chip, int length)
334 {
335 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
336 ch->play_length = (length+1)/2;
337 ch->next_skip_last_nibble = length&1;
338 }
339
UPD7759_cmd_w(int chip,UINT8 data)340 static void UPD7759_cmd_w(int chip, UINT8 data)
341 {
342 enum { PARAM_8x = 1 };
343
344 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
345
346 if(!ch->drq && UPD7759_chips.intf->mode == UPD7759_SLAVE_MODE)
347 {
348 ch->playing = 1;
349 ch->state = 0;
350 ch->sample = 0;
351 ch->nibble = 0;
352 ch->pos = 0;
353 ch->buffer_ptr = 0;
354 ch->started = 0;
355 ch->drq = 1;
356 timer_adjust(ch->timer, TIME_IN_HZ(DRQ_FREQUENCY), chip, TIME_IN_HZ(DRQ_FREQUENCY));
357 return;
358 }
359
360 if(ch->play_length)
361 {
362 if(ch->skip_last_nibble)
363 {
364 ch->buffer[ch->buffer_ptr-1] = (ch->buffer[ch->buffer_ptr-1] & 0xf0) | (data >> 4);
365 ch->buffer[ch->buffer_ptr++] = data << 4;
366 } else
367 ch->buffer[ch->buffer_ptr++] = data;
368
369 ch->play_length--;
370
371 if(!ch->play_length)
372 {
373 if(ch->skip_last_nibble && ch->next_skip_last_nibble)
374 ch->buffer_ptr--;
375 ch->skip_last_nibble ^= ch->next_skip_last_nibble;
376 ch->next_skip_last_nibble = 0;
377 }
378
379 if(ch->buffer_ptr == sizeof(ch->buffer))
380 ch->suspend = 1;
381 return;
382 }
383
384 if(ch->param_mode)
385 {
386 switch(ch->param_mode)
387 {
388 case PARAM_8x:
389 ch->param_mode = 0;
390 UPD7759_start_play(chip, data + 1);
391 return;
392
393 default:
394 logerror("UPD7759.%d Unknown parameter mode %d ?\n", chip, ch->param_mode);
395 ch->param_mode = 0;
396 }
397 }
398
399 if(!ch->started && (data != 0x00 && data != 0xff))
400 ch->started = 1;
401
402 switch(data & 0xc0)
403 {
404 case 0x00:
405 if(data == 0x00)
406 {
407 if(ch->started) {
408 if(UPD7759_chips.intf->mode == UPD7759_SLAVE_MODE)
409 timer_adjust(ch->timer, TIME_NEVER, 0, 0);
410 ch->drq = 0;
411 }
412 }
413 else
414 {
415 ch->wait_samples += (Machine->sample_rate * data)/SILENCE_FREQUENCY;
416 ch->suspend = 1;
417 }
418 break;
419
420 case 0x40:
421 UPD7759_set_frequency(ch, data & 0x1f);
422 UPD7759_start_play(chip, 256);
423 break;
424
425 case 0x80:
426 UPD7759_set_frequency(ch, data & 0x1f);
427 ch->param_mode = PARAM_8x;
428 break;
429
430 case 0xc0:
431 if(data == 0xff) {
432 if(UPD7759_chips.intf->mode == UPD7759_STANDALONE_MODE)
433 logerror("UPD7759.%d: cmd_w 0xff in standalone mode\n", chip);
434 if(ch->drq && ch->started)
435 {
436 ch->drq = 0;
437 timer_adjust(ch->timer, TIME_NEVER, 0, 0);
438 }
439 }
440 else
441 logerror("UPD7759.%d: Unknown command %02x\n", chip, data);
442 break;
443 }
444 }
445
UPD7759_standalone_load_data(int chip)446 static void UPD7759_standalone_load_data(int chip)
447 {
448 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
449
450 while(ch->drq && !ch->suspend) {
451 UPD7759_cmd_w(chip, ch->cur_rombank[ch->rr_pos]);
452 ch->rr_pos = (ch->rr_pos + 1) & 0x1ffff;
453 }
454 }
455
UPD7759_reset_w(int chip,UINT8 data)456 void UPD7759_reset_w(int chip, UINT8 data)
457 {
458 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
459
460 if(Machine->sample_rate == 0)
461 return;
462
463 if(chip >= UPD7759_chips.intf->num) {
464 logerror("UPD7759_reset_w() called with channel = %d, but only %d channels allocated\n", chip, UPD7759_chips.intf->num);
465 return;
466 }
467
468 ch->reset = data;
469 if(!data) {
470 stream_update(ch->channel, 0);
471 ch->playing = 0;
472 ch->drq = 0;
473 ch->suspend = 0;
474 ch->rr_pos = 0;
475 ch->param_mode = 0;
476 ch->play_length = 0;
477 ch->waiting = 0;
478 ch->wait_samples = 0;
479
480 timer_adjust(ch->timer, TIME_NEVER, 0, 0); //* more comprehensive reset
481 }
482 }
483
UPD7759_start_w(int chip,UINT8 data)484 void UPD7759_start_w(int chip, UINT8 data)
485 {
486 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
487 int old_start;
488
489 if(Machine->sample_rate == 0)
490 return;
491
492 if(chip >= UPD7759_chips.intf->num) {
493 logerror("UPD7759_start_w() called with channel = %d, but only %d channels allocated\n", chip, UPD7759_chips.intf->num);
494 return;
495 }
496
497 old_start = ch->start;
498 ch->start = data;
499
500 // Start sample on rising edge, but ignore if already playing
501 if(!old_start && data && !ch->playing && UPD7759_chips.intf->mode == UPD7759_STANDALONE_MODE) {
502 UINT8 scount;
503
504 if(memcmp(ch->cur_rombank+1, "\x5A\xA5\x69\x55", 4))
505 logerror("UPD7759.%d: Header check failure on sample start\n", chip);
506
507 scount = ch->cur_rombank[0];
508
509 if(ch->port > scount) {
510 logerror("UPD7759.%d: Sample number %x is higher than rom sample number (%x)\n", chip, ch->port, scount);
511 return;
512 }
513
514 ch->rr_pos = ((ch->cur_rombank[5+ch->port*2]<<8)|ch->cur_rombank[6+ch->port*2])*2;
515
516 ch->playing = 1;
517 ch->drq = 1;
518 ch->state = 0;
519 ch->sample = 0;
520 ch->nibble = 0;
521 ch->pos = 0;
522 ch->buffer_ptr = 0;
523 ch->started = 0;
524 stream_update(ch->channel, 0);
525 }
526 }
527
UPD7759_port_w(int chip,UINT8 data)528 void UPD7759_port_w(int chip, UINT8 data)
529 {
530 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
531
532 if(Machine->sample_rate == 0)
533 return;
534
535 if(chip >= UPD7759_chips.intf->num) {
536 logerror("UPD7759_port_w() called with channel = %d, but only %d channels allocated\n", chip, UPD7759_chips.intf->num);
537 return;
538 }
539
540 ch->port = data;
541
542 if(UPD7759_chips.intf->mode == UPD7759_SLAVE_MODE) {
543 timer_adjust(ch->timer, TIME_IN_HZ(DRQ_FREQUENCY), chip, TIME_IN_HZ(DRQ_FREQUENCY));
544 UPD7759_cmd_w(chip, data);
545 }
546 }
547
UPD7759_busy_r(int chip)548 int UPD7759_busy_r(int chip)
549 {
550 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
551
552 if(Machine->sample_rate == 0)
553 return 0;
554
555 if(chip >= UPD7759_chips.intf->num) {
556 logerror("UPD7759_busy_r() called with channel = %d, but only %d channels allocated\n", chip, UPD7759_chips.intf->num);
557 return 0;
558 }
559
560 return !ch->playing;
561 }
562
UPD7759_set_bank_base(int chip,UINT32 base)563 void UPD7759_set_bank_base(int chip, UINT32 base)
564 {
565 struct UPD7759_chip *ch = &UPD7759_chips.chip[chip];
566
567 if(Machine->sample_rate == 0)
568 return;
569
570 if(chip >= UPD7759_chips.intf->num) {
571 logerror("UPD7759_set_bank_base() called with channel = %d, but only %d channels allocated\n", chip, UPD7759_chips.intf->num);
572 return;
573 }
574
575 ch->cur_rombank = ch->rom + base;
576 }
577
WRITE_HANDLER(UPD7759_0_start_w)578 WRITE_HANDLER(UPD7759_0_start_w)
579 {
580 UPD7759_start_w(0,data);
581 }
582
WRITE_HANDLER(UPD7759_0_reset_w)583 WRITE_HANDLER(UPD7759_0_reset_w)
584 {
585 UPD7759_reset_w(0,data);
586 }
587
WRITE_HANDLER(UPD7759_0_port_w)588 WRITE_HANDLER(UPD7759_0_port_w)
589 {
590 UPD7759_port_w(0,data);
591 }
592
READ_HANDLER(UPD7759_0_busy_r)593 READ_HANDLER(UPD7759_0_busy_r)
594 {
595 return UPD7759_busy_r(0);
596 }
597