1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <gtest/gtest.h>
25 #include "brw_vec4.h"
26 #include "program/program.h"
27
28 using namespace brw;
29
30 #define register_coalesce(v) _register_coalesce(v, __func__)
31
32 class register_coalesce_test : public ::testing::Test {
33 virtual void SetUp();
34 virtual void TearDown();
35
36 public:
37 struct brw_compiler *compiler;
38 struct intel_device_info *devinfo;
39 void *ctx;
40 struct gl_shader_program *shader_prog;
41 struct brw_vue_prog_data *prog_data;
42 vec4_visitor *v;
43 };
44
45
46 class register_coalesce_vec4_visitor : public vec4_visitor
47 {
48 public:
register_coalesce_vec4_visitor(struct brw_compiler * compiler,void * mem_ctx,nir_shader * shader,struct brw_vue_prog_data * prog_data)49 register_coalesce_vec4_visitor(struct brw_compiler *compiler,
50 void *mem_ctx,
51 nir_shader *shader,
52 struct brw_vue_prog_data *prog_data)
53 : vec4_visitor(compiler, NULL, NULL, prog_data, shader, mem_ctx,
54 false /* no_spills */, -1, false)
55 {
56 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
57 }
58
59 protected:
make_reg_for_system_value(int)60 virtual dst_reg *make_reg_for_system_value(int /* location */)
61 {
62 unreachable("Not reached");
63 }
64
setup_payload()65 virtual void setup_payload()
66 {
67 unreachable("Not reached");
68 }
69
emit_prolog()70 virtual void emit_prolog()
71 {
72 unreachable("Not reached");
73 }
74
emit_thread_end()75 virtual void emit_thread_end()
76 {
77 unreachable("Not reached");
78 }
79
emit_urb_write_header(int)80 virtual void emit_urb_write_header(int /* mrf */)
81 {
82 unreachable("Not reached");
83 }
84
emit_urb_write_opcode(bool)85 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */)
86 {
87 unreachable("Not reached");
88 }
89 };
90
91
SetUp()92 void register_coalesce_test::SetUp()
93 {
94 ctx = ralloc_context(NULL);
95 compiler = rzalloc(ctx, struct brw_compiler);
96 devinfo = rzalloc(ctx, struct intel_device_info);
97 compiler->devinfo = devinfo;
98
99 prog_data = ralloc(ctx, struct brw_vue_prog_data);
100
101 nir_shader *shader =
102 nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL);
103
104 v = new register_coalesce_vec4_visitor(compiler, ctx, shader, prog_data);
105
106 devinfo->ver = 4;
107 devinfo->verx10 = devinfo->ver * 10;
108 }
109
TearDown()110 void register_coalesce_test::TearDown()
111 {
112 delete v;
113 v = NULL;
114
115 ralloc_free(ctx);
116 ctx = NULL;
117 }
118
119 static void
_register_coalesce(vec4_visitor * v,const char * func)120 _register_coalesce(vec4_visitor *v, const char *func)
121 {
122 const bool print = getenv("TEST_DEBUG");
123
124 if (print) {
125 printf("%s: instructions before:\n", func);
126 v->dump_instructions();
127 }
128
129 v->calculate_cfg();
130 v->opt_register_coalesce();
131
132 if (print) {
133 printf("%s: instructions after:\n", func);
134 v->dump_instructions();
135 }
136 }
137
TEST_F(register_coalesce_test,test_compute_to_mrf)138 TEST_F(register_coalesce_test, test_compute_to_mrf)
139 {
140 src_reg something = src_reg(v, glsl_type::float_type);
141 dst_reg temp = dst_reg(v, glsl_type::float_type);
142 dst_reg init;
143
144 dst_reg m0 = dst_reg(MRF, 0);
145 m0.writemask = WRITEMASK_X;
146 m0.type = BRW_REGISTER_TYPE_F;
147
148 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
149 v->emit(v->MOV(m0, src_reg(temp)));
150
151 register_coalesce(v);
152
153 EXPECT_EQ(mul->dst.file, MRF);
154 }
155
156
TEST_F(register_coalesce_test,test_multiple_use)157 TEST_F(register_coalesce_test, test_multiple_use)
158 {
159 src_reg something = src_reg(v, glsl_type::float_type);
160 dst_reg temp = dst_reg(v, glsl_type::vec4_type);
161 dst_reg init;
162
163 dst_reg m0 = dst_reg(MRF, 0);
164 m0.writemask = WRITEMASK_X;
165 m0.type = BRW_REGISTER_TYPE_F;
166
167 dst_reg m1 = dst_reg(MRF, 1);
168 m1.writemask = WRITEMASK_XYZW;
169 m1.type = BRW_REGISTER_TYPE_F;
170
171 src_reg src = src_reg(temp);
172 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
173 src.swizzle = BRW_SWIZZLE_XXXX;
174 v->emit(v->MOV(m0, src));
175 src.swizzle = BRW_SWIZZLE_XYZW;
176 v->emit(v->MOV(m1, src));
177
178 register_coalesce(v);
179
180 EXPECT_NE(mul->dst.file, MRF);
181 }
182
TEST_F(register_coalesce_test,test_dp4_mrf)183 TEST_F(register_coalesce_test, test_dp4_mrf)
184 {
185 src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
186 src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
187 dst_reg init;
188
189 dst_reg m0 = dst_reg(MRF, 0);
190 m0.writemask = WRITEMASK_Y;
191 m0.type = BRW_REGISTER_TYPE_F;
192
193 dst_reg temp = dst_reg(v, glsl_type::float_type);
194
195 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
196 v->emit(v->MOV(m0, src_reg(temp)));
197
198 register_coalesce(v);
199
200 EXPECT_EQ(dp4->dst.file, MRF);
201 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
202 }
203
TEST_F(register_coalesce_test,test_dp4_grf)204 TEST_F(register_coalesce_test, test_dp4_grf)
205 {
206 src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
207 src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
208 dst_reg init;
209
210 dst_reg to = dst_reg(v, glsl_type::vec4_type);
211 dst_reg temp = dst_reg(v, glsl_type::float_type);
212
213 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
214 to.writemask = WRITEMASK_Y;
215 v->emit(v->MOV(to, src_reg(temp)));
216
217 /* if we don't do something with the result, the automatic dead code
218 * elimination will remove all our instructions.
219 */
220 src_reg src = src_reg(to);
221 src.negate = true;
222 v->emit(v->MOV(dst_reg(MRF, 0), src));
223
224 register_coalesce(v);
225
226 EXPECT_EQ(dp4->dst.nr, to.nr);
227 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
228 }
229
TEST_F(register_coalesce_test,test_channel_mul_grf)230 TEST_F(register_coalesce_test, test_channel_mul_grf)
231 {
232 src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
233 src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
234 dst_reg init;
235
236 dst_reg to = dst_reg(v, glsl_type::vec4_type);
237 dst_reg temp = dst_reg(v, glsl_type::float_type);
238
239 vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2));
240 to.writemask = WRITEMASK_Y;
241 v->emit(v->MOV(to, src_reg(temp)));
242
243 /* if we don't do something with the result, the automatic dead code
244 * elimination will remove all our instructions.
245 */
246 src_reg src = src_reg(to);
247 src.negate = true;
248 v->emit(v->MOV(dst_reg(MRF, 0), src));
249
250 register_coalesce(v);
251
252 EXPECT_EQ(mul->dst.nr, to.nr);
253 }
254