1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 3 4define amdgpu_cs i32 @test_shl_and_1(i32 inreg %arg1) { 5; CHECK-LABEL: test_shl_and_1: 6; CHECK: ; %bb.0: ; %.entry 7; CHECK-NEXT: s_lshl_b32 s0, s0, 4 8; CHECK-NEXT: ; return to shader part epilog 9.entry: 10 %z1 = shl i32 %arg1, 2 11 %z2 = and i32 %z1, 1073741820 12 %z3 = shl i32 %z2, 2 13 ret i32 %z3 14} 15 16define amdgpu_cs i32 @test_shl_and_2(i32 inreg %arg1) { 17; CHECK-LABEL: test_shl_and_2: 18; CHECK: ; %bb.0: ; %.entry 19; CHECK-NEXT: s_lshl_b32 s0, s0, 8 20; CHECK-NEXT: ; return to shader part epilog 21.entry: 22 %z1 = shl i32 %arg1, 5 23 %z2 = and i32 %z1, 536870880 24 %z3 = shl i32 %z2, 3 25 ret i32 %z3 26} 27 28define amdgpu_cs i32 @test_shl_and_3(i32 inreg %arg1) { 29; CHECK-LABEL: test_shl_and_3: 30; CHECK: ; %bb.0: ; %.entry 31; CHECK-NEXT: s_lshl_b32 s0, s0, 5 32; CHECK-NEXT: s_and_b32 s0, s0, 0x7ffffff0 33; CHECK-NEXT: ; return to shader part epilog 34.entry: 35 %z1 = shl i32 %arg1, 3 36 %z2 = and i32 %z1, 536870908 37 %z3 = shl i32 %z2, 2 38 ret i32 %z3 39} 40 41define amdgpu_cs i32 @test_lshr_and_1(i32 inreg %arg1) { 42; CHECK-LABEL: test_lshr_and_1: 43; CHECK: ; %bb.0: ; %.entry 44; CHECK-NEXT: s_lshr_b32 s0, s0, 4 45; CHECK-NEXT: ; return to shader part epilog 46.entry: 47 %z1 = lshr i32 %arg1, 2 48 %z2 = and i32 %z1, 1073741820 49 %z3 = lshr i32 %z2, 2 50 ret i32 %z3 51} 52 53define amdgpu_cs i32 @test_lshr_and_2(i32 inreg %arg1) { 54; CHECK-LABEL: test_lshr_and_2: 55; CHECK: ; %bb.0: ; %.entry 56; CHECK-NEXT: s_lshr_b32 s0, s0, 8 57; CHECK-NEXT: s_and_b32 s0, s0, 0x3fffffc 58; CHECK-NEXT: ; return to shader part epilog 59.entry: 60 %z1 = lshr i32 %arg1, 5 61 %z2 = and i32 %z1, 536870880 62 %z3 = lshr i32 %z2, 3 63 ret i32 %z3 64} 65 66define amdgpu_cs i32 @test_lshr_and_3(i32 inreg %arg1) { 67; CHECK-LABEL: test_lshr_and_3: 68; CHECK: ; %bb.0: ; %.entry 69; CHECK-NEXT: s_lshr_b32 s0, s0, 5 70; CHECK-NEXT: ; return to shader part epilog 71.entry: 72 %z1 = lshr i32 %arg1, 3 73 %z2 = and i32 %z1, 536870908 74 %z3 = lshr i32 %z2, 2 75 ret i32 %z3 76} 77 78define amdgpu_cs i32 @test_ashr_and_1(i32 inreg %arg1) { 79; CHECK-LABEL: test_ashr_and_1: 80; CHECK: ; %bb.0: ; %.entry 81; CHECK-NEXT: s_ashr_i32 s0, s0, 4 82; CHECK-NEXT: s_and_b32 s0, s0, 0xfffffff 83; CHECK-NEXT: ; return to shader part epilog 84.entry: 85 %z1 = ashr i32 %arg1, 2 86 %z2 = and i32 %z1, 1073741820 87 %z3 = ashr i32 %z2, 2 88 ret i32 %z3 89} 90 91define amdgpu_cs i32 @test_ashr_and_2(i32 inreg %arg1) { 92; CHECK-LABEL: test_ashr_and_2: 93; CHECK: ; %bb.0: ; %.entry 94; CHECK-NEXT: s_ashr_i32 s0, s0, 8 95; CHECK-NEXT: s_and_b32 s0, s0, 0x3fffffc 96; CHECK-NEXT: ; return to shader part epilog 97.entry: 98 %z1 = ashr i32 %arg1, 5 99 %z2 = and i32 %z1, 536870880 100 %z3 = ashr i32 %z2, 3 101 ret i32 %z3 102} 103 104define amdgpu_cs i32 @test_ashr_and_3(i32 inreg %arg1) { 105; CHECK-LABEL: test_ashr_and_3: 106; CHECK: ; %bb.0: ; %.entry 107; CHECK-NEXT: s_ashr_i32 s0, s0, 5 108; CHECK-NEXT: s_and_b32 s0, s0, 0x7ffffff 109; CHECK-NEXT: ; return to shader part epilog 110.entry: 111 %z1 = ashr i32 %arg1, 3 112 %z2 = and i32 %z1, 536870908 113 %z3 = ashr i32 %z2, 2 114 ret i32 %z3 115} 116 117define amdgpu_cs i32 @test_shl_or_1(i32 inreg %arg1) { 118; CHECK-LABEL: test_shl_or_1: 119; CHECK: ; %bb.0: ; %.entry 120; CHECK-NEXT: s_lshl_b32 s0, s0, 4 121; CHECK-NEXT: s_or_b32 s0, s0, 12 122; CHECK-NEXT: ; return to shader part epilog 123.entry: 124 %z1 = shl i32 %arg1, 2 125 %z2 = or i32 %z1, 3221225475 126 %z3 = shl i32 %z2, 2 127 ret i32 %z3 128} 129 130define amdgpu_cs i32 @test_shl_or_2(i32 inreg %arg1) { 131; CHECK-LABEL: test_shl_or_2: 132; CHECK: ; %bb.0: ; %.entry 133; CHECK-NEXT: s_lshl_b32 s0, s0, 8 134; CHECK-NEXT: s_or_b32 s0, s0, 0xfffffc00 135; CHECK-NEXT: ; return to shader part epilog 136.entry: 137 %z1 = shl i32 %arg1, 3 138 %z2 = or i32 %z1, 536870880 139 %z3 = shl i32 %z2, 5 140 ret i32 %z3 141} 142 143define amdgpu_cs i32 @test_shl_or_3(i32 inreg %arg1) { 144; CHECK-LABEL: test_shl_or_3: 145; CHECK: ; %bb.0: ; %.entry 146; CHECK-NEXT: s_lshl_b32 s0, s0, 5 147; CHECK-NEXT: s_or_b32 s0, s0, 0x7fffff80 148; CHECK-NEXT: ; return to shader part epilog 149.entry: 150 %z1 = shl i32 %arg1, 2 151 %z2 = or i32 %z1, 268435440 152 %z3 = shl i32 %z2, 3 153 ret i32 %z3 154} 155 156define amdgpu_cs i32 @test_lshr_or_1(i32 inreg %arg1) { 157; CHECK-LABEL: test_lshr_or_1: 158; CHECK: ; %bb.0: ; %.entry 159; CHECK-NEXT: s_lshr_b32 s0, s0, 4 160; CHECK-NEXT: ; return to shader part epilog 161.entry: 162 %z1 = lshr i32 %arg1, 2 163 %z2 = or i32 %z1, 3 164 %z3 = lshr i32 %z2, 2 165 ret i32 %z3 166} 167 168define amdgpu_cs i32 @test_lshr_or_2(i32 inreg %arg1) { 169; CHECK-LABEL: test_lshr_or_2: 170; CHECK: ; %bb.0: ; %.entry 171; CHECK-NEXT: s_mov_b32 s0, 0xffffff 172; CHECK-NEXT: ; return to shader part epilog 173.entry: 174 %z1 = lshr i32 %arg1, 3 175 %z2 = or i32 %z1, 536870880 176 %z3 = lshr i32 %z2, 5 177 ret i32 %z3 178} 179 180define amdgpu_cs i32 @test_lshr_or_3(i32 inreg %arg1) { 181; CHECK-LABEL: test_lshr_or_3: 182; CHECK: ; %bb.0: ; %.entry 183; CHECK-NEXT: s_lshr_b32 s0, s0, 5 184; CHECK-NEXT: s_or_b32 s0, s0, 0x1fffffe 185; CHECK-NEXT: ; return to shader part epilog 186.entry: 187 %z1 = lshr i32 %arg1, 2 188 %z2 = or i32 %z1, 268435440 189 %z3 = lshr i32 %z2, 3 190 ret i32 %z3 191} 192 193define amdgpu_cs i32 @test_ashr_or_1(i32 inreg %arg1) { 194; CHECK-LABEL: test_ashr_or_1: 195; CHECK: ; %bb.0: ; %.entry 196; CHECK-NEXT: s_ashr_i32 s0, s0, 4 197; CHECK-NEXT: ; return to shader part epilog 198.entry: 199 %z1 = ashr i32 %arg1, 2 200 %z2 = or i32 %z1, 3 201 %z3 = ashr i32 %z2, 2 202 ret i32 %z3 203} 204 205define amdgpu_cs i32 @test_ashr_or_2(i32 inreg %arg1) { 206; CHECK-LABEL: test_ashr_or_2: 207; CHECK: ; %bb.0: ; %.entry 208; CHECK-NEXT: s_ashr_i32 s0, s0, 8 209; CHECK-NEXT: s_or_b32 s0, s0, 0xffffff 210; CHECK-NEXT: ; return to shader part epilog 211.entry: 212 %z1 = ashr i32 %arg1, 3 213 %z2 = or i32 %z1, 536870880 214 %z3 = ashr i32 %z2, 5 215 ret i32 %z3 216} 217 218define amdgpu_cs i32 @test_ashr_or_3(i32 inreg %arg1) { 219; CHECK-LABEL: test_ashr_or_3: 220; CHECK: ; %bb.0: ; %.entry 221; CHECK-NEXT: s_ashr_i32 s0, s0, 5 222; CHECK-NEXT: s_or_b32 s0, s0, 0x1fffffe 223; CHECK-NEXT: ; return to shader part epilog 224.entry: 225 %z1 = ashr i32 %arg1, 2 226 %z2 = or i32 %z1, 268435440 227 %z3 = ashr i32 %z2, 3 228 ret i32 %z3 229} 230 231define amdgpu_cs i32 @test_shl_xor_1(i32 inreg %arg1) { 232; CHECK-LABEL: test_shl_xor_1: 233; CHECK: ; %bb.0: ; %.entry 234; CHECK-NEXT: s_lshl_b32 s0, s0, 4 235; CHECK-NEXT: s_xor_b32 s0, s0, -16 236; CHECK-NEXT: ; return to shader part epilog 237.entry: 238 %z1 = shl i32 %arg1, 2 239 %z2 = xor i32 %z1, 1073741820 240 %z3 = shl i32 %z2, 2 241 ret i32 %z3 242} 243 244define amdgpu_cs i32 @test_shl_xor_2(i32 inreg %arg1) { 245; CHECK-LABEL: test_shl_xor_2: 246; CHECK: ; %bb.0: ; %.entry 247; CHECK-NEXT: s_lshl_b32 s0, s0, 6 248; CHECK-NEXT: ; return to shader part epilog 249.entry: 250 %z1 = shl i32 %arg1, 1 251 %z2 = xor i32 %z1, 4160749568 252 %z3 = shl i32 %z2, 5 253 ret i32 %z3 254} 255 256define amdgpu_cs i32 @test_shl_xor_3(i32 inreg %arg1) { 257; CHECK-LABEL: test_shl_xor_3: 258; CHECK: ; %bb.0: ; %.entry 259; CHECK-NEXT: s_lshl_b32 s0, s0, 5 260; CHECK-NEXT: s_xor_b32 s0, s0, 56 261; CHECK-NEXT: ; return to shader part epilog 262.entry: 263 %z1 = shl i32 %arg1, 2 264 %z2 = xor i32 %z1, 3221225479 265 %z3 = shl i32 %z2, 3 266 ret i32 %z3 267} 268 269define amdgpu_cs i32 @test_lshr_xor_1(i32 inreg %arg1) { 270; CHECK-LABEL: test_lshr_xor_1: 271; CHECK: ; %bb.0: ; %.entry 272; CHECK-NEXT: s_lshr_b32 s0, s0, 4 273; CHECK-NEXT: s_xor_b32 s0, s0, 0xfffffff 274; CHECK-NEXT: ; return to shader part epilog 275.entry: 276 %z1 = lshr i32 %arg1, 2 277 %z2 = xor i32 %z1, 1073741820 278 %z3 = lshr i32 %z2, 2 279 ret i32 %z3 280} 281 282define amdgpu_cs i32 @test_lshr_xor_2(i32 inreg %arg1) { 283; CHECK-LABEL: test_lshr_xor_2: 284; CHECK: ; %bb.0: ; %.entry 285; CHECK-NEXT: s_lshr_b32 s0, s0, 6 286; CHECK-NEXT: ; return to shader part epilog 287.entry: 288 %z1 = lshr i32 %arg1, 1 289 %z2 = xor i32 %z1, 31 290 %z3 = lshr i32 %z2, 5 291 ret i32 %z3 292} 293 294define amdgpu_cs i32 @test_lshr_xor_3(i32 inreg %arg1) { 295; CHECK-LABEL: test_lshr_xor_3: 296; CHECK: ; %bb.0: ; %.entry 297; CHECK-NEXT: s_lshr_b32 s0, s0, 5 298; CHECK-NEXT: s_xor_b32 s0, s0, 0x18000000 299; CHECK-NEXT: ; return to shader part epilog 300.entry: 301 %z1 = lshr i32 %arg1, 2 302 %z2 = xor i32 %z1, 3221225479 303 %z3 = lshr i32 %z2, 3 304 ret i32 %z3 305} 306 307define amdgpu_cs i32 @test_ashr_xor_1(i32 inreg %arg1) { 308; CHECK-LABEL: test_ashr_xor_1: 309; CHECK: ; %bb.0: ; %.entry 310; CHECK-NEXT: s_ashr_i32 s0, s0, 4 311; CHECK-NEXT: s_xor_b32 s0, s0, 0xfffffff 312; CHECK-NEXT: ; return to shader part epilog 313.entry: 314 %z1 = ashr i32 %arg1, 2 315 %z2 = xor i32 %z1, 1073741820 316 %z3 = ashr i32 %z2, 2 317 ret i32 %z3 318} 319 320define amdgpu_cs i32 @test_ashr_xor_2(i32 inreg %arg1) { 321; CHECK-LABEL: test_ashr_xor_2: 322; CHECK: ; %bb.0: ; %.entry 323; CHECK-NEXT: s_ashr_i32 s0, s0, 6 324; CHECK-NEXT: ; return to shader part epilog 325.entry: 326 %z1 = ashr i32 %arg1, 1 327 %z2 = xor i32 %z1, 31 328 %z3 = ashr i32 %z2, 5 329 ret i32 %z3 330} 331 332define amdgpu_cs i32 @test_ashr_xor_3(i32 inreg %arg1) { 333; CHECK-LABEL: test_ashr_xor_3: 334; CHECK: ; %bb.0: ; %.entry 335; CHECK-NEXT: s_ashr_i32 s0, s0, 5 336; CHECK-NEXT: s_xor_b32 s0, s0, 0xf8000000 337; CHECK-NEXT: ; return to shader part epilog 338.entry: 339 %z1 = ashr i32 %arg1, 2 340 %z2 = xor i32 %z1, 3221225479 341 %z3 = ashr i32 %z2, 3 342 ret i32 %z3 343} 344