1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
3
4define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
5; CHECK-LABEL: test_vmullbq_int_u8:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vmullb.u8 q0, q0, q1
8; CHECK-NEXT:    bx lr
9entry:
10  %0 = tail call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0)
11  ret <8 x i16> %0
12}
13
14declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1
15
16define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
17; CHECK-LABEL: test_vmullbq_int_s16:
18; CHECK:       @ %bb.0: @ %entry
19; CHECK-NEXT:    vmullb.s16 q0, q0, q1
20; CHECK-NEXT:    bx lr
21entry:
22  %0 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0)
23  ret <4 x i32> %0
24}
25
26declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1
27
28define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
29; CHECK-LABEL: test_vmullbq_int_u32:
30; CHECK:       @ %bb.0: @ %entry
31; CHECK-NEXT:    vmullb.u32 q2, q0, q1
32; CHECK-NEXT:    vmov q0, q2
33; CHECK-NEXT:    bx lr
34entry:
35  %0 = tail call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0)
36  ret <2 x i64> %0
37}
38
39declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1
40
41define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
42; CHECK-LABEL: test_vmullbq_poly_p16:
43; CHECK:       @ %bb.0: @ %entry
44; CHECK-NEXT:    vmullb.p16 q0, q0, q1
45; CHECK-NEXT:    bx lr
46entry:
47  %0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0)
48  ret <4 x i32> %0
49}
50
51declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
52
53define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
54; CHECK-LABEL: test_vmullbq_int_m_s8:
55; CHECK:       @ %bb.0: @ %entry
56; CHECK-NEXT:    vmsr p0, r0
57; CHECK-NEXT:    vpst
58; CHECK-NEXT:    vmullbt.s8 q0, q1, q2
59; CHECK-NEXT:    bx lr
60entry:
61  %0 = zext i16 %p to i32
62  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
63  %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)
64  ret <8 x i16> %2
65}
66
67declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
68
69declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
70
71define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) #0 {
72; CHECK-LABEL: test_vmullbq_int_m_u16:
73; CHECK:       @ %bb.0: @ %entry
74; CHECK-NEXT:    vmsr p0, r0
75; CHECK-NEXT:    vpst
76; CHECK-NEXT:    vmullbt.u16 q0, q1, q2
77; CHECK-NEXT:    bx lr
78entry:
79  %0 = zext i16 %p to i32
80  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
81  %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)
82  ret <4 x i32> %2
83}
84
85declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
86
87declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
88
89define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
90; CHECK-LABEL: test_vmullbq_int_m_s32:
91; CHECK:       @ %bb.0: @ %entry
92; CHECK-NEXT:    vmsr p0, r0
93; CHECK-NEXT:    vpst
94; CHECK-NEXT:    vmullbt.s32 q0, q1, q2
95; CHECK-NEXT:    bx lr
96entry:
97  %0 = zext i16 %p to i32
98  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
99  %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, <4 x i1> %1, <2 x i64> %inactive)
100  ret <2 x i64> %2
101}
102
103declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32, <4 x i1>, <2 x i64>) #1
104
105define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
106; CHECK-LABEL: test_vmullbq_poly_m_p8:
107; CHECK:       @ %bb.0: @ %entry
108; CHECK-NEXT:    vmsr p0, r0
109; CHECK-NEXT:    vpst
110; CHECK-NEXT:    vmullbt.p8 q0, q1, q2
111; CHECK-NEXT:    bx lr
112entry:
113  %0 = zext i16 %p to i32
114  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
115  %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 0, <8 x i1> %1, <8 x i16> %inactive)
116  ret <8 x i16> %2
117}
118
119declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
120
121define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
122; CHECK-LABEL: test_vmullbq_int_x_u8:
123; CHECK:       @ %bb.0: @ %entry
124; CHECK-NEXT:    vmsr p0, r0
125; CHECK-NEXT:    vpst
126; CHECK-NEXT:    vmullbt.u8 q0, q0, q1
127; CHECK-NEXT:    bx lr
128entry:
129  %0 = zext i16 %p to i32
130  %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
131  %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef)
132  ret <8 x i16> %2
133}
134
135define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
136; CHECK-LABEL: test_vmullbq_int_x_s16:
137; CHECK:       @ %bb.0: @ %entry
138; CHECK-NEXT:    vmsr p0, r0
139; CHECK-NEXT:    vpst
140; CHECK-NEXT:    vmullbt.s16 q0, q0, q1
141; CHECK-NEXT:    bx lr
142entry:
143  %0 = zext i16 %p to i32
144  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
145  %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef)
146  ret <4 x i32> %2
147}
148
149define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
150; CHECK-LABEL: test_vmullbq_int_x_u32:
151; CHECK:       @ %bb.0: @ %entry
152; CHECK-NEXT:    vmsr p0, r0
153; CHECK-NEXT:    vpst
154; CHECK-NEXT:    vmullbt.u32 q2, q0, q1
155; CHECK-NEXT:    vmov q0, q2
156; CHECK-NEXT:    bx lr
157entry:
158  %0 = zext i16 %p to i32
159  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
160  %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, <4 x i1> %1, <2 x i64> undef)
161  ret <2 x i64> %2
162}
163
164define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_x_p16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
165; CHECK-LABEL: test_vmullbq_poly_x_p16:
166; CHECK:       @ %bb.0: @ %entry
167; CHECK-NEXT:    vmsr p0, r0
168; CHECK-NEXT:    vpst
169; CHECK-NEXT:    vmullbt.p16 q0, q0, q1
170; CHECK-NEXT:    bx lr
171entry:
172  %0 = zext i16 %p to i32
173  %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
174  %2 = tail call <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, <4 x i1> %1, <4 x i32> undef)
175  ret <4 x i32> %2
176}
177
178declare <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1
179