1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <errno.h>
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_screen.h"
29 #include "util/u_inlines.h"
30 #include "util/format/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/ralloc.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "intel/compiler/brw_compiler.h"
37
38 static bool
iris_is_color_fast_clear_compatible(struct iris_context * ice,enum isl_format format,const union isl_color_value color)39 iris_is_color_fast_clear_compatible(struct iris_context *ice,
40 enum isl_format format,
41 const union isl_color_value color)
42 {
43 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
44 const struct intel_device_info *devinfo = &batch->screen->devinfo;
45
46 if (isl_format_has_int_channel(format)) {
47 perf_debug(&ice->dbg, "Integer fast clear not enabled for %s\n",
48 isl_format_get_name(format));
49 return false;
50 }
51
52 for (int i = 0; i < 4; i++) {
53 if (!isl_format_has_color_component(format, i)) {
54 continue;
55 }
56
57 if (devinfo->ver < 9 &&
58 color.f32[i] != 0.0f && color.f32[i] != 1.0f) {
59 return false;
60 }
61 }
62
63 return true;
64 }
65
66 static bool
can_fast_clear_color(struct iris_context * ice,struct pipe_resource * p_res,unsigned level,const struct pipe_box * box,bool render_condition_enabled,enum isl_format render_format,union isl_color_value color)67 can_fast_clear_color(struct iris_context *ice,
68 struct pipe_resource *p_res,
69 unsigned level,
70 const struct pipe_box *box,
71 bool render_condition_enabled,
72 enum isl_format render_format,
73 union isl_color_value color)
74 {
75 struct iris_resource *res = (void *) p_res;
76
77 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
78 return false;
79
80 if (!isl_aux_usage_has_fast_clears(res->aux.usage))
81 return false;
82
83 /* Check for partial clear */
84 if (box->x > 0 || box->y > 0 ||
85 box->width < u_minify(p_res->width0, level) ||
86 box->height < u_minify(p_res->height0, level)) {
87 return false;
88 }
89
90 /* Avoid conditional fast clears to maintain correct tracking of the aux
91 * state (see iris_resource_finish_write for more info). Note that partial
92 * fast clears (if they existed) would not pose a problem with conditional
93 * rendering.
94 */
95 if (render_condition_enabled &&
96 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
97 return false;
98 }
99
100 /* Disable sRGB fast-clears for non-0/1 color values. For texturing and
101 * draw calls, HW expects the clear color to be in two different color
102 * spaces after sRGB fast-clears - sRGB in the former and linear in the
103 * latter. By limiting the allowable values to 0/1, both color space
104 * requirements are satisfied.
105 */
106 if (isl_format_is_srgb(render_format) &&
107 !isl_color_value_is_zero_one(color, render_format)) {
108 return false;
109 }
110
111 /* We store clear colors as floats or uints as needed. If there are
112 * texture views in play, the formats will not properly be respected
113 * during resolves because the resolve operations only know about the
114 * resource and not the renderbuffer.
115 */
116 if (!iris_render_formats_color_compatible(render_format, res->surf.format,
117 color, false)) {
118 return false;
119 }
120
121 if (!iris_is_color_fast_clear_compatible(ice, res->surf.format, color))
122 return false;
123
124 /* The RENDER_SURFACE_STATE page for TGL says:
125 *
126 * For an 8 bpp surface with NUM_MULTISAMPLES = 1, Surface Width not
127 * multiple of 64 pixels and more than 1 mip level in the view, Fast Clear
128 * is not supported when AUX_CCS_E is set in this field.
129 *
130 * The granularity of a fast-clear is one CCS element. For an 8 bpp primary
131 * surface, this maps to 32px x 4rows. Due to the surface layout parameters,
132 * if LOD0's width isn't a multiple of 64px, LOD1 and LOD2+ will share CCS
133 * elements. Assuming LOD2 exists, don't fast-clear any level above LOD0
134 * to avoid stomping on other LODs.
135 */
136 if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 &&
137 res->aux.usage == ISL_AUX_USAGE_GFX12_CCS_E && p_res->width0 % 64) {
138 return false;
139 }
140
141 return true;
142 }
143
144 static union isl_color_value
convert_clear_color(enum pipe_format format,const union pipe_color_union * color)145 convert_clear_color(enum pipe_format format,
146 const union pipe_color_union *color)
147 {
148 uint32_t pixel[4];
149 util_format_pack_rgba(format, pixel, color, 1);
150
151 union isl_color_value converted_color;
152 util_format_unpack_rgba(format, &converted_color, pixel, 1);
153
154 /* The converted clear color has channels that are:
155 * - clamped
156 * - quantized
157 * - filled with 0/1 if missing from the format
158 * - swizzled for luminance and intensity formats
159 */
160 return converted_color;
161 }
162
163 static void
fast_clear_color(struct iris_context * ice,struct iris_resource * res,unsigned level,const struct pipe_box * box,union isl_color_value color)164 fast_clear_color(struct iris_context *ice,
165 struct iris_resource *res,
166 unsigned level,
167 const struct pipe_box *box,
168 union isl_color_value color)
169 {
170 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
171 const struct intel_device_info *devinfo = &batch->screen->devinfo;
172 struct pipe_resource *p_res = (void *) res;
173
174 bool color_changed = res->aux.clear_color_unknown ||
175 memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0;
176
177 if (color_changed) {
178 /* If we are clearing to a new clear value, we need to resolve fast
179 * clears from other levels/layers first, since we can't have different
180 * levels/layers with different fast clear colors.
181 */
182 for (unsigned res_lvl = 0; res_lvl < res->surf.levels; res_lvl++) {
183 const unsigned level_layers =
184 iris_get_num_logical_layers(res, res_lvl);
185 for (unsigned layer = 0; layer < level_layers; layer++) {
186 if (res_lvl == level &&
187 layer >= box->z &&
188 layer < box->z + box->depth) {
189 /* We're going to clear this layer anyway. Leave it alone. */
190 continue;
191 }
192
193 enum isl_aux_state aux_state =
194 iris_resource_get_aux_state(res, res_lvl, layer);
195
196 if (aux_state != ISL_AUX_STATE_CLEAR &&
197 aux_state != ISL_AUX_STATE_PARTIAL_CLEAR &&
198 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
199 /* This slice doesn't have any fast-cleared bits. */
200 continue;
201 }
202
203 /* If we got here, then the level may have fast-clear bits that use
204 * the old clear value. We need to do a color resolve to get rid
205 * of their use of the clear color before we can change it.
206 * Fortunately, few applications ever change their clear color at
207 * different levels/layers, so this shouldn't happen often.
208 */
209 iris_resource_prepare_access(ice, res,
210 res_lvl, 1, layer, 1,
211 res->aux.usage,
212 false);
213 if (res->aux.clear_color_unknown) {
214 perf_debug(&ice->dbg,
215 "Resolving resource (%p) level %d, layer %d: color changing from "
216 "(unknown) to (%0.2f, %0.2f, %0.2f, %0.2f)\n",
217 res, res_lvl, layer,
218 color.f32[0], color.f32[1], color.f32[2], color.f32[3]);
219 } else {
220 perf_debug(&ice->dbg,
221 "Resolving resource (%p) level %d, layer %d: color changing from "
222 "(%0.2f, %0.2f, %0.2f, %0.2f) to "
223 "(%0.2f, %0.2f, %0.2f, %0.2f)\n",
224 res, res_lvl, layer,
225 res->aux.clear_color.f32[0],
226 res->aux.clear_color.f32[1],
227 res->aux.clear_color.f32[2],
228 res->aux.clear_color.f32[3],
229 color.f32[0], color.f32[1], color.f32[2], color.f32[3]);
230 }
231 }
232 }
233 }
234
235 iris_resource_set_clear_color(ice, res, color);
236
237 /* If the buffer is already in ISL_AUX_STATE_CLEAR, and the color hasn't
238 * changed, the clear is redundant and can be skipped.
239 */
240 const enum isl_aux_state aux_state =
241 iris_resource_get_aux_state(res, level, box->z);
242 if (!color_changed && box->depth == 1 && aux_state == ISL_AUX_STATE_CLEAR)
243 return;
244
245 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
246 *
247 * "Any transition from any value in {Clear, Render, Resolve} to a
248 * different value in {Clear, Render, Resolve} requires end of pipe
249 * synchronization."
250 *
251 * In other words, fast clear ops are not properly synchronized with
252 * other drawing. We need to use a PIPE_CONTROL to ensure that the
253 * contents of the previous draw hit the render target before we resolve
254 * and again afterwards to ensure that the resolve is complete before we
255 * do any more regular drawing.
256 */
257 iris_emit_end_of_pipe_sync(batch,
258 "fast clear: pre-flush",
259 PIPE_CONTROL_RENDER_TARGET_FLUSH |
260 PIPE_CONTROL_TILE_CACHE_FLUSH |
261 (devinfo->verx10 == 120 ?
262 PIPE_CONTROL_DEPTH_STALL : 0) |
263 (devinfo->verx10 == 125 ?
264 PIPE_CONTROL_FLUSH_HDC : 0) |
265 PIPE_CONTROL_PSS_STALL_SYNC);
266
267 iris_batch_sync_region_start(batch);
268
269 /* If we reach this point, we need to fast clear to change the state to
270 * ISL_AUX_STATE_CLEAR, or to update the fast clear color (or both).
271 */
272 enum blorp_batch_flags blorp_flags = 0;
273 blorp_flags |= color_changed ? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR;
274
275 struct blorp_batch blorp_batch;
276 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
277
278 struct blorp_surf surf;
279 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
280 p_res, res->aux.usage, level, true);
281
282 blorp_fast_clear(&blorp_batch, &surf, res->surf.format,
283 ISL_SWIZZLE_IDENTITY,
284 level, box->z, box->depth,
285 box->x, box->y, box->x + box->width,
286 box->y + box->height);
287 blorp_batch_finish(&blorp_batch);
288 iris_emit_end_of_pipe_sync(batch,
289 "fast clear: post flush",
290 PIPE_CONTROL_RENDER_TARGET_FLUSH |
291 (devinfo->verx10 == 120 ?
292 PIPE_CONTROL_TILE_CACHE_FLUSH |
293 PIPE_CONTROL_DEPTH_STALL : 0) |
294 PIPE_CONTROL_PSS_STALL_SYNC);
295 iris_batch_sync_region_end(batch);
296
297 iris_resource_set_aux_state(ice, res, level, box->z,
298 box->depth, ISL_AUX_STATE_CLEAR);
299 ice->state.dirty |= IRIS_DIRTY_RENDER_BUFFER;
300 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
301 return;
302 }
303
304 static void
clear_color(struct iris_context * ice,struct pipe_resource * p_res,unsigned level,const struct pipe_box * box,bool render_condition_enabled,enum isl_format format,struct isl_swizzle swizzle,union isl_color_value color)305 clear_color(struct iris_context *ice,
306 struct pipe_resource *p_res,
307 unsigned level,
308 const struct pipe_box *box,
309 bool render_condition_enabled,
310 enum isl_format format,
311 struct isl_swizzle swizzle,
312 union isl_color_value color)
313 {
314 struct iris_resource *res = (void *) p_res;
315
316 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
317 const struct intel_device_info *devinfo = &batch->screen->devinfo;
318 enum blorp_batch_flags blorp_flags = iris_blorp_flags_for_batch(batch);
319
320 if (render_condition_enabled) {
321 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
322 return;
323
324 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
325 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
326 }
327
328 if (p_res->target == PIPE_BUFFER)
329 util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
330
331 iris_batch_maybe_flush(batch, 1500);
332
333 bool can_fast_clear = can_fast_clear_color(ice, p_res, level, box,
334 render_condition_enabled,
335 format, color);
336 if (can_fast_clear) {
337 fast_clear_color(ice, res, level, box, color);
338 return;
339 }
340
341 enum isl_aux_usage aux_usage =
342 iris_resource_render_aux_usage(ice, res, level, format, false);
343
344 iris_resource_prepare_render(ice, res, level, box->z, box->depth,
345 aux_usage);
346 iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_RENDER_WRITE);
347
348 struct blorp_surf surf;
349 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &surf,
350 p_res, aux_usage, level, true);
351
352 iris_batch_sync_region_start(batch);
353
354 struct blorp_batch blorp_batch;
355 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
356
357 if (!isl_format_supports_rendering(devinfo, format) &&
358 isl_format_is_rgbx(format))
359 format = isl_format_rgbx_to_rgba(format);
360
361 blorp_clear(&blorp_batch, &surf, format, swizzle,
362 level, box->z, box->depth, box->x, box->y,
363 box->x + box->width, box->y + box->height,
364 color, 0 /* color_write_disable */);
365
366 blorp_batch_finish(&blorp_batch);
367 iris_batch_sync_region_end(batch);
368
369 iris_flush_and_dirty_for_history(ice, batch, res,
370 PIPE_CONTROL_RENDER_TARGET_FLUSH,
371 "cache history: post color clear");
372
373 iris_resource_finish_render(ice, res, level,
374 box->z, box->depth, aux_usage);
375 }
376
377 static bool
can_fast_clear_depth(struct iris_context * ice,struct iris_resource * res,unsigned level,const struct pipe_box * box,bool render_condition_enabled,float depth)378 can_fast_clear_depth(struct iris_context *ice,
379 struct iris_resource *res,
380 unsigned level,
381 const struct pipe_box *box,
382 bool render_condition_enabled,
383 float depth)
384 {
385 struct pipe_resource *p_res = (void *) res;
386 struct pipe_context *ctx = (void *) ice;
387 struct iris_screen *screen = (void *) ctx->screen;
388 const struct intel_device_info *devinfo = &screen->devinfo;
389
390 if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
391 return false;
392
393 /* Check for partial clears */
394 if (box->x > 0 || box->y > 0 ||
395 box->width < u_minify(p_res->width0, level) ||
396 box->height < u_minify(p_res->height0, level)) {
397 return false;
398 }
399
400 /* Avoid conditional fast clears to maintain correct tracking of the aux
401 * state (see iris_resource_finish_write for more info). Note that partial
402 * fast clears would not pose a problem with conditional rendering.
403 */
404 if (render_condition_enabled &&
405 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
406 return false;
407 }
408
409 if (!iris_resource_level_has_hiz(res, level))
410 return false;
411
412 if (!blorp_can_hiz_clear_depth(devinfo, &res->surf, res->aux.usage,
413 level, box->z, box->x, box->y,
414 box->x + box->width,
415 box->y + box->height)) {
416 return false;
417 }
418
419 return true;
420 }
421
422 static void
fast_clear_depth(struct iris_context * ice,struct iris_resource * res,unsigned level,const struct pipe_box * box,float depth)423 fast_clear_depth(struct iris_context *ice,
424 struct iris_resource *res,
425 unsigned level,
426 const struct pipe_box *box,
427 float depth)
428 {
429 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
430
431 bool update_clear_depth = false;
432
433 /* If we're clearing to a new clear value, then we need to resolve any clear
434 * flags out of the HiZ buffer into the real depth buffer.
435 */
436 if (res->aux.clear_color_unknown || res->aux.clear_color.f32[0] != depth) {
437 for (unsigned res_level = 0; res_level < res->surf.levels; res_level++) {
438 const unsigned level_layers =
439 iris_get_num_logical_layers(res, res_level);
440 for (unsigned layer = 0; layer < level_layers; layer++) {
441 if (res_level == level &&
442 layer >= box->z &&
443 layer < box->z + box->depth) {
444 /* We're going to clear this layer anyway. Leave it alone. */
445 continue;
446 }
447
448 enum isl_aux_state aux_state =
449 iris_resource_get_aux_state(res, res_level, layer);
450
451 if (aux_state != ISL_AUX_STATE_CLEAR &&
452 aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
453 /* This slice doesn't have any fast-cleared bits. */
454 continue;
455 }
456
457 /* If we got here, then the level may have fast-clear bits that
458 * use the old clear value. We need to do a depth resolve to get
459 * rid of their use of the clear value before we can change it.
460 * Fortunately, few applications ever change their depth clear
461 * value so this shouldn't happen often.
462 */
463 iris_hiz_exec(ice, batch, res, res_level, layer, 1,
464 ISL_AUX_OP_FULL_RESOLVE, false);
465 iris_resource_set_aux_state(ice, res, res_level, layer, 1,
466 ISL_AUX_STATE_RESOLVED);
467 }
468 }
469 const union isl_color_value clear_value = { .f32 = {depth, } };
470 iris_resource_set_clear_color(ice, res, clear_value);
471 update_clear_depth = true;
472 }
473
474 if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
475 /* From Bspec 47010 (Depth Buffer Clear):
476 *
477 * Since the fast clear cycles to CCS are not cached in TileCache,
478 * any previous depth buffer writes to overlapping pixels must be
479 * flushed out of TileCache before a succeeding Depth Buffer Clear.
480 * This restriction only applies to Depth Buffer with write-thru
481 * enabled, since fast clears to CCS only occur for write-thru mode.
482 *
483 * There may have been a write to this depth buffer. Flush it from the
484 * tile cache just in case.
485 */
486 iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear",
487 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
488 PIPE_CONTROL_TILE_CACHE_FLUSH);
489 }
490
491 for (unsigned l = 0; l < box->depth; l++) {
492 enum isl_aux_state aux_state =
493 iris_resource_get_aux_state(res, level, box->z + l);
494 if (update_clear_depth || aux_state != ISL_AUX_STATE_CLEAR) {
495 if (aux_state == ISL_AUX_STATE_CLEAR) {
496 perf_debug(&ice->dbg, "Performing HiZ clear just to update the "
497 "depth clear value\n");
498 }
499 iris_hiz_exec(ice, batch, res, level,
500 box->z + l, 1, ISL_AUX_OP_FAST_CLEAR,
501 update_clear_depth);
502 }
503 }
504
505 iris_resource_set_aux_state(ice, res, level, box->z, box->depth,
506 ISL_AUX_STATE_CLEAR);
507 ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER;
508 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_BINDINGS;
509 }
510
511 static void
clear_depth_stencil(struct iris_context * ice,struct pipe_resource * p_res,unsigned level,const struct pipe_box * box,bool render_condition_enabled,bool clear_depth,bool clear_stencil,float depth,uint8_t stencil)512 clear_depth_stencil(struct iris_context *ice,
513 struct pipe_resource *p_res,
514 unsigned level,
515 const struct pipe_box *box,
516 bool render_condition_enabled,
517 bool clear_depth,
518 bool clear_stencil,
519 float depth,
520 uint8_t stencil)
521 {
522 struct iris_resource *res = (void *) p_res;
523
524 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
525 enum blorp_batch_flags blorp_flags = 0;
526
527 if (render_condition_enabled) {
528 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
529 return;
530
531 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT)
532 blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE;
533 }
534
535 iris_batch_maybe_flush(batch, 1500);
536
537 struct iris_resource *z_res;
538 struct iris_resource *stencil_res;
539 struct blorp_surf z_surf;
540 struct blorp_surf stencil_surf;
541
542 iris_get_depth_stencil_resources(p_res, &z_res, &stencil_res);
543 if (z_res && clear_depth &&
544 can_fast_clear_depth(ice, z_res, level, box, render_condition_enabled,
545 depth)) {
546 fast_clear_depth(ice, z_res, level, box, depth);
547 iris_flush_and_dirty_for_history(ice, batch, res, 0,
548 "cache history: post fast Z clear");
549 clear_depth = false;
550 z_res = false;
551 }
552
553 /* At this point, we might have fast cleared the depth buffer. So if there's
554 * no stencil clear pending, return early.
555 */
556 if (!(clear_depth || (clear_stencil && stencil_res))) {
557 return;
558 }
559
560 if (clear_depth && z_res) {
561 const enum isl_aux_usage aux_usage =
562 iris_resource_render_aux_usage(ice, z_res, level, z_res->surf.format,
563 false);
564 iris_resource_prepare_render(ice, z_res, level, box->z, box->depth,
565 aux_usage);
566 iris_emit_buffer_barrier_for(batch, z_res->bo, IRIS_DOMAIN_DEPTH_WRITE);
567 iris_blorp_surf_for_resource(&batch->screen->isl_dev, &z_surf,
568 &z_res->base.b, aux_usage, level, true);
569 }
570
571 uint8_t stencil_mask = clear_stencil && stencil_res ? 0xff : 0;
572 if (stencil_mask) {
573 iris_resource_prepare_access(ice, stencil_res, level, 1, box->z,
574 box->depth, stencil_res->aux.usage, false);
575 iris_emit_buffer_barrier_for(batch, stencil_res->bo,
576 IRIS_DOMAIN_DEPTH_WRITE);
577 iris_blorp_surf_for_resource(&batch->screen->isl_dev,
578 &stencil_surf, &stencil_res->base.b,
579 stencil_res->aux.usage, level, true);
580 }
581
582 iris_batch_sync_region_start(batch);
583
584 struct blorp_batch blorp_batch;
585 blorp_batch_init(&ice->blorp, &blorp_batch, batch, blorp_flags);
586
587 blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
588 level, box->z, box->depth,
589 box->x, box->y,
590 box->x + box->width,
591 box->y + box->height,
592 clear_depth && z_res, depth,
593 stencil_mask, stencil);
594
595 blorp_batch_finish(&blorp_batch);
596 iris_batch_sync_region_end(batch);
597
598 iris_flush_and_dirty_for_history(ice, batch, res, 0,
599 "cache history: post slow ZS clear");
600
601 if (clear_depth && z_res) {
602 iris_resource_finish_render(ice, z_res, level, box->z, box->depth,
603 z_surf.aux_usage);
604 }
605
606 if (stencil_mask) {
607 iris_resource_finish_write(ice, stencil_res, level, box->z, box->depth,
608 stencil_res->aux.usage);
609 }
610 }
611
612 /**
613 * The pipe->clear() driver hook.
614 *
615 * This clears buffers attached to the current draw framebuffer.
616 */
617 static void
iris_clear(struct pipe_context * ctx,unsigned buffers,const struct pipe_scissor_state * scissor_state,const union pipe_color_union * p_color,double depth,unsigned stencil)618 iris_clear(struct pipe_context *ctx,
619 unsigned buffers,
620 const struct pipe_scissor_state *scissor_state,
621 const union pipe_color_union *p_color,
622 double depth,
623 unsigned stencil)
624 {
625 struct iris_context *ice = (void *) ctx;
626 struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
627
628 assert(buffers != 0);
629
630 struct pipe_box box = {
631 .width = cso_fb->width,
632 .height = cso_fb->height,
633 };
634
635 if (scissor_state) {
636 box.x = scissor_state->minx;
637 box.y = scissor_state->miny;
638 box.width = MIN2(box.width, scissor_state->maxx - scissor_state->minx);
639 box.height = MIN2(box.height, scissor_state->maxy - scissor_state->miny);
640 }
641
642 if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
643 struct pipe_surface *psurf = cso_fb->zsbuf;
644
645 box.depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1;
646 box.z = psurf->u.tex.first_layer,
647 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box, true,
648 buffers & PIPE_CLEAR_DEPTH,
649 buffers & PIPE_CLEAR_STENCIL,
650 depth, stencil);
651 }
652
653 if (buffers & PIPE_CLEAR_COLOR) {
654 for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
655 if (buffers & (PIPE_CLEAR_COLOR0 << i)) {
656 struct pipe_surface *psurf = cso_fb->cbufs[i];
657 struct iris_surface *isurf = (void *) psurf;
658 box.depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1,
659 box.z = psurf->u.tex.first_layer,
660
661 clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
662 true, isurf->view.format, isurf->view.swizzle,
663 convert_clear_color(psurf->format, p_color));
664 }
665 }
666 }
667 }
668
669 /**
670 * The pipe->clear_texture() driver hook.
671 *
672 * This clears the given texture resource.
673 */
674 static void
iris_clear_texture(struct pipe_context * ctx,struct pipe_resource * p_res,unsigned level,const struct pipe_box * box,const void * data)675 iris_clear_texture(struct pipe_context *ctx,
676 struct pipe_resource *p_res,
677 unsigned level,
678 const struct pipe_box *box,
679 const void *data)
680 {
681 struct iris_context *ice = (void *) ctx;
682 struct iris_screen *screen = (void *) ctx->screen;
683 const struct intel_device_info *devinfo = &screen->devinfo;
684
685 if (util_format_is_depth_or_stencil(p_res->format)) {
686 const struct util_format_unpack_description *unpack =
687 util_format_unpack_description(p_res->format);
688
689 float depth = 0.0;
690 uint8_t stencil = 0;
691
692 if (unpack->unpack_z_float)
693 util_format_unpack_z_float(p_res->format, &depth, data, 1);
694
695 if (unpack->unpack_s_8uint)
696 util_format_unpack_s_8uint(p_res->format, &stencil, data, 1);
697
698 clear_depth_stencil(ice, p_res, level, box, true, true, true,
699 depth, stencil);
700 } else {
701 union isl_color_value color;
702 struct iris_resource *res = (void *) p_res;
703 enum isl_format format = res->surf.format;
704
705 if (!isl_format_supports_rendering(devinfo, format)) {
706 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
707 // XXX: actually just get_copy_format_for_bpb from BLORP
708 // XXX: don't cut and paste this
709 switch (fmtl->bpb) {
710 case 8: format = ISL_FORMAT_R8_UINT; break;
711 case 16: format = ISL_FORMAT_R8G8_UINT; break;
712 case 24: format = ISL_FORMAT_R8G8B8_UINT; break;
713 case 32: format = ISL_FORMAT_R8G8B8A8_UINT; break;
714 case 48: format = ISL_FORMAT_R16G16B16_UINT; break;
715 case 64: format = ISL_FORMAT_R16G16B16A16_UINT; break;
716 case 96: format = ISL_FORMAT_R32G32B32_UINT; break;
717 case 128: format = ISL_FORMAT_R32G32B32A32_UINT; break;
718 default:
719 unreachable("Unknown format bpb");
720 }
721
722 /* No aux surfaces for non-renderable surfaces */
723 assert(res->aux.usage == ISL_AUX_USAGE_NONE);
724 }
725
726 isl_color_value_unpack(&color, format, data);
727
728 clear_color(ice, p_res, level, box, true, format,
729 ISL_SWIZZLE_IDENTITY, color);
730 }
731 }
732
733 /**
734 * The pipe->clear_render_target() driver hook.
735 *
736 * This clears the given render target surface.
737 */
738 static void
iris_clear_render_target(struct pipe_context * ctx,struct pipe_surface * psurf,const union pipe_color_union * p_color,unsigned dst_x,unsigned dst_y,unsigned width,unsigned height,bool render_condition_enabled)739 iris_clear_render_target(struct pipe_context *ctx,
740 struct pipe_surface *psurf,
741 const union pipe_color_union *p_color,
742 unsigned dst_x, unsigned dst_y,
743 unsigned width, unsigned height,
744 bool render_condition_enabled)
745 {
746 struct iris_context *ice = (void *) ctx;
747 struct iris_surface *isurf = (void *) psurf;
748 struct pipe_box box = {
749 .x = dst_x,
750 .y = dst_y,
751 .z = psurf->u.tex.first_layer,
752 .width = width,
753 .height = height,
754 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
755 };
756
757 clear_color(ice, psurf->texture, psurf->u.tex.level, &box,
758 render_condition_enabled,
759 isurf->view.format, isurf->view.swizzle,
760 convert_clear_color(psurf->format, p_color));
761 }
762
763 /**
764 * The pipe->clear_depth_stencil() driver hook.
765 *
766 * This clears the given depth/stencil surface.
767 */
768 static void
iris_clear_depth_stencil(struct pipe_context * ctx,struct pipe_surface * psurf,unsigned flags,double depth,unsigned stencil,unsigned dst_x,unsigned dst_y,unsigned width,unsigned height,bool render_condition_enabled)769 iris_clear_depth_stencil(struct pipe_context *ctx,
770 struct pipe_surface *psurf,
771 unsigned flags,
772 double depth,
773 unsigned stencil,
774 unsigned dst_x, unsigned dst_y,
775 unsigned width, unsigned height,
776 bool render_condition_enabled)
777 {
778 struct iris_context *ice = (void *) ctx;
779 struct pipe_box box = {
780 .x = dst_x,
781 .y = dst_y,
782 .z = psurf->u.tex.first_layer,
783 .width = width,
784 .height = height,
785 .depth = psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1
786 };
787
788 assert(util_format_is_depth_or_stencil(psurf->texture->format));
789
790 clear_depth_stencil(ice, psurf->texture, psurf->u.tex.level, &box,
791 render_condition_enabled,
792 flags & PIPE_CLEAR_DEPTH, flags & PIPE_CLEAR_STENCIL,
793 depth, stencil);
794 }
795
796 void
iris_init_clear_functions(struct pipe_context * ctx)797 iris_init_clear_functions(struct pipe_context *ctx)
798 {
799 ctx->clear = iris_clear;
800 ctx->clear_texture = iris_clear_texture;
801 ctx->clear_render_target = iris_clear_render_target;
802 ctx->clear_depth_stencil = iris_clear_depth_stencil;
803 }
804