1 /*
2 * Copyright 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef IRIS_RESOURCE_H
24 #define IRIS_RESOURCE_H
25
26 #include "pipe/p_state.h"
27 #include "util/u_inlines.h"
28 #include "util/u_range.h"
29 #include "util/u_threaded_context.h"
30 #include "intel/isl/isl.h"
31 #include "iris_bufmgr.h"
32
33 struct iris_batch;
34 struct iris_context;
35 struct shader_info;
36
37 #define IRIS_MAX_MIPLEVELS 15
38
39 struct iris_format_info {
40 enum isl_format fmt;
41 struct isl_swizzle swizzle;
42 };
43
44 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
45 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
46 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
47 #define IRIS_RESOURCE_FLAG_BINDLESS_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
48 #define IRIS_RESOURCE_FLAG_DEVICE_MEM (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
49
50 /**
51 * Resources represent a GPU buffer object or image (mipmap tree).
52 *
53 * They contain the storage (BO) and layout information (ISL surface).
54 */
55 struct iris_resource {
56 struct threaded_resource base;
57 enum pipe_format internal_format;
58
59 /**
60 * The ISL surface layout information for this resource.
61 *
62 * This is not filled out for PIPE_BUFFER resources, but is guaranteed
63 * to be zeroed. Note that this also guarantees that res->surf.tiling
64 * will be ISL_TILING_LINEAR, so it's safe to check that.
65 */
66 struct isl_surf surf;
67
68 /** Backing storage for the resource */
69 struct iris_bo *bo;
70
71 /** offset at which data starts in the BO */
72 uint64_t offset;
73
74 /**
75 * A bitfield of PIPE_BIND_* indicating how this resource was bound
76 * in the past. Only meaningful for PIPE_BUFFER; used for flushing.
77 */
78 unsigned bind_history;
79
80 /**
81 * A bitfield of MESA_SHADER_* stages indicating where this resource
82 * was bound.
83 */
84 unsigned bind_stages;
85
86 /**
87 * For PIPE_BUFFER resources, a range which may contain valid data.
88 *
89 * This is a conservative estimate of what part of the buffer contains
90 * valid data that we have to preserve. The rest of the buffer is
91 * considered invalid, and we can promote writes to that region to
92 * be unsynchronized writes, avoiding blit copies.
93 */
94 struct util_range valid_buffer_range;
95
96 /**
97 * Auxiliary buffer information (CCS, MCS, or HiZ).
98 */
99 struct {
100 /** The surface layout for the auxiliary buffer. */
101 struct isl_surf surf;
102
103 /** The buffer object containing the auxiliary data. */
104 struct iris_bo *bo;
105
106 /** Offset into 'bo' where the auxiliary surface starts. */
107 uint32_t offset;
108
109 struct {
110 struct isl_surf surf;
111
112 /** Offset into 'bo' where the auxiliary surface starts. */
113 uint32_t offset;
114 } extra_aux;
115
116 /**
117 * When importing resources with a clear color, we may not know the
118 * clear color on the CPU at first.
119 */
120 bool clear_color_unknown;
121
122 /**
123 * Fast clear color for this surface. For depth surfaces, the clear
124 * value is stored as a float32 in the red component.
125 *
126 * Do not rely on this value if clear_color_unknown is set.
127 */
128 union isl_color_value clear_color;
129
130 /** Buffer object containing the indirect clear color. */
131 struct iris_bo *clear_color_bo;
132
133 /** Offset into bo where the clear color can be found. */
134 uint64_t clear_color_offset;
135
136 /**
137 * \brief The type of auxiliary compression used by this resource.
138 *
139 * This describes the type of auxiliary compression that is intended to
140 * be used by this resource. An aux usage of ISL_AUX_USAGE_NONE means
141 * that auxiliary compression is permanently disabled. An aux usage
142 * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
143 * compression will always be enabled for this surface.
144 */
145 enum isl_aux_usage usage;
146
147 /**
148 * \brief Maps miptree slices to their current aux state.
149 *
150 * This two-dimensional array is indexed as [level][layer] and stores an
151 * aux state for each slice.
152 */
153 enum isl_aux_state **state;
154 } aux;
155
156 /**
157 * For external surfaces, this is format that was used to create or import
158 * the surface. For internal surfaces, this will always be
159 * PIPE_FORMAT_NONE.
160 */
161 enum pipe_format external_format;
162
163 /**
164 * For external surfaces, this is DRM format modifier that was used to
165 * create or import the surface. For internal surfaces, this will always
166 * be DRM_FORMAT_MOD_INVALID.
167 */
168 const struct isl_drm_modifier_info *mod_info;
169
170 /**
171 * The screen the resource was originally created with, stored for refcounting.
172 */
173 struct pipe_screen *orig_screen;
174 };
175
176 /**
177 * A simple <resource, offset> tuple for storing a reference to a
178 * piece of state stored in a GPU buffer object.
179 */
180 struct iris_state_ref {
181 struct pipe_resource *res;
182 uint32_t offset;
183 };
184
185 /**
186 * The SURFACE_STATE descriptors for a resource.
187 */
188 struct iris_surface_state {
189 /**
190 * CPU-side copy of the packed SURFACE_STATE structures, already
191 * aligned so they can be uploaded as a contiguous pile of bytes.
192 *
193 * This can be updated and re-uploaded if (e.g.) addresses need to change.
194 */
195 uint32_t *cpu;
196
197 /**
198 * A bitfield of ISL_AUX_USAGE_* modes that are present in the surface
199 * states.
200 */
201 unsigned aux_usages;
202
203 /**
204 * How many states are there? (Each aux mode has its own state.)
205 */
206 unsigned num_states;
207
208 /**
209 * Address of the resource (res->bo->address). Note that "Surface
210 * Base Address" may be offset from this value.
211 */
212 uint64_t bo_address;
213
214 /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */
215 struct iris_state_ref ref;
216 };
217
218 /**
219 * Gallium CSO for sampler views (texture views).
220 *
221 * In addition to the normal pipe_resource, this adds an ISL view
222 * which may reinterpret the format or restrict levels/layers.
223 *
224 * These can also be linear texture buffers.
225 */
226 struct iris_sampler_view {
227 struct pipe_sampler_view base;
228 struct isl_view view;
229
230 union isl_color_value clear_color;
231
232 /* A short-cut (not a reference) to the actual resource being viewed.
233 * Multi-planar (or depth+stencil) images may have multiple resources
234 * chained together; this skips having to traverse base->texture->*.
235 */
236 struct iris_resource *res;
237
238 /** The resource (BO) holding our SURFACE_STATE. */
239 struct iris_surface_state surface_state;
240 };
241
242 /**
243 * Image view representation.
244 */
245 struct iris_image_view {
246 struct pipe_image_view base;
247
248 /** The resource (BO) holding our SURFACE_STATE. */
249 struct iris_surface_state surface_state;
250 };
251
252 /**
253 * Gallium CSO for surfaces (framebuffer attachments).
254 *
255 * A view of a surface that can be bound to a color render target or
256 * depth/stencil attachment.
257 */
258 struct iris_surface {
259 struct pipe_surface base;
260 struct isl_view view;
261 struct isl_view read_view;
262 union isl_color_value clear_color;
263
264 /** The resource (BO) holding our SURFACE_STATE. */
265 struct iris_surface_state surface_state;
266 /** The resource (BO) holding our SURFACE_STATE for read. */
267 struct iris_surface_state surface_state_read;
268 };
269
270 /**
271 * Transfer object - information about a buffer mapping.
272 */
273 struct iris_transfer {
274 struct threaded_transfer base;
275 struct pipe_debug_callback *dbg;
276 void *buffer;
277 void *ptr;
278
279 /** A linear staging resource for GPU-based copy_region transfers. */
280 struct pipe_resource *staging;
281 struct blorp_context *blorp;
282 struct iris_batch *batch;
283
284 bool dest_had_defined_contents;
285
286 void (*unmap)(struct iris_transfer *);
287 };
288
289 /**
290 * Memory Object
291 */
292 struct iris_memory_object {
293 struct pipe_memory_object b;
294 struct iris_bo *bo;
295 uint64_t format;
296 unsigned stride;
297 };
298
299 /**
300 * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
301 */
302 static inline struct iris_bo *
iris_resource_bo(struct pipe_resource * p_res)303 iris_resource_bo(struct pipe_resource *p_res)
304 {
305 struct iris_resource *res = (void *) p_res;
306 return res->bo;
307 }
308
309 static inline uint32_t
iris_mocs(const struct iris_bo * bo,const struct isl_device * dev,isl_surf_usage_flags_t usage)310 iris_mocs(const struct iris_bo *bo,
311 const struct isl_device *dev,
312 isl_surf_usage_flags_t usage)
313 {
314 return isl_mocs(dev, usage, bo && iris_bo_is_external(bo));
315 }
316
317 struct iris_format_info iris_format_for_usage(const struct intel_device_info *,
318 enum pipe_format pf,
319 isl_surf_usage_flags_t usage);
320
321 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
322
323 void iris_get_depth_stencil_resources(struct pipe_resource *res,
324 struct iris_resource **out_z,
325 struct iris_resource **out_s);
326 bool iris_resource_set_clear_color(struct iris_context *ice,
327 struct iris_resource *res,
328 union isl_color_value color);
329
330 void iris_replace_buffer_storage(struct pipe_context *ctx,
331 struct pipe_resource *dst,
332 struct pipe_resource *src,
333 unsigned num_rebinds,
334 uint32_t rebind_mask,
335 uint32_t delete_buffer_id);
336
337
338 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
339
340 void iris_dirty_for_history(struct iris_context *ice,
341 struct iris_resource *res);
342 uint32_t iris_flush_bits_for_history(struct iris_context *ice,
343 struct iris_resource *res);
344
345 void iris_flush_and_dirty_for_history(struct iris_context *ice,
346 struct iris_batch *batch,
347 struct iris_resource *res,
348 uint32_t extra_flags,
349 const char *reason);
350
351 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
352 unsigned level);
353
354 void iris_resource_disable_aux(struct iris_resource *res);
355
356 #define INTEL_REMAINING_LAYERS UINT32_MAX
357 #define INTEL_REMAINING_LEVELS UINT32_MAX
358
359 void
360 iris_hiz_exec(struct iris_context *ice,
361 struct iris_batch *batch,
362 struct iris_resource *res,
363 unsigned int level, unsigned int start_layer,
364 unsigned int num_layers, enum isl_aux_op op,
365 bool update_clear_depth);
366
367 /**
368 * Prepare a miptree for access
369 *
370 * This function should be called prior to any access to miptree in order to
371 * perform any needed resolves.
372 *
373 * \param[in] start_level The first mip level to be accessed
374 *
375 * \param[in] num_levels The number of miplevels to be accessed or
376 * INTEL_REMAINING_LEVELS to indicate every level
377 * above start_level will be accessed
378 *
379 * \param[in] start_layer The first array slice or 3D layer to be accessed
380 *
381 * \param[in] num_layers The number of array slices or 3D layers be
382 * accessed or INTEL_REMAINING_LAYERS to indicate
383 * every layer above start_layer will be accessed
384 *
385 * \param[in] aux_supported Whether or not the access will support the
386 * miptree's auxiliary compression format; this
387 * must be false for uncompressed miptrees
388 *
389 * \param[in] fast_clear_supported Whether or not the access will support
390 * fast clears in the miptree's auxiliary
391 * compression format
392 */
393 void
394 iris_resource_prepare_access(struct iris_context *ice,
395 struct iris_resource *res,
396 uint32_t start_level, uint32_t num_levels,
397 uint32_t start_layer, uint32_t num_layers,
398 enum isl_aux_usage aux_usage,
399 bool fast_clear_supported);
400
401 /**
402 * Complete a write operation
403 *
404 * This function should be called after any operation writes to a miptree.
405 * This will update the miptree's compression state so that future resolves
406 * happen correctly. Technically, this function can be called before the
407 * write occurs but the caller must ensure that they don't interlace
408 * iris_resource_prepare_access and iris_resource_finish_write calls to
409 * overlapping layer/level ranges.
410 *
411 * \param[in] level The mip level that was written
412 *
413 * \param[in] start_layer The first array slice or 3D layer written
414 *
415 * \param[in] num_layers The number of array slices or 3D layers
416 * written or INTEL_REMAINING_LAYERS to indicate
417 * every layer above start_layer was written
418 *
419 * \param[in] written_with_aux Whether or not the write was done with
420 * auxiliary compression enabled
421 */
422 void
423 iris_resource_finish_write(struct iris_context *ice,
424 struct iris_resource *res, uint32_t level,
425 uint32_t start_layer, uint32_t num_layers,
426 enum isl_aux_usage aux_usage);
427
428 /** Get the auxiliary compression state of a miptree slice */
429 enum isl_aux_state
430 iris_resource_get_aux_state(const struct iris_resource *res,
431 uint32_t level, uint32_t layer);
432
433 /**
434 * Set the auxiliary compression state of a miptree slice range
435 *
436 * This function directly sets the auxiliary compression state of a slice
437 * range of a miptree. It only modifies data structures and does not do any
438 * resolves. This should only be called by code which directly performs
439 * compression operations such as fast clears and resolves. Most code should
440 * use iris_resource_prepare_access or iris_resource_finish_write.
441 */
442 void
443 iris_resource_set_aux_state(struct iris_context *ice,
444 struct iris_resource *res, uint32_t level,
445 uint32_t start_layer, uint32_t num_layers,
446 enum isl_aux_state aux_state);
447
448 /**
449 * Prepare a miptree for raw access
450 *
451 * This helper prepares the miptree for access that knows nothing about any
452 * sort of compression whatsoever. This is useful when mapping the surface or
453 * using it with the blitter.
454 */
455 static inline void
iris_resource_access_raw(struct iris_context * ice,struct iris_resource * res,uint32_t level,uint32_t layer,uint32_t num_layers,bool write)456 iris_resource_access_raw(struct iris_context *ice,
457 struct iris_resource *res,
458 uint32_t level, uint32_t layer,
459 uint32_t num_layers,
460 bool write)
461 {
462 iris_resource_prepare_access(ice, res, level, 1, layer, num_layers,
463 ISL_AUX_USAGE_NONE, false);
464 if (write) {
465 iris_resource_finish_write(ice, res, level, layer, num_layers,
466 ISL_AUX_USAGE_NONE);
467 }
468 }
469
470 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
471 const struct iris_resource *res,
472 enum isl_format view_fmt);
473 void iris_resource_prepare_texture(struct iris_context *ice,
474 struct iris_resource *res,
475 enum isl_format view_format,
476 uint32_t start_level, uint32_t num_levels,
477 uint32_t start_layer, uint32_t num_layers);
478
479 enum isl_aux_usage iris_image_view_aux_usage(struct iris_context *ice,
480 const struct pipe_image_view *pview,
481 const struct shader_info *info);
482 enum isl_format iris_image_view_get_format(struct iris_context *ice,
483 const struct pipe_image_view *img);
484
485 bool iris_has_invalid_primary(const struct iris_resource *res,
486 unsigned start_level, unsigned num_levels,
487 unsigned start_layer, unsigned num_layers);
488
489 void iris_resource_check_level_layer(const struct iris_resource *res,
490 uint32_t level, uint32_t layer);
491
492 bool iris_resource_level_has_hiz(const struct iris_resource *res,
493 uint32_t level);
494
495 bool iris_sample_with_depth_aux(const struct intel_device_info *devinfo,
496 const struct iris_resource *res);
497
498 bool iris_can_sample_mcs_with_clear(const struct intel_device_info *devinfo,
499 const struct iris_resource *res);
500
501 bool iris_has_color_unresolved(const struct iris_resource *res,
502 unsigned start_level, unsigned num_levels,
503 unsigned start_layer, unsigned num_layers);
504
505 bool iris_render_formats_color_compatible(enum isl_format a,
506 enum isl_format b,
507 union isl_color_value color,
508 bool clear_color_unknown);
509 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
510 struct iris_resource *res,
511 uint32_t level,
512 enum isl_format render_fmt,
513 bool draw_aux_disabled);
514 void iris_resource_prepare_render(struct iris_context *ice,
515 struct iris_resource *res, uint32_t level,
516 uint32_t start_layer, uint32_t layer_count,
517 enum isl_aux_usage aux_usage);
518 void iris_resource_finish_render(struct iris_context *ice,
519 struct iris_resource *res, uint32_t level,
520 uint32_t start_layer, uint32_t layer_count,
521 enum isl_aux_usage aux_usage);
522 #endif
523