1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_bitcast.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
34 #include "pipe/p_shader_tokens.h"
35
36 #include "sb/sb_public.h"
37
38 #define NUM_OF_CYCLES 3
39 #define NUM_OF_COMPONENTS 4
40
alu_writes(struct r600_bytecode_alu * alu)41 static inline bool alu_writes(struct r600_bytecode_alu *alu)
42 {
43 return alu->dst.write || alu->is_op3;
44 }
45
r600_bytecode_get_num_operands(const struct r600_bytecode_alu * alu)46 static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu *alu)
47 {
48 return r600_isa_alu(alu->op)->src_count;
49 }
50
r600_bytecode_cf(void)51 static struct r600_bytecode_cf *r600_bytecode_cf(void)
52 {
53 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
54
55 if (!cf)
56 return NULL;
57 list_inithead(&cf->list);
58 list_inithead(&cf->alu);
59 list_inithead(&cf->vtx);
60 list_inithead(&cf->tex);
61 list_inithead(&cf->gds);
62 return cf;
63 }
64
r600_bytecode_alu(void)65 static struct r600_bytecode_alu *r600_bytecode_alu(void)
66 {
67 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
68
69 if (!alu)
70 return NULL;
71 list_inithead(&alu->list);
72 return alu;
73 }
74
r600_bytecode_vtx(void)75 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
76 {
77 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
78
79 if (!vtx)
80 return NULL;
81 list_inithead(&vtx->list);
82 return vtx;
83 }
84
r600_bytecode_tex(void)85 static struct r600_bytecode_tex *r600_bytecode_tex(void)
86 {
87 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
88
89 if (!tex)
90 return NULL;
91 list_inithead(&tex->list);
92 return tex;
93 }
94
r600_bytecode_gds(void)95 static struct r600_bytecode_gds *r600_bytecode_gds(void)
96 {
97 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
98
99 if (gds == NULL)
100 return NULL;
101 list_inithead(&gds->list);
102 return gds;
103 }
104
stack_entry_size(enum radeon_family chip)105 static unsigned stack_entry_size(enum radeon_family chip) {
106 /* Wavefront size:
107 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
108 * Aruba/Sumo/Sumo2/redwood/juniper
109 * 32: R630/R730/R710/Palm/Cedar
110 * 16: R610/Rs780
111 *
112 * Stack row size:
113 * Wavefront Size 16 32 48 64
114 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
115 * Columns per Row (R9xx+) 8 4 4 4 */
116
117 switch (chip) {
118 /* FIXME: are some chips missing here? */
119 /* wavefront size 16 */
120 case CHIP_RV610:
121 case CHIP_RS780:
122 case CHIP_RV620:
123 case CHIP_RS880:
124 /* wavefront size 32 */
125 case CHIP_RV630:
126 case CHIP_RV635:
127 case CHIP_RV730:
128 case CHIP_RV710:
129 case CHIP_PALM:
130 case CHIP_CEDAR:
131 return 8;
132
133 /* wavefront size 64 */
134 default:
135 return 4;
136 }
137 }
138
r600_bytecode_init(struct r600_bytecode * bc,enum chip_class chip_class,enum radeon_family family,bool has_compressed_msaa_texturing)139 void r600_bytecode_init(struct r600_bytecode *bc,
140 enum chip_class chip_class,
141 enum radeon_family family,
142 bool has_compressed_msaa_texturing)
143 {
144 static unsigned next_shader_id = 0;
145
146 bc->debug_id = ++next_shader_id;
147
148 if ((chip_class == R600) &&
149 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
150 bc->ar_handling = AR_HANDLE_RV6XX;
151 bc->r6xx_nop_after_rel_dst = 1;
152 } else {
153 bc->ar_handling = AR_HANDLE_NORMAL;
154 bc->r6xx_nop_after_rel_dst = 0;
155 }
156
157 list_inithead(&bc->cf);
158 bc->chip_class = chip_class;
159 bc->family = family;
160 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
161 bc->stack.entry_size = stack_entry_size(family);
162 }
163
r600_bytecode_add_cf(struct r600_bytecode * bc)164 int r600_bytecode_add_cf(struct r600_bytecode *bc)
165 {
166 struct r600_bytecode_cf *cf = r600_bytecode_cf();
167
168 if (!cf)
169 return -ENOMEM;
170 list_addtail(&cf->list, &bc->cf);
171 if (bc->cf_last) {
172 cf->id = bc->cf_last->id + 2;
173 if (bc->cf_last->eg_alu_extended) {
174 /* take into account extended alu size */
175 cf->id += 2;
176 bc->ndw += 2;
177 }
178 }
179 bc->cf_last = cf;
180 bc->ncf++;
181 bc->ndw += 2;
182 bc->force_add_cf = 0;
183 bc->ar_loaded = 0;
184 return 0;
185 }
186
r600_bytecode_add_output(struct r600_bytecode * bc,const struct r600_bytecode_output * output)187 int r600_bytecode_add_output(struct r600_bytecode *bc,
188 const struct r600_bytecode_output *output)
189 {
190 int r;
191
192 if (output->gpr >= bc->ngpr)
193 bc->ngpr = output->gpr + 1;
194
195 if (bc->cf_last && (bc->cf_last->op == output->op ||
196 (bc->cf_last->op == CF_OP_EXPORT &&
197 output->op == CF_OP_EXPORT_DONE)) &&
198 output->type == bc->cf_last->output.type &&
199 output->elem_size == bc->cf_last->output.elem_size &&
200 output->swizzle_x == bc->cf_last->output.swizzle_x &&
201 output->swizzle_y == bc->cf_last->output.swizzle_y &&
202 output->swizzle_z == bc->cf_last->output.swizzle_z &&
203 output->swizzle_w == bc->cf_last->output.swizzle_w &&
204 output->comp_mask == bc->cf_last->output.comp_mask &&
205 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
206
207 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
208 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
209
210 bc->cf_last->op = bc->cf_last->output.op = output->op;
211 bc->cf_last->output.gpr = output->gpr;
212 bc->cf_last->output.array_base = output->array_base;
213 bc->cf_last->output.burst_count += output->burst_count;
214 return 0;
215
216 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
217 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
218
219 bc->cf_last->op = bc->cf_last->output.op = output->op;
220 bc->cf_last->output.burst_count += output->burst_count;
221 return 0;
222 }
223 }
224
225 r = r600_bytecode_add_cf(bc);
226 if (r)
227 return r;
228 bc->cf_last->op = output->op;
229 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
230 bc->cf_last->barrier = 1;
231 return 0;
232 }
233
r600_bytecode_add_pending_output(struct r600_bytecode * bc,const struct r600_bytecode_output * output)234 int r600_bytecode_add_pending_output(struct r600_bytecode *bc,
235 const struct r600_bytecode_output *output)
236 {
237 assert(bc->n_pending_outputs + 1 < ARRAY_SIZE(bc->pending_outputs));
238 bc->pending_outputs[bc->n_pending_outputs++] = *output;
239
240 return 0;
241 }
242
243 void
r600_bytecode_add_ack(struct r600_bytecode * bc)244 r600_bytecode_add_ack(struct r600_bytecode *bc)
245 {
246 bc->need_wait_ack = true;
247 }
248
249 int
r600_bytecode_wait_acks(struct r600_bytecode * bc)250 r600_bytecode_wait_acks(struct r600_bytecode *bc)
251 {
252 /* Store acks are an R700+ feature. */
253 if (bc->chip_class < R700)
254 return 0;
255
256 if (!bc->need_wait_ack)
257 return 0;
258
259 int ret = r600_bytecode_add_cfinst(bc, CF_OP_WAIT_ACK);
260 if (ret != 0)
261 return ret;
262
263 struct r600_bytecode_cf *cf = bc->cf_last;
264 cf->barrier = 1;
265 /* Request a wait if the number of outstanding acks is > 0 */
266 cf->cf_addr = 0;
267
268 return 0;
269 }
270
271 uint32_t
r600_bytecode_write_export_ack_type(struct r600_bytecode * bc,bool indirect)272 r600_bytecode_write_export_ack_type(struct r600_bytecode *bc, bool indirect)
273 {
274 if (bc->chip_class >= R700) {
275 if (indirect)
276 return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND_ACK_EG;
277 else
278 return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_ACK_EG;
279 } else {
280 if (indirect)
281 return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
282 else
283 return V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
284 }
285 }
286
287 /* alu instructions that can ony exits once per group */
is_alu_once_inst(struct r600_bytecode_alu * alu)288 static int is_alu_once_inst(struct r600_bytecode_alu *alu)
289 {
290 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) || alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
291 }
292
is_alu_reduction_inst(struct r600_bytecode * bc,struct r600_bytecode_alu * alu)293 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
294 {
295 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
296 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
297 }
298
is_alu_mova_inst(struct r600_bytecode_alu * alu)299 static int is_alu_mova_inst(struct r600_bytecode_alu *alu)
300 {
301 return r600_isa_alu(alu->op)->flags & AF_MOVA;
302 }
303
alu_uses_rel(struct r600_bytecode_alu * alu)304 static int alu_uses_rel(struct r600_bytecode_alu *alu)
305 {
306 unsigned num_src = r600_bytecode_get_num_operands(alu);
307 unsigned src;
308
309 if (alu->dst.rel) {
310 return 1;
311 }
312
313 for (src = 0; src < num_src; ++src) {
314 if (alu->src[src].rel) {
315 return 1;
316 }
317 }
318 return 0;
319 }
320
is_lds_read(int sel)321 static int is_lds_read(int sel)
322 {
323 return sel == EG_V_SQ_ALU_SRC_LDS_OQ_A_POP || sel == EG_V_SQ_ALU_SRC_LDS_OQ_B_POP;
324 }
325
alu_uses_lds(struct r600_bytecode_alu * alu)326 static int alu_uses_lds(struct r600_bytecode_alu *alu)
327 {
328 unsigned num_src = r600_bytecode_get_num_operands(alu);
329 unsigned src;
330
331 for (src = 0; src < num_src; ++src) {
332 if (is_lds_read(alu->src[src].sel)) {
333 return 1;
334 }
335 }
336 return 0;
337 }
338
is_alu_64bit_inst(struct r600_bytecode_alu * alu)339 static int is_alu_64bit_inst(struct r600_bytecode_alu *alu)
340 {
341 const struct alu_op_info *op = r600_isa_alu(alu->op);
342 return (op->flags & AF_64);
343 }
344
is_alu_vec_unit_inst(struct r600_bytecode * bc,struct r600_bytecode_alu * alu)345 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
346 {
347 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
348 return !(slots & AF_S);
349 }
350
is_alu_trans_unit_inst(struct r600_bytecode * bc,struct r600_bytecode_alu * alu)351 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
352 {
353 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
354 return !(slots & AF_V);
355 }
356
357 /* alu instructions that can execute on any unit */
is_alu_any_unit_inst(struct r600_bytecode * bc,struct r600_bytecode_alu * alu)358 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
359 {
360 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
361 return slots == AF_VS;
362 }
363
is_nop_inst(struct r600_bytecode_alu * alu)364 static int is_nop_inst(struct r600_bytecode_alu *alu)
365 {
366 return alu->op == ALU_OP0_NOP;
367 }
368
assign_alu_units(struct r600_bytecode * bc,struct r600_bytecode_alu * alu_first,struct r600_bytecode_alu * assignment[5])369 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
370 struct r600_bytecode_alu *assignment[5])
371 {
372 struct r600_bytecode_alu *alu;
373 unsigned i, chan, trans;
374 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
375
376 for (i = 0; i < max_slots; i++)
377 assignment[i] = NULL;
378
379 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
380 chan = alu->dst.chan;
381 if (max_slots == 4)
382 trans = 0;
383 else if (is_alu_trans_unit_inst(bc, alu))
384 trans = 1;
385 else if (is_alu_vec_unit_inst(bc, alu))
386 trans = 0;
387 else if (assignment[chan])
388 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
389 else
390 trans = 0;
391
392 if (trans) {
393 if (assignment[4]) {
394 assert(0); /* ALU.Trans has already been allocated. */
395 return -1;
396 }
397 assignment[4] = alu;
398 } else {
399 if (assignment[chan]) {
400 assert(0); /* ALU.chan has already been allocated. */
401 return -1;
402 }
403 assignment[chan] = alu;
404 }
405
406 if (alu->last)
407 break;
408 }
409 return 0;
410 }
411
412 struct alu_bank_swizzle {
413 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
414 int hw_cfile_addr[4];
415 int hw_cfile_elem[4];
416 };
417
418 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
419 [SQ_ALU_VEC_012] = { 0, 1, 2 },
420 [SQ_ALU_VEC_021] = { 0, 2, 1 },
421 [SQ_ALU_VEC_120] = { 1, 2, 0 },
422 [SQ_ALU_VEC_102] = { 1, 0, 2 },
423 [SQ_ALU_VEC_201] = { 2, 0, 1 },
424 [SQ_ALU_VEC_210] = { 2, 1, 0 }
425 };
426
427 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
428 [SQ_ALU_SCL_210] = { 2, 1, 0 },
429 [SQ_ALU_SCL_122] = { 1, 2, 2 },
430 [SQ_ALU_SCL_212] = { 2, 1, 2 },
431 [SQ_ALU_SCL_221] = { 2, 2, 1 }
432 };
433
init_bank_swizzle(struct alu_bank_swizzle * bs)434 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
435 {
436 int i, cycle, component;
437 /* set up gpr use */
438 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
439 for (component = 0; component < NUM_OF_COMPONENTS; component++)
440 bs->hw_gpr[cycle][component] = -1;
441 for (i = 0; i < 4; i++)
442 bs->hw_cfile_addr[i] = -1;
443 for (i = 0; i < 4; i++)
444 bs->hw_cfile_elem[i] = -1;
445 }
446
reserve_gpr(struct alu_bank_swizzle * bs,unsigned sel,unsigned chan,unsigned cycle)447 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
448 {
449 if (bs->hw_gpr[cycle][chan] == -1)
450 bs->hw_gpr[cycle][chan] = sel;
451 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
452 /* Another scalar operation has already used the GPR read port for the channel. */
453 return -1;
454 }
455 return 0;
456 }
457
reserve_cfile(const struct r600_bytecode * bc,struct alu_bank_swizzle * bs,unsigned sel,unsigned chan)458 static int reserve_cfile(const struct r600_bytecode *bc,
459 struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
460 {
461 int res, num_res = 4;
462 if (bc->chip_class >= R700) {
463 num_res = 2;
464 chan /= 2;
465 }
466 for (res = 0; res < num_res; ++res) {
467 if (bs->hw_cfile_addr[res] == -1) {
468 bs->hw_cfile_addr[res] = sel;
469 bs->hw_cfile_elem[res] = chan;
470 return 0;
471 } else if (bs->hw_cfile_addr[res] == sel &&
472 bs->hw_cfile_elem[res] == chan)
473 return 0; /* Read for this scalar element already reserved, nothing to do here. */
474 }
475 /* All cfile read ports are used, cannot reference vector element. */
476 return -1;
477 }
478
is_gpr(unsigned sel)479 static int is_gpr(unsigned sel)
480 {
481 return (sel <= 127);
482 }
483
484 /* CB constants start at 512, and get translated to a kcache index when ALU
485 * clauses are constructed. Note that we handle kcache constants the same way
486 * as (the now gone) cfile constants, is that really required? */
is_cfile(unsigned sel)487 static int is_cfile(unsigned sel)
488 {
489 return (sel > 255 && sel < 512) ||
490 (sel > 511 && sel < 4607) || /* Kcache before translation. */
491 (sel > 127 && sel < 192); /* Kcache after translation. */
492 }
493
is_const(int sel)494 static int is_const(int sel)
495 {
496 return is_cfile(sel) ||
497 (sel >= V_SQ_ALU_SRC_0 &&
498 sel <= V_SQ_ALU_SRC_LITERAL);
499 }
500
check_vector(const struct r600_bytecode * bc,const struct r600_bytecode_alu * alu,struct alu_bank_swizzle * bs,int bank_swizzle)501 static int check_vector(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
502 struct alu_bank_swizzle *bs, int bank_swizzle)
503 {
504 int r, src, num_src, sel, elem, cycle;
505
506 num_src = r600_bytecode_get_num_operands(alu);
507 for (src = 0; src < num_src; src++) {
508 sel = alu->src[src].sel;
509 elem = alu->src[src].chan;
510 if (is_gpr(sel)) {
511 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
512 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
513 /* Nothing to do; special-case optimization,
514 * second source uses first source’s reservation. */
515 continue;
516 else {
517 r = reserve_gpr(bs, sel, elem, cycle);
518 if (r)
519 return r;
520 }
521 } else if (is_cfile(sel)) {
522 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
523 if (r)
524 return r;
525 }
526 /* No restrictions on PV, PS, literal or special constants. */
527 }
528 return 0;
529 }
530
check_scalar(const struct r600_bytecode * bc,const struct r600_bytecode_alu * alu,struct alu_bank_swizzle * bs,int bank_swizzle)531 static int check_scalar(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
532 struct alu_bank_swizzle *bs, int bank_swizzle)
533 {
534 int r, src, num_src, const_count, sel, elem, cycle;
535
536 num_src = r600_bytecode_get_num_operands(alu);
537 for (const_count = 0, src = 0; src < num_src; ++src) {
538 sel = alu->src[src].sel;
539 elem = alu->src[src].chan;
540 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
541 if (const_count >= 2)
542 /* More than two references to a constant in
543 * transcendental operation. */
544 return -1;
545 else
546 const_count++;
547 }
548 if (is_cfile(sel)) {
549 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
550 if (r)
551 return r;
552 }
553 }
554 for (src = 0; src < num_src; ++src) {
555 sel = alu->src[src].sel;
556 elem = alu->src[src].chan;
557 if (is_gpr(sel)) {
558 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
559 if (cycle < const_count)
560 /* Cycle for GPR load conflicts with
561 * constant load in transcendental operation. */
562 return -1;
563 r = reserve_gpr(bs, sel, elem, cycle);
564 if (r)
565 return r;
566 }
567 /* PV PS restrictions */
568 if (const_count && (sel == 254 || sel == 255)) {
569 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
570 if (cycle < const_count)
571 return -1;
572 }
573 }
574 return 0;
575 }
576
check_and_set_bank_swizzle(const struct r600_bytecode * bc,struct r600_bytecode_alu * slots[5])577 static int check_and_set_bank_swizzle(const struct r600_bytecode *bc,
578 struct r600_bytecode_alu *slots[5])
579 {
580 struct alu_bank_swizzle bs;
581 int bank_swizzle[5];
582 int i, r = 0, forced = 1;
583 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
584 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
585
586 for (i = 0; i < max_slots; i++) {
587 if (slots[i]) {
588 if (slots[i]->bank_swizzle_force) {
589 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
590 } else {
591 forced = 0;
592 }
593 }
594
595 if (i < 4 && slots[i])
596 scalar_only = false;
597 }
598 if (forced)
599 return 0;
600
601 /* Just check every possible combination of bank swizzle.
602 * Not very efficent, but works on the first try in most of the cases. */
603 for (i = 0; i < 4; i++)
604 if (!slots[i] || !slots[i]->bank_swizzle_force)
605 bank_swizzle[i] = SQ_ALU_VEC_012;
606 else
607 bank_swizzle[i] = slots[i]->bank_swizzle;
608
609 bank_swizzle[4] = SQ_ALU_SCL_210;
610 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
611
612 init_bank_swizzle(&bs);
613 if (scalar_only == false) {
614 for (i = 0; i < 4; i++) {
615 if (slots[i]) {
616 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
617 if (r)
618 break;
619 }
620 }
621 } else
622 r = 0;
623
624 if (!r && max_slots == 5 && slots[4]) {
625 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
626 }
627 if (!r) {
628 for (i = 0; i < max_slots; i++) {
629 if (slots[i])
630 slots[i]->bank_swizzle = bank_swizzle[i];
631 }
632 return 0;
633 }
634
635 if (scalar_only) {
636 bank_swizzle[4]++;
637 } else {
638 for (i = 0; i < max_slots; i++) {
639 if (!slots[i] || !slots[i]->bank_swizzle_force) {
640 bank_swizzle[i]++;
641 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
642 break;
643 else if (i < max_slots - 1)
644 bank_swizzle[i] = SQ_ALU_VEC_012;
645 else
646 return -1;
647 }
648 }
649 }
650 }
651
652 /* Couldn't find a working swizzle. */
653 return -1;
654 }
655
replace_gpr_with_pv_ps(struct r600_bytecode * bc,struct r600_bytecode_alu * slots[5],struct r600_bytecode_alu * alu_prev)656 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
657 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
658 {
659 struct r600_bytecode_alu *prev[5];
660 int gpr[5], chan[5];
661 int i, j, r, src, num_src;
662 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
663
664 r = assign_alu_units(bc, alu_prev, prev);
665 if (r)
666 return r;
667
668 for (i = 0; i < max_slots; ++i) {
669 if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
670
671 if (is_alu_64bit_inst(prev[i])) {
672 gpr[i] = -1;
673 continue;
674 }
675
676 gpr[i] = prev[i]->dst.sel;
677 /* cube writes more than PV.X */
678 if (is_alu_reduction_inst(bc, prev[i]))
679 chan[i] = 0;
680 else
681 chan[i] = prev[i]->dst.chan;
682 } else
683 gpr[i] = -1;
684 }
685
686 for (i = 0; i < max_slots; ++i) {
687 struct r600_bytecode_alu *alu = slots[i];
688 if (!alu)
689 continue;
690
691 if (is_alu_64bit_inst(alu))
692 continue;
693 num_src = r600_bytecode_get_num_operands(alu);
694 for (src = 0; src < num_src; ++src) {
695 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
696 continue;
697
698 if (bc->chip_class < CAYMAN) {
699 if (alu->src[src].sel == gpr[4] &&
700 alu->src[src].chan == chan[4] &&
701 alu_prev->pred_sel == alu->pred_sel) {
702 alu->src[src].sel = V_SQ_ALU_SRC_PS;
703 alu->src[src].chan = 0;
704 continue;
705 }
706 }
707
708 for (j = 0; j < 4; ++j) {
709 if (alu->src[src].sel == gpr[j] &&
710 alu->src[src].chan == j &&
711 alu_prev->pred_sel == alu->pred_sel) {
712 alu->src[src].sel = V_SQ_ALU_SRC_PV;
713 alu->src[src].chan = chan[j];
714 break;
715 }
716 }
717 }
718 }
719
720 return 0;
721 }
722
r600_bytecode_special_constants(uint32_t value,unsigned * sel)723 void r600_bytecode_special_constants(uint32_t value, unsigned *sel)
724 {
725 switch(value) {
726 case 0:
727 *sel = V_SQ_ALU_SRC_0;
728 break;
729 case 1:
730 *sel = V_SQ_ALU_SRC_1_INT;
731 break;
732 case -1:
733 *sel = V_SQ_ALU_SRC_M_1_INT;
734 break;
735 case 0x3F800000: /* 1.0f */
736 *sel = V_SQ_ALU_SRC_1;
737 break;
738 case 0x3F000000: /* 0.5f */
739 *sel = V_SQ_ALU_SRC_0_5;
740 break;
741 default:
742 *sel = V_SQ_ALU_SRC_LITERAL;
743 break;
744 }
745 }
746
747 /* compute how many literal are needed */
r600_bytecode_alu_nliterals(struct r600_bytecode_alu * alu,uint32_t literal[4],unsigned * nliteral)748 static int r600_bytecode_alu_nliterals(struct r600_bytecode_alu *alu,
749 uint32_t literal[4], unsigned *nliteral)
750 {
751 unsigned num_src = r600_bytecode_get_num_operands(alu);
752 unsigned i, j;
753
754 for (i = 0; i < num_src; ++i) {
755 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
756 uint32_t value = alu->src[i].value;
757 unsigned found = 0;
758 for (j = 0; j < *nliteral; ++j) {
759 if (literal[j] == value) {
760 found = 1;
761 break;
762 }
763 }
764 if (!found) {
765 if (*nliteral >= 4)
766 return -EINVAL;
767 literal[(*nliteral)++] = value;
768 }
769 }
770 }
771 return 0;
772 }
773
r600_bytecode_alu_adjust_literals(struct r600_bytecode_alu * alu,uint32_t literal[4],unsigned nliteral)774 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode_alu *alu,
775 uint32_t literal[4], unsigned nliteral)
776 {
777 unsigned num_src = r600_bytecode_get_num_operands(alu);
778 unsigned i, j;
779
780 for (i = 0; i < num_src; ++i) {
781 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
782 uint32_t value = alu->src[i].value;
783 for (j = 0; j < nliteral; ++j) {
784 if (literal[j] == value) {
785 alu->src[i].chan = j;
786 break;
787 }
788 }
789 }
790 }
791 }
792
merge_inst_groups(struct r600_bytecode * bc,struct r600_bytecode_alu * slots[5],struct r600_bytecode_alu * alu_prev)793 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
794 struct r600_bytecode_alu *alu_prev)
795 {
796 struct r600_bytecode_alu *prev[5];
797 struct r600_bytecode_alu *result[5] = { NULL };
798
799 uint8_t interp_xz = 0;
800
801 uint32_t literal[4], prev_literal[4];
802 unsigned nliteral = 0, prev_nliteral = 0;
803
804 int i, j, r, src, num_src;
805 int num_once_inst = 0;
806 int have_mova = 0, have_rel = 0;
807 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
808
809 r = assign_alu_units(bc, alu_prev, prev);
810 if (r)
811 return r;
812
813 for (i = 0; i < max_slots; ++i) {
814 if (prev[i]) {
815 if (prev[i]->pred_sel)
816 return 0;
817 if (is_alu_once_inst(prev[i]))
818 return 0;
819
820 if (prev[i]->op == ALU_OP2_INTERP_X)
821 interp_xz |= 1;
822 if (prev[i]->op == ALU_OP2_INTERP_Z)
823 interp_xz |= 2;
824 }
825 if (slots[i]) {
826 if (slots[i]->pred_sel)
827 return 0;
828 if (is_alu_once_inst(slots[i]))
829 return 0;
830 if (slots[i]->op == ALU_OP2_INTERP_X)
831 interp_xz |= 1;
832 if (slots[i]->op == ALU_OP2_INTERP_Z)
833 interp_xz |= 2;
834 }
835 if (interp_xz == 3)
836 return 0;
837 }
838
839 for (i = 0; i < max_slots; ++i) {
840 struct r600_bytecode_alu *alu;
841
842 if (num_once_inst > 0)
843 return 0;
844
845 /* check number of literals */
846 if (prev[i]) {
847 if (r600_bytecode_alu_nliterals(prev[i], literal, &nliteral))
848 return 0;
849 if (r600_bytecode_alu_nliterals(prev[i], prev_literal, &prev_nliteral))
850 return 0;
851 if (is_alu_mova_inst(prev[i])) {
852 if (have_rel)
853 return 0;
854 have_mova = 1;
855 }
856
857 if (alu_uses_rel(prev[i])) {
858 if (have_mova) {
859 return 0;
860 }
861 have_rel = 1;
862 }
863 if (alu_uses_lds(prev[i]))
864 return 0;
865
866 num_once_inst += is_alu_once_inst(prev[i]);
867 }
868 if (slots[i] && r600_bytecode_alu_nliterals(slots[i], literal, &nliteral))
869 return 0;
870
871 /* Let's check used slots. */
872 if (prev[i] && !slots[i]) {
873 result[i] = prev[i];
874 continue;
875 } else if (prev[i] && slots[i]) {
876 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
877 /* Trans unit is still free try to use it. */
878 if (is_alu_any_unit_inst(bc, slots[i]) && !alu_uses_lds(slots[i])) {
879 result[i] = prev[i];
880 result[4] = slots[i];
881 } else if (is_alu_any_unit_inst(bc, prev[i])) {
882 if (slots[i]->dst.sel == prev[i]->dst.sel &&
883 alu_writes(slots[i]) &&
884 alu_writes(prev[i]))
885 return 0;
886
887 result[i] = slots[i];
888 result[4] = prev[i];
889 } else
890 return 0;
891 } else
892 return 0;
893 } else if(!slots[i]) {
894 continue;
895 } else {
896 if (max_slots == 5 && slots[i] && prev[4] &&
897 slots[i]->dst.sel == prev[4]->dst.sel &&
898 slots[i]->dst.chan == prev[4]->dst.chan &&
899 alu_writes(slots[i]) &&
900 alu_writes(prev[4]))
901 return 0;
902
903 result[i] = slots[i];
904 }
905
906 alu = slots[i];
907 num_once_inst += is_alu_once_inst(alu);
908
909 /* don't reschedule NOPs */
910 if (is_nop_inst(alu))
911 return 0;
912
913 if (is_alu_mova_inst(alu)) {
914 if (have_rel) {
915 return 0;
916 }
917 have_mova = 1;
918 }
919
920 if (alu_uses_rel(alu)) {
921 if (have_mova) {
922 return 0;
923 }
924 have_rel = 1;
925 }
926
927 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
928 alu->op == ALU_OP0_SET_CF_IDX1)
929 return 0; /* data hazard with MOVA */
930
931 /* Let's check source gprs */
932 num_src = r600_bytecode_get_num_operands(alu);
933 for (src = 0; src < num_src; ++src) {
934
935 /* Constants don't matter. */
936 if (!is_gpr(alu->src[src].sel))
937 continue;
938
939 for (j = 0; j < max_slots; ++j) {
940 if (!prev[j] || !alu_writes(prev[j]))
941 continue;
942
943 /* If it's relative then we can't determin which gpr is really used. */
944 if (prev[j]->dst.chan == alu->src[src].chan &&
945 (prev[j]->dst.sel == alu->src[src].sel ||
946 prev[j]->dst.rel || alu->src[src].rel))
947 return 0;
948 }
949 }
950 }
951
952 /* more than one PRED_ or KILL_ ? */
953 if (num_once_inst > 1)
954 return 0;
955
956 /* check if the result can still be swizzlet */
957 r = check_and_set_bank_swizzle(bc, result);
958 if (r)
959 return 0;
960
961 /* looks like everything worked out right, apply the changes */
962
963 /* undo adding previus literals */
964 bc->cf_last->ndw -= align(prev_nliteral, 2);
965
966 /* sort instructions */
967 for (i = 0; i < max_slots; ++i) {
968 slots[i] = result[i];
969 if (result[i]) {
970 list_del(&result[i]->list);
971 result[i]->last = 0;
972 list_addtail(&result[i]->list, &bc->cf_last->alu);
973 }
974 }
975
976 /* determine new last instruction */
977 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
978
979 /* determine new first instruction */
980 for (i = 0; i < max_slots; ++i) {
981 if (result[i]) {
982 bc->cf_last->curr_bs_head = result[i];
983 break;
984 }
985 }
986
987 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
988 bc->cf_last->prev2_bs_head = NULL;
989
990 return 0;
991 }
992
993 /* we'll keep kcache sets sorted by bank & addr */
r600_bytecode_alloc_kcache_line(struct r600_bytecode * bc,struct r600_bytecode_kcache * kcache,unsigned bank,unsigned line,unsigned index_mode)994 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
995 struct r600_bytecode_kcache *kcache,
996 unsigned bank, unsigned line, unsigned index_mode)
997 {
998 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
999
1000 for (i = 0; i < kcache_banks; i++) {
1001 if (kcache[i].mode) {
1002 int d;
1003
1004 if (kcache[i].bank < bank)
1005 continue;
1006
1007 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
1008 kcache[i].bank > bank) {
1009 /* try to insert new line */
1010 if (kcache[kcache_banks-1].mode) {
1011 /* all sets are in use */
1012 return -ENOMEM;
1013 }
1014
1015 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
1016 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1017 kcache[i].bank = bank;
1018 kcache[i].addr = line;
1019 kcache[i].index_mode = index_mode;
1020 return 0;
1021 }
1022
1023 d = line - kcache[i].addr;
1024
1025 if (d == -1) {
1026 kcache[i].addr--;
1027 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
1028 /* we are prepending the line to the current set,
1029 * discarding the existing second line,
1030 * so we'll have to insert line+2 after it */
1031 line += 2;
1032 continue;
1033 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
1034 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1035 return 0;
1036 } else {
1037 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
1038 return -ENOMEM;
1039 }
1040 } else if (d == 1) {
1041 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1042 return 0;
1043 } else if (d == 0)
1044 return 0;
1045 } else { /* free kcache set - use it */
1046 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1047 kcache[i].bank = bank;
1048 kcache[i].addr = line;
1049 kcache[i].index_mode = index_mode;
1050 return 0;
1051 }
1052 }
1053 return -ENOMEM;
1054 }
1055
r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode * bc,struct r600_bytecode_kcache * kcache,struct r600_bytecode_alu * alu)1056 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1057 struct r600_bytecode_kcache *kcache,
1058 struct r600_bytecode_alu *alu)
1059 {
1060 int i, r;
1061
1062 for (i = 0; i < 3; i++) {
1063 unsigned bank, line, sel = alu->src[i].sel, index_mode;
1064
1065 if (sel < 512)
1066 continue;
1067
1068 bank = alu->src[i].kc_bank;
1069 assert(bank < R600_MAX_HW_CONST_BUFFERS);
1070 line = (sel-512)>>4;
1071 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1072
1073 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
1074 return r;
1075 }
1076 return 0;
1077 }
1078
r600_bytecode_assign_kcache_banks(struct r600_bytecode_alu * alu,struct r600_bytecode_kcache * kcache)1079 static int r600_bytecode_assign_kcache_banks(
1080 struct r600_bytecode_alu *alu,
1081 struct r600_bytecode_kcache * kcache)
1082 {
1083 int i, j;
1084
1085 /* Alter the src operands to refer to the kcache. */
1086 for (i = 0; i < 3; ++i) {
1087 static const unsigned int base[] = {128, 160, 256, 288};
1088 unsigned int line, sel = alu->src[i].sel, found = 0;
1089
1090 if (sel < 512)
1091 continue;
1092
1093 sel -= 512;
1094 line = sel>>4;
1095
1096 for (j = 0; j < 4 && !found; ++j) {
1097 switch (kcache[j].mode) {
1098 case V_SQ_CF_KCACHE_NOP:
1099 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1100 R600_ERR("unexpected kcache line mode\n");
1101 return -ENOMEM;
1102 default:
1103 if (kcache[j].bank == alu->src[i].kc_bank &&
1104 kcache[j].addr <= line &&
1105 line < kcache[j].addr + kcache[j].mode) {
1106 alu->src[i].sel = sel - (kcache[j].addr<<4);
1107 alu->src[i].sel += base[j];
1108 found=1;
1109 }
1110 }
1111 }
1112 }
1113 return 0;
1114 }
1115
r600_bytecode_alloc_kcache_lines(struct r600_bytecode * bc,struct r600_bytecode_alu * alu,unsigned type)1116 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1117 struct r600_bytecode_alu *alu,
1118 unsigned type)
1119 {
1120 struct r600_bytecode_kcache kcache_sets[4];
1121 struct r600_bytecode_kcache *kcache = kcache_sets;
1122 int r;
1123
1124 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1125
1126 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1127 /* can't alloc, need to start new clause */
1128 if ((r = r600_bytecode_add_cf(bc))) {
1129 return r;
1130 }
1131 bc->cf_last->op = type;
1132
1133 /* retry with the new clause */
1134 kcache = bc->cf_last->kcache;
1135 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1136 /* can't alloc again- should never happen */
1137 return r;
1138 }
1139 } else {
1140 /* update kcache sets */
1141 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1142 }
1143
1144 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1145 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1146 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1147 if (bc->chip_class < EVERGREEN)
1148 return -ENOMEM;
1149 bc->cf_last->eg_alu_extended = 1;
1150 }
1151
1152 return 0;
1153 }
1154
insert_nop_r6xx(struct r600_bytecode * bc)1155 static int insert_nop_r6xx(struct r600_bytecode *bc)
1156 {
1157 struct r600_bytecode_alu alu;
1158 int r, i;
1159
1160 for (i = 0; i < 4; i++) {
1161 memset(&alu, 0, sizeof(alu));
1162 alu.op = ALU_OP0_NOP;
1163 alu.src[0].chan = i;
1164 alu.dst.chan = i;
1165 alu.last = (i == 3);
1166 r = r600_bytecode_add_alu(bc, &alu);
1167 if (r)
1168 return r;
1169 }
1170 return 0;
1171 }
1172
1173 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
load_ar_r6xx(struct r600_bytecode * bc)1174 static int load_ar_r6xx(struct r600_bytecode *bc)
1175 {
1176 struct r600_bytecode_alu alu;
1177 int r;
1178
1179 if (bc->ar_loaded)
1180 return 0;
1181
1182 /* hack to avoid making MOVA the last instruction in the clause */
1183 if ((bc->cf_last->ndw>>1) >= 110)
1184 bc->force_add_cf = 1;
1185
1186 memset(&alu, 0, sizeof(alu));
1187 alu.op = ALU_OP1_MOVA_GPR_INT;
1188 alu.src[0].sel = bc->ar_reg;
1189 alu.src[0].chan = bc->ar_chan;
1190 alu.last = 1;
1191 alu.index_mode = INDEX_MODE_LOOP;
1192 r = r600_bytecode_add_alu(bc, &alu);
1193 if (r)
1194 return r;
1195
1196 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1197 bc->ar_loaded = 1;
1198 return 0;
1199 }
1200
1201 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
load_ar(struct r600_bytecode * bc)1202 static int load_ar(struct r600_bytecode *bc)
1203 {
1204 struct r600_bytecode_alu alu;
1205 int r;
1206
1207 if (bc->ar_handling)
1208 return load_ar_r6xx(bc);
1209
1210 if (bc->ar_loaded)
1211 return 0;
1212
1213 /* hack to avoid making MOVA the last instruction in the clause */
1214 if ((bc->cf_last->ndw>>1) >= 110)
1215 bc->force_add_cf = 1;
1216
1217 memset(&alu, 0, sizeof(alu));
1218 alu.op = ALU_OP1_MOVA_INT;
1219 alu.src[0].sel = bc->ar_reg;
1220 alu.src[0].chan = bc->ar_chan;
1221 alu.last = 1;
1222 r = r600_bytecode_add_alu(bc, &alu);
1223 if (r)
1224 return r;
1225
1226 bc->cf_last->r6xx_uses_waterfall = 1;
1227 bc->ar_loaded = 1;
1228 return 0;
1229 }
1230
r600_bytecode_add_alu_type(struct r600_bytecode * bc,const struct r600_bytecode_alu * alu,unsigned type)1231 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1232 const struct r600_bytecode_alu *alu, unsigned type)
1233 {
1234 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1235 struct r600_bytecode_alu *lalu;
1236 int i, r;
1237
1238 if (!nalu)
1239 return -ENOMEM;
1240 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1241
1242 if (alu->is_op3) {
1243 /* will fail later since alu does not support it. */
1244 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1245 }
1246
1247 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1248 /* check if we could add it anyway */
1249 if (bc->cf_last->op == CF_OP_ALU &&
1250 type == CF_OP_ALU_PUSH_BEFORE) {
1251 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1252 if (lalu->execute_mask) {
1253 bc->force_add_cf = 1;
1254 break;
1255 }
1256 }
1257 } else
1258 bc->force_add_cf = 1;
1259 }
1260
1261 /* cf can contains only alu or only vtx or only tex */
1262 if (bc->cf_last == NULL || bc->force_add_cf) {
1263 r = r600_bytecode_add_cf(bc);
1264 if (r) {
1265 free(nalu);
1266 return r;
1267 }
1268 }
1269 bc->cf_last->op = type;
1270
1271 /* Load index register if required */
1272 if (bc->chip_class >= EVERGREEN) {
1273 for (i = 0; i < 3; i++)
1274 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1275 egcm_load_index_reg(bc, 0, true);
1276 }
1277
1278 /* Check AR usage and load it if required */
1279 for (i = 0; i < 3; i++)
1280 if (nalu->src[i].rel && !bc->ar_loaded)
1281 load_ar(bc);
1282
1283 if (nalu->dst.rel && !bc->ar_loaded)
1284 load_ar(bc);
1285
1286 /* Setup the kcache for this ALU instruction. This will start a new
1287 * ALU clause if needed. */
1288 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1289 free(nalu);
1290 return r;
1291 }
1292
1293 if (!bc->cf_last->curr_bs_head) {
1294 bc->cf_last->curr_bs_head = nalu;
1295 }
1296 /* number of gpr == the last gpr used in any alu */
1297 for (i = 0; i < 3; i++) {
1298 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1299 bc->ngpr = nalu->src[i].sel + 1;
1300 }
1301 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1302 r600_bytecode_special_constants(nalu->src[i].value,
1303 &nalu->src[i].sel);
1304 }
1305 if (nalu->dst.sel >= bc->ngpr) {
1306 bc->ngpr = nalu->dst.sel + 1;
1307 }
1308 list_addtail(&nalu->list, &bc->cf_last->alu);
1309 /* each alu use 2 dwords */
1310 bc->cf_last->ndw += 2;
1311 bc->ndw += 2;
1312
1313 /* process cur ALU instructions for bank swizzle */
1314 if (nalu->last) {
1315 uint32_t literal[4];
1316 unsigned nliteral;
1317 struct r600_bytecode_alu *slots[5];
1318 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1319 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1320 if (r)
1321 return r;
1322
1323 if (bc->cf_last->prev_bs_head) {
1324 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1325 if (r)
1326 return r;
1327 }
1328
1329 if (bc->cf_last->prev_bs_head) {
1330 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1331 if (r)
1332 return r;
1333 }
1334
1335 r = check_and_set_bank_swizzle(bc, slots);
1336 if (r)
1337 return r;
1338
1339 for (i = 0, nliteral = 0; i < max_slots; i++) {
1340 if (slots[i]) {
1341 r = r600_bytecode_alu_nliterals(slots[i], literal, &nliteral);
1342 if (r)
1343 return r;
1344 }
1345 }
1346 bc->cf_last->ndw += align(nliteral, 2);
1347
1348 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1349 * worst case */
1350 if ((bc->cf_last->ndw >> 1) >= 120) {
1351 bc->force_add_cf = 1;
1352 }
1353
1354 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1355 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1356 bc->cf_last->curr_bs_head = NULL;
1357 }
1358
1359 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1360 insert_nop_r6xx(bc);
1361
1362 /* Might need to insert spill write ops after current clause */
1363 if (nalu->last && bc->n_pending_outputs) {
1364 while (bc->n_pending_outputs) {
1365 r = r600_bytecode_add_output(bc, &bc->pending_outputs[--bc->n_pending_outputs]);
1366 if (r)
1367 return r;
1368 }
1369 }
1370
1371 return 0;
1372 }
1373
r600_bytecode_add_alu(struct r600_bytecode * bc,const struct r600_bytecode_alu * alu)1374 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1375 {
1376 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1377 }
1378
r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode * bc)1379 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1380 {
1381 switch (bc->chip_class) {
1382 case R600:
1383 return 8;
1384
1385 case R700:
1386 case EVERGREEN:
1387 case CAYMAN:
1388 return 16;
1389
1390 default:
1391 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1392 return 8;
1393 }
1394 }
1395
last_inst_was_not_vtx_fetch(struct r600_bytecode * bc)1396 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1397 {
1398 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1399 bc->cf_last->op != CF_OP_GDS &&
1400 (bc->chip_class == CAYMAN ||
1401 bc->cf_last->op != CF_OP_TEX));
1402 }
1403
r600_bytecode_add_vtx_internal(struct r600_bytecode * bc,const struct r600_bytecode_vtx * vtx,bool use_tc)1404 static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx,
1405 bool use_tc)
1406 {
1407 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1408 int r;
1409
1410 if (!nvtx)
1411 return -ENOMEM;
1412 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1413
1414 /* Load index register if required */
1415 if (bc->chip_class >= EVERGREEN) {
1416 if (vtx->buffer_index_mode)
1417 egcm_load_index_reg(bc, vtx->buffer_index_mode - 1, false);
1418 }
1419
1420 /* cf can contains only alu or only vtx or only tex */
1421 if (bc->cf_last == NULL ||
1422 last_inst_was_not_vtx_fetch(bc) ||
1423 bc->force_add_cf) {
1424 r = r600_bytecode_add_cf(bc);
1425 if (r) {
1426 free(nvtx);
1427 return r;
1428 }
1429 switch (bc->chip_class) {
1430 case R600:
1431 case R700:
1432 bc->cf_last->op = CF_OP_VTX;
1433 break;
1434 case EVERGREEN:
1435 if (use_tc)
1436 bc->cf_last->op = CF_OP_TEX;
1437 else
1438 bc->cf_last->op = CF_OP_VTX;
1439 break;
1440 case CAYMAN:
1441 bc->cf_last->op = CF_OP_TEX;
1442 break;
1443 default:
1444 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1445 free(nvtx);
1446 return -EINVAL;
1447 }
1448 }
1449 list_addtail(&nvtx->list, &bc->cf_last->vtx);
1450 /* each fetch use 4 dwords */
1451 bc->cf_last->ndw += 4;
1452 bc->ndw += 4;
1453 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1454 bc->force_add_cf = 1;
1455
1456 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1457 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1458
1459 return 0;
1460 }
1461
r600_bytecode_add_vtx(struct r600_bytecode * bc,const struct r600_bytecode_vtx * vtx)1462 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1463 {
1464 return r600_bytecode_add_vtx_internal(bc, vtx, false);
1465 }
1466
r600_bytecode_add_vtx_tc(struct r600_bytecode * bc,const struct r600_bytecode_vtx * vtx)1467 int r600_bytecode_add_vtx_tc(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1468 {
1469 return r600_bytecode_add_vtx_internal(bc, vtx, true);
1470 }
1471
r600_bytecode_add_tex(struct r600_bytecode * bc,const struct r600_bytecode_tex * tex)1472 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1473 {
1474 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1475 int r;
1476
1477 if (!ntex)
1478 return -ENOMEM;
1479 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1480
1481 /* Load index register if required */
1482 if (bc->chip_class >= EVERGREEN) {
1483 if (tex->sampler_index_mode || tex->resource_index_mode)
1484 egcm_load_index_reg(bc, 1, false);
1485 }
1486
1487 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1488 if (bc->cf_last != NULL &&
1489 bc->cf_last->op == CF_OP_TEX) {
1490 struct r600_bytecode_tex *ttex;
1491 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1492 if (ttex->dst_gpr == ntex->src_gpr &&
1493 (ttex->dst_sel_x < 4 || ttex->dst_sel_y < 4 ||
1494 ttex->dst_sel_z < 4 || ttex->dst_sel_w < 4)) {
1495 bc->force_add_cf = 1;
1496 break;
1497 }
1498 }
1499 /* vtx instrs get inserted after tex, so make sure we aren't moving the tex
1500 * before (say) the instr fetching the texcoord.
1501 */
1502 if (!list_is_empty(&bc->cf_last->vtx))
1503 bc->force_add_cf = 1;
1504
1505 /* slight hack to make gradients always go into same cf */
1506 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1507 bc->force_add_cf = 1;
1508 }
1509
1510 /* cf can contains only alu or only vtx or only tex */
1511 if (bc->cf_last == NULL ||
1512 bc->cf_last->op != CF_OP_TEX ||
1513 bc->force_add_cf) {
1514 r = r600_bytecode_add_cf(bc);
1515 if (r) {
1516 free(ntex);
1517 return r;
1518 }
1519 bc->cf_last->op = CF_OP_TEX;
1520 }
1521 if (ntex->src_gpr >= bc->ngpr) {
1522 bc->ngpr = ntex->src_gpr + 1;
1523 }
1524 if (ntex->dst_gpr >= bc->ngpr) {
1525 bc->ngpr = ntex->dst_gpr + 1;
1526 }
1527 list_addtail(&ntex->list, &bc->cf_last->tex);
1528 /* each texture fetch use 4 dwords */
1529 bc->cf_last->ndw += 4;
1530 bc->ndw += 4;
1531 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1532 bc->force_add_cf = 1;
1533 return 0;
1534 }
1535
r600_bytecode_add_gds(struct r600_bytecode * bc,const struct r600_bytecode_gds * gds)1536 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds)
1537 {
1538 struct r600_bytecode_gds *ngds = r600_bytecode_gds();
1539 int r;
1540
1541 if (ngds == NULL)
1542 return -ENOMEM;
1543 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds));
1544
1545 if (bc->chip_class >= EVERGREEN) {
1546 if (gds->uav_index_mode)
1547 egcm_load_index_reg(bc, gds->uav_index_mode - 1, false);
1548 }
1549
1550 if (bc->cf_last == NULL ||
1551 bc->cf_last->op != CF_OP_GDS ||
1552 bc->force_add_cf) {
1553 r = r600_bytecode_add_cf(bc);
1554 if (r) {
1555 free(ngds);
1556 return r;
1557 }
1558 bc->cf_last->op = CF_OP_GDS;
1559 }
1560
1561 list_addtail(&ngds->list, &bc->cf_last->gds);
1562 bc->cf_last->ndw += 4; /* each GDS uses 4 dwords */
1563 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1564 bc->force_add_cf = 1;
1565 return 0;
1566 }
1567
r600_bytecode_add_cfinst(struct r600_bytecode * bc,unsigned op)1568 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1569 {
1570 int r;
1571
1572 /* Emit WAIT_ACK before control flow to ensure pending writes are always acked. */
1573 if (op != CF_OP_WAIT_ACK && op != CF_OP_MEM_SCRATCH)
1574 r600_bytecode_wait_acks(bc);
1575
1576 r = r600_bytecode_add_cf(bc);
1577 if (r)
1578 return r;
1579
1580 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1581 bc->cf_last->op = op;
1582 return 0;
1583 }
1584
cm_bytecode_add_cf_end(struct r600_bytecode * bc)1585 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1586 {
1587 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1588 }
1589
1590 /* common to all 3 families */
r600_bytecode_vtx_build(struct r600_bytecode * bc,struct r600_bytecode_vtx * vtx,unsigned id)1591 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1592 {
1593 if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
1594 return r700_bytecode_fetch_mem_build(bc, vtx, id);
1595 bc->bytecode[id] = S_SQ_VTX_WORD0_VTX_INST(r600_isa_fetch_opcode(bc->isa->hw_class, vtx->op)) |
1596 S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1597 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1598 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1599 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1600 if (bc->chip_class < CAYMAN)
1601 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1602 id++;
1603 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1604 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1605 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1606 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1607 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1608 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1609 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1610 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1611 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1612 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1613 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1614 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1615 if (bc->chip_class >= EVERGREEN)
1616 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1617 if (bc->chip_class < CAYMAN)
1618 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1619 id++;
1620 bc->bytecode[id++] = 0;
1621 return 0;
1622 }
1623
1624 /* common to all 3 families */
r600_bytecode_tex_build(struct r600_bytecode * bc,struct r600_bytecode_tex * tex,unsigned id)1625 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1626 {
1627 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1628 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1629 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1630 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1631 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1632 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1633 if (bc->chip_class >= EVERGREEN)
1634 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1635 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1636 id++;
1637 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1638 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1639 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1640 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1641 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1642 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1643 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1644 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1645 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1646 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1647 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1648 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1649 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1650 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1651 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1652 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1653 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1654 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1655 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1656 bc->bytecode[id++] = 0;
1657 return 0;
1658 }
1659
1660 /* r600 only, r700/eg bits in r700_asm.c */
r600_bytecode_alu_build(struct r600_bytecode * bc,struct r600_bytecode_alu * alu,unsigned id)1661 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1662 {
1663 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1664
1665 /* don't replace gpr by pv or ps for destination register */
1666 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1667 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1668 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1669 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1670 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1671 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1672 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1673 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1674 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1675 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1676 S_SQ_ALU_WORD0_LAST(alu->last);
1677
1678 if (alu->is_op3) {
1679 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1680 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1681 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1682 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1683 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1684 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1685 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1686 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1687 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1688 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1689 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1690 } else {
1691 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1692 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1693 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1694 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1695 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1696 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1697 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1698 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1699 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1700 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1701 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1702 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1703 }
1704 return 0;
1705 }
1706
r600_bytecode_cf_vtx_build(uint32_t * bytecode,const struct r600_bytecode_cf * cf)1707 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1708 {
1709 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1710 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1711 S_SQ_CF_WORD1_BARRIER(1) |
1712 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1)|
1713 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1714 }
1715
1716 /* common for r600/r700 - eg in eg_asm.c */
r600_bytecode_cf_build(struct r600_bytecode * bc,struct r600_bytecode_cf * cf)1717 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1718 {
1719 unsigned id = cf->id;
1720 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1721 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1722
1723
1724 if (cf->op == CF_NATIVE) {
1725 bc->bytecode[id++] = cf->isa[0];
1726 bc->bytecode[id++] = cf->isa[1];
1727 } else if (cfop->flags & CF_ALU) {
1728 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1729 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1730 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1731 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1732
1733 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1734 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1735 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1736 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1737 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1738 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1739 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1740 } else if (cfop->flags & CF_FETCH) {
1741 if (bc->chip_class == R700)
1742 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1743 else
1744 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1745 } else if (cfop->flags & CF_EXP) {
1746 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1747 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1748 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1749 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1750 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1751 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1752 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1753 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1754 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1755 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1756 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1757 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1758 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1759 } else if (cfop->flags & CF_MEM) {
1760 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1761 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1762 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1763 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1764 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1765 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1766 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1767 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1768 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1769 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1770 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1771 } else {
1772 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1773 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1774 S_SQ_CF_WORD1_BARRIER(1) |
1775 S_SQ_CF_WORD1_COND(cf->cond) |
1776 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1777 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1778 }
1779 return 0;
1780 }
1781
r600_bytecode_build(struct r600_bytecode * bc)1782 int r600_bytecode_build(struct r600_bytecode *bc)
1783 {
1784 struct r600_bytecode_cf *cf;
1785 struct r600_bytecode_alu *alu;
1786 struct r600_bytecode_vtx *vtx;
1787 struct r600_bytecode_tex *tex;
1788 struct r600_bytecode_gds *gds;
1789 uint32_t literal[4];
1790 unsigned nliteral;
1791 unsigned addr;
1792 int i, r;
1793
1794 if (!bc->nstack) { // If not 0, Stack_size already provided by llvm
1795 if (bc->stack.max_entries)
1796 bc->nstack = bc->stack.max_entries;
1797 else if (bc->type == PIPE_SHADER_VERTEX ||
1798 bc->type == PIPE_SHADER_TESS_EVAL ||
1799 bc->type == PIPE_SHADER_TESS_CTRL)
1800 bc->nstack = 1;
1801 }
1802
1803 /* first path compute addr of each CF block */
1804 /* addr start after all the CF instructions */
1805 addr = bc->cf_last->id + 2;
1806 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1807 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1808 addr += 3;
1809 addr &= 0xFFFFFFFCUL;
1810 }
1811 cf->addr = addr;
1812 addr += cf->ndw;
1813 bc->ndw = cf->addr + cf->ndw;
1814 }
1815 free(bc->bytecode);
1816 bc->bytecode = calloc(4, bc->ndw);
1817 if (bc->bytecode == NULL)
1818 return -ENOMEM;
1819 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1820 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1821 addr = cf->addr;
1822 if (bc->chip_class >= EVERGREEN)
1823 r = eg_bytecode_cf_build(bc, cf);
1824 else
1825 r = r600_bytecode_cf_build(bc, cf);
1826 if (r)
1827 return r;
1828 if (cfop->flags & CF_ALU) {
1829 nliteral = 0;
1830 memset(literal, 0, sizeof(literal));
1831 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1832 r = r600_bytecode_alu_nliterals(alu, literal, &nliteral);
1833 if (r)
1834 return r;
1835 r600_bytecode_alu_adjust_literals(alu, literal, nliteral);
1836 r600_bytecode_assign_kcache_banks(alu, cf->kcache);
1837
1838 switch(bc->chip_class) {
1839 case R600:
1840 r = r600_bytecode_alu_build(bc, alu, addr);
1841 break;
1842 case R700:
1843 r = r700_bytecode_alu_build(bc, alu, addr);
1844 break;
1845 case EVERGREEN:
1846 case CAYMAN:
1847 r = eg_bytecode_alu_build(bc, alu, addr);
1848 break;
1849 default:
1850 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1851 return -EINVAL;
1852 }
1853 if (r)
1854 return r;
1855 addr += 2;
1856 if (alu->last) {
1857 for (i = 0; i < align(nliteral, 2); ++i) {
1858 bc->bytecode[addr++] = literal[i];
1859 }
1860 nliteral = 0;
1861 memset(literal, 0, sizeof(literal));
1862 }
1863 }
1864 } else if (cf->op == CF_OP_VTX) {
1865 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1866 r = r600_bytecode_vtx_build(bc, vtx, addr);
1867 if (r)
1868 return r;
1869 addr += 4;
1870 }
1871 } else if (cf->op == CF_OP_GDS) {
1872 assert(bc->chip_class >= EVERGREEN);
1873 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
1874 r = eg_bytecode_gds_build(bc, gds, addr);
1875 if (r)
1876 return r;
1877 addr += 4;
1878 }
1879 } else if (cf->op == CF_OP_TEX) {
1880 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1881 assert(bc->chip_class >= EVERGREEN);
1882 r = r600_bytecode_vtx_build(bc, vtx, addr);
1883 if (r)
1884 return r;
1885 addr += 4;
1886 }
1887 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1888 r = r600_bytecode_tex_build(bc, tex, addr);
1889 if (r)
1890 return r;
1891 addr += 4;
1892 }
1893 }
1894 }
1895 return 0;
1896 }
1897
r600_bytecode_clear(struct r600_bytecode * bc)1898 void r600_bytecode_clear(struct r600_bytecode *bc)
1899 {
1900 struct r600_bytecode_cf *cf = NULL, *next_cf;
1901
1902 free(bc->bytecode);
1903 bc->bytecode = NULL;
1904
1905 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1906 struct r600_bytecode_alu *alu = NULL, *next_alu;
1907 struct r600_bytecode_tex *tex = NULL, *next_tex;
1908 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1909 struct r600_bytecode_gds *gds = NULL, *next_gds;
1910
1911 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1912 free(alu);
1913 }
1914
1915 list_inithead(&cf->alu);
1916
1917 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1918 free(tex);
1919 }
1920
1921 list_inithead(&cf->tex);
1922
1923 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1924 free(vtx);
1925 }
1926
1927 list_inithead(&cf->vtx);
1928
1929 LIST_FOR_EACH_ENTRY_SAFE(gds, next_gds, &cf->gds, list) {
1930 free(gds);
1931 }
1932
1933 list_inithead(&cf->gds);
1934
1935 free(cf);
1936 }
1937
1938 list_inithead(&cf->list);
1939 }
1940
print_swizzle(unsigned swz)1941 static int print_swizzle(unsigned swz)
1942 {
1943 const char * swzchars = "xyzw01?_";
1944 assert(swz<8 && swz != 6);
1945 return fprintf(stderr, "%c", swzchars[swz]);
1946 }
1947
print_sel(unsigned sel,unsigned rel,unsigned index_mode,unsigned need_brackets)1948 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1949 unsigned need_brackets)
1950 {
1951 int o = 0;
1952 if (rel && index_mode >= 5 && sel < 128)
1953 o += fprintf(stderr, "G");
1954 if (rel || need_brackets) {
1955 o += fprintf(stderr, "[");
1956 }
1957 o += fprintf(stderr, "%d", sel);
1958 if (rel) {
1959 if (index_mode == 0 || index_mode == 6)
1960 o += fprintf(stderr, "+AR");
1961 else if (index_mode == 4)
1962 o += fprintf(stderr, "+AL");
1963 }
1964 if (rel || need_brackets) {
1965 o += fprintf(stderr, "]");
1966 }
1967 return o;
1968 }
1969
print_dst(struct r600_bytecode_alu * alu)1970 static int print_dst(struct r600_bytecode_alu *alu)
1971 {
1972 int o = 0;
1973 unsigned sel = alu->dst.sel;
1974 char reg_char = 'R';
1975 if (sel > 128 - 4) { /* clause temporary gpr */
1976 sel -= 128 - 4;
1977 reg_char = 'T';
1978 }
1979
1980 if (alu_writes(alu)) {
1981 o += fprintf(stderr, "%c", reg_char);
1982 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1983 } else {
1984 o += fprintf(stderr, "__");
1985 }
1986 o += fprintf(stderr, ".");
1987 o += print_swizzle(alu->dst.chan);
1988 return o;
1989 }
1990
print_src(struct r600_bytecode_alu * alu,unsigned idx)1991 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1992 {
1993 int o = 0;
1994 struct r600_bytecode_alu_src *src = &alu->src[idx];
1995 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1996
1997 if (src->neg)
1998 o += fprintf(stderr,"-");
1999 if (src->abs)
2000 o += fprintf(stderr,"|");
2001
2002 if (sel < 128 - 4) {
2003 o += fprintf(stderr, "R");
2004 } else if (sel < 128) {
2005 o += fprintf(stderr, "T");
2006 sel -= 128 - 4;
2007 } else if (sel < 160) {
2008 o += fprintf(stderr, "KC0");
2009 need_brackets = 1;
2010 sel -= 128;
2011 } else if (sel < 192) {
2012 o += fprintf(stderr, "KC1");
2013 need_brackets = 1;
2014 sel -= 160;
2015 } else if (sel >= 512) {
2016 o += fprintf(stderr, "C%d", src->kc_bank);
2017 need_brackets = 1;
2018 sel -= 512;
2019 } else if (sel >= 448) {
2020 o += fprintf(stderr, "Param");
2021 sel -= 448;
2022 need_chan = 0;
2023 } else if (sel >= 288) {
2024 o += fprintf(stderr, "KC3");
2025 need_brackets = 1;
2026 sel -= 288;
2027 } else if (sel >= 256) {
2028 o += fprintf(stderr, "KC2");
2029 need_brackets = 1;
2030 sel -= 256;
2031 } else {
2032 need_sel = 0;
2033 need_chan = 0;
2034 switch (sel) {
2035 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A:
2036 o += fprintf(stderr, "LDS_A[0x%08X]", src->value);
2037 break;
2038 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B:
2039 o += fprintf(stderr, "LDS_B[0x%08X]", src->value);
2040 break;
2041 case EG_V_SQ_ALU_SRC_LDS_OQ_A:
2042 o += fprintf(stderr, "LDS_OQ_A");
2043 need_chan = 1;
2044 break;
2045 case EG_V_SQ_ALU_SRC_LDS_OQ_B:
2046 o += fprintf(stderr, "LDS_OQ_B");
2047 need_chan = 1;
2048 break;
2049 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP:
2050 o += fprintf(stderr, "LDS_OQ_A_POP");
2051 need_chan = 1;
2052 break;
2053 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP:
2054 o += fprintf(stderr, "LDS_OQ_B_POP");
2055 need_chan = 1;
2056 break;
2057 case EG_V_SQ_ALU_SRC_TIME_LO:
2058 o += fprintf(stderr, "TIME_LO");
2059 break;
2060 case EG_V_SQ_ALU_SRC_TIME_HI:
2061 o += fprintf(stderr, "TIME_HI");
2062 break;
2063 case EG_V_SQ_ALU_SRC_SE_ID:
2064 o += fprintf(stderr, "SE_ID");
2065 break;
2066 case EG_V_SQ_ALU_SRC_SIMD_ID:
2067 o += fprintf(stderr, "SIMD_ID");
2068 break;
2069 case EG_V_SQ_ALU_SRC_HW_WAVE_ID:
2070 o += fprintf(stderr, "HW_WAVE_ID");
2071 break;
2072 case V_SQ_ALU_SRC_PS:
2073 o += fprintf(stderr, "PS");
2074 break;
2075 case V_SQ_ALU_SRC_PV:
2076 o += fprintf(stderr, "PV");
2077 need_chan = 1;
2078 break;
2079 case V_SQ_ALU_SRC_LITERAL:
2080 o += fprintf(stderr, "[0x%08X %f]", src->value, u_bitcast_u2f(src->value));
2081 break;
2082 case V_SQ_ALU_SRC_0_5:
2083 o += fprintf(stderr, "0.5");
2084 break;
2085 case V_SQ_ALU_SRC_M_1_INT:
2086 o += fprintf(stderr, "-1");
2087 break;
2088 case V_SQ_ALU_SRC_1_INT:
2089 o += fprintf(stderr, "1");
2090 break;
2091 case V_SQ_ALU_SRC_1:
2092 o += fprintf(stderr, "1.0");
2093 break;
2094 case V_SQ_ALU_SRC_0:
2095 o += fprintf(stderr, "0");
2096 break;
2097 default:
2098 o += fprintf(stderr, "??IMM_%d", sel);
2099 break;
2100 }
2101 }
2102
2103 if (need_sel)
2104 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
2105
2106 if (need_chan) {
2107 o += fprintf(stderr, ".");
2108 o += print_swizzle(src->chan);
2109 }
2110
2111 if (src->abs)
2112 o += fprintf(stderr,"|");
2113
2114 return o;
2115 }
2116
print_indent(int p,int c)2117 static int print_indent(int p, int c)
2118 {
2119 int o = 0;
2120 while (p++ < c)
2121 o += fprintf(stderr, " ");
2122 return o;
2123 }
2124
r600_bytecode_disasm(struct r600_bytecode * bc)2125 void r600_bytecode_disasm(struct r600_bytecode *bc)
2126 {
2127 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2128 static int index = 0;
2129 struct r600_bytecode_cf *cf = NULL;
2130 struct r600_bytecode_alu *alu = NULL;
2131 struct r600_bytecode_vtx *vtx = NULL;
2132 struct r600_bytecode_tex *tex = NULL;
2133 struct r600_bytecode_gds *gds = NULL;
2134
2135 unsigned i, id, ngr = 0, last;
2136 uint32_t literal[4];
2137 unsigned nliteral;
2138 char chip = '6';
2139
2140 switch (bc->chip_class) {
2141 case R700:
2142 chip = '7';
2143 break;
2144 case EVERGREEN:
2145 chip = 'E';
2146 break;
2147 case CAYMAN:
2148 chip = 'C';
2149 break;
2150 case R600:
2151 default:
2152 chip = '6';
2153 break;
2154 }
2155 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2156 bc->ndw, bc->ngpr, bc->nstack);
2157 fprintf(stderr, "shader %d -- %c\n", index++, chip);
2158
2159 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2160 id = cf->id;
2161 if (cf->op == CF_NATIVE) {
2162 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
2163 bc->bytecode[id + 1]);
2164 } else {
2165 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
2166 if (cfop->flags & CF_ALU) {
2167 if (cf->eg_alu_extended) {
2168 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
2169 bc->bytecode[id + 1], "ALU_EXT");
2170 id += 2;
2171 }
2172 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2173 bc->bytecode[id + 1], cfop->name);
2174 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
2175 for (i = 0; i < 4; ++i) {
2176 if (cf->kcache[i].mode) {
2177 int c_start = (cf->kcache[i].addr << 4);
2178 int c_end = c_start + (cf->kcache[i].mode << 4);
2179 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
2180 i, cf->kcache[i].bank, c_start, c_end,
2181 cf->kcache[i].index_mode ? " " : "",
2182 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
2183 }
2184 }
2185 fprintf(stderr, "\n");
2186 } else if (cfop->flags & CF_FETCH) {
2187 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2188 bc->bytecode[id + 1], cfop->name);
2189 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
2190 if (cf->vpm)
2191 fprintf(stderr, "VPM ");
2192 if (cf->end_of_program)
2193 fprintf(stderr, "EOP ");
2194 fprintf(stderr, "\n");
2195
2196 } else if (cfop->flags & CF_EXP) {
2197 int o = 0;
2198 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
2199 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2200 bc->bytecode[id + 1], cfop->name);
2201 o += print_indent(o, 43);
2202 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2203 if (cf->output.burst_count > 1) {
2204 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2205 cf->output.array_base + cf->output.burst_count - 1);
2206
2207 o += print_indent(o, 55);
2208 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2209 cf->output.gpr + cf->output.burst_count - 1);
2210 } else {
2211 o += fprintf(stderr, "%d ", cf->output.array_base);
2212 o += print_indent(o, 55);
2213 o += fprintf(stderr, "R%d.", cf->output.gpr);
2214 }
2215
2216 o += print_swizzle(cf->output.swizzle_x);
2217 o += print_swizzle(cf->output.swizzle_y);
2218 o += print_swizzle(cf->output.swizzle_z);
2219 o += print_swizzle(cf->output.swizzle_w);
2220
2221 print_indent(o, 67);
2222
2223 fprintf(stderr, " ES:%X ", cf->output.elem_size);
2224 if (cf->mark)
2225 fprintf(stderr, "MARK ");
2226 if (!cf->barrier)
2227 fprintf(stderr, "NO_BARRIER ");
2228 if (cf->end_of_program)
2229 fprintf(stderr, "EOP ");
2230 fprintf(stderr, "\n");
2231 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2232 int o = 0;
2233 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2234 "WRITE_IND_ACK"};
2235 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2236 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2237 o += print_indent(o, 43);
2238 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2239
2240 if (r600_isa_cf(cf->op)->flags & CF_RAT) {
2241 o += fprintf(stderr, "RAT%d", cf->rat.id);
2242 if (cf->rat.index_mode) {
2243 o += fprintf(stderr, "[IDX%d]", cf->rat.index_mode - 1);
2244 }
2245 o += fprintf(stderr, " INST: %d ", cf->rat.inst);
2246 }
2247
2248 if (cf->output.burst_count > 1) {
2249 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2250 cf->output.array_base + cf->output.burst_count - 1);
2251 o += print_indent(o, 55);
2252 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2253 cf->output.gpr + cf->output.burst_count - 1);
2254 } else {
2255 o += fprintf(stderr, "%d ", cf->output.array_base);
2256 o += print_indent(o, 55);
2257 o += fprintf(stderr, "R%d.", cf->output.gpr);
2258 }
2259 for (i = 0; i < 4; ++i) {
2260 if (cf->output.comp_mask & (1 << i))
2261 o += print_swizzle(i);
2262 else
2263 o += print_swizzle(7);
2264 }
2265
2266 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND ||
2267 cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND)
2268 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2269
2270 o += print_indent(o, 67);
2271
2272 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2273 if (cf->output.array_size != 0xFFF)
2274 fprintf(stderr, "AS:%i ", cf->output.array_size);
2275 if (cf->mark)
2276 fprintf(stderr, "MARK ");
2277 if (!cf->barrier)
2278 fprintf(stderr, "NO_BARRIER ");
2279 if (cf->end_of_program)
2280 fprintf(stderr, "EOP ");
2281
2282 if (cf->output.mark)
2283 fprintf(stderr, "MARK ");
2284
2285 fprintf(stderr, "\n");
2286 } else {
2287 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2288 bc->bytecode[id + 1], cfop->name);
2289 fprintf(stderr, "@%d ", cf->cf_addr);
2290 if (cf->cond)
2291 fprintf(stderr, "CND:%X ", cf->cond);
2292 if (cf->pop_count)
2293 fprintf(stderr, "POP:%X ", cf->pop_count);
2294 if (cf->count && (cfop->flags & CF_EMIT))
2295 fprintf(stderr, "STREAM%d ", cf->count);
2296 if (cf->vpm)
2297 fprintf(stderr, "VPM ");
2298 if (cf->end_of_program)
2299 fprintf(stderr, "EOP ");
2300 fprintf(stderr, "\n");
2301 }
2302 }
2303
2304 id = cf->addr;
2305 nliteral = 0;
2306 last = 1;
2307 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2308 const char *omod_str[] = {"","*2","*4","/2"};
2309 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2310 int o = 0;
2311
2312 r600_bytecode_alu_nliterals(alu, literal, &nliteral);
2313 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2314 if (last)
2315 o += fprintf(stderr, "%4d ", ++ngr);
2316 else
2317 o += fprintf(stderr, " ");
2318 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2319 alu->update_pred ? 'P':' ',
2320 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2321
2322 o += fprintf(stderr, "%s%s%s ", aop->name,
2323 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2324
2325 o += print_indent(o,60);
2326 o += print_dst(alu);
2327 for (i = 0; i < aop->src_count; ++i) {
2328 o += fprintf(stderr, i == 0 ? ", ": ", ");
2329 o += print_src(alu, i);
2330 }
2331
2332 if (alu->bank_swizzle) {
2333 o += print_indent(o,75);
2334 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2335 }
2336
2337 fprintf(stderr, "\n");
2338 id += 2;
2339
2340 if (alu->last) {
2341 for (i = 0; i < nliteral; i++, id++) {
2342 float *f = (float*)(bc->bytecode + id);
2343 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2344 print_indent(o, 60);
2345 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2346 }
2347 id += nliteral & 1;
2348 nliteral = 0;
2349 }
2350 last = alu->last;
2351 }
2352
2353 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2354 int o = 0;
2355 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2356 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2357
2358 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2359
2360 o += print_indent(o, 50);
2361
2362 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2363 o += print_swizzle(tex->dst_sel_x);
2364 o += print_swizzle(tex->dst_sel_y);
2365 o += print_swizzle(tex->dst_sel_z);
2366 o += print_swizzle(tex->dst_sel_w);
2367
2368 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2369 o += print_swizzle(tex->src_sel_x);
2370 o += print_swizzle(tex->src_sel_y);
2371 o += print_swizzle(tex->src_sel_z);
2372 o += print_swizzle(tex->src_sel_w);
2373
2374 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2375 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2376
2377 if (tex->sampler_index_mode)
2378 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2379
2380 if (tex->lod_bias)
2381 fprintf(stderr, "LB:%d ", tex->lod_bias);
2382
2383 fprintf(stderr, "CT:%c%c%c%c ",
2384 tex->coord_type_x ? 'N' : 'U',
2385 tex->coord_type_y ? 'N' : 'U',
2386 tex->coord_type_z ? 'N' : 'U',
2387 tex->coord_type_w ? 'N' : 'U');
2388
2389 if (tex->offset_x)
2390 fprintf(stderr, "OX:%d ", tex->offset_x);
2391 if (tex->offset_y)
2392 fprintf(stderr, "OY:%d ", tex->offset_y);
2393 if (tex->offset_z)
2394 fprintf(stderr, "OZ:%d ", tex->offset_z);
2395
2396 id += 4;
2397 fprintf(stderr, "\n");
2398 }
2399
2400 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2401 int o = 0;
2402 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2403 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2404 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2405
2406 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2407
2408 o += print_indent(o, 50);
2409
2410 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2411 o += print_swizzle(vtx->dst_sel_x);
2412 o += print_swizzle(vtx->dst_sel_y);
2413 o += print_swizzle(vtx->dst_sel_z);
2414 o += print_swizzle(vtx->dst_sel_w);
2415
2416 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2417 o += print_swizzle(vtx->src_sel_x);
2418 if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
2419 o += print_swizzle(vtx->src_sel_y);
2420
2421 if (vtx->offset)
2422 fprintf(stderr, " +%db", vtx->offset);
2423
2424 o += print_indent(o, 55);
2425
2426 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2427
2428 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2429
2430 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2431 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2432
2433 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2434 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2435
2436 if (r600_isa_fetch(vtx->op)->flags & FF_MEM) {
2437 if (vtx->uncached)
2438 fprintf(stderr, "UNCACHED ");
2439 if (vtx->indexed)
2440 fprintf(stderr, "INDEXED:%d ", vtx->indexed);
2441
2442 fprintf(stderr, "ELEM_SIZE:%d ", vtx->elem_size);
2443 if (vtx->burst_count)
2444 fprintf(stderr, "BURST_COUNT:%d ", vtx->burst_count);
2445 fprintf(stderr, "ARRAY_BASE:%d ", vtx->array_base);
2446 fprintf(stderr, "ARRAY_SIZE:%d ", vtx->array_size);
2447 }
2448
2449 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2450 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2451 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2452 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2453 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2454
2455 id += 4;
2456 }
2457
2458 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
2459 int o = 0;
2460 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2461 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2462
2463 o += fprintf(stderr, "%s ", r600_isa_fetch(gds->op)->name);
2464
2465 if (gds->op != FETCH_OP_TF_WRITE) {
2466 o += fprintf(stderr, "R%d.", gds->dst_gpr);
2467 o += print_swizzle(gds->dst_sel_x);
2468 o += print_swizzle(gds->dst_sel_y);
2469 o += print_swizzle(gds->dst_sel_z);
2470 o += print_swizzle(gds->dst_sel_w);
2471 }
2472
2473 o += fprintf(stderr, ", R%d.", gds->src_gpr);
2474 o += print_swizzle(gds->src_sel_x);
2475 o += print_swizzle(gds->src_sel_y);
2476 o += print_swizzle(gds->src_sel_z);
2477
2478 if (gds->op != FETCH_OP_TF_WRITE) {
2479 o += fprintf(stderr, ", R%d.", gds->src_gpr2);
2480 }
2481 if (gds->alloc_consume) {
2482 o += fprintf(stderr, " UAV: %d", gds->uav_id);
2483 if (gds->uav_index_mode)
2484 o += fprintf(stderr, "[%s]", index_mode[gds->uav_index_mode]);
2485 }
2486 fprintf(stderr, "\n");
2487 id += 4;
2488 }
2489 }
2490
2491 fprintf(stderr, "--------------------------------------\n");
2492 }
2493
r600_vertex_data_type(enum pipe_format pformat,unsigned * format,unsigned * num_format,unsigned * format_comp,unsigned * endian)2494 void r600_vertex_data_type(enum pipe_format pformat,
2495 unsigned *format,
2496 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2497 {
2498 const struct util_format_description *desc;
2499 unsigned i;
2500
2501 *format = 0;
2502 *num_format = 0;
2503 *format_comp = 0;
2504 *endian = ENDIAN_NONE;
2505
2506 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2507 *format = FMT_10_11_11_FLOAT;
2508 *endian = r600_endian_swap(32);
2509 return;
2510 }
2511
2512 if (pformat == PIPE_FORMAT_B5G6R5_UNORM) {
2513 *format = FMT_5_6_5;
2514 *endian = r600_endian_swap(16);
2515 return;
2516 }
2517
2518 if (pformat == PIPE_FORMAT_B5G5R5A1_UNORM) {
2519 *format = FMT_1_5_5_5;
2520 *endian = r600_endian_swap(16);
2521 return;
2522 }
2523
2524 if (pformat == PIPE_FORMAT_A1B5G5R5_UNORM) {
2525 *format = FMT_5_5_5_1;
2526 return;
2527 }
2528
2529 desc = util_format_description(pformat);
2530 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2531 goto out_unknown;
2532 }
2533
2534 /* Find the first non-VOID channel. */
2535 for (i = 0; i < 4; i++) {
2536 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2537 break;
2538 }
2539 }
2540
2541 *endian = r600_endian_swap(desc->channel[i].size);
2542
2543 switch (desc->channel[i].type) {
2544 /* Half-floats, floats, ints */
2545 case UTIL_FORMAT_TYPE_FLOAT:
2546 switch (desc->channel[i].size) {
2547 case 16:
2548 switch (desc->nr_channels) {
2549 case 1:
2550 *format = FMT_16_FLOAT;
2551 break;
2552 case 2:
2553 *format = FMT_16_16_FLOAT;
2554 break;
2555 case 3:
2556 case 4:
2557 *format = FMT_16_16_16_16_FLOAT;
2558 break;
2559 }
2560 break;
2561 case 32:
2562 switch (desc->nr_channels) {
2563 case 1:
2564 *format = FMT_32_FLOAT;
2565 break;
2566 case 2:
2567 *format = FMT_32_32_FLOAT;
2568 break;
2569 case 3:
2570 *format = FMT_32_32_32_FLOAT;
2571 break;
2572 case 4:
2573 *format = FMT_32_32_32_32_FLOAT;
2574 break;
2575 }
2576 break;
2577 default:
2578 goto out_unknown;
2579 }
2580 break;
2581 /* Unsigned ints */
2582 case UTIL_FORMAT_TYPE_UNSIGNED:
2583 /* Signed ints */
2584 case UTIL_FORMAT_TYPE_SIGNED:
2585 switch (desc->channel[i].size) {
2586 case 4:
2587 switch (desc->nr_channels) {
2588 case 2:
2589 *format = FMT_4_4;
2590 break;
2591 case 4:
2592 *format = FMT_4_4_4_4;
2593 break;
2594 }
2595 break;
2596 case 8:
2597 switch (desc->nr_channels) {
2598 case 1:
2599 *format = FMT_8;
2600 break;
2601 case 2:
2602 *format = FMT_8_8;
2603 break;
2604 case 3:
2605 case 4:
2606 *format = FMT_8_8_8_8;
2607 break;
2608 }
2609 break;
2610 case 10:
2611 if (desc->nr_channels != 4)
2612 goto out_unknown;
2613
2614 *format = FMT_2_10_10_10;
2615 break;
2616 case 16:
2617 switch (desc->nr_channels) {
2618 case 1:
2619 *format = FMT_16;
2620 break;
2621 case 2:
2622 *format = FMT_16_16;
2623 break;
2624 case 3:
2625 case 4:
2626 *format = FMT_16_16_16_16;
2627 break;
2628 }
2629 break;
2630 case 32:
2631 switch (desc->nr_channels) {
2632 case 1:
2633 *format = FMT_32;
2634 break;
2635 case 2:
2636 *format = FMT_32_32;
2637 break;
2638 case 3:
2639 *format = FMT_32_32_32;
2640 break;
2641 case 4:
2642 *format = FMT_32_32_32_32;
2643 break;
2644 }
2645 break;
2646 default:
2647 goto out_unknown;
2648 }
2649 break;
2650 default:
2651 goto out_unknown;
2652 }
2653
2654 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2655 *format_comp = 1;
2656 }
2657
2658 *num_format = 0;
2659 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2660 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2661 if (!desc->channel[i].normalized) {
2662 if (desc->channel[i].pure_integer)
2663 *num_format = 1;
2664 else
2665 *num_format = 2;
2666 }
2667 }
2668 return;
2669 out_unknown:
2670 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2671 }
2672
r600_create_vertex_fetch_shader(struct pipe_context * ctx,unsigned count,const struct pipe_vertex_element * elements)2673 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2674 unsigned count,
2675 const struct pipe_vertex_element *elements)
2676 {
2677 struct r600_context *rctx = (struct r600_context *)ctx;
2678 struct r600_bytecode bc;
2679 struct r600_bytecode_vtx vtx;
2680 const struct util_format_description *desc;
2681 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2682 unsigned format, num_format, format_comp, endian;
2683 uint32_t *bytecode;
2684 int i, j, r, fs_size;
2685 struct r600_fetch_shader *shader;
2686 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB ||
2687 (rctx->screen->b.debug_flags & DBG_NIR);
2688 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2689
2690 assert(count < 32);
2691
2692 memset(&bc, 0, sizeof(bc));
2693 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2694 rctx->screen->has_compressed_msaa_texturing);
2695
2696 bc.isa = rctx->isa;
2697
2698 for (i = 0; i < count; i++) {
2699 if (elements[i].instance_divisor > 1) {
2700 if (rctx->b.chip_class == CAYMAN) {
2701 for (j = 0; j < 4; j++) {
2702 struct r600_bytecode_alu alu;
2703 memset(&alu, 0, sizeof(alu));
2704 alu.op = ALU_OP2_MULHI_UINT;
2705 alu.src[0].sel = 0;
2706 alu.src[0].chan = 3;
2707 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2708 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2709 alu.dst.sel = i + 1;
2710 alu.dst.chan = j;
2711 alu.dst.write = j == 3;
2712 alu.last = j == 3;
2713 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2714 r600_bytecode_clear(&bc);
2715 return NULL;
2716 }
2717 }
2718 } else {
2719 struct r600_bytecode_alu alu;
2720 memset(&alu, 0, sizeof(alu));
2721 alu.op = ALU_OP2_MULHI_UINT;
2722 alu.src[0].sel = 0;
2723 alu.src[0].chan = 3;
2724 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2725 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2726 alu.dst.sel = i + 1;
2727 alu.dst.chan = 3;
2728 alu.dst.write = 1;
2729 alu.last = 1;
2730 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2731 r600_bytecode_clear(&bc);
2732 return NULL;
2733 }
2734 }
2735 }
2736 }
2737
2738 for (i = 0; i < count; i++) {
2739 r600_vertex_data_type(elements[i].src_format,
2740 &format, &num_format, &format_comp, &endian);
2741
2742 desc = util_format_description(elements[i].src_format);
2743 if (!desc) {
2744 r600_bytecode_clear(&bc);
2745 R600_ERR("unknown format %d\n", elements[i].src_format);
2746 return NULL;
2747 }
2748
2749 if (elements[i].src_offset > 65535) {
2750 r600_bytecode_clear(&bc);
2751 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2752 return NULL;
2753 }
2754
2755 memset(&vtx, 0, sizeof(vtx));
2756 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2757 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2758 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2759 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2760 vtx.mega_fetch_count = 0x1F;
2761 vtx.dst_gpr = i + 1;
2762 vtx.dst_sel_x = desc->swizzle[0];
2763 vtx.dst_sel_y = desc->swizzle[1];
2764 vtx.dst_sel_z = desc->swizzle[2];
2765 vtx.dst_sel_w = desc->swizzle[3];
2766 vtx.data_format = format;
2767 vtx.num_format_all = num_format;
2768 vtx.format_comp_all = format_comp;
2769 vtx.offset = elements[i].src_offset;
2770 vtx.endian = endian;
2771
2772 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2773 r600_bytecode_clear(&bc);
2774 return NULL;
2775 }
2776 }
2777
2778 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2779
2780 if ((r = r600_bytecode_build(&bc))) {
2781 r600_bytecode_clear(&bc);
2782 return NULL;
2783 }
2784
2785 if (rctx->screen->b.debug_flags & DBG_FS) {
2786 fprintf(stderr, "--------------------------------------------------------------\n");
2787 fprintf(stderr, "Vertex elements state:\n");
2788 for (i = 0; i < count; i++) {
2789 fprintf(stderr, " ");
2790 util_dump_vertex_element(stderr, elements+i);
2791 fprintf(stderr, "\n");
2792 }
2793
2794 if (!sb_disasm) {
2795 r600_bytecode_disasm(&bc);
2796
2797 fprintf(stderr, "______________________________________________________________\n");
2798 } else {
2799 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2800 }
2801 }
2802
2803 fs_size = bc.ndw*4;
2804
2805 /* Allocate the CSO. */
2806 shader = CALLOC_STRUCT(r600_fetch_shader);
2807 if (!shader) {
2808 r600_bytecode_clear(&bc);
2809 return NULL;
2810 }
2811
2812 u_suballocator_alloc(&rctx->allocator_fetch_shader, fs_size, 256,
2813 &shader->offset,
2814 (struct pipe_resource**)&shader->buffer);
2815 if (!shader->buffer) {
2816 r600_bytecode_clear(&bc);
2817 FREE(shader);
2818 return NULL;
2819 }
2820
2821 bytecode = r600_buffer_map_sync_with_rings
2822 (&rctx->b, shader->buffer,
2823 PIPE_MAP_WRITE | PIPE_MAP_UNSYNCHRONIZED | RADEON_MAP_TEMPORARY);
2824 bytecode += shader->offset / 4;
2825
2826 if (R600_BIG_ENDIAN) {
2827 for (i = 0; i < fs_size / 4; ++i) {
2828 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2829 }
2830 } else {
2831 memcpy(bytecode, bc.bytecode, fs_size);
2832 }
2833 rctx->b.ws->buffer_unmap(rctx->b.ws, shader->buffer->buf);
2834
2835 r600_bytecode_clear(&bc);
2836 return shader;
2837 }
2838
r600_bytecode_alu_read(struct r600_bytecode * bc,struct r600_bytecode_alu * alu,uint32_t word0,uint32_t word1)2839 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2840 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2841 {
2842 /* WORD0 */
2843 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2844 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2845 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2846 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2847 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2848 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2849 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2850 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2851 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2852 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2853 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2854
2855 /* WORD1 */
2856 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2857 if (alu->bank_swizzle)
2858 alu->bank_swizzle_force = alu->bank_swizzle;
2859 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2860 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2861 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2862 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2863 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2864 {
2865 alu->is_op3 = 1;
2866 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2867 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2868 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2869 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2870 alu->op = r600_isa_alu_by_opcode(bc->isa,
2871 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2872
2873 }
2874 else /*ALU_DWORD1_OP2*/
2875 {
2876 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2877 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2878 alu->op = r600_isa_alu_by_opcode(bc->isa,
2879 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2880 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2881 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2882 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2883 alu->execute_mask =
2884 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2885 }
2886 }
2887
2888 #if 0
2889 void r600_bytecode_export_read(struct r600_bytecode *bc,
2890 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2891 {
2892 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2893 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2894 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2895 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2896
2897 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2898 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2899 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2900 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2901 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2902 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2903 output->op = r600_isa_cf_by_opcode(bc->isa,
2904 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2905 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2906 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2907 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2908 }
2909 #endif
2910