1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <math.h>
25
26 #include "util/bitscan.h"
27 #include "util/half_float.h"
28 #include "compiler.h"
29 #include "helpers.h"
30 #include "midgard_ops.h"
31
32 /* Pretty printer for Midgard IR, for use debugging compiler-internal
33 * passes like register allocation. The output superficially resembles
34 * Midgard assembly, with the exception that unit information and such is
35 * (normally) omitted, and generic indices are usually used instead of
36 * registers */
37
38 static void
mir_print_index(int source)39 mir_print_index(int source)
40 {
41 if (source == ~0) {
42 printf("_");
43 return;
44 }
45
46 if (source >= SSA_FIXED_MINIMUM) {
47 /* Specific register */
48 int reg = SSA_REG_FROM_FIXED(source);
49
50 /* TODO: Moving threshold */
51 if (reg > 16 && reg < 24)
52 printf("u%d", 23 - reg);
53 else
54 printf("r%d", reg);
55 } else {
56 printf("%d", source);
57 }
58 }
59
60 static const char components[16] = "xyzwefghijklmnop";
61
62 static void
mir_print_mask(unsigned mask)63 mir_print_mask(unsigned mask)
64 {
65 printf(".");
66
67 for (unsigned i = 0; i < 16; ++i) {
68 if (mask & (1 << i))
69 putchar(components[i]);
70 }
71 }
72
73 static void
mir_print_swizzle(unsigned * swizzle,nir_alu_type T)74 mir_print_swizzle(unsigned *swizzle, nir_alu_type T)
75 {
76 unsigned comps = mir_components_for_type(T);
77
78 printf(".");
79
80 for (unsigned i = 0; i < comps; ++i) {
81 unsigned C = swizzle[i];
82 assert(C < comps);
83 putchar(components[C]);
84 }
85 }
86
87 static const char *
mir_get_unit(unsigned unit)88 mir_get_unit(unsigned unit)
89 {
90 switch (unit) {
91 case ALU_ENAB_VEC_MUL:
92 return "vmul";
93 case ALU_ENAB_SCAL_ADD:
94 return "sadd";
95 case ALU_ENAB_VEC_ADD:
96 return "vadd";
97 case ALU_ENAB_SCAL_MUL:
98 return "smul";
99 case ALU_ENAB_VEC_LUT:
100 return "lut";
101 case ALU_ENAB_BR_COMPACT:
102 return "br";
103 case ALU_ENAB_BRANCH:
104 return "brx";
105 default:
106 return "???";
107 }
108 }
109
110 void
mir_print_constant_component(FILE * fp,const midgard_constants * consts,unsigned c,midgard_reg_mode reg_mode,bool half,unsigned mod,midgard_alu_op op)111 mir_print_constant_component(FILE *fp, const midgard_constants *consts, unsigned c,
112 midgard_reg_mode reg_mode, bool half,
113 unsigned mod, midgard_alu_op op)
114 {
115 bool is_sint = false, is_uint = false, is_hex = false;
116 const char *opname = alu_opcode_props[op].name;
117
118 /* Add a sentinel name to prevent crashing */
119 if (!opname)
120 opname = "unknown";
121
122 if (opname[0] == 'u') {
123 /* If the opcode starts with a 'u' we are sure we deal with an
124 * unsigned int operation
125 */
126 is_uint = true;
127 } else if (opname[0] == 'i') {
128 /* Bit ops are easier to follow when the constant is printed in
129 * hexadecimal. Other operations starting with a 'i' are
130 * considered to operate on signed integers. That might not
131 * be true for all of them, but it's good enough for traces.
132 */
133 if (op >= midgard_alu_op_iand &&
134 op <= midgard_alu_op_ibitcount8)
135 is_hex = true;
136 else
137 is_sint = true;
138 }
139
140 if (half)
141 reg_mode--;
142
143 switch (reg_mode) {
144 case midgard_reg_mode_64:
145 if (is_sint) {
146 fprintf(fp, "%"PRIi64, consts->i64[c]);
147 } else if (is_uint) {
148 fprintf(fp, "%"PRIu64, consts->u64[c]);
149 } else if (is_hex) {
150 fprintf(fp, "0x%"PRIX64, consts->u64[c]);
151 } else {
152 double v = consts->f64[c];
153
154 if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabs(v);
155 if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
156
157 printf("%g", v);
158 }
159 break;
160
161 case midgard_reg_mode_32:
162 if (is_sint) {
163 int64_t v;
164
165 if (half && mod == midgard_int_zero_extend)
166 v = consts->u32[c];
167 else if (half && mod == midgard_int_shift)
168 v = (uint64_t)consts->u32[c] << 32;
169 else
170 v = consts->i32[c];
171
172 fprintf(fp, "%"PRIi64, v);
173 } else if (is_uint || is_hex) {
174 uint64_t v;
175
176 if (half && mod == midgard_int_shift)
177 v = (uint64_t)consts->u32[c] << 32;
178 else
179 v = consts->u32[c];
180
181 fprintf(fp, is_uint ? "%"PRIu64 : "0x%"PRIX64, v);
182 } else {
183 float v = consts->f32[c];
184
185 if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabsf(v);
186 if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
187
188 fprintf(fp, "%g", v);
189 }
190 break;
191
192 case midgard_reg_mode_16:
193 if (is_sint) {
194 int32_t v;
195
196 if (half && mod == midgard_int_zero_extend)
197 v = consts->u16[c];
198 else if (half && mod == midgard_int_shift)
199 v = (uint32_t)consts->u16[c] << 16;
200 else
201 v = consts->i16[c];
202
203 fprintf(fp, "%d", v);
204 } else if (is_uint || is_hex) {
205 uint32_t v;
206
207 if (half && mod == midgard_int_shift)
208 v = (uint32_t)consts->u16[c] << 16;
209 else
210 v = consts->u16[c];
211
212 fprintf(fp, is_uint ? "%u" : "0x%X", v);
213 } else {
214 float v = _mesa_half_to_float(consts->f16[c]);
215
216 if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabsf(v);
217 if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
218
219 fprintf(fp, "%g", v);
220 }
221 break;
222
223 case midgard_reg_mode_8:
224 fprintf(fp, "0x%X", consts->u8[c]);
225
226 if (mod)
227 fprintf(fp, " /* %u */", mod);
228
229 assert(!half); /* No 4-bit */
230
231 break;
232 }
233 }
234
235 static void
mir_print_embedded_constant(midgard_instruction * ins,unsigned src_idx)236 mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
237 {
238 assert(src_idx <= 1);
239
240 unsigned base_size = max_bitsize_for_alu(ins);
241 unsigned sz = nir_alu_type_get_type_size(ins->src_types[src_idx]);
242 bool half = (sz == (base_size >> 1));
243 unsigned mod = mir_pack_mod(ins, src_idx, false);
244 unsigned *swizzle = ins->swizzle[src_idx];
245 midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins));
246 unsigned comp_mask = effective_writemask(ins->op, ins->mask);
247 unsigned num_comp = util_bitcount(comp_mask);
248 unsigned max_comp = mir_components_for_type(ins->dest_type);
249 bool first = true;
250
251 printf("#");
252
253 if (num_comp > 1)
254 printf("vec%d(", num_comp);
255
256 for (unsigned comp = 0; comp < max_comp; comp++) {
257 if (!(comp_mask & (1 << comp)))
258 continue;
259
260 if (first)
261 first = false;
262 else
263 printf(", ");
264
265 mir_print_constant_component(stdout, &ins->constants,
266 swizzle[comp], reg_mode,
267 half, mod, ins->op);
268 }
269
270 if (num_comp > 1)
271 printf(")");
272 }
273
274 #define PRINT_SRC(ins, c) \
275 do { mir_print_index(ins->src[c]); \
276 if (ins->src[c] != ~0 && ins->src_types[c] != nir_type_invalid) { \
277 pan_print_alu_type(ins->src_types[c], stdout); \
278 mir_print_swizzle(ins->swizzle[c], ins->src_types[c]); \
279 } } while (0)
280
281 void
mir_print_instruction(midgard_instruction * ins)282 mir_print_instruction(midgard_instruction *ins)
283 {
284 printf("\t");
285
286 if (midgard_is_branch_unit(ins->unit)) {
287 const char *branch_target_names[] = {
288 "goto", "break", "continue", "discard"
289 };
290
291 printf("%s.", mir_get_unit(ins->unit));
292 if (ins->branch.target_type == TARGET_DISCARD)
293 printf("discard.");
294 else if (ins->writeout)
295 printf("write.");
296 else if (ins->unit == ALU_ENAB_BR_COMPACT &&
297 !ins->branch.conditional)
298 printf("uncond.");
299 else
300 printf("cond.");
301
302 if (!ins->branch.conditional)
303 printf("always");
304 else if (ins->branch.invert_conditional)
305 printf("false");
306 else
307 printf("true");
308
309 if (ins->writeout) {
310 printf(" (c: ");
311 PRINT_SRC(ins, 0);
312 printf(", z: ");
313 PRINT_SRC(ins, 2);
314 printf(", s: ");
315 PRINT_SRC(ins, 3);
316 printf(")");
317 }
318
319 if (ins->branch.target_type != TARGET_DISCARD)
320 printf(" %s -> block(%d)\n",
321 ins->branch.target_type < 4 ?
322 branch_target_names[ins->branch.target_type] : "??",
323 ins->branch.target_block);
324
325 return;
326 }
327
328 switch (ins->type) {
329 case TAG_ALU_4: {
330 midgard_alu_op op = ins->op;
331 const char *name = alu_opcode_props[op].name;
332
333 if (ins->unit)
334 printf("%s.", mir_get_unit(ins->unit));
335
336 printf("%s", name ? name : "??");
337 break;
338 }
339
340 case TAG_LOAD_STORE_4: {
341 midgard_load_store_op op = ins->op;
342 const char *name = load_store_opcode_props[op].name;
343
344 assert(name);
345 printf("%s", name);
346 break;
347 }
348
349 case TAG_TEXTURE_4: {
350 printf("texture");
351
352 if (ins->helper_terminate)
353 printf(".terminate");
354
355 if (ins->helper_execute)
356 printf(".execute");
357
358 break;
359 }
360
361 default:
362 assert(0);
363 }
364
365 if (ins->compact_branch && ins->branch.invert_conditional)
366 printf(".not");
367
368 printf(" ");
369 mir_print_index(ins->dest);
370
371 if (ins->dest != ~0) {
372 pan_print_alu_type(ins->dest_type, stdout);
373 mir_print_mask(ins->mask);
374 }
375
376 printf(", ");
377
378 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
379
380 if (ins->src[0] == r_constant)
381 mir_print_embedded_constant(ins, 0);
382 else
383 PRINT_SRC(ins, 0);
384
385 printf(", ");
386
387 if (ins->has_inline_constant)
388 printf("#%d", ins->inline_constant);
389 else if (ins->src[1] == r_constant)
390 mir_print_embedded_constant(ins, 1);
391 else
392 PRINT_SRC(ins, 1);
393
394 for (unsigned c = 2; c <= 3; ++c) {
395 printf(", ");
396 PRINT_SRC(ins, c);
397 }
398
399 if (ins->no_spill)
400 printf(" /* no spill */");
401
402 printf("\n");
403 }
404
405 /* Dumps MIR for a block or entire shader respective */
406
407 void
mir_print_block(midgard_block * block)408 mir_print_block(midgard_block *block)
409 {
410 printf("block%u: {\n", block->base.name);
411
412 if (block->scheduled) {
413 mir_foreach_bundle_in_block(block, bundle) {
414 for (unsigned i = 0; i < bundle->instruction_count; ++i)
415 mir_print_instruction(bundle->instructions[i]);
416
417 printf("\n");
418 }
419 } else {
420 mir_foreach_instr_in_block(block, ins) {
421 mir_print_instruction(ins);
422 }
423 }
424
425 printf("}");
426
427 if (block->base.successors[0]) {
428 printf(" -> ");
429 pan_foreach_successor((&block->base), succ)
430 printf(" block%u ", succ->name);
431 }
432
433 printf(" from { ");
434 mir_foreach_predecessor(block, pred)
435 printf("block%u ", pred->base.name);
436 printf("}");
437
438 printf("\n\n");
439 }
440
441 void
mir_print_shader(compiler_context * ctx)442 mir_print_shader(compiler_context *ctx)
443 {
444 mir_foreach_block(ctx, block) {
445 mir_print_block((midgard_block *) block);
446 }
447 }
448