1 /*
2 * Copyright © 2021 Ilia Mirkin
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <limits.h>
25 #include <stdio.h>
26 #include <stdint.h>
27 #include <stdlib.h>
28 #include <sys/ioctl.h>
29 #include <nouveau_drm.h>
30 #include "drm-shim/drm_shim.h"
31 #include "util/u_math.h"
32
33 bool drm_shim_driver_prefers_first_render_node = true;
34
35 struct nouveau_device {
36 uint64_t next_offset;
37 };
38
39 static struct nouveau_device nouveau = {
40 .next_offset = 0x1000,
41 };
42
43 struct nouveau_shim_bo {
44 struct shim_bo base;
45 uint64_t offset;
46 };
47
48 static struct nouveau_shim_bo *
nouveau_shim_bo(struct shim_bo * bo)49 nouveau_shim_bo(struct shim_bo *bo)
50 {
51 return (struct nouveau_shim_bo *)bo;
52 }
53
54 struct nouveau_device_info {
55 uint32_t chip_id;
56 };
57
58 static struct nouveau_device_info device_info;
59
60 static int
nouveau_ioctl_noop(int fd,unsigned long request,void * arg)61 nouveau_ioctl_noop(int fd, unsigned long request, void *arg)
62 {
63 return 0;
64 }
65
66 static int
nouveau_ioctl_gem_new(int fd,unsigned long request,void * arg)67 nouveau_ioctl_gem_new(int fd, unsigned long request, void *arg)
68 {
69 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
70 struct drm_nouveau_gem_new *create = arg;
71 struct nouveau_shim_bo *bo = calloc(1, sizeof(*bo));
72
73 drm_shim_bo_init(&bo->base, create->info.size);
74
75 assert(ULONG_MAX - nouveau.next_offset > create->info.size);
76
77 create->info.handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
78 create->info.map_handle = drm_shim_bo_get_mmap_offset(shim_fd, &bo->base);
79
80 if (create->align != 0)
81 nouveau.next_offset = align64(nouveau.next_offset, create->align);
82 create->info.offset = nouveau.next_offset;
83 nouveau.next_offset += create->info.size;
84
85 bo->offset = create->info.offset;
86
87 drm_shim_bo_put(&bo->base);
88
89 return 0;
90 }
91
92 static int
nouveau_ioctl_gem_info(int fd,unsigned long request,void * arg)93 nouveau_ioctl_gem_info(int fd, unsigned long request, void *arg)
94 {
95 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
96 struct drm_nouveau_gem_info *info = arg;
97 struct nouveau_shim_bo *bo =
98 nouveau_shim_bo(drm_shim_bo_lookup(shim_fd, info->handle));
99 info->map_handle = drm_shim_bo_get_mmap_offset(shim_fd, &bo->base);
100 info->offset = bo->offset;
101 info->size = bo->base.size;
102
103 drm_shim_bo_put(&bo->base);
104
105 return 0;
106 }
107
108 static int
nouveau_ioctl_gem_pushbuf(int fd,unsigned long request,void * arg)109 nouveau_ioctl_gem_pushbuf(int fd, unsigned long request, void *arg)
110 {
111 struct drm_nouveau_gem_pushbuf *submit = arg;
112 submit->vram_available = 3ULL << 30;
113 submit->gart_available = 1ULL << 40;
114 return 0;
115 }
116
117 static int
nouveau_ioctl_channel_alloc(int fd,unsigned long request,void * arg)118 nouveau_ioctl_channel_alloc(int fd, unsigned long request, void *arg)
119 {
120 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
121 struct drm_nouveau_channel_alloc *alloc = arg;
122 if (device_info.chip_id == 0x50 || device_info.chip_id >= 0x80)
123 alloc->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM | NOUVEAU_GEM_DOMAIN_GART;
124 else
125 alloc->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
126
127 /* NOTE: this will get leaked since we don't handle the channel
128 * free. However only one channel is created per screen, so impact should
129 * be limited. */
130 struct nouveau_shim_bo *notify = calloc(1, sizeof(*notify));
131 drm_shim_bo_init(¬ify->base, 0x1000);
132 notify->offset = nouveau.next_offset;
133 nouveau.next_offset += 0x1000;
134 alloc->notifier_handle = drm_shim_bo_get_handle(shim_fd, ¬ify->base);
135
136 drm_shim_bo_put(¬ify->base);
137
138 return 0;
139 }
140
141 static int
nouveau_ioctl_get_param(int fd,unsigned long request,void * arg)142 nouveau_ioctl_get_param(int fd, unsigned long request, void *arg)
143 {
144 struct drm_nouveau_getparam *gp = arg;
145
146 switch (gp->param) {
147 case NOUVEAU_GETPARAM_CHIPSET_ID:
148 gp->value = device_info.chip_id;
149 return 0;
150 case NOUVEAU_GETPARAM_PCI_VENDOR:
151 gp->value = 0x10de;
152 return 0;
153 case NOUVEAU_GETPARAM_PCI_DEVICE:
154 gp->value = 0x1004;
155 return 0;
156 case NOUVEAU_GETPARAM_BUS_TYPE:
157 gp->value = 2 /* NV_PCIE */;
158 return 0;
159 case NOUVEAU_GETPARAM_FB_SIZE:
160 gp->value = 3ULL << 30;
161 return 0;
162 case NOUVEAU_GETPARAM_AGP_SIZE:
163 gp->value = 1ULL << 40;
164 return 0;
165 case NOUVEAU_GETPARAM_PTIMER_TIME:
166 gp->value = 0;
167 return 0;
168 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
169 gp->value = 1;
170 return 0;
171 case NOUVEAU_GETPARAM_GRAPH_UNITS:
172 gp->value = 0x01000001;
173 return 0;
174 default:
175 fprintf(stderr, "Unknown DRM_IOCTL_NOUVEAU_GETPARAM %llu\n",
176 (long long unsigned)gp->param);
177 return -1;
178 }
179 }
180
181 static ioctl_fn_t driver_ioctls[] = {
182 [DRM_NOUVEAU_GETPARAM] = nouveau_ioctl_get_param,
183 [DRM_NOUVEAU_CHANNEL_ALLOC] = nouveau_ioctl_channel_alloc,
184 [DRM_NOUVEAU_CHANNEL_FREE] = nouveau_ioctl_noop,
185 [DRM_NOUVEAU_GROBJ_ALLOC] = nouveau_ioctl_noop,
186 [DRM_NOUVEAU_NOTIFIEROBJ_ALLOC] = nouveau_ioctl_noop,
187 [DRM_NOUVEAU_GPUOBJ_FREE] = nouveau_ioctl_noop,
188 [DRM_NOUVEAU_GEM_NEW] = nouveau_ioctl_gem_new,
189 [DRM_NOUVEAU_GEM_PUSHBUF] = nouveau_ioctl_gem_pushbuf,
190 [DRM_NOUVEAU_GEM_CPU_PREP] = nouveau_ioctl_noop,
191 [DRM_NOUVEAU_GEM_INFO] = nouveau_ioctl_gem_info,
192 };
193
194 static void
nouveau_driver_get_device_info(void)195 nouveau_driver_get_device_info(void)
196 {
197 const char *env = getenv("NOUVEAU_CHIPSET");
198
199 if (!env) {
200 device_info.chip_id = 0xf0;
201 return;
202 }
203
204 device_info.chip_id = strtol(env, NULL, 16);
205 }
206
207 void
drm_shim_driver_init(void)208 drm_shim_driver_init(void)
209 {
210 shim_device.bus_type = DRM_BUS_PCI;
211 shim_device.driver_name = "nouveau";
212 shim_device.driver_ioctls = driver_ioctls;
213 shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
214
215 shim_device.version_major = 1;
216 shim_device.version_minor = 0;
217 shim_device.version_patchlevel = 1;
218
219 nouveau_driver_get_device_info();
220
221 /* nothing looks at the pci id, so fix it to a GTX 780 */
222 static const char uevent_content[] =
223 "DRIVER=nouveau\n"
224 "PCI_CLASS=30000\n"
225 "PCI_ID=10de:1004\n"
226 "PCI_SUBSYS_ID=1028:075B\n"
227 "PCI_SLOT_NAME=0000:01:00.0\n"
228 "MODALIAS=pci:v000010ded00005916sv00001028sd0000075Bbc03sc00i00\n";
229 drm_shim_override_file(uevent_content,
230 "/sys/dev/char/%d:%d/device/uevent",
231 DRM_MAJOR, render_node_minor);
232 drm_shim_override_file("0x0\n",
233 "/sys/dev/char/%d:%d/device/revision",
234 DRM_MAJOR, render_node_minor);
235 drm_shim_override_file("0x10de",
236 "/sys/dev/char/%d:%d/device/vendor",
237 DRM_MAJOR, render_node_minor);
238 drm_shim_override_file("0x10de",
239 "/sys/devices/pci0000:00/0000:01:00.0/vendor");
240 drm_shim_override_file("0x1004",
241 "/sys/dev/char/%d:%d/device/device",
242 DRM_MAJOR, render_node_minor);
243 drm_shim_override_file("0x1004",
244 "/sys/devices/pci0000:00/0000:01:00.0/device");
245 drm_shim_override_file("0x1234",
246 "/sys/dev/char/%d:%d/device/subsystem_vendor",
247 DRM_MAJOR, render_node_minor);
248 drm_shim_override_file("0x1234",
249 "/sys/devices/pci0000:00/0000:01:00.0/subsystem_vendor");
250 drm_shim_override_file("0x1234",
251 "/sys/dev/char/%d:%d/device/subsystem_device",
252 DRM_MAJOR, render_node_minor);
253 drm_shim_override_file("0x1234",
254 "/sys/devices/pci0000:00/0000:01:00.0/subsystem_device");
255 }
256