1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 */
24
25 /* This file implements randomized SDMA texture blit tests. */
26
27 #include "r600_pipe_common.h"
28 #include "util/u_surface.h"
29 #include "util/rand_xor.h"
30
31 static uint64_t seed_xorshift128plus[2];
32
33 #define RAND_NUM_SIZE 8
34
35 /* The GPU blits are emulated on the CPU using these CPU textures. */
36
37 struct cpu_texture {
38 uint8_t *ptr;
39 uint64_t size;
40 uint64_t layer_stride;
41 unsigned stride;
42 };
43
alloc_cpu_texture(struct cpu_texture * tex,struct pipe_resource * templ,int bpp)44 static void alloc_cpu_texture(struct cpu_texture *tex,
45 struct pipe_resource *templ, int bpp)
46 {
47 tex->stride = align(templ->width0 * bpp, RAND_NUM_SIZE);
48 tex->layer_stride = (uint64_t)tex->stride * templ->height0;
49 tex->size = tex->layer_stride * templ->array_size;
50 tex->ptr = malloc(tex->size);
51 assert(tex->ptr);
52 }
53
set_random_pixels(struct pipe_context * ctx,struct pipe_resource * tex,struct cpu_texture * cpu)54 static void set_random_pixels(struct pipe_context *ctx,
55 struct pipe_resource *tex,
56 struct cpu_texture *cpu)
57 {
58 struct pipe_transfer *t;
59 uint8_t *map;
60 unsigned x,y,z;
61
62 map = pipe_texture_map_3d(ctx, tex, 0, PIPE_MAP_WRITE,
63 0, 0, 0, tex->width0, tex->height0,
64 tex->array_size, &t);
65 assert(map);
66
67 for (z = 0; z < tex->array_size; z++) {
68 for (y = 0; y < tex->height0; y++) {
69 uint64_t *ptr = (uint64_t*)
70 (map + t->layer_stride*z + t->stride*y);
71 uint64_t *ptr_cpu = (uint64_t*)
72 (cpu->ptr + cpu->layer_stride*z + cpu->stride*y);
73 unsigned size = cpu->stride / RAND_NUM_SIZE;
74
75 assert(t->stride % RAND_NUM_SIZE == 0);
76 assert(cpu->stride % RAND_NUM_SIZE == 0);
77
78 for (x = 0; x < size; x++) {
79 *ptr++ = *ptr_cpu++ =
80 rand_xorshift128plus(seed_xorshift128plus);
81 }
82 }
83 }
84
85 pipe_texture_unmap(ctx, t);
86 }
87
compare_textures(struct pipe_context * ctx,struct pipe_resource * tex,struct cpu_texture * cpu,int bpp)88 static bool compare_textures(struct pipe_context *ctx,
89 struct pipe_resource *tex,
90 struct cpu_texture *cpu, int bpp)
91 {
92 struct pipe_transfer *t;
93 uint8_t *map;
94 int y,z;
95 bool pass = true;
96
97 map = pipe_texture_map_3d(ctx, tex, 0, PIPE_MAP_READ,
98 0, 0, 0, tex->width0, tex->height0,
99 tex->array_size, &t);
100 assert(map);
101
102 for (z = 0; z < tex->array_size; z++) {
103 for (y = 0; y < tex->height0; y++) {
104 uint8_t *ptr = map + t->layer_stride*z + t->stride*y;
105 uint8_t *cpu_ptr = cpu->ptr +
106 cpu->layer_stride*z + cpu->stride*y;
107
108 if (memcmp(ptr, cpu_ptr, tex->width0 * bpp)) {
109 pass = false;
110 goto done;
111 }
112 }
113 }
114 done:
115 pipe_texture_unmap(ctx, t);
116 return pass;
117 }
118
get_format_from_bpp(int bpp)119 static enum pipe_format get_format_from_bpp(int bpp)
120 {
121 switch (bpp) {
122 case 1:
123 return PIPE_FORMAT_R8_UINT;
124 case 2:
125 return PIPE_FORMAT_R16_UINT;
126 case 4:
127 return PIPE_FORMAT_R32_UINT;
128 case 8:
129 return PIPE_FORMAT_R32G32_UINT;
130 case 16:
131 return PIPE_FORMAT_R32G32B32A32_UINT;
132 default:
133 assert(0);
134 return PIPE_FORMAT_NONE;
135 }
136 }
137
array_mode_to_string(struct r600_common_screen * rscreen,struct radeon_surf * surf)138 static const char *array_mode_to_string(struct r600_common_screen *rscreen,
139 struct radeon_surf *surf)
140 {
141 if (rscreen->chip_class >= GFX9) {
142 /* TODO */
143 return " UNKNOWN";
144 } else {
145 switch (surf->u.legacy.level[0].mode) {
146 case RADEON_SURF_MODE_LINEAR_ALIGNED:
147 return "LINEAR_ALIGNED";
148 case RADEON_SURF_MODE_1D:
149 return "1D_TILED_THIN1";
150 case RADEON_SURF_MODE_2D:
151 return "2D_TILED_THIN1";
152 default:
153 assert(0);
154 return " UNKNOWN";
155 }
156 }
157 }
158
generate_max_tex_side(unsigned max_tex_side)159 static unsigned generate_max_tex_side(unsigned max_tex_side)
160 {
161 switch (rand() % 4) {
162 case 0:
163 /* Try to hit large sizes in 1/4 of the cases. */
164 return max_tex_side;
165 case 1:
166 /* Try to hit 1D tiling in 1/4 of the cases. */
167 return 128;
168 default:
169 /* Try to hit common sizes in 2/4 of the cases. */
170 return 2048;
171 }
172 }
173
r600_test_dma(struct r600_common_screen * rscreen)174 void r600_test_dma(struct r600_common_screen *rscreen)
175 {
176 struct pipe_screen *screen = &rscreen->b;
177 struct pipe_context *ctx = screen->context_create(screen, NULL, 0);
178 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
179 uint64_t max_alloc_size;
180 unsigned i, iterations, num_partial_copies, max_tex_side;
181 unsigned num_pass = 0, num_fail = 0;
182
183 max_tex_side = screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_SIZE);
184
185 /* Max 128 MB allowed for both textures. */
186 max_alloc_size = 128 * 1024 * 1024;
187
188 /* the seed for random test parameters */
189 srand(0x9b47d95b);
190 /* the seed for random pixel data */
191 s_rand_xorshift128plus(seed_xorshift128plus, false);
192
193 iterations = 1000000000; /* just kill it when you are bored */
194 num_partial_copies = 30;
195
196 /* These parameters are randomly generated per test:
197 * - whether to do one whole-surface copy or N partial copies per test
198 * - which tiling modes to use (LINEAR_ALIGNED, 1D, 2D)
199 * - which texture dimensions to use
200 * - whether to use VRAM (all tiling modes) and GTT (staging, linear
201 * only) allocations
202 * - random initial pixels in src
203 * - generate random subrectangle copies for partial blits
204 */
205 for (i = 0; i < iterations; i++) {
206 struct pipe_resource tsrc = {}, tdst = {}, *src, *dst;
207 struct r600_texture *rdst;
208 struct r600_texture *rsrc;
209 struct cpu_texture src_cpu, dst_cpu;
210 unsigned bpp, max_width, max_height, max_depth, j, num;
211 unsigned gfx_blits = 0, dma_blits = 0, max_tex_side_gen;
212 unsigned max_tex_layers;
213 bool pass;
214 bool do_partial_copies = rand() & 1;
215
216 /* generate a random test case */
217 tsrc.target = tdst.target = PIPE_TEXTURE_2D_ARRAY;
218 tsrc.depth0 = tdst.depth0 = 1;
219
220 bpp = 1 << (rand() % 5);
221 tsrc.format = tdst.format = get_format_from_bpp(bpp);
222
223 max_tex_side_gen = generate_max_tex_side(max_tex_side);
224 max_tex_layers = rand() % 4 ? 1 : 5;
225
226 tsrc.width0 = (rand() % max_tex_side_gen) + 1;
227 tsrc.height0 = (rand() % max_tex_side_gen) + 1;
228 tsrc.array_size = (rand() % max_tex_layers) + 1;
229
230 /* Have a 1/4 chance of getting power-of-two dimensions. */
231 if (rand() % 4 == 0) {
232 tsrc.width0 = util_next_power_of_two(tsrc.width0);
233 tsrc.height0 = util_next_power_of_two(tsrc.height0);
234 }
235
236 if (!do_partial_copies) {
237 /* whole-surface copies only, same dimensions */
238 tdst = tsrc;
239 } else {
240 max_tex_side_gen = generate_max_tex_side(max_tex_side);
241 max_tex_layers = rand() % 4 ? 1 : 5;
242
243 /* many partial copies, dimensions can be different */
244 tdst.width0 = (rand() % max_tex_side_gen) + 1;
245 tdst.height0 = (rand() % max_tex_side_gen) + 1;
246 tdst.array_size = (rand() % max_tex_layers) + 1;
247
248 /* Have a 1/4 chance of getting power-of-two dimensions. */
249 if (rand() % 4 == 0) {
250 tdst.width0 = util_next_power_of_two(tdst.width0);
251 tdst.height0 = util_next_power_of_two(tdst.height0);
252 }
253 }
254
255 /* check texture sizes */
256 if ((uint64_t)tsrc.width0 * tsrc.height0 * tsrc.array_size * bpp +
257 (uint64_t)tdst.width0 * tdst.height0 * tdst.array_size * bpp >
258 max_alloc_size) {
259 /* too large, try again */
260 i--;
261 continue;
262 }
263
264 /* VRAM + the tiling mode depends on dimensions (3/4 of cases),
265 * or GTT + linear only (1/4 of cases)
266 */
267 tsrc.usage = rand() % 4 ? PIPE_USAGE_DEFAULT : PIPE_USAGE_STAGING;
268 tdst.usage = rand() % 4 ? PIPE_USAGE_DEFAULT : PIPE_USAGE_STAGING;
269
270 /* Allocate textures (both the GPU and CPU copies).
271 * The CPU will emulate what the GPU should be doing.
272 */
273 src = screen->resource_create(screen, &tsrc);
274 dst = screen->resource_create(screen, &tdst);
275 assert(src);
276 assert(dst);
277 rdst = (struct r600_texture*)dst;
278 rsrc = (struct r600_texture*)src;
279 alloc_cpu_texture(&src_cpu, &tsrc, bpp);
280 alloc_cpu_texture(&dst_cpu, &tdst, bpp);
281
282 printf("%4u: dst = (%5u x %5u x %u, %s), "
283 " src = (%5u x %5u x %u, %s), bpp = %2u, ",
284 i, tdst.width0, tdst.height0, tdst.array_size,
285 array_mode_to_string(rscreen, &rdst->surface),
286 tsrc.width0, tsrc.height0, tsrc.array_size,
287 array_mode_to_string(rscreen, &rsrc->surface), bpp);
288 fflush(stdout);
289
290 /* set src pixels */
291 set_random_pixels(ctx, src, &src_cpu);
292
293 /* clear dst pixels */
294 rctx->clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, true);
295 memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
296
297 /* preparation */
298 max_width = MIN2(tsrc.width0, tdst.width0);
299 max_height = MIN2(tsrc.height0, tdst.height0);
300 max_depth = MIN2(tsrc.array_size, tdst.array_size);
301
302 num = do_partial_copies ? num_partial_copies : 1;
303 for (j = 0; j < num; j++) {
304 int width, height, depth;
305 int srcx, srcy, srcz, dstx, dsty, dstz;
306 struct pipe_box box;
307 unsigned old_num_draw_calls = rctx->num_draw_calls;
308 unsigned old_num_dma_calls = rctx->num_dma_calls;
309
310 if (!do_partial_copies) {
311 /* copy whole src to dst */
312 width = max_width;
313 height = max_height;
314 depth = max_depth;
315
316 srcx = srcy = srcz = dstx = dsty = dstz = 0;
317 } else {
318 /* random sub-rectangle copies from src to dst */
319 depth = (rand() % max_depth) + 1;
320 srcz = rand() % (tsrc.array_size - depth + 1);
321 dstz = rand() % (tdst.array_size - depth + 1);
322
323 /* special code path to hit the tiled partial copies */
324 if (!rsrc->surface.is_linear &&
325 !rdst->surface.is_linear &&
326 rand() & 1) {
327 if (max_width < 8 || max_height < 8)
328 continue;
329 width = ((rand() % (max_width / 8)) + 1) * 8;
330 height = ((rand() % (max_height / 8)) + 1) * 8;
331
332 srcx = rand() % (tsrc.width0 - width + 1) & ~0x7;
333 srcy = rand() % (tsrc.height0 - height + 1) & ~0x7;
334
335 dstx = rand() % (tdst.width0 - width + 1) & ~0x7;
336 dsty = rand() % (tdst.height0 - height + 1) & ~0x7;
337 } else {
338 /* just make sure that it doesn't divide by zero */
339 assert(max_width > 0 && max_height > 0);
340
341 width = (rand() % max_width) + 1;
342 height = (rand() % max_height) + 1;
343
344 srcx = rand() % (tsrc.width0 - width + 1);
345 srcy = rand() % (tsrc.height0 - height + 1);
346
347 dstx = rand() % (tdst.width0 - width + 1);
348 dsty = rand() % (tdst.height0 - height + 1);
349 }
350
351 /* special code path to hit out-of-bounds reads in L2T */
352 if (rsrc->surface.is_linear &&
353 !rdst->surface.is_linear &&
354 rand() % 4 == 0) {
355 srcx = 0;
356 srcy = 0;
357 srcz = 0;
358 }
359 }
360
361 /* GPU copy */
362 u_box_3d(srcx, srcy, srcz, width, height, depth, &box);
363 rctx->dma_copy(ctx, dst, 0, dstx, dsty, dstz, src, 0, &box);
364
365 /* See which engine was used. */
366 gfx_blits += rctx->num_draw_calls > old_num_draw_calls;
367 dma_blits += rctx->num_dma_calls > old_num_dma_calls;
368
369 /* CPU copy */
370 util_copy_box(dst_cpu.ptr, tdst.format, dst_cpu.stride,
371 dst_cpu.layer_stride,
372 dstx, dsty, dstz, width, height, depth,
373 src_cpu.ptr, src_cpu.stride,
374 src_cpu.layer_stride,
375 srcx, srcy, srcz);
376 }
377
378 pass = compare_textures(ctx, dst, &dst_cpu, bpp);
379 if (pass)
380 num_pass++;
381 else
382 num_fail++;
383
384 printf("BLITs: GFX = %2u, DMA = %2u, %s [%u/%u]\n",
385 gfx_blits, dma_blits, pass ? "pass" : "fail",
386 num_pass, num_pass+num_fail);
387
388 /* cleanup */
389 pipe_resource_reference(&src, NULL);
390 pipe_resource_reference(&dst, NULL);
391 free(src_cpu.ptr);
392 free(dst_cpu.ptr);
393 }
394
395 ctx->destroy(ctx);
396 exit(0);
397 }
398