1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "ac_binary.h"
25
26 #include "ac_gpu_info.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29
30 #include <gelf.h>
31 #include <libelf.h>
32 #include <sid.h>
33 #include <stdio.h>
34
35 #define SPILLED_SGPRS 0x4
36 #define SPILLED_VGPRS 0x8
37
38 /* Parse configuration data in .AMDGPU.config section format. */
ac_parse_shader_binary_config(const char * data,size_t nbytes,unsigned wave_size,bool really_needs_scratch,const struct radeon_info * info,struct ac_shader_config * conf)39 void ac_parse_shader_binary_config(const char *data, size_t nbytes, unsigned wave_size,
40 bool really_needs_scratch, const struct radeon_info *info,
41 struct ac_shader_config *conf)
42 {
43 uint32_t scratch_size = 0;
44
45 for (size_t i = 0; i < nbytes; i += 8) {
46 unsigned reg = util_le32_to_cpu(*(uint32_t *)(data + i));
47 unsigned value = util_le32_to_cpu(*(uint32_t *)(data + i + 4));
48 switch (reg) {
49 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
50 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
51 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
52 case R_00B848_COMPUTE_PGM_RSRC1:
53 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
54 if (wave_size == 32 || info->wave64_vgpr_alloc_granularity == 8)
55 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8);
56 else
57 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
58
59 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
60 /* TODO: LLVM doesn't set FLOAT_MODE for non-compute shaders */
61 conf->float_mode = G_00B028_FLOAT_MODE(value);
62 conf->rsrc1 = value;
63 break;
64 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
65 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
66 /* TODO: LLVM doesn't set SHARED_VGPR_CNT for all shader types */
67 conf->num_shared_vgprs = G_00B02C_SHARED_VGPR_CNT(value);
68 conf->rsrc2 = value;
69 break;
70 case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
71 conf->num_shared_vgprs = G_00B12C_SHARED_VGPR_CNT(value);
72 conf->rsrc2 = value;
73 break;
74 case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
75 conf->num_shared_vgprs = G_00B22C_SHARED_VGPR_CNT(value);
76 conf->rsrc2 = value;
77 break;
78 case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
79 conf->num_shared_vgprs = G_00B42C_SHARED_VGPR_CNT(value);
80 conf->rsrc2 = value;
81 break;
82 case R_00B84C_COMPUTE_PGM_RSRC2:
83 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
84 conf->rsrc2 = value;
85 break;
86 case R_00B8A0_COMPUTE_PGM_RSRC3:
87 conf->num_shared_vgprs = G_00B8A0_SHARED_VGPR_CNT(value);
88 conf->rsrc3 = value;
89 break;
90 case R_0286CC_SPI_PS_INPUT_ENA:
91 conf->spi_ps_input_ena = value;
92 break;
93 case R_0286D0_SPI_PS_INPUT_ADDR:
94 conf->spi_ps_input_addr = value;
95 break;
96 case R_0286E8_SPI_TMPRING_SIZE:
97 case R_00B860_COMPUTE_TMPRING_SIZE:
98 /* WAVESIZE is in units of 256 dwords. */
99 scratch_size = value;
100 break;
101 case SPILLED_SGPRS:
102 conf->spilled_sgprs = value;
103 break;
104 case SPILLED_VGPRS:
105 conf->spilled_vgprs = value;
106 break;
107 default: {
108 static bool printed;
109
110 if (!printed) {
111 fprintf(stderr,
112 "Warning: LLVM emitted unknown "
113 "config register: 0x%x\n",
114 reg);
115 printed = true;
116 }
117 } break;
118 }
119 }
120
121 if (!conf->spi_ps_input_addr)
122 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
123
124 if (really_needs_scratch) {
125 /* sgprs spills aren't spilling */
126 conf->scratch_bytes_per_wave = G_00B860_WAVESIZE(scratch_size) * 256 * 4;
127 }
128
129 /* GFX 10.3 internally:
130 * - aligns VGPRS to 16 for Wave32 and 8 for Wave64
131 * - aligns LDS to 1024
132 *
133 * For shader-db stats, set num_vgprs that the hw actually uses.
134 */
135 if (info->chip_class >= GFX10_3) {
136 conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8);
137 }
138
139 /* Enable 64-bit and 16-bit denormals, because there is no performance
140 * cost.
141 *
142 * Don't enable denormals for 32-bit floats, because:
143 * - denormals disable output modifiers
144 * - denormals break v_mad_f32
145 * - GFX6 & GFX7 would be very slow
146 */
147 conf->float_mode &= ~V_00B028_FP_ALL_DENORMS;
148 conf->float_mode |= V_00B028_FP_64_DENORMS;
149 }
150