1 /*
2  * Copyright (c) 2015 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "common/intel_l3_config.h"
25 
26 #include "brw_context.h"
27 #include "brw_defines.h"
28 #include "brw_state.h"
29 #include "brw_batch.h"
30 
31 /**
32  * Calculate the desired L3 partitioning based on the current state of the
33  * pipeline.  For now this simply returns the conservative defaults calculated
34  * by get_default_l3_weights(), but we could probably do better by gathering
35  * more statistics from the pipeline state (e.g. guess of expected URB usage
36  * and bound surfaces), or by using feed-back from performance counters.
37  */
38 static struct intel_l3_weights
get_pipeline_state_l3_weights(const struct brw_context * brw)39 get_pipeline_state_l3_weights(const struct brw_context *brw)
40 {
41    const struct brw_stage_state *stage_states[] = {
42       [MESA_SHADER_VERTEX] = &brw->vs.base,
43       [MESA_SHADER_TESS_CTRL] = &brw->tcs.base,
44       [MESA_SHADER_TESS_EVAL] = &brw->tes.base,
45       [MESA_SHADER_GEOMETRY] = &brw->gs.base,
46       [MESA_SHADER_FRAGMENT] = &brw->wm.base,
47       [MESA_SHADER_COMPUTE] = &brw->cs.base
48    };
49    bool needs_dc = false, needs_slm = false;
50 
51    for (unsigned i = 0; i < ARRAY_SIZE(stage_states); i++) {
52       const struct gl_program *prog =
53          brw->ctx._Shader->CurrentProgram[stage_states[i]->stage];
54       const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
55 
56       needs_dc |= (prog && (prog->sh.data->NumAtomicBuffers ||
57                             prog->sh.data->NumShaderStorageBlocks ||
58                             prog->info.num_images)) ||
59          (prog_data && prog_data->total_scratch);
60       needs_slm |= prog_data && prog_data->total_shared;
61    }
62 
63    return intel_get_default_l3_weights(&brw->screen->devinfo,
64                                        needs_dc, needs_slm);
65 }
66 
67 /**
68  * Program the hardware to use the specified L3 configuration.
69  */
70 static void
setup_l3_config(struct brw_context * brw,const struct intel_l3_config * cfg)71 setup_l3_config(struct brw_context *brw, const struct intel_l3_config *cfg)
72 {
73    const struct intel_device_info *devinfo = &brw->screen->devinfo;
74    const bool has_dc = cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_ALL];
75    const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] ||
76                        cfg->n[INTEL_L3P_ALL];
77    const bool has_c = cfg->n[INTEL_L3P_C] || cfg->n[INTEL_L3P_RO] ||
78                       cfg->n[INTEL_L3P_ALL];
79    const bool has_t = cfg->n[INTEL_L3P_T] || cfg->n[INTEL_L3P_RO] ||
80                       cfg->n[INTEL_L3P_ALL];
81    const bool has_slm = cfg->n[INTEL_L3P_SLM];
82 
83    /* According to the hardware docs, the L3 partitioning can only be changed
84     * while the pipeline is completely drained and the caches are flushed,
85     * which involves a first PIPE_CONTROL flush which stalls the pipeline...
86     */
87    brw_emit_pipe_control_flush(brw,
88                                PIPE_CONTROL_DATA_CACHE_FLUSH |
89                                PIPE_CONTROL_CS_STALL);
90 
91    /* ...followed by a second pipelined PIPE_CONTROL that initiates
92     * invalidation of the relevant caches.  Note that because RO invalidation
93     * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
94     * command is processed by the CS) we cannot combine it with the previous
95     * stalling flush as the hardware documentation suggests, because that
96     * would cause the CS to stall on previous rendering *after* RO
97     * invalidation and wouldn't prevent the RO caches from being polluted by
98     * concurrent rendering before the stall completes.  This intentionally
99     * doesn't implement the SKL+ hardware workaround suggesting to enable CS
100     * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
101     * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
102     * already guarantee that there is no concurrent GPGPU kernel execution
103     * (see SKL HSD 2132585).
104     */
105    brw_emit_pipe_control_flush(brw,
106                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
107                                PIPE_CONTROL_CONST_CACHE_INVALIDATE |
108                                PIPE_CONTROL_INSTRUCTION_INVALIDATE |
109                                PIPE_CONTROL_STATE_CACHE_INVALIDATE);
110 
111    /* Now send a third stalling flush to make sure that invalidation is
112     * complete when the L3 configuration registers are modified.
113     */
114    brw_emit_pipe_control_flush(brw,
115                                PIPE_CONTROL_DATA_CACHE_FLUSH |
116                                PIPE_CONTROL_CS_STALL);
117 
118    if (devinfo->ver >= 8) {
119       assert(!cfg->n[INTEL_L3P_IS] && !cfg->n[INTEL_L3P_C] && !cfg->n[INTEL_L3P_T]);
120 
121       const unsigned imm_data = (
122          (devinfo->ver < 11 && has_slm ? GFX8_L3CNTLREG_SLM_ENABLE : 0) |
123          (devinfo->ver == 11 ? GFX11_L3CNTLREG_USE_FULL_WAYS : 0) |
124          SET_FIELD(cfg->n[INTEL_L3P_URB], GFX8_L3CNTLREG_URB_ALLOC) |
125          SET_FIELD(cfg->n[INTEL_L3P_RO], GFX8_L3CNTLREG_RO_ALLOC) |
126          SET_FIELD(cfg->n[INTEL_L3P_DC], GFX8_L3CNTLREG_DC_ALLOC) |
127          SET_FIELD(cfg->n[INTEL_L3P_ALL], GFX8_L3CNTLREG_ALL_ALLOC));
128 
129       /* Set up the L3 partitioning. */
130       brw_load_register_imm32(brw, GFX8_L3CNTLREG, imm_data);
131    } else {
132       assert(!cfg->n[INTEL_L3P_ALL]);
133 
134       /* When enabled SLM only uses a portion of the L3 on half of the banks,
135        * the matching space on the remaining banks has to be allocated to a
136        * client (URB for all validated configurations) set to the
137        * lower-bandwidth 2-bank address hashing mode.
138        */
139       const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
140       assert(!urb_low_bw || cfg->n[INTEL_L3P_URB] == cfg->n[INTEL_L3P_SLM]);
141 
142       /* Minimum number of ways that can be allocated to the URB. */
143       const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
144       assert(cfg->n[INTEL_L3P_URB] >= n0_urb);
145 
146       BEGIN_BATCH(7);
147       OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
148 
149       /* Demote any clients with no ways assigned to LLC. */
150       OUT_BATCH(GFX7_L3SQCREG1);
151       OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
152                  devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
153                  IVB_L3SQCREG1_SQGHPCI_DEFAULT) |
154                 (has_dc ? 0 : GFX7_L3SQCREG1_CONV_DC_UC) |
155                 (has_is ? 0 : GFX7_L3SQCREG1_CONV_IS_UC) |
156                 (has_c ? 0 : GFX7_L3SQCREG1_CONV_C_UC) |
157                 (has_t ? 0 : GFX7_L3SQCREG1_CONV_T_UC));
158 
159       /* Set up the L3 partitioning. */
160       OUT_BATCH(GFX7_L3CNTLREG2);
161       OUT_BATCH((has_slm ? GFX7_L3CNTLREG2_SLM_ENABLE : 0) |
162                 SET_FIELD(cfg->n[INTEL_L3P_URB] - n0_urb, GFX7_L3CNTLREG2_URB_ALLOC) |
163                 (urb_low_bw ? GFX7_L3CNTLREG2_URB_LOW_BW : 0) |
164                 SET_FIELD(cfg->n[INTEL_L3P_ALL], GFX7_L3CNTLREG2_ALL_ALLOC) |
165                 SET_FIELD(cfg->n[INTEL_L3P_RO], GFX7_L3CNTLREG2_RO_ALLOC) |
166                 SET_FIELD(cfg->n[INTEL_L3P_DC], GFX7_L3CNTLREG2_DC_ALLOC));
167       OUT_BATCH(GFX7_L3CNTLREG3);
168       OUT_BATCH(SET_FIELD(cfg->n[INTEL_L3P_IS], GFX7_L3CNTLREG3_IS_ALLOC) |
169                 SET_FIELD(cfg->n[INTEL_L3P_C], GFX7_L3CNTLREG3_C_ALLOC) |
170                 SET_FIELD(cfg->n[INTEL_L3P_T], GFX7_L3CNTLREG3_T_ALLOC));
171 
172       ADVANCE_BATCH();
173 
174       if (can_do_hsw_l3_atomics(brw->screen)) {
175          /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
176           * them disabled to avoid crashing the system hard.
177           */
178          BEGIN_BATCH(5);
179          OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
180          OUT_BATCH(HSW_SCRATCH1);
181          OUT_BATCH(has_dc ? 0 : HSW_SCRATCH1_L3_ATOMIC_DISABLE);
182          OUT_BATCH(HSW_ROW_CHICKEN3);
183          OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) |
184                    (has_dc ? 0 : HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE));
185          ADVANCE_BATCH();
186       }
187    }
188 }
189 
190 /**
191  * Update the URB size in the context state for the specified L3
192  * configuration.
193  */
194 static void
update_urb_size(struct brw_context * brw,const struct intel_l3_config * cfg)195 update_urb_size(struct brw_context *brw, const struct intel_l3_config *cfg)
196 {
197    const struct intel_device_info *devinfo = &brw->screen->devinfo;
198    const unsigned sz = intel_get_l3_config_urb_size(devinfo, cfg);
199 
200    if (brw->urb.size != sz) {
201       brw->urb.size = sz;
202       brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
203 
204       /* If we change the total URB size, reset the individual stage sizes to
205        * zero so that, even if there is no URB size change, gfx7_upload_urb
206        * still re-emits 3DSTATE_URB_*.
207        */
208       brw->urb.vsize = 0;
209       brw->urb.gsize = 0;
210       brw->urb.hsize = 0;
211       brw->urb.dsize = 0;
212    }
213 }
214 
215 void
brw_emit_l3_state(struct brw_context * brw)216 brw_emit_l3_state(struct brw_context *brw)
217 {
218    const struct intel_l3_weights w = get_pipeline_state_l3_weights(brw);
219    const float dw = intel_diff_l3_weights(w, intel_get_l3_config_weights(brw->l3.config));
220    /* The distance between any two compatible weight vectors cannot exceed two
221     * due to the triangle inequality.
222     */
223    const float large_dw_threshold = 2.0;
224    /* Somewhat arbitrary, simply makes sure that there will be no repeated
225     * transitions to the same L3 configuration, could probably do better here.
226     */
227    const float small_dw_threshold = 0.5;
228    /* If we're emitting a new batch the caches should already be clean and the
229     * transition should be relatively cheap, so it shouldn't hurt much to use
230     * the smaller threshold.  Otherwise use the larger threshold so that we
231     * only reprogram the L3 mid-batch if the most recently programmed
232     * configuration is incompatible with the current pipeline state.
233     */
234    const float dw_threshold = (brw->ctx.NewDriverState & BRW_NEW_BATCH ?
235                                small_dw_threshold : large_dw_threshold);
236 
237    if (dw > dw_threshold && can_do_pipelined_register_writes(brw->screen)) {
238       const struct intel_l3_config *const cfg =
239          intel_get_l3_config(&brw->screen->devinfo, w);
240 
241       setup_l3_config(brw, cfg);
242       update_urb_size(brw, cfg);
243       brw->l3.config = cfg;
244 
245       if (INTEL_DEBUG(DEBUG_L3)) {
246          fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold);
247          intel_dump_l3_config(cfg, stderr);
248       }
249    }
250 }
251 
252 const struct brw_tracked_state gfx7_l3_state = {
253    .dirty = {
254       .mesa = 0,
255       .brw = BRW_NEW_BATCH |
256              BRW_NEW_BLORP |
257              BRW_NEW_CS_PROG_DATA |
258              BRW_NEW_FS_PROG_DATA |
259              BRW_NEW_GS_PROG_DATA |
260              BRW_NEW_TCS_PROG_DATA |
261              BRW_NEW_TES_PROG_DATA |
262              BRW_NEW_VS_PROG_DATA,
263    },
264    .emit = brw_emit_l3_state
265 };
266 
267 /**
268  * Hack to restore the default L3 configuration.
269  *
270  * This will be called at the end of every batch in order to reset the L3
271  * configuration to the default values for the time being until the kernel is
272  * fixed.  Until kernel commit 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
273  * (included in v4.1) we would set the MI_RESTORE_INHIBIT bit when submitting
274  * batch buffers for the default context used by the DDX, which meant that any
275  * context state changed by the GL would leak into the DDX, the assumption
276  * being that the DDX would initialize any state it cares about manually.  The
277  * DDX is however not careful enough to program an L3 configuration
278  * explicitly, and it makes assumptions about it (URB size) which won't hold
279  * and cause it to misrender if we let our L3 set-up to leak into the DDX.
280  *
281  * Since v4.1 of the Linux kernel the default context is saved and restored
282  * normally, so it's far less likely for our L3 programming to interfere with
283  * other contexts -- In fact restoring the default L3 configuration at the end
284  * of the batch will be redundant most of the time.  A kind of state leak is
285  * still possible though if the context making assumptions about L3 state is
286  * created immediately after our context was active (e.g. without the DDX
287  * default context being scheduled in between) because at present the DRM
288  * doesn't fully initialize the contents of newly created contexts and instead
289  * sets the MI_RESTORE_INHIBIT flag causing it to inherit the state from the
290  * last active context.
291  *
292  * It's possible to realize such a scenario if, say, an X server (or a GL
293  * application using an outdated non-L3-aware Mesa version) is started while
294  * another GL application is running and happens to have modified the L3
295  * configuration, or if no X server is running at all and a GL application
296  * using a non-L3-aware Mesa version is started after another GL application
297  * ran and modified the L3 configuration -- The latter situation can actually
298  * be reproduced easily on IVB in our CI system.
299  */
300 void
gfx7_restore_default_l3_config(struct brw_context * brw)301 gfx7_restore_default_l3_config(struct brw_context *brw)
302 {
303    const struct intel_device_info *devinfo = &brw->screen->devinfo;
304    const struct intel_l3_config *const cfg = intel_get_default_l3_config(devinfo);
305 
306    if (cfg != brw->l3.config &&
307        can_do_pipelined_register_writes(brw->screen)) {
308       setup_l3_config(brw, cfg);
309       update_urb_size(brw, cfg);
310       brw->l3.config = cfg;
311    }
312 }
313