1//
2// Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3// Copyright (c) 2014, Red Hat Inc. All rights reserved.
4// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5//
6// This code is free software; you can redistribute it and/or modify it
7// under the terms of the GNU General Public License version 2 only, as
8// published by the Free Software Foundation.
9//
10// This code is distributed in the hope that it will be useful, but WITHOUT
11// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13// version 2 for more details (a copy is included in the LICENSE file that
14// accompanied this code).
15//
16// You should have received a copy of the GNU General Public License version
17// 2 along with this work; if not, write to the Free Software Foundation,
18// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19//
20// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21// or visit www.oracle.com if you need additional information or have any
22// questions.
23//
24//
25
26// AArch64 Bsd Architecture Description File
27
28//----------OS-DEPENDENT ENCODING BLOCK----------------------------------------
29// This block specifies the encoding classes used by the compiler to
30// output byte streams.  Encoding classes generate functions which are
31// called by Machine Instruction Nodes in order to generate the bit
32// encoding of the instruction.  Operands specify their base encoding
33// interface with the interface keyword.  There are currently
34// supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
35// COND_INTER.  REG_INTER causes an operand to generate a function
36// which returns its register number when queried.  CONST_INTER causes
37// an operand to generate a function which returns the value of the
38// constant when queried.  MEMORY_INTER causes an operand to generate
39// four functions which return the Base Register, the Index Register,
40// the Scale Value, and the Offset Value of the operand when queried.
41// COND_INTER causes an operand to generate six functions which return
42// the encoding code (ie - encoding bits for the instruction)
43// associated with each basic boolean condition for a conditional
44// instruction.  Instructions specify two basic values for encoding.
45// They use the ins_encode keyword to specify their encoding class
46// (which must be one of the class names specified in the encoding
47// block), and they use the opcode keyword to specify, in order, their
48// primary, secondary, and tertiary opcode.  Only the opcode sections
49// which a particular instruction needs for encoding need to be
50// specified.
51encode %{
52  // Build emit functions for each basic byte or larger field in the intel
53  // encoding scheme (opcode, rm, sib, immediate), and call them from C++
54  // code in the enc_class source block.  Emit functions will live in the
55  // main source block for now.  In future, we can generalize this by
56  // adding a syntax that specifies the sizes of fields in an order,
57  // so that the adlc can build the emit functions automagically
58
59  enc_class Java_To_Runtime(method meth) %{
60  %}
61
62%}
63
64
65// Platform dependent source
66
67source %{
68
69%}
70