1 /* 2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP 27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP 28 29 #include "runtime/abstract_vm_version.hpp" 30 #include "runtime/globals_extension.hpp" 31 #include "utilities/sizes.hpp" 32 33 class VM_Version : public Abstract_VM_Version { 34 friend class JVMCIVMStructs; 35 36 protected: 37 static int _cpu; 38 static int _model; 39 static int _model2; 40 static int _variant; 41 static int _revision; 42 static int _stepping; 43 static bool _dcpop; 44 struct PsrInfo { 45 uint32_t dczid_el0; 46 uint32_t ctr_el0; 47 }; 48 static PsrInfo _psr_info; 49 static void get_processor_features(); 50 #ifdef __FreeBSD__ 51 static unsigned long os_get_processor_features(); 52 #endif 53 54 public: 55 // Initialization 56 static void initialize(); 57 58 // Asserts assert_is_initialized()59 static void assert_is_initialized() { 60 } 61 expensive_load(int ld_size,int scale)62 static bool expensive_load(int ld_size, int scale) { 63 if (cpu_family() == CPU_ARM) { 64 // Half-word load with index shift by 1 (aka scale is 2) has 65 // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1]. 66 if (ld_size == 2 && scale == 2) { 67 return true; 68 } 69 } 70 return false; 71 } 72 73 // The CPU implementer codes can be found in 74 // ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile 75 // https://developer.arm.com/docs/ddi0487/latest 76 enum Family { 77 CPU_AMPERE = 0xC0, 78 CPU_ARM = 'A', 79 CPU_BROADCOM = 'B', 80 CPU_CAVIUM = 'C', 81 CPU_DEC = 'D', 82 CPU_HISILICON = 'H', 83 CPU_INFINEON = 'I', 84 CPU_MOTOROLA = 'M', 85 CPU_NVIDIA = 'N', 86 CPU_AMCC = 'P', 87 CPU_QUALCOM = 'Q', 88 CPU_MARVELL = 'V', 89 CPU_INTEL = 'i', 90 }; 91 92 enum Feature_Flag { 93 CPU_FP = (1<<0), 94 CPU_ASIMD = (1<<1), 95 CPU_EVTSTRM = (1<<2), 96 CPU_AES = (1<<3), 97 CPU_PMULL = (1<<4), 98 CPU_SHA1 = (1<<5), 99 CPU_SHA2 = (1<<6), 100 CPU_CRC32 = (1<<7), 101 CPU_LSE = (1<<8), 102 CPU_STXR_PREFETCH= (1 << 29), 103 CPU_A53MAC = (1 << 30), 104 CPU_DMB_ATOMICS = (1 << 31), 105 }; 106 cpu_family()107 static int cpu_family() { return _cpu; } cpu_model()108 static int cpu_model() { return _model; } cpu_model2()109 static int cpu_model2() { return _model2; } cpu_variant()110 static int cpu_variant() { return _variant; } cpu_revision()111 static int cpu_revision() { return _revision; } supports_dcpop()112 static bool supports_dcpop() { return _dcpop; } dczid_el0_offset()113 static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); } ctr_el0_offset()114 static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); } is_zva_enabled()115 static bool is_zva_enabled() { 116 // Check the DZP bit (bit 4) of dczid_el0 is zero 117 // and block size (bit 0~3) is not zero. 118 return ((_psr_info.dczid_el0 & 0x10) == 0 && 119 (_psr_info.dczid_el0 & 0xf) != 0); 120 } zva_length()121 static int zva_length() { 122 assert(is_zva_enabled(), "ZVA not available"); 123 return 4 << (_psr_info.dczid_el0 & 0xf); 124 } icache_line_size()125 static int icache_line_size() { 126 return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4; 127 } dcache_line_size()128 static int dcache_line_size() { 129 return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4; 130 } supports_fast_class_init_checks()131 static bool supports_fast_class_init_checks() { return true; } 132 }; 133 134 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP 135