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25 
26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
28 
29 #include "runtime/abstract_vm_version.hpp"
30 #include "utilities/sizes.hpp"
31 
32 class VM_Version : public Abstract_VM_Version {
33   friend class JVMCIVMStructs;
34 
35 protected:
36   static int _cpu;
37   static int _model;
38   static int _model2;
39   static int _variant;
40   static int _revision;
41   static int _stepping;
42 
43   static int _zva_length;
44   static int _dcache_line_size;
45   static int _icache_line_size;
46   static int _initial_sve_vector_length;
47 
48   // Read additional info using OS-specific interfaces
49   static void get_os_cpu_info();
50 
51   // Sets the SVE length and returns a new actual value or negative on error.
52   // If the len is larger than the system largest supported SVE vector length,
53   // the function sets the largest supported value.
54   static int set_and_get_current_sve_vector_length(int len);
55   static int get_current_sve_vector_length();
56 
57 public:
58   // Initialization
59   static void initialize();
60 
61   // Asserts
assert_is_initialized()62   static void assert_is_initialized() {
63   }
64 
expensive_load(int ld_size,int scale)65   static bool expensive_load(int ld_size, int scale) {
66     if (cpu_family() == CPU_ARM) {
67       // Half-word load with index shift by 1 (aka scale is 2) has
68       // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
69       if (ld_size == 2 && scale == 2) {
70         return true;
71       }
72     }
73     return false;
74   }
75 
76   // The CPU implementer codes can be found in
77   // ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
78   // https://developer.arm.com/docs/ddi0487/latest
79   enum Family {
80     CPU_AMPERE    = 0xC0,
81     CPU_ARM       = 'A',
82     CPU_BROADCOM  = 'B',
83     CPU_CAVIUM    = 'C',
84     CPU_DEC       = 'D',
85     CPU_HISILICON = 'H',
86     CPU_INFINEON  = 'I',
87     CPU_MOTOROLA  = 'M',
88     CPU_NVIDIA    = 'N',
89     CPU_AMCC      = 'P',
90     CPU_QUALCOM   = 'Q',
91     CPU_MARVELL   = 'V',
92     CPU_INTEL     = 'i',
93   };
94 
95   enum Feature_Flag {
96     CPU_FP           = (1<<0),
97     CPU_ASIMD        = (1<<1),
98     CPU_EVTSTRM      = (1<<2),
99     CPU_AES          = (1<<3),
100     CPU_PMULL        = (1<<4),
101     CPU_SHA1         = (1<<5),
102     CPU_SHA2         = (1<<6),
103     CPU_CRC32        = (1<<7),
104     CPU_LSE          = (1<<8),
105     CPU_DCPOP        = (1<<16),
106     CPU_SHA3         = (1<<17),
107     CPU_SHA512       = (1<<21),
108     CPU_SVE          = (1<<22),
109     // flags above must follow Linux HWCAP
110     CPU_SVE2         = (1<<28),
111     CPU_STXR_PREFETCH= (1<<29),
112     CPU_A53MAC       = (1<<30),
113   };
114 
cpu_family()115   static int cpu_family()                     { return _cpu; }
cpu_model()116   static int cpu_model()                      { return _model; }
cpu_model2()117   static int cpu_model2()                     { return _model2; }
cpu_variant()118   static int cpu_variant()                    { return _variant; }
cpu_revision()119   static int cpu_revision()                   { return _revision; }
120 
is_zva_enabled()121   static bool is_zva_enabled() { return 0 <= _zva_length; }
zva_length()122   static int zva_length() {
123     assert(is_zva_enabled(), "ZVA not available");
124     return _zva_length;
125   }
126 
icache_line_size()127   static int icache_line_size() { return _icache_line_size; }
dcache_line_size()128   static int dcache_line_size() { return _dcache_line_size; }
get_initial_sve_vector_length()129   static int get_initial_sve_vector_length()  { return _initial_sve_vector_length; };
130 
supports_fast_class_init_checks()131   static bool supports_fast_class_init_checks() { return true; }
supports_stack_watermark_barrier()132   constexpr static bool supports_stack_watermark_barrier() { return true; }
133 };
134 
135 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP
136