1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK2
7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK4
11 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
12 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK5
13 // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK6
14
15 // expected-no-diagnostics
16 #ifndef HEADER
17 #define HEADER
18
19 int a;
20
21 int foo(int *a);
22
main(int argc,char ** argv)23 int main(int argc, char **argv) {
24 #pragma omp target teams distribute parallel for map(tofrom:a) if(target:argc) schedule(static, a)
25 for (int i= 0; i < argc; ++i)
26 a = foo(&i) + foo(&a) + foo(&argc);
27 return 0;
28 }
29
30
31 #endif
32 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
33 // CHECK1-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
34 // CHECK1-NEXT: entry:
35 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
36 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
37 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
38 // CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
39 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
40 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
41 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
42 // CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
43 // CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
44 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
45 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
46 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
47 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
48 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
49 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 false)
50 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
51 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
52 // CHECK1: user_code.entry:
53 // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
54 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
55 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
56 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
57 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
58 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
59 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
60 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
61 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
62 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
63 // CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR3:[0-9]+]]
64 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 false)
65 // CHECK1-NEXT: ret void
66 // CHECK1: worker.exit:
67 // CHECK1-NEXT: ret void
68 //
69 //
70 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
71 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
72 // CHECK1-NEXT: entry:
73 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
74 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
75 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
76 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
77 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
78 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
79 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
80 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
81 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
82 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
83 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
84 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
85 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
86 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
87 // CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 4
88 // CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
89 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
90 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 8
91 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
92 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
93 // CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
94 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
95 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
96 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
97 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
98 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
99 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
100 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
101 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
102 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
103 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
104 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
105 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
106 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
107 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
108 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
109 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
110 // CHECK1: omp.precond.then:
111 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
112 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
113 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4
114 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
115 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
116 // CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
117 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
118 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
119 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
120 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
121 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
122 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
123 // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
124 // CHECK1: cond.true:
125 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
126 // CHECK1-NEXT: br label [[COND_END:%.*]]
127 // CHECK1: cond.false:
128 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
129 // CHECK1-NEXT: br label [[COND_END]]
130 // CHECK1: cond.end:
131 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
132 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
133 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
134 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
135 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
136 // CHECK1: omp.inner.for.cond:
137 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
138 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
139 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
140 // CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
141 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
142 // CHECK1: omp.inner.for.body:
143 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
144 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
145 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
146 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
147 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
148 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
149 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
150 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
151 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
152 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
153 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
154 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
155 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
156 // CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8*
157 // CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8
158 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
159 // CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8*
160 // CHECK1-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8
161 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
162 // CHECK1-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP19]] to i8*
163 // CHECK1-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 8
164 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
165 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i32* [[TMP0]] to i8*
166 // CHECK1-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 8
167 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
168 // CHECK1-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP21]] to i8*
169 // CHECK1-NEXT: store i8* [[TMP31]], i8** [[TMP30]], align 8
170 // CHECK1-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
171 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4
172 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
173 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP33]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i64, i64, i64, i32*, i64)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP34]], i64 5)
174 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
175 // CHECK1: omp.inner.for.inc:
176 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
177 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
178 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
179 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
180 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
181 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
182 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
183 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4
184 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
185 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
186 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP39]], [[TMP40]]
187 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4
188 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
189 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
190 // CHECK1-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP41]], [[TMP42]]
191 // CHECK1-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]]
192 // CHECK1: cond.true14:
193 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
194 // CHECK1-NEXT: br label [[COND_END16:%.*]]
195 // CHECK1: cond.false15:
196 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
197 // CHECK1-NEXT: br label [[COND_END16]]
198 // CHECK1: cond.end16:
199 // CHECK1-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP43]], [[COND_TRUE14]] ], [ [[TMP44]], [[COND_FALSE15]] ]
200 // CHECK1-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4
201 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
202 // CHECK1-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV]], align 4
203 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
204 // CHECK1: omp.inner.for.end:
205 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
206 // CHECK1: omp.loop.exit:
207 // CHECK1-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
208 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4
209 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP47]])
210 // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
211 // CHECK1: omp.precond.end:
212 // CHECK1-NEXT: ret void
213 //
214 //
215 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
216 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
217 // CHECK1-NEXT: entry:
218 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
219 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
220 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
221 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
222 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
223 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
224 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
225 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
226 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
227 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
228 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
229 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
230 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
231 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
232 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
233 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
234 // CHECK1-NEXT: [[I7:%.*]] = alloca i32, align 4
235 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
236 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
237 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
238 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
239 // CHECK1-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
240 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
241 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
242 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
243 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
244 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
245 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
246 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
247 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
248 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
249 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
250 // CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
251 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
252 // CHECK1-NEXT: store i32 0, i32* [[I]], align 4
253 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
254 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
255 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
256 // CHECK1: omp.precond.then:
257 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
258 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
259 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
260 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
261 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP5]] to i32
262 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
263 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP6]] to i32
264 // CHECK1-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
265 // CHECK1-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
266 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
267 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
268 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8
269 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
270 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
271 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
272 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
273 // CHECK1: omp.dispatch.cond:
274 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
275 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
276 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP11]] to i32
277 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP10]], [[CONV8]]
278 // CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
279 // CHECK1: cond.true:
280 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
281 // CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[TMP12]] to i32
282 // CHECK1-NEXT: br label [[COND_END:%.*]]
283 // CHECK1: cond.false:
284 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
285 // CHECK1-NEXT: br label [[COND_END]]
286 // CHECK1: cond.end:
287 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[CONV10]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
288 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
289 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
290 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
291 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
292 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
293 // CHECK1-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
294 // CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
295 // CHECK1: omp.dispatch.body:
296 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
297 // CHECK1: omp.inner.for.cond:
298 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
299 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
300 // CHECK1-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
301 // CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
302 // CHECK1: omp.inner.for.body:
303 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
304 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
305 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
306 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I7]], align 4
307 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I7]]) #[[ATTR4:[0-9]+]]
308 // CHECK1-NEXT: [[CALL13:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]]
309 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CALL]], [[CALL13]]
310 // CHECK1-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[CONV]]) #[[ATTR4]]
311 // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CALL15]]
312 // CHECK1-NEXT: store i32 [[ADD16]], i32* [[TMP0]], align 4
313 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
314 // CHECK1: omp.body.continue:
315 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
316 // CHECK1: omp.inner.for.inc:
317 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
318 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
319 // CHECK1-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
320 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
321 // CHECK1: omp.inner.for.end:
322 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
323 // CHECK1: omp.dispatch.inc:
324 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
325 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
326 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
327 // CHECK1-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_LB]], align 4
328 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
329 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
330 // CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]
331 // CHECK1-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_UB]], align 4
332 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
333 // CHECK1: omp.dispatch.end:
334 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
335 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
336 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]])
337 // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
338 // CHECK1: omp.precond.end:
339 // CHECK1-NEXT: ret void
340 //
341 //
342 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
343 // CHECK2-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
344 // CHECK2-NEXT: entry:
345 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
346 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
347 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
348 // CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
349 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
350 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
351 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
352 // CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
353 // CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
354 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
355 // CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
356 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
357 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 false)
358 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
359 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
360 // CHECK2: user_code.entry:
361 // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
362 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
363 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4
364 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4
365 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
366 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
367 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
368 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
369 // CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]]
370 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 false)
371 // CHECK2-NEXT: ret void
372 // CHECK2: worker.exit:
373 // CHECK2-NEXT: ret void
374 //
375 //
376 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
377 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
378 // CHECK2-NEXT: entry:
379 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
380 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
381 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
382 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
383 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
384 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
385 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
386 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
387 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
388 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
389 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
390 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
391 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
392 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
393 // CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4
394 // CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
395 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
396 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4
397 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
398 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
399 // CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
400 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
401 // CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
402 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
403 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
404 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
405 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
406 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
407 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
408 // CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
409 // CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
410 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
411 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
412 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
413 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
414 // CHECK2: omp.precond.then:
415 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
416 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
417 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4
418 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
419 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
420 // CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
421 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
422 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
423 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
424 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
425 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
426 // CHECK2-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
427 // CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
428 // CHECK2: cond.true:
429 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
430 // CHECK2-NEXT: br label [[COND_END:%.*]]
431 // CHECK2: cond.false:
432 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
433 // CHECK2-NEXT: br label [[COND_END]]
434 // CHECK2: cond.end:
435 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
436 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
437 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
438 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
439 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
440 // CHECK2: omp.inner.for.cond:
441 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
442 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
443 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
444 // CHECK2-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
445 // CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
446 // CHECK2: omp.inner.for.body:
447 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
448 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
449 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
450 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARGC_CASTED]], align 4
451 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4
452 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
453 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
454 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
455 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
456 // CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8*
457 // CHECK2-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4
458 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
459 // CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8*
460 // CHECK2-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4
461 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
462 // CHECK2-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8*
463 // CHECK2-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4
464 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
465 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i32* [[TMP0]] to i8*
466 // CHECK2-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4
467 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
468 // CHECK2-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8*
469 // CHECK2-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4
470 // CHECK2-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
471 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4
472 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
473 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, i32*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5)
474 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
475 // CHECK2: omp.inner.for.inc:
476 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
477 // CHECK2-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
478 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
479 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
480 // CHECK2-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
481 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
482 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
483 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4
484 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
485 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
486 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
487 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4
488 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
489 // CHECK2-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
490 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]]
491 // CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
492 // CHECK2: cond.true11:
493 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
494 // CHECK2-NEXT: br label [[COND_END13:%.*]]
495 // CHECK2: cond.false12:
496 // CHECK2-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
497 // CHECK2-NEXT: br label [[COND_END13]]
498 // CHECK2: cond.end13:
499 // CHECK2-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ]
500 // CHECK2-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4
501 // CHECK2-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
502 // CHECK2-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4
503 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
504 // CHECK2: omp.inner.for.end:
505 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
506 // CHECK2: omp.loop.exit:
507 // CHECK2-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
508 // CHECK2-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4
509 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]])
510 // CHECK2-NEXT: br label [[OMP_PRECOND_END]]
511 // CHECK2: omp.precond.end:
512 // CHECK2-NEXT: ret void
513 //
514 //
515 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
516 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
517 // CHECK2-NEXT: entry:
518 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
519 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
520 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
521 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
522 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
523 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
524 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
525 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
526 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
527 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
528 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
529 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
530 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
531 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
532 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
533 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
534 // CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4
535 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
536 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
537 // CHECK2-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
538 // CHECK2-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
539 // CHECK2-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
540 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
541 // CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
542 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
543 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
544 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
545 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
546 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
547 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
548 // CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
549 // CHECK2-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
550 // CHECK2-NEXT: store i32 0, i32* [[I]], align 4
551 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
552 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
553 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
554 // CHECK2: omp.precond.then:
555 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
556 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
557 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
558 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
559 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
560 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4
561 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
562 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
563 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
564 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
565 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
566 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
567 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
568 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
569 // CHECK2: omp.dispatch.cond:
570 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
571 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
572 // CHECK2-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
573 // CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
574 // CHECK2: cond.true:
575 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
576 // CHECK2-NEXT: br label [[COND_END:%.*]]
577 // CHECK2: cond.false:
578 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
579 // CHECK2-NEXT: br label [[COND_END]]
580 // CHECK2: cond.end:
581 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
582 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
583 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
584 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
585 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
586 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
587 // CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
588 // CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
589 // CHECK2: omp.dispatch.body:
590 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
591 // CHECK2: omp.inner.for.cond:
592 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
593 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
594 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
595 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
596 // CHECK2: omp.inner.for.body:
597 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
598 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
599 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
600 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4
601 // CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR4:[0-9]+]]
602 // CHECK2-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]]
603 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]]
604 // CHECK2-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR4]]
605 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
606 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4
607 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
608 // CHECK2: omp.body.continue:
609 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
610 // CHECK2: omp.inner.for.inc:
611 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
612 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1
613 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
614 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
615 // CHECK2: omp.inner.for.end:
616 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
617 // CHECK2: omp.dispatch.inc:
618 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
619 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
620 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
621 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4
622 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
623 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
624 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]
625 // CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4
626 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
627 // CHECK2: omp.dispatch.end:
628 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
629 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
630 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]])
631 // CHECK2-NEXT: br label [[OMP_PRECOND_END]]
632 // CHECK2: omp.precond.end:
633 // CHECK2-NEXT: ret void
634 //
635 //
636 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
637 // CHECK3-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
638 // CHECK3-NEXT: entry:
639 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
640 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
641 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
642 // CHECK3-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
643 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
644 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
645 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
646 // CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
647 // CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
648 // CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
649 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
650 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
651 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 false)
652 // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
653 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
654 // CHECK3: user_code.entry:
655 // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
656 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
657 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4
658 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4
659 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
660 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
661 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
662 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
663 // CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]]
664 // CHECK3-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 false)
665 // CHECK3-NEXT: ret void
666 // CHECK3: worker.exit:
667 // CHECK3-NEXT: ret void
668 //
669 //
670 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
671 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
672 // CHECK3-NEXT: entry:
673 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
674 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
675 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
676 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
677 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
678 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
679 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
680 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
681 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
682 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
683 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
684 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
685 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
686 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
687 // CHECK3-NEXT: [[I4:%.*]] = alloca i32, align 4
688 // CHECK3-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
689 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
690 // CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4
691 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
692 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
693 // CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
694 // CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
695 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
696 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
697 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
698 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
699 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
700 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
701 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
702 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
703 // CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
704 // CHECK3-NEXT: store i32 0, i32* [[I]], align 4
705 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
706 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
707 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
708 // CHECK3: omp.precond.then:
709 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
710 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
711 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4
712 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
713 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
714 // CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
715 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
716 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
717 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
718 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
719 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
720 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
721 // CHECK3-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
722 // CHECK3: cond.true:
723 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
724 // CHECK3-NEXT: br label [[COND_END:%.*]]
725 // CHECK3: cond.false:
726 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
727 // CHECK3-NEXT: br label [[COND_END]]
728 // CHECK3: cond.end:
729 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
730 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
731 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
732 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
733 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
734 // CHECK3: omp.inner.for.cond:
735 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
736 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
737 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
738 // CHECK3-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
739 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
740 // CHECK3: omp.inner.for.body:
741 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
742 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
743 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
744 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARGC_CASTED]], align 4
745 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4
746 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
747 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
748 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
749 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
750 // CHECK3-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8*
751 // CHECK3-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4
752 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
753 // CHECK3-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8*
754 // CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4
755 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
756 // CHECK3-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8*
757 // CHECK3-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4
758 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
759 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i32* [[TMP0]] to i8*
760 // CHECK3-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4
761 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
762 // CHECK3-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8*
763 // CHECK3-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4
764 // CHECK3-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
765 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4
766 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
767 // CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, i32*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5)
768 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
769 // CHECK3: omp.inner.for.inc:
770 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
771 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
772 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
773 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
774 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
775 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
776 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
777 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4
778 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
779 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
780 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
781 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4
782 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
783 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
784 // CHECK3-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]]
785 // CHECK3-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
786 // CHECK3: cond.true11:
787 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
788 // CHECK3-NEXT: br label [[COND_END13:%.*]]
789 // CHECK3: cond.false12:
790 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
791 // CHECK3-NEXT: br label [[COND_END13]]
792 // CHECK3: cond.end13:
793 // CHECK3-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ]
794 // CHECK3-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4
795 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
796 // CHECK3-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4
797 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
798 // CHECK3: omp.inner.for.end:
799 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
800 // CHECK3: omp.loop.exit:
801 // CHECK3-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
802 // CHECK3-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4
803 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]])
804 // CHECK3-NEXT: br label [[OMP_PRECOND_END]]
805 // CHECK3: omp.precond.end:
806 // CHECK3-NEXT: ret void
807 //
808 //
809 // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
810 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
811 // CHECK3-NEXT: entry:
812 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
813 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
814 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
815 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
816 // CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
817 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
818 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
819 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
820 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
821 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
822 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
823 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
824 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
825 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
826 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
827 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
828 // CHECK3-NEXT: [[I4:%.*]] = alloca i32, align 4
829 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
830 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
831 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
832 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
833 // CHECK3-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
834 // CHECK3-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
835 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
836 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
837 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
838 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
839 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
840 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
841 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
842 // CHECK3-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
843 // CHECK3-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
844 // CHECK3-NEXT: store i32 0, i32* [[I]], align 4
845 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
846 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
847 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
848 // CHECK3: omp.precond.then:
849 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
850 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
851 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
852 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
853 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
854 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4
855 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
856 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
857 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
858 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
859 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
860 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
861 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
862 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
863 // CHECK3: omp.dispatch.cond:
864 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
865 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
866 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
867 // CHECK3-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
868 // CHECK3: cond.true:
869 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
870 // CHECK3-NEXT: br label [[COND_END:%.*]]
871 // CHECK3: cond.false:
872 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
873 // CHECK3-NEXT: br label [[COND_END]]
874 // CHECK3: cond.end:
875 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
876 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
877 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
878 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
879 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
880 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
881 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
882 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
883 // CHECK3: omp.dispatch.body:
884 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
885 // CHECK3: omp.inner.for.cond:
886 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
887 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
888 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
889 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
890 // CHECK3: omp.inner.for.body:
891 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
892 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
893 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
894 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I4]], align 4
895 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR4:[0-9]+]]
896 // CHECK3-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]]
897 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]]
898 // CHECK3-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR4]]
899 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
900 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4
901 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
902 // CHECK3: omp.body.continue:
903 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
904 // CHECK3: omp.inner.for.inc:
905 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
906 // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1
907 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
908 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
909 // CHECK3: omp.inner.for.end:
910 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
911 // CHECK3: omp.dispatch.inc:
912 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
913 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
914 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
915 // CHECK3-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4
916 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
917 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
918 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]
919 // CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4
920 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
921 // CHECK3: omp.dispatch.end:
922 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
923 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
924 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]])
925 // CHECK3-NEXT: br label [[OMP_PRECOND_END]]
926 // CHECK3: omp.precond.end:
927 // CHECK3-NEXT: ret void
928 //
929 //
930 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
931 // CHECK4-SAME: (i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
932 // CHECK4-NEXT: entry:
933 // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
934 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
935 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
936 // CHECK4-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
937 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
938 // CHECK4-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
939 // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
940 // CHECK4-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
941 // CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
942 // CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
943 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
944 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
945 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
946 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
947 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 false)
948 // CHECK4-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
949 // CHECK4-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
950 // CHECK4: user_code.entry:
951 // CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
952 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
953 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
954 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
955 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
956 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
957 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
958 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
959 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
960 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
961 // CHECK4-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i64 [[TMP4]], i32* [[TMP0]], i64 [[TMP6]]) #[[ATTR3:[0-9]+]]
962 // CHECK4-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 false)
963 // CHECK4-NEXT: ret void
964 // CHECK4: worker.exit:
965 // CHECK4-NEXT: ret void
966 //
967 //
968 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
969 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
970 // CHECK4-NEXT: entry:
971 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
972 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
973 // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
974 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
975 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
976 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
977 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
978 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
979 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
980 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
981 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
982 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
983 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
984 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
985 // CHECK4-NEXT: [[I5:%.*]] = alloca i32, align 4
986 // CHECK4-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
987 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
988 // CHECK4-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 8
989 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
990 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
991 // CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
992 // CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
993 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
994 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
995 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
996 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
997 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
998 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
999 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1000 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1001 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1002 // CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
1003 // CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
1004 // CHECK4-NEXT: store i32 0, i32* [[I]], align 4
1005 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1006 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1007 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1008 // CHECK4: omp.precond.then:
1009 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1010 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1011 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4
1012 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1013 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1014 // CHECK4-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
1015 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1016 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
1017 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
1018 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1019 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1020 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
1021 // CHECK4-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1022 // CHECK4: cond.true:
1023 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1024 // CHECK4-NEXT: br label [[COND_END:%.*]]
1025 // CHECK4: cond.false:
1026 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1027 // CHECK4-NEXT: br label [[COND_END]]
1028 // CHECK4: cond.end:
1029 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1030 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1031 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1032 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
1033 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1034 // CHECK4: omp.inner.for.cond:
1035 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1036 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1037 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
1038 // CHECK4-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
1039 // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1040 // CHECK4: omp.inner.for.body:
1041 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1042 // CHECK4-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
1043 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1044 // CHECK4-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
1045 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
1046 // CHECK4-NEXT: [[CONV8:%.*]] = bitcast i64* [[ARGC_CASTED]] to i32*
1047 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
1048 // CHECK4-NEXT: [[TMP19:%.*]] = load i64, i64* [[ARGC_CASTED]], align 8
1049 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
1050 // CHECK4-NEXT: [[CONV9:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
1051 // CHECK4-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
1052 // CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
1053 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
1054 // CHECK4-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to i8*
1055 // CHECK4-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8
1056 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
1057 // CHECK4-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to i8*
1058 // CHECK4-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8
1059 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
1060 // CHECK4-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP19]] to i8*
1061 // CHECK4-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 8
1062 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
1063 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i32* [[TMP0]] to i8*
1064 // CHECK4-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 8
1065 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
1066 // CHECK4-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP21]] to i8*
1067 // CHECK4-NEXT: store i8* [[TMP31]], i8** [[TMP30]], align 8
1068 // CHECK4-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1069 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4
1070 // CHECK4-NEXT: [[TMP34:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1071 // CHECK4-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP33]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i64, i64, i64, i32*, i64)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP34]], i64 5)
1072 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1073 // CHECK4: omp.inner.for.inc:
1074 // CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1075 // CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1076 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
1077 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
1078 // CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1079 // CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1080 // CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
1081 // CHECK4-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_COMB_LB]], align 4
1082 // CHECK4-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1083 // CHECK4-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1084 // CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP39]], [[TMP40]]
1085 // CHECK4-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_COMB_UB]], align 4
1086 // CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1087 // CHECK4-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1088 // CHECK4-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP41]], [[TMP42]]
1089 // CHECK4-NEXT: br i1 [[CMP13]], label [[COND_TRUE14:%.*]], label [[COND_FALSE15:%.*]]
1090 // CHECK4: cond.true14:
1091 // CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1092 // CHECK4-NEXT: br label [[COND_END16:%.*]]
1093 // CHECK4: cond.false15:
1094 // CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1095 // CHECK4-NEXT: br label [[COND_END16]]
1096 // CHECK4: cond.end16:
1097 // CHECK4-NEXT: [[COND17:%.*]] = phi i32 [ [[TMP43]], [[COND_TRUE14]] ], [ [[TMP44]], [[COND_FALSE15]] ]
1098 // CHECK4-NEXT: store i32 [[COND17]], i32* [[DOTOMP_COMB_UB]], align 4
1099 // CHECK4-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1100 // CHECK4-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV]], align 4
1101 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
1102 // CHECK4: omp.inner.for.end:
1103 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1104 // CHECK4: omp.loop.exit:
1105 // CHECK4-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1106 // CHECK4-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4
1107 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP47]])
1108 // CHECK4-NEXT: br label [[OMP_PRECOND_END]]
1109 // CHECK4: omp.precond.end:
1110 // CHECK4-NEXT: ret void
1111 //
1112 //
1113 // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
1114 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
1115 // CHECK4-NEXT: entry:
1116 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1117 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1118 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1119 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1120 // CHECK4-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
1121 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8
1122 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1123 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1124 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1125 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1126 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
1127 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
1128 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1129 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1130 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1131 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1132 // CHECK4-NEXT: [[I7:%.*]] = alloca i32, align 4
1133 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1134 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1135 // CHECK4-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1136 // CHECK4-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1137 // CHECK4-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8
1138 // CHECK4-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8
1139 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1140 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32*
1141 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8
1142 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
1143 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1144 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1145 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1146 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1147 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1148 // CHECK4-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
1149 // CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_3]], align 4
1150 // CHECK4-NEXT: store i32 0, i32* [[I]], align 4
1151 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1152 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1153 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1154 // CHECK4: omp.precond.then:
1155 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1156 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1157 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
1158 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1159 // CHECK4-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP5]] to i32
1160 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1161 // CHECK4-NEXT: [[CONV6:%.*]] = trunc i64 [[TMP6]] to i32
1162 // CHECK4-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_LB]], align 4
1163 // CHECK4-NEXT: store i32 [[CONV6]], i32* [[DOTOMP_UB]], align 4
1164 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1165 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1166 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8
1167 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1168 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1169 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
1170 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1171 // CHECK4: omp.dispatch.cond:
1172 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1173 // CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1174 // CHECK4-NEXT: [[CONV8:%.*]] = trunc i64 [[TMP11]] to i32
1175 // CHECK4-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP10]], [[CONV8]]
1176 // CHECK4-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1177 // CHECK4: cond.true:
1178 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1179 // CHECK4-NEXT: [[CONV10:%.*]] = trunc i64 [[TMP12]] to i32
1180 // CHECK4-NEXT: br label [[COND_END:%.*]]
1181 // CHECK4: cond.false:
1182 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1183 // CHECK4-NEXT: br label [[COND_END]]
1184 // CHECK4: cond.end:
1185 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[CONV10]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1186 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1187 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1188 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
1189 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1190 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1191 // CHECK4-NEXT: [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1192 // CHECK4-NEXT: br i1 [[CMP11]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1193 // CHECK4: omp.dispatch.body:
1194 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1195 // CHECK4: omp.inner.for.cond:
1196 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1197 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1198 // CHECK4-NEXT: [[CMP12:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
1199 // CHECK4-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1200 // CHECK4: omp.inner.for.body:
1201 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1202 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
1203 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1204 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I7]], align 4
1205 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I7]]) #[[ATTR4:[0-9]+]]
1206 // CHECK4-NEXT: [[CALL13:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]]
1207 // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[CALL]], [[CALL13]]
1208 // CHECK4-NEXT: [[CALL15:%.*]] = call i32 @_Z3fooPi(i32* [[CONV]]) #[[ATTR4]]
1209 // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CALL15]]
1210 // CHECK4-NEXT: store i32 [[ADD16]], i32* [[TMP0]], align 4
1211 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1212 // CHECK4: omp.body.continue:
1213 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1214 // CHECK4: omp.inner.for.inc:
1215 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1216 // CHECK4-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
1217 // CHECK4-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
1218 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
1219 // CHECK4: omp.inner.for.end:
1220 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1221 // CHECK4: omp.dispatch.inc:
1222 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1223 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1224 // CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
1225 // CHECK4-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_LB]], align 4
1226 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1227 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1228 // CHECK4-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]
1229 // CHECK4-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_UB]], align 4
1230 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
1231 // CHECK4: omp.dispatch.end:
1232 // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1233 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1234 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]])
1235 // CHECK4-NEXT: br label [[OMP_PRECOND_END]]
1236 // CHECK4: omp.precond.end:
1237 // CHECK4-NEXT: ret void
1238 //
1239 //
1240 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
1241 // CHECK5-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
1242 // CHECK5-NEXT: entry:
1243 // CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1244 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
1245 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1246 // CHECK5-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
1247 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1248 // CHECK5-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1249 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1250 // CHECK5-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
1251 // CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1252 // CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
1253 // CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1254 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
1255 // CHECK5-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 false)
1256 // CHECK5-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1257 // CHECK5-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1258 // CHECK5: user_code.entry:
1259 // CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
1260 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1261 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4
1262 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4
1263 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1264 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1265 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1266 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
1267 // CHECK5-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]]
1268 // CHECK5-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 false)
1269 // CHECK5-NEXT: ret void
1270 // CHECK5: worker.exit:
1271 // CHECK5-NEXT: ret void
1272 //
1273 //
1274 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
1275 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
1276 // CHECK5-NEXT: entry:
1277 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1278 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1279 // CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1280 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
1281 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1282 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1283 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1284 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1285 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1286 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1287 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1288 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1289 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1290 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1291 // CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4
1292 // CHECK5-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
1293 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1294 // CHECK5-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4
1295 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1296 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1297 // CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1298 // CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
1299 // CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1300 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
1301 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1302 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
1303 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1304 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1305 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1306 // CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
1307 // CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1308 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4
1309 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1310 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1311 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1312 // CHECK5: omp.precond.then:
1313 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1314 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1315 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4
1316 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1317 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1318 // CHECK5-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
1319 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1320 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
1321 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
1322 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1323 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1324 // CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
1325 // CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1326 // CHECK5: cond.true:
1327 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1328 // CHECK5-NEXT: br label [[COND_END:%.*]]
1329 // CHECK5: cond.false:
1330 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1331 // CHECK5-NEXT: br label [[COND_END]]
1332 // CHECK5: cond.end:
1333 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1334 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1335 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1336 // CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
1337 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1338 // CHECK5: omp.inner.for.cond:
1339 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1340 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1341 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
1342 // CHECK5-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
1343 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1344 // CHECK5: omp.inner.for.body:
1345 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1346 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1347 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1348 // CHECK5-NEXT: store i32 [[TMP16]], i32* [[ARGC_CASTED]], align 4
1349 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4
1350 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1351 // CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1352 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1353 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
1354 // CHECK5-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8*
1355 // CHECK5-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4
1356 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
1357 // CHECK5-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8*
1358 // CHECK5-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4
1359 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
1360 // CHECK5-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8*
1361 // CHECK5-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4
1362 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
1363 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast i32* [[TMP0]] to i8*
1364 // CHECK5-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4
1365 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
1366 // CHECK5-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8*
1367 // CHECK5-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4
1368 // CHECK5-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1369 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4
1370 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1371 // CHECK5-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, i32*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5)
1372 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1373 // CHECK5: omp.inner.for.inc:
1374 // CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1375 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1376 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
1377 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
1378 // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1379 // CHECK5-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1380 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
1381 // CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4
1382 // CHECK5-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1383 // CHECK5-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1384 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
1385 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4
1386 // CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1387 // CHECK5-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1388 // CHECK5-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]]
1389 // CHECK5-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
1390 // CHECK5: cond.true11:
1391 // CHECK5-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1392 // CHECK5-NEXT: br label [[COND_END13:%.*]]
1393 // CHECK5: cond.false12:
1394 // CHECK5-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1395 // CHECK5-NEXT: br label [[COND_END13]]
1396 // CHECK5: cond.end13:
1397 // CHECK5-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ]
1398 // CHECK5-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4
1399 // CHECK5-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1400 // CHECK5-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4
1401 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1402 // CHECK5: omp.inner.for.end:
1403 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1404 // CHECK5: omp.loop.exit:
1405 // CHECK5-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1406 // CHECK5-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4
1407 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]])
1408 // CHECK5-NEXT: br label [[OMP_PRECOND_END]]
1409 // CHECK5: omp.precond.end:
1410 // CHECK5-NEXT: ret void
1411 //
1412 //
1413 // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1
1414 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
1415 // CHECK5-NEXT: entry:
1416 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1417 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1418 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1419 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1420 // CHECK5-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1421 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
1422 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1423 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1424 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1425 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1426 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1427 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1428 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1429 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1430 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1431 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1432 // CHECK5-NEXT: [[I4:%.*]] = alloca i32, align 4
1433 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1434 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1435 // CHECK5-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1436 // CHECK5-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1437 // CHECK5-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1438 // CHECK5-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
1439 // CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1440 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
1441 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1442 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
1443 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1444 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1445 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1446 // CHECK5-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
1447 // CHECK5-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1448 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4
1449 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1450 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1451 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1452 // CHECK5: omp.precond.then:
1453 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1454 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1455 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
1456 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1457 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1458 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4
1459 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
1460 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1461 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1462 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1463 // CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1464 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1465 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
1466 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1467 // CHECK5: omp.dispatch.cond:
1468 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1469 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1470 // CHECK5-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
1471 // CHECK5-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1472 // CHECK5: cond.true:
1473 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1474 // CHECK5-NEXT: br label [[COND_END:%.*]]
1475 // CHECK5: cond.false:
1476 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1477 // CHECK5-NEXT: br label [[COND_END]]
1478 // CHECK5: cond.end:
1479 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1480 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1481 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1482 // CHECK5-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
1483 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1484 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1485 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1486 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1487 // CHECK5: omp.dispatch.body:
1488 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1489 // CHECK5: omp.inner.for.cond:
1490 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1491 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1492 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
1493 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1494 // CHECK5: omp.inner.for.body:
1495 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1496 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
1497 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1498 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I4]], align 4
1499 // CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR4:[0-9]+]]
1500 // CHECK5-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]]
1501 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]]
1502 // CHECK5-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR4]]
1503 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
1504 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4
1505 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1506 // CHECK5: omp.body.continue:
1507 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1508 // CHECK5: omp.inner.for.inc:
1509 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1510 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1
1511 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
1512 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1513 // CHECK5: omp.inner.for.end:
1514 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1515 // CHECK5: omp.dispatch.inc:
1516 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1517 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1518 // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
1519 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4
1520 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1521 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1522 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]
1523 // CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4
1524 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
1525 // CHECK5: omp.dispatch.end:
1526 // CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1527 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1528 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]])
1529 // CHECK5-NEXT: br label [[OMP_PRECOND_END]]
1530 // CHECK5: omp.precond.end:
1531 // CHECK5-NEXT: ret void
1532 //
1533 //
1534 // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24
1535 // CHECK6-SAME: (i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
1536 // CHECK6-NEXT: entry:
1537 // CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1538 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
1539 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1540 // CHECK6-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
1541 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1542 // CHECK6-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1543 // CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1544 // CHECK6-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
1545 // CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1546 // CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
1547 // CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1548 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
1549 // CHECK6-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 false)
1550 // CHECK6-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1551 // CHECK6-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1552 // CHECK6: user_code.entry:
1553 // CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]])
1554 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1555 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[ARGC_CASTED]], align 4
1556 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4
1557 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1558 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1559 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1560 // CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTTHREADID_TEMP_]], align 4
1561 // CHECK6-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]], i32 [[TMP4]], i32* [[TMP0]], i32 [[TMP6]]) #[[ATTR3:[0-9]+]]
1562 // CHECK6-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i1 true, i1 false)
1563 // CHECK6-NEXT: ret void
1564 // CHECK6: worker.exit:
1565 // CHECK6-NEXT: ret void
1566 //
1567 //
1568 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
1569 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
1570 // CHECK6-NEXT: entry:
1571 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1572 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1573 // CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1574 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
1575 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1576 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1577 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
1578 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1579 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1580 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
1581 // CHECK6-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1582 // CHECK6-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1583 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1584 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1585 // CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4
1586 // CHECK6-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4
1587 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1588 // CHECK6-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x i8*], align 4
1589 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1590 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1591 // CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1592 // CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
1593 // CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1594 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
1595 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1596 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
1597 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1598 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1599 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1600 // CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
1601 // CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1602 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4
1603 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1604 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1605 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1606 // CHECK6: omp.precond.then:
1607 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1608 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1609 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4
1610 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1611 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1612 // CHECK6-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
1613 // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1614 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
1615 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
1616 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1617 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1618 // CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
1619 // CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1620 // CHECK6: cond.true:
1621 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1622 // CHECK6-NEXT: br label [[COND_END:%.*]]
1623 // CHECK6: cond.false:
1624 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1625 // CHECK6-NEXT: br label [[COND_END]]
1626 // CHECK6: cond.end:
1627 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1628 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1629 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1630 // CHECK6-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
1631 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1632 // CHECK6: omp.inner.for.cond:
1633 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1634 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1635 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
1636 // CHECK6-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
1637 // CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1638 // CHECK6: omp.inner.for.body:
1639 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1640 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1641 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1642 // CHECK6-NEXT: store i32 [[TMP16]], i32* [[ARGC_CASTED]], align 4
1643 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARGC_CASTED]], align 4
1644 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1645 // CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1646 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1647 // CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
1648 // CHECK6-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to i8*
1649 // CHECK6-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 4
1650 // CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
1651 // CHECK6-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to i8*
1652 // CHECK6-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 4
1653 // CHECK6-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
1654 // CHECK6-NEXT: [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to i8*
1655 // CHECK6-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 4
1656 // CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
1657 // CHECK6-NEXT: [[TMP27:%.*]] = bitcast i32* [[TMP0]] to i8*
1658 // CHECK6-NEXT: store i8* [[TMP27]], i8** [[TMP26]], align 4
1659 // CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
1660 // CHECK6-NEXT: [[TMP29:%.*]] = inttoptr i32 [[TMP19]] to i8*
1661 // CHECK6-NEXT: store i8* [[TMP29]], i8** [[TMP28]], align 4
1662 // CHECK6-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1663 // CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4
1664 // CHECK6-NEXT: [[TMP32:%.*]] = bitcast [5 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1665 // CHECK6-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32, i32, i32, i32*, i32)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP32]], i32 5)
1666 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1667 // CHECK6: omp.inner.for.inc:
1668 // CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1669 // CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1670 // CHECK6-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
1671 // CHECK6-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
1672 // CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1673 // CHECK6-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1674 // CHECK6-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
1675 // CHECK6-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_COMB_LB]], align 4
1676 // CHECK6-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1677 // CHECK6-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1678 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
1679 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_COMB_UB]], align 4
1680 // CHECK6-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1681 // CHECK6-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1682 // CHECK6-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]]
1683 // CHECK6-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
1684 // CHECK6: cond.true11:
1685 // CHECK6-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1686 // CHECK6-NEXT: br label [[COND_END13:%.*]]
1687 // CHECK6: cond.false12:
1688 // CHECK6-NEXT: [[TMP42:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1689 // CHECK6-NEXT: br label [[COND_END13]]
1690 // CHECK6: cond.end13:
1691 // CHECK6-NEXT: [[COND14:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE11]] ], [ [[TMP42]], [[COND_FALSE12]] ]
1692 // CHECK6-NEXT: store i32 [[COND14]], i32* [[DOTOMP_COMB_UB]], align 4
1693 // CHECK6-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1694 // CHECK6-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV]], align 4
1695 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]
1696 // CHECK6: omp.inner.for.end:
1697 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1698 // CHECK6: omp.loop.exit:
1699 // CHECK6-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1700 // CHECK6-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4
1701 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP45]])
1702 // CHECK6-NEXT: br label [[OMP_PRECOND_END]]
1703 // CHECK6: omp.precond.end:
1704 // CHECK6-NEXT: ret void
1705 //
1706 //
1707 // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1
1708 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[ARGC:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
1709 // CHECK6-NEXT: entry:
1710 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1711 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1712 // CHECK6-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1713 // CHECK6-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1714 // CHECK6-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1715 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4
1716 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1717 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1718 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
1719 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1720 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1721 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
1722 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1723 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1724 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1725 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1726 // CHECK6-NEXT: [[I4:%.*]] = alloca i32, align 4
1727 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1728 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1729 // CHECK6-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1730 // CHECK6-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1731 // CHECK6-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4
1732 // CHECK6-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4
1733 // CHECK6-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1734 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4
1735 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4
1736 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
1737 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1738 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1739 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1740 // CHECK6-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1
1741 // CHECK6-NEXT: store i32 [[SUB3]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1742 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4
1743 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1744 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1745 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1746 // CHECK6: omp.precond.then:
1747 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1748 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1749 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
1750 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1751 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1752 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4
1753 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4
1754 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1755 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1756 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1757 // CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1758 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1759 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP7]])
1760 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1761 // CHECK6: omp.dispatch.cond:
1762 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1763 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1764 // CHECK6-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
1765 // CHECK6-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1766 // CHECK6: cond.true:
1767 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1768 // CHECK6-NEXT: br label [[COND_END:%.*]]
1769 // CHECK6: cond.false:
1770 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1771 // CHECK6-NEXT: br label [[COND_END]]
1772 // CHECK6: cond.end:
1773 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1774 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1775 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1776 // CHECK6-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
1777 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1778 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1779 // CHECK6-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1780 // CHECK6-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1781 // CHECK6: omp.dispatch.body:
1782 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1783 // CHECK6: omp.inner.for.cond:
1784 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1785 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1786 // CHECK6-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
1787 // CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1788 // CHECK6: omp.inner.for.body:
1789 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1790 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
1791 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1792 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I4]], align 4
1793 // CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3fooPi(i32* [[I4]]) #[[ATTR4:[0-9]+]]
1794 // CHECK6-NEXT: [[CALL8:%.*]] = call i32 @_Z3fooPi(i32* [[TMP0]]) #[[ATTR4]]
1795 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[CALL]], [[CALL8]]
1796 // CHECK6-NEXT: [[CALL10:%.*]] = call i32 @_Z3fooPi(i32* [[ARGC_ADDR]]) #[[ATTR4]]
1797 // CHECK6-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
1798 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[TMP0]], align 4
1799 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1800 // CHECK6: omp.body.continue:
1801 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1802 // CHECK6: omp.inner.for.inc:
1803 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1804 // CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP20]], 1
1805 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
1806 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]]
1807 // CHECK6: omp.inner.for.end:
1808 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1809 // CHECK6: omp.dispatch.inc:
1810 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1811 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1812 // CHECK6-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
1813 // CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_LB]], align 4
1814 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1815 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1816 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]
1817 // CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_UB]], align 4
1818 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
1819 // CHECK6: omp.dispatch.end:
1820 // CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1821 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1822 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP26]])
1823 // CHECK6-NEXT: br label [[OMP_PRECOND_END]]
1824 // CHECK6: omp.precond.end:
1825 // CHECK6-NEXT: ret void
1826 //
1827