1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10
19
20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute parallel for private(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
main()71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute parallel for private(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global, bound tid and loop vars
80
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84
85 // Skip global, bound tid and loop vars
86 [&]() {
87 g = 2;
88 g1 = 2;
89 sivar = 4;
90
91 }();
92 }
93 }();
94 return 0;
95 #else
96 #pragma omp target
97 #pragma omp teams distribute parallel for private(t_var, vec, s_arr, var, sivar)
98 for (int i = 0; i < 2; ++i) {
99 vec[i] = t_var;
100 s_arr[i] = var;
101 sivar += i;
102 }
103 return tmain<int>();
104 #endif
105 }
106
107
108
109 // Skip global, bound tid and loop vars
110
111 // private(s_arr)
112
113 // private(var)
114
115
116 // Skip global, bound tid and loop vars
117
118 // private(s_arr)
119
120 // private(var)
121
122
123
124
125 // Skip global, bound tid and loop vars
126
127 // private(s_arr)
128
129
130 // private(var)
131
132
133 // Skip global, bound tid and loop vars
134 // prev lb and ub
135 // iter variables
136
137 // private(s_arr)
138
139
140 // private(var)
141
142
143
144 #endif
145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
147 // CHECK1-NEXT: entry:
148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
150 // CHECK1-NEXT: ret void
151 //
152 //
153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
154 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
155 // CHECK1-NEXT: entry:
156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
157 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
158 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
160 // CHECK1-NEXT: ret void
161 //
162 //
163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
164 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
165 // CHECK1-NEXT: entry:
166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
170 // CHECK1-NEXT: ret void
171 //
172 //
173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
174 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
175 // CHECK1-NEXT: entry:
176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
177 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
178 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
182 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
183 // CHECK1-NEXT: ret void
184 //
185 //
186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
187 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
188 // CHECK1-NEXT: entry:
189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
191 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
192 // CHECK1-NEXT: ret void
193 //
194 //
195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
196 // CHECK1-SAME: () #[[ATTR0]] {
197 // CHECK1-NEXT: entry:
198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
201 // CHECK1-NEXT: ret void
202 //
203 //
204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
205 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
206 // CHECK1-NEXT: entry:
207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
209 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
210 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
211 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
214 // CHECK1-NEXT: ret void
215 //
216 //
217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
218 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
219 // CHECK1-NEXT: entry:
220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
221 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
223 // CHECK1: arraydestroy.body:
224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
229 // CHECK1: arraydestroy.done1:
230 // CHECK1-NEXT: ret void
231 //
232 //
233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
234 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
235 // CHECK1-NEXT: entry:
236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
238 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
239 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
240 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
246 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
247 // CHECK1-NEXT: ret void
248 //
249 //
250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
251 // CHECK1-SAME: () #[[ATTR0]] {
252 // CHECK1-NEXT: entry:
253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
255 // CHECK1-NEXT: ret void
256 //
257 //
258 // CHECK1-LABEL: define {{[^@]+}}@main
259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
260 // CHECK1-NEXT: entry:
261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
262 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
263 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
264 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
265 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
266 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
267 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
268 // CHECK1: omp_offload.failed:
269 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]]
270 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
271 // CHECK1: omp_offload.cont:
272 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
273 // CHECK1-NEXT: ret i32 [[CALL]]
274 //
275 //
276 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96
277 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
278 // CHECK1-NEXT: entry:
279 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
280 // CHECK1-NEXT: ret void
281 //
282 //
283 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
284 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
285 // CHECK1-NEXT: entry:
286 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
287 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
288 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
289 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
290 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
291 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
292 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
293 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
294 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
295 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
296 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
297 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
298 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
299 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
300 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
301 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
302 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
303 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
304 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
305 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
306 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
307 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
308 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
309 // CHECK1: arrayctor.loop:
310 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
311 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
312 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
313 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
314 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
315 // CHECK1: arrayctor.cont:
316 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
317 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
318 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
319 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
320 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
321 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
322 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
323 // CHECK1: cond.true:
324 // CHECK1-NEXT: br label [[COND_END:%.*]]
325 // CHECK1: cond.false:
326 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
327 // CHECK1-NEXT: br label [[COND_END]]
328 // CHECK1: cond.end:
329 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
330 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
331 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
332 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
333 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
334 // CHECK1: omp.inner.for.cond:
335 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
336 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
337 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
338 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
339 // CHECK1: omp.inner.for.cond.cleanup:
340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
341 // CHECK1: omp.inner.for.body:
342 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
343 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
344 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
345 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
346 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
347 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
348 // CHECK1: omp.inner.for.inc:
349 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
350 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
351 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
352 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
353 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
354 // CHECK1: omp.inner.for.end:
355 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
356 // CHECK1: omp.loop.exit:
357 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
358 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
359 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
360 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
361 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
362 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2
363 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
364 // CHECK1: arraydestroy.body:
365 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
366 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
367 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
368 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
369 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
370 // CHECK1: arraydestroy.done3:
371 // CHECK1-NEXT: ret void
372 //
373 //
374 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
375 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
376 // CHECK1-NEXT: entry:
377 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
378 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
379 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
380 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
381 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
382 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
383 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
384 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
385 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
386 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
387 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
388 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
389 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
390 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
391 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
392 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
393 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
394 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
395 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
396 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
398 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
399 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
400 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
401 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
402 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
403 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
404 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
405 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
406 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
407 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
408 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
409 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
410 // CHECK1: arrayctor.loop:
411 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
412 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
413 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
414 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
415 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
416 // CHECK1: arrayctor.cont:
417 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
418 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
419 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
420 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
421 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
422 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
423 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
424 // CHECK1: cond.true:
425 // CHECK1-NEXT: br label [[COND_END:%.*]]
426 // CHECK1: cond.false:
427 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
428 // CHECK1-NEXT: br label [[COND_END]]
429 // CHECK1: cond.end:
430 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
431 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
432 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
433 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
434 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
435 // CHECK1: omp.inner.for.cond:
436 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
437 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
438 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
439 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
440 // CHECK1: omp.inner.for.cond.cleanup:
441 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
442 // CHECK1: omp.inner.for.body:
443 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
444 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
445 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
446 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
447 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
448 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
449 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
450 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
451 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
452 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
453 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
454 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
455 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8*
456 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
457 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false)
458 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
459 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4
460 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
461 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4
462 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
463 // CHECK1: omp.body.continue:
464 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
465 // CHECK1: omp.inner.for.inc:
466 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
467 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
468 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
470 // CHECK1: omp.inner.for.end:
471 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
472 // CHECK1: omp.loop.exit:
473 // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
474 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
475 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
476 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
477 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
478 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2
479 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
480 // CHECK1: arraydestroy.body:
481 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
482 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
483 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
484 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
485 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
486 // CHECK1: arraydestroy.done8:
487 // CHECK1-NEXT: ret void
488 //
489 //
490 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
491 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
492 // CHECK1-NEXT: entry:
493 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
494 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
495 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
496 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
497 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
498 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
499 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
500 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
501 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
502 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
503 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
504 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
505 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
506 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
507 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
508 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
509 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
510 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
511 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
512 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
513 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
514 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
515 // CHECK1: omp_offload.failed:
516 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
517 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
518 // CHECK1: omp_offload.cont:
519 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
520 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
521 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
522 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
523 // CHECK1: arraydestroy.body:
524 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
525 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
526 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
527 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
528 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
529 // CHECK1: arraydestroy.done2:
530 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
531 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
532 // CHECK1-NEXT: ret i32 [[TMP4]]
533 //
534 //
535 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
536 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
537 // CHECK1-NEXT: entry:
538 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
539 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
540 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
541 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
542 // CHECK1-NEXT: ret void
543 //
544 //
545 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
546 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
547 // CHECK1-NEXT: entry:
548 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
549 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
550 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
551 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
552 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
553 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
554 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
555 // CHECK1-NEXT: ret void
556 //
557 //
558 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
559 // CHECK1-SAME: () #[[ATTR4]] {
560 // CHECK1-NEXT: entry:
561 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
562 // CHECK1-NEXT: ret void
563 //
564 //
565 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
566 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
567 // CHECK1-NEXT: entry:
568 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
569 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
570 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
571 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
572 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
573 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
574 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
575 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
576 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
577 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
578 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
579 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
580 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
581 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
582 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
583 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
584 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
585 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
586 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
587 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
588 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
589 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
590 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
591 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
592 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
593 // CHECK1: arrayctor.loop:
594 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
595 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
596 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
597 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
598 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
599 // CHECK1: arrayctor.cont:
600 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
601 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
602 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
603 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
604 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
605 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
606 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
607 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
608 // CHECK1: cond.true:
609 // CHECK1-NEXT: br label [[COND_END:%.*]]
610 // CHECK1: cond.false:
611 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
612 // CHECK1-NEXT: br label [[COND_END]]
613 // CHECK1: cond.end:
614 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
615 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
616 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
617 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
618 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
619 // CHECK1: omp.inner.for.cond:
620 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
621 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
622 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
623 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
624 // CHECK1: omp.inner.for.cond.cleanup:
625 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
626 // CHECK1: omp.inner.for.body:
627 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
628 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
629 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
630 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
631 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
632 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
633 // CHECK1: omp.inner.for.inc:
634 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
635 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
636 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
637 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
638 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
639 // CHECK1: omp.inner.for.end:
640 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
641 // CHECK1: omp.loop.exit:
642 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
643 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
644 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
645 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
646 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
647 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2
648 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
649 // CHECK1: arraydestroy.body:
650 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
651 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
652 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
653 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
654 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
655 // CHECK1: arraydestroy.done5:
656 // CHECK1-NEXT: ret void
657 //
658 //
659 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
660 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
661 // CHECK1-NEXT: entry:
662 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
663 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
664 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
665 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
666 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
667 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
668 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
669 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
670 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
671 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
672 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
673 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
674 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
675 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
676 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
677 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8
678 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
679 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
680 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
681 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
682 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
683 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
684 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
685 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
686 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
687 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
688 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
689 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
690 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
691 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
692 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
693 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
694 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
695 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
696 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
697 // CHECK1: arrayctor.loop:
698 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
699 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
700 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
701 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
702 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
703 // CHECK1: arrayctor.cont:
704 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
705 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8
706 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
707 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
708 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
709 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
710 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
711 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
712 // CHECK1: cond.true:
713 // CHECK1-NEXT: br label [[COND_END:%.*]]
714 // CHECK1: cond.false:
715 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
716 // CHECK1-NEXT: br label [[COND_END]]
717 // CHECK1: cond.end:
718 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
719 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
720 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
721 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
722 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
723 // CHECK1: omp.inner.for.cond:
724 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
725 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
726 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
727 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
728 // CHECK1: omp.inner.for.cond.cleanup:
729 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
730 // CHECK1: omp.inner.for.body:
731 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
732 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
733 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
734 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
735 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
736 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
737 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
738 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
739 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
740 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8
741 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
742 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
743 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]]
744 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8*
745 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
746 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)
747 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
748 // CHECK1: omp.body.continue:
749 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
750 // CHECK1: omp.inner.for.inc:
751 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
752 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
753 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
754 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
755 // CHECK1: omp.inner.for.end:
756 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
757 // CHECK1: omp.loop.exit:
758 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
759 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
760 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
761 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
762 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
763 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2
764 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
765 // CHECK1: arraydestroy.body:
766 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
767 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
768 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
769 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
770 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
771 // CHECK1: arraydestroy.done9:
772 // CHECK1-NEXT: ret void
773 //
774 //
775 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
776 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
777 // CHECK1-NEXT: entry:
778 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
779 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
780 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
781 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
782 // CHECK1-NEXT: ret void
783 //
784 //
785 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
786 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
787 // CHECK1-NEXT: entry:
788 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
789 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
790 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
791 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
792 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
793 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
794 // CHECK1-NEXT: ret void
795 //
796 //
797 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
798 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
799 // CHECK1-NEXT: entry:
800 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
801 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
802 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
803 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
804 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
805 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
806 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
807 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
808 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
809 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
810 // CHECK1-NEXT: ret void
811 //
812 //
813 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
814 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
815 // CHECK1-NEXT: entry:
816 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
817 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
818 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
819 // CHECK1-NEXT: ret void
820 //
821 //
822 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp
823 // CHECK1-SAME: () #[[ATTR0]] {
824 // CHECK1-NEXT: entry:
825 // CHECK1-NEXT: call void @__cxx_global_var_init()
826 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
827 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
828 // CHECK1-NEXT: ret void
829 //
830 //
831 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
832 // CHECK1-SAME: () #[[ATTR0]] {
833 // CHECK1-NEXT: entry:
834 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
835 // CHECK1-NEXT: ret void
836 //
837 //
838 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
839 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
840 // CHECK2-NEXT: entry:
841 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
842 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
843 // CHECK2-NEXT: ret void
844 //
845 //
846 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
847 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
848 // CHECK2-NEXT: entry:
849 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
850 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
851 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
852 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
853 // CHECK2-NEXT: ret void
854 //
855 //
856 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
857 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
858 // CHECK2-NEXT: entry:
859 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
860 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
861 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
862 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
863 // CHECK2-NEXT: ret void
864 //
865 //
866 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
867 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
868 // CHECK2-NEXT: entry:
869 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
870 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
871 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
872 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
873 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
874 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
875 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4
876 // CHECK2-NEXT: ret void
877 //
878 //
879 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
880 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
881 // CHECK2-NEXT: entry:
882 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
883 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
884 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
885 // CHECK2-NEXT: ret void
886 //
887 //
888 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
889 // CHECK2-SAME: () #[[ATTR0]] {
890 // CHECK2-NEXT: entry:
891 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
892 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
893 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
894 // CHECK2-NEXT: ret void
895 //
896 //
897 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
898 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
899 // CHECK2-NEXT: entry:
900 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
901 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
902 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
903 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
904 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
905 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
906 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
907 // CHECK2-NEXT: ret void
908 //
909 //
910 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
911 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
912 // CHECK2-NEXT: entry:
913 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
914 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
915 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
916 // CHECK2: arraydestroy.body:
917 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
918 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
919 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
920 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
921 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
922 // CHECK2: arraydestroy.done1:
923 // CHECK2-NEXT: ret void
924 //
925 //
926 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
927 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
928 // CHECK2-NEXT: entry:
929 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
930 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
931 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
932 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
933 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
934 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
935 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
936 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
937 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
938 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
939 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
940 // CHECK2-NEXT: ret void
941 //
942 //
943 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
944 // CHECK2-SAME: () #[[ATTR0]] {
945 // CHECK2-NEXT: entry:
946 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
947 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
948 // CHECK2-NEXT: ret void
949 //
950 //
951 // CHECK2-LABEL: define {{[^@]+}}@main
952 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
953 // CHECK2-NEXT: entry:
954 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
955 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
956 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
957 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
958 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
959 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
960 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
961 // CHECK2: omp_offload.failed:
962 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]]
963 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
964 // CHECK2: omp_offload.cont:
965 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
966 // CHECK2-NEXT: ret i32 [[CALL]]
967 //
968 //
969 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96
970 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
971 // CHECK2-NEXT: entry:
972 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
973 // CHECK2-NEXT: ret void
974 //
975 //
976 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
977 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
978 // CHECK2-NEXT: entry:
979 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
980 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
981 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
982 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
983 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
984 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
985 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
986 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
987 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
988 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
989 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
990 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
991 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
992 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
993 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
994 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
995 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
996 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
997 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
998 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
999 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1000 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1001 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1002 // CHECK2: arrayctor.loop:
1003 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1004 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1005 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1006 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1007 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1008 // CHECK2: arrayctor.cont:
1009 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1010 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1011 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1012 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1013 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1014 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1015 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1016 // CHECK2: cond.true:
1017 // CHECK2-NEXT: br label [[COND_END:%.*]]
1018 // CHECK2: cond.false:
1019 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1020 // CHECK2-NEXT: br label [[COND_END]]
1021 // CHECK2: cond.end:
1022 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1023 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1024 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1025 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1026 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1027 // CHECK2: omp.inner.for.cond:
1028 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1029 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1030 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1031 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1032 // CHECK2: omp.inner.for.cond.cleanup:
1033 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1034 // CHECK2: omp.inner.for.body:
1035 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1036 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1037 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1038 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1039 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
1040 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1041 // CHECK2: omp.inner.for.inc:
1042 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1043 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1044 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1045 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1046 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1047 // CHECK2: omp.inner.for.end:
1048 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1049 // CHECK2: omp.loop.exit:
1050 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1051 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
1052 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
1053 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1054 // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1055 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2
1056 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1057 // CHECK2: arraydestroy.body:
1058 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1059 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1060 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1061 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
1062 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
1063 // CHECK2: arraydestroy.done3:
1064 // CHECK2-NEXT: ret void
1065 //
1066 //
1067 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
1068 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1069 // CHECK2-NEXT: entry:
1070 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1071 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1072 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1073 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1074 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1075 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1076 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1077 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1078 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1079 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1080 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1081 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1082 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1083 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1084 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1085 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1086 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1087 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1088 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1089 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1090 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1091 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1092 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1093 // CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1094 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1095 // CHECK2-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
1096 // CHECK2-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1097 // CHECK2-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4
1098 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1099 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1100 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1101 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1102 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1103 // CHECK2: arrayctor.loop:
1104 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1105 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1106 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
1107 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1108 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1109 // CHECK2: arrayctor.cont:
1110 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1111 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1112 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1113 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1114 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1115 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1116 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1117 // CHECK2: cond.true:
1118 // CHECK2-NEXT: br label [[COND_END:%.*]]
1119 // CHECK2: cond.false:
1120 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1121 // CHECK2-NEXT: br label [[COND_END]]
1122 // CHECK2: cond.end:
1123 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1124 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1125 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1126 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1127 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1128 // CHECK2: omp.inner.for.cond:
1129 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1130 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1131 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1132 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1133 // CHECK2: omp.inner.for.cond.cleanup:
1134 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1135 // CHECK2: omp.inner.for.body:
1136 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1137 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1138 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1139 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1140 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
1141 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1142 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1143 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1144 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
1145 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
1146 // CHECK2-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
1147 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
1148 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8*
1149 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1150 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false)
1151 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
1152 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4
1153 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
1154 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4
1155 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1156 // CHECK2: omp.body.continue:
1157 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1158 // CHECK2: omp.inner.for.inc:
1159 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1160 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
1161 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
1162 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1163 // CHECK2: omp.inner.for.end:
1164 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1165 // CHECK2: omp.loop.exit:
1166 // CHECK2-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1167 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
1168 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
1169 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1170 // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1171 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2
1172 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1173 // CHECK2: arraydestroy.body:
1174 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1175 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1176 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1177 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1178 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1179 // CHECK2: arraydestroy.done8:
1180 // CHECK2-NEXT: ret void
1181 //
1182 //
1183 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1184 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat {
1185 // CHECK2-NEXT: entry:
1186 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1187 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1188 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1189 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1190 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1191 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1192 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1193 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1194 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1195 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4
1196 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1197 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1198 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1199 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
1200 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1201 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
1202 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1203 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1204 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
1205 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
1206 // CHECK2-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
1207 // CHECK2-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1208 // CHECK2: omp_offload.failed:
1209 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1210 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1211 // CHECK2: omp_offload.cont:
1212 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
1213 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1214 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1215 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1216 // CHECK2: arraydestroy.body:
1217 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1218 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1219 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1220 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1221 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1222 // CHECK2: arraydestroy.done2:
1223 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1224 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
1225 // CHECK2-NEXT: ret i32 [[TMP4]]
1226 //
1227 //
1228 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1229 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1230 // CHECK2-NEXT: entry:
1231 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1232 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1233 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1234 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1235 // CHECK2-NEXT: ret void
1236 //
1237 //
1238 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1239 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1240 // CHECK2-NEXT: entry:
1241 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1242 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1243 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1244 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1245 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1246 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1247 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
1248 // CHECK2-NEXT: ret void
1249 //
1250 //
1251 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1252 // CHECK2-SAME: () #[[ATTR4]] {
1253 // CHECK2-NEXT: entry:
1254 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
1255 // CHECK2-NEXT: ret void
1256 //
1257 //
1258 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
1259 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1260 // CHECK2-NEXT: entry:
1261 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1262 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1263 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1264 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1265 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1266 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1267 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1268 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1269 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1270 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1271 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1272 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1273 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1274 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
1275 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1276 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1277 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1278 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1279 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1280 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1281 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1282 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1283 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1284 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1285 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1286 // CHECK2: arrayctor.loop:
1287 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1288 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1289 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1290 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1291 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1292 // CHECK2: arrayctor.cont:
1293 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1294 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
1295 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1296 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1297 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1298 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1299 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1300 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1301 // CHECK2: cond.true:
1302 // CHECK2-NEXT: br label [[COND_END:%.*]]
1303 // CHECK2: cond.false:
1304 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1305 // CHECK2-NEXT: br label [[COND_END]]
1306 // CHECK2: cond.end:
1307 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1308 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1309 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1310 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1311 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1312 // CHECK2: omp.inner.for.cond:
1313 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1314 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1315 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1316 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1317 // CHECK2: omp.inner.for.cond.cleanup:
1318 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1319 // CHECK2: omp.inner.for.body:
1320 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1321 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1322 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1323 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1324 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
1325 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1326 // CHECK2: omp.inner.for.inc:
1327 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1328 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1329 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1330 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1331 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1332 // CHECK2: omp.inner.for.end:
1333 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1334 // CHECK2: omp.loop.exit:
1335 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1336 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4
1337 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]])
1338 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1339 // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1340 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2
1341 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1342 // CHECK2: arraydestroy.body:
1343 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1344 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1345 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1346 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1347 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1348 // CHECK2: arraydestroy.done5:
1349 // CHECK2-NEXT: ret void
1350 //
1351 //
1352 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5
1353 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1354 // CHECK2-NEXT: entry:
1355 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1356 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1357 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1358 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1359 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1360 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1361 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
1362 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1363 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1364 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1365 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1366 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1367 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1368 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1369 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1370 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8
1371 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1372 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1373 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1374 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1375 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1376 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
1377 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1378 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1379 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1380 // CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1381 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1382 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
1383 // CHECK2-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
1384 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
1385 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1386 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1387 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1388 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1389 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1390 // CHECK2: arrayctor.loop:
1391 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1392 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1393 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
1394 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1395 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1396 // CHECK2: arrayctor.cont:
1397 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1398 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8
1399 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1400 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1401 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1402 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1403 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1404 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1405 // CHECK2: cond.true:
1406 // CHECK2-NEXT: br label [[COND_END:%.*]]
1407 // CHECK2: cond.false:
1408 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1409 // CHECK2-NEXT: br label [[COND_END]]
1410 // CHECK2: cond.end:
1411 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1412 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1413 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1414 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1415 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1416 // CHECK2: omp.inner.for.cond:
1417 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1418 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1419 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1420 // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1421 // CHECK2: omp.inner.for.cond.cleanup:
1422 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1423 // CHECK2: omp.inner.for.body:
1424 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1425 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1426 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1427 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1428 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
1429 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1430 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1431 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1432 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
1433 // CHECK2-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8
1434 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
1435 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
1436 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]]
1437 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8*
1438 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
1439 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false)
1440 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1441 // CHECK2: omp.body.continue:
1442 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1443 // CHECK2: omp.inner.for.inc:
1444 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1445 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1
1446 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
1447 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1448 // CHECK2: omp.inner.for.end:
1449 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1450 // CHECK2: omp.loop.exit:
1451 // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1452 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
1453 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
1454 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1455 // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1456 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2
1457 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1458 // CHECK2: arraydestroy.body:
1459 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1460 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1461 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1462 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
1463 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
1464 // CHECK2: arraydestroy.done9:
1465 // CHECK2-NEXT: ret void
1466 //
1467 //
1468 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1469 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1470 // CHECK2-NEXT: entry:
1471 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1472 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1473 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1474 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1475 // CHECK2-NEXT: ret void
1476 //
1477 //
1478 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1479 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1480 // CHECK2-NEXT: entry:
1481 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1482 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1483 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1484 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1485 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1486 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1487 // CHECK2-NEXT: ret void
1488 //
1489 //
1490 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1491 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1492 // CHECK2-NEXT: entry:
1493 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1494 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1495 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1496 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1497 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1498 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1499 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1500 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1501 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1502 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1503 // CHECK2-NEXT: ret void
1504 //
1505 //
1506 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1507 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1508 // CHECK2-NEXT: entry:
1509 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1510 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1511 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1512 // CHECK2-NEXT: ret void
1513 //
1514 //
1515 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp
1516 // CHECK2-SAME: () #[[ATTR0]] {
1517 // CHECK2-NEXT: entry:
1518 // CHECK2-NEXT: call void @__cxx_global_var_init()
1519 // CHECK2-NEXT: call void @__cxx_global_var_init.1()
1520 // CHECK2-NEXT: call void @__cxx_global_var_init.2()
1521 // CHECK2-NEXT: ret void
1522 //
1523 //
1524 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1525 // CHECK2-SAME: () #[[ATTR0]] {
1526 // CHECK2-NEXT: entry:
1527 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
1528 // CHECK2-NEXT: ret void
1529 //
1530 //
1531 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1532 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1533 // CHECK3-NEXT: entry:
1534 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1535 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1536 // CHECK3-NEXT: ret void
1537 //
1538 //
1539 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1540 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1541 // CHECK3-NEXT: entry:
1542 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1543 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1544 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1545 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1546 // CHECK3-NEXT: ret void
1547 //
1548 //
1549 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1550 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1551 // CHECK3-NEXT: entry:
1552 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1553 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1554 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1555 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1556 // CHECK3-NEXT: ret void
1557 //
1558 //
1559 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1560 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1561 // CHECK3-NEXT: entry:
1562 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1563 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1564 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1565 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1566 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1567 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1568 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
1569 // CHECK3-NEXT: ret void
1570 //
1571 //
1572 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1573 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1574 // CHECK3-NEXT: entry:
1575 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1576 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1577 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1578 // CHECK3-NEXT: ret void
1579 //
1580 //
1581 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1582 // CHECK3-SAME: () #[[ATTR0]] {
1583 // CHECK3-NEXT: entry:
1584 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
1585 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
1586 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1587 // CHECK3-NEXT: ret void
1588 //
1589 //
1590 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1591 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1592 // CHECK3-NEXT: entry:
1593 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1594 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1595 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1596 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1597 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1598 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1599 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1600 // CHECK3-NEXT: ret void
1601 //
1602 //
1603 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1604 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1605 // CHECK3-NEXT: entry:
1606 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1607 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1608 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1609 // CHECK3: arraydestroy.body:
1610 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1611 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1612 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1613 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1614 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1615 // CHECK3: arraydestroy.done1:
1616 // CHECK3-NEXT: ret void
1617 //
1618 //
1619 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1620 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1621 // CHECK3-NEXT: entry:
1622 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1623 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1624 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1625 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1626 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1627 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1628 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1629 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1630 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1631 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1632 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
1633 // CHECK3-NEXT: ret void
1634 //
1635 //
1636 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1637 // CHECK3-SAME: () #[[ATTR0]] {
1638 // CHECK3-NEXT: entry:
1639 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1640 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1641 // CHECK3-NEXT: ret void
1642 //
1643 //
1644 // CHECK3-LABEL: define {{[^@]+}}@main
1645 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1646 // CHECK3-NEXT: entry:
1647 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1648 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1649 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1650 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
1651 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
1652 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
1653 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1654 // CHECK3: omp_offload.failed:
1655 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]]
1656 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1657 // CHECK3: omp_offload.cont:
1658 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1659 // CHECK3-NEXT: ret i32 [[CALL]]
1660 //
1661 //
1662 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96
1663 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
1664 // CHECK3-NEXT: entry:
1665 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1666 // CHECK3-NEXT: ret void
1667 //
1668 //
1669 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1670 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1671 // CHECK3-NEXT: entry:
1672 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1673 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1674 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1675 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1676 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1677 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1678 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1679 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1680 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1681 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1682 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1683 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1684 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1685 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1686 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1687 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1688 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1689 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1690 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1691 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1692 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1693 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1694 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1695 // CHECK3: arrayctor.loop:
1696 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1697 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1698 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1699 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1700 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1701 // CHECK3: arrayctor.cont:
1702 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1703 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1704 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1705 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1706 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1707 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1708 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1709 // CHECK3: cond.true:
1710 // CHECK3-NEXT: br label [[COND_END:%.*]]
1711 // CHECK3: cond.false:
1712 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1713 // CHECK3-NEXT: br label [[COND_END]]
1714 // CHECK3: cond.end:
1715 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1716 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1717 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1718 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1719 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1720 // CHECK3: omp.inner.for.cond:
1721 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1722 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1723 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1724 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1725 // CHECK3: omp.inner.for.cond.cleanup:
1726 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1727 // CHECK3: omp.inner.for.body:
1728 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1729 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1730 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]])
1731 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1732 // CHECK3: omp.inner.for.inc:
1733 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1734 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1735 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
1736 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1737 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1738 // CHECK3: omp.inner.for.end:
1739 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1740 // CHECK3: omp.loop.exit:
1741 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1742 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
1743 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
1744 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1745 // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1746 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2
1747 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1748 // CHECK3: arraydestroy.body:
1749 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1750 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1751 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1752 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
1753 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
1754 // CHECK3: arraydestroy.done3:
1755 // CHECK3-NEXT: ret void
1756 //
1757 //
1758 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1759 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1760 // CHECK3-NEXT: entry:
1761 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1762 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1763 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1764 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1765 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1766 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1767 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1768 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1769 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1770 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1771 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1772 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1773 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1774 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1775 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1776 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1777 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1778 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1779 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1780 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1781 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1782 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1783 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
1784 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
1785 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
1786 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
1787 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1788 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1789 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1790 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1791 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1792 // CHECK3: arrayctor.loop:
1793 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1794 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1795 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1796 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1797 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1798 // CHECK3: arrayctor.cont:
1799 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1800 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1801 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
1802 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1803 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1804 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1805 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1806 // CHECK3: cond.true:
1807 // CHECK3-NEXT: br label [[COND_END:%.*]]
1808 // CHECK3: cond.false:
1809 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1810 // CHECK3-NEXT: br label [[COND_END]]
1811 // CHECK3: cond.end:
1812 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1813 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1814 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1815 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
1816 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1817 // CHECK3: omp.inner.for.cond:
1818 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1819 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1820 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1821 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1822 // CHECK3: omp.inner.for.cond.cleanup:
1823 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1824 // CHECK3: omp.inner.for.body:
1825 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1826 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1827 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1828 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1829 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
1830 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1831 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
1832 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
1833 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
1834 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]]
1835 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1836 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1837 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false)
1838 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
1839 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4
1840 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
1841 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4
1842 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1843 // CHECK3: omp.body.continue:
1844 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1845 // CHECK3: omp.inner.for.inc:
1846 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1847 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1
1848 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
1849 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
1850 // CHECK3: omp.inner.for.end:
1851 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1852 // CHECK3: omp.loop.exit:
1853 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1854 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
1855 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
1856 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1857 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1858 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
1859 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1860 // CHECK3: arraydestroy.body:
1861 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1862 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1863 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1864 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1865 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1866 // CHECK3: arraydestroy.done6:
1867 // CHECK3-NEXT: ret void
1868 //
1869 //
1870 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1871 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
1872 // CHECK3-NEXT: entry:
1873 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1874 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1875 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1876 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1877 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1878 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1879 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1880 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1881 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1882 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
1883 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1884 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1885 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1886 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
1887 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1888 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1889 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1890 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1891 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
1892 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
1893 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
1894 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1895 // CHECK3: omp_offload.failed:
1896 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1897 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1898 // CHECK3: omp_offload.cont:
1899 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1900 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1901 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1902 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1903 // CHECK3: arraydestroy.body:
1904 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1905 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1906 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1907 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1908 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1909 // CHECK3: arraydestroy.done2:
1910 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1911 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
1912 // CHECK3-NEXT: ret i32 [[TMP4]]
1913 //
1914 //
1915 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1916 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1917 // CHECK3-NEXT: entry:
1918 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1919 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1920 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1921 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1922 // CHECK3-NEXT: ret void
1923 //
1924 //
1925 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1926 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1927 // CHECK3-NEXT: entry:
1928 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1929 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1930 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1931 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1932 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1933 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1934 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1935 // CHECK3-NEXT: ret void
1936 //
1937 //
1938 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1939 // CHECK3-SAME: () #[[ATTR4]] {
1940 // CHECK3-NEXT: entry:
1941 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
1942 // CHECK3-NEXT: ret void
1943 //
1944 //
1945 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
1946 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1947 // CHECK3-NEXT: entry:
1948 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1949 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1950 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1951 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1952 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1953 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1954 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1955 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1956 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1957 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1958 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1959 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1960 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1961 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1962 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1963 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1964 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1965 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1966 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1967 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1968 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1969 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1970 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1971 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1972 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1973 // CHECK3: arrayctor.loop:
1974 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1975 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1976 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1977 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1978 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1979 // CHECK3: arrayctor.cont:
1980 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1981 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1982 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1983 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1984 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1985 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1986 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1987 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1988 // CHECK3: cond.true:
1989 // CHECK3-NEXT: br label [[COND_END:%.*]]
1990 // CHECK3: cond.false:
1991 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1992 // CHECK3-NEXT: br label [[COND_END]]
1993 // CHECK3: cond.end:
1994 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1995 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1996 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1997 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1998 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1999 // CHECK3: omp.inner.for.cond:
2000 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2001 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2002 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2003 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2004 // CHECK3: omp.inner.for.cond.cleanup:
2005 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2006 // CHECK3: omp.inner.for.body:
2007 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2008 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2009 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]])
2010 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2011 // CHECK3: omp.inner.for.inc:
2012 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2013 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2014 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
2015 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2016 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2017 // CHECK3: omp.inner.for.end:
2018 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2019 // CHECK3: omp.loop.exit:
2020 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2021 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
2022 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
2023 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2024 // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2025 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2
2026 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2027 // CHECK3: arraydestroy.body:
2028 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2029 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2030 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2031 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
2032 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2033 // CHECK3: arraydestroy.done5:
2034 // CHECK3-NEXT: ret void
2035 //
2036 //
2037 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
2038 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
2039 // CHECK3-NEXT: entry:
2040 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2041 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2042 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2043 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2044 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2045 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2046 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2047 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2048 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2049 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2050 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2051 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2052 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2053 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2054 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2055 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
2056 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2057 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2058 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2059 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2060 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2061 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2062 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2063 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2064 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2065 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2066 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
2067 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
2068 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2069 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2070 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2071 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2072 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2073 // CHECK3: arrayctor.loop:
2074 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2075 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2076 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2077 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2078 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2079 // CHECK3: arrayctor.cont:
2080 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
2081 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
2082 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2083 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2084 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2085 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2086 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2087 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2088 // CHECK3: cond.true:
2089 // CHECK3-NEXT: br label [[COND_END:%.*]]
2090 // CHECK3: cond.false:
2091 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2092 // CHECK3-NEXT: br label [[COND_END]]
2093 // CHECK3: cond.end:
2094 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2095 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2096 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2097 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2098 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2099 // CHECK3: omp.inner.for.cond:
2100 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2101 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2102 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2103 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2104 // CHECK3: omp.inner.for.cond.cleanup:
2105 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2106 // CHECK3: omp.inner.for.body:
2107 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2108 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2109 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2110 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2111 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
2112 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
2113 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
2114 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
2115 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4
2116 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
2117 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]]
2118 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
2119 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
2120 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false)
2121 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2122 // CHECK3: omp.body.continue:
2123 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2124 // CHECK3: omp.inner.for.inc:
2125 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2126 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
2127 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
2128 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2129 // CHECK3: omp.inner.for.end:
2130 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2131 // CHECK3: omp.loop.exit:
2132 // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2133 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
2134 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
2135 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2136 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2137 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
2138 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2139 // CHECK3: arraydestroy.body:
2140 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2141 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2142 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2143 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
2144 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2145 // CHECK3: arraydestroy.done7:
2146 // CHECK3-NEXT: ret void
2147 //
2148 //
2149 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2150 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2151 // CHECK3-NEXT: entry:
2152 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2153 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2154 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2155 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2156 // CHECK3-NEXT: ret void
2157 //
2158 //
2159 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2160 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2161 // CHECK3-NEXT: entry:
2162 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2163 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2164 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2165 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2166 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2167 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2168 // CHECK3-NEXT: ret void
2169 //
2170 //
2171 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2172 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2173 // CHECK3-NEXT: entry:
2174 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2175 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2176 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2177 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2178 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2179 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2180 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2181 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2182 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2183 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2184 // CHECK3-NEXT: ret void
2185 //
2186 //
2187 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2188 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2189 // CHECK3-NEXT: entry:
2190 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2191 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2192 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2193 // CHECK3-NEXT: ret void
2194 //
2195 //
2196 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp
2197 // CHECK3-SAME: () #[[ATTR0]] {
2198 // CHECK3-NEXT: entry:
2199 // CHECK3-NEXT: call void @__cxx_global_var_init()
2200 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
2201 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
2202 // CHECK3-NEXT: ret void
2203 //
2204 //
2205 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2206 // CHECK3-SAME: () #[[ATTR0]] {
2207 // CHECK3-NEXT: entry:
2208 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
2209 // CHECK3-NEXT: ret void
2210 //
2211 //
2212 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
2213 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
2214 // CHECK4-NEXT: entry:
2215 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2216 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2217 // CHECK4-NEXT: ret void
2218 //
2219 //
2220 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2221 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2222 // CHECK4-NEXT: entry:
2223 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2224 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2225 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2226 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2227 // CHECK4-NEXT: ret void
2228 //
2229 //
2230 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2231 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2232 // CHECK4-NEXT: entry:
2233 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2234 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2235 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2236 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2237 // CHECK4-NEXT: ret void
2238 //
2239 //
2240 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2241 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2242 // CHECK4-NEXT: entry:
2243 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2244 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2245 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2246 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2247 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2248 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2249 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4
2250 // CHECK4-NEXT: ret void
2251 //
2252 //
2253 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2254 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2255 // CHECK4-NEXT: entry:
2256 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2257 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2258 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2259 // CHECK4-NEXT: ret void
2260 //
2261 //
2262 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2263 // CHECK4-SAME: () #[[ATTR0]] {
2264 // CHECK4-NEXT: entry:
2265 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
2266 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
2267 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2268 // CHECK4-NEXT: ret void
2269 //
2270 //
2271 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2272 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2273 // CHECK4-NEXT: entry:
2274 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2275 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2276 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2277 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2278 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2279 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2280 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2281 // CHECK4-NEXT: ret void
2282 //
2283 //
2284 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2285 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2286 // CHECK4-NEXT: entry:
2287 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
2288 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
2289 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2290 // CHECK4: arraydestroy.body:
2291 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2292 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2293 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2294 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2295 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2296 // CHECK4: arraydestroy.done1:
2297 // CHECK4-NEXT: ret void
2298 //
2299 //
2300 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2301 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2302 // CHECK4-NEXT: entry:
2303 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2304 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2305 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2306 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2307 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2308 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2309 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2310 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2311 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2312 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2313 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
2314 // CHECK4-NEXT: ret void
2315 //
2316 //
2317 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2318 // CHECK4-SAME: () #[[ATTR0]] {
2319 // CHECK4-NEXT: entry:
2320 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2321 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2322 // CHECK4-NEXT: ret void
2323 //
2324 //
2325 // CHECK4-LABEL: define {{[^@]+}}@main
2326 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
2327 // CHECK4-NEXT: entry:
2328 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2329 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2330 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
2331 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
2332 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
2333 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
2334 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2335 // CHECK4: omp_offload.failed:
2336 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]]
2337 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
2338 // CHECK4: omp_offload.cont:
2339 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
2340 // CHECK4-NEXT: ret i32 [[CALL]]
2341 //
2342 //
2343 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96
2344 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] {
2345 // CHECK4-NEXT: entry:
2346 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2347 // CHECK4-NEXT: ret void
2348 //
2349 //
2350 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
2351 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
2352 // CHECK4-NEXT: entry:
2353 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2354 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2355 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2356 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2357 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2358 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2359 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2360 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2361 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2362 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2363 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2364 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2365 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2366 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2367 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2368 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2369 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2370 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2371 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2372 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2373 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2374 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2375 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2376 // CHECK4: arrayctor.loop:
2377 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2378 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2379 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2380 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2381 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2382 // CHECK4: arrayctor.cont:
2383 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2384 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2385 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2386 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2387 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2388 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2389 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2390 // CHECK4: cond.true:
2391 // CHECK4-NEXT: br label [[COND_END:%.*]]
2392 // CHECK4: cond.false:
2393 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2394 // CHECK4-NEXT: br label [[COND_END]]
2395 // CHECK4: cond.end:
2396 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2397 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2398 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2399 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2400 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2401 // CHECK4: omp.inner.for.cond:
2402 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2403 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2404 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2405 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2406 // CHECK4: omp.inner.for.cond.cleanup:
2407 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2408 // CHECK4: omp.inner.for.body:
2409 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2410 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2411 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]])
2412 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2413 // CHECK4: omp.inner.for.inc:
2414 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2415 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2416 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
2417 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2418 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
2419 // CHECK4: omp.inner.for.end:
2420 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2421 // CHECK4: omp.loop.exit:
2422 // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2423 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
2424 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
2425 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2426 // CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2427 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2
2428 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2429 // CHECK4: arraydestroy.body:
2430 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2431 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2432 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2433 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
2434 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
2435 // CHECK4: arraydestroy.done3:
2436 // CHECK4-NEXT: ret void
2437 //
2438 //
2439 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
2440 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
2441 // CHECK4-NEXT: entry:
2442 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2443 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2444 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2445 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2446 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2447 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2448 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2449 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2450 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2451 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2452 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2453 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2454 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2455 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2456 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2457 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2458 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2459 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2460 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2461 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2462 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2463 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2464 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2465 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2466 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
2467 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
2468 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2469 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2470 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2471 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2472 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2473 // CHECK4: arrayctor.loop:
2474 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2475 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2476 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2477 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2478 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2479 // CHECK4: arrayctor.cont:
2480 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2481 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2482 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2483 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2484 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2485 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2486 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2487 // CHECK4: cond.true:
2488 // CHECK4-NEXT: br label [[COND_END:%.*]]
2489 // CHECK4: cond.false:
2490 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2491 // CHECK4-NEXT: br label [[COND_END]]
2492 // CHECK4: cond.end:
2493 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2494 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2495 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2496 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2497 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2498 // CHECK4: omp.inner.for.cond:
2499 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2500 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2501 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2502 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2503 // CHECK4: omp.inner.for.cond.cleanup:
2504 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2505 // CHECK4: omp.inner.for.body:
2506 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2507 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2508 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2509 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2510 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
2511 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
2512 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
2513 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
2514 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
2515 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]]
2516 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
2517 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8*
2518 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false)
2519 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
2520 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4
2521 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
2522 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4
2523 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2524 // CHECK4: omp.body.continue:
2525 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2526 // CHECK4: omp.inner.for.inc:
2527 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2528 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1
2529 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
2530 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
2531 // CHECK4: omp.inner.for.end:
2532 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2533 // CHECK4: omp.loop.exit:
2534 // CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2535 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4
2536 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
2537 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2538 // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2539 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
2540 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2541 // CHECK4: arraydestroy.body:
2542 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2543 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2544 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2545 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
2546 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2547 // CHECK4: arraydestroy.done6:
2548 // CHECK4-NEXT: ret void
2549 //
2550 //
2551 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2552 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat {
2553 // CHECK4-NEXT: entry:
2554 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2555 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2556 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2557 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2558 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2559 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
2560 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2561 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2562 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2563 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4
2564 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2565 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
2566 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2567 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
2568 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
2569 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
2570 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
2571 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2572 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
2573 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0)
2574 // CHECK4-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
2575 // CHECK4-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2576 // CHECK4: omp_offload.failed:
2577 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
2578 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
2579 // CHECK4: omp_offload.cont:
2580 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
2581 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2582 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2583 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2584 // CHECK4: arraydestroy.body:
2585 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2586 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2587 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2588 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2589 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2590 // CHECK4: arraydestroy.done2:
2591 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2592 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
2593 // CHECK4-NEXT: ret i32 [[TMP4]]
2594 //
2595 //
2596 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2597 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2598 // CHECK4-NEXT: entry:
2599 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2600 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2601 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2602 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2603 // CHECK4-NEXT: ret void
2604 //
2605 //
2606 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2607 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2608 // CHECK4-NEXT: entry:
2609 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2610 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2611 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2612 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2613 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2614 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2615 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
2616 // CHECK4-NEXT: ret void
2617 //
2618 //
2619 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
2620 // CHECK4-SAME: () #[[ATTR4]] {
2621 // CHECK4-NEXT: entry:
2622 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
2623 // CHECK4-NEXT: ret void
2624 //
2625 //
2626 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
2627 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
2628 // CHECK4-NEXT: entry:
2629 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2630 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2631 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2632 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2633 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2634 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2635 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2636 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2637 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2638 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2639 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2640 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2641 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2642 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
2643 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2644 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2645 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2646 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2647 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2648 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2649 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2650 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2651 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2652 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2653 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2654 // CHECK4: arrayctor.loop:
2655 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2656 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2657 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2658 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2659 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2660 // CHECK4: arrayctor.cont:
2661 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
2662 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
2663 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2664 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2665 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2666 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2667 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2668 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2669 // CHECK4: cond.true:
2670 // CHECK4-NEXT: br label [[COND_END:%.*]]
2671 // CHECK4: cond.false:
2672 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2673 // CHECK4-NEXT: br label [[COND_END]]
2674 // CHECK4: cond.end:
2675 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2676 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2677 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2678 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2679 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2680 // CHECK4: omp.inner.for.cond:
2681 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2682 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2683 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2684 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2685 // CHECK4: omp.inner.for.cond.cleanup:
2686 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2687 // CHECK4: omp.inner.for.body:
2688 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2689 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2690 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]])
2691 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2692 // CHECK4: omp.inner.for.inc:
2693 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2694 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2695 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
2696 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2697 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
2698 // CHECK4: omp.inner.for.end:
2699 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2700 // CHECK4: omp.loop.exit:
2701 // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2702 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4
2703 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]])
2704 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2705 // CHECK4-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2706 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2
2707 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2708 // CHECK4: arraydestroy.body:
2709 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2710 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2711 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2712 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
2713 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2714 // CHECK4: arraydestroy.done5:
2715 // CHECK4-NEXT: ret void
2716 //
2717 //
2718 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5
2719 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
2720 // CHECK4-NEXT: entry:
2721 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2722 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2723 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2724 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2725 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2726 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2727 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
2728 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2729 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2730 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2731 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2732 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2733 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2734 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2735 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2736 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
2737 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
2738 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2739 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2740 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2741 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2742 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
2743 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2744 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2745 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2746 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2747 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4
2748 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4
2749 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2750 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2751 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2752 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2753 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2754 // CHECK4: arrayctor.loop:
2755 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2756 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2757 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
2758 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2759 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2760 // CHECK4: arrayctor.cont:
2761 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
2762 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
2763 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2764 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
2765 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2766 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2767 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2768 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2769 // CHECK4: cond.true:
2770 // CHECK4-NEXT: br label [[COND_END:%.*]]
2771 // CHECK4: cond.false:
2772 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2773 // CHECK4-NEXT: br label [[COND_END]]
2774 // CHECK4: cond.end:
2775 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2776 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2777 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2778 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
2779 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2780 // CHECK4: omp.inner.for.cond:
2781 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2782 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2783 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2784 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2785 // CHECK4: omp.inner.for.cond.cleanup:
2786 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2787 // CHECK4: omp.inner.for.body:
2788 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2789 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2790 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2791 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2792 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4
2793 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
2794 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]]
2795 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4
2796 // CHECK4-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4
2797 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
2798 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]]
2799 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
2800 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8*
2801 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false)
2802 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2803 // CHECK4: omp.body.continue:
2804 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2805 // CHECK4: omp.inner.for.inc:
2806 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2807 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1
2808 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
2809 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
2810 // CHECK4: omp.inner.for.end:
2811 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2812 // CHECK4: omp.loop.exit:
2813 // CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2814 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4
2815 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]])
2816 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2817 // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2818 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
2819 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2820 // CHECK4: arraydestroy.body:
2821 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2822 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2823 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2824 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
2825 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2826 // CHECK4: arraydestroy.done7:
2827 // CHECK4-NEXT: ret void
2828 //
2829 //
2830 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2831 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2832 // CHECK4-NEXT: entry:
2833 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2834 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2835 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2836 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2837 // CHECK4-NEXT: ret void
2838 //
2839 //
2840 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2841 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2842 // CHECK4-NEXT: entry:
2843 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2844 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2845 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2846 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2847 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2848 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2849 // CHECK4-NEXT: ret void
2850 //
2851 //
2852 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2853 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2854 // CHECK4-NEXT: entry:
2855 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2856 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2857 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2858 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2859 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2860 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2861 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2862 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2863 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2864 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2865 // CHECK4-NEXT: ret void
2866 //
2867 //
2868 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2869 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2870 // CHECK4-NEXT: entry:
2871 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2872 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2873 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2874 // CHECK4-NEXT: ret void
2875 //
2876 //
2877 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp
2878 // CHECK4-SAME: () #[[ATTR0]] {
2879 // CHECK4-NEXT: entry:
2880 // CHECK4-NEXT: call void @__cxx_global_var_init()
2881 // CHECK4-NEXT: call void @__cxx_global_var_init.1()
2882 // CHECK4-NEXT: call void @__cxx_global_var_init.2()
2883 // CHECK4-NEXT: ret void
2884 //
2885 //
2886 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2887 // CHECK4-SAME: () #[[ATTR0]] {
2888 // CHECK4-NEXT: entry:
2889 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
2890 // CHECK4-NEXT: ret void
2891 //
2892 //
2893 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
2894 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
2895 // CHECK9-NEXT: entry:
2896 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2897 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2898 // CHECK9-NEXT: ret void
2899 //
2900 //
2901 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2902 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2903 // CHECK9-NEXT: entry:
2904 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2905 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2906 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2907 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2908 // CHECK9-NEXT: ret void
2909 //
2910 //
2911 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2912 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2913 // CHECK9-NEXT: entry:
2914 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2915 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2916 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2917 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2918 // CHECK9-NEXT: ret void
2919 //
2920 //
2921 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2922 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2923 // CHECK9-NEXT: entry:
2924 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2925 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2926 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2927 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2928 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2929 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2930 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
2931 // CHECK9-NEXT: ret void
2932 //
2933 //
2934 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2935 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2936 // CHECK9-NEXT: entry:
2937 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2938 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2939 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2940 // CHECK9-NEXT: ret void
2941 //
2942 //
2943 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2944 // CHECK9-SAME: () #[[ATTR0]] {
2945 // CHECK9-NEXT: entry:
2946 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
2947 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
2948 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2949 // CHECK9-NEXT: ret void
2950 //
2951 //
2952 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2953 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2954 // CHECK9-NEXT: entry:
2955 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2956 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2957 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2958 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2959 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2960 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2961 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2962 // CHECK9-NEXT: ret void
2963 //
2964 //
2965 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2966 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2967 // CHECK9-NEXT: entry:
2968 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2969 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2970 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2971 // CHECK9: arraydestroy.body:
2972 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2973 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2974 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2975 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2976 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2977 // CHECK9: arraydestroy.done1:
2978 // CHECK9-NEXT: ret void
2979 //
2980 //
2981 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2982 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2983 // CHECK9-NEXT: entry:
2984 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2985 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2986 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2987 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2988 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2989 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2990 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2991 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2992 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2993 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2994 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
2995 // CHECK9-NEXT: ret void
2996 //
2997 //
2998 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2999 // CHECK9-SAME: () #[[ATTR0]] {
3000 // CHECK9-NEXT: entry:
3001 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3002 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3003 // CHECK9-NEXT: ret void
3004 //
3005 //
3006 // CHECK9-LABEL: define {{[^@]+}}@main
3007 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
3008 // CHECK9-NEXT: entry:
3009 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3010 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3011 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
3012 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
3013 // CHECK9-NEXT: ret i32 0
3014 //
3015 //
3016 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
3017 // CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
3018 // CHECK9-NEXT: entry:
3019 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
3020 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
3021 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
3022 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
3023 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
3024 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3025 // CHECK9-NEXT: ret void
3026 //
3027 //
3028 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
3029 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
3030 // CHECK9-NEXT: entry:
3031 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3032 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3033 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3034 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
3035 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
3036 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3037 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3038 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3039 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3040 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
3041 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
3042 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
3043 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3044 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
3045 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3046 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3047 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
3048 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3049 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3050 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3051 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3052 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
3053 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3054 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3055 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3056 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3057 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
3058 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3059 // CHECK9: cond.true:
3060 // CHECK9-NEXT: br label [[COND_END:%.*]]
3061 // CHECK9: cond.false:
3062 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3063 // CHECK9-NEXT: br label [[COND_END]]
3064 // CHECK9: cond.end:
3065 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3066 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3067 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3068 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3069 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3070 // CHECK9: omp.inner.for.cond:
3071 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3072 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3073 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3074 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3075 // CHECK9: omp.inner.for.body:
3076 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3077 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
3078 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3079 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
3080 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
3081 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3082 // CHECK9: omp.inner.for.inc:
3083 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3084 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3085 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
3086 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3087 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
3088 // CHECK9: omp.inner.for.end:
3089 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3090 // CHECK9: omp.loop.exit:
3091 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
3092 // CHECK9-NEXT: ret void
3093 //
3094 //
3095 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
3096 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
3097 // CHECK9-NEXT: entry:
3098 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3099 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3100 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
3101 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
3102 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3103 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
3104 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
3105 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3106 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3107 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3108 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3109 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
3110 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
3111 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
3112 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3113 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
3114 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
3115 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3116 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3117 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3118 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3119 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
3120 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3121 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3122 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3123 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
3124 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3125 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
3126 // CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
3127 // CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
3128 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3129 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3130 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8
3131 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3132 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
3133 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3134 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3135 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
3136 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3137 // CHECK9: cond.true:
3138 // CHECK9-NEXT: br label [[COND_END:%.*]]
3139 // CHECK9: cond.false:
3140 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3141 // CHECK9-NEXT: br label [[COND_END]]
3142 // CHECK9: cond.end:
3143 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3144 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3145 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3146 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
3147 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3148 // CHECK9: omp.inner.for.cond:
3149 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3150 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3151 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
3152 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3153 // CHECK9: omp.inner.for.body:
3154 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3155 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
3156 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3157 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3158 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4
3159 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8
3160 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
3161 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4
3162 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
3163 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP11]], align 8
3164 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
3165 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8
3166 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
3167 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
3168 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8
3169 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
3170 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3171 // CHECK9: omp.body.continue:
3172 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3173 // CHECK9: omp.inner.for.inc:
3174 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3175 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
3176 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
3177 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
3178 // CHECK9: omp.inner.for.end:
3179 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3180 // CHECK9: omp.loop.exit:
3181 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
3182 // CHECK9-NEXT: ret void
3183 //
3184 //
3185 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp
3186 // CHECK9-SAME: () #[[ATTR0]] {
3187 // CHECK9-NEXT: entry:
3188 // CHECK9-NEXT: call void @__cxx_global_var_init()
3189 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
3190 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
3191 // CHECK9-NEXT: ret void
3192 //
3193 //
3194 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3195 // CHECK9-SAME: () #[[ATTR0]] {
3196 // CHECK9-NEXT: entry:
3197 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
3198 // CHECK9-NEXT: ret void
3199 //
3200 //
3201 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init
3202 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
3203 // CHECK10-NEXT: entry:
3204 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3205 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3206 // CHECK10-NEXT: ret void
3207 //
3208 //
3209 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3210 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3211 // CHECK10-NEXT: entry:
3212 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3213 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3214 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3215 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3216 // CHECK10-NEXT: ret void
3217 //
3218 //
3219 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3220 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3221 // CHECK10-NEXT: entry:
3222 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3223 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3224 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3225 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3226 // CHECK10-NEXT: ret void
3227 //
3228 //
3229 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3230 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3231 // CHECK10-NEXT: entry:
3232 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3233 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3234 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3235 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3236 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3237 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3238 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4
3239 // CHECK10-NEXT: ret void
3240 //
3241 //
3242 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3243 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3244 // CHECK10-NEXT: entry:
3245 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3246 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3247 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3248 // CHECK10-NEXT: ret void
3249 //
3250 //
3251 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3252 // CHECK10-SAME: () #[[ATTR0]] {
3253 // CHECK10-NEXT: entry:
3254 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3255 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3256 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3257 // CHECK10-NEXT: ret void
3258 //
3259 //
3260 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3261 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3262 // CHECK10-NEXT: entry:
3263 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3264 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3265 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3266 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3267 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3268 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3269 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3270 // CHECK10-NEXT: ret void
3271 //
3272 //
3273 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3274 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3275 // CHECK10-NEXT: entry:
3276 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3277 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3278 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3279 // CHECK10: arraydestroy.body:
3280 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3281 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3282 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3283 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3284 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3285 // CHECK10: arraydestroy.done1:
3286 // CHECK10-NEXT: ret void
3287 //
3288 //
3289 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3290 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3291 // CHECK10-NEXT: entry:
3292 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3293 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3294 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3295 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3296 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3297 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3298 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3299 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3300 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3301 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3302 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4
3303 // CHECK10-NEXT: ret void
3304 //
3305 //
3306 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3307 // CHECK10-SAME: () #[[ATTR0]] {
3308 // CHECK10-NEXT: entry:
3309 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3310 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3311 // CHECK10-NEXT: ret void
3312 //
3313 //
3314 // CHECK10-LABEL: define {{[^@]+}}@main
3315 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
3316 // CHECK10-NEXT: entry:
3317 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3318 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3319 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
3320 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
3321 // CHECK10-NEXT: ret i32 0
3322 //
3323 //
3324 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
3325 // CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
3326 // CHECK10-NEXT: entry:
3327 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
3328 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8
3329 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
3330 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
3331 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
3332 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3333 // CHECK10-NEXT: ret void
3334 //
3335 //
3336 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
3337 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
3338 // CHECK10-NEXT: entry:
3339 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3340 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3341 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3342 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
3343 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
3344 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3345 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3346 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3347 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3348 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4
3349 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4
3350 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
3351 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3352 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
3353 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3354 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3355 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8
3356 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3357 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3358 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3359 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3360 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
3361 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3362 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3363 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3364 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3365 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
3366 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3367 // CHECK10: cond.true:
3368 // CHECK10-NEXT: br label [[COND_END:%.*]]
3369 // CHECK10: cond.false:
3370 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3371 // CHECK10-NEXT: br label [[COND_END]]
3372 // CHECK10: cond.end:
3373 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3374 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3375 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3376 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3377 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3378 // CHECK10: omp.inner.for.cond:
3379 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3380 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3381 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3382 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3383 // CHECK10: omp.inner.for.body:
3384 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3385 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
3386 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3387 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
3388 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]])
3389 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3390 // CHECK10: omp.inner.for.inc:
3391 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3392 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3393 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
3394 // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3395 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
3396 // CHECK10: omp.inner.for.end:
3397 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3398 // CHECK10: omp.loop.exit:
3399 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
3400 // CHECK10-NEXT: ret void
3401 //
3402 //
3403 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
3404 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
3405 // CHECK10-NEXT: entry:
3406 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3407 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3408 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
3409 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
3410 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3411 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
3412 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
3413 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3414 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3415 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3416 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3417 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4
3418 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4
3419 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8
3420 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3421 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
3422 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
3423 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3424 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3425 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3426 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3427 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8
3428 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3429 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3430 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
3431 // CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
3432 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
3433 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
3434 // CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4
3435 // CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4
3436 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3437 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3438 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8
3439 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3440 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
3441 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3442 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3443 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
3444 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3445 // CHECK10: cond.true:
3446 // CHECK10-NEXT: br label [[COND_END:%.*]]
3447 // CHECK10: cond.false:
3448 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3449 // CHECK10-NEXT: br label [[COND_END]]
3450 // CHECK10: cond.end:
3451 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3452 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3453 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3454 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
3455 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3456 // CHECK10: omp.inner.for.cond:
3457 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3458 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3459 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
3460 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3461 // CHECK10: omp.inner.for.body:
3462 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3463 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
3464 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3465 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3466 // CHECK10-NEXT: store i32 1, i32* [[G]], align 4
3467 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8
3468 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
3469 // CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4
3470 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
3471 // CHECK10-NEXT: store i32* [[G]], i32** [[TMP11]], align 8
3472 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
3473 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8
3474 // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
3475 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
3476 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8
3477 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
3478 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3479 // CHECK10: omp.body.continue:
3480 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3481 // CHECK10: omp.inner.for.inc:
3482 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3483 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
3484 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
3485 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
3486 // CHECK10: omp.inner.for.end:
3487 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3488 // CHECK10: omp.loop.exit:
3489 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
3490 // CHECK10-NEXT: ret void
3491 //
3492 //
3493 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp
3494 // CHECK10-SAME: () #[[ATTR0]] {
3495 // CHECK10-NEXT: entry:
3496 // CHECK10-NEXT: call void @__cxx_global_var_init()
3497 // CHECK10-NEXT: call void @__cxx_global_var_init.1()
3498 // CHECK10-NEXT: call void @__cxx_global_var_init.2()
3499 // CHECK10-NEXT: ret void
3500 //
3501 //
3502 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3503 // CHECK10-SAME: () #[[ATTR0]] {
3504 // CHECK10-NEXT: entry:
3505 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
3506 // CHECK10-NEXT: ret void
3507 //
3508 //