1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10
19
20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute parallel for simd firstprivate(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
main()71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute parallel for simd firstprivate(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global and bound tid vars
80 // skip loop vars
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84
85 // Skip global and bound tid vars, and prev lb and ub vars
86 // skip loop vars
87
88 // use of private vars
89 [&]() {
90 g = 2;
91 g1 = 2;
92 sivar = 4;
93
94 }();
95 }
96 }();
97 return 0;
98
99
100 #else
101 #pragma omp target
102 #pragma omp teams distribute parallel for simd firstprivate(t_var, vec, s_arr, var, sivar)
103 for (int i = 0; i < 2; ++i) {
104 vec[i] = t_var;
105 s_arr[i] = var;
106 sivar += i;
107 }
108 return tmain<int>();
109 #endif
110 }
111
112
113
114
115
116 // Skip global and bound tid vars
117 // Skip temp vars for loop
118
119 // param copy
120
121 // T_VAR and SIVAR
122
123 // preparation vars
124
125 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
126
127 // firstprivate(s_arr)
128
129 // firstprivate(var)
130
131
132 // Skip global and bound tid vars, and prev lb ub vars
133 // Skip temp vars for loop
134
135 // param copy
136
137 // T_VAR and SIVAR
138
139 // preparation vars
140
141 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
142
143 // firstprivate(s_arr)
144
145 // firstprivate(var)
146
147
148
149
150
151
152 // Skip global and bound tid vars
153 // Skip temp vars for loop
154
155 // param copy
156
157 // T_VAR and preparation variables
158
159 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
160
161 // firstprivate(s_arr)
162
163 // firstprivate(var)
164
165
166 // Skip global and bound tid vars
167 // Skip temp vars for loop
168
169 // param copy
170
171 // T_VAR and preparation variables
172
173 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
174
175 // firstprivate(s_arr)
176
177 // firstprivate(var)
178
179
180
181 #endif
182 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
183 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
184 // CHECK1-NEXT: entry:
185 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
186 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
187 // CHECK1-NEXT: ret void
188 //
189 //
190 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
191 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
192 // CHECK1-NEXT: entry:
193 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
194 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
195 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
196 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
197 // CHECK1-NEXT: ret void
198 //
199 //
200 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
201 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
202 // CHECK1-NEXT: entry:
203 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
204 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
205 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
206 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
207 // CHECK1-NEXT: ret void
208 //
209 //
210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
211 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
212 // CHECK1-NEXT: entry:
213 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
214 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
215 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
216 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
217 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
218 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
219 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
220 // CHECK1-NEXT: ret void
221 //
222 //
223 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
224 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
225 // CHECK1-NEXT: entry:
226 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
227 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
228 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
229 // CHECK1-NEXT: ret void
230 //
231 //
232 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
233 // CHECK1-SAME: () #[[ATTR0]] {
234 // CHECK1-NEXT: entry:
235 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
236 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
237 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
238 // CHECK1-NEXT: ret void
239 //
240 //
241 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
242 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
243 // CHECK1-NEXT: entry:
244 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
245 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
246 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
247 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
248 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
249 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
250 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
251 // CHECK1-NEXT: ret void
252 //
253 //
254 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
255 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
256 // CHECK1-NEXT: entry:
257 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
258 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
259 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
260 // CHECK1: arraydestroy.body:
261 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
262 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
263 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
264 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
265 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
266 // CHECK1: arraydestroy.done1:
267 // CHECK1-NEXT: ret void
268 //
269 //
270 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
271 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
272 // CHECK1-NEXT: entry:
273 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
274 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
275 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
276 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
277 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
278 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
279 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
280 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
281 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
282 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
283 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
284 // CHECK1-NEXT: ret void
285 //
286 //
287 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
288 // CHECK1-SAME: () #[[ATTR0]] {
289 // CHECK1-NEXT: entry:
290 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
291 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
292 // CHECK1-NEXT: ret void
293 //
294 //
295 // CHECK1-LABEL: define {{[^@]+}}@main
296 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
297 // CHECK1-NEXT: entry:
298 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
299 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
300 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
301 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
302 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
303 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
304 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
305 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
306 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
307 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
308 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
309 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
310 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
311 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
312 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
313 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
314 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
315 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
316 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
317 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
318 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
319 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
320 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
321 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
322 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
323 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
324 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8
325 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
326 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
327 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8
328 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
329 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
330 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
331 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
332 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8
333 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
334 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
335 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8
336 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
337 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
338 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
339 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
340 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8
341 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
342 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
343 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8
344 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
345 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
346 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
347 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
348 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8
349 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
350 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
351 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
352 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
353 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8
354 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
355 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
356 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
357 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
358 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
359 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
360 // CHECK1: omp_offload.failed:
361 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]]
362 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
363 // CHECK1: omp_offload.cont:
364 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
365 // CHECK1-NEXT: ret i32 [[CALL]]
366 //
367 //
368 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101
369 // CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
370 // CHECK1-NEXT: entry:
371 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
372 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
373 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
374 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
375 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
376 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
377 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
378 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
379 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
380 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
381 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
382 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
383 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
384 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
385 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
386 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
387 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
388 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
389 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
390 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
391 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
392 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
393 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
394 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
395 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
396 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
397 // CHECK1-NEXT: ret void
398 //
399 //
400 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
401 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
402 // CHECK1-NEXT: entry:
403 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
404 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
405 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
406 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
407 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
408 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
409 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
410 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
411 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
412 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
413 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
414 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
415 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
416 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
417 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
418 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
419 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
420 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
421 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
422 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
423 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
424 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
425 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
426 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
427 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
428 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
429 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
430 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
431 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
432 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
433 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
434 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
435 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
436 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
437 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
438 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
439 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
440 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
441 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
442 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
443 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
444 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
445 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
446 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
447 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
448 // CHECK1: omp.arraycpy.body:
449 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
450 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
451 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
452 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
453 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
454 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
455 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
456 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
457 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
458 // CHECK1: omp.arraycpy.done4:
459 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
460 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
461 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
462 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
463 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
464 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
465 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
466 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
467 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
468 // CHECK1: cond.true:
469 // CHECK1-NEXT: br label [[COND_END:%.*]]
470 // CHECK1: cond.false:
471 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
472 // CHECK1-NEXT: br label [[COND_END]]
473 // CHECK1: cond.end:
474 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
475 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
476 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
477 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
478 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
479 // CHECK1: omp.inner.for.cond:
480 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
481 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
482 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
483 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
484 // CHECK1: omp.inner.for.cond.cleanup:
485 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
486 // CHECK1: omp.inner.for.body:
487 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
488 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
489 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
490 // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
491 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
492 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
493 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
494 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
495 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
496 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
497 // CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
498 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
499 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
500 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
501 // CHECK1: omp.inner.for.inc:
502 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
503 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
504 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
505 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
506 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
507 // CHECK1: omp.inner.for.end:
508 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
509 // CHECK1: omp.loop.exit:
510 // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
511 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
512 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
513 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
514 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
515 // CHECK1-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
516 // CHECK1: .omp.final.then:
517 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
518 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
519 // CHECK1: .omp.final.done:
520 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
521 // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
522 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
523 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
524 // CHECK1: arraydestroy.body:
525 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
526 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
527 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
528 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
529 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
530 // CHECK1: arraydestroy.done11:
531 // CHECK1-NEXT: ret void
532 //
533 //
534 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
535 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
536 // CHECK1-NEXT: entry:
537 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
538 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
539 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
540 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
541 // CHECK1-NEXT: ret void
542 //
543 //
544 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
545 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
546 // CHECK1-NEXT: entry:
547 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
548 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
549 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
550 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
551 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
552 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
553 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
554 // CHECK1-NEXT: ret void
555 //
556 //
557 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
558 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
559 // CHECK1-NEXT: entry:
560 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
561 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
562 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
563 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
564 // CHECK1-NEXT: ret void
565 //
566 //
567 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
568 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
569 // CHECK1-NEXT: entry:
570 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
571 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
572 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
573 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
574 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
575 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
576 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
577 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
578 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
579 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
580 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
581 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
582 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
583 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
584 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
585 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
586 // CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
587 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
588 // CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
589 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
590 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
591 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
592 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
593 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
594 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
595 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
596 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
597 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
598 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
599 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
600 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
601 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
602 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
603 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
604 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
605 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
606 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
607 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
608 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
609 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
610 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
611 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
612 // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
613 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
614 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
615 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
616 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
617 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
618 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
619 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
620 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
621 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
622 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
623 // CHECK1: omp.arraycpy.body:
624 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
625 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
626 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
627 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
628 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
629 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
630 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
631 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
632 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
633 // CHECK1: omp.arraycpy.done6:
634 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
635 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]])
636 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
637 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
638 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
639 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
640 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
641 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
642 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
643 // CHECK1: cond.true:
644 // CHECK1-NEXT: br label [[COND_END:%.*]]
645 // CHECK1: cond.false:
646 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
647 // CHECK1-NEXT: br label [[COND_END]]
648 // CHECK1: cond.end:
649 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
650 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
651 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
652 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
653 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
654 // CHECK1: omp.inner.for.cond:
655 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
656 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
657 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
658 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
659 // CHECK1: omp.inner.for.cond.cleanup:
660 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
661 // CHECK1: omp.inner.for.body:
662 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
663 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
664 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
665 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
666 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
667 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
668 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
669 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
670 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
671 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
672 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
673 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
674 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
675 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
676 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
677 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
678 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
679 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
680 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
681 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
682 // CHECK1: omp.body.continue:
683 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
684 // CHECK1: omp.inner.for.inc:
685 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
686 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
687 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
688 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
689 // CHECK1: omp.inner.for.end:
690 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
691 // CHECK1: omp.loop.exit:
692 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
693 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
694 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
695 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
696 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
697 // CHECK1-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
698 // CHECK1: .omp.final.then:
699 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
700 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
701 // CHECK1: .omp.final.done:
702 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
703 // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
704 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
705 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
706 // CHECK1: arraydestroy.body:
707 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
708 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
709 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
710 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
711 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
712 // CHECK1: arraydestroy.done15:
713 // CHECK1-NEXT: ret void
714 //
715 //
716 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
717 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
718 // CHECK1-NEXT: entry:
719 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
720 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
721 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
722 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
723 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
724 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
725 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
726 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
727 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
728 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
729 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
730 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
731 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
732 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
733 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
734 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
735 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
736 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
737 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
738 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
739 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
740 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
741 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
742 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
743 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
744 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
745 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
746 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
747 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
748 // CHECK1-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
749 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
750 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
751 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8
752 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
753 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
754 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
755 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
756 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8
757 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
758 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
759 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8
760 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
761 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
762 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8
763 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
764 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8
765 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
766 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
767 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
768 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
769 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
770 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8
771 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
772 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
773 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
774 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
775 // CHECK1-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8
776 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
777 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
778 // CHECK1-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8
779 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
780 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8
781 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
782 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
783 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
784 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
785 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
786 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
787 // CHECK1: omp_offload.failed:
788 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
789 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
790 // CHECK1: omp_offload.cont:
791 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
792 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
793 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
794 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
795 // CHECK1: arraydestroy.body:
796 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
797 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
798 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
799 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
800 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
801 // CHECK1: arraydestroy.done2:
802 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
803 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4
804 // CHECK1-NEXT: ret i32 [[TMP32]]
805 //
806 //
807 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
808 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
809 // CHECK1-NEXT: entry:
810 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
811 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
812 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
813 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
814 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4
815 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
816 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4
817 // CHECK1-NEXT: ret void
818 //
819 //
820 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
821 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
822 // CHECK1-NEXT: entry:
823 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
824 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
825 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
826 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
827 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
828 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
829 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
830 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
831 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
832 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
833 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
834 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
835 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
836 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
837 // CHECK1-NEXT: ret void
838 //
839 //
840 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
841 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
842 // CHECK1-NEXT: entry:
843 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
844 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
845 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
846 // CHECK1-NEXT: ret void
847 //
848 //
849 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
850 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
851 // CHECK1-NEXT: entry:
852 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
853 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
854 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
855 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
856 // CHECK1-NEXT: ret void
857 //
858 //
859 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
860 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
861 // CHECK1-NEXT: entry:
862 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
863 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
864 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
865 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
866 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
867 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
868 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
869 // CHECK1-NEXT: ret void
870 //
871 //
872 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
873 // CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
874 // CHECK1-NEXT: entry:
875 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
876 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
877 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
878 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
879 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
880 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
881 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
882 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
883 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
884 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
885 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
886 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
887 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
888 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
889 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
890 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
891 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
892 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
893 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
894 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
895 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
896 // CHECK1-NEXT: ret void
897 //
898 //
899 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
900 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
901 // CHECK1-NEXT: entry:
902 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
903 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
904 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
905 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
906 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
907 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
908 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
909 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
910 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
911 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
912 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
913 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
914 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
915 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
916 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
917 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
918 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
919 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
920 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
921 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
922 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
923 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
924 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
925 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
926 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
927 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
928 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
929 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
930 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
931 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
932 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
933 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
934 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
935 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
936 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
937 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
938 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
939 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
940 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
941 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
942 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
943 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
944 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
945 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
946 // CHECK1: omp.arraycpy.body:
947 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
948 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
949 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
950 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
951 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
952 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
953 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
954 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
955 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
956 // CHECK1: omp.arraycpy.done4:
957 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
958 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
959 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
960 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
961 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
962 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
963 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
964 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
965 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
966 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
967 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
968 // CHECK1: cond.true:
969 // CHECK1-NEXT: br label [[COND_END:%.*]]
970 // CHECK1: cond.false:
971 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
972 // CHECK1-NEXT: br label [[COND_END]]
973 // CHECK1: cond.end:
974 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
975 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
976 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
977 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
978 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
979 // CHECK1: omp.inner.for.cond:
980 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
981 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
982 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
983 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
984 // CHECK1: omp.inner.for.cond.cleanup:
985 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
986 // CHECK1: omp.inner.for.body:
987 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
988 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
989 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
990 // CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
991 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
992 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
993 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
994 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
995 // CHECK1-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
996 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
997 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
998 // CHECK1: omp.inner.for.inc:
999 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1000 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1001 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1002 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1003 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
1004 // CHECK1: omp.inner.for.end:
1005 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1006 // CHECK1: omp.loop.exit:
1007 // CHECK1-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1008 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
1009 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
1010 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1011 // CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
1012 // CHECK1-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1013 // CHECK1: .omp.final.then:
1014 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
1015 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1016 // CHECK1: .omp.final.done:
1017 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1018 // CHECK1-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
1019 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
1020 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1021 // CHECK1: arraydestroy.body:
1022 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1023 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1024 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1025 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1026 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1027 // CHECK1: arraydestroy.done11:
1028 // CHECK1-NEXT: ret void
1029 //
1030 //
1031 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
1032 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1033 // CHECK1-NEXT: entry:
1034 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1035 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1036 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1037 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1038 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1039 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1040 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
1041 // CHECK1-NEXT: ret void
1042 //
1043 //
1044 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
1045 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1046 // CHECK1-NEXT: entry:
1047 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1048 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1049 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1050 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1051 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1052 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1053 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1054 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1055 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1056 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1057 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1058 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1059 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1060 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1061 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1062 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1063 // CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1064 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1065 // CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1066 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
1067 // CHECK1-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
1068 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1069 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1070 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1071 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1072 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1073 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1074 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1075 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1076 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1077 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1078 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1079 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1080 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1081 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1082 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1083 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1084 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1085 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
1086 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1087 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
1088 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
1089 // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
1090 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1091 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1092 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
1093 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1094 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
1095 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
1096 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
1097 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1098 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
1099 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1100 // CHECK1: omp.arraycpy.body:
1101 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1102 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1103 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1104 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1105 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1106 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1107 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1108 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
1109 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1110 // CHECK1: omp.arraycpy.done6:
1111 // CHECK1-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1112 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
1113 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]])
1114 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
1115 // CHECK1-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
1116 // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1117 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
1118 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1119 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1120 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
1121 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1122 // CHECK1: cond.true:
1123 // CHECK1-NEXT: br label [[COND_END:%.*]]
1124 // CHECK1: cond.false:
1125 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1126 // CHECK1-NEXT: br label [[COND_END]]
1127 // CHECK1: cond.end:
1128 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1129 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1130 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1131 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
1132 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1133 // CHECK1: omp.inner.for.cond:
1134 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1135 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1136 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
1137 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1138 // CHECK1: omp.inner.for.cond.cleanup:
1139 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1140 // CHECK1: omp.inner.for.body:
1141 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1142 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
1143 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1144 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1145 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
1146 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1147 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
1148 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
1149 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
1150 // CHECK1-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
1151 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
1152 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
1153 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
1154 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
1155 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
1156 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false)
1157 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1158 // CHECK1: omp.body.continue:
1159 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1160 // CHECK1: omp.inner.for.inc:
1161 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1162 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
1163 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
1164 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1165 // CHECK1: omp.inner.for.end:
1166 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1167 // CHECK1: omp.loop.exit:
1168 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1169 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1170 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1171 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1172 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1173 // CHECK1-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1174 // CHECK1: .omp.final.then:
1175 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
1176 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
1177 // CHECK1: .omp.final.done:
1178 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
1179 // CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
1180 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
1181 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1182 // CHECK1: arraydestroy.body:
1183 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1184 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1185 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1186 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1187 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1188 // CHECK1: arraydestroy.done15:
1189 // CHECK1-NEXT: ret void
1190 //
1191 //
1192 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1193 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1194 // CHECK1-NEXT: entry:
1195 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1196 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1197 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1198 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1199 // CHECK1-NEXT: ret void
1200 //
1201 //
1202 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1203 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1204 // CHECK1-NEXT: entry:
1205 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1206 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1207 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1208 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1209 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1210 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1211 // CHECK1-NEXT: ret void
1212 //
1213 //
1214 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1215 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1216 // CHECK1-NEXT: entry:
1217 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1218 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1219 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1220 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1221 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1222 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1223 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1224 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1225 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1226 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1227 // CHECK1-NEXT: ret void
1228 //
1229 //
1230 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
1231 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1232 // CHECK1-NEXT: entry:
1233 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1234 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
1235 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1236 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
1237 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1238 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1239 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
1240 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
1241 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
1242 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1243 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1244 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
1245 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1246 // CHECK1-NEXT: ret void
1247 //
1248 //
1249 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1250 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1251 // CHECK1-NEXT: entry:
1252 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1253 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1254 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1255 // CHECK1-NEXT: ret void
1256 //
1257 //
1258 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
1259 // CHECK1-SAME: () #[[ATTR0]] {
1260 // CHECK1-NEXT: entry:
1261 // CHECK1-NEXT: call void @__cxx_global_var_init()
1262 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
1263 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
1264 // CHECK1-NEXT: ret void
1265 //
1266 //
1267 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1268 // CHECK1-SAME: () #[[ATTR0]] {
1269 // CHECK1-NEXT: entry:
1270 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
1271 // CHECK1-NEXT: ret void
1272 //
1273 //
1274 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
1275 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
1276 // CHECK2-NEXT: entry:
1277 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1278 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1279 // CHECK2-NEXT: ret void
1280 //
1281 //
1282 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1283 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1284 // CHECK2-NEXT: entry:
1285 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1286 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1287 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1288 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1289 // CHECK2-NEXT: ret void
1290 //
1291 //
1292 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1293 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1294 // CHECK2-NEXT: entry:
1295 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1296 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1297 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1298 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1299 // CHECK2-NEXT: ret void
1300 //
1301 //
1302 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1303 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1304 // CHECK2-NEXT: entry:
1305 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1306 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1307 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1308 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1309 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1310 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1311 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4
1312 // CHECK2-NEXT: ret void
1313 //
1314 //
1315 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1316 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1317 // CHECK2-NEXT: entry:
1318 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1319 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1320 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1321 // CHECK2-NEXT: ret void
1322 //
1323 //
1324 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1325 // CHECK2-SAME: () #[[ATTR0]] {
1326 // CHECK2-NEXT: entry:
1327 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
1328 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
1329 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1330 // CHECK2-NEXT: ret void
1331 //
1332 //
1333 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1334 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1335 // CHECK2-NEXT: entry:
1336 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1337 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1338 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1339 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1340 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1341 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1342 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1343 // CHECK2-NEXT: ret void
1344 //
1345 //
1346 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1347 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1348 // CHECK2-NEXT: entry:
1349 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
1350 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1351 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1352 // CHECK2: arraydestroy.body:
1353 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1354 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1355 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1356 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1357 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1358 // CHECK2: arraydestroy.done1:
1359 // CHECK2-NEXT: ret void
1360 //
1361 //
1362 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1363 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1364 // CHECK2-NEXT: entry:
1365 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1366 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1367 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1368 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1369 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1370 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1371 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1372 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1373 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1374 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1375 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
1376 // CHECK2-NEXT: ret void
1377 //
1378 //
1379 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1380 // CHECK2-SAME: () #[[ATTR0]] {
1381 // CHECK2-NEXT: entry:
1382 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1383 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1384 // CHECK2-NEXT: ret void
1385 //
1386 //
1387 // CHECK2-LABEL: define {{[^@]+}}@main
1388 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
1389 // CHECK2-NEXT: entry:
1390 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1391 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1392 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1393 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1394 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1395 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1396 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1397 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
1398 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
1399 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1400 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
1401 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1402 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
1403 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1404 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4
1405 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1406 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1407 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
1408 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
1409 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1410 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
1411 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
1412 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1413 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8
1414 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1415 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
1416 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8
1417 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1418 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
1419 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8
1420 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1421 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8
1422 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1423 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
1424 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8
1425 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1426 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
1427 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8
1428 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1429 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8
1430 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1431 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
1432 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8
1433 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1434 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
1435 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8
1436 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1437 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8
1438 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1439 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1440 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8
1441 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1442 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
1443 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8
1444 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1445 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8
1446 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1447 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1448 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
1449 // CHECK2-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1450 // CHECK2-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1451 // CHECK2-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1452 // CHECK2: omp_offload.failed:
1453 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]]
1454 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1455 // CHECK2: omp_offload.cont:
1456 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
1457 // CHECK2-NEXT: ret i32 [[CALL]]
1458 //
1459 //
1460 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101
1461 // CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
1462 // CHECK2-NEXT: entry:
1463 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1464 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1465 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1466 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1467 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1468 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1469 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1470 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1471 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1472 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1473 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1474 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1475 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1476 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1477 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1478 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1479 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1480 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1481 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1482 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4
1483 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1484 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
1485 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1486 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4
1487 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1488 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]])
1489 // CHECK2-NEXT: ret void
1490 //
1491 //
1492 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1493 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
1494 // CHECK2-NEXT: entry:
1495 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1496 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1497 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1498 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1499 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1500 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1501 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1502 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1503 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1504 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1505 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1506 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1507 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1508 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
1509 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
1510 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1511 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1512 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
1513 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1514 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1515 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1516 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1517 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1518 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1519 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1520 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1521 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1522 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1523 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1524 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1525 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1526 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1527 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1528 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
1529 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
1530 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1531 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1532 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
1533 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1534 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
1535 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
1536 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1537 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1538 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
1539 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1540 // CHECK2: omp.arraycpy.body:
1541 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1542 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1543 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1544 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1545 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1546 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1547 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1548 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
1549 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
1550 // CHECK2: omp.arraycpy.done4:
1551 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
1552 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]])
1553 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
1554 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1555 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1556 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1557 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1558 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1559 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1560 // CHECK2: cond.true:
1561 // CHECK2-NEXT: br label [[COND_END:%.*]]
1562 // CHECK2: cond.false:
1563 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1564 // CHECK2-NEXT: br label [[COND_END]]
1565 // CHECK2: cond.end:
1566 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1567 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
1568 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1569 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
1570 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1571 // CHECK2: omp.inner.for.cond:
1572 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1573 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1574 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1575 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1576 // CHECK2: omp.inner.for.cond.cleanup:
1577 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1578 // CHECK2: omp.inner.for.body:
1579 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
1580 // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
1581 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
1582 // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
1583 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
1584 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1585 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV8]], align 4
1586 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1587 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[CONV1]], align 8
1588 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
1589 // CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV9]], align 4
1590 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
1591 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], [2 x i32]* [[VEC2]], i64 [[TMP19]], [2 x %struct.S]* [[S_ARR3]], %struct.S* [[VAR5]], i64 [[TMP21]])
1592 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1593 // CHECK2: omp.inner.for.inc:
1594 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1595 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
1596 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1597 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
1598 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1599 // CHECK2: omp.inner.for.end:
1600 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1601 // CHECK2: omp.loop.exit:
1602 // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1603 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
1604 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
1605 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1606 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
1607 // CHECK2-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1608 // CHECK2: .omp.final.then:
1609 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1610 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1611 // CHECK2: .omp.final.done:
1612 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1613 // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0
1614 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i64 2
1615 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1616 // CHECK2: arraydestroy.body:
1617 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1618 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1619 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1620 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1621 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1622 // CHECK2: arraydestroy.done11:
1623 // CHECK2-NEXT: ret void
1624 //
1625 //
1626 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1627 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1628 // CHECK2-NEXT: entry:
1629 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1630 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1631 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1632 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
1633 // CHECK2-NEXT: ret void
1634 //
1635 //
1636 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1637 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1638 // CHECK2-NEXT: entry:
1639 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1640 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
1641 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1642 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
1643 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1644 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
1645 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
1646 // CHECK2-NEXT: ret void
1647 //
1648 //
1649 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1650 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1651 // CHECK2-NEXT: entry:
1652 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1653 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1654 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1655 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
1656 // CHECK2-NEXT: ret void
1657 //
1658 //
1659 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
1660 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] {
1661 // CHECK2-NEXT: entry:
1662 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1663 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1664 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1665 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1666 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1667 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1668 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
1669 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
1670 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1671 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1672 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1673 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1674 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1675 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1676 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1677 // CHECK2-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1678 // CHECK2-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
1679 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1680 // CHECK2-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1681 // CHECK2-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
1682 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1683 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1684 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1685 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1686 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1687 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1688 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1689 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1690 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
1691 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
1692 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1693 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1694 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
1695 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
1696 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
1697 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1698 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1699 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
1700 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
1701 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
1702 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
1703 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
1704 // CHECK2-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
1705 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1706 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1707 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
1708 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
1709 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
1710 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
1711 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
1712 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
1713 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
1714 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1715 // CHECK2: omp.arraycpy.body:
1716 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1717 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1718 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1719 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
1720 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1721 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1722 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1723 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
1724 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
1725 // CHECK2: omp.arraycpy.done6:
1726 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
1727 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP8]])
1728 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
1729 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1730 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
1731 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1732 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1733 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
1734 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1735 // CHECK2: cond.true:
1736 // CHECK2-NEXT: br label [[COND_END:%.*]]
1737 // CHECK2: cond.false:
1738 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1739 // CHECK2-NEXT: br label [[COND_END]]
1740 // CHECK2: cond.end:
1741 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1742 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1743 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1744 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
1745 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1746 // CHECK2: omp.inner.for.cond:
1747 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1748 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1749 // CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1750 // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1751 // CHECK2: omp.inner.for.cond.cleanup:
1752 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1753 // CHECK2: omp.inner.for.body:
1754 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1755 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
1756 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1757 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1758 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 8
1759 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
1760 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
1761 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
1762 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
1763 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
1764 // CHECK2-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
1765 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
1766 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8*
1767 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR7]] to i8*
1768 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false)
1769 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
1770 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[CONV1]], align 8
1771 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
1772 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[CONV1]], align 8
1773 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1774 // CHECK2: omp.body.continue:
1775 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1776 // CHECK2: omp.inner.for.inc:
1777 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1778 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
1779 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
1780 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
1781 // CHECK2: omp.inner.for.end:
1782 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1783 // CHECK2: omp.loop.exit:
1784 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1785 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
1786 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
1787 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1788 // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1789 // CHECK2-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1790 // CHECK2: .omp.final.then:
1791 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1792 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1793 // CHECK2: .omp.final.done:
1794 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
1795 // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0
1796 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2
1797 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1798 // CHECK2: arraydestroy.body:
1799 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1800 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1801 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1802 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1803 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1804 // CHECK2: arraydestroy.done15:
1805 // CHECK2-NEXT: ret void
1806 //
1807 //
1808 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1809 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat {
1810 // CHECK2-NEXT: entry:
1811 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1812 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1813 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1814 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1815 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1816 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
1817 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1818 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1819 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
1820 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
1821 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
1822 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1823 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1824 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4
1825 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1826 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
1827 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
1828 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
1829 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1830 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
1831 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
1832 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
1833 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
1834 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
1835 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1836 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4
1837 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1838 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1839 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1840 // CHECK2-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1841 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1842 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1843 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8
1844 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1845 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1846 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
1847 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1848 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8
1849 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1850 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
1851 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8
1852 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1853 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
1854 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8
1855 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1856 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8
1857 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1858 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
1859 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8
1860 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1861 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
1862 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8
1863 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1864 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8
1865 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1866 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
1867 // CHECK2-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8
1868 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1869 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
1870 // CHECK2-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8
1871 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1872 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8
1873 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1874 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1875 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
1876 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
1877 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1878 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1879 // CHECK2: omp_offload.failed:
1880 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
1881 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
1882 // CHECK2: omp_offload.cont:
1883 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
1884 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1885 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1886 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1887 // CHECK2: arraydestroy.body:
1888 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1889 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1890 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1891 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1892 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1893 // CHECK2: arraydestroy.done2:
1894 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1895 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4
1896 // CHECK2-NEXT: ret i32 [[TMP32]]
1897 //
1898 //
1899 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1900 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1901 // CHECK2-NEXT: entry:
1902 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1903 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1904 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1905 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
1906 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4
1907 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
1908 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4
1909 // CHECK2-NEXT: ret void
1910 //
1911 //
1912 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1913 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1914 // CHECK2-NEXT: entry:
1915 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1916 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
1917 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1918 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
1919 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1920 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1921 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
1922 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
1923 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
1924 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
1925 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
1926 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1927 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1928 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
1929 // CHECK2-NEXT: ret void
1930 //
1931 //
1932 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1933 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1934 // CHECK2-NEXT: entry:
1935 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1936 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1937 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1938 // CHECK2-NEXT: ret void
1939 //
1940 //
1941 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1942 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1943 // CHECK2-NEXT: entry:
1944 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1945 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1946 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1947 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1948 // CHECK2-NEXT: ret void
1949 //
1950 //
1951 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1952 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1953 // CHECK2-NEXT: entry:
1954 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1955 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1956 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1957 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1958 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1959 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1960 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
1961 // CHECK2-NEXT: ret void
1962 //
1963 //
1964 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1965 // CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1966 // CHECK2-NEXT: entry:
1967 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1968 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1969 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1970 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
1971 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
1972 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1973 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
1974 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
1975 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1976 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
1977 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
1978 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
1979 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
1980 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
1981 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
1982 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8
1983 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
1984 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4
1985 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
1986 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
1987 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
1988 // CHECK2-NEXT: ret void
1989 //
1990 //
1991 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
1992 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1993 // CHECK2-NEXT: entry:
1994 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1995 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1996 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
1997 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1998 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
1999 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
2000 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
2001 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2002 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2003 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2004 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2005 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2006 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2007 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
2008 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2009 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2010 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2011 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2012 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8
2013 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
2014 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
2015 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2016 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2017 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2018 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
2019 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2020 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
2021 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2022 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
2023 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2024 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
2025 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
2026 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2027 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2028 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2029 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2030 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
2031 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2032 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false)
2033 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2034 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2035 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2036 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
2037 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2038 // CHECK2: omp.arraycpy.body:
2039 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2040 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2041 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2042 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2043 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2044 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2045 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2046 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2047 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2048 // CHECK2: omp.arraycpy.done4:
2049 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
2050 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2051 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
2052 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2053 // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8
2054 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2055 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
2056 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2057 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2058 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
2059 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2060 // CHECK2: cond.true:
2061 // CHECK2-NEXT: br label [[COND_END:%.*]]
2062 // CHECK2: cond.false:
2063 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2064 // CHECK2-NEXT: br label [[COND_END]]
2065 // CHECK2: cond.end:
2066 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
2067 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2068 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2069 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
2070 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2071 // CHECK2: omp.inner.for.cond:
2072 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2073 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2074 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
2075 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2076 // CHECK2: omp.inner.for.cond.cleanup:
2077 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2078 // CHECK2: omp.inner.for.body:
2079 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2080 // CHECK2-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
2081 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2082 // CHECK2-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
2083 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 8
2084 // CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
2085 // CHECK2-NEXT: store i32 [[TMP19]], i32* [[CONV9]], align 4
2086 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
2087 // CHECK2-NEXT: [[TMP21:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8
2088 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP16]], i64 [[TMP18]], [2 x i32]* [[VEC2]], i64 [[TMP20]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP21]])
2089 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2090 // CHECK2: omp.inner.for.inc:
2091 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2092 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2093 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
2094 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2095 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2096 // CHECK2: omp.inner.for.end:
2097 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2098 // CHECK2: omp.loop.exit:
2099 // CHECK2-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2100 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4
2101 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]])
2102 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2103 // CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
2104 // CHECK2-NEXT: br i1 [[TMP27]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2105 // CHECK2: .omp.final.then:
2106 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
2107 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
2108 // CHECK2: .omp.final.done:
2109 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2110 // CHECK2-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
2111 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
2112 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2113 // CHECK2: arraydestroy.body:
2114 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2115 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2116 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2117 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2118 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2119 // CHECK2: arraydestroy.done11:
2120 // CHECK2-NEXT: ret void
2121 //
2122 //
2123 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
2124 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2125 // CHECK2-NEXT: entry:
2126 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2127 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
2128 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2129 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
2130 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2131 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
2132 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
2133 // CHECK2-NEXT: ret void
2134 //
2135 //
2136 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5
2137 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
2138 // CHECK2-NEXT: entry:
2139 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2140 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2141 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2142 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2143 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2144 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
2145 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
2146 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
2147 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
2148 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2149 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2150 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2151 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2152 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2153 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2154 // CHECK2-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
2155 // CHECK2-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
2156 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2157 // CHECK2-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2158 // CHECK2-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
2159 // CHECK2-NEXT: [[_TMP9:%.*]] = alloca %struct.S.0*, align 8
2160 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
2161 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2162 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2163 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2164 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2165 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2166 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
2167 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2168 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
2169 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2170 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
2171 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2172 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
2173 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8
2174 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2175 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2176 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
2177 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32
2178 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
2179 // CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP4]] to i32
2180 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_LB]], align 4
2181 // CHECK2-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_UB]], align 4
2182 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2183 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2184 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8*
2185 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2186 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false)
2187 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
2188 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
2189 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2190 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
2191 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2192 // CHECK2: omp.arraycpy.body:
2193 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2194 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2195 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2196 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2197 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2198 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2199 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2200 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
2201 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
2202 // CHECK2: omp.arraycpy.done6:
2203 // CHECK2-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
2204 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
2205 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP8]])
2206 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
2207 // CHECK2-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP9]], align 8
2208 // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2209 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
2210 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2211 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2212 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
2213 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2214 // CHECK2: cond.true:
2215 // CHECK2-NEXT: br label [[COND_END:%.*]]
2216 // CHECK2: cond.false:
2217 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2218 // CHECK2-NEXT: br label [[COND_END]]
2219 // CHECK2: cond.end:
2220 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
2221 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2222 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2223 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
2224 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2225 // CHECK2: omp.inner.for.cond:
2226 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2227 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2228 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
2229 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2230 // CHECK2: omp.inner.for.cond.cleanup:
2231 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2232 // CHECK2: omp.inner.for.body:
2233 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2234 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
2235 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2236 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2237 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8
2238 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
2239 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
2240 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]]
2241 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
2242 // CHECK2-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP9]], align 8
2243 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
2244 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64
2245 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
2246 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX12]] to i8*
2247 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
2248 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i64 4, i1 false)
2249 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2250 // CHECK2: omp.body.continue:
2251 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2252 // CHECK2: omp.inner.for.inc:
2253 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2254 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP24]], 1
2255 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4
2256 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
2257 // CHECK2: omp.inner.for.end:
2258 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2259 // CHECK2: omp.loop.exit:
2260 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2261 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
2262 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
2263 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2264 // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2265 // CHECK2-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2266 // CHECK2: .omp.final.then:
2267 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
2268 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
2269 // CHECK2: .omp.final.done:
2270 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
2271 // CHECK2-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0
2272 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN14]], i64 2
2273 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2274 // CHECK2: arraydestroy.body:
2275 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2276 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2277 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2278 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
2279 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
2280 // CHECK2: arraydestroy.done15:
2281 // CHECK2-NEXT: ret void
2282 //
2283 //
2284 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2285 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2286 // CHECK2-NEXT: entry:
2287 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2288 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2289 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2290 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2291 // CHECK2-NEXT: ret void
2292 //
2293 //
2294 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2295 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2296 // CHECK2-NEXT: entry:
2297 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2298 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2299 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2300 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2301 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2302 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2303 // CHECK2-NEXT: ret void
2304 //
2305 //
2306 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2307 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2308 // CHECK2-NEXT: entry:
2309 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2310 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2311 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2312 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2313 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2314 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2315 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2316 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2317 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2318 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2319 // CHECK2-NEXT: ret void
2320 //
2321 //
2322 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2323 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2324 // CHECK2-NEXT: entry:
2325 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2326 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
2327 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2328 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
2329 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2330 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2331 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
2332 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
2333 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
2334 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2335 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2336 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2337 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2338 // CHECK2-NEXT: ret void
2339 //
2340 //
2341 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2342 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2343 // CHECK2-NEXT: entry:
2344 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2345 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2346 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2347 // CHECK2-NEXT: ret void
2348 //
2349 //
2350 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
2351 // CHECK2-SAME: () #[[ATTR0]] {
2352 // CHECK2-NEXT: entry:
2353 // CHECK2-NEXT: call void @__cxx_global_var_init()
2354 // CHECK2-NEXT: call void @__cxx_global_var_init.1()
2355 // CHECK2-NEXT: call void @__cxx_global_var_init.2()
2356 // CHECK2-NEXT: ret void
2357 //
2358 //
2359 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2360 // CHECK2-SAME: () #[[ATTR0]] {
2361 // CHECK2-NEXT: entry:
2362 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
2363 // CHECK2-NEXT: ret void
2364 //
2365 //
2366 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
2367 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
2368 // CHECK3-NEXT: entry:
2369 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2370 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2371 // CHECK3-NEXT: ret void
2372 //
2373 //
2374 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2375 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2376 // CHECK3-NEXT: entry:
2377 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2378 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2379 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2380 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2381 // CHECK3-NEXT: ret void
2382 //
2383 //
2384 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2385 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2386 // CHECK3-NEXT: entry:
2387 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2388 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2389 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2390 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2391 // CHECK3-NEXT: ret void
2392 //
2393 //
2394 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2395 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2396 // CHECK3-NEXT: entry:
2397 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2398 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2399 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2400 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2401 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2402 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2403 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
2404 // CHECK3-NEXT: ret void
2405 //
2406 //
2407 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2408 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2409 // CHECK3-NEXT: entry:
2410 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2411 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2412 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2413 // CHECK3-NEXT: ret void
2414 //
2415 //
2416 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2417 // CHECK3-SAME: () #[[ATTR0]] {
2418 // CHECK3-NEXT: entry:
2419 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
2420 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
2421 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2422 // CHECK3-NEXT: ret void
2423 //
2424 //
2425 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2426 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2427 // CHECK3-NEXT: entry:
2428 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2429 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2430 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2431 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2432 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2433 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2434 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2435 // CHECK3-NEXT: ret void
2436 //
2437 //
2438 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2439 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2440 // CHECK3-NEXT: entry:
2441 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
2442 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
2443 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2444 // CHECK3: arraydestroy.body:
2445 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2446 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2447 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2448 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2449 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2450 // CHECK3: arraydestroy.done1:
2451 // CHECK3-NEXT: ret void
2452 //
2453 //
2454 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2455 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2456 // CHECK3-NEXT: entry:
2457 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2458 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2459 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2460 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2461 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2462 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2463 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2464 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2465 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2466 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2467 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
2468 // CHECK3-NEXT: ret void
2469 //
2470 //
2471 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2472 // CHECK3-SAME: () #[[ATTR0]] {
2473 // CHECK3-NEXT: entry:
2474 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2475 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2476 // CHECK3-NEXT: ret void
2477 //
2478 //
2479 // CHECK3-LABEL: define {{[^@]+}}@main
2480 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
2481 // CHECK3-NEXT: entry:
2482 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2483 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2484 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
2485 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
2486 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
2487 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
2488 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2489 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
2490 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
2491 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4
2492 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2493 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
2494 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4
2495 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
2496 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2497 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
2498 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
2499 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2500 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
2501 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
2502 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2503 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
2504 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2505 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
2506 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4
2507 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2508 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
2509 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4
2510 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2511 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
2512 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2513 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
2514 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4
2515 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2516 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
2517 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4
2518 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2519 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
2520 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2521 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
2522 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4
2523 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2524 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
2525 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4
2526 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2527 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4
2528 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2529 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
2530 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4
2531 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2532 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
2533 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4
2534 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2535 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4
2536 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2537 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2538 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
2539 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2540 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2541 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2542 // CHECK3: omp_offload.failed:
2543 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]]
2544 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2545 // CHECK3: omp_offload.cont:
2546 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
2547 // CHECK3-NEXT: ret i32 [[CALL]]
2548 //
2549 //
2550 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101
2551 // CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
2552 // CHECK3-NEXT: entry:
2553 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2554 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2555 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2556 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2557 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
2558 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2559 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
2560 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2561 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2562 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2563 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2564 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
2565 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2566 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2567 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2568 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2569 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
2570 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2571 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2572 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
2573 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
2574 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
2575 // CHECK3-NEXT: ret void
2576 //
2577 //
2578 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
2579 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
2580 // CHECK3-NEXT: entry:
2581 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2582 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2583 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2584 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2585 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2586 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2587 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
2588 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2589 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2590 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2591 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2592 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2593 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2594 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
2595 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
2596 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2597 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2598 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
2599 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2600 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2601 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
2602 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2603 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2604 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2605 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2606 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2607 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2608 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
2609 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2610 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2611 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2612 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
2613 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
2614 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2615 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2616 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
2617 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2618 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
2619 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2620 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
2621 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2622 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
2623 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2624 // CHECK3: omp.arraycpy.body:
2625 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2626 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2627 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2628 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2629 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2630 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2631 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2632 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
2633 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
2634 // CHECK3: omp.arraycpy.done3:
2635 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
2636 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
2637 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
2638 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2639 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
2640 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2641 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2642 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
2643 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2644 // CHECK3: cond.true:
2645 // CHECK3-NEXT: br label [[COND_END:%.*]]
2646 // CHECK3: cond.false:
2647 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2648 // CHECK3-NEXT: br label [[COND_END]]
2649 // CHECK3: cond.end:
2650 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2651 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
2652 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2653 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
2654 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2655 // CHECK3: omp.inner.for.cond:
2656 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2657 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2658 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
2659 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2660 // CHECK3: omp.inner.for.cond.cleanup:
2661 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2662 // CHECK3: omp.inner.for.body:
2663 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
2664 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
2665 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2666 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4
2667 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2668 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2669 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4
2670 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
2671 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]])
2672 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2673 // CHECK3: omp.inner.for.inc:
2674 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2675 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
2676 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
2677 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
2678 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2679 // CHECK3: omp.inner.for.end:
2680 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2681 // CHECK3: omp.loop.exit:
2682 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2683 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
2684 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
2685 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2686 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
2687 // CHECK3-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2688 // CHECK3: .omp.final.then:
2689 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
2690 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2691 // CHECK3: .omp.final.done:
2692 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
2693 // CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2694 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
2695 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2696 // CHECK3: arraydestroy.body:
2697 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2698 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2699 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2700 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
2701 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
2702 // CHECK3: arraydestroy.done8:
2703 // CHECK3-NEXT: ret void
2704 //
2705 //
2706 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev
2707 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2708 // CHECK3-NEXT: entry:
2709 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2710 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2711 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2712 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
2713 // CHECK3-NEXT: ret void
2714 //
2715 //
2716 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
2717 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2718 // CHECK3-NEXT: entry:
2719 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2720 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
2721 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2722 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
2723 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2724 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
2725 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
2726 // CHECK3-NEXT: ret void
2727 //
2728 //
2729 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev
2730 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2731 // CHECK3-NEXT: entry:
2732 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2733 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2734 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2735 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
2736 // CHECK3-NEXT: ret void
2737 //
2738 //
2739 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
2740 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
2741 // CHECK3-NEXT: entry:
2742 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2743 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2744 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2745 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2746 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
2747 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2748 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
2749 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
2750 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
2751 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2752 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2753 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2754 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2755 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2756 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2757 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
2758 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
2759 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2760 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2761 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
2762 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2763 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2764 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2765 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2766 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2767 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
2768 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
2769 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2770 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
2771 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
2772 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
2773 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
2774 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
2775 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2776 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2777 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
2778 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
2779 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
2780 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
2781 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
2782 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
2783 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
2784 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
2785 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
2786 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2787 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
2788 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2789 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
2790 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2791 // CHECK3: omp.arraycpy.body:
2792 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2793 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2794 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2795 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
2796 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2797 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2798 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2799 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
2800 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
2801 // CHECK3: omp.arraycpy.done3:
2802 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
2803 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
2804 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
2805 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2806 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2807 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
2808 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2809 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
2810 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2811 // CHECK3: cond.true:
2812 // CHECK3-NEXT: br label [[COND_END:%.*]]
2813 // CHECK3: cond.false:
2814 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2815 // CHECK3-NEXT: br label [[COND_END]]
2816 // CHECK3: cond.end:
2817 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2818 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2819 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2820 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
2821 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2822 // CHECK3: omp.inner.for.cond:
2823 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2824 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2825 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
2826 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2827 // CHECK3: omp.inner.for.cond.cleanup:
2828 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2829 // CHECK3: omp.inner.for.body:
2830 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2831 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
2832 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2833 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2834 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
2835 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
2836 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
2837 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
2838 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
2839 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
2840 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
2841 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
2842 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
2843 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
2844 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
2845 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
2846 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
2847 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2848 // CHECK3: omp.body.continue:
2849 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2850 // CHECK3: omp.inner.for.inc:
2851 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2852 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
2853 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
2854 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2855 // CHECK3: omp.inner.for.end:
2856 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2857 // CHECK3: omp.loop.exit:
2858 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2859 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
2860 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
2861 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2862 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2863 // CHECK3-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2864 // CHECK3: .omp.final.then:
2865 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
2866 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
2867 // CHECK3: .omp.final.done:
2868 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
2869 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
2870 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
2871 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2872 // CHECK3: arraydestroy.body:
2873 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2874 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2875 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2876 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2877 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2878 // CHECK3: arraydestroy.done11:
2879 // CHECK3-NEXT: ret void
2880 //
2881 //
2882 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2883 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
2884 // CHECK3-NEXT: entry:
2885 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2886 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2887 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2888 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2889 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2890 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
2891 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
2892 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2893 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
2894 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
2895 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
2896 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2897 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2898 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
2899 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2900 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
2901 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2902 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
2903 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
2904 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
2905 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
2906 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
2907 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
2908 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
2909 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
2910 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
2911 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2912 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2913 // CHECK3-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
2914 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2915 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
2916 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4
2917 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2918 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
2919 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
2920 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2921 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4
2922 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2923 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
2924 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4
2925 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2926 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
2927 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4
2928 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2929 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4
2930 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2931 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
2932 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
2933 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2934 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
2935 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4
2936 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2937 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
2938 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2939 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
2940 // CHECK3-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4
2941 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2942 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
2943 // CHECK3-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4
2944 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2945 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4
2946 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2947 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2948 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
2949 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
2950 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2951 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2952 // CHECK3: omp_offload.failed:
2953 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
2954 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2955 // CHECK3: omp_offload.cont:
2956 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
2957 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2958 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
2959 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2960 // CHECK3: arraydestroy.body:
2961 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2962 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2963 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2964 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2965 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2966 // CHECK3: arraydestroy.done2:
2967 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2968 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4
2969 // CHECK3-NEXT: ret i32 [[TMP32]]
2970 //
2971 //
2972 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev
2973 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2974 // CHECK3-NEXT: entry:
2975 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
2976 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
2977 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
2978 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
2979 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4
2980 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
2981 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4
2982 // CHECK3-NEXT: ret void
2983 //
2984 //
2985 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
2986 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2987 // CHECK3-NEXT: entry:
2988 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2989 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
2990 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2991 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
2992 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2993 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2994 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
2995 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
2996 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
2997 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
2998 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2999 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
3000 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
3001 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
3002 // CHECK3-NEXT: ret void
3003 //
3004 //
3005 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev
3006 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3007 // CHECK3-NEXT: entry:
3008 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3009 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3010 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3011 // CHECK3-NEXT: ret void
3012 //
3013 //
3014 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3015 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3016 // CHECK3-NEXT: entry:
3017 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3018 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3019 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3020 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3021 // CHECK3-NEXT: ret void
3022 //
3023 //
3024 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3025 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3026 // CHECK3-NEXT: entry:
3027 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3028 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3029 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3030 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3031 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3032 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3033 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
3034 // CHECK3-NEXT: ret void
3035 //
3036 //
3037 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
3038 // CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
3039 // CHECK3-NEXT: entry:
3040 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3041 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3042 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
3043 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
3044 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3045 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3046 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3047 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3048 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3049 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
3050 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3051 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3052 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
3053 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
3054 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3055 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
3056 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3057 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3058 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
3059 // CHECK3-NEXT: ret void
3060 //
3061 //
3062 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
3063 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
3064 // CHECK3-NEXT: entry:
3065 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3066 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3067 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3068 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3069 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
3070 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
3071 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3072 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3073 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3074 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3075 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3076 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3077 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3078 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
3079 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
3080 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3081 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3082 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
3083 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
3084 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
3085 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3086 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3087 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3088 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3089 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3090 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3091 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
3092 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3093 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3094 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
3095 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
3096 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3097 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3098 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3099 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3100 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
3101 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3102 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
3103 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3104 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
3105 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3106 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
3107 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3108 // CHECK3: omp.arraycpy.body:
3109 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3110 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3111 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3112 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3113 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3114 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3115 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3116 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
3117 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
3118 // CHECK3: omp.arraycpy.done4:
3119 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3120 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
3121 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
3122 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
3123 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
3124 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3125 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
3126 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3127 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3128 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
3129 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3130 // CHECK3: cond.true:
3131 // CHECK3-NEXT: br label [[COND_END:%.*]]
3132 // CHECK3: cond.false:
3133 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3134 // CHECK3-NEXT: br label [[COND_END]]
3135 // CHECK3: cond.end:
3136 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
3137 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3138 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3139 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
3140 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3141 // CHECK3: omp.inner.for.cond:
3142 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3143 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3144 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
3145 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3146 // CHECK3: omp.inner.for.cond.cleanup:
3147 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3148 // CHECK3: omp.inner.for.body:
3149 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3150 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3151 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3152 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4
3153 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3154 // CHECK3-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
3155 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]])
3156 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3157 // CHECK3: omp.inner.for.inc:
3158 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3159 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3160 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
3161 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3162 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
3163 // CHECK3: omp.inner.for.end:
3164 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3165 // CHECK3: omp.loop.exit:
3166 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3167 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
3168 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
3169 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3170 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
3171 // CHECK3-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3172 // CHECK3: .omp.final.then:
3173 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
3174 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
3175 // CHECK3: .omp.final.done:
3176 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3177 // CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3178 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
3179 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3180 // CHECK3: arraydestroy.body:
3181 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3182 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3183 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3184 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
3185 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
3186 // CHECK3: arraydestroy.done10:
3187 // CHECK3-NEXT: ret void
3188 //
3189 //
3190 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
3191 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3192 // CHECK3-NEXT: entry:
3193 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3194 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
3195 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3196 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
3197 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3198 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
3199 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
3200 // CHECK3-NEXT: ret void
3201 //
3202 //
3203 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
3204 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
3205 // CHECK3-NEXT: entry:
3206 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3207 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3208 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3209 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3210 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3211 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3212 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
3213 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
3214 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3215 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3216 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3217 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3218 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3219 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3220 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3221 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
3222 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
3223 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3224 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3225 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
3226 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
3227 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
3228 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3229 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3230 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3231 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3232 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3233 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3234 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3235 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
3236 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3237 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
3238 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
3239 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
3240 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3241 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3242 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3243 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3244 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
3245 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
3246 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3247 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3248 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
3249 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3250 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
3251 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3252 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
3253 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3254 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
3255 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3256 // CHECK3: omp.arraycpy.body:
3257 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3258 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3259 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3260 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3261 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3262 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3263 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3264 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
3265 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
3266 // CHECK3: omp.arraycpy.done4:
3267 // CHECK3-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3268 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
3269 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]])
3270 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
3271 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
3272 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3273 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
3274 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3275 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3276 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
3277 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3278 // CHECK3: cond.true:
3279 // CHECK3-NEXT: br label [[COND_END:%.*]]
3280 // CHECK3: cond.false:
3281 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3282 // CHECK3-NEXT: br label [[COND_END]]
3283 // CHECK3: cond.end:
3284 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
3285 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3286 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3287 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
3288 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3289 // CHECK3: omp.inner.for.cond:
3290 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3291 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3292 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
3293 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3294 // CHECK3: omp.inner.for.cond.cleanup:
3295 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3296 // CHECK3: omp.inner.for.body:
3297 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3298 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
3299 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3300 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3301 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3302 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
3303 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
3304 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
3305 // CHECK3-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
3306 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
3307 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
3308 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
3309 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
3310 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false)
3311 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3312 // CHECK3: omp.body.continue:
3313 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3314 // CHECK3: omp.inner.for.inc:
3315 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3316 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
3317 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
3318 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
3319 // CHECK3: omp.inner.for.end:
3320 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3321 // CHECK3: omp.loop.exit:
3322 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3323 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3324 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3325 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3326 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3327 // CHECK3-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3328 // CHECK3: .omp.final.then:
3329 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
3330 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
3331 // CHECK3: .omp.final.done:
3332 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3333 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
3334 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
3335 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3336 // CHECK3: arraydestroy.body:
3337 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3338 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3339 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3340 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
3341 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
3342 // CHECK3: arraydestroy.done12:
3343 // CHECK3-NEXT: ret void
3344 //
3345 //
3346 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3347 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3348 // CHECK3-NEXT: entry:
3349 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3350 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3351 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3352 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3353 // CHECK3-NEXT: ret void
3354 //
3355 //
3356 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3357 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3358 // CHECK3-NEXT: entry:
3359 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3360 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3361 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3362 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3363 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3364 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3365 // CHECK3-NEXT: ret void
3366 //
3367 //
3368 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3369 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3370 // CHECK3-NEXT: entry:
3371 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3372 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3373 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3374 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3375 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3376 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3377 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3378 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3379 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3380 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3381 // CHECK3-NEXT: ret void
3382 //
3383 //
3384 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
3385 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3386 // CHECK3-NEXT: entry:
3387 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3388 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
3389 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3390 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
3391 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3392 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3393 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
3394 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
3395 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
3396 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
3397 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3398 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
3399 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3400 // CHECK3-NEXT: ret void
3401 //
3402 //
3403 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3404 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3405 // CHECK3-NEXT: entry:
3406 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3407 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3408 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3409 // CHECK3-NEXT: ret void
3410 //
3411 //
3412 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
3413 // CHECK3-SAME: () #[[ATTR0]] {
3414 // CHECK3-NEXT: entry:
3415 // CHECK3-NEXT: call void @__cxx_global_var_init()
3416 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
3417 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
3418 // CHECK3-NEXT: ret void
3419 //
3420 //
3421 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3422 // CHECK3-SAME: () #[[ATTR0]] {
3423 // CHECK3-NEXT: entry:
3424 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
3425 // CHECK3-NEXT: ret void
3426 //
3427 //
3428 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
3429 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
3430 // CHECK4-NEXT: entry:
3431 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3432 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3433 // CHECK4-NEXT: ret void
3434 //
3435 //
3436 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3437 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3438 // CHECK4-NEXT: entry:
3439 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3440 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3441 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3442 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3443 // CHECK4-NEXT: ret void
3444 //
3445 //
3446 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3447 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3448 // CHECK4-NEXT: entry:
3449 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3450 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3451 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3452 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3453 // CHECK4-NEXT: ret void
3454 //
3455 //
3456 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3457 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3458 // CHECK4-NEXT: entry:
3459 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3460 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3461 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3462 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3463 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3464 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3465 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4
3466 // CHECK4-NEXT: ret void
3467 //
3468 //
3469 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3470 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3471 // CHECK4-NEXT: entry:
3472 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3473 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3474 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3475 // CHECK4-NEXT: ret void
3476 //
3477 //
3478 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3479 // CHECK4-SAME: () #[[ATTR0]] {
3480 // CHECK4-NEXT: entry:
3481 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
3482 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
3483 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3484 // CHECK4-NEXT: ret void
3485 //
3486 //
3487 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3488 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3489 // CHECK4-NEXT: entry:
3490 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3491 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3492 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3493 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3494 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3495 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3496 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3497 // CHECK4-NEXT: ret void
3498 //
3499 //
3500 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3501 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3502 // CHECK4-NEXT: entry:
3503 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
3504 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
3505 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3506 // CHECK4: arraydestroy.body:
3507 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3508 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3509 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3510 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3511 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3512 // CHECK4: arraydestroy.done1:
3513 // CHECK4-NEXT: ret void
3514 //
3515 //
3516 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3517 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3518 // CHECK4-NEXT: entry:
3519 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3520 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3521 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3522 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3523 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3524 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3525 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3526 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3527 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3528 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3529 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
3530 // CHECK4-NEXT: ret void
3531 //
3532 //
3533 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3534 // CHECK4-SAME: () #[[ATTR0]] {
3535 // CHECK4-NEXT: entry:
3536 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3537 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3538 // CHECK4-NEXT: ret void
3539 //
3540 //
3541 // CHECK4-LABEL: define {{[^@]+}}@main
3542 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
3543 // CHECK4-NEXT: entry:
3544 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3545 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3546 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
3547 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3548 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3549 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3550 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3551 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
3552 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4
3553 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4
3554 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3555 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
3556 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4
3557 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
3558 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3559 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
3560 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
3561 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3562 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
3563 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
3564 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3565 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4
3566 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3567 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]**
3568 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4
3569 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3570 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]**
3571 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4
3572 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3573 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4
3574 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3575 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]**
3576 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4
3577 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3578 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]**
3579 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4
3580 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3581 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4
3582 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3583 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S**
3584 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4
3585 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3586 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S**
3587 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4
3588 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3589 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4
3590 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3591 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
3592 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4
3593 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3594 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
3595 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4
3596 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3597 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4
3598 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3599 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3600 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2)
3601 // CHECK4-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
3602 // CHECK4-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
3603 // CHECK4-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3604 // CHECK4: omp_offload.failed:
3605 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]]
3606 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
3607 // CHECK4: omp_offload.cont:
3608 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
3609 // CHECK4-NEXT: ret i32 [[CALL]]
3610 //
3611 //
3612 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101
3613 // CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
3614 // CHECK4-NEXT: entry:
3615 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3616 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3617 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3618 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3619 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
3620 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3621 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
3622 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3623 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3624 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3625 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3626 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
3627 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3628 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3629 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3630 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3631 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
3632 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3633 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
3634 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4
3635 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
3636 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]])
3637 // CHECK4-NEXT: ret void
3638 //
3639 //
3640 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
3641 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
3642 // CHECK4-NEXT: entry:
3643 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3644 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3645 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3646 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3647 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3648 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3649 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
3650 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3651 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3652 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3653 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3654 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3655 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3656 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
3657 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
3658 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3659 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3660 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
3661 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
3662 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3663 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
3664 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3665 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3666 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3667 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3668 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3669 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3670 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
3671 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3672 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3673 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3674 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
3675 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
3676 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3677 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3678 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
3679 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3680 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
3681 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
3682 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
3683 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3684 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]]
3685 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3686 // CHECK4: omp.arraycpy.body:
3687 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3688 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3689 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3690 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3691 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3692 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3693 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3694 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
3695 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
3696 // CHECK4: omp.arraycpy.done3:
3697 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
3698 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
3699 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
3700 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3701 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
3702 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3703 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3704 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
3705 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3706 // CHECK4: cond.true:
3707 // CHECK4-NEXT: br label [[COND_END:%.*]]
3708 // CHECK4: cond.false:
3709 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3710 // CHECK4-NEXT: br label [[COND_END]]
3711 // CHECK4: cond.end:
3712 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
3713 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
3714 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3715 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4
3716 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3717 // CHECK4: omp.inner.for.cond:
3718 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3719 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3720 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
3721 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3722 // CHECK4: omp.inner.for.cond.cleanup:
3723 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3724 // CHECK4: omp.inner.for.body:
3725 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
3726 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
3727 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3728 // CHECK4-NEXT: store i32 [[TMP16]], i32* [[T_VAR_CASTED]], align 4
3729 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3730 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
3731 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[SIVAR_CASTED]], align 4
3732 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4
3733 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 7, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], [2 x i32]* [[VEC1]], i32 [[TMP17]], [2 x %struct.S]* [[S_ARR2]], %struct.S* [[VAR4]], i32 [[TMP19]])
3734 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3735 // CHECK4: omp.inner.for.inc:
3736 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3737 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
3738 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
3739 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
3740 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
3741 // CHECK4: omp.inner.for.end:
3742 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3743 // CHECK4: omp.loop.exit:
3744 // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3745 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
3746 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
3747 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3748 // CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
3749 // CHECK4-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3750 // CHECK4: .omp.final.then:
3751 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
3752 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
3753 // CHECK4: .omp.final.done:
3754 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
3755 // CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
3756 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2
3757 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3758 // CHECK4: arraydestroy.body:
3759 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3760 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3761 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3762 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
3763 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
3764 // CHECK4: arraydestroy.done8:
3765 // CHECK4-NEXT: ret void
3766 //
3767 //
3768 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev
3769 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3770 // CHECK4-NEXT: entry:
3771 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3772 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3773 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3774 // CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
3775 // CHECK4-NEXT: ret void
3776 //
3777 //
3778 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
3779 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3780 // CHECK4-NEXT: entry:
3781 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3782 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
3783 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3784 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
3785 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3786 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
3787 // CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
3788 // CHECK4-NEXT: ret void
3789 //
3790 //
3791 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev
3792 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3793 // CHECK4-NEXT: entry:
3794 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
3795 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
3796 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
3797 // CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
3798 // CHECK4-NEXT: ret void
3799 //
3800 //
3801 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
3802 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] {
3803 // CHECK4-NEXT: entry:
3804 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3805 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3806 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3807 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3808 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
3809 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
3810 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4
3811 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4
3812 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
3813 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3814 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
3815 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3816 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3817 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3818 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3819 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4
3820 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
3821 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
3822 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3823 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
3824 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
3825 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3826 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3827 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3828 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3829 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
3830 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
3831 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3832 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4
3833 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4
3834 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
3835 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4
3836 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4
3837 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3838 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3839 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
3840 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
3841 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
3842 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
3843 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3844 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3845 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8*
3846 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3847 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
3848 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
3849 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
3850 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3851 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP8]]
3852 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3853 // CHECK4: omp.arraycpy.body:
3854 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3855 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3856 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
3857 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
3858 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
3859 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3860 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3861 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
3862 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
3863 // CHECK4: omp.arraycpy.done3:
3864 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
3865 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]])
3866 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
3867 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3868 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
3869 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3870 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3871 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1
3872 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3873 // CHECK4: cond.true:
3874 // CHECK4-NEXT: br label [[COND_END:%.*]]
3875 // CHECK4: cond.false:
3876 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3877 // CHECK4-NEXT: br label [[COND_END]]
3878 // CHECK4: cond.end:
3879 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
3880 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3881 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3882 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
3883 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3884 // CHECK4: omp.inner.for.cond:
3885 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3886 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3887 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
3888 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3889 // CHECK4: omp.inner.for.cond.cleanup:
3890 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3891 // CHECK4: omp.inner.for.body:
3892 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3893 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
3894 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3895 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3896 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
3897 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
3898 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP18]]
3899 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
3900 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
3901 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP19]]
3902 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8*
3903 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S* [[VAR4]] to i8*
3904 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false)
3905 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4
3906 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4
3907 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP22]]
3908 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4
3909 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3910 // CHECK4: omp.body.continue:
3911 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3912 // CHECK4: omp.inner.for.inc:
3913 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3914 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP24]], 1
3915 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4
3916 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
3917 // CHECK4: omp.inner.for.end:
3918 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3919 // CHECK4: omp.loop.exit:
3920 // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3921 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
3922 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
3923 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3924 // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3925 // CHECK4-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3926 // CHECK4: .omp.final.then:
3927 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
3928 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
3929 // CHECK4: .omp.final.done:
3930 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
3931 // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0
3932 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2
3933 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3934 // CHECK4: arraydestroy.body:
3935 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3936 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3937 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3938 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
3939 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
3940 // CHECK4: arraydestroy.done11:
3941 // CHECK4-NEXT: ret void
3942 //
3943 //
3944 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3945 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat {
3946 // CHECK4-NEXT: entry:
3947 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3948 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3949 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3950 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3951 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3952 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
3953 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
3954 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
3955 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3956 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3957 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3958 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
3959 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3960 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4
3961 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3962 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3963 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3964 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
3965 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3966 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
3967 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3968 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
3969 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
3970 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
3971 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4
3972 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
3973 // CHECK4-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3974 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3975 // CHECK4-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
3976 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3977 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
3978 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4
3979 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3980 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
3981 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
3982 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3983 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4
3984 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3985 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]**
3986 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4
3987 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3988 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]**
3989 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4
3990 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3991 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4
3992 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3993 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]**
3994 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4
3995 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3996 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]**
3997 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4
3998 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3999 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4
4000 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4001 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0**
4002 // CHECK4-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4
4003 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4004 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0**
4005 // CHECK4-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4
4006 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4007 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4
4008 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4009 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4010 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2)
4011 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.6, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.7, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0)
4012 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
4013 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4014 // CHECK4: omp_offload.failed:
4015 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]]
4016 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
4017 // CHECK4: omp_offload.cont:
4018 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
4019 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4020 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4021 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4022 // CHECK4: arraydestroy.body:
4023 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4024 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4025 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4026 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
4027 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
4028 // CHECK4: arraydestroy.done2:
4029 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
4030 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4
4031 // CHECK4-NEXT: ret i32 [[TMP32]]
4032 //
4033 //
4034 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev
4035 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4036 // CHECK4-NEXT: entry:
4037 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
4038 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
4039 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
4040 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
4041 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4
4042 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
4043 // CHECK4-NEXT: store i32 0, i32* [[B]], align 4
4044 // CHECK4-NEXT: ret void
4045 //
4046 //
4047 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
4048 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4049 // CHECK4-NEXT: entry:
4050 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
4051 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4
4052 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
4053 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4
4054 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
4055 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4056 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4
4057 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
4058 // CHECK4-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4
4059 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
4060 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
4061 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
4062 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
4063 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
4064 // CHECK4-NEXT: ret void
4065 //
4066 //
4067 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev
4068 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4069 // CHECK4-NEXT: entry:
4070 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4
4071 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4
4072 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4
4073 // CHECK4-NEXT: ret void
4074 //
4075 //
4076 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
4077 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4078 // CHECK4-NEXT: entry:
4079 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4080 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4081 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4082 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
4083 // CHECK4-NEXT: ret void
4084 //
4085 //
4086 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4087 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4088 // CHECK4-NEXT: entry:
4089 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4090 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4091 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4092 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4093 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4094 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4095 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
4096 // CHECK4-NEXT: ret void
4097 //
4098 //
4099 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
4100 // CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
4101 // CHECK4-NEXT: entry:
4102 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4103 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4104 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4105 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4106 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4107 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4108 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4109 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4110 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4111 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4112 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4113 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4114 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4115 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4116 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4117 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4
4118 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4119 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4120 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]])
4121 // CHECK4-NEXT: ret void
4122 //
4123 //
4124 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
4125 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
4126 // CHECK4-NEXT: entry:
4127 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4128 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4129 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4130 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4131 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4132 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4133 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4134 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4135 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4136 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4137 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4138 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4139 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4140 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
4141 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
4142 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4143 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4144 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
4145 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
4146 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
4147 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
4148 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4149 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4150 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4151 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4152 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4153 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4154 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4155 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4156 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4157 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4158 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
4159 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
4160 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4161 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4162 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
4163 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4164 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false)
4165 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4166 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
4167 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4168 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]]
4169 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4170 // CHECK4: omp.arraycpy.body:
4171 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4172 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4173 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
4174 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
4175 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
4176 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4177 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4178 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
4179 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
4180 // CHECK4: omp.arraycpy.done4:
4181 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4182 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
4183 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]])
4184 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
4185 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
4186 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4187 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
4188 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4189 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4190 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
4191 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4192 // CHECK4: cond.true:
4193 // CHECK4-NEXT: br label [[COND_END:%.*]]
4194 // CHECK4: cond.false:
4195 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4196 // CHECK4-NEXT: br label [[COND_END]]
4197 // CHECK4: cond.end:
4198 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
4199 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
4200 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4201 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
4202 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4203 // CHECK4: omp.inner.for.cond:
4204 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4205 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4206 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
4207 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4208 // CHECK4: omp.inner.for.cond.cleanup:
4209 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4210 // CHECK4: omp.inner.for.body:
4211 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
4212 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
4213 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4214 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[T_VAR_CASTED]], align 4
4215 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4
4216 // CHECK4-NEXT: [[TMP19:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
4217 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP15]], i32 [[TMP16]], [2 x i32]* [[VEC2]], i32 [[TMP18]], [2 x %struct.S.0]* [[S_ARR3]], %struct.S.0* [[TMP19]])
4218 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4219 // CHECK4: omp.inner.for.inc:
4220 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4221 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
4222 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
4223 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
4224 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
4225 // CHECK4: omp.inner.for.end:
4226 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4227 // CHECK4: omp.loop.exit:
4228 // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4229 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4
4230 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]])
4231 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4232 // CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
4233 // CHECK4-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4234 // CHECK4: .omp.final.then:
4235 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
4236 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
4237 // CHECK4: .omp.final.done:
4238 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
4239 // CHECK4-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4240 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
4241 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4242 // CHECK4: arraydestroy.body:
4243 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4244 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4245 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4246 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
4247 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
4248 // CHECK4: arraydestroy.done10:
4249 // CHECK4-NEXT: ret void
4250 //
4251 //
4252 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
4253 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4254 // CHECK4-NEXT: entry:
4255 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4256 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
4257 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4258 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
4259 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4260 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
4261 // CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]])
4262 // CHECK4-NEXT: ret void
4263 //
4264 //
4265 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5
4266 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
4267 // CHECK4-NEXT: entry:
4268 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4269 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4270 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4271 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4272 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4
4273 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
4274 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4
4275 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4
4276 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
4277 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4278 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
4279 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4280 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4281 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4282 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4283 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
4284 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
4285 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
4286 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4287 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
4288 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4
4289 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
4290 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4291 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4292 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4293 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4294 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4
4295 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4
4296 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4297 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4
4298 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4
4299 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4
4300 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4
4301 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4
4302 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4303 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4304 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4
4305 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4
4306 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_LB]], align 4
4307 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4
4308 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4309 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4310 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8*
4311 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
4312 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i32 8, i1 false)
4313 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4314 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
4315 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
4316 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]]
4317 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
4318 // CHECK4: omp.arraycpy.body:
4319 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4320 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
4321 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]])
4322 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]])
4323 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
4324 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
4325 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
4326 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
4327 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
4328 // CHECK4: omp.arraycpy.done4:
4329 // CHECK4-NEXT: [[TMP9:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
4330 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
4331 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP9]], %struct.St* [[AGG_TMP6]])
4332 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
4333 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4
4334 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4335 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4
4336 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4337 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4338 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1
4339 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4340 // CHECK4: cond.true:
4341 // CHECK4-NEXT: br label [[COND_END:%.*]]
4342 // CHECK4: cond.false:
4343 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4344 // CHECK4-NEXT: br label [[COND_END]]
4345 // CHECK4: cond.end:
4346 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
4347 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4348 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4349 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
4350 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4351 // CHECK4: omp.inner.for.cond:
4352 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4353 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4354 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
4355 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4356 // CHECK4: omp.inner.for.cond.cleanup:
4357 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
4358 // CHECK4: omp.inner.for.body:
4359 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4360 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
4361 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4362 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4363 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4
4364 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4
4365 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP19]]
4366 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4
4367 // CHECK4-NEXT: [[TMP20:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4
4368 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4
4369 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP21]]
4370 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8*
4371 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast %struct.S.0* [[TMP20]] to i8*
4372 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP22]], i8* align 4 [[TMP23]], i32 4, i1 false)
4373 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4374 // CHECK4: omp.body.continue:
4375 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4376 // CHECK4: omp.inner.for.inc:
4377 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4378 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
4379 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4
4380 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
4381 // CHECK4: omp.inner.for.end:
4382 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4383 // CHECK4: omp.loop.exit:
4384 // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
4385 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4
4386 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
4387 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4388 // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4389 // CHECK4-NEXT: br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4390 // CHECK4: .omp.final.then:
4391 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
4392 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
4393 // CHECK4: .omp.final.done:
4394 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
4395 // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0
4396 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
4397 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4398 // CHECK4: arraydestroy.body:
4399 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4400 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
4401 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4402 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
4403 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
4404 // CHECK4: arraydestroy.done12:
4405 // CHECK4-NEXT: ret void
4406 //
4407 //
4408 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4409 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4410 // CHECK4-NEXT: entry:
4411 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4412 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4413 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4414 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4415 // CHECK4-NEXT: ret void
4416 //
4417 //
4418 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4419 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4420 // CHECK4-NEXT: entry:
4421 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4422 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4423 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4424 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4425 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4426 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
4427 // CHECK4-NEXT: ret void
4428 //
4429 //
4430 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4431 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4432 // CHECK4-NEXT: entry:
4433 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4434 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4435 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4436 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4437 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4438 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4439 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4440 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4441 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
4442 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4443 // CHECK4-NEXT: ret void
4444 //
4445 //
4446 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
4447 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4448 // CHECK4-NEXT: entry:
4449 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4450 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4
4451 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4452 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4
4453 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4454 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4455 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4
4456 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
4457 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
4458 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0
4459 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
4460 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
4461 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4462 // CHECK4-NEXT: ret void
4463 //
4464 //
4465 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4466 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4467 // CHECK4-NEXT: entry:
4468 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
4469 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
4470 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
4471 // CHECK4-NEXT: ret void
4472 //
4473 //
4474 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
4475 // CHECK4-SAME: () #[[ATTR0]] {
4476 // CHECK4-NEXT: entry:
4477 // CHECK4-NEXT: call void @__cxx_global_var_init()
4478 // CHECK4-NEXT: call void @__cxx_global_var_init.1()
4479 // CHECK4-NEXT: call void @__cxx_global_var_init.2()
4480 // CHECK4-NEXT: ret void
4481 //
4482 //
4483 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4484 // CHECK4-SAME: () #[[ATTR0]] {
4485 // CHECK4-NEXT: entry:
4486 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
4487 // CHECK4-NEXT: ret void
4488 //
4489 //
4490 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
4491 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
4492 // CHECK5-NEXT: entry:
4493 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4494 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4495 // CHECK5-NEXT: ret void
4496 //
4497 //
4498 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4499 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4500 // CHECK5-NEXT: entry:
4501 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4502 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4503 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4504 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4505 // CHECK5-NEXT: ret void
4506 //
4507 //
4508 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4509 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4510 // CHECK5-NEXT: entry:
4511 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4512 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4513 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4514 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4515 // CHECK5-NEXT: ret void
4516 //
4517 //
4518 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4519 // CHECK5-SAME: () #[[ATTR0]] {
4520 // CHECK5-NEXT: entry:
4521 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4522 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4523 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4524 // CHECK5-NEXT: ret void
4525 //
4526 //
4527 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4528 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4529 // CHECK5-NEXT: entry:
4530 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4531 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4532 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4533 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4534 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4535 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4536 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4537 // CHECK5-NEXT: ret void
4538 //
4539 //
4540 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4541 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4542 // CHECK5-NEXT: entry:
4543 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4544 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4545 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4546 // CHECK5: arraydestroy.body:
4547 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4548 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4549 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4550 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4551 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4552 // CHECK5: arraydestroy.done1:
4553 // CHECK5-NEXT: ret void
4554 //
4555 //
4556 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4557 // CHECK5-SAME: () #[[ATTR0]] {
4558 // CHECK5-NEXT: entry:
4559 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4560 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4561 // CHECK5-NEXT: ret void
4562 //
4563 //
4564 // CHECK5-LABEL: define {{[^@]+}}@main
4565 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
4566 // CHECK5-NEXT: entry:
4567 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4568 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
4569 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4570 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4571 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4572 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
4573 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
4574 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4575 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4576 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4577 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4578 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4579 // CHECK5: omp.inner.for.cond:
4580 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4581 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
4582 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4583 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4584 // CHECK5: omp.inner.for.body:
4585 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4586 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4587 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4588 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
4589 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2
4590 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4591 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
4592 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]]
4593 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
4594 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4595 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
4596 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]]
4597 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
4598 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2
4599 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4600 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
4601 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
4602 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
4603 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4604 // CHECK5: omp.body.continue:
4605 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4606 // CHECK5: omp.inner.for.inc:
4607 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4608 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
4609 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4610 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4611 // CHECK5: omp.inner.for.end:
4612 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
4613 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
4614 // CHECK5-NEXT: ret i32 [[CALL]]
4615 //
4616 //
4617 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
4618 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
4619 // CHECK5-NEXT: entry:
4620 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4621 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4622 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
4623 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
4624 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
4625 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
4626 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
4627 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
4628 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
4629 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4630 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4631 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4632 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
4633 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
4634 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
4635 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
4636 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
4637 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
4638 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
4639 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
4640 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
4641 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
4642 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
4643 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
4644 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
4645 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
4646 // CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8
4647 // CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
4648 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4649 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4650 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4651 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
4652 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4653 // CHECK5: omp.inner.for.cond:
4654 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4655 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
4656 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
4657 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4658 // CHECK5: omp.inner.for.body:
4659 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4660 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
4661 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4662 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
4663 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
4664 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
4665 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64
4666 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
4667 // CHECK5-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
4668 // CHECK5-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8, !llvm.access.group !6
4669 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
4670 // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
4671 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
4672 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
4673 // CHECK5-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8*
4674 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !6
4675 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4676 // CHECK5: omp.body.continue:
4677 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4678 // CHECK5: omp.inner.for.inc:
4679 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4680 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
4681 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4682 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
4683 // CHECK5: omp.inner.for.end:
4684 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
4685 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
4686 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
4687 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
4688 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4689 // CHECK5: arraydestroy.body:
4690 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4691 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4692 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4693 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
4694 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
4695 // CHECK5: arraydestroy.done6:
4696 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
4697 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4
4698 // CHECK5-NEXT: ret i32 [[TMP17]]
4699 //
4700 //
4701 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4702 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4703 // CHECK5-NEXT: entry:
4704 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4705 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4706 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4707 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4708 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4709 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4710 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
4711 // CHECK5-NEXT: ret void
4712 //
4713 //
4714 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4715 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4716 // CHECK5-NEXT: entry:
4717 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4718 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4719 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4720 // CHECK5-NEXT: ret void
4721 //
4722 //
4723 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4724 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4725 // CHECK5-NEXT: entry:
4726 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4727 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4728 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4729 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4730 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4731 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4732 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4733 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4734 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4735 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4736 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
4737 // CHECK5-NEXT: ret void
4738 //
4739 //
4740 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
4741 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4742 // CHECK5-NEXT: entry:
4743 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4744 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4745 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4746 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
4747 // CHECK5-NEXT: ret void
4748 //
4749 //
4750 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4751 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4752 // CHECK5-NEXT: entry:
4753 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4754 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4755 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4756 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4757 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4758 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4759 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
4760 // CHECK5-NEXT: ret void
4761 //
4762 //
4763 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4764 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4765 // CHECK5-NEXT: entry:
4766 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4767 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4768 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4769 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4770 // CHECK5-NEXT: ret void
4771 //
4772 //
4773 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4774 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4775 // CHECK5-NEXT: entry:
4776 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4777 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4778 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4779 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4780 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4781 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
4782 // CHECK5-NEXT: ret void
4783 //
4784 //
4785 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4786 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4787 // CHECK5-NEXT: entry:
4788 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4789 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4790 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4791 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
4792 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4793 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4794 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4795 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4796 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
4797 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4
4798 // CHECK5-NEXT: ret void
4799 //
4800 //
4801 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4802 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4803 // CHECK5-NEXT: entry:
4804 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4805 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4806 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4807 // CHECK5-NEXT: ret void
4808 //
4809 //
4810 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
4811 // CHECK5-SAME: () #[[ATTR0]] {
4812 // CHECK5-NEXT: entry:
4813 // CHECK5-NEXT: call void @__cxx_global_var_init()
4814 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
4815 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
4816 // CHECK5-NEXT: ret void
4817 //
4818 //
4819 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init
4820 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
4821 // CHECK6-NEXT: entry:
4822 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4823 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4824 // CHECK6-NEXT: ret void
4825 //
4826 //
4827 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4828 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4829 // CHECK6-NEXT: entry:
4830 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4831 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4832 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4833 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4834 // CHECK6-NEXT: ret void
4835 //
4836 //
4837 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4838 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4839 // CHECK6-NEXT: entry:
4840 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4841 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4842 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4843 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4844 // CHECK6-NEXT: ret void
4845 //
4846 //
4847 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4848 // CHECK6-SAME: () #[[ATTR0]] {
4849 // CHECK6-NEXT: entry:
4850 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4851 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4852 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4853 // CHECK6-NEXT: ret void
4854 //
4855 //
4856 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4857 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4858 // CHECK6-NEXT: entry:
4859 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4860 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4861 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4862 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4863 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4864 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4865 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4866 // CHECK6-NEXT: ret void
4867 //
4868 //
4869 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4870 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4871 // CHECK6-NEXT: entry:
4872 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4873 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4874 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4875 // CHECK6: arraydestroy.body:
4876 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4877 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4878 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4879 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4880 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4881 // CHECK6: arraydestroy.done1:
4882 // CHECK6-NEXT: ret void
4883 //
4884 //
4885 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4886 // CHECK6-SAME: () #[[ATTR0]] {
4887 // CHECK6-NEXT: entry:
4888 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4889 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4890 // CHECK6-NEXT: ret void
4891 //
4892 //
4893 // CHECK6-LABEL: define {{[^@]+}}@main
4894 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] {
4895 // CHECK6-NEXT: entry:
4896 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4897 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
4898 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4899 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4900 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4901 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
4902 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
4903 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4904 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4905 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4906 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
4907 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4908 // CHECK6: omp.inner.for.cond:
4909 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4910 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
4911 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
4912 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4913 // CHECK6: omp.inner.for.body:
4914 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4915 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
4916 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4917 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
4918 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2
4919 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4920 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
4921 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]]
4922 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
4923 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4924 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
4925 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]]
4926 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
4927 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2
4928 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
4929 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
4930 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
4931 // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2
4932 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4933 // CHECK6: omp.body.continue:
4934 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4935 // CHECK6: omp.inner.for.inc:
4936 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4937 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
4938 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
4939 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4940 // CHECK6: omp.inner.for.end:
4941 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
4942 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
4943 // CHECK6-NEXT: ret i32 [[CALL]]
4944 //
4945 //
4946 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
4947 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat {
4948 // CHECK6-NEXT: entry:
4949 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4950 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
4951 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
4952 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
4953 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
4954 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
4955 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8
4956 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
4957 // CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
4958 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4959 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4960 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4961 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
4962 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
4963 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4
4964 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
4965 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
4966 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
4967 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
4968 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
4969 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
4970 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
4971 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
4972 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8
4973 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8
4974 // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
4975 // CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8
4976 // CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8
4977 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4978 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4979 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4980 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
4981 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4982 // CHECK6: omp.inner.for.cond:
4983 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4984 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
4985 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
4986 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4987 // CHECK6: omp.inner.for.body:
4988 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
4989 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
4990 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4991 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
4992 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6
4993 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
4994 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64
4995 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
4996 // CHECK6-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
4997 // CHECK6-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8, !llvm.access.group !6
4998 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
4999 // CHECK6-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
5000 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]]
5001 // CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
5002 // CHECK6-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8*
5003 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group !6
5004 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5005 // CHECK6: omp.body.continue:
5006 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5007 // CHECK6: omp.inner.for.inc:
5008 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
5009 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
5010 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
5011 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
5012 // CHECK6: omp.inner.for.end:
5013 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
5014 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
5015 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
5016 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
5017 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5018 // CHECK6: arraydestroy.body:
5019 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5020 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5021 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5022 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
5023 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
5024 // CHECK6: arraydestroy.done6:
5025 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
5026 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4
5027 // CHECK6-NEXT: ret i32 [[TMP17]]
5028 //
5029 //
5030 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
5031 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5032 // CHECK6-NEXT: entry:
5033 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5034 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5035 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5036 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5037 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5038 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
5039 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4
5040 // CHECK6-NEXT: ret void
5041 //
5042 //
5043 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5044 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5045 // CHECK6-NEXT: entry:
5046 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5047 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5048 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5049 // CHECK6-NEXT: ret void
5050 //
5051 //
5052 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
5053 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5054 // CHECK6-NEXT: entry:
5055 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5056 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5057 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5058 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5059 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5060 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5061 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5062 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5063 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5064 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5065 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4
5066 // CHECK6-NEXT: ret void
5067 //
5068 //
5069 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
5070 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5071 // CHECK6-NEXT: entry:
5072 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5073 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5074 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5075 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
5076 // CHECK6-NEXT: ret void
5077 //
5078 //
5079 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
5080 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5081 // CHECK6-NEXT: entry:
5082 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5083 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5084 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5085 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5086 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5087 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5088 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
5089 // CHECK6-NEXT: ret void
5090 //
5091 //
5092 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
5093 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5094 // CHECK6-NEXT: entry:
5095 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5096 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5097 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5098 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5099 // CHECK6-NEXT: ret void
5100 //
5101 //
5102 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
5103 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5104 // CHECK6-NEXT: entry:
5105 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5106 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5107 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5108 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5109 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5110 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
5111 // CHECK6-NEXT: ret void
5112 //
5113 //
5114 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
5115 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5116 // CHECK6-NEXT: entry:
5117 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5118 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5119 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5120 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5121 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5122 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5123 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5124 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5125 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
5126 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4
5127 // CHECK6-NEXT: ret void
5128 //
5129 //
5130 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
5131 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5132 // CHECK6-NEXT: entry:
5133 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
5134 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
5135 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
5136 // CHECK6-NEXT: ret void
5137 //
5138 //
5139 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
5140 // CHECK6-SAME: () #[[ATTR0]] {
5141 // CHECK6-NEXT: entry:
5142 // CHECK6-NEXT: call void @__cxx_global_var_init()
5143 // CHECK6-NEXT: call void @__cxx_global_var_init.1()
5144 // CHECK6-NEXT: call void @__cxx_global_var_init.2()
5145 // CHECK6-NEXT: ret void
5146 //
5147 //
5148 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
5149 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
5150 // CHECK7-NEXT: entry:
5151 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
5152 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
5153 // CHECK7-NEXT: ret void
5154 //
5155 //
5156 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
5157 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
5158 // CHECK7-NEXT: entry:
5159 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5160 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5161 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5162 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
5163 // CHECK7-NEXT: ret void
5164 //
5165 //
5166 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
5167 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5168 // CHECK7-NEXT: entry:
5169 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5170 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5171 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5172 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5173 // CHECK7-NEXT: ret void
5174 //
5175 //
5176 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5177 // CHECK7-SAME: () #[[ATTR0]] {
5178 // CHECK7-NEXT: entry:
5179 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
5180 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
5181 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
5182 // CHECK7-NEXT: ret void
5183 //
5184 //
5185 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
5186 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5187 // CHECK7-NEXT: entry:
5188 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5189 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5190 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5191 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5192 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5193 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5194 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
5195 // CHECK7-NEXT: ret void
5196 //
5197 //
5198 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5199 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
5200 // CHECK7-NEXT: entry:
5201 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
5202 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
5203 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5204 // CHECK7: arraydestroy.body:
5205 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5206 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
5207 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5208 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
5209 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
5210 // CHECK7: arraydestroy.done1:
5211 // CHECK7-NEXT: ret void
5212 //
5213 //
5214 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5215 // CHECK7-SAME: () #[[ATTR0]] {
5216 // CHECK7-NEXT: entry:
5217 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
5218 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
5219 // CHECK7-NEXT: ret void
5220 //
5221 //
5222 // CHECK7-LABEL: define {{[^@]+}}@main
5223 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
5224 // CHECK7-NEXT: entry:
5225 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5226 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
5227 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5228 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5229 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5230 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
5231 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
5232 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5233 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5234 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5235 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
5236 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5237 // CHECK7: omp.inner.for.cond:
5238 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5239 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
5240 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
5241 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5242 // CHECK7: omp.inner.for.body:
5243 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5244 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
5245 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5246 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
5247 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3
5248 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5249 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]]
5250 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
5251 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5252 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]]
5253 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
5254 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3
5255 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5256 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
5257 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
5258 // CHECK7-NEXT: store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
5259 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5260 // CHECK7: omp.body.continue:
5261 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5262 // CHECK7: omp.inner.for.inc:
5263 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5264 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
5265 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5266 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
5267 // CHECK7: omp.inner.for.end:
5268 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
5269 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
5270 // CHECK7-NEXT: ret i32 [[CALL]]
5271 //
5272 //
5273 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
5274 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
5275 // CHECK7-NEXT: entry:
5276 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5277 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
5278 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
5279 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
5280 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
5281 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
5282 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
5283 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
5284 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
5285 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5286 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5287 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5288 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
5289 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
5290 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
5291 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
5292 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
5293 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
5294 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
5295 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
5296 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
5297 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
5298 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
5299 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
5300 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
5301 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
5302 // CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4
5303 // CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
5304 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5305 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5306 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5307 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5308 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5309 // CHECK7: omp.inner.for.cond:
5310 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
5311 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
5312 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5313 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5314 // CHECK7: omp.inner.for.body:
5315 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
5316 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5317 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5318 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
5319 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7
5320 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
5321 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP10]]
5322 // CHECK7-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
5323 // CHECK7-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4, !llvm.access.group !7
5324 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
5325 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP12]]
5326 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8*
5327 // CHECK7-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8*
5328 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !7
5329 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5330 // CHECK7: omp.body.continue:
5331 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5332 // CHECK7: omp.inner.for.inc:
5333 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
5334 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
5335 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
5336 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
5337 // CHECK7: omp.inner.for.end:
5338 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
5339 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
5340 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
5341 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
5342 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5343 // CHECK7: arraydestroy.body:
5344 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5345 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
5346 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5347 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
5348 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
5349 // CHECK7: arraydestroy.done5:
5350 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
5351 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4
5352 // CHECK7-NEXT: ret i32 [[TMP17]]
5353 //
5354 //
5355 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
5356 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5357 // CHECK7-NEXT: entry:
5358 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5359 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5360 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5361 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5362 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5363 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
5364 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4
5365 // CHECK7-NEXT: ret void
5366 //
5367 //
5368 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5369 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5370 // CHECK7-NEXT: entry:
5371 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5372 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5373 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5374 // CHECK7-NEXT: ret void
5375 //
5376 //
5377 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
5378 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5379 // CHECK7-NEXT: entry:
5380 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5381 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5382 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5383 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5384 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5385 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5386 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5387 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5388 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5389 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5390 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4
5391 // CHECK7-NEXT: ret void
5392 //
5393 //
5394 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
5395 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5396 // CHECK7-NEXT: entry:
5397 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5398 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5399 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5400 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
5401 // CHECK7-NEXT: ret void
5402 //
5403 //
5404 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
5405 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5406 // CHECK7-NEXT: entry:
5407 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5408 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5409 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5410 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5411 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5412 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5413 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
5414 // CHECK7-NEXT: ret void
5415 //
5416 //
5417 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
5418 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5419 // CHECK7-NEXT: entry:
5420 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5421 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5422 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5423 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5424 // CHECK7-NEXT: ret void
5425 //
5426 //
5427 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
5428 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5429 // CHECK7-NEXT: entry:
5430 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5431 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5432 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5433 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5434 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5435 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
5436 // CHECK7-NEXT: ret void
5437 //
5438 //
5439 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
5440 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5441 // CHECK7-NEXT: entry:
5442 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5443 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5444 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5445 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5446 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5447 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5448 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5449 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5450 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
5451 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4
5452 // CHECK7-NEXT: ret void
5453 //
5454 //
5455 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
5456 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5457 // CHECK7-NEXT: entry:
5458 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5459 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5460 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5461 // CHECK7-NEXT: ret void
5462 //
5463 //
5464 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
5465 // CHECK7-SAME: () #[[ATTR0]] {
5466 // CHECK7-NEXT: entry:
5467 // CHECK7-NEXT: call void @__cxx_global_var_init()
5468 // CHECK7-NEXT: call void @__cxx_global_var_init.1()
5469 // CHECK7-NEXT: call void @__cxx_global_var_init.2()
5470 // CHECK7-NEXT: ret void
5471 //
5472 //
5473 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init
5474 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
5475 // CHECK8-NEXT: entry:
5476 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
5477 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
5478 // CHECK8-NEXT: ret void
5479 //
5480 //
5481 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
5482 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
5483 // CHECK8-NEXT: entry:
5484 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5485 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5486 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5487 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
5488 // CHECK8-NEXT: ret void
5489 //
5490 //
5491 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
5492 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5493 // CHECK8-NEXT: entry:
5494 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5495 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5496 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5497 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5498 // CHECK8-NEXT: ret void
5499 //
5500 //
5501 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5502 // CHECK8-SAME: () #[[ATTR0]] {
5503 // CHECK8-NEXT: entry:
5504 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
5505 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
5506 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
5507 // CHECK8-NEXT: ret void
5508 //
5509 //
5510 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
5511 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5512 // CHECK8-NEXT: entry:
5513 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5514 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5515 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5516 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5517 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5518 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5519 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
5520 // CHECK8-NEXT: ret void
5521 //
5522 //
5523 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5524 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
5525 // CHECK8-NEXT: entry:
5526 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
5527 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
5528 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5529 // CHECK8: arraydestroy.body:
5530 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5531 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
5532 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5533 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
5534 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
5535 // CHECK8: arraydestroy.done1:
5536 // CHECK8-NEXT: ret void
5537 //
5538 //
5539 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5540 // CHECK8-SAME: () #[[ATTR0]] {
5541 // CHECK8-NEXT: entry:
5542 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
5543 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
5544 // CHECK8-NEXT: ret void
5545 //
5546 //
5547 // CHECK8-LABEL: define {{[^@]+}}@main
5548 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] {
5549 // CHECK8-NEXT: entry:
5550 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5551 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
5552 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5553 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5554 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5555 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
5556 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
5557 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5558 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5559 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5560 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
5561 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5562 // CHECK8: omp.inner.for.cond:
5563 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5564 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
5565 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
5566 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5567 // CHECK8: omp.inner.for.body:
5568 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5569 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
5570 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5571 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
5572 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3
5573 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5574 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]]
5575 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
5576 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5577 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]]
5578 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
5579 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3
5580 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
5581 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
5582 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
5583 // CHECK8-NEXT: store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3
5584 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5585 // CHECK8: omp.body.continue:
5586 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5587 // CHECK8: omp.inner.for.inc:
5588 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5589 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
5590 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
5591 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
5592 // CHECK8: omp.inner.for.end:
5593 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
5594 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
5595 // CHECK8-NEXT: ret i32 [[CALL]]
5596 //
5597 //
5598 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
5599 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat {
5600 // CHECK8-NEXT: entry:
5601 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5602 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
5603 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
5604 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
5605 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
5606 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
5607 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4
5608 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
5609 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
5610 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5611 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5612 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5613 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
5614 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
5615 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4
5616 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
5617 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
5618 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
5619 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
5620 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
5621 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
5622 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
5623 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
5624 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4
5625 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4
5626 // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
5627 // CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4
5628 // CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4
5629 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
5630 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
5631 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
5632 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
5633 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5634 // CHECK8: omp.inner.for.cond:
5635 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
5636 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
5637 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5638 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5639 // CHECK8: omp.inner.for.body:
5640 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
5641 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5642 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5643 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
5644 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7
5645 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
5646 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP10]]
5647 // CHECK8-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
5648 // CHECK8-NEXT: [[TMP11:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4, !llvm.access.group !7
5649 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
5650 // CHECK8-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP12]]
5651 // CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8*
5652 // CHECK8-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP11]] to i8*
5653 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group !7
5654 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5655 // CHECK8: omp.body.continue:
5656 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5657 // CHECK8: omp.inner.for.inc:
5658 // CHECK8-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
5659 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
5660 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
5661 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
5662 // CHECK8: omp.inner.for.end:
5663 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
5664 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
5665 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
5666 // CHECK8-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
5667 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5668 // CHECK8: arraydestroy.body:
5669 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5670 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
5671 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5672 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
5673 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
5674 // CHECK8: arraydestroy.done5:
5675 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
5676 // CHECK8-NEXT: [[TMP17:%.*]] = load i32, i32* [[RETVAL]], align 4
5677 // CHECK8-NEXT: ret i32 [[TMP17]]
5678 //
5679 //
5680 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
5681 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5682 // CHECK8-NEXT: entry:
5683 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5684 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5685 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5686 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5687 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5688 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
5689 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4
5690 // CHECK8-NEXT: ret void
5691 //
5692 //
5693 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5694 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5695 // CHECK8-NEXT: entry:
5696 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5697 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5698 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5699 // CHECK8-NEXT: ret void
5700 //
5701 //
5702 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
5703 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5704 // CHECK8-NEXT: entry:
5705 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
5706 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5707 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
5708 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5709 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
5710 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5711 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5712 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5713 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5714 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5715 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4
5716 // CHECK8-NEXT: ret void
5717 //
5718 //
5719 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
5720 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5721 // CHECK8-NEXT: entry:
5722 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5723 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5724 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5725 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
5726 // CHECK8-NEXT: ret void
5727 //
5728 //
5729 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
5730 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5731 // CHECK8-NEXT: entry:
5732 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5733 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5734 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5735 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5736 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5737 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5738 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
5739 // CHECK8-NEXT: ret void
5740 //
5741 //
5742 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
5743 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5744 // CHECK8-NEXT: entry:
5745 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5746 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5747 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5748 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5749 // CHECK8-NEXT: ret void
5750 //
5751 //
5752 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
5753 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5754 // CHECK8-NEXT: entry:
5755 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5756 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5757 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5758 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5759 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5760 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
5761 // CHECK8-NEXT: ret void
5762 //
5763 //
5764 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
5765 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5766 // CHECK8-NEXT: entry:
5767 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5768 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5769 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5770 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
5771 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5772 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
5773 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5774 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5775 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
5776 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4
5777 // CHECK8-NEXT: ret void
5778 //
5779 //
5780 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
5781 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5782 // CHECK8-NEXT: entry:
5783 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
5784 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
5785 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
5786 // CHECK8-NEXT: ret void
5787 //
5788 //
5789 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
5790 // CHECK8-SAME: () #[[ATTR0]] {
5791 // CHECK8-NEXT: entry:
5792 // CHECK8-NEXT: call void @__cxx_global_var_init()
5793 // CHECK8-NEXT: call void @__cxx_global_var_init.1()
5794 // CHECK8-NEXT: call void @__cxx_global_var_init.2()
5795 // CHECK8-NEXT: ret void
5796 //
5797 //
5798 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
5799 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
5800 // CHECK9-NEXT: entry:
5801 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
5802 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
5803 // CHECK9-NEXT: ret void
5804 //
5805 //
5806 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
5807 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
5808 // CHECK9-NEXT: entry:
5809 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5810 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5811 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5812 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
5813 // CHECK9-NEXT: ret void
5814 //
5815 //
5816 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
5817 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5818 // CHECK9-NEXT: entry:
5819 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5820 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5821 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5822 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
5823 // CHECK9-NEXT: ret void
5824 //
5825 //
5826 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
5827 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5828 // CHECK9-NEXT: entry:
5829 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5830 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5831 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5832 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5833 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
5834 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
5835 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
5836 // CHECK9-NEXT: ret void
5837 //
5838 //
5839 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
5840 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5841 // CHECK9-NEXT: entry:
5842 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5843 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5844 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5845 // CHECK9-NEXT: ret void
5846 //
5847 //
5848 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5849 // CHECK9-SAME: () #[[ATTR0]] {
5850 // CHECK9-NEXT: entry:
5851 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
5852 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
5853 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
5854 // CHECK9-NEXT: ret void
5855 //
5856 //
5857 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
5858 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5859 // CHECK9-NEXT: entry:
5860 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5861 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5862 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5863 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5864 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5865 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5866 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
5867 // CHECK9-NEXT: ret void
5868 //
5869 //
5870 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5871 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
5872 // CHECK9-NEXT: entry:
5873 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
5874 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
5875 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
5876 // CHECK9: arraydestroy.body:
5877 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5878 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5879 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
5880 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
5881 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
5882 // CHECK9: arraydestroy.done1:
5883 // CHECK9-NEXT: ret void
5884 //
5885 //
5886 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
5887 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5888 // CHECK9-NEXT: entry:
5889 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
5890 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
5891 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
5892 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
5893 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
5894 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
5895 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
5896 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
5897 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
5898 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
5899 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
5900 // CHECK9-NEXT: ret void
5901 //
5902 //
5903 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5904 // CHECK9-SAME: () #[[ATTR0]] {
5905 // CHECK9-NEXT: entry:
5906 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
5907 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
5908 // CHECK9-NEXT: ret void
5909 //
5910 //
5911 // CHECK9-LABEL: define {{[^@]+}}@main
5912 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
5913 // CHECK9-NEXT: entry:
5914 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
5915 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
5916 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
5917 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
5918 // CHECK9-NEXT: ret i32 0
5919 //
5920 //
5921 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
5922 // CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
5923 // CHECK9-NEXT: entry:
5924 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
5925 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5926 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
5927 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
5928 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
5929 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
5930 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5931 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
5932 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5933 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
5934 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
5935 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5936 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
5937 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
5938 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5939 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
5940 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
5941 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
5942 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
5943 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
5944 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
5945 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
5946 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
5947 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
5948 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
5949 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
5950 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
5951 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
5952 // CHECK9-NEXT: ret void
5953 //
5954 //
5955 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
5956 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
5957 // CHECK9-NEXT: entry:
5958 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5959 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5960 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
5961 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
5962 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
5963 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
5964 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5965 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
5966 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
5967 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
5968 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5969 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5970 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
5971 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
5972 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
5973 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
5974 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5975 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5976 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
5977 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
5978 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
5979 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
5980 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
5981 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
5982 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
5983 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
5984 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
5985 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
5986 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
5987 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5988 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
5989 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
5990 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5991 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
5992 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5993 // CHECK9: cond.true:
5994 // CHECK9-NEXT: br label [[COND_END:%.*]]
5995 // CHECK9: cond.false:
5996 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
5997 // CHECK9-NEXT: br label [[COND_END]]
5998 // CHECK9: cond.end:
5999 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6000 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
6001 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
6002 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6003 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6004 // CHECK9: omp.inner.for.cond:
6005 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6006 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6007 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6008 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6009 // CHECK9: omp.inner.for.body:
6010 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
6011 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
6012 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6013 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
6014 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
6015 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
6016 // CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
6017 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
6018 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
6019 // CHECK9-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
6020 // CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
6021 // CHECK9-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
6022 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
6023 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
6024 // CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
6025 // CHECK9-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
6026 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
6027 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
6028 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6029 // CHECK9: omp.inner.for.inc:
6030 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6031 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6032 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
6033 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
6034 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
6035 // CHECK9: omp.inner.for.end:
6036 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6037 // CHECK9: omp.loop.exit:
6038 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6039 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6040 // CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
6041 // CHECK9-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6042 // CHECK9: .omp.final.then:
6043 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
6044 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
6045 // CHECK9: .omp.final.done:
6046 // CHECK9-NEXT: ret void
6047 //
6048 //
6049 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
6050 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
6051 // CHECK9-NEXT: entry:
6052 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6053 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6054 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
6055 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
6056 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
6057 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
6058 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
6059 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
6060 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6061 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
6062 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6063 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6064 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6065 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6066 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
6067 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
6068 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6069 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6070 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
6071 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
6072 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
6073 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
6074 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
6075 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
6076 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
6077 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
6078 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
6079 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6080 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
6081 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
6082 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32
6083 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
6084 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32
6085 // CHECK9-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
6086 // CHECK9-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
6087 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6088 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6089 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6090 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
6091 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6092 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6093 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
6094 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6095 // CHECK9: cond.true:
6096 // CHECK9-NEXT: br label [[COND_END:%.*]]
6097 // CHECK9: cond.false:
6098 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6099 // CHECK9-NEXT: br label [[COND_END]]
6100 // CHECK9: cond.end:
6101 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
6102 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6103 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6104 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
6105 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6106 // CHECK9: omp.inner.for.cond:
6107 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6108 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6109 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
6110 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6111 // CHECK9: omp.inner.for.body:
6112 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6113 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
6114 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6115 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
6116 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8
6117 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
6118 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
6119 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8
6120 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
6121 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
6122 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
6123 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
6124 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
6125 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
6126 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
6127 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
6128 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6129 // CHECK9: omp.body.continue:
6130 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6131 // CHECK9: omp.inner.for.inc:
6132 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6133 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
6134 // CHECK9-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
6135 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
6136 // CHECK9: omp.inner.for.end:
6137 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6138 // CHECK9: omp.loop.exit:
6139 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
6140 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6141 // CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
6142 // CHECK9-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6143 // CHECK9: .omp.final.then:
6144 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
6145 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
6146 // CHECK9: .omp.final.done:
6147 // CHECK9-NEXT: ret void
6148 //
6149 //
6150 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
6151 // CHECK9-SAME: () #[[ATTR0]] {
6152 // CHECK9-NEXT: entry:
6153 // CHECK9-NEXT: call void @__cxx_global_var_init()
6154 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
6155 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
6156 // CHECK9-NEXT: ret void
6157 //
6158 //
6159 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
6160 // CHECK9-SAME: () #[[ATTR0]] {
6161 // CHECK9-NEXT: entry:
6162 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
6163 // CHECK9-NEXT: ret void
6164 //
6165 //
6166 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init
6167 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
6168 // CHECK10-NEXT: entry:
6169 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
6170 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
6171 // CHECK10-NEXT: ret void
6172 //
6173 //
6174 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
6175 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
6176 // CHECK10-NEXT: entry:
6177 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6178 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6179 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6180 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
6181 // CHECK10-NEXT: ret void
6182 //
6183 //
6184 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
6185 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6186 // CHECK10-NEXT: entry:
6187 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6188 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6189 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6190 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
6191 // CHECK10-NEXT: ret void
6192 //
6193 //
6194 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
6195 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6196 // CHECK10-NEXT: entry:
6197 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6198 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6199 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6200 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
6201 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
6202 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
6203 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4
6204 // CHECK10-NEXT: ret void
6205 //
6206 //
6207 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
6208 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6209 // CHECK10-NEXT: entry:
6210 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6211 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6212 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6213 // CHECK10-NEXT: ret void
6214 //
6215 //
6216 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
6217 // CHECK10-SAME: () #[[ATTR0]] {
6218 // CHECK10-NEXT: entry:
6219 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
6220 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
6221 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
6222 // CHECK10-NEXT: ret void
6223 //
6224 //
6225 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
6226 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6227 // CHECK10-NEXT: entry:
6228 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6229 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
6230 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6231 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
6232 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6233 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
6234 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
6235 // CHECK10-NEXT: ret void
6236 //
6237 //
6238 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
6239 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
6240 // CHECK10-NEXT: entry:
6241 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
6242 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
6243 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
6244 // CHECK10: arraydestroy.body:
6245 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
6246 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
6247 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
6248 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
6249 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
6250 // CHECK10: arraydestroy.done1:
6251 // CHECK10-NEXT: ret void
6252 //
6253 //
6254 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
6255 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6256 // CHECK10-NEXT: entry:
6257 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6258 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
6259 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6260 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
6261 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6262 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
6263 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
6264 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
6265 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
6266 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
6267 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4
6268 // CHECK10-NEXT: ret void
6269 //
6270 //
6271 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
6272 // CHECK10-SAME: () #[[ATTR0]] {
6273 // CHECK10-NEXT: entry:
6274 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
6275 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
6276 // CHECK10-NEXT: ret void
6277 //
6278 //
6279 // CHECK10-LABEL: define {{[^@]+}}@main
6280 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
6281 // CHECK10-NEXT: entry:
6282 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
6283 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
6284 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
6285 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
6286 // CHECK10-NEXT: ret i32 0
6287 //
6288 //
6289 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
6290 // CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
6291 // CHECK10-NEXT: entry:
6292 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
6293 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
6294 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
6295 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8
6296 // CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
6297 // CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
6298 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
6299 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
6300 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
6301 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
6302 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
6303 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
6304 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
6305 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8
6306 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6307 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32*
6308 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4
6309 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8
6310 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8
6311 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4
6312 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
6313 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4
6314 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8
6315 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8
6316 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
6317 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4
6318 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
6319 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
6320 // CHECK10-NEXT: ret void
6321 //
6322 //
6323 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
6324 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
6325 // CHECK10-NEXT: entry:
6326 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6327 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6328 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
6329 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
6330 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
6331 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8
6332 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6333 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
6334 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
6335 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
6336 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6337 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6338 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
6339 // CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
6340 // CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
6341 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
6342 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6343 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6344 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
6345 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
6346 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
6347 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
6348 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
6349 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
6350 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
6351 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4
6352 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4
6353 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6354 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6355 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6356 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
6357 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6358 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6359 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
6360 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6361 // CHECK10: cond.true:
6362 // CHECK10-NEXT: br label [[COND_END:%.*]]
6363 // CHECK10: cond.false:
6364 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6365 // CHECK10-NEXT: br label [[COND_END]]
6366 // CHECK10: cond.end:
6367 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6368 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
6369 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
6370 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
6371 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6372 // CHECK10: omp.inner.for.cond:
6373 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6374 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6375 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6376 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6377 // CHECK10: omp.inner.for.body:
6378 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4
6379 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
6380 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4
6381 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
6382 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[CONV]], align 8
6383 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[G_CASTED]] to i32*
6384 // CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV5]], align 4
6385 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[G_CASTED]], align 8
6386 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
6387 // CHECK10-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[TMP13]], align 4
6388 // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[G1_CASTED]] to i32*
6389 // CHECK10-NEXT: store i32 [[TMP14]], i32* [[CONV6]], align 4
6390 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[G1_CASTED]], align 8
6391 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV2]], align 8
6392 // CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32*
6393 // CHECK10-NEXT: store i32 [[TMP16]], i32* [[CONV7]], align 4
6394 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8
6395 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
6396 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6397 // CHECK10: omp.inner.for.inc:
6398 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6399 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
6400 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
6401 // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
6402 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
6403 // CHECK10: omp.inner.for.end:
6404 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6405 // CHECK10: omp.loop.exit:
6406 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
6407 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6408 // CHECK10-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
6409 // CHECK10-NEXT: br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6410 // CHECK10: .omp.final.then:
6411 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
6412 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
6413 // CHECK10: .omp.final.done:
6414 // CHECK10-NEXT: ret void
6415 //
6416 //
6417 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
6418 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] {
6419 // CHECK10-NEXT: entry:
6420 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6421 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6422 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
6423 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
6424 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
6425 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
6426 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
6427 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8
6428 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
6429 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
6430 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
6431 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
6432 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6433 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6434 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
6435 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
6436 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6437 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6438 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8
6439 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8
6440 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8
6441 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
6442 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8
6443 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32*
6444 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
6445 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32*
6446 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8
6447 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
6448 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
6449 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8
6450 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP0]] to i32
6451 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8
6452 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP1]] to i32
6453 // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_LB]], align 4
6454 // CHECK10-NEXT: store i32 [[CONV5]], i32* [[DOTOMP_UB]], align 4
6455 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
6456 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
6457 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
6458 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
6459 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
6460 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6461 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
6462 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6463 // CHECK10: cond.true:
6464 // CHECK10-NEXT: br label [[COND_END:%.*]]
6465 // CHECK10: cond.false:
6466 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6467 // CHECK10-NEXT: br label [[COND_END]]
6468 // CHECK10: cond.end:
6469 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
6470 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
6471 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
6472 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
6473 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
6474 // CHECK10: omp.inner.for.cond:
6475 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6476 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
6477 // CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
6478 // CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6479 // CHECK10: omp.inner.for.body:
6480 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6481 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
6482 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6483 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
6484 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8
6485 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[TMP]], align 8
6486 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4
6487 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8
6488 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
6489 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP11]], align 8
6490 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
6491 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[TMP]], align 8
6492 // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8
6493 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
6494 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP14]], align 8
6495 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
6496 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
6497 // CHECK10: omp.body.continue:
6498 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
6499 // CHECK10: omp.inner.for.inc:
6500 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
6501 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
6502 // CHECK10-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
6503 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
6504 // CHECK10: omp.inner.for.end:
6505 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
6506 // CHECK10: omp.loop.exit:
6507 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
6508 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
6509 // CHECK10-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
6510 // CHECK10-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6511 // CHECK10: .omp.final.then:
6512 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
6513 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
6514 // CHECK10: .omp.final.done:
6515 // CHECK10-NEXT: ret void
6516 //
6517 //
6518 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
6519 // CHECK10-SAME: () #[[ATTR0]] {
6520 // CHECK10-NEXT: entry:
6521 // CHECK10-NEXT: call void @__cxx_global_var_init()
6522 // CHECK10-NEXT: call void @__cxx_global_var_init.1()
6523 // CHECK10-NEXT: call void @__cxx_global_var_init.2()
6524 // CHECK10-NEXT: ret void
6525 //
6526 //
6527 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
6528 // CHECK10-SAME: () #[[ATTR0]] {
6529 // CHECK10-NEXT: entry:
6530 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
6531 // CHECK10-NEXT: ret void
6532 //
6533 //
6534 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
6535 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
6536 // CHECK11-NEXT: entry:
6537 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
6538 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
6539 // CHECK11-NEXT: ret void
6540 //
6541 //
6542 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
6543 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
6544 // CHECK11-NEXT: entry:
6545 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6546 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6547 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6548 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
6549 // CHECK11-NEXT: ret void
6550 //
6551 //
6552 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
6553 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6554 // CHECK11-NEXT: entry:
6555 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6556 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6557 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6558 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
6559 // CHECK11-NEXT: ret void
6560 //
6561 //
6562 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
6563 // CHECK11-SAME: () #[[ATTR0]] {
6564 // CHECK11-NEXT: entry:
6565 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
6566 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
6567 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
6568 // CHECK11-NEXT: ret void
6569 //
6570 //
6571 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
6572 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6573 // CHECK11-NEXT: entry:
6574 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6575 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
6576 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6577 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
6578 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6579 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
6580 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
6581 // CHECK11-NEXT: ret void
6582 //
6583 //
6584 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
6585 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
6586 // CHECK11-NEXT: entry:
6587 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
6588 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
6589 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
6590 // CHECK11: arraydestroy.body:
6591 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
6592 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
6593 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
6594 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
6595 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
6596 // CHECK11: arraydestroy.done1:
6597 // CHECK11-NEXT: ret void
6598 //
6599 //
6600 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
6601 // CHECK11-SAME: () #[[ATTR0]] {
6602 // CHECK11-NEXT: entry:
6603 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
6604 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
6605 // CHECK11-NEXT: ret void
6606 //
6607 //
6608 // CHECK11-LABEL: define {{[^@]+}}@main
6609 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
6610 // CHECK11-NEXT: entry:
6611 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
6612 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
6613 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
6614 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
6615 // CHECK11-NEXT: ret i32 0
6616 //
6617 //
6618 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
6619 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6620 // CHECK11-NEXT: entry:
6621 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6622 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6623 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6624 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
6625 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
6626 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
6627 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4
6628 // CHECK11-NEXT: ret void
6629 //
6630 //
6631 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
6632 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6633 // CHECK11-NEXT: entry:
6634 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6635 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6636 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6637 // CHECK11-NEXT: ret void
6638 //
6639 //
6640 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
6641 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6642 // CHECK11-NEXT: entry:
6643 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6644 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
6645 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6646 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
6647 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6648 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
6649 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
6650 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
6651 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
6652 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
6653 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4
6654 // CHECK11-NEXT: ret void
6655 //
6656 //
6657 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
6658 // CHECK11-SAME: () #[[ATTR0]] {
6659 // CHECK11-NEXT: entry:
6660 // CHECK11-NEXT: call void @__cxx_global_var_init()
6661 // CHECK11-NEXT: call void @__cxx_global_var_init.1()
6662 // CHECK11-NEXT: call void @__cxx_global_var_init.2()
6663 // CHECK11-NEXT: ret void
6664 //
6665 //
6666 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init
6667 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
6668 // CHECK12-NEXT: entry:
6669 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
6670 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
6671 // CHECK12-NEXT: ret void
6672 //
6673 //
6674 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
6675 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
6676 // CHECK12-NEXT: entry:
6677 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6678 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6679 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6680 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
6681 // CHECK12-NEXT: ret void
6682 //
6683 //
6684 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
6685 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6686 // CHECK12-NEXT: entry:
6687 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6688 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6689 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6690 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
6691 // CHECK12-NEXT: ret void
6692 //
6693 //
6694 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
6695 // CHECK12-SAME: () #[[ATTR0]] {
6696 // CHECK12-NEXT: entry:
6697 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
6698 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
6699 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
6700 // CHECK12-NEXT: ret void
6701 //
6702 //
6703 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
6704 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6705 // CHECK12-NEXT: entry:
6706 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6707 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
6708 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6709 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
6710 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6711 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
6712 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
6713 // CHECK12-NEXT: ret void
6714 //
6715 //
6716 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
6717 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
6718 // CHECK12-NEXT: entry:
6719 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
6720 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
6721 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
6722 // CHECK12: arraydestroy.body:
6723 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
6724 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
6725 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
6726 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
6727 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
6728 // CHECK12: arraydestroy.done1:
6729 // CHECK12-NEXT: ret void
6730 //
6731 //
6732 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
6733 // CHECK12-SAME: () #[[ATTR0]] {
6734 // CHECK12-NEXT: entry:
6735 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
6736 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
6737 // CHECK12-NEXT: ret void
6738 //
6739 //
6740 // CHECK12-LABEL: define {{[^@]+}}@main
6741 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] {
6742 // CHECK12-NEXT: entry:
6743 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
6744 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
6745 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
6746 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
6747 // CHECK12-NEXT: ret i32 0
6748 //
6749 //
6750 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
6751 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6752 // CHECK12-NEXT: entry:
6753 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6754 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6755 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6756 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
6757 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
6758 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
6759 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4
6760 // CHECK12-NEXT: ret void
6761 //
6762 //
6763 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
6764 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6765 // CHECK12-NEXT: entry:
6766 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6767 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6768 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6769 // CHECK12-NEXT: ret void
6770 //
6771 //
6772 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
6773 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
6774 // CHECK12-NEXT: entry:
6775 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
6776 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
6777 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
6778 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
6779 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
6780 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
6781 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
6782 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
6783 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
6784 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
6785 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4
6786 // CHECK12-NEXT: ret void
6787 //
6788 //
6789 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
6790 // CHECK12-SAME: () #[[ATTR0]] {
6791 // CHECK12-NEXT: entry:
6792 // CHECK12-NEXT: call void @__cxx_global_var_init()
6793 // CHECK12-NEXT: call void @__cxx_global_var_init.1()
6794 // CHECK12-NEXT: call void @__cxx_global_var_init.2()
6795 // CHECK12-NEXT: ret void
6796 //
6797