1unit stm32f411xe; 2interface 3{$PACKRECORDS 2} 4{$GOTO ON} 5{$MODESWITCH ADVANCEDRECORDS} 6// * 7// ****************************************************************************** 8// * @file stm32f411xe.h 9// * @author MCD Application Team 10// * @version V2.4.0 11// * @date 14-August-2015 12// CMSIS STM32F411xExx Device Peripheral Access Layer Header File. 13// * 14// * This file contains: 15// * - Data structures and the address mapping for all peripherals 16// * - Peripheral's registers declarations and bits definition 17// * - Macros to access peripheral�s registers hardware 18// * 19// ****************************************************************************** 20// * @attention 21// * 22// * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 23// * 24// * Redistribution and use in source and binary forms, with or without modification, 25// * are permitted provided that the following conditions are met: 26// * 1. Redistributions of source code must retain the above copyright notice, 27// * this list of conditions and the following disclaimer. 28// * 2. Redistributions in binary form must reproduce the above copyright notice, 29// * this list of conditions and the following disclaimer in the documentation 30// * and/or other materials provided with the distribution. 31// * 3. Neither the name of STMicroelectronics nor the names of its contributors 32// * may be used to endorse or promote products derived from this software 33// * without specific prior written permission. 34// * 35// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 36// * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37// * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 38// * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 39// * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40// * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 41// * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 42// * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 43// * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44// * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45// * 46// ****************************************************************************** 47// Configuration of the Cortex-M4 Processor and Core Peripherals 48// STM32F4XX Interrupt Number Definition, according to the selected device 49// * in @ref Library_configuration_section 50 51type 52 TIRQn_Enum = ( 53 NonMaskableInt_IRQn = -14, // 2 Non Maskable Interrupt 54 MemoryManagement_IRQn = -12, // 4 Cortex-M4 Memory Management Interrupt 55 BusFault_IRQn = -11, // 5 Cortex-M4 Bus Fault Interrupt 56 UsageFault_IRQn = -10, // 6 Cortex-M4 Usage Fault Interrupt 57 SVCall_IRQn = -5, // 11 Cortex-M4 SV Call Interrupt 58 DebugMonitor_IRQn = -4, // 12 Cortex-M4 Debug Monitor Interrupt 59 PendSV_IRQn = -2, // 14 Cortex-M4 Pend SV Interrupt 60 SysTick_IRQn = -1, // 15 Cortex-M4 System Tick Interrupt 61 WWDG_IRQn = 0, // Window WatchDog Interrupt 62 PVD_IRQn = 1, // PVD through EXTI Line detection Interrupt 63 TAMP_STAMP_IRQn = 2, // Tamper and TimeStamp interrupts through the EXTI line 64 RTC_WKUP_IRQn = 3, // RTC Wakeup interrupt through the EXTI line 65 FLASH_IRQn = 4, // FLASH global Interrupt 66 RCC_IRQn = 5, // RCC global Interrupt 67 EXTI0_IRQn = 6, // EXTI Line0 Interrupt 68 EXTI1_IRQn = 7, // EXTI Line1 Interrupt 69 EXTI2_IRQn = 8, // EXTI Line2 Interrupt 70 EXTI3_IRQn = 9, // EXTI Line3 Interrupt 71 EXTI4_IRQn = 10, // EXTI Line4 Interrupt 72 DMA1_Stream0_IRQn = 11, // DMA1 Stream 0 global Interrupt 73 DMA1_Stream1_IRQn = 12, // DMA1 Stream 1 global Interrupt 74 DMA1_Stream2_IRQn = 13, // DMA1 Stream 2 global Interrupt 75 DMA1_Stream3_IRQn = 14, // DMA1 Stream 3 global Interrupt 76 DMA1_Stream4_IRQn = 15, // DMA1 Stream 4 global Interrupt 77 DMA1_Stream5_IRQn = 16, // DMA1 Stream 5 global Interrupt 78 DMA1_Stream6_IRQn = 17, // DMA1 Stream 6 global Interrupt 79 ADC_IRQn = 18, // ADC1, ADC2 and ADC3 global Interrupts 80 EXTI9_5_IRQn = 23, // External Line[9:5] Interrupts 81 TIM1_BRK_TIM9_IRQn = 24, // TIM1 Break interrupt and TIM9 global interrupt 82 TIM1_UP_TIM10_IRQn = 25, // TIM1 Update Interrupt and TIM10 global interrupt 83 TIM1_TRG_COM_TIM11_IRQn = 26, // TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt 84 TIM1_CC_IRQn = 27, // TIM1 Capture Compare Interrupt 85 TIM2_IRQn = 28, // TIM2 global Interrupt 86 TIM3_IRQn = 29, // TIM3 global Interrupt 87 TIM4_IRQn = 30, // TIM4 global Interrupt 88 I2C1_EV_IRQn = 31, // I2C1 Event Interrupt 89 I2C1_ER_IRQn = 32, // I2C1 Error Interrupt 90 I2C2_EV_IRQn = 33, // I2C2 Event Interrupt 91 I2C2_ER_IRQn = 34, // I2C2 Error Interrupt 92 SPI1_IRQn = 35, // SPI1 global Interrupt 93 SPI2_IRQn = 36, // SPI2 global Interrupt 94 USART1_IRQn = 37, // USART1 global Interrupt 95 USART2_IRQn = 38, // USART2 global Interrupt 96 EXTI15_10_IRQn = 40, // External Line[15:10] Interrupts 97 RTC_Alarm_IRQn = 41, // RTC Alarm (A and B) through EXTI Line Interrupt 98 OTG_FS_WKUP_IRQn = 42, // USB OTG FS Wakeup through EXTI line interrupt 99 DMA1_Stream7_IRQn = 47, // DMA1 Stream7 Interrupt 100 SDIO_IRQn = 49, // SDIO global Interrupt 101 TIM5_IRQn = 50, // TIM5 global Interrupt 102 SPI3_IRQn = 51, // SPI3 global Interrupt 103 DMA2_Stream0_IRQn = 56, // DMA2 Stream 0 global Interrupt 104 DMA2_Stream1_IRQn = 57, // DMA2 Stream 1 global Interrupt 105 DMA2_Stream2_IRQn = 58, // DMA2 Stream 2 global Interrupt 106 DMA2_Stream3_IRQn = 59, // DMA2 Stream 3 global Interrupt 107 DMA2_Stream4_IRQn = 60, // DMA2 Stream 4 global Interrupt 108 OTG_FS_IRQn = 67, // USB OTG FS global Interrupt 109 DMA2_Stream5_IRQn = 68, // DMA2 Stream 5 global interrupt 110 DMA2_Stream6_IRQn = 69, // DMA2 Stream 6 global interrupt 111 DMA2_Stream7_IRQn = 70, // DMA2 Stream 7 global interrupt 112 USART6_IRQn = 71, // USART6 global interrupt 113 I2C3_EV_IRQn = 72, // I2C3 event interrupt 114 I2C3_ER_IRQn = 73, // I2C3 error interrupt 115 FPU_IRQn = 81, // FPU global interrupt 116 SPI4_IRQn = 84, // SPI4 global Interrupt 117 SPI5_IRQn = 85 // SPI5 global Interrupt 118 ); 119 120 TADC_Registers = record 121 SR : longword; // ADC status register 122 CR1 : longword; // ADC control register 1 123 CR2 : longword; // ADC control register 2 124 SMPR1 : longword; // ADC sample time register 1 125 SMPR2 : longword; // ADC sample time register 2 126 JOFR1 : longword; // ADC injected channel data offset register 1 127 JOFR2 : longword; // ADC injected channel data offset register 2 128 JOFR3 : longword; // ADC injected channel data offset register 3 129 JOFR4 : longword; // ADC injected channel data offset register 4 130 HTR : longword; // ADC watchdog higher threshold register 131 LTR : longword; // ADC watchdog lower threshold register 132 SQR1 : longword; // ADC regular sequence register 1 133 SQR2 : longword; // ADC regular sequence register 2 134 SQR3 : longword; // ADC regular sequence register 3 135 JSQR : longword; // ADC injected sequence register 136 JDR1 : longword; // ADC injected data register 1 137 JDR2 : longword; // ADC injected data register 2 138 JDR3 : longword; // ADC injected data register 3 139 JDR4 : longword; // ADC injected data register 4 140 DR : longword; // ADC regular data register 141 end; 142 143 TADC_COMMON_Registers = record 144 CSR : longword; // ADC Common status register 145 CCR : longword; // ADC common control register 146 CDR : longword; // ADC common regular data register for dual 147 end; 148 149 TCRC_Registers = record 150 DR : longword; // CRC Data register 151 IDR : byte; // CRC Independent data register 152 RESERVED0 : byte; // Reserved, 0x05 153 RESERVED1 : word; // Reserved, 0x06 154 CR : longword; // CRC Control register 155 end; 156 157 TDBGMCU_Registers = record 158 IDCODE : longword; // MCU device ID code 159 CR : longword; // Debug MCU configuration register 160 APB1FZ : longword; // Debug MCU APB1 freeze register 161 APB2FZ : longword; // Debug MCU APB2 freeze register 162 end; 163 164 TDMA_STREAM_Registers = record 165 CR : longword; // DMA stream x configuration register 166 NDTR : longword; // DMA stream x number of data register 167 PAR : longword; // DMA stream x peripheral address register 168 M0AR : longword; // DMA stream x memory 0 address register 169 M1AR : longword; // DMA stream x memory 1 address register 170 FCR : longword; // DMA stream x FIFO control register 171 end; 172 173 TDMA_Registers = record 174 LISR : longword; // DMA low interrupt status register 175 HISR : longword; // DMA high interrupt status register 176 LIFCR : longword; // DMA low interrupt flag clear register 177 HIFCR : longword; // DMA high interrupt flag clear register 178 end; 179 180 TEXTI_Registers = record 181 IMR : longword; // EXTI Interrupt mask register 182 EMR : longword; // EXTI Event mask register 183 RTSR : longword; // EXTI Rising trigger selection register 184 FTSR : longword; // EXTI Falling trigger selection register 185 SWIER : longword; // EXTI Software interrupt event register 186 PR : longword; // EXTI Pending register 187 end; 188 189 TFLASH_Registers = record 190 ACR : longword; // FLASH access control register 191 KEYR : longword; // FLASH key register 192 OPTKEYR : longword; // FLASH option key register 193 SR : longword; // FLASH status register 194 CR : longword; // FLASH control register 195 OPTCR : longword; // FLASH option control register 196 OPTCR1 : longword; // FLASH option control register 1 197 end; 198 199 TGPIO_Registers = record 200 MODER : longword; // GPIO port mode register 201 OTYPER : longword; // GPIO port output type register 202 OSPEEDR : longword; // GPIO port output speed register 203 PUPDR : longword; // GPIO port pull-up/pull-down register 204 IDR : longword; // GPIO port input data register 205 ODR : longword; // GPIO port output data register 206 BSRR : longword; // GPIO port bit set/reset register 207 LCKR : longword; // GPIO port configuration lock register 208 AFR : array[0..1] of longword; // GPIO alternate function registers 209 end; 210 211 TSYSCFG_Registers = record 212 MEMRMP : longword; // SYSCFG memory remap register 213 PMC : longword; // SYSCFG peripheral mode configuration register 214 EXTICR : array[0..3] of longword; // SYSCFG external interrupt configuration registers 215 RESERVED : array[0..1] of longword; // Reserved, 0x18-0x1C 216 CMPCR : longword; // SYSCFG Compensation cell control register 217 end; 218 219 TI2C_Registers = record 220 CR1 : longword; // I2C Control register 1 221 CR2 : longword; // I2C Control register 2 222 OAR1 : longword; // I2C Own address register 1 223 OAR2 : longword; // I2C Own address register 2 224 DR : longword; // I2C Data register 225 SR1 : longword; // I2C Status register 1 226 SR2 : longword; // I2C Status register 2 227 CCR : longword; // I2C Clock control register 228 TRISE : longword; // I2C TRISE register 229 FLTR : longword; // I2C FLTR register 230 end; 231 232 TIWDG_Registers = record 233 KR : longword; // IWDG Key register 234 PR : longword; // IWDG Prescaler register 235 RLR : longword; // IWDG Reload register 236 SR : longword; // IWDG Status register 237 end; 238 239 TPWR_Registers = record 240 CR : longword; // PWR power control register 241 CSR : longword; // PWR power control/status register 242 end; 243 244 TRCC_Registers = record 245 CR : longword; // RCC clock control register 246 PLLCFGR : longword; // RCC PLL configuration register 247 CFGR : longword; // RCC clock configuration register 248 CIR : longword; // RCC clock interrupt register 249 AHB1RSTR : longword; // RCC AHB1 peripheral reset register 250 AHB2RSTR : longword; // RCC AHB2 peripheral reset register 251 AHB3RSTR : longword; // RCC AHB3 peripheral reset register 252 RESERVED0 : longword; // Reserved, 0x1C 253 APB1RSTR : longword; // RCC APB1 peripheral reset register 254 APB2RSTR : longword; // RCC APB2 peripheral reset register 255 RESERVED1 : array[0..1] of longword; // Reserved, 0x28-0x2C 256 AHB1ENR : longword; // RCC AHB1 peripheral clock register 257 AHB2ENR : longword; // RCC AHB2 peripheral clock register 258 AHB3ENR : longword; // RCC AHB3 peripheral clock register 259 RESERVED2 : longword; // Reserved, 0x3C 260 APB1ENR : longword; // RCC APB1 peripheral clock enable register 261 APB2ENR : longword; // RCC APB2 peripheral clock enable register 262 RESERVED3 : array[0..1] of longword; // Reserved, 0x48-0x4C 263 AHB1LPENR : longword; // RCC AHB1 peripheral clock enable in low power mode register 264 AHB2LPENR : longword; // RCC AHB2 peripheral clock enable in low power mode register 265 AHB3LPENR : longword; // RCC AHB3 peripheral clock enable in low power mode register 266 RESERVED4 : longword; // Reserved, 0x5C 267 APB1LPENR : longword; // RCC APB1 peripheral clock enable in low power mode register 268 APB2LPENR : longword; // RCC APB2 peripheral clock enable in low power mode register 269 RESERVED5 : array[0..1] of longword; // Reserved, 0x68-0x6C 270 BDCR : longword; // RCC Backup domain control register 271 CSR : longword; // RCC clock control & status register 272 RESERVED6 : array[0..1] of longword; // Reserved, 0x78-0x7C 273 SSCGR : longword; // RCC spread spectrum clock generation register 274 PLLI2SCFGR : longword; // RCC PLLI2S configuration register 275 RESERVED7 : longword; // Reserved 0x88 276 DCKCFGR : longword; // RCC Dedicated Clocks Configuration Register 277 end; 278 279 TRTC_Registers = record 280 TR : longword; // RTC time register 281 DR : longword; // RTC date register 282 CR : longword; // RTC control register 283 ISR : longword; // RTC initialization and status register 284 PRER : longword; // RTC prescaler register 285 WUTR : longword; // RTC wakeup timer register 286 CALIBR : longword; // RTC calibration register 287 ALRMAR : longword; // RTC alarm A register 288 ALRMBR : longword; // RTC alarm B register 289 WPR : longword; // RTC write protection register 290 SSR : longword; // RTC sub second register 291 SHIFTR : longword; // RTC shift control register 292 TSTR : longword; // RTC time stamp time register 293 TSDR : longword; // RTC time stamp date register 294 TSSSR : longword; // RTC time-stamp sub second register 295 CALR : longword; // RTC calibration register 296 TAFCR : longword; // RTC tamper and alternate function configuration register 297 ALRMASSR : longword; // RTC alarm A sub second register 298 ALRMBSSR : longword; // RTC alarm B sub second register 299 RESERVED7 : longword; // Reserved, 0x4C 300 BKP0R : longword; // RTC backup register 1 301 BKP1R : longword; // RTC backup register 1 302 BKP2R : longword; // RTC backup register 2 303 BKP3R : longword; // RTC backup register 3 304 BKP4R : longword; // RTC backup register 4 305 BKP5R : longword; // RTC backup register 5 306 BKP6R : longword; // RTC backup register 6 307 BKP7R : longword; // RTC backup register 7 308 BKP8R : longword; // RTC backup register 8 309 BKP9R : longword; // RTC backup register 9 310 BKP10R : longword; // RTC backup register 10 311 BKP11R : longword; // RTC backup register 11 312 BKP12R : longword; // RTC backup register 12 313 BKP13R : longword; // RTC backup register 13 314 BKP14R : longword; // RTC backup register 14 315 BKP15R : longword; // RTC backup register 15 316 BKP16R : longword; // RTC backup register 16 317 BKP17R : longword; // RTC backup register 17 318 BKP18R : longword; // RTC backup register 18 319 BKP19R : longword; // RTC backup register 19 320 end; 321 322 TSDIO_Registers = record 323 POWER : longword; // SDIO power control register 324 CLKCR : longword; // SDI clock control register 325 ARG : longword; // SDIO argument register 326 CMD : longword; // SDIO command register 327 RESPCMD : longword; // SDIO command response register 328 RESP1 : longword; // SDIO response 1 register 329 RESP2 : longword; // SDIO response 2 register 330 RESP3 : longword; // SDIO response 3 register 331 RESP4 : longword; // SDIO response 4 register 332 DTIMER : longword; // SDIO data timer register 333 DLEN : longword; // SDIO data length register 334 DCTRL : longword; // SDIO data control register 335 DCOUNT : longword; // SDIO data counter register 336 STA : longword; // SDIO status register 337 ICR : longword; // SDIO interrupt clear register 338 MASK : longword; // SDIO mask register 339 RESERVED0 : array[0..1] of longword; // Reserved, 0x40-0x44 340 FIFOCNT : longword; // SDIO FIFO counter register 341 RESERVED1 : array[0..12] of longword; // Reserved, 0x4C-0x7C 342 FIFO : longword; // SDIO data FIFO register 343 end; 344 345 TSPI_Registers = record 346 CR1 : longword; // SPI control register 1 (not used in I2S mode) 347 CR2 : longword; // SPI control register 2 348 SR : longword; // SPI status register 349 DR : longword; // SPI data register 350 CRCPR : longword; // SPI CRC polynomial register (not used in I2S mode) 351 RXCRCR : longword; // SPI RX CRC register (not used in I2S mode) 352 TXCRCR : longword; // SPI TX CRC register (not used in I2S mode) 353 I2SCFGR : longword; // SPI_I2S configuration register 354 I2SPR : longword; // SPI_I2S prescaler register 355 end; 356 357 TTIM_Registers = record 358 CR1 : longword; // TIM control register 1 359 CR2 : longword; // TIM control register 2 360 SMCR : longword; // TIM slave mode control register 361 DIER : longword; // TIM DMA/interrupt enable register 362 SR : longword; // TIM status register 363 EGR : longword; // TIM event generation register 364 CCMR1 : longword; // TIM capture/compare mode register 1 365 CCMR2 : longword; // TIM capture/compare mode register 2 366 CCER : longword; // TIM capture/compare enable register 367 CNT : longword; // TIM counter register 368 PSC : longword; // TIM prescaler 369 ARR : longword; // TIM auto-reload register 370 RCR : longword; // TIM repetition counter register 371 CCR1 : longword; // TIM capture/compare register 1 372 CCR2 : longword; // TIM capture/compare register 2 373 CCR3 : longword; // TIM capture/compare register 3 374 CCR4 : longword; // TIM capture/compare register 4 375 BDTR : longword; // TIM break and dead-time register 376 DCR : longword; // TIM DMA control register 377 DMAR : longword; // TIM DMA address for full transfer 378 &OR : longword; // TIM option register 379 end; 380 381 TUSART_Registers = record 382 SR : longword; // USART Status register 383 DR : longword; // USART Data register 384 BRR : longword; // USART Baud rate register 385 CR1 : longword; // USART Control register 1 386 CR2 : longword; // USART Control register 2 387 CR3 : longword; // USART Control register 3 388 GTPR : longword; // USART Guard time and prescaler register 389 end; 390 391 TWWDG_Registers = record 392 CR : longword; // WWDG Control register 393 CFR : longword; // WWDG Configuration register 394 SR : longword; // WWDG Status register 395 end; 396 397 TUSB_OTG_GLOBAL_Registers = record 398 GOTGCTL : longword; // USB_OTG Control and Status Register 399 GOTGINT : longword; // USB_OTG Interrupt Register 400 GAHBCFG : longword; // Core AHB Configuration Register 401 GUSBCFG : longword; // Core USB Configuration Register 402 GRSTCTL : longword; // Core Reset Register 403 GINTSTS : longword; // Core Interrupt Register 404 GINTMSK : longword; // Core Interrupt Mask Register 405 GRXSTSR : longword; // Receive Sts Q Read Register 406 GRXSTSP : longword; // Receive Sts Q Read & POP Register 407 GRXFSIZ : longword; // Receive FIFO Size Register 408 DIEPTXF0_HNPTXFSIZ : longword; // EP0 / Non Periodic Tx FIFO Size Register 409 HNPTXSTS : longword; // Non Periodic Tx FIFO/Queue Sts reg 410 RESERVED30 : array[0..1] of longword; // Reserved 411 GCCFG : longword; // General Purpose IO Register 412 CID : longword; // User ID Register 413 RESERVED40 : array[0..47] of longword; // Reserved 414 HPTXFSIZ : longword; // Host Periodic Tx FIFO Size Reg 415 DIEPTXF : array[0..14] of longword; // dev Periodic Transmit FIFO 416 end; 417 418 TUSB_OTG_DEVICE_Registers = record 419 DCFG : longword; // dev Configuration Register 420 DCTL : longword; // dev Control Register 421 DSTS : longword; // dev Status Register (RO) 422 RESERVED0C : longword; // Reserved 423 DIEPMSK : longword; // dev IN Endpoint Mask 424 DOEPMSK : longword; // dev OUT Endpoint Mask 425 DAINT : longword; // dev All Endpoints Itr Reg 426 DAINTMSK : longword; // dev All Endpoints Itr Mask 427 RESERVED20 : longword; // Reserved 428 RESERVED9 : longword; // Reserved 429 DVBUSDIS : longword; // dev VBUS discharge Register 430 DVBUSPULSE : longword; // dev VBUS Pulse Register 431 DTHRCTL : longword; // dev thr 432 DIEPEMPMSK : longword; // dev empty msk 433 DEACHINT : longword; // dedicated EP interrupt 434 DEACHMSK : longword; // dedicated EP msk 435 RESERVED40 : longword; // dedicated EP mask 436 DINEP1MSK : longword; // dedicated EP mask 437 RESERVED44 : array[0..14] of longword; // Reserved 438 DOUTEP1MSK : longword; // dedicated EP msk 439 end; 440 441 TUSB_OTG_INENDPOINT_Registers = record 442 DIEPCTL : longword; // dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h 443 RESERVED04 : longword; // Reserved 900h + (ep_num * 20h) + 04h 444 DIEPINT : longword; // dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h 445 RESERVED0C : longword; // Reserved 900h + (ep_num * 20h) + 0Ch 446 DIEPTSIZ : longword; // IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h 447 DIEPDMA : longword; // IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h 448 DTXFSTS : longword; // IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h 449 RESERVED18 : longword; // Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch 450 end; 451 452 TUSB_OTG_OUTENDPOINT_Registers = record 453 DOEPCTL : longword; // dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h 454 RESERVED04 : longword; // Reserved B00h + (ep_num * 20h) + 04h 455 DOEPINT : longword; // dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h 456 RESERVED0C : longword; // Reserved B00h + (ep_num * 20h) + 0Ch 457 DOEPTSIZ : longword; // dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h 458 DOEPDMA : longword; // dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h 459 RESERVED18 : array[0..1] of longword; // Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch 460 end; 461 462 TUSB_OTG_HOST_Registers = record 463 HCFG : longword; // Host Configuration Register 400h 464 HFIR : longword; // Host Frame Interval Register 404h 465 HFNUM : longword; // Host Frame Nbr/Frame Remaining 408h 466 RESERVED40C : longword; // Reserved 40Ch 467 HPTXSTS : longword; // Host Periodic Tx FIFO/ Queue Status 410h 468 HAINT : longword; // Host All Channels Interrupt Register 414h 469 HAINTMSK : longword; // Host All Channels Interrupt Mask 418h 470 end; 471 472 TUSB_OTG_HOSTCHANNEL_Registers = record 473 HCCHAR : longword; 474 HCSPLT : longword; 475 HCINT : longword; 476 HCINTMSK : longword; 477 HCTSIZ : longword; 478 HCDMA : longword; 479 RESERVED : array[0..1] of longword; 480 end; 481 482const 483 FLASH_BASE = $08000000; // FLASH(up to 1 MB) base address in the alias region 484 CCMDATARAM_BASE = $10000000; // CCM(core coupled memory) data RAM(64 KB) base address in the alias region 485 SRAM1_BASE = $20000000; // SRAM1(112 KB) base address in the alias region 486 SRAM2_BASE = $2001C000; // SRAM2(16 KB) base address in the alias region 487 PERIPH_BASE = $40000000; // Peripheral base address in the alias region 488 BKPSRAM_BASE = $40024000; // Backup SRAM(4 KB) base address in the alias region 489 SRAM1_BB_BASE = $22000000; // SRAM1(112 KB) base address in the bit-band region 490 SRAM2_BB_BASE = $22380000; // SRAM2(16 KB) base address in the bit-band region 491 PERIPH_BB_BASE = $42000000; // Peripheral base address in the bit-band region 492 BKPSRAM_BB_BASE = $42480000; // Backup SRAM(4 KB) base address in the bit-band region 493 SRAM_BASE = $20000000; 494 SRAM_BB_BASE = $22000000; 495 APB1PERIPH_BASE = $40000000; 496 APB2PERIPH_BASE = PERIPH_BASE + $00010000; 497 AHB1PERIPH_BASE = PERIPH_BASE + $00020000; 498 AHB2PERIPH_BASE = PERIPH_BASE + $10000000; 499 TIM2_BASE = APB1PERIPH_BASE + $0000; 500 TIM3_BASE = APB1PERIPH_BASE + $0400; 501 TIM4_BASE = APB1PERIPH_BASE + $0800; 502 TIM5_BASE = APB1PERIPH_BASE + $0C00; 503 RTC_BASE = APB1PERIPH_BASE + $2800; 504 WWDG_BASE = APB1PERIPH_BASE + $2C00; 505 IWDG_BASE = APB1PERIPH_BASE + $3000; 506 I2S2ext_BASE = APB1PERIPH_BASE + $3400; 507 SPI2_BASE = APB1PERIPH_BASE + $3800; 508 SPI3_BASE = APB1PERIPH_BASE + $3C00; 509 I2S3ext_BASE = APB1PERIPH_BASE + $4000; 510 USART2_BASE = APB1PERIPH_BASE + $4400; 511 I2C1_BASE = APB1PERIPH_BASE + $5400; 512 I2C2_BASE = APB1PERIPH_BASE + $5800; 513 I2C3_BASE = APB1PERIPH_BASE + $5C00; 514 PWR_BASE = APB1PERIPH_BASE + $7000; 515 TIM1_BASE = APB2PERIPH_BASE + $0000; 516 USART1_BASE = APB2PERIPH_BASE + $1000; 517 USART6_BASE = APB2PERIPH_BASE + $1400; 518 ADC1_BASE = APB2PERIPH_BASE + $2000; 519 ADC_BASE = APB2PERIPH_BASE + $2300; 520 SDIO_BASE = APB2PERIPH_BASE + $2C00; 521 SPI1_BASE = APB2PERIPH_BASE + $3000; 522 SPI4_BASE = APB2PERIPH_BASE + $3400; 523 SYSCFG_BASE = APB2PERIPH_BASE + $3800; 524 EXTI_BASE = APB2PERIPH_BASE + $3C00; 525 TIM9_BASE = APB2PERIPH_BASE + $4000; 526 TIM10_BASE = APB2PERIPH_BASE + $4400; 527 TIM11_BASE = APB2PERIPH_BASE + $4800; 528 SPI5_BASE = APB2PERIPH_BASE + $5000; 529 GPIOA_BASE = AHB1PERIPH_BASE + $0000; 530 GPIOB_BASE = AHB1PERIPH_BASE + $0400; 531 GPIOC_BASE = AHB1PERIPH_BASE + $0800; 532 GPIOD_BASE = AHB1PERIPH_BASE + $0C00; 533 GPIOE_BASE = AHB1PERIPH_BASE + $1000; 534 GPIOH_BASE = AHB1PERIPH_BASE + $1C00; 535 CRC_BASE = AHB1PERIPH_BASE + $3000; 536 RCC_BASE = AHB1PERIPH_BASE + $3800; 537 FLASH_R_BASE = AHB1PERIPH_BASE + $3C00; 538 DMA1_BASE = AHB1PERIPH_BASE + $6000; 539 DMA1_Stream0_BASE = DMA1_BASE + $010; 540 DMA1_Stream1_BASE = DMA1_BASE + $028; 541 DMA1_Stream2_BASE = DMA1_BASE + $040; 542 DMA1_Stream3_BASE = DMA1_BASE + $058; 543 DMA1_Stream4_BASE = DMA1_BASE + $070; 544 DMA1_Stream5_BASE = DMA1_BASE + $088; 545 DMA1_Stream6_BASE = DMA1_BASE + $0A0; 546 DMA1_Stream7_BASE = DMA1_BASE + $0B8; 547 DMA2_BASE = AHB1PERIPH_BASE + $6400; 548 DMA2_Stream0_BASE = DMA2_BASE + $010; 549 DMA2_Stream1_BASE = DMA2_BASE + $028; 550 DMA2_Stream2_BASE = DMA2_BASE + $040; 551 DMA2_Stream3_BASE = DMA2_BASE + $058; 552 DMA2_Stream4_BASE = DMA2_BASE + $070; 553 DMA2_Stream5_BASE = DMA2_BASE + $088; 554 DMA2_Stream6_BASE = DMA2_BASE + $0A0; 555 DMA2_Stream7_BASE = DMA2_BASE + $0B8; 556 DBGMCU_BASE = $E0042000; 557 USB_OTG_FS_PERIPH_BASE = $50000000; 558 USB_OTG_GLOBAL_BASE = $000; 559 USB_OTG_DEVICE_BASE = $800; 560 USB_OTG_IN_ENDPOINT_BASE = $900; 561 USB_OTG_OUT_ENDPOINT_BASE = $B00; 562 USB_OTG_HOST_BASE = $400; 563 USB_OTG_HOST_PORT_BASE = $440; 564 USB_OTG_HOST_CHANNEL_BASE = $500; 565 USB_OTG_PCGCCTL_BASE = $E00; 566 USB_OTG_FIFO_BASE = $1000; 567 568var 569 TIM2 : TTIM_Registers absolute TIM2_BASE; 570 TIM3 : TTIM_Registers absolute TIM3_BASE; 571 TIM4 : TTIM_Registers absolute TIM4_BASE; 572 TIM5 : TTIM_Registers absolute TIM5_BASE; 573 RTC : TRTC_Registers absolute RTC_BASE; 574 WWDG : TWWDG_Registers absolute WWDG_BASE; 575 IWDG : TIWDG_Registers absolute IWDG_BASE; 576 I2S2ext : TSPI_Registers absolute I2S2ext_BASE; 577 SPI2 : TSPI_Registers absolute SPI2_BASE; 578 SPI3 : TSPI_Registers absolute SPI3_BASE; 579 I2S3ext : TSPI_Registers absolute I2S3ext_BASE; 580 USART2 : TUSART_Registers absolute USART2_BASE; 581 I2C1 : TI2C_Registers absolute I2C1_BASE; 582 I2C2 : TI2C_Registers absolute I2C2_BASE; 583 I2C3 : TI2C_Registers absolute I2C3_BASE; 584 PWR : TPWR_Registers absolute PWR_BASE; 585 TIM1 : TTIM_Registers absolute TIM1_BASE; 586 USART1 : TUSART_Registers absolute USART1_BASE; 587 USART6 : TUSART_Registers absolute USART6_BASE; 588 ADC : TADC_Common_Registers absolute ADC_BASE; 589 ADC1 : TADC_Registers absolute ADC1_BASE; 590 SDIO : TSDIO_Registers absolute SDIO_BASE; 591 SPI1 : TSPI_Registers absolute SPI1_BASE; 592 SPI4 : TSPI_Registers absolute SPI4_BASE; 593 SYSCFG : TSYSCFG_Registers absolute SYSCFG_BASE; 594 EXTI : TEXTI_Registers absolute EXTI_BASE; 595 TIM9 : TTIM_Registers absolute TIM9_BASE; 596 TIM10 : TTIM_Registers absolute TIM10_BASE; 597 TIM11 : TTIM_Registers absolute TIM11_BASE; 598 SPI5 : TSPI_Registers absolute SPI5_BASE; 599 GPIOA : TGPIO_Registers absolute GPIOA_BASE; 600 GPIOB : TGPIO_Registers absolute GPIOB_BASE; 601 GPIOC : TGPIO_Registers absolute GPIOC_BASE; 602 GPIOD : TGPIO_Registers absolute GPIOD_BASE; 603 GPIOE : TGPIO_Registers absolute GPIOE_BASE; 604 GPIOH : TGPIO_Registers absolute GPIOH_BASE; 605 CRC : TCRC_Registers absolute CRC_BASE; 606 RCC : TRCC_Registers absolute RCC_BASE; 607 FLASH : TFLASH_Registers absolute FLASH_R_BASE; 608 DMA1 : TDMA_Registers absolute DMA1_BASE; 609 DMA1_Stream0 : TDMA_Stream_Registers absolute DMA1_Stream0_BASE; 610 DMA1_Stream1 : TDMA_Stream_Registers absolute DMA1_Stream1_BASE; 611 DMA1_Stream2 : TDMA_Stream_Registers absolute DMA1_Stream2_BASE; 612 DMA1_Stream3 : TDMA_Stream_Registers absolute DMA1_Stream3_BASE; 613 DMA1_Stream4 : TDMA_Stream_Registers absolute DMA1_Stream4_BASE; 614 DMA1_Stream5 : TDMA_Stream_Registers absolute DMA1_Stream5_BASE; 615 DMA1_Stream6 : TDMA_Stream_Registers absolute DMA1_Stream6_BASE; 616 DMA1_Stream7 : TDMA_Stream_Registers absolute DMA1_Stream7_BASE; 617 DMA2 : TDMA_Registers absolute DMA2_BASE; 618 DMA2_Stream0 : TDMA_Stream_Registers absolute DMA2_Stream0_BASE; 619 DMA2_Stream1 : TDMA_Stream_Registers absolute DMA2_Stream1_BASE; 620 DMA2_Stream2 : TDMA_Stream_Registers absolute DMA2_Stream2_BASE; 621 DMA2_Stream3 : TDMA_Stream_Registers absolute DMA2_Stream3_BASE; 622 DMA2_Stream4 : TDMA_Stream_Registers absolute DMA2_Stream4_BASE; 623 DMA2_Stream5 : TDMA_Stream_Registers absolute DMA2_Stream5_BASE; 624 DMA2_Stream6 : TDMA_Stream_Registers absolute DMA2_Stream6_BASE; 625 DMA2_Stream7 : TDMA_Stream_Registers absolute DMA2_Stream7_BASE; 626 DBGMCU : TDBGMCU_Registers absolute DBGMCU_BASE; 627 628implementation 629 630procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt'; 631procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt'; 632procedure BusFault_interrupt; external name 'BusFault_interrupt'; 633procedure UsageFault_interrupt; external name 'UsageFault_interrupt'; 634procedure SVCall_interrupt; external name 'SVCall_interrupt'; 635procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt'; 636procedure PendSV_interrupt; external name 'PendSV_interrupt'; 637procedure SysTick_interrupt; external name 'SysTick_interrupt'; 638procedure WWDG_interrupt; external name 'WWDG_interrupt'; 639procedure PVD_interrupt; external name 'PVD_interrupt'; 640procedure TAMP_STAMP_interrupt; external name 'TAMP_STAMP_interrupt'; 641procedure RTC_WKUP_interrupt; external name 'RTC_WKUP_interrupt'; 642procedure FLASH_interrupt; external name 'FLASH_interrupt'; 643procedure RCC_interrupt; external name 'RCC_interrupt'; 644procedure EXTI0_interrupt; external name 'EXTI0_interrupt'; 645procedure EXTI1_interrupt; external name 'EXTI1_interrupt'; 646procedure EXTI2_interrupt; external name 'EXTI2_interrupt'; 647procedure EXTI3_interrupt; external name 'EXTI3_interrupt'; 648procedure EXTI4_interrupt; external name 'EXTI4_interrupt'; 649procedure DMA1_Stream0_interrupt; external name 'DMA1_Stream0_interrupt'; 650procedure DMA1_Stream1_interrupt; external name 'DMA1_Stream1_interrupt'; 651procedure DMA1_Stream2_interrupt; external name 'DMA1_Stream2_interrupt'; 652procedure DMA1_Stream3_interrupt; external name 'DMA1_Stream3_interrupt'; 653procedure DMA1_Stream4_interrupt; external name 'DMA1_Stream4_interrupt'; 654procedure DMA1_Stream5_interrupt; external name 'DMA1_Stream5_interrupt'; 655procedure DMA1_Stream6_interrupt; external name 'DMA1_Stream6_interrupt'; 656procedure ADC_interrupt; external name 'ADC_interrupt'; 657procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt'; 658procedure TIM1_BRK_TIM9_interrupt; external name 'TIM1_BRK_TIM9_interrupt'; 659procedure TIM1_UP_TIM10_interrupt; external name 'TIM1_UP_TIM10_interrupt'; 660procedure TIM1_TRG_COM_TIM11_interrupt; external name 'TIM1_TRG_COM_TIM11_interrupt'; 661procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt'; 662procedure TIM2_interrupt; external name 'TIM2_interrupt'; 663procedure TIM3_interrupt; external name 'TIM3_interrupt'; 664procedure TIM4_interrupt; external name 'TIM4_interrupt'; 665procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt'; 666procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt'; 667procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt'; 668procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt'; 669procedure SPI1_interrupt; external name 'SPI1_interrupt'; 670procedure SPI2_interrupt; external name 'SPI2_interrupt'; 671procedure USART1_interrupt; external name 'USART1_interrupt'; 672procedure USART2_interrupt; external name 'USART2_interrupt'; 673procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt'; 674procedure RTC_Alarm_interrupt; external name 'RTC_Alarm_interrupt'; 675procedure OTG_FS_WKUP_interrupt; external name 'OTG_FS_WKUP_interrupt'; 676procedure DMA1_Stream7_interrupt; external name 'DMA1_Stream7_interrupt'; 677procedure SDIO_interrupt; external name 'SDIO_interrupt'; 678procedure TIM5_interrupt; external name 'TIM5_interrupt'; 679procedure SPI3_interrupt; external name 'SPI3_interrupt'; 680procedure DMA2_Stream0_interrupt; external name 'DMA2_Stream0_interrupt'; 681procedure DMA2_Stream1_interrupt; external name 'DMA2_Stream1_interrupt'; 682procedure DMA2_Stream2_interrupt; external name 'DMA2_Stream2_interrupt'; 683procedure DMA2_Stream3_interrupt; external name 'DMA2_Stream3_interrupt'; 684procedure DMA2_Stream4_interrupt; external name 'DMA2_Stream4_interrupt'; 685procedure OTG_FS_interrupt; external name 'OTG_FS_interrupt'; 686procedure DMA2_Stream5_interrupt; external name 'DMA2_Stream5_interrupt'; 687procedure DMA2_Stream6_interrupt; external name 'DMA2_Stream6_interrupt'; 688procedure DMA2_Stream7_interrupt; external name 'DMA2_Stream7_interrupt'; 689procedure USART6_interrupt; external name 'USART6_interrupt'; 690procedure I2C3_EV_interrupt; external name 'I2C3_EV_interrupt'; 691procedure I2C3_ER_interrupt; external name 'I2C3_ER_interrupt'; 692procedure FPU_interrupt; external name 'FPU_interrupt'; 693procedure SPI4_interrupt; external name 'SPI4_interrupt'; 694procedure SPI5_interrupt; external name 'SPI5_interrupt'; 695 696{$i cortexm4f_start.inc} 697 698procedure Vectors; assembler; nostackframe; 699label interrupt_vectors; 700asm 701 .section ".init.interrupt_vectors" 702 interrupt_vectors: 703 .long _stack_top 704 .long Startup 705 .long NonMaskableInt_interrupt 706 .long 0 707 .long MemoryManagement_interrupt 708 .long BusFault_interrupt 709 .long UsageFault_interrupt 710 .long 0 711 .long 0 712 .long 0 713 .long 0 714 .long SVCall_interrupt 715 .long DebugMonitor_interrupt 716 .long 0 717 .long PendSV_interrupt 718 .long SysTick_interrupt 719 .long WWDG_interrupt 720 .long PVD_interrupt 721 .long TAMP_STAMP_interrupt 722 .long RTC_WKUP_interrupt 723 .long FLASH_interrupt 724 .long RCC_interrupt 725 .long EXTI0_interrupt 726 .long EXTI1_interrupt 727 .long EXTI2_interrupt 728 .long EXTI3_interrupt 729 .long EXTI4_interrupt 730 .long DMA1_Stream0_interrupt 731 .long DMA1_Stream1_interrupt 732 .long DMA1_Stream2_interrupt 733 .long DMA1_Stream3_interrupt 734 .long DMA1_Stream4_interrupt 735 .long DMA1_Stream5_interrupt 736 .long DMA1_Stream6_interrupt 737 .long ADC_interrupt 738 .long 0 739 .long 0 740 .long 0 741 .long 0 742 .long EXTI9_5_interrupt 743 .long TIM1_BRK_TIM9_interrupt 744 .long TIM1_UP_TIM10_interrupt 745 .long TIM1_TRG_COM_TIM11_interrupt 746 .long TIM1_CC_interrupt 747 .long TIM2_interrupt 748 .long TIM3_interrupt 749 .long TIM4_interrupt 750 .long I2C1_EV_interrupt 751 .long I2C1_ER_interrupt 752 .long I2C2_EV_interrupt 753 .long I2C2_ER_interrupt 754 .long SPI1_interrupt 755 .long SPI2_interrupt 756 .long USART1_interrupt 757 .long USART2_interrupt 758 .long 0 759 .long EXTI15_10_interrupt 760 .long RTC_Alarm_interrupt 761 .long OTG_FS_WKUP_interrupt 762 .long 0 763 .long 0 764 .long 0 765 .long 0 766 .long DMA1_Stream7_interrupt 767 .long 0 768 .long SDIO_interrupt 769 .long TIM5_interrupt 770 .long SPI3_interrupt 771 .long 0 772 .long 0 773 .long 0 774 .long 0 775 .long DMA2_Stream0_interrupt 776 .long DMA2_Stream1_interrupt 777 .long DMA2_Stream2_interrupt 778 .long DMA2_Stream3_interrupt 779 .long DMA2_Stream4_interrupt 780 .long 0 781 .long 0 782 .long 0 783 .long 0 784 .long 0 785 .long 0 786 .long OTG_FS_interrupt 787 .long DMA2_Stream5_interrupt 788 .long DMA2_Stream6_interrupt 789 .long DMA2_Stream7_interrupt 790 .long USART6_interrupt 791 .long I2C3_EV_interrupt 792 .long I2C3_ER_interrupt 793 .long 0 794 .long 0 795 .long 0 796 .long 0 797 .long 0 798 .long 0 799 .long 0 800 .long FPU_interrupt 801 .long 0 802 .long 0 803 .long SPI4_interrupt 804 .long SPI5_interrupt 805 .set NonMaskableInt_interrupt, HaltProc 806 .set MemoryManagement_interrupt, HaltProc 807 .set BusFault_interrupt, HaltProc 808 .set UsageFault_interrupt, HaltProc 809 .set SVCall_interrupt, HaltProc 810 .set DebugMonitor_interrupt, HaltProc 811 .set PendSV_interrupt, HaltProc 812 .set SysTick_interrupt, HaltProc 813 .set WWDG_interrupt, HaltProc 814 .set PVD_interrupt, HaltProc 815 .set TAMP_STAMP_interrupt, HaltProc 816 .set RTC_WKUP_interrupt, HaltProc 817 .set FLASH_interrupt, HaltProc 818 .set RCC_interrupt, HaltProc 819 .set EXTI0_interrupt, HaltProc 820 .set EXTI1_interrupt, HaltProc 821 .set EXTI2_interrupt, HaltProc 822 .set EXTI3_interrupt, HaltProc 823 .set EXTI4_interrupt, HaltProc 824 .set DMA1_Stream0_interrupt, HaltProc 825 .set DMA1_Stream1_interrupt, HaltProc 826 .set DMA1_Stream2_interrupt, HaltProc 827 .set DMA1_Stream3_interrupt, HaltProc 828 .set DMA1_Stream4_interrupt, HaltProc 829 .set DMA1_Stream5_interrupt, HaltProc 830 .set DMA1_Stream6_interrupt, HaltProc 831 .set ADC_interrupt, HaltProc 832 .set EXTI9_5_interrupt, HaltProc 833 .set TIM1_BRK_TIM9_interrupt, HaltProc 834 .set TIM1_UP_TIM10_interrupt, HaltProc 835 .set TIM1_TRG_COM_TIM11_interrupt, HaltProc 836 .set TIM1_CC_interrupt, HaltProc 837 .set TIM2_interrupt, HaltProc 838 .set TIM3_interrupt, HaltProc 839 .set TIM4_interrupt, HaltProc 840 .set I2C1_EV_interrupt, HaltProc 841 .set I2C1_ER_interrupt, HaltProc 842 .set I2C2_EV_interrupt, HaltProc 843 .set I2C2_ER_interrupt, HaltProc 844 .set SPI1_interrupt, HaltProc 845 .set SPI2_interrupt, HaltProc 846 .set USART1_interrupt, HaltProc 847 .set USART2_interrupt, HaltProc 848 .set EXTI15_10_interrupt, HaltProc 849 .set RTC_Alarm_interrupt, HaltProc 850 .set OTG_FS_WKUP_interrupt, HaltProc 851 .set DMA1_Stream7_interrupt, HaltProc 852 .set SDIO_interrupt, HaltProc 853 .set TIM5_interrupt, HaltProc 854 .set SPI3_interrupt, HaltProc 855 .set DMA2_Stream0_interrupt, HaltProc 856 .set DMA2_Stream1_interrupt, HaltProc 857 .set DMA2_Stream2_interrupt, HaltProc 858 .set DMA2_Stream3_interrupt, HaltProc 859 .set DMA2_Stream4_interrupt, HaltProc 860 .set OTG_FS_interrupt, HaltProc 861 .set DMA2_Stream5_interrupt, HaltProc 862 .set DMA2_Stream6_interrupt, HaltProc 863 .set DMA2_Stream7_interrupt, HaltProc 864 .set USART6_interrupt, HaltProc 865 .set I2C3_EV_interrupt, HaltProc 866 .set I2C3_ER_interrupt, HaltProc 867 .set FPU_interrupt, HaltProc 868 .set SPI4_interrupt, HaltProc 869 .set SPI5_interrupt, HaltProc 870 .text 871end; 872end. 873